From e56bd5a599e1f0645157bc9f83799cb873b16137 Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 16:19:43 +0100 Subject: [PATCH 01/69] AhbLite3.py: assignment <= is deprecated --- AhbLite3.py | 70 ++++++++++++++++++++++++++--------------------------- 1 file changed, 35 insertions(+), 35 deletions(-) diff --git a/AhbLite3.py b/AhbLite3.py index 442a9f0..8271947 100644 --- a/AhbLite3.py +++ b/AhbLite3.py @@ -8,14 +8,14 @@ def AhbLite3MasterIdle(ahb): - ahb.HADDR <= 0 - ahb.HWRITE <= 0 - ahb.HSIZE <= 0 - ahb.HBURST <= 0 - ahb.HPROT <= 0 - ahb.HTRANS <= 0 - ahb.HMASTLOCK <= 0 - ahb.HWDATA <= 0 + ahb.HADDR.value = 0 + ahb.HWRITE.value = 0 + ahb.HSIZE.value = 0 + ahb.HBURST.value = 0 + ahb.HPROT.value = 0 + ahb.HTRANS.value = 0 + ahb.HMASTLOCK.value = 0 + ahb.HWDATA.value = 0 @@ -108,14 +108,14 @@ def __init__(self,ahb,transactor,clk,reset): @cocotb.coroutine def stim(self): ahb = self.ahb - ahb.HADDR <= 0 - ahb.HWRITE <= 0 - ahb.HSIZE <= 0 - ahb.HBURST <= 0 - ahb.HPROT <= 0 - ahb.HTRANS <= 0 - ahb.HMASTLOCK <= 0 - ahb.HWDATA <= 0 + ahb.HADDR.value = 0 + ahb.HWRITE.value = 0 + ahb.HSIZE.value = 0 + ahb.HBURST.value = 0 + ahb.HPROT.value = 0 + ahb.HTRANS.value = 0 + ahb.HMASTLOCK.value = 0 + ahb.HWDATA.value = 0 HWDATAbuffer = 0 while True: for trans in self.transactor.getTransactions(): @@ -123,14 +123,14 @@ def stim(self): while int(self.ahb.HREADY) == 0: yield RisingEdge(self.clk) - ahb.HADDR <= trans.HADDR - ahb.HWRITE <= trans.HWRITE - ahb.HSIZE <= trans.HSIZE - ahb.HBURST <= trans.HBURST - ahb.HPROT <= trans.HPROT - ahb.HTRANS <= trans.HTRANS - ahb.HMASTLOCK <= trans.HMASTLOCK - ahb.HWDATA <= HWDATAbuffer + ahb.HADDR.value = trans.HADDR + ahb.HWRITE.value = trans.HWRITE + ahb.HSIZE.value = trans.HSIZE + ahb.HBURST.value = trans.HBURST + ahb.HPROT.value = trans.HPROT + ahb.HTRANS.value = trans.HTRANS + ahb.HMASTLOCK.value = trans.HMASTLOCK + ahb.HWDATA.value = HWDATAbuffer HWDATAbuffer = trans.HWDATA class AhbLite3Terminaison: @@ -145,8 +145,8 @@ def __init__(self,ahb,clk,reset): @cocotb.coroutine def stim(self): randomizer = BoolRandomizer() - self.ahb.HREADY <= 1 - self.ahb.HSEL <= 1 + self.ahb.HREADY.value = 1 + self.ahb.HSEL.value = 1 while True: yield RisingEdge(self.clk) self.randomHREADY = randomizer.get() @@ -159,7 +159,7 @@ def combEvent(self): self.doComb() def doComb(self): - self.ahb.HREADY <= (self.randomHREADY and (int(self.ahb.HREADYOUT) == 1)) + self.ahb.HREADY.value = (self.randomHREADY and (int(self.ahb.HREADYOUT) == 1)) class AhbLite3MasterReadChecker: @@ -210,7 +210,7 @@ def __init__(self,ahb,base,size,clk,reset): @cocotb.coroutine def stimReady(self): randomizer = BoolRandomizer() - self.ahb.HREADYOUT <= 1 + self.ahb.HREADYOUT.value = 1 busy = False while True: yield RisingEdge(self.clk) @@ -222,16 +222,16 @@ def stimReady(self): raise TestFailure("HREADYOUT == 0 but HREADY == 1 ??? " + self.ahb.HREADY._name) busy = busyNew if (busy): - self.ahb.HREADYOUT <= randomizer.get() # make some random delay for NONSEQ and SEQ requests + self.ahb.HREADYOUT.value = randomizer.get() # make some random delay for NONSEQ and SEQ requests else: - self.ahb.HREADYOUT <= 1 # IDLE and BUSY require 0 WS + self.ahb.HREADYOUT.value = 1 # IDLE and BUSY require 0 WS @cocotb.coroutine def stim(self): ahb = self.ahb - ahb.HREADYOUT <= 1 - ahb.HRESP <= 0 - ahb.HRDATA <= 0 + ahb.HREADYOUT.value = 1 + ahb.HRESP.value = 0 + ahb.HRDATA.value = 0 valid = 0 while True: yield RisingEdge(self.clk) @@ -252,7 +252,7 @@ def stim(self): address = int(ahb.HADDR) addressOffset = address % (len(ahb.HWDATA)//8) - ahb.HRDATA <= 0 + ahb.HRDATA.value = 0 if valid == 1: if trans >= 2: if write == 0: @@ -261,4 +261,4 @@ def stim(self): data |= self.ram[address-self.base + idx] << (8*(addressOffset + idx)) # print("read %x with %x" % (address + idx, self.ram[address-self.base + idx])) # print(str(data)) - ahb.HRDATA <= int(data) + ahb.HRDATA.value = int(data) From bf4b5c2334a477c4182a99ad96ef357e89defd97 Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 16:20:52 +0100 Subject: [PATCH 02/69] Apb3.py: assignment <= is deprecated --- Apb3.py | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/Apb3.py b/Apb3.py index 9fe0efb..49fa31e 100644 --- a/Apb3.py +++ b/Apb3.py @@ -20,7 +20,7 @@ def __init__(self, dut, name, clk = None): self.PRDATA = dut.__getattr__(name + "_PRDATA") def idle(self): - self.PSEL <= 0 + self.PSEL.value = 0 @coroutine def delay(self, cycle): @@ -29,16 +29,16 @@ def delay(self, cycle): @coroutine def write(self, address, data, sel = 1): - self.PADDR <= address - self.PSEL <= sel - self.PENABLE <= False - self.PWRITE <= True - self.PWDATA <= data + self.PADDR.value = address + self.PSEL.value = sel + self.PENABLE.value = False + self.PWRITE.value = True + self.PWDATA.value = data yield RisingEdge(self.clk) - self.PENABLE <= True + self.PENABLE.value = True yield waitClockedCond(self.clk, lambda : self.PREADY == True) randSignal(self.PADDR) - self.PSEL <= 0 + self.PSEL.value = 0 randSignal(self.PENABLE) randSignal(self.PWRITE) randSignal(self.PWDATA) @@ -51,16 +51,16 @@ def writeMasked(self, address, data, mask, sel = 1): @coroutine def read(self, address, sel=1): - self.PADDR <= address - self.PSEL <= sel - self.PENABLE <= False - self.PWRITE <= False + self.PADDR.value = address + self.PSEL.value = sel + self.PENABLE.value = False + self.PWRITE.value = False randSignal(self.PWDATA) yield RisingEdge(self.clk) - self.PENABLE <= True + self.PENABLE.value = True yield waitClockedCond(self.clk, lambda: self.PREADY == True) randSignal(self.PADDR) - self.PSEL <= 0 + self.PSEL.value = 0 randSignal(self.PENABLE) randSignal(self.PWRITE) raise ReturnValue(int(self.PRDATA)) From e62262897e00306e2be33754032b943fcda9275c Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 16:23:33 +0100 Subject: [PATCH 03/69] Axi4.py: assignment <= is deprecated --- Axi4.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Axi4.py b/Axi4.py index cfc21d6..401f6d3 100644 --- a/Axi4.py +++ b/Axi4.py @@ -74,8 +74,8 @@ def __init__(self,name,parent,axi,addressWidth,clk,reset): StreamDriverMaster(axi.w, self.genWriteData, clk, reset) StreamMonitor(axi.r, self.onReadRsp, clk, reset) StreamMonitor(axi.b, self.onWriteRsp, clk, reset) - axi.w.payload.last <= 0 - axi.r.payload.last <= 0 + axi.w.payload.last.value = 0 + axi.r.payload.last.value = 0 def freeReservatedAddresses(self,uut,ref,equal): self.reservedAddresses.pop(ref,None) From 94f7f62e4a5397e70ab8208018d3ba678a35457e Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 16:23:36 +0100 Subject: [PATCH 04/69] ClockDomain.py: assignment <= is deprecated --- ClockDomain.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/ClockDomain.py b/ClockDomain.py index 39bf48b..64068ef 100644 --- a/ClockDomain.py +++ b/ClockDomain.py @@ -50,12 +50,12 @@ def start(self): cocotb.fork(self._waitEndReset()) if self.reset: - self.reset <= self.typeReset + self.reset.value = self.typeReset yield Timer(self.halfPeriod * 5) if self.reset: - self.reset <= int(1 if self.typeReset == RESET_ACTIVE_LEVEL.LOW else 0) + self.reset.value = int(1 if self.typeReset == RESET_ACTIVE_LEVEL.LOW else 0) ########################################################################## @@ -70,9 +70,9 @@ def stop(self): @cocotb.coroutine def _clkGen(self): while True: - self.clk <= 0 + self.clk.value = 0 yield Timer(self.halfPeriod) - self.clk <= 1 + self.clk.value = 1 yield Timer(self.halfPeriod) From be01610e0e6f6a378374cc10ab2f031e356fee25 Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 16:24:04 +0100 Subject: [PATCH 05/69] Spi.py: assignment <= is deprecated --- Spi.py | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/Spi.py b/Spi.py index 7b1d7e3..d991cb0 100644 --- a/Spi.py +++ b/Spi.py @@ -40,22 +40,22 @@ def __init__(self, spi): self.dataWidth = 8 def init(self, cpol, cpha, baudrate, dataWidth = 8): - self.spi.ss <= True + self.spi.ss.value = True self.cpol = cpol self.cpha = cpha self.baudPeriode = baudrate self.dataWidth = dataWidth - self.spi.sclk <= cpol + self.spi.sclk.value = cpol @coroutine def enable(self): - self.spi.ss <= False + self.spi.ss.value = False yield Timer(self.baudPeriode) @coroutine def disable(self): yield Timer(self.baudPeriode) - self.spi.ss <= True + self.spi.ss.value = True yield Timer(self.baudPeriode) @coroutine @@ -63,19 +63,19 @@ def exchange(self, masterData): buffer = "" if not self.cpha: for i in range(self.dataWidth): - self.spi.mosi <= testBit(masterData, self.dataWidth - 1 - i) + self.spi.mosi.value = testBit(masterData, self.dataWidth - 1 - i) yield Timer(self.baudPeriode >> 1) buffer = buffer + str(self.spi.miso.write) if bool(self.spi.miso.writeEnable) else "x" - self.spi.sclk <= (not self.cpol) + self.spi.sclk.value = (not self.cpol) yield Timer(self.baudPeriode >> 1) - self.spi.sclk <= (self.cpol) + self.spi.sclk.value = (self.cpol) else: for i in range(self.dataWidth): - self.spi.mosi <= testBit(masterData, self.dataWidth -1 - i) - self.spi.sclk <= (not self.cpol) + self.spi.mosi.value = testBit(masterData, self.dataWidth -1 - i) + self.spi.sclk.value = (not self.cpol) yield Timer(self.baudPeriode >> 1) buffer = buffer + str(self.spi.miso.write) if bool(self.spi.miso.writeEnable) else "x" - self.spi.sclk <= (self.cpol) + self.spi.sclk.value = (self.cpol) yield Timer(self.baudPeriode >> 1) raise ReturnValue(buffer) From 16fc94399e463ee8a0843ebe53e71808d403ed66 Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 16:24:57 +0100 Subject: [PATCH 06/69] Stream.py: assignment <= is deprecated --- Stream.py | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/Stream.py b/Stream.py index 400489e..d39501e 100644 --- a/Stream.py +++ b/Stream.py @@ -94,11 +94,11 @@ def __init__(self,stream,transactor,clk,reset): @cocotb.coroutine def stim(self): stream = self.stream - stream.valid <= 0 + stream.valid.value = 0 while True: yield RisingEdge(self.clk) if int(stream.valid) == 1 and int(stream.ready) == 1: - stream.valid <= 0 + stream.valid.value = 0 for i in range(nextDelay): yield RisingEdge(self.clk) @@ -112,12 +112,12 @@ def stim(self): nextDelay = trans.nextDelay else: nextDelay = 0 - stream.valid <= 1 + stream.valid.value = 1 for name in stream.payload.nameToElement: if hasattr(trans,name) == False: raise Exception("Missing element in bundle :" + name) - e = stream.payload.nameToElement[name] <= getattr(trans,name) + e = stream.payload.nameToElement[name].value = getattr(trans,name) @@ -132,10 +132,10 @@ def __init__(self,stream,clk,reset): @cocotb.coroutine def stim(self): stream = self.stream - stream.ready <= 1 + stream.ready.value = 1 while True: yield RisingEdge(self.clk) - stream.ready <= self.randomizer.get() + stream.ready.value = self.randomizer.get() def TransactionFromBundle(bundle): From bfb831d6adcc29e4e91a49f712f0bd68bed90ec2 Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 16:26:28 +0100 Subject: [PATCH 07/69] misc.py: assignment <= is deprecated --- misc.py | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/misc.py b/misc.py index 939e0ab..41a0a17 100644 --- a/misc.py +++ b/misc.py @@ -30,10 +30,10 @@ def randBits(width): return random.getrandbits(width) def randSignal(that): - that <= random.getrandbits(len(that)) + that.value = random.getrandbits(len(that)) def randBoolSignal(that,prob): - that <= (random.random() < prob) + that.value = (random.random() < prob) @coroutine @@ -86,15 +86,15 @@ def sint(signal): @cocotb.coroutine def ClockDomainAsyncReset(clk,reset,period = 1000): if reset: - reset <= 1 - clk <= 0 + reset.value = 1 + clk.value = 0 yield Timer(period) if reset: - reset <= 0 + reset.value = 0 while True: - clk <= 0 + clk.value = 0 yield Timer(period/2) - clk <= 1 + clk.value = 1 yield Timer(period/2) @cocotb.coroutine @@ -154,15 +154,15 @@ def StreamRandomizer(streamName, onNew,handle, dut, clk): ready = getattr(dut, streamName + "_ready") payloads = [a for a in dut if a._name.startswith(streamName + "_payload")] - valid <= 0 + valid.value = 0 while True: yield RisingEdge(clk) if int(ready) == 1: - valid <= 0 + valid.value = 0 if int(valid) == 0 or int(ready) == 1: if validRandomizer.get(): - valid <= 1 + valid.value = 1 for e in payloads: randSignal(e) yield Timer(1) @@ -181,11 +181,11 @@ def FlowRandomizer(streamName, onNew,handle, dut, clk): valid = getattr(dut, streamName + "_valid") payloads = [a for a in dut if a._name.startswith(streamName + "_payload")] - valid <= 0 + valid.value = 0 while True: yield RisingEdge(clk) if validRandomizer.get(): - valid <= 1 + valid.value = 1 for e in payloads: randSignal(e) yield Timer(1) @@ -198,7 +198,7 @@ def FlowRandomizer(streamName, onNew,handle, dut, clk): if onNew: onNew(payload,handle) else: - valid <= 0 + valid.value = 0 @cocotb.coroutine def StreamReader(streamName, onTransaction, handle, dut, clk): @@ -207,10 +207,10 @@ def StreamReader(streamName, onTransaction, handle, dut, clk): ready = getattr(dut, streamName + "_ready") payloads = [a for a in dut if a._name.startswith(streamName + "_payload")] - ready <= 0 + ready.value = 0 while True: yield RisingEdge(clk) - ready <= validRandomizer.get() + ready.value = validRandomizer.get() if int(valid) == 1 and int(ready) == 1: if len(payloads) == 1 and payloads[0]._name == streamName + "_payload": payload = int(payloads[0]) From d28bc4339de8dd3bd61a937a6068fe401b2d1d14 Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 16:29:22 +0100 Subject: [PATCH 08/69] AhbLite3.py: import local ref change --- AhbLite3.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/AhbLite3.py b/AhbLite3.py index 8271947..0d2b31c 100644 --- a/AhbLite3.py +++ b/AhbLite3.py @@ -4,7 +4,7 @@ from cocotb.result import TestFailure from cocotb.triggers import RisingEdge, Edge -from cocotblib.misc import log2Up, BoolRandomizer, assertEquals +from .misc import log2Up, BoolRandomizer, assertEquals def AhbLite3MasterIdle(ahb): From f13c70a13aa8b8b553022b3cdbda17dbe187de39 Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 16:32:09 +0100 Subject: [PATCH 09/69] Apb3.py: import local ref change --- Apb3.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Apb3.py b/Apb3.py index 49fa31e..dfa2780 100644 --- a/Apb3.py +++ b/Apb3.py @@ -5,7 +5,7 @@ from cocotb.result import TestFailure, ReturnValue from cocotb.triggers import RisingEdge, Edge -from cocotblib.misc import log2Up, BoolRandomizer, assertEquals, waitClockedCond, randSignal +from .misc import log2Up, BoolRandomizer, assertEquals, waitClockedCond, randSignal class Apb3: From 72cf46691271d7b79f1fbb316a66656081da970c Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 16:32:23 +0100 Subject: [PATCH 10/69] Axi4.py: import local ref change --- Axi4.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/Axi4.py b/Axi4.py index 401f6d3..a02709e 100644 --- a/Axi4.py +++ b/Axi4.py @@ -1,11 +1,11 @@ import random from queue import Queue -from cocotblib.Phase import PHASE_SIM, Infrastructure -from cocotblib.Scorboard import ScorboardOutOfOrder -from cocotblib.misc import BoolRandomizer, log2Up, randBits +from .Phase import PHASE_SIM, Infrastructure +from .Scorboard import ScorboardOutOfOrder +from .misc import BoolRandomizer, log2Up, randBits -from cocotblib.Stream import Stream, Transaction, StreamDriverSlave, StreamDriverMaster, StreamMonitor +from .Stream import Stream, Transaction, StreamDriverSlave, StreamDriverMaster, StreamMonitor class Axi4: From 17baf5ed1d674504fbd44c0dfdbfe54646e38ac3 Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 16:34:50 +0100 Subject: [PATCH 11/69] Flow.py: import local ref change --- Flow.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Flow.py b/Flow.py index 8514594..911fa71 100644 --- a/Flow.py +++ b/Flow.py @@ -1,6 +1,6 @@ import cocotb from cocotb.triggers import RisingEdge, Event -from cocotblib.misc import Bundle +from .misc import Bundle ############################################################################### From 450f8555e91b31d687498746e300c77f4f65c436 Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 16:37:41 +0100 Subject: [PATCH 12/69] Scorboard.py: import local ref change --- Scorboard.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Scorboard.py b/Scorboard.py index 5841904..37c2325 100644 --- a/Scorboard.py +++ b/Scorboard.py @@ -3,7 +3,7 @@ import cocotb from cocotb.result import TestFailure -from cocotblib.Phase import Infrastructure, PHASE_CHECK_SCORBOARDS +from .Phase import Infrastructure, PHASE_CHECK_SCORBOARDS class ScorboardInOrder(Infrastructure): From 2afed892a14466583f061dcff76e105664911df0 Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 16:39:18 +0100 Subject: [PATCH 13/69] Spi.py: import local ref change --- Spi.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Spi.py b/Spi.py index d991cb0..68dfed0 100644 --- a/Spi.py +++ b/Spi.py @@ -5,8 +5,8 @@ from cocotb.result import TestFailure, ReturnValue from cocotb.triggers import RisingEdge, Edge, Timer -from cocotblib.TriState import TriStateOutput -from cocotblib.misc import log2Up, BoolRandomizer, assertEquals, testBit +from .TriState import TriStateOutput +from .misc import log2Up, BoolRandomizer, assertEquals, testBit class SpiMaster: From 1373392c34016807207cf045496e2189f7c57a4f Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 16:41:42 +0100 Subject: [PATCH 14/69] Stream.py: import local ref change --- Stream.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Stream.py b/Stream.py index d39501e..eff1177 100644 --- a/Stream.py +++ b/Stream.py @@ -3,10 +3,10 @@ import types from cocotb.result import TestFailure from cocotb.triggers import RisingEdge, Timer, Event -from cocotblib.Phase import Infrastructure, PHASE_WAIT_TASKS_END -from cocotblib.Scorboard import ScorboardInOrder +from .Phase import Infrastructure, PHASE_WAIT_TASKS_END +from .Scorboard import ScorboardInOrder -from cocotblib.misc import Bundle, BoolRandomizer +from .misc import Bundle, BoolRandomizer class Stream: From 38393a7c9903c266a2f47c15372f576aa1da562f Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 16:43:36 +0100 Subject: [PATCH 15/69] AhbLite3.py: cocotb.fork is deprecated --- AhbLite3.py | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/AhbLite3.py b/AhbLite3.py index 0d2b31c..7e84c32 100644 --- a/AhbLite3.py +++ b/AhbLite3.py @@ -103,7 +103,7 @@ def __init__(self,ahb,transactor,clk,reset): self.clk = clk self.reset = reset self.transactor = transactor - cocotb.fork(self.stim()) + cocotb.start_soon(self.stim()) @cocotb.coroutine def stim(self): @@ -139,8 +139,8 @@ def __init__(self,ahb,clk,reset): self.clk = clk self.reset = reset self.randomHREADY = True - cocotb.fork(self.stim()) - cocotb.fork(self.combEvent()) + cocotb.start_soon(self.stim()) + cocotb.start_soon(self.combEvent()) @cocotb.coroutine def stim(self): @@ -169,7 +169,7 @@ def __init__(self,ahb,buffer,clk,reset): self.reset = reset self.buffer = buffer self.counter = 0 - cocotb.fork(self.stim()) + cocotb.start_soon(self.stim()) @cocotb.coroutine def stim(self): @@ -204,8 +204,8 @@ def __init__(self,ahb,base,size,clk,reset): self.size = size self.ram = bytearray(b'\x00' * size) - cocotb.fork(self.stim()) - cocotb.fork(self.stimReady()) + cocotb.start_soon(self.stim()) + cocotb.start_soon(self.stimReady()) @cocotb.coroutine def stimReady(self): From 2dae0197265959f8093abffe87f9d77b7e290ddb Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 16:45:48 +0100 Subject: [PATCH 16/69] ClockDomain.py: cocotb.fork is deprecated --- ClockDomain.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/ClockDomain.py b/ClockDomain.py index 64068ef..a71c19f 100644 --- a/ClockDomain.py +++ b/ClockDomain.py @@ -17,7 +17,7 @@ class RESET_ACTIVE_LEVEL: # # # Create a clock with a reset active high # clockDomain = ClockDomain(dut.clk, 400, dut.reset, RESET_ACTIVE_LEVEL.HIGH) -# cocobt.fork( clockDomain.start() ) +# cocotb.start_soon( clockDomain.start() ) # class ClockDomain: @@ -45,9 +45,9 @@ def __init__(self, clk, halfPeriod, reset=None, resetActiveLevel=RESET_ACTIVE_LE @cocotb.coroutine def start(self): - self.fork_gen = cocotb.fork(self._clkGen()) + self.fork_gen = cocotb.start_soon(self._clkGen()) if self.reset != None : - cocotb.fork(self._waitEndReset()) + cocotb.start_soon(self._waitEndReset()) if self.reset: self.reset.value = self.typeReset From c74e92f9f15d103f44ac501a945e410b52e3e9a0 Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 16:47:00 +0100 Subject: [PATCH 17/69] Flow.py: cocotb.fork is deprecated --- Flow.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Flow.py b/Flow.py index 911fa71..8afd8fa 100644 --- a/Flow.py +++ b/Flow.py @@ -26,7 +26,7 @@ def __init__(self, dut, name): #========================================================================== def startMonitoringValid(self, clk): self.clk = clk - self.fork_valid = cocotb.fork(self.monitor_valid()) + self.fork_valid = cocotb.start_soon(self.monitor_valid()) #========================================================================== From 4a2ced2cd85c8b9247f6f03ebed91ddca63f561e Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 16:47:43 +0100 Subject: [PATCH 18/69] Stream.py: cocotb.fork is deprecated --- Stream.py | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/Stream.py b/Stream.py index eff1177..1cf6d3f 100644 --- a/Stream.py +++ b/Stream.py @@ -20,11 +20,11 @@ def __init__(self, dut, name): def startMonitoringReady(self, clk): self.clk = clk - self.fork_ready = cocotb.fork(self.monitor_ready()) + self.fork_ready = cocotb.start_soon(self.monitor_ready()) def startMonitoringValid(self, clk): self.clk = clk - self.fork_valid = cocotb.fork(self.monitor_valid()) + self.fork_valid = cocotb.start_soon(self.monitor_valid()) def stopMonitoring(self): self.fork_ready.kill() @@ -89,7 +89,7 @@ def __init__(self,stream,transactor,clk,reset): self.reset = reset self.transactor = transactor - cocotb.fork(self.stim()) + cocotb.start_soon(self.stim()) @cocotb.coroutine def stim(self): @@ -127,7 +127,7 @@ def __init__(self,stream,clk,reset): self.clk = clk self.reset = reset self.randomizer = BoolRandomizer() - cocotb.fork(self.stim()) + cocotb.start_soon(self.stim()) @cocotb.coroutine def stim(self): @@ -151,7 +151,7 @@ def __init__(self,stream,callback,clk,reset): self.callback = callback self.clk = clk self.reset = reset - cocotb.fork(self.stim()) + cocotb.start_soon(self.stim()) @cocotb.coroutine def stim(self): From f7248f0b74c5cd6ff565d7ae42db5083e5933c04 Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 16:48:44 +0100 Subject: [PATCH 19/69] AhbLite3.py: consistently use @coroutine --- AhbLite3.py | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/AhbLite3.py b/AhbLite3.py index 7e84c32..9f045bb 100644 --- a/AhbLite3.py +++ b/AhbLite3.py @@ -3,6 +3,7 @@ import cocotb from cocotb.result import TestFailure from cocotb.triggers import RisingEdge, Edge +from cocotb.decorators import coroutine from .misc import log2Up, BoolRandomizer, assertEquals @@ -105,7 +106,7 @@ def __init__(self,ahb,transactor,clk,reset): self.transactor = transactor cocotb.start_soon(self.stim()) - @cocotb.coroutine + @coroutine def stim(self): ahb = self.ahb ahb.HADDR.value = 0 @@ -142,7 +143,7 @@ def __init__(self,ahb,clk,reset): cocotb.start_soon(self.stim()) cocotb.start_soon(self.combEvent()) - @cocotb.coroutine + @coroutine def stim(self): randomizer = BoolRandomizer() self.ahb.HREADY.value = 1 @@ -152,7 +153,7 @@ def stim(self): self.randomHREADY = randomizer.get() self.doComb() - @cocotb.coroutine + @coroutine def combEvent(self): while True: yield Edge(self.ahb.HREADYOUT) @@ -171,7 +172,7 @@ def __init__(self,ahb,buffer,clk,reset): self.counter = 0 cocotb.start_soon(self.stim()) - @cocotb.coroutine + @coroutine def stim(self): ahb = self.ahb readIncoming = False @@ -207,7 +208,7 @@ def __init__(self,ahb,base,size,clk,reset): cocotb.start_soon(self.stim()) cocotb.start_soon(self.stimReady()) - @cocotb.coroutine + @coroutine def stimReady(self): randomizer = BoolRandomizer() self.ahb.HREADYOUT.value = 1 @@ -226,7 +227,7 @@ def stimReady(self): else: self.ahb.HREADYOUT.value = 1 # IDLE and BUSY require 0 WS - @cocotb.coroutine + @coroutine def stim(self): ahb = self.ahb ahb.HREADYOUT.value = 1 From 6ea46102899e08c7617985eb1cd4e271f221cfcd Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 16:49:57 +0100 Subject: [PATCH 20/69] Apb3.py: consistently use @coroutine --- Apb3.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Apb3.py b/Apb3.py index dfa2780..4df046f 100644 --- a/Apb3.py +++ b/Apb3.py @@ -1,9 +1,9 @@ import random import cocotb -from cocotb.decorators import coroutine from cocotb.result import TestFailure, ReturnValue from cocotb.triggers import RisingEdge, Edge +from cocotb.decorators import coroutine from .misc import log2Up, BoolRandomizer, assertEquals, waitClockedCond, randSignal From 9800fd5bc6972604d98e57782d32c22e230dcaca Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 16:52:01 +0100 Subject: [PATCH 21/69] ClockDomain.py: consistently use @coroutine --- ClockDomain.py | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/ClockDomain.py b/ClockDomain.py index a71c19f..0559082 100644 --- a/ClockDomain.py +++ b/ClockDomain.py @@ -1,5 +1,6 @@ import cocotb from cocotb.triggers import Timer, RisingEdge, Event +from cocotb.decorators import coroutine ############################################################################### @@ -42,7 +43,7 @@ def __init__(self, clk, halfPeriod, reset=None, resetActiveLevel=RESET_ACTIVE_LE ########################################################################## # Generate the clock signals - @cocotb.coroutine + @coroutine def start(self): self.fork_gen = cocotb.start_soon(self._clkGen()) @@ -67,7 +68,7 @@ def stop(self): ########################################################################## # Generate the clk - @cocotb.coroutine + @coroutine def _clkGen(self): while True: self.clk.value = 0 @@ -78,7 +79,7 @@ def _clkGen(self): ########################################################################## # Wait the end of the reset - @cocotb.coroutine + @coroutine def _waitEndReset(self): while True: yield RisingEdge(self.clk) From f6bd5e9ff337ce85ba3aed784c39ccbf3949f7a4 Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 16:53:05 +0100 Subject: [PATCH 22/69] Flow.py: consistently use @coroutine --- Flow.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Flow.py b/Flow.py index 8afd8fa..4b5db9f 100644 --- a/Flow.py +++ b/Flow.py @@ -1,5 +1,7 @@ import cocotb from cocotb.triggers import RisingEdge, Event +from cocotb.decorators import coroutine + from .misc import Bundle @@ -39,7 +41,7 @@ def stopMonitoring(self): #========================================================================== # Monitor the valid signal #========================================================================== - @cocotb.coroutine + @coroutine def monitor_valid(self): while True: yield RisingEdge(self.clk) From 102db6ff063d00e7f89622730654693ae25c7bc5 Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 16:54:44 +0100 Subject: [PATCH 23/69] Phase.py: consistently use @coroutine --- Phase.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/Phase.py b/Phase.py index f53a622..db6da68 100644 --- a/Phase.py +++ b/Phase.py @@ -1,6 +1,7 @@ import cocotb from cocotb.result import TestFailure, TestError from cocotb.triggers import Timer +from cocotb.decorators import coroutine PHASE_NULL = 0 PHASE_SIM = 100 @@ -62,7 +63,7 @@ def __init__(self): def setWaitTasksEndTime(self,value): self.waitTasksEndTime = value - @cocotb.coroutine + @coroutine def waitChild(self): while True: if self.canPhaseProgress(self.phase): @@ -79,7 +80,7 @@ def switchPhase(self,phase): for infra in self.children: infra.startPhase(self.phase) - @cocotb.coroutine + @coroutine def run(self): self.switchPhase(PHASE_SIM) yield self.waitChild() From 13927f9c44da8dd8cab2166e61faa24e839854b4 Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 16:56:35 +0100 Subject: [PATCH 24/69] Spi.py: consistently use @coroutine --- Spi.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Spi.py b/Spi.py index 68dfed0..09ff091 100644 --- a/Spi.py +++ b/Spi.py @@ -1,9 +1,9 @@ import random import cocotb -from cocotb.decorators import coroutine from cocotb.result import TestFailure, ReturnValue from cocotb.triggers import RisingEdge, Edge, Timer +from cocotb.decorators import coroutine from .TriState import TriStateOutput from .misc import log2Up, BoolRandomizer, assertEquals, testBit From 72972653cb55748f2f6b80e4ef88971219b52519 Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 16:59:27 +0100 Subject: [PATCH 25/69] Stream.py: consistently use @coroutine --- Stream.py | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/Stream.py b/Stream.py index 1cf6d3f..ec7aad5 100644 --- a/Stream.py +++ b/Stream.py @@ -1,14 +1,15 @@ -import cocotb import types + +import cocotb from cocotb.result import TestFailure from cocotb.triggers import RisingEdge, Timer, Event +from cocotb.decorators import coroutine + from .Phase import Infrastructure, PHASE_WAIT_TASKS_END from .Scorboard import ScorboardInOrder - from .misc import Bundle, BoolRandomizer - class Stream: def __init__(self, dut, name): self.valid = dut.__getattr__(name + "_valid") @@ -30,14 +31,14 @@ def stopMonitoring(self): self.fork_ready.kill() self.fork_valid.kill() - @cocotb.coroutine + @coroutine def monitor_ready(self): while True: yield RisingEdge(self.clk) if int(self.ready) == 1: self.event_ready.set( self.payload ) - @cocotb.coroutine + @coroutine def monitor_valid(self): while True: yield RisingEdge(self.clk) @@ -91,7 +92,7 @@ def __init__(self,stream,transactor,clk,reset): cocotb.start_soon(self.stim()) - @cocotb.coroutine + @coroutine def stim(self): stream = self.stream stream.valid.value = 0 @@ -129,7 +130,7 @@ def __init__(self,stream,clk,reset): self.randomizer = BoolRandomizer() cocotb.start_soon(self.stim()) - @cocotb.coroutine + @coroutine def stim(self): stream = self.stream stream.ready.value = 1 @@ -153,7 +154,7 @@ def __init__(self,stream,callback,clk,reset): self.reset = reset cocotb.start_soon(self.stim()) - @cocotb.coroutine + @coroutine def stim(self): stream = self.stream while True: From 25ddfc3e7a614318f631da0849f76e9dd05f8325 Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 17:00:24 +0100 Subject: [PATCH 26/69] misc.py: consistently use @coroutine --- misc.py | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/misc.py b/misc.py index 41a0a17..eabc40d 100644 --- a/misc.py +++ b/misc.py @@ -2,10 +2,9 @@ import cocotb from cocotb.binary import BinaryValue -from cocotb.decorators import coroutine from cocotb.result import TestFailure from cocotb.triggers import Timer, RisingEdge - +from cocotb.decorators import coroutine def cocotbXHack(): if hasattr(BinaryValue,"_resolve_to_0"): @@ -83,7 +82,7 @@ def sint(signal): return signal.value.signed_integer -@cocotb.coroutine +@coroutine def ClockDomainAsyncReset(clk,reset,period = 1000): if reset: reset.value = 1 @@ -97,14 +96,14 @@ def ClockDomainAsyncReset(clk,reset,period = 1000): clk.value = 1 yield Timer(period/2) -@cocotb.coroutine +@coroutine def SimulationTimeout(duration): yield Timer(duration) raise TestFailure("Simulation timeout") import time -@cocotb.coroutine +@coroutine def simulationSpeedPrinter(clk): counter = 0 lastTime = time.time() @@ -147,7 +146,7 @@ def get(self): MyObject = type('MyObject', (object,), {}) -@cocotb.coroutine +@coroutine def StreamRandomizer(streamName, onNew,handle, dut, clk): validRandomizer = BoolRandomizer() valid = getattr(dut, streamName + "_valid") @@ -175,7 +174,7 @@ def StreamRandomizer(streamName, onNew,handle, dut, clk): if onNew: onNew(payload,handle) -@cocotb.coroutine +@coroutine def FlowRandomizer(streamName, onNew,handle, dut, clk): validRandomizer = BoolRandomizer() valid = getattr(dut, streamName + "_valid") @@ -200,7 +199,7 @@ def FlowRandomizer(streamName, onNew,handle, dut, clk): else: valid.value = 0 -@cocotb.coroutine +@coroutine def StreamReader(streamName, onTransaction, handle, dut, clk): validRandomizer = BoolRandomizer() valid = getattr(dut, streamName + "_valid") From 0a283f0b3bc3444c246148ac907885cfab5ff920 Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 17:02:19 +0100 Subject: [PATCH 27/69] AhbLite3.py: dut.log is deprecated --- AhbLite3.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/AhbLite3.py b/AhbLite3.py index 9f045bb..279afff 100644 --- a/AhbLite3.py +++ b/AhbLite3.py @@ -188,7 +188,7 @@ def stim(self): assertEquals((int(ahb.HRDATA) >> (i*8)) & 0xFF,(bufferData >> (i*8)) & 0xFF,"AHB master read checker faild %x " %(int(ahb.HADDR)) ) self.counter += 1 - # cocotb.log.info("POP " + str(self.buffer.qsize())) + # cocotb._log.info("POP " + str(self.buffer.qsize())) readIncoming = int(ahb.HTRANS) >= 2 and int(ahb.HWRITE) == 0 size = 1 << int(ahb.HSIZE) From 4c47bada657dcb51280e8a609774f781d03e25d8 Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 17:02:50 +0100 Subject: [PATCH 28/69] Scorboard.py: dut.log is deprecated --- Scorboard.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/Scorboard.py b/Scorboard.py index 37c2325..5a4aa8d 100644 --- a/Scorboard.py +++ b/Scorboard.py @@ -34,7 +34,7 @@ def update(self): def match(self,uut,ref): if not uut.equalRef(ref): - cocotb.log.error("Missmatch detected in " + self.getPath()) + cocotb._log.error("Missmatch detected in " + self.getPath()) uut.assertEqualRef(ref) def startPhase(self, phase): @@ -48,7 +48,7 @@ def startPhase(self, phase): for e in self.uuts.queue: error += "UUT:\n" + str(e) + "\n" - cocotb.log.error(error) + cocotb._log.error(error) def endPhase(self, phase): @@ -104,7 +104,7 @@ def match(self,uut,ref): l(uut,ref,equal) if not equal: - cocotb.log.error("Missmatch detected in " + self.getPath()) + cocotb._log.error("Missmatch detected in " + self.getPath()) uut.assertEqualRef(ref) def startPhase(self, phase): @@ -120,7 +120,7 @@ def startPhase(self, phase): for e in l.queue: error += "UUT:\n" + str(e) + "\n" - cocotb.log.error(error) + cocotb._log.error(error) def endPhase(self, phase): From 3b92a7dcfe41c0e658b92d71faa714905bc6dcd9 Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 17:02:52 +0100 Subject: [PATCH 29/69] AhbLite3.py: Whitespace change only --- AhbLite3.py | 44 +++++++++++++++++++++++--------------------- 1 file changed, 23 insertions(+), 21 deletions(-) diff --git a/AhbLite3.py b/AhbLite3.py index 279afff..e96df74 100644 --- a/AhbLite3.py +++ b/AhbLite3.py @@ -19,7 +19,6 @@ def AhbLite3MasterIdle(ahb): ahb.HWDATA.value = 0 - class AhbLite3Transaction: def __init__(self): self.HADDR = 0 @@ -31,12 +30,14 @@ def __init__(self): self.HMASTLOCK = 0 self.HWDATA = 0 + class AhbLite3TraficGenerator: - def __init__(self,addressWidth,dataWidth): + def __init__(self, addressWidth, dataWidth): self.addressWidth = addressWidth self.dataWidth = dataWidth + def genRandomAddress(self): - return random.randint(0,(1 << self.addressWidth)-1) + return random.randint(0, (1 << self.addressWidth)-1) def getTransactions(self): if random.random() < 0.8: @@ -44,12 +45,12 @@ def getTransactions(self): return [trans] else: OneKiB = 1 << 10 # this pesky 1 KiB wall a burst must not cross - hSize = random.randint(0,log2Up(self.dataWidth//8)) + hSize = random.randint(0, log2Up(self.dataWidth//8)) bytesPerBeat = 1 << hSize - maxBurst = 5 if hSize == 7 else 7 # a full-width 1024 bit bus can only burst up to 8 beats for not crossing a 1 KiB boundary - burst = random.randint(0,maxBurst) + maxBurst = 5 if hSize == 7 else 7 # a full-width 1024 bit bus can only burst up to 8 beats for not crossing a 1 KiB boundary + burst = random.randint(0, maxBurst) write = random.random() < 0.5 - prot = random.randint(0,15) + prot = random.randint(0, 15) address = self.genRandomAddress() & ~(bytesPerBeat-1) incrUnspecified = burst == 1 @@ -58,17 +59,17 @@ def getTransactions(self): if incrUnspecified: maxBeats = (OneKiB - (address % OneKiB)) // bytesPerBeat - burstBeats = random.randint(1,maxBeats) + burstBeats = random.randint(1, maxBeats) else: burstCase = burst >> 1 - burstBeats = [1,4,8,16][burstCase] + burstBeats = [1, 4, 8, 16][burstCase] burstBytes = bytesPerBeat*burstBeats while incrFixed and ((address % OneKiB) + burstBytes) > OneKiB: address = address - bytesPerBeat - addressBase = address - address % burstBytes # for wrapFixed bursts + addressBase = address - address % burstBytes # for wrapFixed bursts buffer = [] for beat in range(burstBeats): @@ -81,8 +82,8 @@ def getTransactions(self): trans.HBURST = burst trans.HPROT = prot trans.HADDR = address - trans.HTRANS = 1 # BUSY - trans.HWDATA = random.randint(0,(1 << self.dataWidth)-1) + trans.HTRANS = 1 # BUSY + trans.HWDATA = random.randint(0, (1 << self.dataWidth)-1) buffer.append(trans) trans = AhbLite3Transaction() trans.HWRITE = write @@ -90,16 +91,17 @@ def getTransactions(self): trans.HBURST = burst trans.HPROT = prot trans.HADDR = address - trans.HTRANS = 2 if beat == 0 else 3 # first beat is NONSEQ, others are SEQ - trans.HWDATA = random.randint(0,(1 << self.dataWidth)-1) + trans.HTRANS = 2 if beat == 0 else 3 # first beat is NONSEQ, others are SEQ + trans.HWDATA = random.randint(0, (1 << self.dataWidth)-1) address += bytesPerBeat if wrapFixed and (address == addressBase + burstBytes): address = addressBase buffer.append(trans) return buffer + class AhbLite3MasterDriver: - def __init__(self,ahb,transactor,clk,reset): + def __init__(self, ahb, transactor, clk, reset): self.ahb = ahb self.clk = clk self.reset = reset @@ -134,8 +136,9 @@ def stim(self): ahb.HWDATA.value = HWDATAbuffer HWDATAbuffer = trans.HWDATA + class AhbLite3Terminaison: - def __init__(self,ahb,clk,reset): + def __init__(self, ahb, clk, reset): self.ahb = ahb self.clk = clk self.reset = reset @@ -164,7 +167,7 @@ def doComb(self): class AhbLite3MasterReadChecker: - def __init__(self,ahb,buffer,clk,reset): + def __init__(self, ahb, buffer, clk, reset): self.ahb = ahb self.clk = clk self.reset = reset @@ -185,7 +188,7 @@ def stim(self): bufferData = self.buffer.get() for i in range(byteOffset,byteOffset + size): - assertEquals((int(ahb.HRDATA) >> (i*8)) & 0xFF,(bufferData >> (i*8)) & 0xFF,"AHB master read checker faild %x " %(int(ahb.HADDR)) ) + assertEquals((int(ahb.HRDATA) >> (i*8)) & 0xFF, (bufferData >> (i*8)) & 0xFF, "AHB master read checker faild %x " % (int(ahb.HADDR))) self.counter += 1 # cocotb._log.info("POP " + str(self.buffer.qsize())) @@ -195,9 +198,8 @@ def stim(self): byteOffset = int(ahb.HADDR) % (len(ahb.HWDATA) // 8) - class AhbLite3SlaveMemory: - def __init__(self,ahb,base,size,clk,reset): + def __init__(self, ahb, base, size, clk, reset): self.ahb = ahb self.clk = clk self.reset = reset @@ -243,7 +245,7 @@ def stim(self): if trans >= 2: if write == 1: for idx in range(size): - self.ram[address-self.base + idx] = (int(ahb.HWDATA) >> (8*(addressOffset + idx))) & 0xFF + self.ram[address-self.base + idx] = (int(ahb.HWDATA) >> (8*(addressOffset + idx))) & 0xFF # print("write %x with %x" % (address + idx,(int(ahb.HWDATA) >> (8*(addressOffset + idx))) & 0xFF)) valid = int(ahb.HSEL) From 1749517ae70ab7e7e4af294c150dcbcc899571cb Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 17:05:03 +0100 Subject: [PATCH 30/69] Apb3.py: Whitespace change only --- Apb3.py | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/Apb3.py b/Apb3.py index 4df046f..e2f1fa3 100644 --- a/Apb3.py +++ b/Apb3.py @@ -9,7 +9,7 @@ class Apb3: - def __init__(self, dut, name, clk = None): + def __init__(self, dut, name, clk=None): self.clk = clk self.PADDR = dut.__getattr__(name + "_PADDR") self.PSEL = dut.__getattr__(name + "_PSEL") @@ -28,7 +28,7 @@ def delay(self, cycle): yield RisingEdge(self.clk) @coroutine - def write(self, address, data, sel = 1): + def write(self, address, data, sel=1): self.PADDR.value = address self.PSEL.value = sel self.PENABLE.value = False @@ -44,10 +44,10 @@ def write(self, address, data, sel = 1): randSignal(self.PWDATA) @coroutine - def writeMasked(self, address, data, mask, sel = 1): - readThread = self.read(address,sel) + def writeMasked(self, address, data, mask, sel=1): + readThread = self.read(address, sel) yield readThread - yield self.write(address,(readThread.retval & ~mask) | (data & mask),sel) + yield self.write(address, (readThread.retval & ~mask) | (data & mask), sel) @coroutine def read(self, address, sel=1): @@ -65,18 +65,17 @@ def read(self, address, sel=1): randSignal(self.PWRITE) raise ReturnValue(int(self.PRDATA)) - @coroutine def readAssert(self, address, data, sel=1): - readThread = self.read(address,sel) + readThread = self.read(address, sel) yield readThread - assertEquals(int(readThread.retval), data," APB readAssert failure") + assertEquals(int(readThread.retval), data, " APB readAssert failure") @coroutine def readAssertMasked(self, address, data, mask, sel=1): - readThread = self.read(address,sel) + readThread = self.read(address, sel) yield readThread - assertEquals(int(readThread.retval) & mask, data," APB readAssert failure") + assertEquals(int(readThread.retval) & mask, data, " APB readAssert failure") @coroutine def pull(self, address, dataValue, dataMask, sel=1): @@ -84,4 +83,4 @@ def pull(self, address, dataValue, dataMask, sel=1): readThread = self.read(address, sel) yield readThread if (int(readThread.retval) & dataMask) == dataValue: - break \ No newline at end of file + break From 1ae8205d2c744bdeaf189a1222bdda3f8b9dc7d1 Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 17:05:56 +0100 Subject: [PATCH 31/69] Axi4.py: Whitespace change only --- Axi4.py | 80 ++++++++++++++++++++++++++++----------------------------- 1 file changed, 40 insertions(+), 40 deletions(-) diff --git a/Axi4.py b/Axi4.py index a02709e..58f6f70 100644 --- a/Axi4.py +++ b/Axi4.py @@ -4,38 +4,40 @@ from .Phase import PHASE_SIM, Infrastructure from .Scorboard import ScorboardOutOfOrder from .misc import BoolRandomizer, log2Up, randBits - from .Stream import Stream, Transaction, StreamDriverSlave, StreamDriverMaster, StreamMonitor class Axi4: - def __init__(self,dut,name): - self.ar = Stream(dut,name + "_ar") - self.r = Stream(dut, name + "_r") + def __init__(self, dut, name): + self.ar = Stream(dut, name + "_ar") + self.r = Stream(dut, name + "_r") self.aw = Stream(dut, name + "_aw") - self.w = Stream(dut, name + "_w") - self.b = Stream(dut, name + "_b") + self.w = Stream(dut, name + "_w") + self.b = Stream(dut, name + "_b") + class Axi4ReadOnly: - def __init__(self,dut,name): - self.ar = Stream(dut,name + "_ar") - self.r = Stream(dut, name + "_r") + def __init__(self, dut, name): + self.ar = Stream(dut, name + "_ar") + self.r = Stream(dut, name + "_r") + class Axi4WriteOnly: - def __init__(self,dut,name): + def __init__(self, dut, name): self.aw = Stream(dut, name + "_aw") - self.w = Stream(dut, name + "_w") - self.b = Stream(dut, name + "_b") + self.w = Stream(dut, name + "_w") + self.b = Stream(dut, name + "_b") + class Axi4Shared: - def __init__(self,dut,name): - self.arw = Stream(dut,name + "_arw") - self.r = Stream(dut, name + "_r") - self.w = Stream(dut, name + "_w") - self.b = Stream(dut, name + "_b") + def __init__(self, dut, name): + self.arw = Stream(dut, name + "_arw") + self.r = Stream(dut, name + "_r") + self.w = Stream(dut, name + "_w") + self.b = Stream(dut, name + "_b") -def Axi4AddrIncr(address,burst,len,size): +def Axi4AddrIncr(address, burst, len, size): if burst == 0: return address if burst == 1: @@ -47,10 +49,9 @@ def Axi4AddrIncr(address,burst,len,size): return (address & ~burstMask) | base - class Axi4SharedMemoryChecker(Infrastructure): - def __init__(self,name,parent,axi,addressWidth,clk,reset): - Infrastructure.__init__(self,name,parent) + def __init__(self, name, parent, axi, addressWidth, clk, reset): + Infrastructure.__init__(self, name, parent) self.axi = axi self.idWidth = len(axi.arw.payload.hid) self.addressWidth = addressWidth @@ -59,11 +60,11 @@ def __init__(self,name,parent,axi,addressWidth,clk,reset): self.readWriteRand = BoolRandomizer() self.writeDataRand = BoolRandomizer() self.writeRspScoreboard = ScorboardOutOfOrder("writeRspScoreboard", self) - self.readRspScoreboard = ScorboardOutOfOrder("readRspScoreboard", self) + self.readRspScoreboard = ScorboardOutOfOrder("readRspScoreboard", self) self.writeRspScoreboard.addListener(self.freeReservatedAddresses) self.readRspScoreboard.addListener(self.freeReservatedAddresses) - self.cmdTasks = Queue() - self.writeTasks = Queue() + self.cmdTasks = Queue() + self.writeTasks = Queue() self.nonZeroReadRspCounter = 0 self.nonZeroReadRspCounterTarget = 1000 self.reservedAddresses = {} @@ -77,10 +78,10 @@ def __init__(self,name,parent,axi,addressWidth,clk,reset): axi.w.payload.last.value = 0 axi.r.payload.last.value = 0 - def freeReservatedAddresses(self,uut,ref,equal): - self.reservedAddresses.pop(ref,None) + def freeReservatedAddresses(self, uut, ref, equal): + self.reservedAddresses.pop(ref, None) - def isAddressRangeBusy(self,start,end): + def isAddressRangeBusy(self, start, end): for r in self.reservedAddresses.values(): if start < r[1] and end > r[0]: return True @@ -94,10 +95,10 @@ def genNewCmd(self): cmd.hid = randBits(self.idWidth) # Each master can use 4 id cmd.region = randBits(4) cmd.len = randBits(4) - cmd.size = random.randint(0,log2Up(self.dataWidth//8)) - cmd.burst = random.randint(0,2) + cmd.size = random.randint(0, log2Up(self.dataWidth//8)) + cmd.burst = random.randint(0, 2) if cmd.burst == 2: - cmd.len = random.choice([2,4,8,16])-1 + cmd.len = random.choice([2, 4, 8, 16])-1 else: cmd.len = randBits(4) + (16 if random.random() < 0.1 else 0) + (32 if random.random() < 0.02 else 0) cmd.lock = randBits(1) @@ -107,13 +108,13 @@ def genNewCmd(self): byteCount = (1 << cmd.size)*(cmd.len + 1) while(True): - cmd.addr = self.genRandomeAddress() & ~((1 << cmd.size)-1) + cmd.addr = self.genRandomeAddress() & ~((1 << cmd.size)-1) if cmd.burst == 1: - if cmd.addr + byteCount >= (1<= (1 << self.addressWidth): continue if cmd.burst == 0: start = cmd.addr - end = start + cmd.size + end = start + cmd.size if cmd.burst == 1: start = cmd.addr @@ -123,7 +124,7 @@ def genNewCmd(self): start = cmd.addr & ~(byteCount-1) end = start + byteCount - if self.isAddressRangeBusy(start,end): + if self.isAddressRangeBusy(start, end): continue break @@ -140,14 +141,14 @@ def genNewCmd(self): for s in range(self.dataWidth//8): if (dataTrans.strb >> s) & 1 == 1: self.ram[(beatAddr & ~(self.dataWidth//8-1)) + s] = (dataTrans.data >> (s*8)) & 0xFF - beatAddr = Axi4AddrIncr(beatAddr,cmd.burst,cmd.len,cmd.size) + beatAddr = Axi4AddrIncr(beatAddr, cmd.burst, cmd.len, cmd.size) writeRsp = Transaction() writeRsp.resp = 0 writeRsp.hid = cmd.hid - self.reservedAddresses[writeRsp] = [start,end] - self.writeRspScoreboard.refPush(writeRsp,writeRsp.hid) + self.reservedAddresses[writeRsp] = [start, end] + self.writeRspScoreboard.refPush(writeRsp, writeRsp.hid) else: cmd.write = 0 @@ -169,7 +170,6 @@ def genNewCmd(self): self.cmdTasks.put(cmd) # print(str(len(self.cmdTasks.queue)) + " " + str(len(self.writeTasks.queue))) - def genReadWriteCmd(self): if self.doReadWriteCmdRand.get(): while self.cmdTasks.empty(): @@ -186,8 +186,8 @@ def genWriteData(self): self.genNewCmd() return self.writeTasks.get() - def onWriteRsp(self,trans): - self.writeRspScoreboard.uutPush(trans,trans.hid) + def onWriteRsp(self, trans): + self.writeRspScoreboard.uutPush(trans, trans.hid) def onReadRsp(self, trans): self.readRspScoreboard.uutPush(trans, trans.hid) From 29ef28efe365ee225d3bf85ef84cc87ea63a02e8 Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 17:07:00 +0100 Subject: [PATCH 32/69] ClockDomain.py: Whitespace change only --- ClockDomain.py | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/ClockDomain.py b/ClockDomain.py index 0559082..cdd44ce 100644 --- a/ClockDomain.py +++ b/ClockDomain.py @@ -21,8 +21,6 @@ class RESET_ACTIVE_LEVEL: # cocotb.start_soon( clockDomain.start() ) # class ClockDomain: - - ########################################################################## # Constructor # @@ -31,11 +29,10 @@ class ClockDomain: # @param reset : Reset generated # @param resetactiveLevel : Reset active low or high def __init__(self, clk, halfPeriod, reset=None, resetActiveLevel=RESET_ACTIVE_LEVEL.LOW): - self.halfPeriod = halfPeriod - self.clk = clk - self.reset = reset + self.clk = clk + self.reset = reset self.typeReset = resetActiveLevel self.event_endReset = Event() @@ -47,7 +44,7 @@ def __init__(self, clk, halfPeriod, reset=None, resetActiveLevel=RESET_ACTIVE_LE def start(self): self.fork_gen = cocotb.start_soon(self._clkGen()) - if self.reset != None : + if self.reset != None: cocotb.start_soon(self._waitEndReset()) if self.reset: @@ -62,7 +59,6 @@ def start(self): ########################################################################## # Stop all processes def stop(self): - self.fork_gen.kill() From 2b5392a72729549b9283e80d154bfcdbed80ad17 Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 17:09:46 +0100 Subject: [PATCH 33/69] Flow.py: Whitespace change only --- Flow.py | 24 +++++++++++------------- 1 file changed, 11 insertions(+), 13 deletions(-) diff --git a/Flow.py b/Flow.py index 4b5db9f..ea05e8d 100644 --- a/Flow.py +++ b/Flow.py @@ -9,41 +9,39 @@ # Flow # class Flow: - - #========================================================================== + # ========================================================================== # Constructor - #========================================================================== + # ========================================================================== def __init__(self, dut, name): - # interface self.valid = dut.__getattr__(name + "_valid") - self.payload = Bundle(dut,name + "_payload") + self.payload = Bundle(dut, name + "_payload") # Event self.event_valid = Event() - #========================================================================== + # ========================================================================== # Start to monitor the valid signal - #========================================================================== + # ========================================================================== def startMonitoringValid(self, clk): - self.clk = clk + self.clk = clk self.fork_valid = cocotb.start_soon(self.monitor_valid()) - #========================================================================== + # ========================================================================== # Stop monitoring - #========================================================================== + # ========================================================================== def stopMonitoring(self): self.fork_valid.kill() - #========================================================================== + # ========================================================================== # Monitor the valid signal - #========================================================================== + # ========================================================================== @coroutine def monitor_valid(self): while True: yield RisingEdge(self.clk) if int(self.valid) == 1: - self.event_valid.set( self.payload ) + self.event_valid.set(self.payload) From cea05b398367ff5b86f6cf24815c86b1dc13a75a Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 17:12:27 +0100 Subject: [PATCH 34/69] Phase.py: Whitespace change only --- Phase.py | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/Phase.py b/Phase.py index db6da68..cc9d69e 100644 --- a/Phase.py +++ b/Phase.py @@ -11,7 +11,7 @@ class Infrastructure: - def __init__(self,name,parent): + def __init__(self, name, parent): self.name = name self.parent = parent if parent != None: @@ -41,7 +41,7 @@ def endPhase(self, phase): for child in self.children: child.endPhase(phase) - def addChild(self,child): + def addChild(self, child): if child not in self.children: self.children.append(child) @@ -60,7 +60,7 @@ def __init__(self): self.waitTasksEndTime = 0 # setSimManager(self) - def setWaitTasksEndTime(self,value): + def setWaitTasksEndTime(self, value): self.waitTasksEndTime = value @coroutine @@ -73,7 +73,7 @@ def waitChild(self): def getPhase(self): return self.phase - def switchPhase(self,phase): + def switchPhase(self, phase): for infra in self.children: infra.endPhase(self.phase) self.phase = phase @@ -90,6 +90,7 @@ def run(self): self.switchPhase(PHASE_CHECK_SCORBOARDS) self.switchPhase(PHASE_DONE) + # _simManager = None # # def getSimManager(): @@ -99,6 +100,3 @@ def run(self): # global _simManager # _simManager = that # - - - From 0beca2b42b6b789d6419e29e43f7b29cb3c8237e Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 17:13:51 +0100 Subject: [PATCH 35/69] Scorboard.py: Whitespace change only --- Scorboard.py | 36 +++++++++++++++--------------------- 1 file changed, 15 insertions(+), 21 deletions(-) diff --git a/Scorboard.py b/Scorboard.py index 5a4aa8d..01e58c7 100644 --- a/Scorboard.py +++ b/Scorboard.py @@ -7,19 +7,19 @@ class ScorboardInOrder(Infrastructure): - def __init__(self,name,parent): - Infrastructure.__init__(self,name,parent) + def __init__(self, name, parent): + Infrastructure.__init__(self, name, parent) self.refs = Queue() self.uuts = Queue() self.refsCounter = 0 self.uutsCounter = 0 - def refPush(self,ref): + def refPush(self, ref): self.refs.put(ref) self.refsCounter += 1 self.update() - def uutPush(self,uut): + def uutPush(self, uut): self.uuts.put(uut) self.uutsCounter += 1 self.update() @@ -29,10 +29,9 @@ def update(self): ref = self.refs.get() uut = self.uuts.get() - self.match(uut,ref) + self.match(uut, ref) - - def match(self,uut,ref): + def match(self, uut, ref): if not uut.equalRef(ref): cocotb._log.error("Missmatch detected in " + self.getPath()) uut.assertEqualRef(ref) @@ -50,7 +49,6 @@ def startPhase(self, phase): cocotb._log.error(error) - def endPhase(self, phase): Infrastructure.endPhase(self, phase) if phase == PHASE_CHECK_SCORBOARDS: @@ -59,17 +57,16 @@ def endPhase(self, phase): class ScorboardOutOfOrder(Infrastructure): - def __init__(self,name,parent): - Infrastructure.__init__(self,name,parent) + def __init__(self, name, parent): + Infrastructure.__init__(self, name, parent) self.refsDic = {} self.uutsDic = {} self.listeners = [] - - def addListener(self,func): + def addListener(self, func): self.listeners.append(func) - def refPush(self,ref,oooid): + def refPush(self, ref, oooid): if oooid not in self.refsDic: self.refsDic[oooid] = Queue() self.refsDic[oooid].put(ref) @@ -81,7 +78,7 @@ def uutPush(self, uut, oooid): self.uutsDic[oooid].put(uut) self.update(oooid) - def update(self,oooid): + def update(self, oooid): if oooid in self.uutsDic and oooid in self.refsDic: refs = self.refsDic[oooid] uuts = self.uutsDic[oooid] @@ -89,19 +86,18 @@ def update(self,oooid): ref = refs.get() uut = uuts.get() - self.match(uut,ref) + self.match(uut, ref) - #Clean + # Clean if refs.empty(): self.refsDic.pop(oooid) if uuts.empty(): self.uutsDic.pop(oooid) - - def match(self,uut,ref): + def match(self, uut, ref): equal = uut.equalRef(ref) for l in self.listeners: - l(uut,ref,equal) + l(uut, ref, equal) if not equal: cocotb._log.error("Missmatch detected in " + self.getPath()) @@ -122,10 +118,8 @@ def startPhase(self, phase): cocotb._log.error(error) - def endPhase(self, phase): Infrastructure.endPhase(self, phase) if phase == PHASE_CHECK_SCORBOARDS: if len(self.refsDic) != 0 or len(self.uutsDic) != 0: raise TestFailure("Scoreboard not empty") - From 5c28060474dc9f16c288e289a701e3589a22e7a7 Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 17:14:08 +0100 Subject: [PATCH 36/69] Spi.py: Whitespace change only --- Spi.py | 16 +++++----------- 1 file changed, 5 insertions(+), 11 deletions(-) diff --git a/Spi.py b/Spi.py index 09ff091..1ca13f8 100644 --- a/Spi.py +++ b/Spi.py @@ -14,23 +14,17 @@ def __init__(self, dut, name): self.sclk = dut.__getattr__(name + "_sclk") self.mosi = dut.__getattr__(name + "_mosi") self.miso = dut.__getattr__(name + "_miso") - self.ss = dut.__getattr__(name + "_ss") - - - + self.ss = dut.__getattr__(name + "_ss") class SpiSlave: def __init__(self, dut, name): self.sclk = dut.__getattr__(name + "_sclk") self.mosi = dut.__getattr__(name + "_mosi") - self.miso = TriStateOutput(dut,name + "_miso") + self.miso = TriStateOutput(dut, name + "_miso") self.ss = dut.__getattr__(name + "_ss") - - - class SpiSlaveMaster: def __init__(self, spi): self.spi = spi @@ -39,7 +33,7 @@ def __init__(self, spi): self.baudPeriode = 1000 self.dataWidth = 8 - def init(self, cpol, cpha, baudrate, dataWidth = 8): + def init(self, cpol, cpha, baudrate, dataWidth=8): self.spi.ss.value = True self.cpol = cpol self.cpha = cpha @@ -71,7 +65,7 @@ def exchange(self, masterData): self.spi.sclk.value = (self.cpol) else: for i in range(self.dataWidth): - self.spi.mosi.value = testBit(masterData, self.dataWidth -1 - i) + self.spi.mosi.value = testBit(masterData, self.dataWidth - 1 - i) self.spi.sclk.value = (not self.cpol) yield Timer(self.baudPeriode >> 1) buffer = buffer + str(self.spi.miso.write) if bool(self.spi.miso.writeEnable) else "x" @@ -84,4 +78,4 @@ def exchange(self, masterData): def exchangeCheck(self, masterData, slaveData): c = self.exchange(masterData) yield c - assert slaveData == int(c.retval,2) \ No newline at end of file + assert slaveData == int(c.retval, 2) From 899580ffc55dd9a1ae63df53aa2fb71fc75ac1d1 Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 17:15:34 +0100 Subject: [PATCH 37/69] Stream.py: Whitespace change only --- Stream.py | 58 ++++++++++++++++++++++++++----------------------------- 1 file changed, 27 insertions(+), 31 deletions(-) diff --git a/Stream.py b/Stream.py index ec7aad5..8e4b781 100644 --- a/Stream.py +++ b/Stream.py @@ -10,21 +10,22 @@ from .Scorboard import ScorboardInOrder from .misc import Bundle, BoolRandomizer + class Stream: def __init__(self, dut, name): - self.valid = dut.__getattr__(name + "_valid") - self.ready = dut.__getattr__(name + "_ready") - self.payload = Bundle(dut,name + "_payload") + self.valid = dut.__getattr__(name + "_valid") + self.ready = dut.__getattr__(name + "_ready") + self.payload = Bundle(dut, name + "_payload") # Event self.event_ready = Event() self.event_valid = Event() def startMonitoringReady(self, clk): - self.clk = clk + self.clk = clk self.fork_ready = cocotb.start_soon(self.monitor_ready()) def startMonitoringValid(self, clk): - self.clk = clk + self.clk = clk self.fork_valid = cocotb.start_soon(self.monitor_valid()) def stopMonitoring(self): @@ -36,39 +37,38 @@ def monitor_ready(self): while True: yield RisingEdge(self.clk) if int(self.ready) == 1: - self.event_ready.set( self.payload ) + self.event_ready.set(self.payload) @coroutine def monitor_valid(self): while True: yield RisingEdge(self.clk) if int(self.valid) == 1: - self.event_valid.set( self.payload ) + self.event_valid.set(self.payload) class Transaction(object): def __init__(self): - object.__setattr__(self,"_nameToElement",{}) + object.__setattr__(self, "_nameToElement", {}) def __setattr__(self, key, value): # print("set " + key) if key[0] != '_': self._nameToElement[key] = value - object.__setattr__(self,key,value) + object.__setattr__(self, key, value) - def equalRef(self,ref): + def equalRef(self, ref): # if(len(self._nameToElement) != len(ref._nameToElement)): # return False for name in self._nameToElement: - refValue = getattr(ref,name) - if refValue != None and self._nameToElement[name] != getattr(ref,name): + refValue = getattr(ref, name) + if refValue != None and self._nameToElement[name] != getattr(ref, name): return False return True - def assertEqualRef(self,ref): + def assertEqualRef(self, ref): if not self.equalRef(ref): - raise TestFailure("\nFAIL transaction not equal\ntransaction =>\n%s\nref =>\n%s\n\n" % (self,ref)) - + raise TestFailure("\nFAIL transaction not equal\ntransaction =>\n%s\nref =>\n%s\n\n" % (self, ref)) def __str__(self): buffer = "" @@ -78,13 +78,14 @@ def __str__(self): biggerName = len(n) for name in self._nameToElement: e = self._nameToElement[name] - buffer += "%s %s: 0x%x\n" % (name," "*(biggerName-len(name)), 0 if e == None else e) + buffer += "%s %s: 0x%x\n" % (name, " "*(biggerName-len(name)), 0 if e == None else e) return buffer # Transaction = type('Transaction', (object,), {}) + class StreamDriverMaster: - def __init__(self,stream,transactor,clk,reset): + def __init__(self, stream, transactor, clk, reset): self.stream = stream self.clk = clk self.reset = reset @@ -104,26 +105,25 @@ def stim(self): yield RisingEdge(self.clk) if self.transactor != None and (int(stream.valid) == 0 or int(stream.ready) == 1): - if isinstance(self.transactor,types.GeneratorType): + if isinstance(self.transactor, types.GeneratorType): trans = next(self.transactor) else: trans = self.transactor() if trans != None: - if hasattr(trans,"nextDelay"): + if hasattr(trans, "nextDelay"): nextDelay = trans.nextDelay else: nextDelay = 0 stream.valid.value = 1 for name in stream.payload.nameToElement: - if hasattr(trans,name) == False: + if hasattr(trans, name) == False: raise Exception("Missing element in bundle :" + name) - e = stream.payload.nameToElement[name].value = getattr(trans,name) - + e = stream.payload.nameToElement[name].value = getattr(trans, name) class StreamDriverSlave: - def __init__(self,stream,clk,reset): + def __init__(self, stream, clk, reset): self.stream = stream self.clk = clk self.reset = reset @@ -142,12 +142,12 @@ def stim(self): def TransactionFromBundle(bundle): trans = Transaction() for name in bundle.nameToElement: - setattr(trans,name, int(bundle.nameToElement[name])) + setattr(trans, name, int(bundle.nameToElement[name])) return trans class StreamMonitor: - def __init__(self,stream,callback,clk,reset): + def __init__(self, stream, callback, clk, reset): self.stream = stream self.callback = callback self.clk = clk @@ -165,11 +165,9 @@ def stim(self): self.callback(trans) - - class StreamFifoTester(Infrastructure): - def __init__(self,name,parent,pushStream,popStream,transactionGenerator,dutCounterTarget,clk,reset): - Infrastructure.__init__(self,name,parent) + def __init__(self, name, parent, pushStream, popStream, transactionGenerator, dutCounterTarget, clk, reset): + Infrastructure.__init__(self, name, parent) self.pushStream = pushStream self.popStream = popStream self.clk = clk @@ -205,5 +203,3 @@ def onRef(self, uut): def canPhaseProgress(self, phase): return self.dutCounter > self.dutCounterTarget - - From 39eb195a92477b245e3e60fd90dff4ed0a3b22b1 Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 17:18:17 +0100 Subject: [PATCH 38/69] TriState.py: Whitespace change only --- TriState.py | 20 ++++++++------------ 1 file changed, 8 insertions(+), 12 deletions(-) diff --git a/TriState.py b/TriState.py index c2e06d7..8f86bbc 100644 --- a/TriState.py +++ b/TriState.py @@ -2,25 +2,21 @@ # Tristate # class TriState: - - #========================================================================== + # ========================================================================== # Constructor - #========================================================================== + # ========================================================================== def __init__(self, dut, name): - # interface - self.read = dut.__getattr__(name + "_read") - self.write = dut.__getattr__(name + "_write") + self.read = dut.__getattr__(name + "_read") + self.write = dut.__getattr__(name + "_write") self.writeEnable = dut.__getattr__(name + "_writeEnable") class TriStateOutput: - - #========================================================================== + # ========================================================================== # Constructor - #========================================================================== + # ========================================================================== def __init__(self, dut, name): - # interface - self.write = dut.__getattr__(name + "_write") - self.writeEnable = dut.__getattr__(name + "_writeEnable") \ No newline at end of file + self.write = dut.__getattr__(name + "_write") + self.writeEnable = dut.__getattr__(name + "_writeEnable") From 92187c7e486098491067c371c64f11c001d710d9 Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 17:18:45 +0100 Subject: [PATCH 39/69] misc.py: Whitespace change only --- misc.py | 80 +++++++++++++++++++++++++++++++++------------------------ 1 file changed, 46 insertions(+), 34 deletions(-) diff --git a/misc.py b/misc.py index eabc40d..6d923c3 100644 --- a/misc.py +++ b/misc.py @@ -6,54 +6,64 @@ from cocotb.triggers import Timer, RisingEdge from cocotb.decorators import coroutine + def cocotbXHack(): - if hasattr(BinaryValue,"_resolve_to_0"): + if hasattr(BinaryValue, "_resolve_to_0"): # cocotb <= 1.4.0 - BinaryValue._resolve_to_0 = BinaryValue._resolve_to_0 + BinaryValue._resolve_to_error + BinaryValue._resolve_to_0 = BinaryValue._resolve_to_0 + BinaryValue._resolve_to_error BinaryValue._resolve_to_error = "" elif hasattr(cocotb.binary, "resolve_x_to"): # cocotb 1.5.0+ cocotb.binary.resolve_x_to = "ZEROS" cocotb.binary._resolve_table = cocotb.binary._ResolveTable() + def log2Up(value): return value.bit_length()-1 -def randInt(min,max): + +def randInt(min, max): return random.randint(min, max) + def randBool(): return bool(random.getrandbits(1)) + def randBits(width): return random.getrandbits(width) + def randSignal(that): that.value = random.getrandbits(len(that)) -def randBoolSignal(that,prob): + +def randBoolSignal(that, prob): that.value = (random.random() < prob) @coroutine -def clockedWaitTrue(clk,that): +def clockedWaitTrue(clk, that): while True: yield RisingEdge(clk) if that == True: break + def assertEquals(a, b, name): if int(a) != int(b): - raise TestFailure("FAIL %s %d != %d" % (name,int(a),int(b))) + raise TestFailure("FAIL %s %d != %d" % (name, int(a), int(b))) + def truncUInt(value, signal): - if isinstance( signal, int ): + if isinstance(signal, int): return value & ((1 << signal)-1) else: return value & ((1 << len(signal)) - 1) + def truncSInt(value, signal): - if isinstance( signal, int ): + if isinstance(signal, int): bitCount = signal else: bitCount = len(signal) @@ -65,25 +75,28 @@ def truncSInt(value, signal): def setBit(v, index, x): - mask = 1 << index - v &= ~mask - if x: - v |= mask - return v + mask = 1 << index + v &= ~mask + if x: + v |= mask + return v + def testBit(int_type, offset): - mask = 1 << offset - return (int_type & mask) != 0 + mask = 1 << offset + return (int_type & mask) != 0 + def uint(signal): return signal.value.integer + def sint(signal): return signal.value.signed_integer @coroutine -def ClockDomainAsyncReset(clk,reset,period = 1000): +def ClockDomainAsyncReset(clk, reset, period=1000): if reset: reset.value = 1 clk.value = 0 @@ -96,6 +109,7 @@ def ClockDomainAsyncReset(clk,reset,period = 1000): clk.value = 1 yield Timer(period/2) + @coroutine def SimulationTimeout(duration): yield Timer(duration) @@ -103,6 +117,8 @@ def SimulationTimeout(duration): import time + + @coroutine def simulationSpeedPrinter(clk): counter = 0 @@ -113,11 +129,10 @@ def simulationSpeedPrinter(clk): thisTime = time.time() if thisTime - lastTime >= 1.0: lastTime = thisTime - print("Sim speed : %f khz" %(counter/1000.0)) + print("Sim speed : %f khz" % (counter/1000.0)) counter = 0 - class BoolRandomizer: def __init__(self): self.prob = 0.5 @@ -133,9 +148,8 @@ def get(self): return random.random() < self.prob - # class Stream: -# def __init__(self,name,dut): +# def __init__(self, name, dut): # self.valid = getattr(dut, name + "_valid") # self.ready = getattr(dut, name + "_ready") # payloads = [a for a in dut if a._name.startswith(name + "_payload")] @@ -143,11 +157,11 @@ def get(self): # self.payload = payloads[0] - MyObject = type('MyObject', (object,), {}) + @coroutine -def StreamRandomizer(streamName, onNew,handle, dut, clk): +def StreamRandomizer(streamName, onNew, handle, dut, clk): validRandomizer = BoolRandomizer() valid = getattr(dut, streamName + "_valid") ready = getattr(dut, streamName + "_ready") @@ -172,10 +186,11 @@ def StreamRandomizer(streamName, onNew,handle, dut, clk): for e in payloads: payload.__setattr__(e._name[len(streamName + "_payload_"):], int(e)) if onNew: - onNew(payload,handle) + onNew(payload, handle) + @coroutine -def FlowRandomizer(streamName, onNew,handle, dut, clk): +def FlowRandomizer(streamName, onNew, handle, dut, clk): validRandomizer = BoolRandomizer() valid = getattr(dut, streamName + "_valid") payloads = [a for a in dut if a._name.startswith(streamName + "_payload")] @@ -195,10 +210,11 @@ def FlowRandomizer(streamName, onNew,handle, dut, clk): for e in payloads: payload.__setattr__(e._name[len(streamName + "_payload_"):], int(e)) if onNew: - onNew(payload,handle) + onNew(payload, handle) else: valid.value = 0 + @coroutine def StreamReader(streamName, onTransaction, handle, dut, clk): validRandomizer = BoolRandomizer() @@ -219,12 +235,11 @@ def StreamReader(streamName, onTransaction, handle, dut, clk): payload.__setattr__(e._name[len(streamName + "_payload_"):], int(e)) if onTransaction: - onTransaction(payload,handle) - + onTransaction(payload, handle) class Bundle: - def __init__(self,dut,name): + def __init__(self, dut, name): self.nameToElement = {} self.elements = [a for a in dut if (a._name.lower().startswith(name.lower() + "_") and not a._name.lower().endswith("_readablebuffer"))] @@ -249,8 +264,7 @@ def __getattr__(self, name): return self.nameToElement[name] - -def readIHex(path, callback,context): +def readIHex(path, callback, context): with open(path) as f: offset = 0 for line in f: @@ -261,14 +275,13 @@ def readIHex(path, callback,context): key = int(line[7:9], 16) if key == 0: array = [int(line[9 + i * 2:11 + i * 2], 16) for i in range(0, byteCount)] - callback(nextAddr,array,context) + callback(nextAddr, array, context) elif key == 2: offset = int(line[9:13], 16) else: pass - @coroutine def TriggerAndCond(trigger, cond): while(True): @@ -285,8 +298,7 @@ def waitClockedCond(clk, cond): break - @coroutine def TimerClk(clk, count): for i in range(count): - yield RisingEdge(clk) \ No newline at end of file + yield RisingEdge(clk) From ba836eae855a2899b55257215236c320feed148e Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 17:20:52 +0100 Subject: [PATCH 40/69] AhbLite3.py: Whitespace change only (2nd) --- AhbLite3.py | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/AhbLite3.py b/AhbLite3.py index e96df74..0d7c100 100644 --- a/AhbLite3.py +++ b/AhbLite3.py @@ -21,14 +21,14 @@ def AhbLite3MasterIdle(ahb): class AhbLite3Transaction: def __init__(self): - self.HADDR = 0 - self.HWRITE = 0 - self.HSIZE = 0 - self.HBURST = 0 - self.HPROT = 0 - self.HTRANS = 0 + self.HADDR = 0 + self.HWRITE = 0 + self.HSIZE = 0 + self.HBURST = 0 + self.HPROT = 0 + self.HTRANS = 0 self.HMASTLOCK = 0 - self.HWDATA = 0 + self.HWDATA = 0 class AhbLite3TraficGenerator: @@ -111,14 +111,14 @@ def __init__(self, ahb, transactor, clk, reset): @coroutine def stim(self): ahb = self.ahb - ahb.HADDR.value = 0 - ahb.HWRITE.value = 0 - ahb.HSIZE.value = 0 - ahb.HBURST.value = 0 - ahb.HPROT.value = 0 - ahb.HTRANS.value = 0 + ahb.HADDR.value = 0 + ahb.HWRITE.value = 0 + ahb.HSIZE.value = 0 + ahb.HBURST.value = 0 + ahb.HPROT.value = 0 + ahb.HTRANS.value = 0 ahb.HMASTLOCK.value = 0 - ahb.HWDATA.value = 0 + ahb.HWDATA.value = 0 HWDATAbuffer = 0 while True: for trans in self.transactor.getTransactions(): @@ -233,8 +233,8 @@ def stimReady(self): def stim(self): ahb = self.ahb ahb.HREADYOUT.value = 1 - ahb.HRESP.value = 0 - ahb.HRDATA.value = 0 + ahb.HRESP.value = 0 + ahb.HRDATA.value = 0 valid = 0 while True: yield RisingEdge(self.clk) From 8f38841cc0f976d2f71638657a997fbb2312c8e5 Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 17:23:30 +0100 Subject: [PATCH 41/69] Apb3.py: Whitespace change only (2nd) --- Apb3.py | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/Apb3.py b/Apb3.py index e2f1fa3..f129121 100644 --- a/Apb3.py +++ b/Apb3.py @@ -11,13 +11,13 @@ class Apb3: def __init__(self, dut, name, clk=None): self.clk = clk - self.PADDR = dut.__getattr__(name + "_PADDR") - self.PSEL = dut.__getattr__(name + "_PSEL") - self.PENABLE = dut.__getattr__(name + "_PENABLE") - self.PREADY = dut.__getattr__(name + "_PREADY") - self.PWRITE = dut.__getattr__(name + "_PWRITE") - self.PWDATA = dut.__getattr__(name + "_PWDATA") - self.PRDATA = dut.__getattr__(name + "_PRDATA") + self.PADDR = dut.__getattr__(name + "_PADDR") + self.PSEL = dut.__getattr__(name + "_PSEL") + self.PENABLE = dut.__getattr__(name + "_PENABLE") + self.PREADY = dut.__getattr__(name + "_PREADY") + self.PWRITE = dut.__getattr__(name + "_PWRITE") + self.PWDATA = dut.__getattr__(name + "_PWDATA") + self.PRDATA = dut.__getattr__(name + "_PRDATA") def idle(self): self.PSEL.value = 0 @@ -36,7 +36,7 @@ def write(self, address, data, sel=1): self.PWDATA.value = data yield RisingEdge(self.clk) self.PENABLE.value = True - yield waitClockedCond(self.clk, lambda : self.PREADY == True) + yield waitClockedCond(self.clk, lambda: self.PREADY == True) randSignal(self.PADDR) self.PSEL.value = 0 randSignal(self.PENABLE) From 21cd5822ea42463b3803e036500584304fc1dafa Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 17:24:56 +0100 Subject: [PATCH 42/69] ClockDomain.py: Whitespace change only (2nd) --- ClockDomain.py | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/ClockDomain.py b/ClockDomain.py index cdd44ce..a02edaf 100644 --- a/ClockDomain.py +++ b/ClockDomain.py @@ -8,7 +8,7 @@ # class RESET_ACTIVE_LEVEL: HIGH = 1 - LOW = 0 + LOW = 0 ############################################################################### @@ -37,12 +37,10 @@ def __init__(self, clk, halfPeriod, reset=None, resetActiveLevel=RESET_ACTIVE_LE self.event_endReset = Event() - ########################################################################## # Generate the clock signals @coroutine def start(self): - self.fork_gen = cocotb.start_soon(self._clkGen()) if self.reset != None: cocotb.start_soon(self._waitEndReset()) @@ -55,13 +53,11 @@ def start(self): if self.reset: self.reset.value = int(1 if self.typeReset == RESET_ACTIVE_LEVEL.LOW else 0) - ########################################################################## # Stop all processes def stop(self): self.fork_gen.kill() - ########################################################################## # Generate the clk @coroutine @@ -72,7 +68,6 @@ def _clkGen(self): self.clk.value = 1 yield Timer(self.halfPeriod) - ########################################################################## # Wait the end of the reset @coroutine @@ -84,7 +79,6 @@ def _waitEndReset(self): self.event_endReset.set() break; - ########################################################################## # Display the frequency of the clock domain def __str__(self): From 9ec680f8a06a695c154cc7cd26c8f4d9f72d9734 Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 17:26:04 +0100 Subject: [PATCH 43/69] Flow.py: Whitespace change only (2nd) --- Flow.py | 3 --- 1 file changed, 3 deletions(-) diff --git a/Flow.py b/Flow.py index ea05e8d..202e288 100644 --- a/Flow.py +++ b/Flow.py @@ -20,7 +20,6 @@ def __init__(self, dut, name): # Event self.event_valid = Event() - # ========================================================================== # Start to monitor the valid signal # ========================================================================== @@ -28,14 +27,12 @@ def startMonitoringValid(self, clk): self.clk = clk self.fork_valid = cocotb.start_soon(self.monitor_valid()) - # ========================================================================== # Stop monitoring # ========================================================================== def stopMonitoring(self): self.fork_valid.kill() - # ========================================================================== # Monitor the valid signal # ========================================================================== From 395b015dc8745d5809dd0e6aee9aaa3dfe41a9f0 Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 17:26:29 +0100 Subject: [PATCH 44/69] ClockDomain.py: equality operator with object None --- ClockDomain.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ClockDomain.py b/ClockDomain.py index a02edaf..642adec 100644 --- a/ClockDomain.py +++ b/ClockDomain.py @@ -42,7 +42,7 @@ def __init__(self, clk, halfPeriod, reset=None, resetActiveLevel=RESET_ACTIVE_LE @coroutine def start(self): self.fork_gen = cocotb.start_soon(self._clkGen()) - if self.reset != None: + if self.reset is not None: cocotb.start_soon(self._waitEndReset()) if self.reset: From 0ef489ffd09bf1eab90d6862ae973a8b6bace030 Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 17:28:43 +0100 Subject: [PATCH 45/69] Phase.py: equality operator with object None --- Phase.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Phase.py b/Phase.py index cc9d69e..0128fab 100644 --- a/Phase.py +++ b/Phase.py @@ -14,7 +14,7 @@ class Infrastructure: def __init__(self, name, parent): self.name = name self.parent = parent - if parent != None: + if parent is not None: parent.addChild(self) self.children = [] @@ -46,7 +46,7 @@ def addChild(self, child): self.children.append(child) def getPath(self): - if self.parent != None: + if self.parent is not None: return self.parent.getPath() + "/" + self.name else: return self.name From b9b12e9eccd0c6252b25055b3c82ec7af16247c9 Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 17:29:52 +0100 Subject: [PATCH 46/69] Stream.py: equality operator with object None --- Stream.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/Stream.py b/Stream.py index 8e4b781..9e18c15 100644 --- a/Stream.py +++ b/Stream.py @@ -62,7 +62,7 @@ def equalRef(self, ref): # return False for name in self._nameToElement: refValue = getattr(ref, name) - if refValue != None and self._nameToElement[name] != getattr(ref, name): + if refValue is not None and self._nameToElement[name] != getattr(ref, name): return False return True @@ -78,7 +78,7 @@ def __str__(self): biggerName = len(n) for name in self._nameToElement: e = self._nameToElement[name] - buffer += "%s %s: 0x%x\n" % (name, " "*(biggerName-len(name)), 0 if e == None else e) + buffer += "%s %s: 0x%x\n" % (name, " "*(biggerName-len(name)), 0 if e is None else e) return buffer # Transaction = type('Transaction', (object,), {}) @@ -104,12 +104,12 @@ def stim(self): for i in range(nextDelay): yield RisingEdge(self.clk) - if self.transactor != None and (int(stream.valid) == 0 or int(stream.ready) == 1): + if self.transactor is not None and (int(stream.valid) == 0 or int(stream.ready) == 1): if isinstance(self.transactor, types.GeneratorType): trans = next(self.transactor) else: trans = self.transactor() - if trans != None: + if trans is not None: if hasattr(trans, "nextDelay"): nextDelay = trans.nextDelay else: From 4edbbd07ab3f8bcd88406d24c4da7d8949cc93e3 Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 17:31:23 +0100 Subject: [PATCH 47/69] ClockDomain.py: stray trailing semicolon --- ClockDomain.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ClockDomain.py b/ClockDomain.py index 642adec..40de90c 100644 --- a/ClockDomain.py +++ b/ClockDomain.py @@ -77,7 +77,7 @@ def _waitEndReset(self): valueReset = int(1 if self.typeReset == RESET_ACTIVE_LEVEL.LOW else 0) if int(self.reset) == valueReset: self.event_endReset.set() - break; + break ########################################################################## # Display the frequency of the clock domain From 9f8c616281abf1a120cb68b5b358976bf0b7e5cb Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 17:34:13 +0100 Subject: [PATCH 48/69] Apb3.py: equality operator with True|False --- Apb3.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Apb3.py b/Apb3.py index f129121..d49dc4b 100644 --- a/Apb3.py +++ b/Apb3.py @@ -36,7 +36,7 @@ def write(self, address, data, sel=1): self.PWDATA.value = data yield RisingEdge(self.clk) self.PENABLE.value = True - yield waitClockedCond(self.clk, lambda: self.PREADY == True) + yield waitClockedCond(self.clk, lambda: self.PREADY.value == 1) randSignal(self.PADDR) self.PSEL.value = 0 randSignal(self.PENABLE) @@ -58,7 +58,7 @@ def read(self, address, sel=1): randSignal(self.PWDATA) yield RisingEdge(self.clk) self.PENABLE.value = True - yield waitClockedCond(self.clk, lambda: self.PREADY == True) + yield waitClockedCond(self.clk, lambda: self.PREADY.value == 1) randSignal(self.PADDR) self.PSEL.value = 0 randSignal(self.PENABLE) From cdf8ad5b1c09201a1c26969f57bdb51807cb02e5 Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 17:36:42 +0100 Subject: [PATCH 49/69] Stream.py: equality operator with True|False --- Stream.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Stream.py b/Stream.py index 9e18c15..32ea30a 100644 --- a/Stream.py +++ b/Stream.py @@ -117,7 +117,7 @@ def stim(self): stream.valid.value = 1 for name in stream.payload.nameToElement: - if hasattr(trans, name) == False: + if hasattr(trans, name) is False: raise Exception("Missing element in bundle :" + name) e = stream.payload.nameToElement[name].value = getattr(trans, name) From 2ec3e91a5b61ff33ccdeaea5502d65b1f77734ac Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 17:37:45 +0100 Subject: [PATCH 50/69] misc.py equality operator with True|False --- misc.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/misc.py b/misc.py index 6d923c3..4d15398 100644 --- a/misc.py +++ b/misc.py @@ -46,7 +46,7 @@ def randBoolSignal(that, prob): def clockedWaitTrue(clk, that): while True: yield RisingEdge(clk) - if that == True: + if that is True: break From 26ccddce87ecd99cf9630859e6ed633b50191a88 Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 17:39:34 +0100 Subject: [PATCH 51/69] Axi4.py: use of built-in as local variable len|min|max --- Axi4.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Axi4.py b/Axi4.py index 58f6f70..608725b 100644 --- a/Axi4.py +++ b/Axi4.py @@ -37,13 +37,13 @@ def __init__(self, dut, name): self.b = Stream(dut, name + "_b") -def Axi4AddrIncr(address, burst, len, size): +def Axi4AddrIncr(address, burst, length, size): if burst == 0: return address if burst == 1: return address + (1 << size) if burst == 2: - burstSize = (1 << size) * (len+1) + burstSize = (1 << size) * (length+1) burstMask = burstSize-1 base = (address + (1 << size)) & burstMask return (address & ~burstMask) | base From 400c1cd50bcbe49d56237f530e5207a5fce1a791 Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 17:41:44 +0100 Subject: [PATCH 52/69] misc.py: use of built-in as local variable len|min|max --- misc.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/misc.py b/misc.py index 4d15398..1bcfd0b 100644 --- a/misc.py +++ b/misc.py @@ -22,8 +22,8 @@ def log2Up(value): return value.bit_length()-1 -def randInt(min, max): - return random.randint(min, max) +def randInt(lower, upper): + return random.randint(lower, upper) def randBool(): From 9283fcf778942308f77b8eed170c1039166d5486 Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 17:42:48 +0100 Subject: [PATCH 53/69] misc.py: Move import declaration to top of file --- misc.py | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/misc.py b/misc.py index 1bcfd0b..81b183a 100644 --- a/misc.py +++ b/misc.py @@ -1,4 +1,5 @@ import random +import time import cocotb from cocotb.binary import BinaryValue @@ -116,9 +117,6 @@ def SimulationTimeout(duration): raise TestFailure("Simulation timeout") -import time - - @coroutine def simulationSpeedPrinter(clk): counter = 0 From 0d4ed52ee261d1d7c249300cfb842101f2ea3391 Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 17:45:05 +0100 Subject: [PATCH 54/69] AhbLite3.py: black --line-length 136 changes --- AhbLite3.py | 40 +++++++++++++++++++++++----------------- 1 file changed, 23 insertions(+), 17 deletions(-) diff --git a/AhbLite3.py b/AhbLite3.py index 0d7c100..150ae32 100644 --- a/AhbLite3.py +++ b/AhbLite3.py @@ -37,21 +37,23 @@ def __init__(self, addressWidth, dataWidth): self.dataWidth = dataWidth def genRandomAddress(self): - return random.randint(0, (1 << self.addressWidth)-1) + return random.randint(0, (1 << self.addressWidth) - 1) def getTransactions(self): if random.random() < 0.8: trans = AhbLite3Transaction() return [trans] else: - OneKiB = 1 << 10 # this pesky 1 KiB wall a burst must not cross - hSize = random.randint(0, log2Up(self.dataWidth//8)) + OneKiB = 1 << 10 # this pesky 1 KiB wall a burst must not cross + hSize = random.randint(0, log2Up(self.dataWidth // 8)) bytesPerBeat = 1 << hSize - maxBurst = 5 if hSize == 7 else 7 # a full-width 1024 bit bus can only burst up to 8 beats for not crossing a 1 KiB boundary + maxBurst = ( + 5 if hSize == 7 else 7 + ) # a full-width 1024 bit bus can only burst up to 8 beats for not crossing a 1 KiB boundary burst = random.randint(0, maxBurst) write = random.random() < 0.5 prot = random.randint(0, 15) - address = self.genRandomAddress() & ~(bytesPerBeat-1) + address = self.genRandomAddress() & ~(bytesPerBeat - 1) incrUnspecified = burst == 1 incrFixed = burst != 1 and burst & 1 == 1 @@ -64,7 +66,7 @@ def getTransactions(self): burstCase = burst >> 1 burstBeats = [1, 4, 8, 16][burstCase] - burstBytes = bytesPerBeat*burstBeats + burstBytes = bytesPerBeat * burstBeats while incrFixed and ((address % OneKiB) + burstBytes) > OneKiB: address = address - bytesPerBeat @@ -75,7 +77,7 @@ def getTransactions(self): for beat in range(burstBeats): if beat > 0: busyProp = random.random() - 0.8 - for busyBeat in range(int(busyProp/0.05)): + for busyBeat in range(int(busyProp / 0.05)): trans = AhbLite3Transaction() trans.HWRITE = write trans.HSIZE = hSize @@ -83,7 +85,7 @@ def getTransactions(self): trans.HPROT = prot trans.HADDR = address trans.HTRANS = 1 # BUSY - trans.HWDATA = random.randint(0, (1 << self.dataWidth)-1) + trans.HWDATA = random.randint(0, (1 << self.dataWidth) - 1) buffer.append(trans) trans = AhbLite3Transaction() trans.HWRITE = write @@ -92,7 +94,7 @@ def getTransactions(self): trans.HPROT = prot trans.HADDR = address trans.HTRANS = 2 if beat == 0 else 3 # first beat is NONSEQ, others are SEQ - trans.HWDATA = random.randint(0, (1 << self.dataWidth)-1) + trans.HWDATA = random.randint(0, (1 << self.dataWidth) - 1) address += bytesPerBeat if wrapFixed and (address == addressBase + burstBytes): address = addressBase @@ -163,7 +165,7 @@ def combEvent(self): self.doComb() def doComb(self): - self.ahb.HREADY.value = (self.randomHREADY and (int(self.ahb.HREADYOUT) == 1)) + self.ahb.HREADY.value = self.randomHREADY and (int(self.ahb.HREADYOUT) == 1) class AhbLite3MasterReadChecker: @@ -187,8 +189,12 @@ def stim(self): raise TestFailure("Empty buffer ??? ") bufferData = self.buffer.get() - for i in range(byteOffset,byteOffset + size): - assertEquals((int(ahb.HRDATA) >> (i*8)) & 0xFF, (bufferData >> (i*8)) & 0xFF, "AHB master read checker faild %x " % (int(ahb.HADDR))) + for i in range(byteOffset, byteOffset + size): + assertEquals( + (int(ahb.HRDATA) >> (i * 8)) & 0xFF, + (bufferData >> (i * 8)) & 0xFF, + "AHB master read checker faild %x " % (int(ahb.HADDR)), + ) self.counter += 1 # cocotb._log.info("POP " + str(self.buffer.qsize())) @@ -205,7 +211,7 @@ def __init__(self, ahb, base, size, clk, reset): self.reset = reset self.base = base self.size = size - self.ram = bytearray(b'\x00' * size) + self.ram = bytearray(b"\x00" * size) cocotb.start_soon(self.stim()) cocotb.start_soon(self.stimReady()) @@ -224,7 +230,7 @@ def stimReady(self): if (busy or busyNew) and int(self.ahb.HREADYOUT) == 0 and int(self.ahb.HREADY) == 1: raise TestFailure("HREADYOUT == 0 but HREADY == 1 ??? " + self.ahb.HREADY._name) busy = busyNew - if (busy): + if busy: self.ahb.HREADYOUT.value = randomizer.get() # make some random delay for NONSEQ and SEQ requests else: self.ahb.HREADYOUT.value = 1 # IDLE and BUSY require 0 WS @@ -245,7 +251,7 @@ def stim(self): if trans >= 2: if write == 1: for idx in range(size): - self.ram[address-self.base + idx] = (int(ahb.HWDATA) >> (8*(addressOffset + idx))) & 0xFF + self.ram[address - self.base + idx] = (int(ahb.HWDATA) >> (8 * (addressOffset + idx))) & 0xFF # print("write %x with %x" % (address + idx,(int(ahb.HWDATA) >> (8*(addressOffset + idx))) & 0xFF)) valid = int(ahb.HSEL) @@ -253,7 +259,7 @@ def stim(self): write = int(ahb.HWRITE) size = 1 << int(ahb.HSIZE) address = int(ahb.HADDR) - addressOffset = address % (len(ahb.HWDATA)//8) + addressOffset = address % (len(ahb.HWDATA) // 8) ahb.HRDATA.value = 0 if valid == 1: @@ -261,7 +267,7 @@ def stim(self): if write == 0: data = 0 for idx in range(size): - data |= self.ram[address-self.base + idx] << (8*(addressOffset + idx)) + data |= self.ram[address - self.base + idx] << (8 * (addressOffset + idx)) # print("read %x with %x" % (address + idx, self.ram[address-self.base + idx])) # print(str(data)) ahb.HRDATA.value = int(data) From b73ee46bafd6ca18db65b80064fd61a7dc11f808 Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 17:45:24 +0100 Subject: [PATCH 55/69] Axi4.py: black --line-length 136 changes --- Axi4.py | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/Axi4.py b/Axi4.py index 608725b..357c628 100644 --- a/Axi4.py +++ b/Axi4.py @@ -43,8 +43,8 @@ def Axi4AddrIncr(address, burst, length, size): if burst == 1: return address + (1 << size) if burst == 2: - burstSize = (1 << size) * (length+1) - burstMask = burstSize-1 + burstSize = (1 << size) * (length + 1) + burstMask = burstSize - 1 base = (address + (1 << size)) & burstMask return (address & ~burstMask) | base @@ -55,7 +55,7 @@ def __init__(self, name, parent, axi, addressWidth, clk, reset): self.axi = axi self.idWidth = len(axi.arw.payload.hid) self.addressWidth = addressWidth - self.ram = bytearray(b'\x00' * ((1 << addressWidth)*len(axi.w.payload.data)//8)) + self.ram = bytearray(b"\x00" * ((1 << addressWidth) * len(axi.w.payload.data) // 8)) self.doReadWriteCmdRand = BoolRandomizer() self.readWriteRand = BoolRandomizer() self.writeDataRand = BoolRandomizer() @@ -95,10 +95,10 @@ def genNewCmd(self): cmd.hid = randBits(self.idWidth) # Each master can use 4 id cmd.region = randBits(4) cmd.len = randBits(4) - cmd.size = random.randint(0, log2Up(self.dataWidth//8)) + cmd.size = random.randint(0, log2Up(self.dataWidth // 8)) cmd.burst = random.randint(0, 2) if cmd.burst == 2: - cmd.len = random.choice([2, 4, 8, 16])-1 + cmd.len = random.choice([2, 4, 8, 16]) - 1 else: cmd.len = randBits(4) + (16 if random.random() < 0.1 else 0) + (32 if random.random() < 0.02 else 0) cmd.lock = randBits(1) @@ -106,9 +106,9 @@ def genNewCmd(self): cmd.qos = randBits(4) cmd.prot = randBits(3) - byteCount = (1 << cmd.size)*(cmd.len + 1) - while(True): - cmd.addr = self.genRandomeAddress() & ~((1 << cmd.size)-1) + byteCount = (1 << cmd.size) * (cmd.len + 1) + while True: + cmd.addr = self.genRandomeAddress() & ~((1 << cmd.size) - 1) if cmd.burst == 1: if cmd.addr + byteCount >= (1 << self.addressWidth): continue @@ -121,7 +121,7 @@ def genNewCmd(self): end = start + byteCount if cmd.burst == 2: - start = cmd.addr & ~(byteCount-1) + start = cmd.addr & ~(byteCount - 1) end = start + byteCount if self.isAddressRangeBusy(start, end): @@ -131,16 +131,16 @@ def genNewCmd(self): if self.readWriteRand.get(): cmd.write = 1 beatAddr = cmd.addr - for i in range(cmd.len+1): + for i in range(cmd.len + 1): dataTrans = Transaction() dataTrans.data = randBits(self.dataWidth) - dataTrans.strb = randBits(self.dataWidth//8) + dataTrans.strb = randBits(self.dataWidth // 8) dataTrans.last = 1 if cmd.len == i else 0 self.writeTasks.put(dataTrans) - for s in range(self.dataWidth//8): + for s in range(self.dataWidth // 8): if (dataTrans.strb >> s) & 1 == 1: - self.ram[(beatAddr & ~(self.dataWidth//8-1)) + s] = (dataTrans.data >> (s*8)) & 0xFF + self.ram[(beatAddr & ~(self.dataWidth // 8 - 1)) + s] = (dataTrans.data >> (s * 8)) & 0xFF beatAddr = Axi4AddrIncr(beatAddr, cmd.burst, cmd.len, cmd.size) writeRsp = Transaction() @@ -155,10 +155,10 @@ def genNewCmd(self): beatAddr = cmd.addr for s in range(cmd.len + 1): readRsp = Transaction() - addrBase = beatAddr & ~(self.dataWidth//8-1) + addrBase = beatAddr & ~(self.dataWidth // 8 - 1) readRsp.data = 0 for i in range(self.dataWidth // 8): - readRsp.data |= self.ram[addrBase + i] << (i*8) + readRsp.data |= self.ram[addrBase + i] << (i * 8) readRsp.resp = 0 readRsp.last = 1 if cmd.len == s else 0 readRsp.hid = cmd.hid From 42bd6418f61f241b1b660feb5b3bb06e7b744043 Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 17:48:06 +0100 Subject: [PATCH 56/69] Spi.py: black --line-length 136 changes --- Spi.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/Spi.py b/Spi.py index 1ca13f8..bde714e 100644 --- a/Spi.py +++ b/Spi.py @@ -60,16 +60,16 @@ def exchange(self, masterData): self.spi.mosi.value = testBit(masterData, self.dataWidth - 1 - i) yield Timer(self.baudPeriode >> 1) buffer = buffer + str(self.spi.miso.write) if bool(self.spi.miso.writeEnable) else "x" - self.spi.sclk.value = (not self.cpol) + self.spi.sclk.value = not self.cpol yield Timer(self.baudPeriode >> 1) - self.spi.sclk.value = (self.cpol) + self.spi.sclk.value = self.cpol else: for i in range(self.dataWidth): self.spi.mosi.value = testBit(masterData, self.dataWidth - 1 - i) - self.spi.sclk.value = (not self.cpol) + self.spi.sclk.value = not self.cpol yield Timer(self.baudPeriode >> 1) buffer = buffer + str(self.spi.miso.write) if bool(self.spi.miso.writeEnable) else "x" - self.spi.sclk.value = (self.cpol) + self.spi.sclk.value = self.cpol yield Timer(self.baudPeriode >> 1) raise ReturnValue(buffer) From c15b9b3a1356634a8ee41bacc20553dd6e60f711 Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 17:50:10 +0100 Subject: [PATCH 57/69] Stream.py: black --line-length 136 changes --- Stream.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Stream.py b/Stream.py index 32ea30a..51404ee 100644 --- a/Stream.py +++ b/Stream.py @@ -1,4 +1,3 @@ - import types import cocotb @@ -53,7 +52,7 @@ def __init__(self): def __setattr__(self, key, value): # print("set " + key) - if key[0] != '_': + if key[0] != "_": self._nameToElement[key] = value object.__setattr__(self, key, value) @@ -78,9 +77,10 @@ def __str__(self): biggerName = len(n) for name in self._nameToElement: e = self._nameToElement[name] - buffer += "%s %s: 0x%x\n" % (name, " "*(biggerName-len(name)), 0 if e is None else e) + buffer += "%s %s: 0x%x\n" % (name, " " * (biggerName - len(name)), 0 if e is None else e) return buffer + # Transaction = type('Transaction', (object,), {}) From 05b83e0eafd763a9659068c50045d46ccbbc172c Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 17:51:44 +0100 Subject: [PATCH 58/69] misc.py: black --line-length 136 changes --- misc.py | 40 +++++++++++++++++++++------------------- 1 file changed, 21 insertions(+), 19 deletions(-) diff --git a/misc.py b/misc.py index 81b183a..97c539f 100644 --- a/misc.py +++ b/misc.py @@ -20,7 +20,7 @@ def cocotbXHack(): def log2Up(value): - return value.bit_length()-1 + return value.bit_length() - 1 def randInt(lower, upper): @@ -40,7 +40,7 @@ def randSignal(that): def randBoolSignal(that, prob): - that.value = (random.random() < prob) + that.value = random.random() < prob @coroutine @@ -58,7 +58,7 @@ def assertEquals(a, b, name): def truncUInt(value, signal): if isinstance(signal, int): - return value & ((1 << signal)-1) + return value & ((1 << signal) - 1) else: return value & ((1 << len(signal)) - 1) @@ -68,9 +68,9 @@ def truncSInt(value, signal): bitCount = signal else: bitCount = len(signal) - masked = value & ((1 << bitCount)-1) - if (masked & (1 << bitCount-1)) != 0: - return - (1 << bitCount) + masked + masked = value & ((1 << bitCount) - 1) + if (masked & (1 << bitCount - 1)) != 0: + return -(1 << bitCount) + masked else: return masked @@ -106,9 +106,9 @@ def ClockDomainAsyncReset(clk, reset, period=1000): reset.value = 0 while True: clk.value = 0 - yield Timer(period/2) + yield Timer(period / 2) clk.value = 1 - yield Timer(period/2) + yield Timer(period / 2) @coroutine @@ -127,7 +127,7 @@ def simulationSpeedPrinter(clk): thisTime = time.time() if thisTime - lastTime >= 1.0: lastTime = thisTime - print("Sim speed : %f khz" % (counter/1000.0)) + print("Sim speed : %f khz" % (counter / 1000.0)) counter = 0 @@ -155,7 +155,7 @@ def get(self): # self.payload = payloads[0] -MyObject = type('MyObject', (object,), {}) +MyObject = type("MyObject", (object,), {}) @coroutine @@ -182,7 +182,7 @@ def StreamRandomizer(streamName, onNew, handle, dut, clk): else: payload = MyObject() for e in payloads: - payload.__setattr__(e._name[len(streamName + "_payload_"):], int(e)) + payload.__setattr__(e._name[len(streamName + "_payload_") :], int(e)) if onNew: onNew(payload, handle) @@ -206,7 +206,7 @@ def FlowRandomizer(streamName, onNew, handle, dut, clk): else: payload = MyObject() for e in payloads: - payload.__setattr__(e._name[len(streamName + "_payload_"):], int(e)) + payload.__setattr__(e._name[len(streamName + "_payload_") :], int(e)) if onNew: onNew(payload, handle) else: @@ -230,7 +230,7 @@ def StreamReader(streamName, onTransaction, handle, dut, clk): else: payload = MyObject() for e in payloads: - payload.__setattr__(e._name[len(streamName + "_payload_"):], int(e)) + payload.__setattr__(e._name[len(streamName + "_payload_") :], int(e)) if onTransaction: onTransaction(payload, handle) @@ -239,7 +239,9 @@ def StreamReader(streamName, onTransaction, handle, dut, clk): class Bundle: def __init__(self, dut, name): self.nameToElement = {} - self.elements = [a for a in dut if (a._name.lower().startswith(name.lower() + "_") and not a._name.lower().endswith("_readablebuffer"))] + self.elements = [ + a for a in dut if (a._name.lower().startswith(name.lower() + "_") and not a._name.lower().endswith("_readablebuffer")) + ] for e in [a for a in dut if a._name == name]: self.elements.append(e) @@ -249,7 +251,7 @@ def __init__(self, dut, name): if len(name) == len(element._name): eName = "itself" else: - eName = element._name[len(name) + 1:] + eName = element._name[len(name) + 1 :] if eName == "id": eName = "hid" @@ -267,12 +269,12 @@ def readIHex(path, callback, context): offset = 0 for line in f: if len(line) > 0: - assert line[0] == ':' + assert line[0] == ":" byteCount = int(line[1:3], 16) nextAddr = int(line[3:7], 16) + offset key = int(line[7:9], 16) if key == 0: - array = [int(line[9 + i * 2:11 + i * 2], 16) for i in range(0, byteCount)] + array = [int(line[9 + i * 2 : 11 + i * 2], 16) for i in range(0, byteCount)] callback(nextAddr, array, context) elif key == 2: offset = int(line[9:13], 16) @@ -282,7 +284,7 @@ def readIHex(path, callback, context): @coroutine def TriggerAndCond(trigger, cond): - while(True): + while True: yield trigger if cond: break @@ -290,7 +292,7 @@ def TriggerAndCond(trigger, cond): @coroutine def waitClockedCond(clk, cond): - while(True): + while True: yield RisingEdge(clk) if cond(): break From 6ed3bb433c283ccee67372e645d1237e3b7014dd Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 17:53:35 +0100 Subject: [PATCH 59/69] Apb3.py: flake8 --max-line-length 136 changes --- Apb3.py | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/Apb3.py b/Apb3.py index d49dc4b..fe70130 100644 --- a/Apb3.py +++ b/Apb3.py @@ -1,11 +1,8 @@ -import random - -import cocotb -from cocotb.result import TestFailure, ReturnValue -from cocotb.triggers import RisingEdge, Edge +from cocotb.result import ReturnValue +from cocotb.triggers import RisingEdge from cocotb.decorators import coroutine -from .misc import log2Up, BoolRandomizer, assertEquals, waitClockedCond, randSignal +from .misc import assertEquals, waitClockedCond, randSignal class Apb3: From 4ad063adc01125393cf254d3828eaad8aa5fcd76 Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 17:56:10 +0100 Subject: [PATCH 60/69] Phase.py: flake8 --max-line-length 136 changes --- Phase.py | 2 -- 1 file changed, 2 deletions(-) diff --git a/Phase.py b/Phase.py index 0128fab..f079182 100644 --- a/Phase.py +++ b/Phase.py @@ -1,5 +1,3 @@ -import cocotb -from cocotb.result import TestFailure, TestError from cocotb.triggers import Timer from cocotb.decorators import coroutine From d599f54afdd039927434d01dd2b5cbcea0fd1775 Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 17:58:06 +0100 Subject: [PATCH 61/69] Scorboard.py: flake8 --max-line-length 136 changes --- Scorboard.py | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/Scorboard.py b/Scorboard.py index 01e58c7..fdaa27b 100644 --- a/Scorboard.py +++ b/Scorboard.py @@ -96,8 +96,8 @@ def update(self, oooid): def match(self, uut, ref): equal = uut.equalRef(ref) - for l in self.listeners: - l(uut, ref, equal) + for handler in self.listeners: + handler(uut, ref, equal) if not equal: cocotb._log.error("Missmatch detected in " + self.getPath()) @@ -108,12 +108,12 @@ def startPhase(self, phase): if phase == PHASE_CHECK_SCORBOARDS: if len(self.refsDic) != 0 or len(self.uutsDic) != 0: error = self.getPath() + " has some remaining transaction :\n" - for l in self.refsDic.values(): - for e in l.queue: + for it in self.refsDic.values(): + for e in it.queue: error += "REF:\n" + str(e) + "\n" - for l in self.uutsDic.values(): - for e in l.queue: + for it in self.uutsDic.values(): + for e in it.queue: error += "UUT:\n" + str(e) + "\n" cocotb._log.error(error) From b57de3ab577a45fcbbcbc32b0efcbfb29ef63428 Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 18:00:22 +0100 Subject: [PATCH 62/69] Spi.py: flake8 --max-line-length 136 changes --- Spi.py | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/Spi.py b/Spi.py index bde714e..667af91 100644 --- a/Spi.py +++ b/Spi.py @@ -1,12 +1,9 @@ -import random - -import cocotb -from cocotb.result import TestFailure, ReturnValue -from cocotb.triggers import RisingEdge, Edge, Timer +from cocotb.result import ReturnValue +from cocotb.triggers import Timer from cocotb.decorators import coroutine from .TriState import TriStateOutput -from .misc import log2Up, BoolRandomizer, assertEquals, testBit +from .misc import testBit class SpiMaster: From a09524487aa646d9cf214bff2993bd647b38ceca Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 18:01:29 +0100 Subject: [PATCH 63/69] misc.py: flake8 --max-line-length 136 changes --- misc.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/misc.py b/misc.py index 97c539f..3529531 100644 --- a/misc.py +++ b/misc.py @@ -247,7 +247,7 @@ def __init__(self, dut, name): self.elements.append(e) for element in self.elements: - # print("append " + element._name + " with name : " + element._name[len(name) + 1:]) + # print("append " + element._name + " with name : " + element._name[len(name) + 1 :]) if len(name) == len(element._name): eName = "itself" else: From ef117690b075f178dbc0407bbce221e24f439ee8 Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 18:04:20 +0100 Subject: [PATCH 64/69] Stream.py: nextDelay never assigned initial value --- Stream.py | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/Stream.py b/Stream.py index 51404ee..93f1d1f 100644 --- a/Stream.py +++ b/Stream.py @@ -97,11 +97,12 @@ def __init__(self, stream, transactor, clk, reset): def stim(self): stream = self.stream stream.valid.value = 0 + next_delay = 0 while True: yield RisingEdge(self.clk) if int(stream.valid) == 1 and int(stream.ready) == 1: stream.valid.value = 0 - for i in range(nextDelay): + for i in range(next_delay): yield RisingEdge(self.clk) if self.transactor is not None and (int(stream.valid) == 0 or int(stream.ready) == 1): @@ -111,9 +112,9 @@ def stim(self): trans = self.transactor() if trans is not None: if hasattr(trans, "nextDelay"): - nextDelay = trans.nextDelay + next_delay = trans.nextDelay else: - nextDelay = 0 + next_delay = 0 stream.valid.value = 1 for name in stream.payload.nameToElement: From f2e316b80ee168b98b6f989209f9f7660b70de86 Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 18:05:50 +0100 Subject: [PATCH 65/69] Stream.py: local variable 'e' is assigned to but never used --- Stream.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Stream.py b/Stream.py index 93f1d1f..827413b 100644 --- a/Stream.py +++ b/Stream.py @@ -120,7 +120,7 @@ def stim(self): for name in stream.payload.nameToElement: if hasattr(trans, name) is False: raise Exception("Missing element in bundle :" + name) - e = stream.payload.nameToElement[name].value = getattr(trans, name) + stream.payload.nameToElement[name].value = getattr(trans, name) class StreamDriverSlave: From 5508e4e05ede696d41a1eff059a7bacab41c24d3 Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 18:08:25 +0100 Subject: [PATCH 66/69] AhbLite3.py: flake8 --max-line-length 136 code-changes --- AhbLite3.py | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/AhbLite3.py b/AhbLite3.py index 150ae32..1e64644 100644 --- a/AhbLite3.py +++ b/AhbLite3.py @@ -180,6 +180,8 @@ def __init__(self, ahb, buffer, clk, reset): @coroutine def stim(self): ahb = self.ahb + size = 0 + byteOffset = 0 readIncoming = False while True: yield RisingEdge(self.clk) @@ -241,6 +243,11 @@ def stim(self): ahb.HREADYOUT.value = 1 ahb.HRESP.value = 0 ahb.HRDATA.value = 0 + addressOffset = 0 + address = 0 + trans = 0 + size = 0 + write = 0 valid = 0 while True: yield RisingEdge(self.clk) From ce1b7d0cc73ebde28509fcb1617133d56ca09b41 Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 18:09:39 +0100 Subject: [PATCH 67/69] Phase.py: flake8 --max-line-length 136 code-changes --- Phase.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Phase.py b/Phase.py index f079182..7b4b964 100644 --- a/Phase.py +++ b/Phase.py @@ -15,12 +15,13 @@ def __init__(self, name, parent): if parent is not None: parent.addChild(self) self.children = [] + self.error = False def getPhase(self): return self.parent.getPhase() def startPhase(self, phase): - error = False + self.error = False for child in self.children: child.startPhase(phase) From 328df3f8d9bdf0bec6bb4958efc89ad1f3116746 Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 18:11:27 +0100 Subject: [PATCH 68/69] .github/workflows/lint.yml: added file requirements_lint.txt added for this task --- .github/workflows/lint.yaml | 35 +++++++++++++++++++++++++++++++++++ requirements_lint.txt | 3 +++ 2 files changed, 38 insertions(+) create mode 100644 .github/workflows/lint.yaml create mode 100644 requirements_lint.txt diff --git a/.github/workflows/lint.yaml b/.github/workflows/lint.yaml new file mode 100644 index 0000000..2cf7139 --- /dev/null +++ b/.github/workflows/lint.yaml @@ -0,0 +1,35 @@ +name: lint +on: + # Runs on all pushes to branches + push: + # Runs on all PRs + pull_request: + # Manual Dispatch + workflow_dispatch: + +jobs: + lint_python: + name: Lint Python Code + runs-on: ubuntu-latest + + env: + BLACK_OPTS: --line-length 136 + # E203 difference of opinion between black and flake8 + # E203 whitespace before ':' + FLAKE8_OPTS: --max-line-length 136 --ignore=E203 + + steps: + - name: Checkout + uses: actions/checkout@main + + - name: Install Linters + run: python3 -m pip install -r ./requirements_lint.txt + + - name: Ensure Black Formatting + run: black --diff --color $BLACK_OPTS . + + - name: Ensure Black Formatting + run: black --check $BLACK_OPTS . + + - name: Lint with Flake8 + run: flake8 $FLAKE8_OPTS --exclude venv . diff --git a/requirements_lint.txt b/requirements_lint.txt new file mode 100644 index 0000000..c49ca57 --- /dev/null +++ b/requirements_lint.txt @@ -0,0 +1,3 @@ +black~=22.3.0 +flake8~=4.0.1 +flake8-no-implicit-concat==0.3.3 From 5397af98bc2b3847dc9561ef265426948c1ec241 Mon Sep 17 00:00:00 2001 From: "Darryl L. Miles" Date: Mon, 15 May 2023 18:13:46 +0100 Subject: [PATCH 69/69] ClockDomain.py: compute self.frequency for __str__ --- ClockDomain.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/ClockDomain.py b/ClockDomain.py index 40de90c..c7f2532 100644 --- a/ClockDomain.py +++ b/ClockDomain.py @@ -1,6 +1,7 @@ import cocotb from cocotb.triggers import Timer, RisingEdge, Event from cocotb.decorators import coroutine +from cocotb.utils import get_time_from_sim_steps ############################################################################### @@ -30,6 +31,7 @@ class ClockDomain: # @param resetactiveLevel : Reset active low or high def __init__(self, clk, halfPeriod, reset=None, resetActiveLevel=RESET_ACTIVE_LEVEL.LOW): self.halfPeriod = halfPeriod + self.frequency = 1 / get_time_from_sim_steps(halfPeriod * 2, units="us") self.clk = clk self.reset = reset