From 88ed3c0a65d15d2c8d7b23b8b65892ad35b28624 Mon Sep 17 00:00:00 2001 From: mikee47 Date: Sun, 23 Jun 2024 11:22:32 +0100 Subject: [PATCH 01/10] Added code that allows programatical control over the initial physical parameters data. That option can be enabled with ENABLE_CUSTOM_PHY=1. --- .../Esp8266/Components/esp8266/component.mk | 9 + .../Esp8266/Components/esp8266/esp8266_phy.c | 268 ++++++++++++++++++ .../Esp8266/Components/sming-arch/README.rst | 3 + 3 files changed, 280 insertions(+) create mode 100644 Sming/Arch/Esp8266/Components/esp8266/esp8266_phy.c diff --git a/Sming/Arch/Esp8266/Components/esp8266/component.mk b/Sming/Arch/Esp8266/Components/esp8266/component.mk index a62bfe2fef..7a141bb6e3 100644 --- a/Sming/Arch/Esp8266/Components/esp8266/component.mk +++ b/Sming/Arch/Esp8266/Components/esp8266/component.mk @@ -13,6 +13,15 @@ ifeq ($(DISABLE_WIFI),1) COMPONENT_DEPENDS += esp-lwip endif + +COMPONENT_VARS += ENABLE_CUSTOM_PHY +ENABLE_CUSTOM_PHY ?= 0 +ifeq ($(ENABLE_CUSTOM_PHY),1) + CFLAGS += -DENABLE_CUSTOM_PHY=1 + LDFLAGS += -Wl,-wrap,register_chipv6_phy -u custom_register_chipv6_phy -u get_adc_mode +endif + + $(FLASH_INIT_DATA): $(SDK_BASE)/.submodule $(Q) cp -f $(@D)/esp_init_data_default_v08.bin $@ diff --git a/Sming/Arch/Esp8266/Components/esp8266/esp8266_phy.c b/Sming/Arch/Esp8266/Components/esp8266/esp8266_phy.c new file mode 100644 index 0000000000..697c04b970 --- /dev/null +++ b/Sming/Arch/Esp8266/Components/esp8266/esp8266_phy.c @@ -0,0 +1,268 @@ +/* + Adapted from Arduino for Sming. + Original copyright note is kept below. + + phy.c - ESP8266 PHY initialization data + Copyright (c) 2015 Ivan Grokhotkov. All rights reserved. + This file is part of the esp8266 core for Arduino environment. + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifdef ENABLE_CUSTOM_PHY + +#include + +#ifndef F_CRYSTAL +#define F_CRYSTAL 40000000 +#endif + +static const uint8_t ICACHE_FLASH_ATTR phyInitData[128] = +{ + [0] = 5, // Reserved, do not change + [1] = 8, // Reserved, do not change + [2] = 4, // Reserved, do not change + [3] = 2, // Reserved, do not change + [4] = 5, // Reserved, do not change + [5] = 5, // Reserved, do not change + [6] = 5, // Reserved, do not change + [7] = 2, // Reserved, do not change + [8] = 5, // Reserved, do not change + [9] = 0, // Reserved, do not change + [10] = 4, // Reserved, do not change + [11] = 5, // Reserved, do not change + [12] = 5, // Reserved, do not change + [13] = 4, // Reserved, do not change + [14] = 5, // Reserved, do not change + [15] = 5, // Reserved, do not change + [16] = 4, // Reserved, do not change + [17] = -2, // Reserved, do not change + [18] = -3, // Reserved, do not change + [19] = -1, // Reserved, do not change + [20] = -16, // Reserved, do not change + [21] = -16, // Reserved, do not change + [22] = -16, // Reserved, do not change + [23] = -32, // Reserved, do not change + [24] = -32, // Reserved, do not change + [25] = -32, // Reserved, do not change + + [26] = 225, // spur_freq_cfg, spur_freq=spur_freq_cfg/spur_freq_cfg_div + [27] = 10, // spur_freq_cfg_div + // each bit for 1 channel, 1 to select the spur_freq if in band, else 40 + [28] = 0xff, // spur_freq_en_h + [29] = 0xff, // spur_freq_en_l + + [30] = 0xf8, // Reserved, do not change + [31] = 0, // Reserved, do not change + [32] = 0xf8, // Reserved, do not change + [33] = 0xf8, // Reserved, do not change + + [34] = 78, // target_power_qdb_0, target power is 78/4=19.5dbm + [35] = 74, // target_power_qdb_1, target power is 74/4=18.5dbm + [36] = 70, // target_power_qdb_2, target power is 70/4=17.5dbm + [37] = 64, // target_power_qdb_3, target power is 64/4=16dbm + [38] = 60, // target_power_qdb_4, target power is 60/4=15dbm + [39] = 56, // target_power_qdb_5, target power is 56/4=14dbm + + [40] = 0, // target_power_index_mcs0 + [41] = 0, // target_power_index_mcs1 + [42] = 1, // target_power_index_mcs2 + [43] = 1, // target_power_index_mcs3 + [44] = 2, // target_power_index_mcs4 + [45] = 3, // target_power_index_mcs5 + [46] = 4, // target_power_index_mcs6 + [47] = 5, // target_power_index_mcs7 + + // crystal_26m_en + // 0: 40MHz + // 1: 26MHz + // 2: 24MHz + #if F_CRYSTAL == 40000000 + [48] = 0, + #else + [48] = 1, + #endif + + // sdio_configure + // 0: Auto by pin strapping + // 1: SDIO dataoutput is at negative edges (SDIO V1.1) + // 2: SDIO dataoutput is at positive edges (SDIO V2.0) + [50] = 0, + + // bt_configure + // 0: None,no bluetooth + // 1: GPIO0 -> WLAN_ACTIVE/ANT_SEL_WIFI + // MTMS -> BT_ACTIVE + // MTCK -> BT_PRIORITY + // U0RXD -> ANT_SEL_BT + // 2: None, have bluetooth + // 3: GPIO0 -> WLAN_ACTIVE/ANT_SEL_WIFI + // MTMS -> BT_PRIORITY + // MTCK -> BT_ACTIVE + // U0RXD -> ANT_SEL_BT + [51] = 0, + + // bt_protocol + // 0: WiFi-BT are not enabled. Antenna is for WiFi + // 1: WiFi-BT are not enabled. Antenna is for BT + // 2: WiFi-BT 2-wire are enabled, (only use BT_ACTIVE), independent ant + // 3: WiFi-BT 3-wire are enabled, (when BT_ACTIVE = 0, BT_PRIORITY must be 0), independent ant + // 4: WiFi-BT 2-wire are enabled, (only use BT_ACTIVE), share ant + // 5: WiFi-BT 3-wire are enabled, (when BT_ACTIVE = 0, BT_PRIORITY must be 0), share ant + [52] = 0, + + // dual_ant_configure + // 0: None + // 1: dual_ant (antenna diversity for WiFi-only): GPIO0 + U0RXD + // 2: T/R switch for External PA/LNA: GPIO0 is high and U0RXD is low during Tx + // 3: T/R switch for External PA/LNA: GPIO0 is low and U0RXD is high during Tx + [53] = 0, + + [54] = 2, // Reserved, do not change + + // share_xtal + // This option is to share crystal clock for BT + // The state of Crystal during sleeping + // 0: Off + // 1: Forcely On + // 2: Automatically On according to XPD_DCDC + // 3: Automatically On according to GPIO2 + [55] = 0, + + [64] = 225, // spur_freq_cfg_2, spur_freq_2=spur_freq_cfg_2/spur_freq_cfg_div_2 + [65] = 10, // spur_freq_cfg_div_2 + [66] = 0, // spur_freq_en_h_2 + [67] = 0, // spur_freq_en_l_2 + [68] = 0, // spur_freq_cfg_msb + [69] = 0, // spur_freq_cfg_2_msb + [70] = 0, // spur_freq_cfg_3_low + [71] = 0, // spur_freq_cfg_3_high + [72] = 0, // spur_freq_cfg_4_low + [73] = 0, // spur_freq_cfg_4_high + + [74] = 1, // Reserved, do not change + [75] = 0x93, // Reserved, do not change + [76] = 0x43, // Reserved, do not change + [77] = 0x00, // Reserved, do not change + + // low_power_en + // 0: disable low power mode + // 1: enable low power mode + [93] = 0, + + // lp_rf_stg10 + // the attenuation of RF gain stage 0 and 1, + // 0xf: 0db, + // 0xe: -2.5db, + // 0xd: -6db, + // 0x9: -8.5db, + // 0xc: -11.5db, + // 0x8: -14db, + // 0x4: -17.5, + // 0x0: -23 + [94] = 0x00, + + // lp_bb_att_ext + // the attenuation of BB gain, + // 0: 0db, + // 1: -0.25db, + // 2: -0.5db, + // 3: -0.75db, + // 4: -1db, + // 5: -1.25db, + // 6: -1.5db, + // 7: -1.75db, + // 8: -2db + // max valve is 24(-6db) + [95] = 0, + + // pwr_ind_11b_en + // 0: 11b power is same as mcs0 and 6m + // 1: enable 11b power different with ofdm + [96] = 0, + + // pwr_ind_11b_0 + // 1m, 2m power index [0~5] + [97] = 0, + + // pwr_ind_11b_1 + // 5.5m, 11m power index [0~5] + [98] = 0, + + // vdd33_const + // the voltage of PA_VDD + // x=0xff: it can measure VDD33, + // 18<=x<=36: use input voltage, + // the value is voltage*10, 33 is 3.3V, 30 is 3.0V, + // x<18 or x>36: default voltage is 3.3V + // + // the value of this byte depend from the TOUT pin usage (1 or 2): + // 1) + // analogRead function (system_adc_read()): + // is only available when wire TOUT pin17 to external circuitry, Input Voltage Range restricted to 0 ~ 1.0V. + // For this function the vdd33_const must be set as real power voltage of VDD3P3 pin 3 and 4 + // The range of operating voltage of ESP8266 is 1.8V~3.6V，the unit of vdd33_const is 0.1V，so effective value range of vdd33_const is [18,36] + // 2) + // getVcc function (system_get_vdd33): + // is only available when TOUT pin17 is suspended (floating), this function measure the power voltage of VDD3P3 pin 3 and 4 + // For this function the vdd33_const must be set to 255 (0xFF). + [107] = 33, + + // disable RF calibration for certain number of times + [108] = 0, + + // freq_correct_en + // bit[0]:0->do not correct frequency offset, 1->correct frequency offset. + // bit[1]:0->bbpll is 168M, it can correct + and - frequency offset, 1->bbpll is 160M, it only can correct + frequency offset + // bit[2]:0->auto measure frequency offset and correct it, 1->use 113 byte force_freq_offset to correct frequency offset. + // 0: do not correct frequency offset. + // 1: auto measure frequency offset and correct it, bbpll is 168M, it can correct + and - frequency offset. + // 3: auto measure frequency offset and correct it, bbpll is 160M, it only can correct + frequency offset. + // 5: use 113 byte force_freq_offset to correct frequency offset, bbpll is 168M, it can correct + and - frequency offset. + // 7: use 113 byte force_freq_offset to correct frequency offset, bbpll is 160M , it only can correct + frequency offset. + [112] = 0, + + // force_freq_offset + // signed, unit is 8kHz + [113] = 0, + + // rf_cal_use_flash + // 0: RF init no RF CAL, using all RF CAL data in flash, it takes about 2ms for RF init + // 1: RF init only do TX power control CAL, others using RF CAL data in flash, it takes about 20ms for RF init + // 2: RF init no RF CAL, using all RF CAL data in flash, it takes about 2ms for RF init (same as 0?!) + // 3: RF init do all RF CAL, it takes about 200ms for RF init + [114] = 1 +}; + +#ifndef F_CRYSTAL +#define F_CRYSTAL 40000000 +#endif + +extern int __real_register_chipv6_phy(uint8_t* initData); + +int __attribute__((weak)) get_adc_mode() +{ + return 33; +} + +int ICACHE_FLASH_ATTR __attribute__((weak)) custom_register_chipv6_phy(uint8_t* initData) +{ + if (initData != NULL) { + memcpy(initData, phyInitData, sizeof(phyInitData)); + initData[107] = get_adc_mode(); + } + return __real_register_chipv6_phy(initData); +} + +int __wrap_register_chipv6_phy(uint8_t* initData) __attribute__ ((alias("custom_register_chipv6_phy"))); + +#endif /* ENABLE_CUSTOM_PHY */ diff --git a/Sming/Arch/Esp8266/Components/sming-arch/README.rst b/Sming/Arch/Esp8266/Components/sming-arch/README.rst index 7ca74663cb..3c144f4533 100644 --- a/Sming/Arch/Esp8266/Components/sming-arch/README.rst +++ b/Sming/Arch/Esp8266/Components/sming-arch/README.rst @@ -8,6 +8,9 @@ SDK 3.0+ Default: OFF. In order to use SDK 3.0.0 or newer please follow the instructions here :component-esp8266:`esp8266`. +- **SDK 3.0.+**: (default: OFF) In order to use SDK 3.0+ you should set one environment variable before (re)compiling Sming AND applications based on it. The variable is SDK_BASE and it should point to `$SMING_HOME/third-party/ESP8266_NONOS_SDK`. +- **Custom Phy data**: (default OFF) Allows programatical control over the initial physical data. This feature can be enabled by recompiling the Sming library and application with `ENABLE_CUSTOM_PHY=1`. + No-WiFi build ------------- From 8b4fb9eb991ce87461332f5efb6e99ee1f392c4d Mon Sep 17 00:00:00 2001 From: Slavey Karadzhov Date: Sat, 20 Oct 2018 05:46:25 -0700 Subject: [PATCH 02/10] Resolve section conflict. --- Sming/Arch/Esp8266/Components/esp8266/esp8266_phy.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Sming/Arch/Esp8266/Components/esp8266/esp8266_phy.c b/Sming/Arch/Esp8266/Components/esp8266/esp8266_phy.c index 697c04b970..ca82b0bfef 100644 --- a/Sming/Arch/Esp8266/Components/esp8266/esp8266_phy.c +++ b/Sming/Arch/Esp8266/Components/esp8266/esp8266_phy.c @@ -26,7 +26,7 @@ #define F_CRYSTAL 40000000 #endif -static const uint8_t ICACHE_FLASH_ATTR phyInitData[128] = +static const uint8_t phyInitData[128] = { [0] = 5, // Reserved, do not change [1] = 8, // Reserved, do not change From 358055634bd56d05e1080797afc514f49902f62a Mon Sep 17 00:00:00 2001 From: Slavey Karadzhov Date: Mon, 22 Oct 2018 00:02:48 +0200 Subject: [PATCH 03/10] Fixed the initial values to match the optimized init data from SDK 3.0 --- .../Esp8266/Components/esp8266/esp8266_phy.c | 36 ++++++++----------- 1 file changed, 14 insertions(+), 22 deletions(-) diff --git a/Sming/Arch/Esp8266/Components/esp8266/esp8266_phy.c b/Sming/Arch/Esp8266/Components/esp8266/esp8266_phy.c index ca82b0bfef..5ee81bf9b3 100644 --- a/Sming/Arch/Esp8266/Components/esp8266/esp8266_phy.c +++ b/Sming/Arch/Esp8266/Components/esp8266/esp8266_phy.c @@ -22,14 +22,14 @@ #include -#ifndef F_CRYSTAL -#define F_CRYSTAL 40000000 +#ifndef ICACHE_RAM_ATTR +#define ICACHE_RAM_ATTR __attribute__((section(".iram.text"))) #endif -static const uint8_t phyInitData[128] = +static const uint8_t ICACHE_FLASH_ATTR phyInitData[128] = { [0] = 5, // Reserved, do not change - [1] = 8, // Reserved, do not change + [1] = 0, // Reserved, do not change [2] = 4, // Reserved, do not change [3] = 2, // Reserved, do not change [4] = 5, // Reserved, do not change @@ -66,11 +66,11 @@ static const uint8_t phyInitData[128] = [32] = 0xf8, // Reserved, do not change [33] = 0xf8, // Reserved, do not change - [34] = 78, // target_power_qdb_0, target power is 78/4=19.5dbm - [35] = 74, // target_power_qdb_1, target power is 74/4=18.5dbm - [36] = 70, // target_power_qdb_2, target power is 70/4=17.5dbm - [37] = 64, // target_power_qdb_3, target power is 64/4=16dbm - [38] = 60, // target_power_qdb_4, target power is 60/4=15dbm + [34] = 0x52, // target_power_qdb_0, target power is 78/4=19.5dbm + [35] = 0x4e, // target_power_qdb_1, target power is 74/4=18.5dbm + [36] = 0x4a, // target_power_qdb_2, target power is 70/4=17.5dbm + [37] = 0x44, // target_power_qdb_3, target power is 64/4=16dbm + [38] = 0x40, // target_power_qdb_4, target power is 60/4=15dbm [39] = 56, // target_power_qdb_5, target power is 56/4=14dbm [40] = 0, // target_power_index_mcs0 @@ -86,11 +86,7 @@ static const uint8_t phyInitData[128] = // 0: 40MHz // 1: 26MHz // 2: 24MHz - #if F_CRYSTAL == 40000000 - [48] = 0, - #else - [48] = 1, - #endif + [48] = 1, // sdio_configure // 0: Auto by pin strapping @@ -229,7 +225,7 @@ static const uint8_t phyInitData[128] = // 3: auto measure frequency offset and correct it, bbpll is 160M, it only can correct + frequency offset. // 5: use 113 byte force_freq_offset to correct frequency offset, bbpll is 168M, it can correct + and - frequency offset. // 7: use 113 byte force_freq_offset to correct frequency offset, bbpll is 160M , it only can correct + frequency offset. - [112] = 0, + [112] = 3, // force_freq_offset // signed, unit is 8kHz @@ -243,21 +239,17 @@ static const uint8_t phyInitData[128] = [114] = 1 }; -#ifndef F_CRYSTAL -#define F_CRYSTAL 40000000 -#endif - extern int __real_register_chipv6_phy(uint8_t* initData); -int __attribute__((weak)) get_adc_mode() +int ICACHE_RAM_ATTR __attribute__((weak)) get_adc_mode() { return 33; } -int ICACHE_FLASH_ATTR __attribute__((weak)) custom_register_chipv6_phy(uint8_t* initData) +int ICACHE_RAM_ATTR __attribute__((weak)) custom_register_chipv6_phy(uint8_t* initData) { if (initData != NULL) { - memcpy(initData, phyInitData, sizeof(phyInitData)); + memcpy_P(initData, phyInitData, sizeof(phyInitData)); initData[107] = get_adc_mode(); } return __real_register_chipv6_phy(initData); From ba8b4b4bb94da310c8f3b3e288ceaa41e7a31a02 Mon Sep 17 00:00:00 2001 From: mikee47 Date: Sun, 23 Jun 2024 11:28:17 +0100 Subject: [PATCH 04/10] Fix documentation regarding Esp8266 SDK usage --- .../Arch/Esp8266/Components/sming-arch/README.rst | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/Sming/Arch/Esp8266/Components/sming-arch/README.rst b/Sming/Arch/Esp8266/Components/sming-arch/README.rst index 3c144f4533..0d1aef3c18 100644 --- a/Sming/Arch/Esp8266/Components/sming-arch/README.rst +++ b/Sming/Arch/Esp8266/Components/sming-arch/README.rst @@ -6,10 +6,18 @@ This Component builds a library containing architecture-specific code, and defin SDK 3.0+ -------- -Default: OFF. In order to use SDK 3.0.0 or newer please follow the instructions here :component-esp8266:`esp8266`. +Sming uses the Espressif Non-OS SDK version 3.0. It is pulled in automatically during builds. +Previous SDK versions are not supported. + +Custom PHY data +--------------- + +.. envvar:: ENABLE_CUSTOM_PHY + + Default: undefined (off) + + Set to 1 to enable programatical control over the initial Wifi PHY data. -- **SDK 3.0.+**: (default: OFF) In order to use SDK 3.0+ you should set one environment variable before (re)compiling Sming AND applications based on it. The variable is SDK_BASE and it should point to `$SMING_HOME/third-party/ESP8266_NONOS_SDK`. -- **Custom Phy data**: (default OFF) Allows programatical control over the initial physical data. This feature can be enabled by recompiling the Sming library and application with `ENABLE_CUSTOM_PHY=1`. No-WiFi build ------------- From 57a0de87bff5942e055ba8882f15b839a4c77d00 Mon Sep 17 00:00:00 2001 From: mikee47 Date: Sun, 23 Jun 2024 11:44:05 +0100 Subject: [PATCH 05/10] Fix compilation --- Sming/Arch/Esp8266/Components/esp8266/esp8266_phy.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/Sming/Arch/Esp8266/Components/esp8266/esp8266_phy.c b/Sming/Arch/Esp8266/Components/esp8266/esp8266_phy.c index 5ee81bf9b3..f369105a05 100644 --- a/Sming/Arch/Esp8266/Components/esp8266/esp8266_phy.c +++ b/Sming/Arch/Esp8266/Components/esp8266/esp8266_phy.c @@ -20,13 +20,11 @@ #ifdef ENABLE_CUSTOM_PHY -#include +#include +#include +#include -#ifndef ICACHE_RAM_ATTR -#define ICACHE_RAM_ATTR __attribute__((section(".iram.text"))) -#endif - -static const uint8_t ICACHE_FLASH_ATTR phyInitData[128] = +static const uint8_t phyInitData[128] PROGMEM = { [0] = 5, // Reserved, do not change [1] = 0, // Reserved, do not change From 1124d0da5989c5247c3dcf524ef68608fab4a605 Mon Sep 17 00:00:00 2001 From: mikee47 Date: Sun, 23 Jun 2024 11:44:29 +0100 Subject: [PATCH 06/10] Apply coding style --- .../Esp8266/Components/esp8266/esp8266_phy.c | 430 +++++++++--------- 1 file changed, 214 insertions(+), 216 deletions(-) diff --git a/Sming/Arch/Esp8266/Components/esp8266/esp8266_phy.c b/Sming/Arch/Esp8266/Components/esp8266/esp8266_phy.c index f369105a05..15475a01bc 100644 --- a/Sming/Arch/Esp8266/Components/esp8266/esp8266_phy.c +++ b/Sming/Arch/Esp8266/Components/esp8266/esp8266_phy.c @@ -24,218 +24,216 @@ #include #include -static const uint8_t phyInitData[128] PROGMEM = -{ - [0] = 5, // Reserved, do not change - [1] = 0, // Reserved, do not change - [2] = 4, // Reserved, do not change - [3] = 2, // Reserved, do not change - [4] = 5, // Reserved, do not change - [5] = 5, // Reserved, do not change - [6] = 5, // Reserved, do not change - [7] = 2, // Reserved, do not change - [8] = 5, // Reserved, do not change - [9] = 0, // Reserved, do not change - [10] = 4, // Reserved, do not change - [11] = 5, // Reserved, do not change - [12] = 5, // Reserved, do not change - [13] = 4, // Reserved, do not change - [14] = 5, // Reserved, do not change - [15] = 5, // Reserved, do not change - [16] = 4, // Reserved, do not change - [17] = -2, // Reserved, do not change - [18] = -3, // Reserved, do not change - [19] = -1, // Reserved, do not change - [20] = -16, // Reserved, do not change - [21] = -16, // Reserved, do not change - [22] = -16, // Reserved, do not change - [23] = -32, // Reserved, do not change - [24] = -32, // Reserved, do not change - [25] = -32, // Reserved, do not change - - [26] = 225, // spur_freq_cfg, spur_freq=spur_freq_cfg/spur_freq_cfg_div - [27] = 10, // spur_freq_cfg_div - // each bit for 1 channel, 1 to select the spur_freq if in band, else 40 - [28] = 0xff, // spur_freq_en_h - [29] = 0xff, // spur_freq_en_l - - [30] = 0xf8, // Reserved, do not change - [31] = 0, // Reserved, do not change - [32] = 0xf8, // Reserved, do not change - [33] = 0xf8, // Reserved, do not change - - [34] = 0x52, // target_power_qdb_0, target power is 78/4=19.5dbm - [35] = 0x4e, // target_power_qdb_1, target power is 74/4=18.5dbm - [36] = 0x4a, // target_power_qdb_2, target power is 70/4=17.5dbm - [37] = 0x44, // target_power_qdb_3, target power is 64/4=16dbm - [38] = 0x40, // target_power_qdb_4, target power is 60/4=15dbm - [39] = 56, // target_power_qdb_5, target power is 56/4=14dbm - - [40] = 0, // target_power_index_mcs0 - [41] = 0, // target_power_index_mcs1 - [42] = 1, // target_power_index_mcs2 - [43] = 1, // target_power_index_mcs3 - [44] = 2, // target_power_index_mcs4 - [45] = 3, // target_power_index_mcs5 - [46] = 4, // target_power_index_mcs6 - [47] = 5, // target_power_index_mcs7 - - // crystal_26m_en - // 0: 40MHz - // 1: 26MHz - // 2: 24MHz - [48] = 1, - - // sdio_configure - // 0: Auto by pin strapping - // 1: SDIO dataoutput is at negative edges (SDIO V1.1) - // 2: SDIO dataoutput is at positive edges (SDIO V2.0) - [50] = 0, - - // bt_configure - // 0: None,no bluetooth - // 1: GPIO0 -> WLAN_ACTIVE/ANT_SEL_WIFI - // MTMS -> BT_ACTIVE - // MTCK -> BT_PRIORITY - // U0RXD -> ANT_SEL_BT - // 2: None, have bluetooth - // 3: GPIO0 -> WLAN_ACTIVE/ANT_SEL_WIFI - // MTMS -> BT_PRIORITY - // MTCK -> BT_ACTIVE - // U0RXD -> ANT_SEL_BT - [51] = 0, - - // bt_protocol - // 0: WiFi-BT are not enabled. Antenna is for WiFi - // 1: WiFi-BT are not enabled. Antenna is for BT - // 2: WiFi-BT 2-wire are enabled, (only use BT_ACTIVE), independent ant - // 3: WiFi-BT 3-wire are enabled, (when BT_ACTIVE = 0, BT_PRIORITY must be 0), independent ant - // 4: WiFi-BT 2-wire are enabled, (only use BT_ACTIVE), share ant - // 5: WiFi-BT 3-wire are enabled, (when BT_ACTIVE = 0, BT_PRIORITY must be 0), share ant - [52] = 0, - - // dual_ant_configure - // 0: None - // 1: dual_ant (antenna diversity for WiFi-only): GPIO0 + U0RXD - // 2: T/R switch for External PA/LNA: GPIO0 is high and U0RXD is low during Tx - // 3: T/R switch for External PA/LNA: GPIO0 is low and U0RXD is high during Tx - [53] = 0, - - [54] = 2, // Reserved, do not change - - // share_xtal - // This option is to share crystal clock for BT - // The state of Crystal during sleeping - // 0: Off - // 1: Forcely On - // 2: Automatically On according to XPD_DCDC - // 3: Automatically On according to GPIO2 - [55] = 0, - - [64] = 225, // spur_freq_cfg_2, spur_freq_2=spur_freq_cfg_2/spur_freq_cfg_div_2 - [65] = 10, // spur_freq_cfg_div_2 - [66] = 0, // spur_freq_en_h_2 - [67] = 0, // spur_freq_en_l_2 - [68] = 0, // spur_freq_cfg_msb - [69] = 0, // spur_freq_cfg_2_msb - [70] = 0, // spur_freq_cfg_3_low - [71] = 0, // spur_freq_cfg_3_high - [72] = 0, // spur_freq_cfg_4_low - [73] = 0, // spur_freq_cfg_4_high - - [74] = 1, // Reserved, do not change - [75] = 0x93, // Reserved, do not change - [76] = 0x43, // Reserved, do not change - [77] = 0x00, // Reserved, do not change - - // low_power_en - // 0: disable low power mode - // 1: enable low power mode - [93] = 0, - - // lp_rf_stg10 - // the attenuation of RF gain stage 0 and 1, - // 0xf: 0db, - // 0xe: -2.5db, - // 0xd: -6db, - // 0x9: -8.5db, - // 0xc: -11.5db, - // 0x8: -14db, - // 0x4: -17.5, - // 0x0: -23 - [94] = 0x00, - - // lp_bb_att_ext - // the attenuation of BB gain, - // 0: 0db, - // 1: -0.25db, - // 2: -0.5db, - // 3: -0.75db, - // 4: -1db, - // 5: -1.25db, - // 6: -1.5db, - // 7: -1.75db, - // 8: -2db - // max valve is 24(-6db) - [95] = 0, - - // pwr_ind_11b_en - // 0: 11b power is same as mcs0 and 6m - // 1: enable 11b power different with ofdm - [96] = 0, - - // pwr_ind_11b_0 - // 1m, 2m power index [0~5] - [97] = 0, - - // pwr_ind_11b_1 - // 5.5m, 11m power index [0~5] - [98] = 0, - - // vdd33_const - // the voltage of PA_VDD - // x=0xff: it can measure VDD33, - // 18<=x<=36: use input voltage, - // the value is voltage*10, 33 is 3.3V, 30 is 3.0V, - // x<18 or x>36: default voltage is 3.3V - // - // the value of this byte depend from the TOUT pin usage (1 or 2): - // 1) - // analogRead function (system_adc_read()): - // is only available when wire TOUT pin17 to external circuitry, Input Voltage Range restricted to 0 ~ 1.0V. - // For this function the vdd33_const must be set as real power voltage of VDD3P3 pin 3 and 4 - // The range of operating voltage of ESP8266 is 1.8V~3.6V，the unit of vdd33_const is 0.1V，so effective value range of vdd33_const is [18,36] - // 2) - // getVcc function (system_get_vdd33): - // is only available when TOUT pin17 is suspended (floating), this function measure the power voltage of VDD3P3 pin 3 and 4 - // For this function the vdd33_const must be set to 255 (0xFF). - [107] = 33, - - // disable RF calibration for certain number of times - [108] = 0, - - // freq_correct_en - // bit[0]:0->do not correct frequency offset, 1->correct frequency offset. - // bit[1]:0->bbpll is 168M, it can correct + and - frequency offset, 1->bbpll is 160M, it only can correct + frequency offset - // bit[2]:0->auto measure frequency offset and correct it, 1->use 113 byte force_freq_offset to correct frequency offset. - // 0: do not correct frequency offset. - // 1: auto measure frequency offset and correct it, bbpll is 168M, it can correct + and - frequency offset. - // 3: auto measure frequency offset and correct it, bbpll is 160M, it only can correct + frequency offset. - // 5: use 113 byte force_freq_offset to correct frequency offset, bbpll is 168M, it can correct + and - frequency offset. - // 7: use 113 byte force_freq_offset to correct frequency offset, bbpll is 160M , it only can correct + frequency offset. - [112] = 3, - - // force_freq_offset - // signed, unit is 8kHz - [113] = 0, - - // rf_cal_use_flash - // 0: RF init no RF CAL, using all RF CAL data in flash, it takes about 2ms for RF init - // 1: RF init only do TX power control CAL, others using RF CAL data in flash, it takes about 20ms for RF init - // 2: RF init no RF CAL, using all RF CAL data in flash, it takes about 2ms for RF init (same as 0?!) - // 3: RF init do all RF CAL, it takes about 200ms for RF init - [114] = 1 -}; +static const uint8_t phyInitData[128] PROGMEM = { + [0] = 5, // Reserved, do not change + [1] = 0, // Reserved, do not change + [2] = 4, // Reserved, do not change + [3] = 2, // Reserved, do not change + [4] = 5, // Reserved, do not change + [5] = 5, // Reserved, do not change + [6] = 5, // Reserved, do not change + [7] = 2, // Reserved, do not change + [8] = 5, // Reserved, do not change + [9] = 0, // Reserved, do not change + [10] = 4, // Reserved, do not change + [11] = 5, // Reserved, do not change + [12] = 5, // Reserved, do not change + [13] = 4, // Reserved, do not change + [14] = 5, // Reserved, do not change + [15] = 5, // Reserved, do not change + [16] = 4, // Reserved, do not change + [17] = -2, // Reserved, do not change + [18] = -3, // Reserved, do not change + [19] = -1, // Reserved, do not change + [20] = -16, // Reserved, do not change + [21] = -16, // Reserved, do not change + [22] = -16, // Reserved, do not change + [23] = -32, // Reserved, do not change + [24] = -32, // Reserved, do not change + [25] = -32, // Reserved, do not change + + [26] = 225, // spur_freq_cfg, spur_freq=spur_freq_cfg/spur_freq_cfg_div + [27] = 10, // spur_freq_cfg_div + // each bit for 1 channel, 1 to select the spur_freq if in band, else 40 + [28] = 0xff, // spur_freq_en_h + [29] = 0xff, // spur_freq_en_l + + [30] = 0xf8, // Reserved, do not change + [31] = 0, // Reserved, do not change + [32] = 0xf8, // Reserved, do not change + [33] = 0xf8, // Reserved, do not change + + [34] = 0x52, // target_power_qdb_0, target power is 78/4=19.5dbm + [35] = 0x4e, // target_power_qdb_1, target power is 74/4=18.5dbm + [36] = 0x4a, // target_power_qdb_2, target power is 70/4=17.5dbm + [37] = 0x44, // target_power_qdb_3, target power is 64/4=16dbm + [38] = 0x40, // target_power_qdb_4, target power is 60/4=15dbm + [39] = 56, // target_power_qdb_5, target power is 56/4=14dbm + + [40] = 0, // target_power_index_mcs0 + [41] = 0, // target_power_index_mcs1 + [42] = 1, // target_power_index_mcs2 + [43] = 1, // target_power_index_mcs3 + [44] = 2, // target_power_index_mcs4 + [45] = 3, // target_power_index_mcs5 + [46] = 4, // target_power_index_mcs6 + [47] = 5, // target_power_index_mcs7 + + // crystal_26m_en + // 0: 40MHz + // 1: 26MHz + // 2: 24MHz + [48] = 1, + + // sdio_configure + // 0: Auto by pin strapping + // 1: SDIO dataoutput is at negative edges (SDIO V1.1) + // 2: SDIO dataoutput is at positive edges (SDIO V2.0) + [50] = 0, + + // bt_configure + // 0: None,no bluetooth + // 1: GPIO0 -> WLAN_ACTIVE/ANT_SEL_WIFI + // MTMS -> BT_ACTIVE + // MTCK -> BT_PRIORITY + // U0RXD -> ANT_SEL_BT + // 2: None, have bluetooth + // 3: GPIO0 -> WLAN_ACTIVE/ANT_SEL_WIFI + // MTMS -> BT_PRIORITY + // MTCK -> BT_ACTIVE + // U0RXD -> ANT_SEL_BT + [51] = 0, + + // bt_protocol + // 0: WiFi-BT are not enabled. Antenna is for WiFi + // 1: WiFi-BT are not enabled. Antenna is for BT + // 2: WiFi-BT 2-wire are enabled, (only use BT_ACTIVE), independent ant + // 3: WiFi-BT 3-wire are enabled, (when BT_ACTIVE = 0, BT_PRIORITY must be 0), independent ant + // 4: WiFi-BT 2-wire are enabled, (only use BT_ACTIVE), share ant + // 5: WiFi-BT 3-wire are enabled, (when BT_ACTIVE = 0, BT_PRIORITY must be 0), share ant + [52] = 0, + + // dual_ant_configure + // 0: None + // 1: dual_ant (antenna diversity for WiFi-only): GPIO0 + U0RXD + // 2: T/R switch for External PA/LNA: GPIO0 is high and U0RXD is low during Tx + // 3: T/R switch for External PA/LNA: GPIO0 is low and U0RXD is high during Tx + [53] = 0, + + [54] = 2, // Reserved, do not change + + // share_xtal + // This option is to share crystal clock for BT + // The state of Crystal during sleeping + // 0: Off + // 1: Forcely On + // 2: Automatically On according to XPD_DCDC + // 3: Automatically On according to GPIO2 + [55] = 0, + + [64] = 225, // spur_freq_cfg_2, spur_freq_2=spur_freq_cfg_2/spur_freq_cfg_div_2 + [65] = 10, // spur_freq_cfg_div_2 + [66] = 0, // spur_freq_en_h_2 + [67] = 0, // spur_freq_en_l_2 + [68] = 0, // spur_freq_cfg_msb + [69] = 0, // spur_freq_cfg_2_msb + [70] = 0, // spur_freq_cfg_3_low + [71] = 0, // spur_freq_cfg_3_high + [72] = 0, // spur_freq_cfg_4_low + [73] = 0, // spur_freq_cfg_4_high + + [74] = 1, // Reserved, do not change + [75] = 0x93, // Reserved, do not change + [76] = 0x43, // Reserved, do not change + [77] = 0x00, // Reserved, do not change + + // low_power_en + // 0: disable low power mode + // 1: enable low power mode + [93] = 0, + + // lp_rf_stg10 + // the attenuation of RF gain stage 0 and 1, + // 0xf: 0db, + // 0xe: -2.5db, + // 0xd: -6db, + // 0x9: -8.5db, + // 0xc: -11.5db, + // 0x8: -14db, + // 0x4: -17.5, + // 0x0: -23 + [94] = 0x00, + + // lp_bb_att_ext + // the attenuation of BB gain, + // 0: 0db, + // 1: -0.25db, + // 2: -0.5db, + // 3: -0.75db, + // 4: -1db, + // 5: -1.25db, + // 6: -1.5db, + // 7: -1.75db, + // 8: -2db + // max valve is 24(-6db) + [95] = 0, + + // pwr_ind_11b_en + // 0: 11b power is same as mcs0 and 6m + // 1: enable 11b power different with ofdm + [96] = 0, + + // pwr_ind_11b_0 + // 1m, 2m power index [0~5] + [97] = 0, + + // pwr_ind_11b_1 + // 5.5m, 11m power index [0~5] + [98] = 0, + + // vdd33_const + // the voltage of PA_VDD + // x=0xff: it can measure VDD33, + // 18<=x<=36: use input voltage, + // the value is voltage*10, 33 is 3.3V, 30 is 3.0V, + // x<18 or x>36: default voltage is 3.3V + // + // the value of this byte depend from the TOUT pin usage (1 or 2): + // 1) + // analogRead function (system_adc_read()): + // is only available when wire TOUT pin17 to external circuitry, Input Voltage Range restricted to 0 ~ 1.0V. + // For this function the vdd33_const must be set as real power voltage of VDD3P3 pin 3 and 4 + // The range of operating voltage of ESP8266 is 1.8V~3.6V，the unit of vdd33_const is 0.1V，so effective value range of vdd33_const is [18,36] + // 2) + // getVcc function (system_get_vdd33): + // is only available when TOUT pin17 is suspended (floating), this function measure the power voltage of VDD3P3 pin 3 and 4 + // For this function the vdd33_const must be set to 255 (0xFF). + [107] = 33, + + // disable RF calibration for certain number of times + [108] = 0, + + // freq_correct_en + // bit[0]:0->do not correct frequency offset, 1->correct frequency offset. + // bit[1]:0->bbpll is 168M, it can correct + and - frequency offset, 1->bbpll is 160M, it only can correct + frequency offset + // bit[2]:0->auto measure frequency offset and correct it, 1->use 113 byte force_freq_offset to correct frequency offset. + // 0: do not correct frequency offset. + // 1: auto measure frequency offset and correct it, bbpll is 168M, it can correct + and - frequency offset. + // 3: auto measure frequency offset and correct it, bbpll is 160M, it only can correct + frequency offset. + // 5: use 113 byte force_freq_offset to correct frequency offset, bbpll is 168M, it can correct + and - frequency offset. + // 7: use 113 byte force_freq_offset to correct frequency offset, bbpll is 160M , it only can correct + frequency offset. + [112] = 3, + + // force_freq_offset + // signed, unit is 8kHz + [113] = 0, + + // rf_cal_use_flash + // 0: RF init no RF CAL, using all RF CAL data in flash, it takes about 2ms for RF init + // 1: RF init only do TX power control CAL, others using RF CAL data in flash, it takes about 20ms for RF init + // 2: RF init no RF CAL, using all RF CAL data in flash, it takes about 2ms for RF init (same as 0?!) + // 3: RF init do all RF CAL, it takes about 200ms for RF init + [114] = 1}; extern int __real_register_chipv6_phy(uint8_t* initData); @@ -246,13 +244,13 @@ int ICACHE_RAM_ATTR __attribute__((weak)) get_adc_mode() int ICACHE_RAM_ATTR __attribute__((weak)) custom_register_chipv6_phy(uint8_t* initData) { - if (initData != NULL) { - memcpy_P(initData, phyInitData, sizeof(phyInitData)); - initData[107] = get_adc_mode(); + if(initData != NULL) { + memcpy_P(initData, phyInitData, sizeof(phyInitData)); + initData[107] = get_adc_mode(); } return __real_register_chipv6_phy(initData); } -int __wrap_register_chipv6_phy(uint8_t* initData) __attribute__ ((alias("custom_register_chipv6_phy"))); +int __wrap_register_chipv6_phy(uint8_t* initData) __attribute__((alias("custom_register_chipv6_phy"))); #endif /* ENABLE_CUSTOM_PHY */ From 231c886fa4ba24f960556918c542dec37653077d Mon Sep 17 00:00:00 2001 From: mikee47 Date: Sun, 23 Jun 2024 11:44:48 +0100 Subject: [PATCH 07/10] Fix version field --- Sming/Arch/Esp8266/Components/esp8266/esp8266_phy.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Sming/Arch/Esp8266/Components/esp8266/esp8266_phy.c b/Sming/Arch/Esp8266/Components/esp8266/esp8266_phy.c index 15475a01bc..9dde90edb2 100644 --- a/Sming/Arch/Esp8266/Components/esp8266/esp8266_phy.c +++ b/Sming/Arch/Esp8266/Components/esp8266/esp8266_phy.c @@ -26,7 +26,7 @@ static const uint8_t phyInitData[128] PROGMEM = { [0] = 5, // Reserved, do not change - [1] = 0, // Reserved, do not change + [1] = 8, // Version [2] = 4, // Reserved, do not change [3] = 2, // Reserved, do not change [4] = 5, // Reserved, do not change From 1224a375cfff979b2ef5fae6c88912961709942c Mon Sep 17 00:00:00 2001 From: mikee47 Date: Sun, 23 Jun 2024 12:23:48 +0100 Subject: [PATCH 08/10] Use a struct to manage modification of PHY data --- .../Esp8266/Components/esp8266/README.rst | 24 ++ .../Esp8266/Components/esp8266/component.mk | 3 +- .../Esp8266/Components/esp8266/esp8266_phy.c | 256 --------------- .../Components/esp8266/esp8266_phy.cpp | 43 +++ .../Components/esp8266/include/esp_phy.h | 309 ++++++++++++++++++ .../Esp8266/Components/sming-arch/README.rst | 16 - 6 files changed, 378 insertions(+), 273 deletions(-) delete mode 100644 Sming/Arch/Esp8266/Components/esp8266/esp8266_phy.c create mode 100644 Sming/Arch/Esp8266/Components/esp8266/esp8266_phy.cpp create mode 100644 Sming/Arch/Esp8266/Components/esp8266/include/esp_phy.h diff --git a/Sming/Arch/Esp8266/Components/esp8266/README.rst b/Sming/Arch/Esp8266/Components/esp8266/README.rst index 37fa9c0e7b..b669164ba7 100644 --- a/Sming/Arch/Esp8266/Components/esp8266/README.rst +++ b/Sming/Arch/Esp8266/Components/esp8266/README.rst @@ -8,3 +8,27 @@ support code. Sming uses libraries from the ESP8266 NON-OS SDK version 3, imported as a submodule. The header and linker files are provided by this Component. + + +.. envvar:: ENABLE_CUSTOM_PHY + + Default: undefined (off) + + The ``phy_init`` partition contains data which the ESP8266 SDK uses to initialise WiFi hardware at startup. + + You may want to change settings for a certain ROM on the device without changing it for all ROMs on the device. + To do this, build with ``ENABLE_CUSTOM_PHY=1`` and add code to your application:: + + #include + + void customPhyInit(PhyInitData data) + { + // Use methods of `data` to modify as required + data.set_vdd33_const(0xff); + } + + See :cpp:struct:`PhyInitData` for further details. + + +.. doxygenstruct:: PhyInitData + :members: diff --git a/Sming/Arch/Esp8266/Components/esp8266/component.mk b/Sming/Arch/Esp8266/Components/esp8266/component.mk index 7a141bb6e3..cb733c3006 100644 --- a/Sming/Arch/Esp8266/Components/esp8266/component.mk +++ b/Sming/Arch/Esp8266/Components/esp8266/component.mk @@ -38,7 +38,8 @@ export SDK_LIBDIR COMPONENT_DOXYGEN_INPUT := \ include/gpio.h \ - include/pwm.h + include/pwm.h \ + include/esp_phy.h # Crash handler hooks this so debugger can be invoked EXTRA_LDFLAGS := $(call Wrap,system_restart_local) diff --git a/Sming/Arch/Esp8266/Components/esp8266/esp8266_phy.c b/Sming/Arch/Esp8266/Components/esp8266/esp8266_phy.c deleted file mode 100644 index 9dde90edb2..0000000000 --- a/Sming/Arch/Esp8266/Components/esp8266/esp8266_phy.c +++ /dev/null @@ -1,256 +0,0 @@ -/* - Adapted from Arduino for Sming. - Original copyright note is kept below. - - phy.c - ESP8266 PHY initialization data - Copyright (c) 2015 Ivan Grokhotkov. All rights reserved. - This file is part of the esp8266 core for Arduino environment. - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - Lesser General Public License for more details. - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifdef ENABLE_CUSTOM_PHY - -#include -#include -#include - -static const uint8_t phyInitData[128] PROGMEM = { - [0] = 5, // Reserved, do not change - [1] = 8, // Version - [2] = 4, // Reserved, do not change - [3] = 2, // Reserved, do not change - [4] = 5, // Reserved, do not change - [5] = 5, // Reserved, do not change - [6] = 5, // Reserved, do not change - [7] = 2, // Reserved, do not change - [8] = 5, // Reserved, do not change - [9] = 0, // Reserved, do not change - [10] = 4, // Reserved, do not change - [11] = 5, // Reserved, do not change - [12] = 5, // Reserved, do not change - [13] = 4, // Reserved, do not change - [14] = 5, // Reserved, do not change - [15] = 5, // Reserved, do not change - [16] = 4, // Reserved, do not change - [17] = -2, // Reserved, do not change - [18] = -3, // Reserved, do not change - [19] = -1, // Reserved, do not change - [20] = -16, // Reserved, do not change - [21] = -16, // Reserved, do not change - [22] = -16, // Reserved, do not change - [23] = -32, // Reserved, do not change - [24] = -32, // Reserved, do not change - [25] = -32, // Reserved, do not change - - [26] = 225, // spur_freq_cfg, spur_freq=spur_freq_cfg/spur_freq_cfg_div - [27] = 10, // spur_freq_cfg_div - // each bit for 1 channel, 1 to select the spur_freq if in band, else 40 - [28] = 0xff, // spur_freq_en_h - [29] = 0xff, // spur_freq_en_l - - [30] = 0xf8, // Reserved, do not change - [31] = 0, // Reserved, do not change - [32] = 0xf8, // Reserved, do not change - [33] = 0xf8, // Reserved, do not change - - [34] = 0x52, // target_power_qdb_0, target power is 78/4=19.5dbm - [35] = 0x4e, // target_power_qdb_1, target power is 74/4=18.5dbm - [36] = 0x4a, // target_power_qdb_2, target power is 70/4=17.5dbm - [37] = 0x44, // target_power_qdb_3, target power is 64/4=16dbm - [38] = 0x40, // target_power_qdb_4, target power is 60/4=15dbm - [39] = 56, // target_power_qdb_5, target power is 56/4=14dbm - - [40] = 0, // target_power_index_mcs0 - [41] = 0, // target_power_index_mcs1 - [42] = 1, // target_power_index_mcs2 - [43] = 1, // target_power_index_mcs3 - [44] = 2, // target_power_index_mcs4 - [45] = 3, // target_power_index_mcs5 - [46] = 4, // target_power_index_mcs6 - [47] = 5, // target_power_index_mcs7 - - // crystal_26m_en - // 0: 40MHz - // 1: 26MHz - // 2: 24MHz - [48] = 1, - - // sdio_configure - // 0: Auto by pin strapping - // 1: SDIO dataoutput is at negative edges (SDIO V1.1) - // 2: SDIO dataoutput is at positive edges (SDIO V2.0) - [50] = 0, - - // bt_configure - // 0: None,no bluetooth - // 1: GPIO0 -> WLAN_ACTIVE/ANT_SEL_WIFI - // MTMS -> BT_ACTIVE - // MTCK -> BT_PRIORITY - // U0RXD -> ANT_SEL_BT - // 2: None, have bluetooth - // 3: GPIO0 -> WLAN_ACTIVE/ANT_SEL_WIFI - // MTMS -> BT_PRIORITY - // MTCK -> BT_ACTIVE - // U0RXD -> ANT_SEL_BT - [51] = 0, - - // bt_protocol - // 0: WiFi-BT are not enabled. Antenna is for WiFi - // 1: WiFi-BT are not enabled. Antenna is for BT - // 2: WiFi-BT 2-wire are enabled, (only use BT_ACTIVE), independent ant - // 3: WiFi-BT 3-wire are enabled, (when BT_ACTIVE = 0, BT_PRIORITY must be 0), independent ant - // 4: WiFi-BT 2-wire are enabled, (only use BT_ACTIVE), share ant - // 5: WiFi-BT 3-wire are enabled, (when BT_ACTIVE = 0, BT_PRIORITY must be 0), share ant - [52] = 0, - - // dual_ant_configure - // 0: None - // 1: dual_ant (antenna diversity for WiFi-only): GPIO0 + U0RXD - // 2: T/R switch for External PA/LNA: GPIO0 is high and U0RXD is low during Tx - // 3: T/R switch for External PA/LNA: GPIO0 is low and U0RXD is high during Tx - [53] = 0, - - [54] = 2, // Reserved, do not change - - // share_xtal - // This option is to share crystal clock for BT - // The state of Crystal during sleeping - // 0: Off - // 1: Forcely On - // 2: Automatically On according to XPD_DCDC - // 3: Automatically On according to GPIO2 - [55] = 0, - - [64] = 225, // spur_freq_cfg_2, spur_freq_2=spur_freq_cfg_2/spur_freq_cfg_div_2 - [65] = 10, // spur_freq_cfg_div_2 - [66] = 0, // spur_freq_en_h_2 - [67] = 0, // spur_freq_en_l_2 - [68] = 0, // spur_freq_cfg_msb - [69] = 0, // spur_freq_cfg_2_msb - [70] = 0, // spur_freq_cfg_3_low - [71] = 0, // spur_freq_cfg_3_high - [72] = 0, // spur_freq_cfg_4_low - [73] = 0, // spur_freq_cfg_4_high - - [74] = 1, // Reserved, do not change - [75] = 0x93, // Reserved, do not change - [76] = 0x43, // Reserved, do not change - [77] = 0x00, // Reserved, do not change - - // low_power_en - // 0: disable low power mode - // 1: enable low power mode - [93] = 0, - - // lp_rf_stg10 - // the attenuation of RF gain stage 0 and 1, - // 0xf: 0db, - // 0xe: -2.5db, - // 0xd: -6db, - // 0x9: -8.5db, - // 0xc: -11.5db, - // 0x8: -14db, - // 0x4: -17.5, - // 0x0: -23 - [94] = 0x00, - - // lp_bb_att_ext - // the attenuation of BB gain, - // 0: 0db, - // 1: -0.25db, - // 2: -0.5db, - // 3: -0.75db, - // 4: -1db, - // 5: -1.25db, - // 6: -1.5db, - // 7: -1.75db, - // 8: -2db - // max valve is 24(-6db) - [95] = 0, - - // pwr_ind_11b_en - // 0: 11b power is same as mcs0 and 6m - // 1: enable 11b power different with ofdm - [96] = 0, - - // pwr_ind_11b_0 - // 1m, 2m power index [0~5] - [97] = 0, - - // pwr_ind_11b_1 - // 5.5m, 11m power index [0~5] - [98] = 0, - - // vdd33_const - // the voltage of PA_VDD - // x=0xff: it can measure VDD33, - // 18<=x<=36: use input voltage, - // the value is voltage*10, 33 is 3.3V, 30 is 3.0V, - // x<18 or x>36: default voltage is 3.3V - // - // the value of this byte depend from the TOUT pin usage (1 or 2): - // 1) - // analogRead function (system_adc_read()): - // is only available when wire TOUT pin17 to external circuitry, Input Voltage Range restricted to 0 ~ 1.0V. - // For this function the vdd33_const must be set as real power voltage of VDD3P3 pin 3 and 4 - // The range of operating voltage of ESP8266 is 1.8V~3.6V，the unit of vdd33_const is 0.1V，so effective value range of vdd33_const is [18,36] - // 2) - // getVcc function (system_get_vdd33): - // is only available when TOUT pin17 is suspended (floating), this function measure the power voltage of VDD3P3 pin 3 and 4 - // For this function the vdd33_const must be set to 255 (0xFF). - [107] = 33, - - // disable RF calibration for certain number of times - [108] = 0, - - // freq_correct_en - // bit[0]:0->do not correct frequency offset, 1->correct frequency offset. - // bit[1]:0->bbpll is 168M, it can correct + and - frequency offset, 1->bbpll is 160M, it only can correct + frequency offset - // bit[2]:0->auto measure frequency offset and correct it, 1->use 113 byte force_freq_offset to correct frequency offset. - // 0: do not correct frequency offset. - // 1: auto measure frequency offset and correct it, bbpll is 168M, it can correct + and - frequency offset. - // 3: auto measure frequency offset and correct it, bbpll is 160M, it only can correct + frequency offset. - // 5: use 113 byte force_freq_offset to correct frequency offset, bbpll is 168M, it can correct + and - frequency offset. - // 7: use 113 byte force_freq_offset to correct frequency offset, bbpll is 160M , it only can correct + frequency offset. - [112] = 3, - - // force_freq_offset - // signed, unit is 8kHz - [113] = 0, - - // rf_cal_use_flash - // 0: RF init no RF CAL, using all RF CAL data in flash, it takes about 2ms for RF init - // 1: RF init only do TX power control CAL, others using RF CAL data in flash, it takes about 20ms for RF init - // 2: RF init no RF CAL, using all RF CAL data in flash, it takes about 2ms for RF init (same as 0?!) - // 3: RF init do all RF CAL, it takes about 200ms for RF init - [114] = 1}; - -extern int __real_register_chipv6_phy(uint8_t* initData); - -int ICACHE_RAM_ATTR __attribute__((weak)) get_adc_mode() -{ - return 33; -} - -int ICACHE_RAM_ATTR __attribute__((weak)) custom_register_chipv6_phy(uint8_t* initData) -{ - if(initData != NULL) { - memcpy_P(initData, phyInitData, sizeof(phyInitData)); - initData[107] = get_adc_mode(); - } - return __real_register_chipv6_phy(initData); -} - -int __wrap_register_chipv6_phy(uint8_t* initData) __attribute__((alias("custom_register_chipv6_phy"))); - -#endif /* ENABLE_CUSTOM_PHY */ diff --git a/Sming/Arch/Esp8266/Components/esp8266/esp8266_phy.cpp b/Sming/Arch/Esp8266/Components/esp8266/esp8266_phy.cpp new file mode 100644 index 0000000000..361ab79ed1 --- /dev/null +++ b/Sming/Arch/Esp8266/Components/esp8266/esp8266_phy.cpp @@ -0,0 +1,43 @@ +/* + Adapted from Arduino for Sming. + Original copyright note is kept below. + + phy.c - ESP8266 PHY initialization data + Copyright (c) 2015 Ivan Grokhotkov. All rights reserved. + This file is part of the esp8266 core for Arduino environment. + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// #ifdef ENABLE_CUSTOM_PHY + +#include "include/esp_phy.h" +#include +#include +#include +#include + +extern "C" { +extern int __wrap_register_chipv6_phy(uint8_t* initData); +extern int __real_register_chipv6_phy(uint8_t* initData); +} + +int ICACHE_RAM_ATTR __wrap_register_chipv6_phy(uint8_t* initData) +{ + if(initData != NULL) { + PhyInitData data{initData}; + customPhyInit(data); + } + return __real_register_chipv6_phy(initData); +} + +// #endif /* ENABLE_CUSTOM_PHY */ diff --git a/Sming/Arch/Esp8266/Components/esp8266/include/esp_phy.h b/Sming/Arch/Esp8266/Components/esp8266/include/esp_phy.h new file mode 100644 index 0000000000..1fdac12d98 --- /dev/null +++ b/Sming/Arch/Esp8266/Components/esp8266/include/esp_phy.h @@ -0,0 +1,309 @@ +/* + Adapted from Arduino for Sming. + Original copyright note is kept below. + + phy.c - ESP8266 PHY initialization data + Copyright (c) 2015 Ivan Grokhotkov. All rights reserved. + This file is part of the esp8266 core for Arduino environment. + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include + +/** + * @brief Structure to manage low-level adjustment of PHY data + * Does not contain the data but a reference to it. + * The data should not be accessed directly. + */ +struct PhyInitData { + uint8_t* data; // [128] + + /* + [26] = 225, // spur_freq_cfg, spur_freq=spur_freq_cfg/spur_freq_cfg_div + [27] = 10, // spur_freq_cfg_div + // each bit for 1 channel, 1 to select the spur_freq if in band, else 40 + [28] = 0xff, // spur_freq_en_h + [29] = 0xff, // spur_freq_en_l + + [34] = 78, // target_power_qdb_0, target power is 78/4=19.5dbm + [35] = 74, // target_power_qdb_1, target power is 74/4=18.5dbm + [36] = 70, // target_power_qdb_2, target power is 70/4=17.5dbm + [37] = 64, // target_power_qdb_3, target power is 64/4=16dbm + [38] = 60, // target_power_qdb_4, target power is 60/4=15dbm + [39] = 56, // target_power_qdb_5, target power is 56/4=14dbm + + [40] = 0, // target_power_index_mcs0 + [41] = 0, // target_power_index_mcs1 + [42] = 1, // target_power_index_mcs2 + [43] = 1, // target_power_index_mcs3 + [44] = 2, // target_power_index_mcs4 + [45] = 3, // target_power_index_mcs5 + [46] = 4, // target_power_index_mcs6 + [47] = 5, // target_power_index_mcs7 +*/ + /** + * @brief crystal_26m_en + * + * 0: 40MHz + * 1: 26MHz + * 2: 24MHz + */ + void set_crystal_26m_en(uint8_t value = 1) + { + data[48] = value; + } + + /** + * @brief sdio_configure + * + * 0: Auto by pin strapping + * 1: SDIO dataoutput is at negative edges (SDIO V1.1) + * 2: SDIO dataoutput is at positive edges (SDIO V2.0) + */ + void set_sdio_configure(uint8_t value = 0) + { + data[50] = value; + } + + /** + * @brief bt_configure + * + * 0: None,no bluetooth + * 1: GPIO0 -> WLAN_ACTIVE/ANT_SEL_WIFI + * MTMS -> BT_ACTIVE + * MTCK -> BT_PRIORITY + * U0RXD -> ANT_SEL_BT + * 2: None, have bluetooth + * 3: GPIO0 -> WLAN_ACTIVE/ANT_SEL_WIFI + * MTMS -> BT_PRIORITY + * MTCK -> BT_ACTIVE + * U0RXD -> ANT_SEL_BT + */ + void set_bt_configure(uint8_t value = 0) + { + data[51] = value; + } + + /** + * @brief bt_protocol + * + * 0: WiFi-BT are not enabled. Antenna is for WiFi + * 1: WiFi-BT are not enabled. Antenna is for BT + * 2: WiFi-BT 2-wire are enabled, (only use BT_ACTIVE), independent ant + * 3: WiFi-BT 3-wire are enabled, (when BT_ACTIVE = 0, BT_PRIORITY must be 0), independent ant + * 4: WiFi-BT 2-wire are enabled, (only use BT_ACTIVE), share ant + * 5: WiFi-BT 3-wire are enabled, (when BT_ACTIVE = 0, BT_PRIORITY must be 0), share ant + */ + void set_bt_protocol(uint8_t value = 0) + { + data[52] = value; + } + + /** + * @brief dual_ant_configure + * + * 0: None + * 1: dual_ant (antenna diversity for WiFi-only): GPIO0 + U0RXD + * 2: T/R switch for External PA/LNA: GPIO0 is high and U0RXD is low during Tx + * 3: T/R switch for External PA/LNA: GPIO0 is low and U0RXD is high during Tx + */ + void set_dual_ant_configure(uint8_t value = 0) + { + data[53] = value; + } + + /** + * @brief share_xtal + * This option is to share crystal clock for BT + * The state of Crystal during sleeping + * 0: Off + * 1: Forceably On + * 2: Automatically On according to XPD_DCDC + * 3: Automatically On according to GPIO2 + */ + void set_share_xtal(uint8_t value = 0) + { + data[55] = value; + } + + /* + [64] = 225, // spur_freq_cfg_2, spur_freq_2=spur_freq_cfg_2/spur_freq_cfg_div_2 + [65] = 10, // spur_freq_cfg_div_2 + [66] = 0, // spur_freq_en_h_2 + [67] = 0, // spur_freq_en_l_2 + [68] = 0, // spur_freq_cfg_msb + [69] = 0, // spur_freq_cfg_2_msb + [70] = 0, // spur_freq_cfg_3_low + [71] = 0, // spur_freq_cfg_3_high + [72] = 0, // spur_freq_cfg_4_low + [73] = 0, // spur_freq_cfg_4_high +*/ + + /** + * @brief low_power_en + * + * 0: disable low power mode + * 1: enable low power mode + */ + void set_low_power_en(uint8_t value = 0) + { + data[93] = value; + } + + /** + * @brief lp_rf_stg10 + * + * The attenuation of RF gain stage 0 and 1: + * + * 0xf: 0db + * 0xe: -2.5db + * 0xd: -6db + * 0x9: -8.5db + * 0xc: -11.5db + * 0x8: -14db + * 0x4: -17.5 + * 0x0: -23 + */ + void set_lp_rf_stg10(uint8_t value = 0) + { + data[94] = value; + } + + /** + * @brief lp_bb_att_ext + * + * The attenuation of BB gain: + * 0: 0db + * 1: -0.25db + * 2: -0.5db + * 3: -0.75db + * 4: -1db + * 5: -1.25db + * 6: -1.5db + * 7: -1.75db + * 8: -2db + * ... + * max valve is 24 (-6db) + */ + void set_lp_bb_att_ext(uint8_t value = 0) + { + data[95] = value; + } + + /** + * @brief pwr_ind_11b_en + * + * 0: 11b power is same as mcs0 and 6m + * 1: enable 11b power different with OFDM + */ + void set_pwr_ind_11b_en(uint8_t value = 0) + { + data[96] = value; + } + + /** + * @brief pwr_ind_11b_0 + * + * 1m, 2m power index [0~5] + */ + void set_pwr_ind_11b_0(uint8_t value = 0) + { + data[97] = value; + } + + /** + * @brief pwr_ind_11b_1 + * + * 5.5m, 11m power index [0~5] + */ + void set_pwr_ind_11b_1(uint8_t value = 0) + { + data[98] = value; + } + + /** + * @brief vdd33_const + * + * The voltage of PA_VDD + * x=0xff: it can measure VDD33, + * 18<=x<=36: use input voltage, + * the value is voltage*10, 33 is 3.3V, 30 is 3.0V, + * x<18 or x>36: default voltage is 3.3V + * + * The value of this byte depend from the TOUT pin usage (1 or 2): + * 1) analogRead function (system_adc_read()) + * Only available when wire TOUT pin17 to external circuitry, Input Voltage Range restricted to 0 ~ 1.0V. + * For this function the vdd33_const must be set as real power voltage of VDD3P3 pin 3 and 4 + * The range of operating voltage of ESP8266 is 1.8V~3.6V，the unit of vdd33_const is 0.1V，so effective value range of vdd33_const is [18,36] + * 2) getVcc function (system_get_vdd33) + * Only available when TOUT pin17 is suspended (floating), this function measure the power voltage of VDD3P3 pin 3 and 4 + * For this function the vdd33_const must be set to 255 (0xFF). + */ + void set_vdd33_const(uint8_t value = 33) + { + data[107] = value; + } + + /** + * @brief rf_cal_disable + * Disable RF calibration for certain number of times + */ + void set_rf_cal_disable(uint8_t value = 0) + { + data[108] = value; + } + + /** + * @brief freq_correct_en + * + * bit[0]:0->do not correct frequency offset, 1->correct frequency offset. + * bit[1]:0->bbpll is 168M, it can correct + and - frequency offset, 1->bbpll is 160M, it only can correct + frequency offset + * bit[2]:0->auto measure frequency offset and correct it, 1->use 113 byte force_freq_offset to correct frequency offset. + * 0: do not correct frequency offset. + * 1: auto measure frequency offset and correct it, bbpll is 168M, it can correct + and - frequency offset. + * 3: auto measure frequency offset and correct it, bbpll is 160M, it only can correct + frequency offset. + * 5: use 113 byte force_freq_offset to correct frequency offset, bbpll is 168M, it can correct + and - frequency offset. + * 7: use 113 byte force_freq_offset to correct frequency offset, bbpll is 160M , it only can correct + frequency offset. + */ + void set_freq_correct_en(uint8_t value = 3) + { + data[112] = value; + } + + /** + * @brief force_freq_offset + * + * signed, unit is 8kHz + */ + void set_force_freq_offset(int8_t value = 0) + { + data[113] = uint8_t(value); + } + + /** + * @brief rf_cal_use_flash + * + * 0: RF init no RF CAL, using all RF CAL data in flash, it takes about 2ms for RF init + * 1: RF init only do TX power control CAL, others using RF CAL data in flash, it takes about 20ms for RF init + * 2: RF init no RF CAL, using all RF CAL data in flash, it takes about 2ms for RF init (same as 0?!) + * 3: RF init do all RF CAL, it takes about 200ms for RF init + */ + void set_rf_cal_use_flash(uint8_t value = 1) + { + data[114] = value; + } +}; + +extern void customPhyInit(PhyInitData data); diff --git a/Sming/Arch/Esp8266/Components/sming-arch/README.rst b/Sming/Arch/Esp8266/Components/sming-arch/README.rst index 0d1aef3c18..347b8fa54b 100644 --- a/Sming/Arch/Esp8266/Components/sming-arch/README.rst +++ b/Sming/Arch/Esp8266/Components/sming-arch/README.rst @@ -3,22 +3,6 @@ Sming (Esp8266) This Component builds a library containing architecture-specific code, and defines dependencies for Sming to build for the Esp8266. -SDK 3.0+ --------- - -Sming uses the Espressif Non-OS SDK version 3.0. It is pulled in automatically during builds. -Previous SDK versions are not supported. - -Custom PHY data ---------------- - -.. envvar:: ENABLE_CUSTOM_PHY - - Default: undefined (off) - - Set to 1 to enable programatical control over the initial Wifi PHY data. - - No-WiFi build ------------- From ca6d93996834f26c734e7f83e1fa974743ec0d95 Mon Sep 17 00:00:00 2001 From: mikee47 Date: Sun, 23 Jun 2024 13:36:28 +0100 Subject: [PATCH 09/10] Review settings as per Espressif Parameter Configuration Guide --- .../Components/esp8266/include/esp_phy.h | 102 ++++++++++++++---- 1 file changed, 83 insertions(+), 19 deletions(-) diff --git a/Sming/Arch/Esp8266/Components/esp8266/include/esp_phy.h b/Sming/Arch/Esp8266/Components/esp8266/include/esp_phy.h index 1fdac12d98..15f6a9c8ed 100644 --- a/Sming/Arch/Esp8266/Components/esp8266/include/esp_phy.h +++ b/Sming/Arch/Esp8266/Components/esp8266/include/esp_phy.h @@ -30,37 +30,99 @@ struct PhyInitData { uint8_t* data; // [128] + /** + * @brief version + */ + uint8_t get_version() const + { + return data[1]; + } + /* [26] = 225, // spur_freq_cfg, spur_freq=spur_freq_cfg/spur_freq_cfg_div [27] = 10, // spur_freq_cfg_div // each bit for 1 channel, 1 to select the spur_freq if in band, else 40 [28] = 0xff, // spur_freq_en_h [29] = 0xff, // spur_freq_en_l +*/ - [34] = 78, // target_power_qdb_0, target power is 78/4=19.5dbm - [35] = 74, // target_power_qdb_1, target power is 74/4=18.5dbm - [36] = 70, // target_power_qdb_2, target power is 70/4=17.5dbm - [37] = 64, // target_power_qdb_3, target power is 64/4=16dbm - [38] = 60, // target_power_qdb_4, target power is 60/4=15dbm - [39] = 56, // target_power_qdb_5, target power is 56/4=14dbm + /** + * @brief Configure the maximum TX powers for channels 1, 11, 13 and 14. + * @param chan1 Limit for channel 1 + * @param chan11 Limit for channel 11 + * @param chan13 Limit for channel 13 + * @param chan14 Limit for channel 14 + * + * Valid range [0:5]. + */ + void set_power_limits(uint8_t chan1, uint8_t chan11, uint8_t chan13, uint8_t chan14) + { + data[78] = 2; // Enable bytes 30-33 to set maximum TX power + data[30] = chan1; + data[31] = chan11; + data[32] = chan13; + data[33] = chan14; + } + + /** + * @brief Disable power limits on channels 1, 11, 13 and 14 + * @note Devices will no longer comply with certfications and may cause unwanted RF interference. + */ + void disable_power_limits() + { + data[78] = 0; // disable bytes 30-33 + } + + /** + * @brief txpwr_dqb + * + * TX power can be switched between six levels. + * Level 0 represents the maximum TX power, level 5 the minimum. + * + * target_power_qdb_0, target power is 78/4=19.5dbm + * target_power_qdb_1, target power is 74/4=18.5dbm + * target_power_qdb_2, target power is 70/4=17.5dbm + * target_power_qdb_3, target power is 64/4=16dbm + * target_power_qdb_4, target power is 60/4=15dbm + * target_power_qdb_5, target power is 56/4=14dbm + */ + void set_txpwr_dqb(uint8_t level, uint8_t value) + { + if(level < 6) { + data[34 + level] = value; + } + } - [40] = 0, // target_power_index_mcs0 - [41] = 0, // target_power_index_mcs1 - [42] = 1, // target_power_index_mcs2 - [43] = 1, // target_power_index_mcs3 - [44] = 2, // target_power_index_mcs4 - [45] = 3, // target_power_index_mcs5 - [46] = 4, // target_power_index_mcs6 - [47] = 5, // target_power_index_mcs7 -*/ /** - * @brief crystal_26m_en + * @brief txpwr_index + * + * Select target power level for specific data rate according to Modulation Coding Scheme (MCS). + * The defaults are: + * + * MCS0: qdb_0 1 Mbit/s, 2 Mbit/s, 5.5 Mbit/s, 11 Mbit/s, 6 Mbit/s, 9 Mbit/s) + * MCS1: qdb_0 12 Mbit/s) + * MCS2: qdb_1 18 Mbit/s) + * MCS3: qdb_1 24 Mbit/s + * MCS4: qdb_2 36 Mbit/s + * MCS5: qdb_3 48 Mbit/s + * MCS6: qdb_4 54 Mbit/s + * MCS7: qdb_5 + */ + void set_txpwr(uint8_t mcs_index, uint8_t txpwr_qdb) + { + if(mcs_index < 8 && txpwr_qdb < 6) { + data[40 + mcs_index] = txpwr_qdb; + } + } + + /** + * @brief crystal_sel * * 0: 40MHz * 1: 26MHz * 2: 24MHz */ - void set_crystal_26m_en(uint8_t value = 1) + void set_crystal_sel(uint8_t value = 1) { data[48] = value; } @@ -293,14 +355,16 @@ struct PhyInitData { } /** - * @brief rf_cal_use_flash + * @brief RF_calibration + * + * To ensure better RF performance, it is recommend to set RF_calibration to 3, otherwise the RF performance may become poor. * * 0: RF init no RF CAL, using all RF CAL data in flash, it takes about 2ms for RF init * 1: RF init only do TX power control CAL, others using RF CAL data in flash, it takes about 20ms for RF init * 2: RF init no RF CAL, using all RF CAL data in flash, it takes about 2ms for RF init (same as 0?!) * 3: RF init do all RF CAL, it takes about 200ms for RF init */ - void set_rf_cal_use_flash(uint8_t value = 1) + void set_rf_calibration(uint8_t value = 1) { data[114] = value; } From 754158b7a35fc5163f0290132278d6bfeaafe03c Mon Sep 17 00:00:00 2001 From: mikee47 Date: Sun, 23 Jun 2024 15:18:40 +0100 Subject: [PATCH 10/10] Fix linkage --- Sming/Arch/Esp8266/Components/esp8266/component.mk | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Sming/Arch/Esp8266/Components/esp8266/component.mk b/Sming/Arch/Esp8266/Components/esp8266/component.mk index cb733c3006..a977b3e0a8 100644 --- a/Sming/Arch/Esp8266/Components/esp8266/component.mk +++ b/Sming/Arch/Esp8266/Components/esp8266/component.mk @@ -14,11 +14,11 @@ COMPONENT_DEPENDS += esp-lwip endif -COMPONENT_VARS += ENABLE_CUSTOM_PHY +COMPONENT_RELINK_VARS += ENABLE_CUSTOM_PHY ENABLE_CUSTOM_PHY ?= 0 ifeq ($(ENABLE_CUSTOM_PHY),1) - CFLAGS += -DENABLE_CUSTOM_PHY=1 - LDFLAGS += -Wl,-wrap,register_chipv6_phy -u custom_register_chipv6_phy -u get_adc_mode + COMPONENT_CXXFLAGS += -DENABLE_CUSTOM_PHY=1 + LDFLAGS += $(call Wrap,register_chipv6_phy) endif