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FEATURE REQUEST: VHDL/Verilog support #15

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SimonBuxx opened this issue Dec 18, 2017 · 0 comments
Open

FEATURE REQUEST: VHDL/Verilog support #15

SimonBuxx opened this issue Dec 18, 2017 · 0 comments
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difficult Issues that are (probably) hard to fix or to implement nice-to-have Features that would be nice to have but are not necessary

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@SimonBuxx
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This could be implemented when everything else is stable and all other features are implemented. Will probably be very hard but is a nice feature to be able to export files for FPGA tools.
@SimonBuxx SimonBuxx added difficult Issues that are (probably) hard to fix or to implement nice-to-have Features that would be nice to have but are not necessary labels Dec 18, 2017
@SimonBuxx SimonBuxx changed the title TODO: VHDL Im- and export in the future VISION: VHDL Im- and export in the future Dec 18, 2017
@SimonBuxx SimonBuxx changed the title VISION: VHDL Im- and export in the future FEATURE REQUEST: VHDL/Verilog support Nov 10, 2019
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difficult Issues that are (probably) hard to fix or to implement nice-to-have Features that would be nice to have but are not necessary
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