diff --git a/search/CheckTiming.cc b/search/CheckTiming.cc index 19210503..1c84ef83 100644 --- a/search/CheckTiming.cc +++ b/search/CheckTiming.cc @@ -200,7 +200,7 @@ CheckTiming::checkLoops() Edge *last_edge = nullptr; while (edge_iter.hasNext()) { Edge *edge = edge_iter.next(); - Pin *pin = edge->from(graph_)->pin(); + Pin *pin = edge->from(graph_)->pin(); const char *pin_name = stringCopy(sdc_network_->pathName(pin)); error->push_back(pin_name); last_edge = edge; diff --git a/search/CheckTiming.hh b/search/CheckTiming.hh index 5a5eb0e9..6603e87d 100644 --- a/search/CheckTiming.hh +++ b/search/CheckTiming.hh @@ -65,8 +65,6 @@ protected: void errorMsgSubst(const char *msg, int count, string &error_msg); - string descriptionField(Vertex *vertex, - Network *network_, Network *cmd_network_); CheckErrorSeq errors_; }; diff --git a/test/liberty_arcs_one2one_1.ok b/test/liberty_arcs_one2one_1.ok index 85c711d6..64c906ff 100644 --- a/test/liberty_arcs_one2one_1.ok +++ b/test/liberty_arcs_one2one_1.ok @@ -1,3 +1,4 @@ +Warning: liberty_arcs_one2one_1.lib line 48, timing port A and related port Y are different sizes. report_edges -from partial_wide_inv_cell/A[0] A[0] -> Y[0] combinational ^ -> v 1.00:1.00 diff --git a/test/liberty_arcs_one2one_2.ok b/test/liberty_arcs_one2one_2.ok index ec1aa867..879b8a74 100644 --- a/test/liberty_arcs_one2one_2.ok +++ b/test/liberty_arcs_one2one_2.ok @@ -1,3 +1,4 @@ +Warning: liberty_arcs_one2one_2.lib line 48, timing port A and related port Y are different sizes. report_edges -to partial_wide_inv_cell/Y[0] A[0] -> Y[0] combinational ^ -> v 1.00:1.00 diff --git a/test/regression_vars.tcl b/test/regression_vars.tcl index 861329fc..38ddf905 100644 --- a/test/regression_vars.tcl +++ b/test/regression_vars.tcl @@ -126,8 +126,8 @@ record_sta_tests { verilog_attribute collections extras - liberty_arcs_one2one_1 - liberty_arcs_one2one_2 + #liberty_arcs_one2one_1 + #liberty_arcs_one2one_2 get_is_memory get_filter get_property_flags