cpu_map.map

Release 14.7 Map P.20131013 (nt64)
Xilinx Map Application Log File for Design 'cpu'

Design Information
------------------
Command Line   : map -intstyle ise -p xc4vsx25-ff668-10 -global_opt off -cm area
-ir off -pr off -c 100 -o cpu_map.ncd cpu.ngd cpu.pcf 
Target Device  : xc4vsx25
Target Package : ff668
Target Speed   : -10
Mapper Version : virtex4 -- $Revision: 1.55 $
Mapped Date    : Thu Jun 11 19:36:15 2020

Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...
Updating timing models...

Design Summary
--------------

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:           189 out of  20,480    1%
  Number of 4 input LUTs:               188 out of  20,480    1%
Logic Distribution:
  Number of occupied Slices:            167 out of  10,240    1%
    Number of Slices containing only related logic:     167 out of     167 100%
    Number of Slices containing unrelated logic:          0 out of     167   0%
      *See NOTES below for an explanation of the effects of unrelated logic.
  Total Number of 4 input LUTs:         190 out of  20,480    1%
    Number used as logic:               188
    Number used as a route-thru:          2

  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.
  Number of bonded IOBs:                 22 out of     320    6%
  Number of BUFG/BUFGCTRLs:               1 out of      32    3%
    Number used as BUFGs:                 1

Average Fanout of Non-Clock Nets:                3.40

Peak Memory Usage:  4495 MB
Total REAL time to MAP completion:  2 secs 
Total CPU time to MAP completion:   2 secs 

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Mapping completed.
See MAP report file "cpu_map.mrp" for details.