From fe6a31b6bffd6c832847d13ef910ca90856e7235 Mon Sep 17 00:00:00 2001
From: SeongRyong Oh <59509067+SeongRyong0726@users.noreply.github.com>
Date: Thu, 21 Nov 2024 13:40:24 -0800
Subject: [PATCH] Update data.yml

---
 _data/data.yml | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/_data/data.yml b/_data/data.yml
index ac7ca7a5ae..de68d8eae5 100644
--- a/_data/data.yml
+++ b/_data/data.yml
@@ -75,13 +75,15 @@ experiences:
         company: 
         details: |
             - CS411(2023 FALL) - Develop project of end-to-end Systolic array on FPGA(PYNQ-Z2).
+            - CS230(2024 FALL)
       - role: Co-Researcher
         time: Visit UCSD for 2 weeks at November
         company: ACT Lab of UCSD (prof. Hadi Esmaeilzadeh)
         details: |
             - TBA
 # Integrating Accelerator and Cheshire which is RISC-V platform from PULP group with AXI protocol, and check functionality with bare-metal code.
-# Build 2 mode systolic array which can matmul and QR decomposition as well.
+# Build multi-functionality systolic array which can matmul and Tiled QR decomposition as well.
+# Build SW simulator for multi-functionality sistolic array, and octree traverse using bank-level parallelism.
 # Stucy backgound of robotic application