From 5ea1cd6ab3277a41eadb2724a379b99beae7b7bc Mon Sep 17 00:00:00 2001 From: Tonokip Date: Mon, 30 Nov 2020 19:36:25 -0600 Subject: [PATCH 01/71] static cosine table --- src/microstepper/cosine.v | 206 +++++++++------------------- src/microstepper/microstepper_top.v | 6 +- src/top.v | 9 +- 3 files changed, 73 insertions(+), 148 deletions(-) diff --git a/src/microstepper/cosine.v b/src/microstepper/cosine.v index 4a09583..460e5cf 100644 --- a/src/microstepper/cosine.v +++ b/src/microstepper/cosine.v @@ -1,150 +1,74 @@ module cosine ( input wire [5:0] cos_index, - output wire [7:0] cos_value, - input wire [511:0] cos_table + output wire [7:0] cos_value ); - - //reg [31:0] cos_table[0:255]; - - //assign cos_value = cos_table[cos_index*8+7:cos_index*8]; - reg [7:0] cos_r; assign cos_value = cos_r; - always @(*) case (cos_index) - 1'd0 : cos_r <= cos_table [ 7 : 0 ]; - 1'd1 : cos_r <= cos_table [ 15 : 8 ]; - 2'd2 : cos_r <= cos_table [ 23 : 16 ]; - 2'd3 : cos_r <= cos_table [ 31 : 24 ]; - 3'd4 : cos_r <= cos_table [ 39 : 32 ]; - 3'd5 : cos_r <= cos_table [ 47 : 40 ]; - 3'd6 : cos_r <= cos_table [ 55 : 48 ]; - 3'd7 : cos_r <= cos_table [ 63 : 56 ]; - 4'd8 : cos_r <= cos_table [ 71 : 64 ]; - 4'd9 : cos_r <= cos_table [ 79 : 72 ]; - 4'd10 : cos_r <= cos_table [ 87 : 80 ]; - 4'd11 : cos_r <= cos_table [ 95 : 88 ]; - 4'd12 : cos_r <= cos_table [ 103 : 96 ]; - 4'd13 : cos_r <= cos_table [ 111 : 104 ]; - 4'd14 : cos_r <= cos_table [ 119 : 112 ]; - 4'd15 : cos_r <= cos_table [ 127 : 120 ]; - 5'd16 : cos_r <= cos_table [ 135 : 128 ]; - 5'd17 : cos_r <= cos_table [ 143 : 136 ]; - 5'd18 : cos_r <= cos_table [ 151 : 144 ]; - 5'd19 : cos_r <= cos_table [ 159 : 152 ]; - 5'd20 : cos_r <= cos_table [ 167 : 160 ]; - 5'd21 : cos_r <= cos_table [ 175 : 168 ]; - 5'd22 : cos_r <= cos_table [ 183 : 176 ]; - 5'd23 : cos_r <= cos_table [ 191 : 184 ]; - 5'd24 : cos_r <= cos_table [ 199 : 192 ]; - 5'd25 : cos_r <= cos_table [ 207 : 200 ]; - 5'd26 : cos_r <= cos_table [ 215 : 208 ]; - 5'd27 : cos_r <= cos_table [ 223 : 216 ]; - 5'd28 : cos_r <= cos_table [ 231 : 224 ]; - 5'd29 : cos_r <= cos_table [ 239 : 232 ]; - 5'd30 : cos_r <= cos_table [ 247 : 240 ]; - 5'd31 : cos_r <= cos_table [ 255 : 248 ]; - 6'd32 : cos_r <= cos_table [ 263 : 256 ]; - 6'd33 : cos_r <= cos_table [ 271 : 264 ]; - 6'd34 : cos_r <= cos_table [ 279 : 272 ]; - 6'd35 : cos_r <= cos_table [ 287 : 280 ]; - 6'd36 : cos_r <= cos_table [ 295 : 288 ]; - 6'd37 : cos_r <= cos_table [ 303 : 296 ]; - 6'd38 : cos_r <= cos_table [ 311 : 304 ]; - 6'd39 : cos_r <= cos_table [ 319 : 312 ]; - 6'd40 : cos_r <= cos_table [ 327 : 320 ]; - 6'd41 : cos_r <= cos_table [ 335 : 328 ]; - 6'd42 : cos_r <= cos_table [ 343 : 336 ]; - 6'd43 : cos_r <= cos_table [ 351 : 344 ]; - 6'd44 : cos_r <= cos_table [ 359 : 352 ]; - 6'd45 : cos_r <= cos_table [ 367 : 360 ]; - 6'd46 : cos_r <= cos_table [ 375 : 368 ]; - 6'd47 : cos_r <= cos_table [ 383 : 376 ]; - 6'd48 : cos_r <= cos_table [ 391 : 384 ]; - 6'd49 : cos_r <= cos_table [ 399 : 392 ]; - 6'd50 : cos_r <= cos_table [ 407 : 400 ]; - 6'd51 : cos_r <= cos_table [ 415 : 408 ]; - 6'd52 : cos_r <= cos_table [ 423 : 416 ]; - 6'd53 : cos_r <= cos_table [ 431 : 424 ]; - 6'd54 : cos_r <= cos_table [ 439 : 432 ]; - 6'd55 : cos_r <= cos_table [ 447 : 440 ]; - 6'd56 : cos_r <= cos_table [ 455 : 448 ]; - 6'd57 : cos_r <= cos_table [ 463 : 456 ]; - 6'd58 : cos_r <= cos_table [ 471 : 464 ]; - 6'd59 : cos_r <= cos_table [ 479 : 472 ]; - 6'd60 : cos_r <= cos_table [ 487 : 480 ]; - 6'd61 : cos_r <= cos_table [ 495 : 488 ]; - 6'd62 : cos_r <= cos_table [ 503 : 496 ]; - default : cos_r <= cos_table [ 511 : 504 ]; + 1'd0: cos_r <= 255; + 1'd1: cos_r <= 255; + 2'd2: cos_r <= 255; + 2'd3: cos_r <= 254; + 3'd4: cos_r <= 254; + 3'd5: cos_r <= 253; + 3'd6: cos_r <= 252; + 3'd7: cos_r <= 251; + 4'd8: cos_r <= 250; + 4'd9: cos_r <= 249; + 4'd10: cos_r <= 247; + 4'd11: cos_r <= 246; + 4'd12: cos_r <= 244; + 4'd13: cos_r <= 242; + 4'd14: cos_r <= 240; + 4'd15: cos_r <= 238; + 5'd16: cos_r <= 236; + 5'd17: cos_r <= 233; + 5'd18: cos_r <= 231; + 5'd19: cos_r <= 228; + 5'd20: cos_r <= 225; + 5'd21: cos_r <= 222; + 5'd22: cos_r <= 219; + 5'd23: cos_r <= 215; + 5'd24: cos_r <= 212; + 5'd25: cos_r <= 208; + 5'd26: cos_r <= 205; + 5'd27: cos_r <= 201; + 5'd28: cos_r <= 197; + 5'd29: cos_r <= 193; + 5'd30: cos_r <= 189; + 5'd31: cos_r <= 185; + 6'd32: cos_r <= 180; + 6'd33: cos_r <= 176; + 6'd34: cos_r <= 171; + 6'd35: cos_r <= 167; + 6'd36: cos_r <= 162; + 6'd37: cos_r <= 157; + 6'd38: cos_r <= 152; + 6'd39: cos_r <= 147; + 6'd40: cos_r <= 142; + 6'd41: cos_r <= 136; + 6'd42: cos_r <= 131; + 6'd43: cos_r <= 126; + 6'd44: cos_r <= 120; + 6'd45: cos_r <= 115; + 6'd46: cos_r <= 109; + 6'd47: cos_r <= 103; + 6'd48: cos_r <= 98; + 6'd49: cos_r <= 92; + 6'd50: cos_r <= 86; + 6'd51: cos_r <= 80; + 6'd52: cos_r <= 74; + 6'd53: cos_r <= 68; + 6'd54: cos_r <= 62; + 6'd55: cos_r <= 56; + 6'd56: cos_r <= 50; + 6'd57: cos_r <= 44; + 6'd58: cos_r <= 37; + 6'd59: cos_r <= 31; + 6'd60: cos_r <= 25; + 6'd61: cos_r <= 19; + 6'd62: cos_r <= 13; + default: cos_r <= 6; endcase - -/* - initial begin - cos_table[0] = 8'd255; - cos_table[1] = 8'd255; - cos_table[2] = 8'd255; - cos_table[3] = 8'd254; - cos_table[4] = 8'd254; - cos_table[5] = 8'd253; - cos_table[6] = 8'd252; - cos_table[7] = 8'd251; - cos_table[8] = 8'd250; - cos_table[9] = 8'd249; - cos_table[10] = 8'd247; - cos_table[11] = 8'd246; - cos_table[12] = 8'd244; - cos_table[13] = 8'd242; - cos_table[14] = 8'd240; - cos_table[15] = 8'd238; - cos_table[16] = 8'd236; - cos_table[17] = 8'd233; - cos_table[18] = 8'd231; - cos_table[19] = 8'd228; - cos_table[20] = 8'd225; - cos_table[21] = 8'd222; - cos_table[22] = 8'd219; - cos_table[23] = 8'd215; - cos_table[24] = 8'd212; - cos_table[25] = 8'd208; - cos_table[26] = 8'd205; - cos_table[27] = 8'd201; - cos_table[28] = 8'd197; - cos_table[29] = 8'd193; - cos_table[30] = 8'd189; - cos_table[31] = 8'd185; - cos_table[32] = 8'd180; - cos_table[33] = 8'd176; - cos_table[34] = 8'd171; - cos_table[35] = 8'd167; - cos_table[36] = 8'd162; - cos_table[37] = 8'd157; - cos_table[38] = 8'd152; - cos_table[39] = 8'd147; - cos_table[40] = 8'd142; - cos_table[41] = 8'd136; - cos_table[42] = 8'd131; - cos_table[43] = 8'd126; - cos_table[44] = 8'd120; - cos_table[45] = 8'd115; - cos_table[46] = 8'd109; - cos_table[47] = 8'd103; - cos_table[48] = 8'd98; - cos_table[49] = 8'd92; - cos_table[50] = 8'd86; - cos_table[51] = 8'd80; - cos_table[52] = 8'd74; - cos_table[53] = 8'd68; - cos_table[54] = 8'd62; - cos_table[55] = 8'd56; - cos_table[56] = 8'd50; - cos_table[57] = 8'd44; - cos_table[58] = 8'd37; - cos_table[59] = 8'd31; - cos_table[60] = 8'd25; - cos_table[61] = 8'd19; - cos_table[62] = 8'd13; - cos_table[63] = 8'd6; - end - */ endmodule diff --git a/src/microstepper/microstepper_top.v b/src/microstepper/microstepper_top.v index e2438aa..7f33371 100644 --- a/src/microstepper/microstepper_top.v +++ b/src/microstepper/microstepper_top.v @@ -17,7 +17,7 @@ module microstepper_top ( input [7:0] config_chargepump_period, input config_invert_highside, input config_invert_lowside, - input [511:0] cos_table, + //input [511:0] cos_table, input step, input dir, input enable @@ -180,13 +180,13 @@ end cosine cosine0 ( .cos_index(cos_index1), .cos_value(pwm1), - .cos_table(cos_table) + //.cos_table(cos_table) ); cosine cosine1 ( .cos_index(cos_index2), .cos_value(pwm2), - .cos_table(cos_table) + //.cos_table(cos_table) ); analog_out ao0 ( diff --git a/src/top.v b/src/top.v index f7d987b..e23da82 100644 --- a/src/top.v +++ b/src/top.v @@ -116,6 +116,7 @@ module top ( reg [7:0] config_chargepump_period = 91; reg config_invert_highside = 0; reg config_invert_lowside = 0; + /* reg [511:0] cos_table; initial begin @@ -184,7 +185,7 @@ module top ( cos_table [ 503 : 496 ] = 13 ; cos_table [ 511 : 504 ] = 6 ; end - +*/ wire step; wire dir; reg enable; @@ -223,7 +224,7 @@ module top ( .config_chargepump_period (config_chargepump_period), .config_invert_highside (config_invert_highside), .config_invert_lowside (config_invert_lowside), - .cos_table (cos_table), + //.cos_table (cos_table), .step (step), .dir (dir), .enable(enable), @@ -326,7 +327,7 @@ module top ( config_invert_highside <= word_data_received[1]; config_invert_lowside <= word_data_received[0]; end - +/* // Write to Cosine Table `CMD_COSINE_CONFIG: begin //config_cosine_table[word_data_received[35:32]] <= word_data_received[31:0]; @@ -336,7 +337,7 @@ module top ( //cos_table[word_data_received[35:32]+1] <= word_data_received[15:8]; //cos_table[word_data_received[35:32]] <= word_data_received[7:0]; end - +*/ // API Version `CMD_API_VERSION: begin word_send_data[7:0] <= `VERSION_PATCH; From 1ad51db2f7a671c076e59f511d5c53a7e9d068a9 Mon Sep 17 00:00:00 2001 From: johnnyr Date: Tue, 1 Dec 2020 01:41:35 -0600 Subject: [PATCH 02/71] preset params for mytimers --- src/microstepper/microstepper_top.v | 12 ++++++------ src/microstepper/mytimer_10.v | 29 +++++++++++++++++++++++++++++ src/microstepper/mytimer_8.v | 29 +++++++++++++++++++++++++++++ 3 files changed, 64 insertions(+), 6 deletions(-) create mode 100644 src/microstepper/mytimer_10.v create mode 100644 src/microstepper/mytimer_8.v diff --git a/src/microstepper/microstepper_top.v b/src/microstepper/microstepper_top.v index 7f33371..5df12af 100644 --- a/src/microstepper/microstepper_top.v +++ b/src/microstepper/microstepper_top.v @@ -103,7 +103,7 @@ end s4r <= {s4r[0], s4}; end - mytimer #( + mytimer_10 #( .WIDTH(10) ) offtimer0 ( .clk (clk), @@ -113,7 +113,7 @@ end .timer (off_timer0) ); - mytimer #( + mytimer_10 #( .WIDTH(10) ) offtimer1 ( .clk (clk), @@ -123,7 +123,7 @@ end .timer (off_timer1) ); - mytimer #( + mytimer_8 #( .WIDTH(8) ) blanktimer0 ( .clk (clk), @@ -133,7 +133,7 @@ end .timer (blank_timer0) ); - mytimer #( + mytimer_8 #( .WIDTH(8) ) blanktimer1 ( .clk (clk), @@ -143,7 +143,7 @@ end .timer (blank_timer1) ); - mytimer #( + mytimer_8 #( .WIDTH(8) ) minimumontimer0 ( .clk (clk), @@ -153,7 +153,7 @@ end .timer (minimum_on_timer0) ); - mytimer #( + mytimer_8 #( .WIDTH(8) ) minimumontimer1 ( .clk (clk), diff --git a/src/microstepper/mytimer_10.v b/src/microstepper/mytimer_10.v new file mode 100644 index 0000000..6648329 --- /dev/null +++ b/src/microstepper/mytimer_10.v @@ -0,0 +1,29 @@ +module mytimer_10 ( + clk, + resetn, + start_enable, + start_time, + timer +); + parameter WIDTH = 10; + + input clk; + input resetn; + input start_enable; + input [WIDTH-1:0] start_time; + output [WIDTH-1:0] timer; + + reg [WIDTH-1:0] counter; + + assign timer = counter; + + always @(posedge clk) begin + if (!resetn) + counter <= 0; + else if( start_enable ) + counter <= start_time; + else if( counter > 0 ) + counter <= counter - 1'b1; +end + +endmodule diff --git a/src/microstepper/mytimer_8.v b/src/microstepper/mytimer_8.v new file mode 100644 index 0000000..1710bab --- /dev/null +++ b/src/microstepper/mytimer_8.v @@ -0,0 +1,29 @@ +module mytimer_8 ( + clk, + resetn, + start_enable, + start_time, + timer +); + parameter WIDTH = 8; + + input clk; + input resetn; + input start_enable; + input [WIDTH-1:0] start_time; + output [WIDTH-1:0] timer; + + reg [WIDTH-1:0] counter; + + assign timer = counter; + + always @(posedge clk) begin + if (!resetn) + counter <= 0; + else if( start_enable ) + counter <= start_time; + else if( counter > 0 ) + counter <= counter - 1'b1; +end + +endmodule From b36b9ac40a22cc05ed5989c77c5e40d2b71afe3b Mon Sep 17 00:00:00 2001 From: johnnyr Date: Tue, 1 Dec 2020 18:28:01 -0600 Subject: [PATCH 03/71] mscontrol --- src/microstepper/microstepper_control.v | 105 +++++++++++++++++++ src/microstepper/microstepper_top.v | 129 ++++++++---------------- 2 files changed, 147 insertions(+), 87 deletions(-) create mode 100644 src/microstepper/microstepper_control.v diff --git a/src/microstepper/microstepper_control.v b/src/microstepper/microstepper_control.v new file mode 100644 index 0000000..68e9c04 --- /dev/null +++ b/src/microstepper/microstepper_control.v @@ -0,0 +1,105 @@ +module microstepper_control ( + input clk, + output [3:0] s_l, + output [3:0] s_h, + input [9:0] config_fastdecay_threshold, + input config_invert_highside, + input config_invert_lowside, + input step, + input dir, + input enable, + input analog_cmp1, + input analog_cmp2, + output fault, + input s1, + input s2, + input s3, + input s4, + output offtimer_en0, + output offtimer_en0, + output a_starting, + output b_starting, + output [7:0] phase_ct, + input [7:0] blank_timer0, + input [7:0] blank_timer1, + input [9:0] off_timer0, + input [9:0] off_timer1, + input [7:0] minimum_on_timer0, + input [7:0] minimum_on_timer1, +); + reg [7:0] phase_ct; + + always @(posedge step) begin + phase_ct <= phase_ct + (dir ? 1 : -1); + end + + wire s1; + wire s2; + wire s3; + wire s4; + + wire overCurrent0 = off_timer0 > 0; + wire overCurrent1 = off_timer1 > 0; + + wire fastDecay0 = off_timer0 >= config_fastdecay_threshold; + wire fastDecay1 = off_timer1 >= config_fastdecay_threshold; + + wire slowDecay0 = overCurrent0 && fastDecay0 == 0; + wire slowDecay1 = overCurrent1 && fastDecay1 == 0; + + wire fault0 = (minimum_on_timer0 > 0) && overCurrent0; + wire fault1 = (minimum_on_timer1 > 0) && overCurrent1; + wire fault = fault0 | fault1; + + reg [1:0] s1r, s2r, s3r, s4r; + wire phase_a1_h, phase_a1_l, phase_a2_h, phase_a2_l; + wire phase_b1_h, phase_b1_l, phase_b2_h, phase_b2_l; + + assign s_l[0] = !(phase_a1_l | fault); + assign s_l[1] = !(phase_a2_l | fault); + assign s_l[2] = !(phase_b1_l | fault); + assign s_l[3] = !(phase_b2_l | fault); + + assign s_h[0] = !(phase_a1_h | fault); + assign s_h[1] = !(phase_a2_h | fault); + assign s_h[2] = !(phase_b1_h | fault); + assign s_h[3] = !(phase_b2_h | fault); + + assign phase_a1_h = config_invert_highside ^ (slowDecay0 | (fastDecay0 ? s1r[1] : ~s1r[1])); + assign phase_a1_l = config_invert_lowside ^ (fastDecay0 ? ~s1r[1] : (slowDecay0 ? 1'b0 : s1r[1])); + assign phase_a2_h = config_invert_highside ^ (slowDecay0 | (fastDecay0 ? s2r[1] : ~s2r[1])); + assign phase_a2_l = config_invert_lowside ^ (fastDecay0 ? ~s2r[1] : (slowDecay0 ? 1'b0 : s2r[1])); + + assign phase_b1_h = config_invert_highside ^ (slowDecay1 | (fastDecay1 ? s3r[1] : ~s3r[1])); + assign phase_b1_l = config_invert_lowside ^ (fastDecay1 ? ~s3r[1] : (slowDecay1 ? 1'b0 : s3r[1])); + assign phase_b2_h = config_invert_highside ^ (slowDecay1 | (fastDecay1 ? s4r[1] : ~s4r[1])); + assign phase_b2_l = config_invert_lowside ^ (fastDecay1 ? ~s4r[1] : (slowDecay1 ? 1'b0 : s4r[1])); + + + wire s1_starting = s1r == 2'b10; + wire s2_starting = s2r == 2'b10; + wire s3_starting = s3r == 2'b10; + wire s4_starting = s4r == 2'b10; + + assign offtimer_en0 = analog_cmp1 & blank_timer0 == 0 & overCurrent0 == 0; + assign offtimer_en0 = analog_cmp2 & blank_timer1 == 0 & overCurrent1 == 0; + assign a_starting = s1_starting | s2_starting; + assign b_starting = s3_starting | s4_starting; + +`ifdef FORMAL + always @(*) begin + assert (!(phase_a1_l == 0 && phase_a1_h == 0)); + assert (!(phase_a2_l == 0 && phase_a2_h == 0)); + assert (!(phase_b1_l == 0 && phase_b1_h == 0)); + assert (!(phase_b2_l == 0 && phase_b2_h == 0)); + end +`endif + + always @(posedge clk) begin + s1r <= {s1r[0], s1}; + s2r <= {s2r[0], s2}; + s3r <= {s3r[0], s3}; + s4r <= {s4r[0], s4}; + end + +endmodule \ No newline at end of file diff --git a/src/microstepper/microstepper_top.v b/src/microstepper/microstepper_top.v index 5df12af..f9df678 100644 --- a/src/microstepper/microstepper_top.v +++ b/src/microstepper/microstepper_top.v @@ -20,95 +20,50 @@ module microstepper_top ( //input [511:0] cos_table, input step, input dir, - input enable + input enable, + output fault, +); + wire [5:0] cos_index1; + wire [5:0] cos_index2; + wire [7:0] pwm1; + wire [7:0] pwm2; + + microstepper_control m_control_0( + .clk(clk), + .s_l(s_l), + .s_h(s_h), + .config_fastdecay_threshold(config_fastdecay_threshold), + .config_invert_highside(config_invert_highside), + .config_invert_lowside(config_invert_lowside), + .step(step), + .dir(dir), + .enable(enable), + .analog_cmp1(analog_cmp1), + .analog_cmp2(analog_cmp2), + .fault(fault), + .s1(s1), + .s2(s2), + .s3(s3), + .s4(s4), + .offtimer_en0(offtimer_en0), + .offtimer_en0(offtimer_en0), + .a_starting(a_starting), + .b_starting(b_starting), + .phase_ct(phase_ct), + .blank_timer0(blank_timer0), + .blank_timer1(blank_timer1), + .off_timer0(off_timer0), + .off_timer1(off_timer1), + .minimum_on_timer0(minimum_on_timer0), + .minimum_on_timer1(minimum_on_timer1), ); - - reg [7:0] phase_ct; - - always @(posedge step) begin - phase_ct <= phase_ct + (dir ? 1 : -1); -end - - wire [5:0] cos_index1; - wire [5:0] cos_index2; - wire s1; - wire s2; - wire s3; - wire s4; - wire [7:0] pwm1; - wire [7:0] pwm2; - - reg [7:0] blank_timer0; - reg [7:0] blank_timer1; - reg [9:0] off_timer0; - reg [9:0] off_timer1; - reg [7:0] minimum_on_timer0; - reg [7:0] minimum_on_timer1; - - wire overCurrent0 = off_timer0 > 0; - wire overCurrent1 = off_timer1 > 0; - - wire fastDecay0 = off_timer0 >= config_fastdecay_threshold; - wire fastDecay1 = off_timer1 >= config_fastdecay_threshold; - - wire slowDecay0 = overCurrent0 && fastDecay0 == 0; - wire slowDecay1 = overCurrent1 && fastDecay1 == 0; - - wire fault0 = (minimum_on_timer0 > 0) && overCurrent0; - wire fault1 = (minimum_on_timer1 > 0) && overCurrent1; - wire fault = fault0 | fault1; - - reg [1:0] s1r, s2r, s3r, s4r; - wire phase_a1_h, phase_a1_l, phase_a2_h, phase_a2_l; - wire phase_b1_h, phase_b1_l, phase_b2_h, phase_b2_l; - - assign s_l[0] = !(phase_a1_l | fault); - assign s_l[1] = !(phase_a2_l | fault); - assign s_l[2] = !(phase_b1_l | fault); - assign s_l[3] = !(phase_b2_l | fault); - - assign s_h[0] = !(phase_a1_h | fault); - assign s_h[1] = !(phase_a2_h | fault); - assign s_h[2] = !(phase_b1_h | fault); - assign s_h[3] = !(phase_b2_h | fault); - - assign phase_a1_h = config_invert_highside ^ (slowDecay0 | (fastDecay0 ? s1r[1] : ~s1r[1])); - assign phase_a1_l = config_invert_lowside ^ (fastDecay0 ? ~s1r[1] : (slowDecay0 ? 1'b0 : s1r[1])); - assign phase_a2_h = config_invert_highside ^ (slowDecay0 | (fastDecay0 ? s2r[1] : ~s2r[1])); - assign phase_a2_l = config_invert_lowside ^ (fastDecay0 ? ~s2r[1] : (slowDecay0 ? 1'b0 : s2r[1])); - - assign phase_b1_h = config_invert_highside ^ (slowDecay1 | (fastDecay1 ? s3r[1] : ~s3r[1])); - assign phase_b1_l = config_invert_lowside ^ (fastDecay1 ? ~s3r[1] : (slowDecay1 ? 1'b0 : s3r[1])); - assign phase_b2_h = config_invert_highside ^ (slowDecay1 | (fastDecay1 ? s4r[1] : ~s4r[1])); - assign phase_b2_l = config_invert_lowside ^ (fastDecay1 ? ~s4r[1] : (slowDecay1 ? 1'b0 : s4r[1])); - - wire s1_starting = s1r == 2'b10; - wire s2_starting = s2r == 2'b10; - wire s3_starting = s3r == 2'b10; - wire s4_starting = s4r == 2'b10; - -`ifdef FORMAL - always @(*) begin - assert (!(phase_a1_l == 0 && phase_a1_h == 0)); - assert (!(phase_a2_l == 0 && phase_a2_h == 0)); - assert (!(phase_b1_l == 0 && phase_b1_h == 0)); - assert (!(phase_b2_l == 0 && phase_b2_h == 0)); - end -`endif - - always @(posedge clk) begin - s1r <= {s1r[0], s1}; - s2r <= {s2r[0], s2}; - s3r <= {s3r[0], s3}; - s4r <= {s4r[0], s4}; - end mytimer_10 #( .WIDTH(10) ) offtimer0 ( .clk (clk), .resetn (resetn), - .start_enable(analog_cmp1 & blank_timer0 == 0 & overCurrent0 == 0), + .start_enable(offtimer_en0), .start_time (config_offtime), .timer (off_timer0) ); @@ -118,7 +73,7 @@ end ) offtimer1 ( .clk (clk), .resetn (resetn), - .start_enable(analog_cmp2 & blank_timer1 == 0 & overCurrent1 == 0), + .start_enable(offtimer_en1), .start_time (config_offtime), .timer (off_timer1) ); @@ -128,7 +83,7 @@ end ) blanktimer0 ( .clk (clk), .resetn (resetn), - .start_enable(s1_starting | s2_starting), + .start_enable(a_starting), .start_time (config_blanktime), .timer (blank_timer0) ); @@ -138,7 +93,7 @@ end ) blanktimer1 ( .clk (clk), .resetn (resetn), - .start_enable(s3_starting | s4_starting), + .start_enable(b_starting), .start_time (config_blanktime), .timer (blank_timer1) ); @@ -148,7 +103,7 @@ end ) minimumontimer0 ( .clk (clk), .resetn (resetn), - .start_enable(s1_starting | s2_starting), + .start_enable(a_starting), .start_time (config_minimum_on_time), .timer (minimum_on_timer0) ); @@ -158,7 +113,7 @@ end ) minimumontimer1 ( .clk (clk), .resetn (resetn), - .start_enable(s3_starting | s4_starting), + .start_enable(b_starting), .start_time (config_minimum_on_time), .timer (minimum_on_timer1) ); From 696784bf6b681bd7ae2b70ea082c2a889376eac9 Mon Sep 17 00:00:00 2001 From: Tonokip Date: Tue, 1 Dec 2020 20:03:15 -0600 Subject: [PATCH 04/71] reuse mytimer for mytimer_8 and mytimer_10 --- src/microstepper/mytimer_10.v | 28 +++++++++------------------- src/microstepper/mytimer_8.v | 28 +++++++++------------------- 2 files changed, 18 insertions(+), 38 deletions(-) diff --git a/src/microstepper/mytimer_10.v b/src/microstepper/mytimer_10.v index 6648329..93a73ad 100644 --- a/src/microstepper/mytimer_10.v +++ b/src/microstepper/mytimer_10.v @@ -5,25 +5,15 @@ module mytimer_10 ( start_time, timer ); - parameter WIDTH = 10; - input clk; - input resetn; - input start_enable; - input [WIDTH-1:0] start_time; - output [WIDTH-1:0] timer; - - reg [WIDTH-1:0] counter; - - assign timer = counter; - - always @(posedge clk) begin - if (!resetn) - counter <= 0; - else if( start_enable ) - counter <= start_time; - else if( counter > 0 ) - counter <= counter - 1'b1; -end + mytimer #( + .WIDTH(8) + ) mytimer8 ( + .clk (clk), + .resetn (resetn), + .start_enable(start_enable), + .start_time (start_time), + .timer (timer) + ); endmodule diff --git a/src/microstepper/mytimer_8.v b/src/microstepper/mytimer_8.v index 1710bab..c61be86 100644 --- a/src/microstepper/mytimer_8.v +++ b/src/microstepper/mytimer_8.v @@ -5,25 +5,15 @@ module mytimer_8 ( start_time, timer ); - parameter WIDTH = 8; - input clk; - input resetn; - input start_enable; - input [WIDTH-1:0] start_time; - output [WIDTH-1:0] timer; - - reg [WIDTH-1:0] counter; - - assign timer = counter; - - always @(posedge clk) begin - if (!resetn) - counter <= 0; - else if( start_enable ) - counter <= start_time; - else if( counter > 0 ) - counter <= counter - 1'b1; -end + mytimer #( + .WIDTH(8) + ) mytimer8 ( + .clk (clk), + .resetn (resetn), + .start_enable(start_enable), + .start_time (start_time), + .timer (timer) + ); endmodule From d775cb8d3d6e0c89ac60db37005f82a149e3b629 Mon Sep 17 00:00:00 2001 From: Tonokip Date: Tue, 1 Dec 2020 20:42:40 -0600 Subject: [PATCH 05/71] timer fixes and missing wires --- src/microstepper/microstepper_control.v | 6 ++-- src/microstepper/microstepper_top.v | 38 ++++++++++++------------- src/microstepper/mytimer_10.v | 11 +++++-- src/microstepper/mytimer_8.v | 9 +++++- 4 files changed, 39 insertions(+), 25 deletions(-) diff --git a/src/microstepper/microstepper_control.v b/src/microstepper/microstepper_control.v index 68e9c04..17e0576 100644 --- a/src/microstepper/microstepper_control.v +++ b/src/microstepper/microstepper_control.v @@ -16,7 +16,7 @@ module microstepper_control ( input s3, input s4, output offtimer_en0, - output offtimer_en0, + output offtimer_en1, output a_starting, output b_starting, output [7:0] phase_ct, @@ -82,7 +82,7 @@ module microstepper_control ( wire s4_starting = s4r == 2'b10; assign offtimer_en0 = analog_cmp1 & blank_timer0 == 0 & overCurrent0 == 0; - assign offtimer_en0 = analog_cmp2 & blank_timer1 == 0 & overCurrent1 == 0; + assign offtimer_en1 = analog_cmp2 & blank_timer1 == 0 & overCurrent1 == 0; assign a_starting = s1_starting | s2_starting; assign b_starting = s3_starting | s4_starting; @@ -102,4 +102,4 @@ module microstepper_control ( s4r <= {s4r[0], s4}; end -endmodule \ No newline at end of file +endmodule diff --git a/src/microstepper/microstepper_top.v b/src/microstepper/microstepper_top.v index f9df678..c6e92e5 100644 --- a/src/microstepper/microstepper_top.v +++ b/src/microstepper/microstepper_top.v @@ -27,6 +27,18 @@ module microstepper_top ( wire [5:0] cos_index2; wire [7:0] pwm1; wire [7:0] pwm2; + + wire s1, s2, s3, s4; + wire offtimer_en0, offtimer_en1; + + wire a_starting, b_starting; + wire [7:0] phase_ct; + wire [7:0] blank_timer0; + wire [7:0] blank_timer1; + wire [9:0] off_timer0; + wire [9:0] off_timer1; + wire [7:0] minimum_on_timer0; + wire [7:0] minimum_on_timer1; microstepper_control m_control_0( .clk(clk), @@ -46,7 +58,7 @@ module microstepper_top ( .s3(s3), .s4(s4), .offtimer_en0(offtimer_en0), - .offtimer_en0(offtimer_en0), + .offtimer_en1(offtimer_en1), .a_starting(a_starting), .b_starting(b_starting), .phase_ct(phase_ct), @@ -58,9 +70,7 @@ module microstepper_top ( .minimum_on_timer1(minimum_on_timer1), ); - mytimer_10 #( - .WIDTH(10) - ) offtimer0 ( + mytimer_10 offtimer0 ( .clk (clk), .resetn (resetn), .start_enable(offtimer_en0), @@ -68,9 +78,7 @@ module microstepper_top ( .timer (off_timer0) ); - mytimer_10 #( - .WIDTH(10) - ) offtimer1 ( + mytimer_10 offtimer1 ( .clk (clk), .resetn (resetn), .start_enable(offtimer_en1), @@ -78,9 +86,7 @@ module microstepper_top ( .timer (off_timer1) ); - mytimer_8 #( - .WIDTH(8) - ) blanktimer0 ( + mytimer_8 blanktimer0 ( .clk (clk), .resetn (resetn), .start_enable(a_starting), @@ -88,9 +94,7 @@ module microstepper_top ( .timer (blank_timer0) ); - mytimer_8 #( - .WIDTH(8) - ) blanktimer1 ( + mytimer_8 blanktimer1 ( .clk (clk), .resetn (resetn), .start_enable(b_starting), @@ -98,9 +102,7 @@ module microstepper_top ( .timer (blank_timer1) ); - mytimer_8 #( - .WIDTH(8) - ) minimumontimer0 ( + mytimer_8 minimumontimer0 ( .clk (clk), .resetn (resetn), .start_enable(a_starting), @@ -108,9 +110,7 @@ module microstepper_top ( .timer (minimum_on_timer0) ); - mytimer_8 #( - .WIDTH(8) - ) minimumontimer1 ( + mytimer_8 minimumontimer1 ( .clk (clk), .resetn (resetn), .start_enable(b_starting), diff --git a/src/microstepper/mytimer_10.v b/src/microstepper/mytimer_10.v index 93a73ad..5ce98e4 100644 --- a/src/microstepper/mytimer_10.v +++ b/src/microstepper/mytimer_10.v @@ -5,10 +5,17 @@ module mytimer_10 ( start_time, timer ); + localparam WIDTH = 10; + + input clk; + input resetn; + input start_enable; + input [WIDTH-1:0] start_time; + output [WIDTH-1:0] timer; mytimer #( - .WIDTH(8) - ) mytimer8 ( + .WIDTH(WIDTH) + ) mytimer10 ( .clk (clk), .resetn (resetn), .start_enable(start_enable), diff --git a/src/microstepper/mytimer_8.v b/src/microstepper/mytimer_8.v index c61be86..38f495d 100644 --- a/src/microstepper/mytimer_8.v +++ b/src/microstepper/mytimer_8.v @@ -5,9 +5,16 @@ module mytimer_8 ( start_time, timer ); + localparam WIDTH = 8; + + input clk; + input resetn; + input start_enable; + input [WIDTH-1:0] start_time; + output [WIDTH-1:0] timer; mytimer #( - .WIDTH(8) + .WIDTH(WIDTH) ) mytimer8 ( .clk (clk), .resetn (resetn), From 29b19b0b9a84506bd596785f5248d81e5d55372a Mon Sep 17 00:00:00 2001 From: johnnyr Date: Fri, 4 Dec 2020 01:27:35 -0600 Subject: [PATCH 06/71] testbench upgrades. part 1 --- Makefile | 6 +- sim_microstepper.ys | 14 ++++ testbench/coil.v | 30 ++++++++ testbench/microstepper_tb.v | 133 ++++++++++++++++++++++++++++++++++++ testbench/pwm_duty.v | 40 +++++++++++ testbench/quad_tb.v | 2 +- 6 files changed, 223 insertions(+), 2 deletions(-) create mode 100644 sim_microstepper.ys create mode 100644 testbench/coil.v create mode 100644 testbench/microstepper_tb.v create mode 100644 testbench/pwm_duty.v diff --git a/Makefile b/Makefile index c794dc0..98ca4d1 100755 --- a/Makefile +++ b/Makefile @@ -57,8 +57,12 @@ formal: lint: verible-verilog-lint src/*.v -testbench: +testbench_quad_encoder: yosys sim.ys + gtkwave testbench/quad_enc.vcd +testbench_microstepper: + yosys sim_microstepper.ys + gtkwave testbench/microstepper.vcd .SECONDARY: .PHONY: all prog clean testbench formal diff --git a/sim_microstepper.ys b/sim_microstepper.ys new file mode 100644 index 0000000..3d86003 --- /dev/null +++ b/sim_microstepper.ys @@ -0,0 +1,14 @@ + +read_verilog -sv testbench/microstepper_tb.v \ + src/microstepper/analog_out.v \ + src/microstepper/chargepump.v \ + src/microstepper/cosine.v \ + src/microstepper/microstep_counter.v \ + src/microstepper/microstepper_control.v \ + src/microstepper/mytimer_8.v \ + src/microstepper/mytimer_10.v \ + src/microstepper/mytimer.v + +prep -top testbench +show microstepper_top +sim -n 40000 -clock clk -vcd testbench/microstepper.vcd diff --git a/testbench/coil.v b/testbench/coil.v new file mode 100644 index 0000000..3a2c1ce --- /dev/null +++ b/testbench/coil.v @@ -0,0 +1,30 @@ +// Linear current ramp +module coil ( + input clk, + input resetn, + input s_l1, + input s_h1, + input s_l2, + input s_h2, + output [12:0] current, +); + reg [12:0] current; + reg [7:0] cnt; + + wire on = (s_l1 && s_h2) | (s_l1 && s_h2); + + always @(posedge clk) begin + if (!resetn) begin + current <= 0; + end + else begin + if ( on ) begin + current <= current + 1; + end + else begin + current <= 0; + end + end + end +endmodule +//(cnt[2]== 1) \ No newline at end of file diff --git a/testbench/microstepper_tb.v b/testbench/microstepper_tb.v new file mode 100644 index 0000000..4c54dba --- /dev/null +++ b/testbench/microstepper_tb.v @@ -0,0 +1,133 @@ +`include "../src/microstepper/microstepper_top.v" +`include "coil.v" +`include "pwm_duty.v" +`timescale 1ns/100ps + +module testbench( + input clk, + output [3:0] s_l, + output [3:0] s_h, + output analog_cmp1, + output analog_out1, + output analog_cmp2, + output analog_out2, + output chargepump_pin, + output fault, + output [7:0] target_current1, +); + + reg step; + reg dir; + reg enable; + reg [7:0] target_current1; + reg [7:0] target_current2; + reg [7:0] current1; + reg [7:0] current2; + reg [9:0] config_offtime; + reg [7:0] config_blanktime; + reg [9:0] config_fastdecay_threshold; + reg [7:0] config_minimum_on_time; + reg [10:0] config_current_threshold; + reg [7:0] config_chargepump_period; + reg config_invert_highside; + reg config_invert_lowside; + + wire resetn; + reg [7:0] resetn_counter = 0; + + assign resetn = &resetn_counter; + always @(posedge clk) begin + if (!resetn) resetn_counter <= resetn_counter +1; + end + + reg analog_cmp1; + reg analog_cmp2; + reg [40:0] step_clock; + reg [20:0] cnt; + always @(posedge clk) begin + if (!resetn) begin + cnt <= 0; + analog_cmp1 <= 0; + analog_cmp2 <= 0; + step <= 1; + enable <= 1; + config_offtime = 810; + config_blanktime = 27; + config_fastdecay_threshold = 706; + config_minimum_on_time = 54; + config_current_threshold = 1024; + config_chargepump_period = 91; + config_invert_highside = 0; + config_invert_lowside = 0; + step_clock = 0; + end + else begin + cnt <= cnt + 1; + step_clock <= step_clock + 1; + step <= step_clock[9]; + if (current1 > target_current1) analog_cmp1 <= 1; + if (current2 > target_current2) analog_cmp2 <= 1; + if (cnt <= 20'hAEC) begin + dir <= 1; + end + else if (cnt <= 20'hEBE) begin + dir <= 0; + end + end + end + + microstepper_top stepper( + .resetn( resetn ), + .clk( clk ), + .fault( fault ), + .s_l( s_l ), + .s_h( s_h ), + .analog_cmp1( analog_cmp1 ), + .analog_out1( analog_out1 ), + .analog_cmp2( analog_cmp2 ), + .analog_out2( analog_out2 ), + .chargepump_pin( chargepump_pin ), + .step( step ), + .dir( dir ), + .enable( enable ), + .config_offtime( config_offtime ), + .config_blanktime( config_blanktime ), + .config_fastdecay_threshold( config_fastdecay_threshold ), + .config_minimum_on_time( config_minimum_on_time ), + .config_current_threshold( config_current_threshold ), + .config_chargepump_period( config_chargepump_period ), + .config_invert_highside( config_invert_highside ), + .config_invert_lowside( config_invert_lowside ), + ); + pwm_duty duty1( + .clk(clk), + .resetn(resetn), + .pwm(analog_out1), + .duty(target_current1) + ); + pwm_duty duty2( + .clk(clk), + .resetn(resetn), + .pwm(analog_out2), + .duty(target_current2) + ); + coil coil1( + .clk(clk), + .resetn(resetn), + .s_l1(s_l[0]), + .s_l2(s_l[1]), + .s_h1(s_h[0]), + .s_h2(s_h[1]), + .current(current1) + ); + coil coil2( + .clk(clk), + .resetn(resetn), + .s_l1(s_l[2]), + .s_l2(s_l[3]), + .s_h1(s_h[2]), + .s_h2(s_h[3]), + .current(current2) + ); +endmodule + diff --git a/testbench/pwm_duty.v b/testbench/pwm_duty.v new file mode 100644 index 0000000..ae8e245 --- /dev/null +++ b/testbench/pwm_duty.v @@ -0,0 +1,40 @@ +// Calculate PWM Duty - cycle by cycle +module pwm_duty( + input clk, + input pwm, + input resetn, + output [12:0] duty, + ); + reg [1:0] edge_b; + reg [11:0] cnt_h; + reg [11:0] cnt_l; + wire tc_edge = edge_b[1] ^ edge_b[0]; + wire pwm; + + reg [12:0] duty; + + always @(posedge clk) begin + if (!resetn) begin + cnt_h <= 0; + cnt_l <= 0; + duty <= 0; + end + else begin + if (tc_edge && edge_b[0]) begin // Rising edge + duty <= ( 255 * cnt_h / (cnt_h + cnt_l) ); + cnt_h <= 0; + cnt_l <= 0; + end + else begin + if (edge_b[1]) begin + cnt_h <= cnt_h + 1; + end + else if (!edge_b[1]) begin + cnt_l <= cnt_l + 1; + end + end + end + edge_b = {edge_b[0], pwm}; + end + +endmodule diff --git a/testbench/quad_tb.v b/testbench/quad_tb.v index 95f7eef..da85005 100644 --- a/testbench/quad_tb.v +++ b/testbench/quad_tb.v @@ -74,7 +74,7 @@ module testbench( end faultn <= &fault; cnt <= cnt + 1; - if (cnt <= 20'h90) begin + if (cnt <= 20'h85) begin enccntA <= enccntA + 1; enc1a <= enccntA[3]; enccntB <= enccntB - 1; From 74d39880a1579dc6854eedf8ee8fae5f3a260890 Mon Sep 17 00:00:00 2001 From: johnnyr Date: Fri, 4 Dec 2020 01:35:29 -0600 Subject: [PATCH 07/71] reset logic for analog out, phase_ct, step dir buffer, instantiation name expansion. --- src/microstepper/analog_out.v | 18 +++++++++++------- src/microstepper/microstepper_control.v | 22 ++++++++++++++++++++-- src/microstepper/microstepper_top.v | 9 +++++---- 3 files changed, 36 insertions(+), 13 deletions(-) diff --git a/src/microstepper/analog_out.v b/src/microstepper/analog_out.v index 3494907..1b55c55 100644 --- a/src/microstepper/analog_out.v +++ b/src/microstepper/analog_out.v @@ -10,13 +10,17 @@ module analog_out ( reg [10:0] pwm_counter; - always @(posedge clk) - if (resetn) - if (pwm_counter <= current_threshold) - pwm_counter <= pwm_counter + 1'b1; - else - pwm_counter <= 0; - + always @(posedge clk) begin + if (!resetn) begin + pwm_counter <= 0; + end + else begin + if (pwm_counter <= current_threshold) + pwm_counter <= pwm_counter + 1'b1; + else + pwm_counter <= 0; + end + end assign analog_out1 = pwm_counter <= pwm1; assign analog_out2 = pwm_counter <= pwm2; diff --git a/src/microstepper/microstepper_control.v b/src/microstepper/microstepper_control.v index 17e0576..653fe34 100644 --- a/src/microstepper/microstepper_control.v +++ b/src/microstepper/microstepper_control.v @@ -1,5 +1,6 @@ module microstepper_control ( input clk, + input resetn, output [3:0] s_l, output [3:0] s_h, input [9:0] config_fastdecay_threshold, @@ -26,11 +27,28 @@ module microstepper_control ( input [9:0] off_timer1, input [7:0] minimum_on_timer0, input [7:0] minimum_on_timer1, +// output step_b_out, ); reg [7:0] phase_ct; +// reg [1:0] step_b; - always @(posedge step) begin - phase_ct <= phase_ct + (dir ? 1 : -1); +// wire step_edge = (step_b[2] ^ step_b[1]) && step_b[2]; + // step edge rising falling + + reg [2:0] step_b; + reg [1:0] dir_b; +// wire step_b_out = step_b[2]; + wire step_rising = (step_b == 2'b01); + + always @(posedge clk) begin + if (!resetn) begin + phase_ct <= 0; + end + else if (step_rising) begin + phase_ct <= phase_ct + dir_b[1]; + end + step_b <= {step_b[1:0], step}; + dir_b <= {dir[0], dir}; end wire s1; diff --git a/src/microstepper/microstepper_top.v b/src/microstepper/microstepper_top.v index c6e92e5..9ddcfb9 100644 --- a/src/microstepper/microstepper_top.v +++ b/src/microstepper/microstepper_top.v @@ -40,8 +40,9 @@ module microstepper_top ( wire [7:0] minimum_on_timer0; wire [7:0] minimum_on_timer1; - microstepper_control m_control_0( + microstepper_control microstepper_control0( .clk(clk), + .resetn(resetn), .s_l(s_l), .s_h(s_h), .config_fastdecay_threshold(config_fastdecay_threshold), @@ -118,14 +119,14 @@ module microstepper_top ( .timer (minimum_on_timer1) ); - chargepump cp0 ( + chargepump chargepump0 ( .clk (clk), .resetn (resetn), .period (config_chargepump_period), .chargepump_pin(chargepump_pin) ); - microstep_counter mc0 ( + microstep_counter microstep_counter0 ( .pos (phase_ct), .cos_index1(cos_index1), .cos_index2(cos_index2), @@ -144,7 +145,7 @@ module microstepper_top ( //.cos_table(cos_table) ); - analog_out ao0 ( + analog_out analog_out0 ( .clk (clk), .resetn (resetn), .pwm1 (pwm1), From cf4ace60e71e523c0a570444c418fe24e58612c5 Mon Sep 17 00:00:00 2001 From: johnnyr Date: Fri, 4 Dec 2020 19:10:59 -0600 Subject: [PATCH 08/71] testbench debugging --- testbench/coil.v | 7 +++---- testbench/microstepper_tb.v | 24 +++++++++++++----------- testbench/pwm_duty.v | 6 +++--- 3 files changed, 19 insertions(+), 18 deletions(-) diff --git a/testbench/coil.v b/testbench/coil.v index 3a2c1ce..dd8c6fe 100644 --- a/testbench/coil.v +++ b/testbench/coil.v @@ -2,16 +2,15 @@ module coil ( input clk, input resetn, + input s_l0, + input s_h0, input s_l1, input s_h1, - input s_l2, - input s_h2, output [12:0] current, ); reg [12:0] current; - reg [7:0] cnt; - wire on = (s_l1 && s_h2) | (s_l1 && s_h2); + wire on = (s_l0 && s_h1) | (s_l1 && s_h0); always @(posedge clk) begin if (!resetn) begin diff --git a/testbench/microstepper_tb.v b/testbench/microstepper_tb.v index 4c54dba..231556d 100644 --- a/testbench/microstepper_tb.v +++ b/testbench/microstepper_tb.v @@ -64,9 +64,11 @@ module testbench( else begin cnt <= cnt + 1; step_clock <= step_clock + 1; - step <= step_clock[9]; + step <= step_clock[11]; if (current1 > target_current1) analog_cmp1 <= 1; + else analog_cmp1 <= 0; if (current2 > target_current2) analog_cmp2 <= 1; + else analog_cmp2 <= 0; if (cnt <= 20'hAEC) begin dir <= 1; end @@ -111,22 +113,22 @@ module testbench( .pwm(analog_out2), .duty(target_current2) ); - coil coil1( + coil coil2( .clk(clk), .resetn(resetn), - .s_l1(s_l[0]), - .s_l2(s_l[1]), - .s_h1(s_h[0]), - .s_h2(s_h[1]), + .s_l0(s_l[0]), + .s_l1(s_l[1]), + .s_h0(s_h[0]), + .s_h1(s_h[1]), .current(current1) ); - coil coil2( + coil coil1( .clk(clk), .resetn(resetn), - .s_l1(s_l[2]), - .s_l2(s_l[3]), - .s_h1(s_h[2]), - .s_h2(s_h[3]), + .s_l0(s_l[2]), + .s_l1(s_l[3]), + .s_h0(s_h[2]), + .s_h1(s_h[3]), .current(current2) ); endmodule diff --git a/testbench/pwm_duty.v b/testbench/pwm_duty.v index ae8e245..24d0289 100644 --- a/testbench/pwm_duty.v +++ b/testbench/pwm_duty.v @@ -8,7 +8,7 @@ module pwm_duty( reg [1:0] edge_b; reg [11:0] cnt_h; reg [11:0] cnt_l; - wire tc_edge = edge_b[1] ^ edge_b[0]; + wire s_edge = edge_b[1] ^ edge_b[0]; wire pwm; reg [12:0] duty; @@ -20,8 +20,8 @@ module pwm_duty( duty <= 0; end else begin - if (tc_edge && edge_b[0]) begin // Rising edge - duty <= ( 255 * cnt_h / (cnt_h + cnt_l) ); + if (s_edge && edge_b[0]) begin // Rising edge + duty <= 8191 * cnt_h / (cnt_h + cnt_l) ; cnt_h <= 0; cnt_l <= 0; end From 8412499eca05365f4539b86c01f9a28911ec4237 Mon Sep 17 00:00:00 2001 From: johnnyr Date: Fri, 4 Dec 2020 19:11:47 -0600 Subject: [PATCH 09/71] tb debug --- sim_microstepper.ys | 2 +- src/microstepper/microstepper_control.v | 17 ++++++++++++++--- src/top.v | 4 ++-- 3 files changed, 17 insertions(+), 6 deletions(-) diff --git a/sim_microstepper.ys b/sim_microstepper.ys index 3d86003..dda1280 100644 --- a/sim_microstepper.ys +++ b/sim_microstepper.ys @@ -11,4 +11,4 @@ read_verilog -sv testbench/microstepper_tb.v \ prep -top testbench show microstepper_top -sim -n 40000 -clock clk -vcd testbench/microstepper.vcd +sim -n 400000 -clock clk -vcd testbench/microstepper.vcd diff --git a/src/microstepper/microstepper_control.v b/src/microstepper/microstepper_control.v index 653fe34..85d75f6 100644 --- a/src/microstepper/microstepper_control.v +++ b/src/microstepper/microstepper_control.v @@ -45,7 +45,7 @@ module microstepper_control ( phase_ct <= 0; end else if (step_rising) begin - phase_ct <= phase_ct + dir_b[1]; + phase_ct <= dir_b[1] ? phase_ct + 1 : phase_ct - 1; end step_b <= {step_b[1:0], step}; dir_b <= {dir[0], dir}; @@ -56,8 +56,9 @@ module microstepper_control ( wire s3; wire s4; + // Off Timer active flag wire overCurrent0 = off_timer0 > 0; - wire overCurrent1 = off_timer1 > 0; + wire overCurrent1 = off_timer1 > 0; wire fastDecay0 = off_timer0 >= config_fastdecay_threshold; wire fastDecay1 = off_timer1 >= config_fastdecay_threshold; @@ -73,11 +74,14 @@ module microstepper_control ( wire phase_a1_h, phase_a1_l, phase_a2_h, phase_a2_l; wire phase_b1_h, phase_b1_l, phase_b2_h, phase_b2_l; + // Switch output Low + assign s_l[0] = !(phase_a1_l | fault); assign s_l[1] = !(phase_a2_l | fault); assign s_l[2] = !(phase_b1_l | fault); assign s_l[3] = !(phase_b2_l | fault); + // Switch output High assign s_h[0] = !(phase_a1_h | fault); assign s_h[1] = !(phase_a2_h | fault); assign s_h[2] = !(phase_b1_h | fault); @@ -93,14 +97,19 @@ module microstepper_control ( assign phase_b2_h = config_invert_highside ^ (slowDecay1 | (fastDecay1 ? s4r[1] : ~s4r[1])); assign phase_b2_l = config_invert_lowside ^ (fastDecay1 ? ~s4r[1] : (slowDecay1 ? 1'b0 : s4r[1])); - + // Start on time per half bridge wire s1_starting = s1r == 2'b10; wire s2_starting = s2r == 2'b10; wire s3_starting = s3r == 2'b10; wire s4_starting = s4r == 2'b10; + // start Off Time + // Target peak current detected. Blank timer and Off timer not active assign offtimer_en0 = analog_cmp1 & blank_timer0 == 0 & overCurrent0 == 0; assign offtimer_en1 = analog_cmp2 & blank_timer1 == 0 & overCurrent1 == 0; + + // Bridge On Time start + // Blank timer and minimum on timer enable assign a_starting = s1_starting | s2_starting; assign b_starting = s3_starting | s4_starting; @@ -113,6 +122,8 @@ module microstepper_control ( end `endif + // Shift register buffer switch output + // Triger start on time always @(posedge clk) begin s1r <= {s1r[0], s1}; s2r <= {s2r[0], s2}; diff --git a/src/top.v b/src/top.v index e23da82..237935d 100644 --- a/src/top.v +++ b/src/top.v @@ -114,8 +114,8 @@ module top ( reg [7:0] config_minimum_on_time = 54; reg [10:0] config_current_threshold = 1024; reg [7:0] config_chargepump_period = 91; - reg config_invert_highside = 0; - reg config_invert_lowside = 0; + reg config_invert_highside = 1; + reg config_invert_lowside = 1; /* reg [511:0] cos_table; From f0e56ef4e29e32edf208ee2c6a45fe92a779432d Mon Sep 17 00:00:00 2001 From: johnnyr Date: Fri, 4 Dec 2020 21:11:12 -0600 Subject: [PATCH 10/71] testbench with Jason and Steve round 3 --- testbench/coil.v | 6 +++++- testbench/microstepper_tb.v | 4 ++-- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/testbench/coil.v b/testbench/coil.v index dd8c6fe..72fc19f 100644 --- a/testbench/coil.v +++ b/testbench/coil.v @@ -7,10 +7,14 @@ module coil ( input s_l1, input s_h1, output [12:0] current, + output positive, + output negative, ); reg [12:0] current; - wire on = (s_l0 && s_h1) | (s_l1 && s_h0); + wire on = (!s_l0 && !s_h1) | (!s_l1 && !s_h0); + wire positive = (!s_l0 && !s_h1); + wire negative = (!s_l1 && !s_h0); always @(posedge clk) begin if (!resetn) begin diff --git a/testbench/microstepper_tb.v b/testbench/microstepper_tb.v index 231556d..6da7730 100644 --- a/testbench/microstepper_tb.v +++ b/testbench/microstepper_tb.v @@ -113,7 +113,7 @@ module testbench( .pwm(analog_out2), .duty(target_current2) ); - coil coil2( + coil coil1( .clk(clk), .resetn(resetn), .s_l0(s_l[0]), @@ -122,7 +122,7 @@ module testbench( .s_h1(s_h[1]), .current(current1) ); - coil coil1( + coil coil2( .clk(clk), .resetn(resetn), .s_l0(s_l[2]), From 886ed5fec3aea12fe150af9c54fcfc65edcebaac Mon Sep 17 00:00:00 2001 From: johnnyr Date: Fri, 4 Dec 2020 21:11:39 -0600 Subject: [PATCH 11/71] patches / hacks from testbench working session --- src/microstepper/microstepper_control.v | 44 +++++++++++++++-------- src/microstepper/microstepper_top.v | 12 ++++--- src/microstepper/mytimer.v | 30 +++++++++------- src/microstepper/mytimer_10.v | 47 ++++++++++++++----------- src/microstepper/mytimer_8.v | 47 ++++++++++++++----------- src/top.v | 4 +-- 6 files changed, 110 insertions(+), 74 deletions(-) diff --git a/src/microstepper/microstepper_control.v b/src/microstepper/microstepper_control.v index 85d75f6..d040407 100644 --- a/src/microstepper/microstepper_control.v +++ b/src/microstepper/microstepper_control.v @@ -27,6 +27,8 @@ module microstepper_control ( input [9:0] off_timer1, input [7:0] minimum_on_timer0, input [7:0] minimum_on_timer1, +// input off_timer0_done, +// input off_timer1_done, // output step_b_out, ); reg [7:0] phase_ct; @@ -56,18 +58,18 @@ module microstepper_control ( wire s3; wire s4; - // Off Timer active flag - wire overCurrent0 = off_timer0 > 0; - wire overCurrent1 = off_timer1 > 0; + // Off Timer active flag + wire off_timer_active0 = off_timer0 > 0; + wire off_timer_active1 = off_timer1 > 0; wire fastDecay0 = off_timer0 >= config_fastdecay_threshold; wire fastDecay1 = off_timer1 >= config_fastdecay_threshold; - wire slowDecay0 = overCurrent0 && fastDecay0 == 0; - wire slowDecay1 = overCurrent1 && fastDecay1 == 0; + wire slowDecay0 = off_timer_active0 && fastDecay0 == 0; + wire slowDecay1 = off_timer_active1 && fastDecay1 == 0; - wire fault0 = (minimum_on_timer0 > 0) && overCurrent0; - wire fault1 = (minimum_on_timer1 > 0) && overCurrent1; + wire fault0 = (minimum_on_timer0 > 0) && off_timer_active0; + wire fault1 = (minimum_on_timer1 > 0) && off_timer_active1; wire fault = fault0 | fault1; reg [1:0] s1r, s2r, s3r, s4r; @@ -75,7 +77,6 @@ module microstepper_control ( wire phase_b1_h, phase_b1_l, phase_b2_h, phase_b2_l; // Switch output Low - assign s_l[0] = !(phase_a1_l | fault); assign s_l[1] = !(phase_a2_l | fault); assign s_l[2] = !(phase_b1_l | fault); @@ -98,20 +99,21 @@ module microstepper_control ( assign phase_b2_l = config_invert_lowside ^ (fastDecay1 ? ~s4r[1] : (slowDecay1 ? 1'b0 : s4r[1])); // Start on time per half bridge + // todo concatanate config inverting for active high or low wire s1_starting = s1r == 2'b10; wire s2_starting = s2r == 2'b10; wire s3_starting = s3r == 2'b10; wire s4_starting = s4r == 2'b10; - // start Off Time - // Target peak current detected. Blank timer and Off timer not active - assign offtimer_en0 = analog_cmp1 & blank_timer0 == 0 & overCurrent0 == 0; - assign offtimer_en1 = analog_cmp2 & blank_timer1 == 0 & overCurrent1 == 0; - // Bridge On Time start // Blank timer and minimum on timer enable - assign a_starting = s1_starting | s2_starting; - assign b_starting = s3_starting | s4_starting; + //assign a_starting = s1_starting | s2_starting; + //assign b_starting = s3_starting | s4_starting; + + // start Off Time + // Target peak current detected. Blank timer and Off timer not active + assign offtimer_en0 = analog_cmp1 & blank_timer0 == 0 & off_timer_active0 == 0; + assign offtimer_en1 = analog_cmp2 & blank_timer1 == 0 & off_timer_active1 == 0; `ifdef FORMAL always @(*) begin @@ -130,5 +132,17 @@ module microstepper_control ( s3r <= {s3r[0], s3}; s4r <= {s4r[0], s4}; end +// +// wire [1:0] off_time_b; +// reg a_starting; +// reg b_starting; + +// always @(posedge clk) begin + //start on time +// if +// a_starting <= ~off_timer0; +// b_starting <= ~off_timer1; + +// end endmodule diff --git a/src/microstepper/microstepper_top.v b/src/microstepper/microstepper_top.v index 9ddcfb9..cd43862 100644 --- a/src/microstepper/microstepper_top.v +++ b/src/microstepper/microstepper_top.v @@ -69,6 +69,8 @@ module microstepper_top ( .off_timer1(off_timer1), .minimum_on_timer0(minimum_on_timer0), .minimum_on_timer1(minimum_on_timer1), +// .off_timer0_done (off_timer0_done), +// .off_timer0_done (off_timer1_done), ); mytimer_10 offtimer0 ( @@ -76,7 +78,8 @@ module microstepper_top ( .resetn (resetn), .start_enable(offtimer_en0), .start_time (config_offtime), - .timer (off_timer0) + .timer (off_timer0), + .done (off_timer0_done) ); mytimer_10 offtimer1 ( @@ -84,13 +87,14 @@ module microstepper_top ( .resetn (resetn), .start_enable(offtimer_en1), .start_time (config_offtime), - .timer (off_timer1) + .timer (off_timer1), + .done (off_timer1_done) ); mytimer_8 blanktimer0 ( .clk (clk), .resetn (resetn), - .start_enable(a_starting), + .start_enable(off_timer0_done), .start_time (config_blanktime), .timer (blank_timer0) ); @@ -98,7 +102,7 @@ module microstepper_top ( mytimer_8 blanktimer1 ( .clk (clk), .resetn (resetn), - .start_enable(b_starting), + .start_enable(off_timer1_done), .start_time (config_blanktime), .timer (blank_timer1) ); diff --git a/src/microstepper/mytimer.v b/src/microstepper/mytimer.v index dd87b02..4c11f73 100644 --- a/src/microstepper/mytimer.v +++ b/src/microstepper/mytimer.v @@ -1,29 +1,33 @@ module mytimer ( - clk, - resetn, - start_enable, - start_time, - timer + input clk, + input resetn, + input start_enable, + input [WIDTH-1:0] start_time, + output [WIDTH-1:0] timer, + output done // single cycle timer done event ); parameter WIDTH = 10; - input clk; - input resetn; - input start_enable; - input [WIDTH-1:0] start_time; - output [WIDTH-1:0] timer; - + reg done = 0; reg [WIDTH-1:0] counter; - + reg run = 1; assign timer = counter; always @(posedge clk) begin if (!resetn) counter <= 0; - else if( start_enable ) + else if( start_enable ) begin counter <= start_time; + run <= 1; + end else if( counter > 0 ) counter <= counter - 1'b1; + else if (run) + done <= 1; + if (done) begin + run <= 0; + done <= 0; + end end endmodule diff --git a/src/microstepper/mytimer_10.v b/src/microstepper/mytimer_10.v index 5ce98e4..d8c94a1 100644 --- a/src/microstepper/mytimer_10.v +++ b/src/microstepper/mytimer_10.v @@ -1,26 +1,33 @@ module mytimer_10 ( - clk, - resetn, - start_enable, - start_time, - timer + input clk, + input resetn, + input start_enable, + input [WIDTH-1:0] start_time, + output [WIDTH-1:0] timer, + output done // single cycle timer done event ); - localparam WIDTH = 10; + parameter WIDTH = 10; - input clk; - input resetn; - input start_enable; - input [WIDTH-1:0] start_time; - output [WIDTH-1:0] timer; + reg done = 0; + reg [WIDTH-1:0] counter; + reg run = 1; + assign timer = counter; - mytimer #( - .WIDTH(WIDTH) - ) mytimer10 ( - .clk (clk), - .resetn (resetn), - .start_enable(start_enable), - .start_time (start_time), - .timer (timer) - ); + always @(posedge clk) begin + if (!resetn) + counter <= 0; + else if( start_enable ) begin + counter <= start_time; + run <= 1; + end + else if( counter > 0 ) + counter <= counter - 1'b1; + else if (run) + done <= 1; + if (done) begin + run <= 0; + done <= 0; + end +end endmodule diff --git a/src/microstepper/mytimer_8.v b/src/microstepper/mytimer_8.v index 38f495d..5519e6b 100644 --- a/src/microstepper/mytimer_8.v +++ b/src/microstepper/mytimer_8.v @@ -1,26 +1,33 @@ module mytimer_8 ( - clk, - resetn, - start_enable, - start_time, - timer + input clk, + input resetn, + input start_enable, + input [WIDTH-1:0] start_time, + output [WIDTH-1:0] timer, + output done // single cycle timer done event ); - localparam WIDTH = 8; + parameter WIDTH = 8; - input clk; - input resetn; - input start_enable; - input [WIDTH-1:0] start_time; - output [WIDTH-1:0] timer; + reg done = 0; + reg [WIDTH-1:0] counter; + reg run = 1; + assign timer = counter; - mytimer #( - .WIDTH(WIDTH) - ) mytimer8 ( - .clk (clk), - .resetn (resetn), - .start_enable(start_enable), - .start_time (start_time), - .timer (timer) - ); + always @(posedge clk) begin + if (!resetn) + counter <= 0; + else if( start_enable ) begin + counter <= start_time; + run <= 1; + end + else if( counter > 0 ) + counter <= counter - 1'b1; + else if (run) + done <= 1; + if (done) begin + run <= 0; + done <= 0; + end +end endmodule diff --git a/src/top.v b/src/top.v index 237935d..e23da82 100644 --- a/src/top.v +++ b/src/top.v @@ -114,8 +114,8 @@ module top ( reg [7:0] config_minimum_on_time = 54; reg [10:0] config_current_threshold = 1024; reg [7:0] config_chargepump_period = 91; - reg config_invert_highside = 1; - reg config_invert_lowside = 1; + reg config_invert_highside = 0; + reg config_invert_lowside = 0; /* reg [511:0] cos_table; From b83fee6262dbfe966e459e33ed5645e1ab93e35c Mon Sep 17 00:00:00 2001 From: johnnyr Date: Sat, 5 Dec 2020 00:14:50 -0600 Subject: [PATCH 12/71] more test bench patches --- testbench/coil.v | 6 ++++++ testbench/microstepper_tb.v | 10 +++++----- 2 files changed, 11 insertions(+), 5 deletions(-) diff --git a/testbench/coil.v b/testbench/coil.v index 72fc19f..54742dc 100644 --- a/testbench/coil.v +++ b/testbench/coil.v @@ -12,6 +12,12 @@ module coil ( ); reg [12:0] current; + // For each coil of motor + // Each coil is driven by s_x1 and s_x2 + // One side s_x1 or s_x2 must be high when the other is low to be on +// wire phase_a_positive = !s_l0 && !s_h1; +// wire phase_a_negative = !s_l1 && !s_h0; +// wire off = s_l0; wire on = (!s_l0 && !s_h1) | (!s_l1 && !s_h0); wire positive = (!s_l0 && !s_h1); wire negative = (!s_l1 && !s_h0); diff --git a/testbench/microstepper_tb.v b/testbench/microstepper_tb.v index 6da7730..a08c485 100644 --- a/testbench/microstepper_tb.v +++ b/testbench/microstepper_tb.v @@ -13,16 +13,16 @@ module testbench( output analog_out2, output chargepump_pin, output fault, - output [7:0] target_current1, + output [12:0] target_current1, ); reg step; reg dir; reg enable; - reg [7:0] target_current1; - reg [7:0] target_current2; - reg [7:0] current1; - reg [7:0] current2; + reg [12:0] target_current1; + reg [12:0] target_current2; + reg [12:0] current1; + reg [12:0] current2; reg [9:0] config_offtime; reg [7:0] config_blanktime; reg [9:0] config_fastdecay_threshold; From 9630e535c57c0a2ddd39c5f470071d018afc2f1d Mon Sep 17 00:00:00 2001 From: johnnyr Date: Sat, 5 Dec 2020 00:15:44 -0600 Subject: [PATCH 13/71] Comments and microstepper refactor from testbench party with Steve and Jason --- src/microstepper/microstepper_control.v | 102 +++++++++++------------- 1 file changed, 46 insertions(+), 56 deletions(-) diff --git a/src/microstepper/microstepper_control.v b/src/microstepper/microstepper_control.v index d040407..7249925 100644 --- a/src/microstepper/microstepper_control.v +++ b/src/microstepper/microstepper_control.v @@ -62,11 +62,6 @@ module microstepper_control ( wire off_timer_active0 = off_timer0 > 0; wire off_timer_active1 = off_timer1 > 0; - wire fastDecay0 = off_timer0 >= config_fastdecay_threshold; - wire fastDecay1 = off_timer1 >= config_fastdecay_threshold; - - wire slowDecay0 = off_timer_active0 && fastDecay0 == 0; - wire slowDecay1 = off_timer_active1 && fastDecay1 == 0; wire fault0 = (minimum_on_timer0 > 0) && off_timer_active0; wire fault1 = (minimum_on_timer1 > 0) && off_timer_active1; @@ -77,38 +72,54 @@ module microstepper_control ( wire phase_b1_h, phase_b1_l, phase_b2_h, phase_b2_l; // Switch output Low - assign s_l[0] = !(phase_a1_l | fault); - assign s_l[1] = !(phase_a2_l | fault); - assign s_l[2] = !(phase_b1_l | fault); - assign s_l[3] = !(phase_b2_l | fault); + assign s_l[0] = config_invert_lowside ^ (phase_a1_l | fault); + assign s_l[1] = config_invert_lowside ^ (phase_a2_l | fault); + assign s_l[2] = config_invert_lowside ^ (phase_b1_l | fault); + assign s_l[3] = config_invert_lowside ^ (phase_b2_l | fault); // Switch output High - assign s_h[0] = !(phase_a1_h | fault); - assign s_h[1] = !(phase_a2_h | fault); - assign s_h[2] = !(phase_b1_h | fault); - assign s_h[3] = !(phase_b2_h | fault); - - assign phase_a1_h = config_invert_highside ^ (slowDecay0 | (fastDecay0 ? s1r[1] : ~s1r[1])); - assign phase_a1_l = config_invert_lowside ^ (fastDecay0 ? ~s1r[1] : (slowDecay0 ? 1'b0 : s1r[1])); - assign phase_a2_h = config_invert_highside ^ (slowDecay0 | (fastDecay0 ? s2r[1] : ~s2r[1])); - assign phase_a2_l = config_invert_lowside ^ (fastDecay0 ? ~s2r[1] : (slowDecay0 ? 1'b0 : s2r[1])); - - assign phase_b1_h = config_invert_highside ^ (slowDecay1 | (fastDecay1 ? s3r[1] : ~s3r[1])); - assign phase_b1_l = config_invert_lowside ^ (fastDecay1 ? ~s3r[1] : (slowDecay1 ? 1'b0 : s3r[1])); - assign phase_b2_h = config_invert_highside ^ (slowDecay1 | (fastDecay1 ? s4r[1] : ~s4r[1])); - assign phase_b2_l = config_invert_lowside ^ (fastDecay1 ? ~s4r[1] : (slowDecay1 ? 1'b0 : s4r[1])); - - // Start on time per half bridge - // todo concatanate config inverting for active high or low - wire s1_starting = s1r == 2'b10; - wire s2_starting = s2r == 2'b10; - wire s3_starting = s3r == 2'b10; - wire s4_starting = s4r == 2'b10; - - // Bridge On Time start - // Blank timer and minimum on timer enable - //assign a_starting = s1_starting | s2_starting; - //assign b_starting = s3_starting | s4_starting; + assign s_h[0] = config_invert_highside ^ (phase_a1_h | fault); + assign s_h[1] = config_invert_highside ^ (phase_a2_h | fault); + assign s_h[2] = config_invert_highside ^ (phase_b1_h | fault); + assign s_h[3] = config_invert_highside ^ (phase_b2_h | fault); + + // Fast decay is first x ticks of off time + // default fast decay = 706 + wire fastDecay0 = off_timer0 >= config_fastdecay_threshold; + wire fastDecay1 = off_timer1 >= config_fastdecay_threshold; + + // Slow decay remainder of off time + wire slowDecay0 = off_timer_active0 && fastDecay0 == 0; + wire slowDecay1 = off_timer_active1 && fastDecay1 == 0; + + // This portion of code sets up output to drive mosfets. Output ON = 0 + + // High side output logic + // If in slow decay =1 + // OR + // ( fast decay and commanded to be OFF ) = 1 + // Then OFF + // Else If Not slow decay (Never in slow decay at same time as fast decay) + // OR + // ( not fast decay ) + // Then + // Follow commanded output + // Else if fast decay + // invert commanded polarity + assign phase_a1_h = slowDecay0 | ( fastDecay0 ? s1 : ~s1 ); + // Low side output logic + // low side output (invert if configured with XOR) + // Invert signal if fast decay commands. + // if slow decay the output is low. Else output = as commanded by microstep counter + assign phase_a1_l = fastDecay0 ? ~s1 : ( slowDecay0 ? 1'b0 : s1 ); + assign phase_a2_h = slowDecay0 | ( fastDecay0 ? s2 : ~s2 ); + assign phase_a2_l = fastDecay0 ? ~s2 : ( slowDecay0 ? 1'b0 : s2 ); + assign phase_b1_h = slowDecay1 | ( fastDecay1 ? s3 : ~s3 ); + assign phase_b1_l = fastDecay1 ? ~s3 : ( slowDecay1 ? 1'b0 : s3 ); + assign phase_b2_h = slowDecay1 | ( fastDecay1 ? s4 : ~s4 ); + assign phase_b2_l = fastDecay1 ? ~s4 : ( slowDecay1 ? 1'b0 : s4 ); + + // NEED DEAD TIME // start Off Time // Target peak current detected. Blank timer and Off timer not active @@ -124,25 +135,4 @@ module microstepper_control ( end `endif - // Shift register buffer switch output - // Triger start on time - always @(posedge clk) begin - s1r <= {s1r[0], s1}; - s2r <= {s2r[0], s2}; - s3r <= {s3r[0], s3}; - s4r <= {s4r[0], s4}; - end -// -// wire [1:0] off_time_b; -// reg a_starting; -// reg b_starting; - -// always @(posedge clk) begin - //start on time -// if -// a_starting <= ~off_timer0; -// b_starting <= ~off_timer1; - -// end - endmodule From 42452cfd5f5890d3246a7b459efa06e6510d558f Mon Sep 17 00:00:00 2001 From: johnnyr Date: Sun, 6 Dec 2020 16:38:46 -0600 Subject: [PATCH 14/71] default output active high, slow decay on low side, improve testbench motor model --- sim_microstepper.tcl | 8 +++ sim_microstepper.ys | 2 +- src/microstepper/microstepper_control.v | 19 +++---- testbench/coil.v | 39 ------------- testbench/hbridge_coil.v | 57 +++++++++++++++++++ testbench/microstepper_tb.v | 76 +++++++++++++------------ 6 files changed, 116 insertions(+), 85 deletions(-) create mode 100644 sim_microstepper.tcl delete mode 100644 testbench/coil.v create mode 100644 testbench/hbridge_coil.v diff --git a/sim_microstepper.tcl b/sim_microstepper.tcl new file mode 100644 index 0000000..85bfc4d --- /dev/null +++ b/sim_microstepper.tcl @@ -0,0 +1,8 @@ +yosys -import + +set + +read_verilog -sv testbench/microstepper_tb.v src/microstepper/*.v +prep -top testbench +show m_control_0 +sim -n 4000 -clock clk -vcd testbench/microstepper.vcd diff --git a/sim_microstepper.ys b/sim_microstepper.ys index dda1280..fe0fbff 100644 --- a/sim_microstepper.ys +++ b/sim_microstepper.ys @@ -11,4 +11,4 @@ read_verilog -sv testbench/microstepper_tb.v \ prep -top testbench show microstepper_top -sim -n 400000 -clock clk -vcd testbench/microstepper.vcd +sim -n 4000 -clock clk -vcd testbench/microstepper.vcd diff --git a/src/microstepper/microstepper_control.v b/src/microstepper/microstepper_control.v index 7249925..94d8576 100644 --- a/src/microstepper/microstepper_control.v +++ b/src/microstepper/microstepper_control.v @@ -53,6 +53,7 @@ module microstepper_control ( dir_b <= {dir[0], dir}; end + // Switch outputs wire s1; wire s2; wire s3; @@ -67,7 +68,7 @@ module microstepper_control ( wire fault1 = (minimum_on_timer1 > 0) && off_timer_active1; wire fault = fault0 | fault1; - reg [1:0] s1r, s2r, s3r, s4r; + reg [1:0] s1r, s2r, s3r, s4r; // Switch output history [ previous : now ] wire phase_a1_h, phase_a1_l, phase_a2_h, phase_a2_l; wire phase_b1_h, phase_b1_l, phase_b2_h, phase_b2_l; @@ -95,22 +96,20 @@ module microstepper_control ( // This portion of code sets up output to drive mosfets. Output ON = 0 // High side output logic - // If in slow decay =1 - // OR - // ( fast decay and commanded to be OFF ) = 1 + // If in slow decay = 1 + // OR ( fast decay and commanded to be OFF ) = 1 // Then OFF // Else If Not slow decay (Never in slow decay at same time as fast decay) - // OR - // ( not fast decay ) - // Then - // Follow commanded output + // OR ( not fast decay ) + // Then Follow commanded output // Else if fast decay // invert commanded polarity assign phase_a1_h = slowDecay0 | ( fastDecay0 ? s1 : ~s1 ); // Low side output logic // low side output (invert if configured with XOR) // Invert signal if fast decay commands. - // if slow decay the output is low. Else output = as commanded by microstep counter + // If slow decay Then the output is low. + // Else output = as commanded by microstep counter assign phase_a1_l = fastDecay0 ? ~s1 : ( slowDecay0 ? 1'b0 : s1 ); assign phase_a2_h = slowDecay0 | ( fastDecay0 ? s2 : ~s2 ); assign phase_a2_l = fastDecay0 ? ~s2 : ( slowDecay0 ? 1'b0 : s2 ); @@ -121,7 +120,7 @@ module microstepper_control ( // NEED DEAD TIME - // start Off Time + // Start Off Time // Target peak current detected. Blank timer and Off timer not active assign offtimer_en0 = analog_cmp1 & blank_timer0 == 0 & off_timer_active0 == 0; assign offtimer_en1 = analog_cmp2 & blank_timer1 == 0 & off_timer_active1 == 0; diff --git a/testbench/coil.v b/testbench/coil.v deleted file mode 100644 index 54742dc..0000000 --- a/testbench/coil.v +++ /dev/null @@ -1,39 +0,0 @@ -// Linear current ramp -module coil ( - input clk, - input resetn, - input s_l0, - input s_h0, - input s_l1, - input s_h1, - output [12:0] current, - output positive, - output negative, -); - reg [12:0] current; - - // For each coil of motor - // Each coil is driven by s_x1 and s_x2 - // One side s_x1 or s_x2 must be high when the other is low to be on -// wire phase_a_positive = !s_l0 && !s_h1; -// wire phase_a_negative = !s_l1 && !s_h0; -// wire off = s_l0; - wire on = (!s_l0 && !s_h1) | (!s_l1 && !s_h0); - wire positive = (!s_l0 && !s_h1); - wire negative = (!s_l1 && !s_h0); - - always @(posedge clk) begin - if (!resetn) begin - current <= 0; - end - else begin - if ( on ) begin - current <= current + 1; - end - else begin - current <= 0; - end - end - end -endmodule -//(cnt[2]== 1) \ No newline at end of file diff --git a/testbench/hbridge_coil.v b/testbench/hbridge_coil.v new file mode 100644 index 0000000..e37462b --- /dev/null +++ b/testbench/hbridge_coil.v @@ -0,0 +1,57 @@ +// Built to work in one polarity +module hbridge_coil ( + input clk, + input resetn, + input low_1, + input high_1, + input low_2, + input high_2, + output signed [12:0] current, +); + reg signed [12:0] current; + reg polarity; // arbitrary polarity + reg on; + reg [8:0] cnt; + reg alive; + reg slow_decay; + reg signed [2:0] current_ramp_cnt; // rates are delay counter sizes + reg signed [3:0] slow_decay_cnt; + reg signed [1:0] fast_decay_cnt; + reg open; // coils not connected. Should never occur? + // For each coil of motor + // Each coil is driven by 2 half bridges. _1 and _2 + // Each half bridge is driven by two drivers. high_ and low_ + // Current goes in one direction when low_0 is on and high_1 is on. + // Current goes the opposite direction when high_0 is on and low_1 is on. + // set state of on for next tick +// wire phase_negative = low_1 && high_0; + always @(posedge clk) begin + if (!resetn) begin + current <= 0; + on <= 0; + polarity <= 0; + cnt <= 0; + current_ramp_cnt <= 0; + slow_decay_cnt <= 0; + fast_decay_cnt <= 0; + end + else begin + cnt <= cnt + 1; + current_ramp_cnt <= current_ramp_cnt + 1; + slow_decay_cnt <= slow_decay_cnt + 1; + fast_decay_cnt <= fast_decay_cnt + 1; + on <= ( low_1 && high_2 ) | ( low_2 && high_1 ); + polarity <= high_2 && low_1; + slow_decay <= ( low_1 && low_2 ) | ( high_1 && high_2 ); + if ( on ) begin + if ( polarity && !current_ramp_cnt ) + current <= current + 1; + else if ( !polarity && current && !fast_decay_cnt ) + current <= current - 1; + end + else if ( slow_decay && current && !slow_decay_cnt ) + current <= current - 1; // slow decay every 4th tick + end + end +endmodule +//(cnt[2]== 1) \ No newline at end of file diff --git a/testbench/microstepper_tb.v b/testbench/microstepper_tb.v index a08c485..7869484 100644 --- a/testbench/microstepper_tb.v +++ b/testbench/microstepper_tb.v @@ -1,5 +1,5 @@ `include "../src/microstepper/microstepper_top.v" -`include "coil.v" +`include "hbridge_coil.v" `include "pwm_duty.v" `timescale 1ns/100ps @@ -12,25 +12,24 @@ module testbench( output analog_cmp2, output analog_out2, output chargepump_pin, - output fault, - output [12:0] target_current1, + output faultn, ); - reg step; - reg dir; - reg enable; - reg [12:0] target_current1; - reg [12:0] target_current2; - reg [12:0] current1; - reg [12:0] current2; - reg [9:0] config_offtime; - reg [7:0] config_blanktime; - reg [9:0] config_fastdecay_threshold; - reg [7:0] config_minimum_on_time; - reg [10:0] config_current_threshold; - reg [7:0] config_chargepump_period; - reg config_invert_highside; - reg config_invert_lowside; + reg step; + reg dir; + reg enable; + reg [12:0] target_current1; + reg [12:0] target_current2; + reg signed [12:0] current1; + reg signed [12:0] current2; + reg [9:0] config_offtime; + reg [7:0] config_blanktime; + reg [9:0] config_fastdecay_threshold; + reg [7:0] config_minimum_on_time; + reg [10:0] config_current_threshold; + reg [7:0] config_chargepump_period; + reg config_invert_highside; + reg config_invert_lowside; wire resetn; reg [7:0] resetn_counter = 0; @@ -50,7 +49,7 @@ module testbench( analog_cmp1 <= 0; analog_cmp2 <= 0; step <= 1; - enable <= 1; + enable_in <= 1; config_offtime = 810; config_blanktime = 27; config_fastdecay_threshold = 706; @@ -63,11 +62,12 @@ module testbench( end else begin cnt <= cnt + 1; + enable_in <= 1; step_clock <= step_clock + 1; step <= step_clock[11]; - if (current1 > target_current1) analog_cmp1 <= 1; + if (current1[12:0] > target_current1) analog_cmp1 <= 1; // compare unsigned else analog_cmp1 <= 0; - if (current2 > target_current2) analog_cmp2 <= 1; + if (current2[12:0] > target_current2) analog_cmp2 <= 1; else analog_cmp2 <= 0; if (cnt <= 20'hAEC) begin dir <= 1; @@ -81,9 +81,15 @@ module testbench( microstepper_top stepper( .resetn( resetn ), .clk( clk ), - .fault( fault ), - .s_l( s_l ), - .s_h( s_h ), + .faultn( faultn ), + .phase_a1_l( phase_a1_l ), + .phase_a2_l( phase_a2_l ), + .phase_b1_l( phase_b1_l ), + .phase_b2_l( phase_b2_l ), + .phase_a1_h( phase_a1_h ), + .phase_a2_h( phase_a2_h ), + .phase_b1_h( phase_b1_h ), + .phase_b2_h( phase_b2_h ), .analog_cmp1( analog_cmp1 ), .analog_out1( analog_out1 ), .analog_cmp2( analog_cmp2 ), @@ -91,7 +97,7 @@ module testbench( .chargepump_pin( chargepump_pin ), .step( step ), .dir( dir ), - .enable( enable ), + .enable_in( enable_in ), .config_offtime( config_offtime ), .config_blanktime( config_blanktime ), .config_fastdecay_threshold( config_fastdecay_threshold ), @@ -113,22 +119,22 @@ module testbench( .pwm(analog_out2), .duty(target_current2) ); - coil coil1( + hbridge_coil hbridge_coil1( .clk(clk), .resetn(resetn), - .s_l0(s_l[0]), - .s_l1(s_l[1]), - .s_h0(s_h[0]), - .s_h1(s_h[1]), + .low_1(phase_a1_l), + .high_1(phase_a1_h), + .low_2(phase_a2_l), + .high_2(phase_a2_h), .current(current1) ); - coil coil2( + hbridge_coil hbridge_coil2( .clk(clk), .resetn(resetn), - .s_l0(s_l[2]), - .s_l1(s_l[3]), - .s_h0(s_h[2]), - .s_h1(s_h[3]), + .low_1(phase_b1_l), + .high_1(phase_b1_h), + .low_2(phase_b2_l), + .high_2(phase_b2_h), .current(current2) ); endmodule From 9883230b30d8df10aa145503405243896c1e7726 Mon Sep 17 00:00:00 2001 From: johnnyr Date: Sun, 6 Dec 2020 21:01:10 -0600 Subject: [PATCH 15/71] debug microstepper test bench. --- sim_microstepper.tcl | 2 +- sim_microstepper.ys | 2 +- src/microstepper/microstepper_control.v | 151 +++++++++++++----------- src/microstepper/microstepper_top.v | 40 ++++--- src/microstepper/mytimer_10.v | 4 +- src/top.v | 10 +- testbench/hbridge_coil.v | 28 +++-- testbench/microstepper_tb.v | 44 ++++--- 8 files changed, 170 insertions(+), 111 deletions(-) diff --git a/sim_microstepper.tcl b/sim_microstepper.tcl index 85bfc4d..a3713ee 100644 --- a/sim_microstepper.tcl +++ b/sim_microstepper.tcl @@ -5,4 +5,4 @@ set read_verilog -sv testbench/microstepper_tb.v src/microstepper/*.v prep -top testbench show m_control_0 -sim -n 4000 -clock clk -vcd testbench/microstepper.vcd +sim -n 40000 -clock clk -vcd testbench/microstepper.vcd diff --git a/sim_microstepper.ys b/sim_microstepper.ys index fe0fbff..dda1280 100644 --- a/sim_microstepper.ys +++ b/sim_microstepper.ys @@ -11,4 +11,4 @@ read_verilog -sv testbench/microstepper_tb.v \ prep -top testbench show microstepper_top -sim -n 4000 -clock clk -vcd testbench/microstepper.vcd +sim -n 400000 -clock clk -vcd testbench/microstepper.vcd diff --git a/src/microstepper/microstepper_control.v b/src/microstepper/microstepper_control.v index 94d8576..cba55af 100644 --- a/src/microstepper/microstepper_control.v +++ b/src/microstepper/microstepper_control.v @@ -1,25 +1,29 @@ module microstepper_control ( input clk, input resetn, - output [3:0] s_l, - output [3:0] s_h, + output phase_a1_l_out, + output phase_a2_l_out, + output phase_b1_l_out, + output phase_b2_l_out, + output phase_a1_h_out, + output phase_a2_h_out, + output phase_b1_h_out, + output phase_b2_h_out, input [9:0] config_fastdecay_threshold, input config_invert_highside, input config_invert_lowside, input step, input dir, - input enable, + input enable_in, input analog_cmp1, input analog_cmp2, - output fault, + output faultn, input s1, input s2, input s3, input s4, output offtimer_en0, output offtimer_en1, - output a_starting, - output b_starting, output [7:0] phase_ct, input [7:0] blank_timer0, input [7:0] blank_timer1, @@ -27,103 +31,110 @@ module microstepper_control ( input [9:0] off_timer1, input [7:0] minimum_on_timer0, input [7:0] minimum_on_timer1, -// input off_timer0_done, -// input off_timer1_done, -// output step_b_out, +// input mixed_decay_enable, ); reg [7:0] phase_ct; -// reg [1:0] step_b; - -// wire step_edge = (step_b[2] ^ step_b[1]) && step_b[2]; - // step edge rising falling + reg [2:0] step_r; + reg [1:0] dir_r; + + reg enable; + + always @(posedge clk) begin + if (!resetn) + enable <= 0; + else + enable <= enable_in; + step_r <= {step_r[1:0], step}; + dir_r <= {dir_r[0], dir}; + end - reg [2:0] step_b; - reg [1:0] dir_b; -// wire step_b_out = step_b[2]; - wire step_rising = (step_b == 2'b01); + wire step_rising = (step_r == 2'b01); always @(posedge clk) begin if (!resetn) begin phase_ct <= 0; end - else if (step_rising) begin - phase_ct <= dir_b[1] ? phase_ct + 1 : phase_ct - 1; - end - step_b <= {step_b[1:0], step}; - dir_b <= {dir[0], dir}; + else if (step_rising) + phase_ct <= dir_r[1] ? phase_ct + 1 : phase_ct - 1; end - // Switch outputs + // Phase polarity control signal from microstep counter wire s1; wire s2; wire s3; wire s4; - // Off Timer active flag - wire off_timer_active0 = off_timer0 > 0; - wire off_timer_active1 = off_timer1 > 0; - - - wire fault0 = (minimum_on_timer0 > 0) && off_timer_active0; - wire fault1 = (minimum_on_timer1 > 0) && off_timer_active1; - wire fault = fault0 | fault1; + // Fault (active low) if off timer starts before minimum on timer expires + wire fault0 = off_timer0 && minimum_on_timer0 && enable; + wire fault1 = off_timer1 && minimum_on_timer1 && enable; + reg faultn; + // Fault latches until reset + always @(posedge clk) begin + if (!resetn) begin + fault0 <= 0; + fault1 <= 0; + faultn <= 1; + end + else if (faultn) begin + faultn <= ( fault0 | fault1 ) && enable; + end + end - reg [1:0] s1r, s2r, s3r, s4r; // Switch output history [ previous : now ] wire phase_a1_h, phase_a1_l, phase_a2_h, phase_a2_l; wire phase_b1_h, phase_b1_l, phase_b2_h, phase_b2_l; - // Switch output Low - assign s_l[0] = config_invert_lowside ^ (phase_a1_l | fault); - assign s_l[1] = config_invert_lowside ^ (phase_a2_l | fault); - assign s_l[2] = config_invert_lowside ^ (phase_b1_l | fault); - assign s_l[3] = config_invert_lowside ^ (phase_b2_l | fault); + // Low side output polarity, enable, and fault shutdown + assign phase_a1_l_out = config_invert_lowside ^ ( phase_a1_l | !enable ); + assign phase_a2_l_out = config_invert_lowside ^ ( phase_a2_l | !enable ); + assign phase_b1_l_out = config_invert_lowside ^ ( phase_b1_l | !enable ); + assign phase_b2_l_out = config_invert_lowside ^ ( phase_b2_l | !enable ); - // Switch output High - assign s_h[0] = config_invert_highside ^ (phase_a1_h | fault); - assign s_h[1] = config_invert_highside ^ (phase_a2_h | fault); - assign s_h[2] = config_invert_highside ^ (phase_b1_h | fault); - assign s_h[3] = config_invert_highside ^ (phase_b2_h | fault); + // High side + assign phase_a1_h_out = config_invert_highside ^ ( phase_a1_h && !faultn && enable ); + assign phase_a2_h_out = config_invert_highside ^ ( phase_a2_h && !faultn && enable ); + assign phase_b1_h_out = config_invert_highside ^ ( phase_b1_h && !faultn && enable ); + assign phase_b2_h_out = config_invert_highside ^ ( phase_b2_h && !faultn && enable ); // Fast decay is first x ticks of off time // default fast decay = 706 wire fastDecay0 = off_timer0 >= config_fastdecay_threshold; wire fastDecay1 = off_timer1 >= config_fastdecay_threshold; - // Slow decay remainder of off time - wire slowDecay0 = off_timer_active0 && fastDecay0 == 0; - wire slowDecay1 = off_timer_active1 && fastDecay1 == 0; - - // This portion of code sets up output to drive mosfets. Output ON = 0 - - // High side output logic - // If in slow decay = 1 - // OR ( fast decay and commanded to be OFF ) = 1 - // Then OFF - // Else If Not slow decay (Never in slow decay at same time as fast decay) - // OR ( not fast decay ) - // Then Follow commanded output - // Else if fast decay - // invert commanded polarity - assign phase_a1_h = slowDecay0 | ( fastDecay0 ? s1 : ~s1 ); + // Slow decay remainder of off time - Active high + wire slowDecay0 = off_timer0 && !fastDecay0; + wire slowDecay1 = off_timer1 && !fastDecay1; + + // This portion of code sets up output to drive mosfets. + // Output ON = 1 when config_invert_lowside and config_invert_highside == 0 + + // High side is ON if slow decay is NOT active + // AND + // ( + // In fast decay AND would normally be off this phase + // OR + // Should be on this phase / polarity + assign phase_a1_h = !slowDecay0 && ( fastDecay0 ? !s1 : s1 ); + assign phase_a2_h = !slowDecay0 && ( fastDecay0 ? !s2 : s2 ); + assign phase_b1_h = !slowDecay1 && ( fastDecay1 ? !s3 : s3 ); + assign phase_b2_h = !slowDecay1 && ( fastDecay1 ? !s4 : s4 ); // Low side output logic - // low side output (invert if configured with XOR) // Invert signal if fast decay commands. // If slow decay Then the output is low. // Else output = as commanded by microstep counter - assign phase_a1_l = fastDecay0 ? ~s1 : ( slowDecay0 ? 1'b0 : s1 ); - assign phase_a2_h = slowDecay0 | ( fastDecay0 ? s2 : ~s2 ); - assign phase_a2_l = fastDecay0 ? ~s2 : ( slowDecay0 ? 1'b0 : s2 ); - assign phase_b1_h = slowDecay1 | ( fastDecay1 ? s3 : ~s3 ); - assign phase_b1_l = fastDecay1 ? ~s3 : ( slowDecay1 ? 1'b0 : s3 ); - assign phase_b2_h = slowDecay1 | ( fastDecay1 ? s4 : ~s4 ); - assign phase_b2_l = fastDecay1 ? ~s4 : ( slowDecay1 ? 1'b0 : s4 ); - - // NEED DEAD TIME + // Low side is ON if slow decay is active + // OR + // Fast decay and would normally be off this phase + assign phase_a1_l = slowDecay0 | ( fastDecay0 ? s1 : !s1 ); + assign phase_a2_l = slowDecay0 | ( fastDecay0 ? s2 : !s2 ); + assign phase_b1_l = slowDecay1 | ( fastDecay1 ? s3 : !s3 ); + assign phase_b2_l = slowDecay1 | ( fastDecay1 ? s4 : !s4 ); + + // Fixed off time peak current controller // Start Off Time // Target peak current detected. Blank timer and Off timer not active - assign offtimer_en0 = analog_cmp1 & blank_timer0 == 0 & off_timer_active0 == 0; - assign offtimer_en1 = analog_cmp2 & blank_timer1 == 0 & off_timer_active1 == 0; + assign offtimer_en0 = analog_cmp1 & !blank_timer0 & !off_timer0; + assign offtimer_en1 = analog_cmp2 & !blank_timer1 & !off_timer1; `ifdef FORMAL always @(*) begin diff --git a/src/microstepper/microstepper_top.v b/src/microstepper/microstepper_top.v index cd43862..b4535f7 100644 --- a/src/microstepper/microstepper_top.v +++ b/src/microstepper/microstepper_top.v @@ -2,8 +2,14 @@ module microstepper_top ( input clk, input resetn, - output [3:0] s_l, - output [3:0] s_h, + output phase_a1_l, + output phase_a2_l, + output phase_b1_l, + output phase_b2_l, + output phase_a1_h, + output phase_a2_h, + output phase_b1_h, + output phase_b2_h, input analog_cmp1, output analog_out1, input analog_cmp2, @@ -11,6 +17,7 @@ module microstepper_top ( output chargepump_pin, input [9:0] config_offtime, input [7:0] config_blanktime, + input [2:0] config_deadtime, input [9:0] config_fastdecay_threshold, input [7:0] config_minimum_on_time, input [10:0] config_current_threshold, @@ -20,8 +27,8 @@ module microstepper_top ( //input [511:0] cos_table, input step, input dir, - input enable, - output fault, + input enable_in, + output faultn, ); wire [5:0] cos_index1; wire [5:0] cos_index2; @@ -43,25 +50,29 @@ module microstepper_top ( microstepper_control microstepper_control0( .clk(clk), .resetn(resetn), - .s_l(s_l), - .s_h(s_h), + .phase_a1_l_out(phase_a1_l), + .phase_a2_l_out(phase_a2_l), + .phase_b1_l_out(phase_b1_l), + .phase_b2_l_out(phase_b2_l), + .phase_a1_h_out(phase_a1_h), + .phase_a2_h_out(phase_a2_h), + .phase_b1_h_out(phase_b1_h), + .phase_b2_h_out(phase_b2_h), .config_fastdecay_threshold(config_fastdecay_threshold), .config_invert_highside(config_invert_highside), .config_invert_lowside(config_invert_lowside), .step(step), .dir(dir), - .enable(enable), + .enable_in(enable_in), .analog_cmp1(analog_cmp1), .analog_cmp2(analog_cmp2), - .fault(fault), + .faultn(faultn), .s1(s1), .s2(s2), .s3(s3), .s4(s4), .offtimer_en0(offtimer_en0), .offtimer_en1(offtimer_en1), - .a_starting(a_starting), - .b_starting(b_starting), .phase_ct(phase_ct), .blank_timer0(blank_timer0), .blank_timer1(blank_timer1), @@ -69,10 +80,11 @@ module microstepper_top ( .off_timer1(off_timer1), .minimum_on_timer0(minimum_on_timer0), .minimum_on_timer1(minimum_on_timer1), -// .off_timer0_done (off_timer0_done), -// .off_timer0_done (off_timer1_done), ); +wire [10:0] Woff_timer0_done; +wire [10:0] off_timer0_done; + mytimer_10 offtimer0 ( .clk (clk), .resetn (resetn), @@ -110,7 +122,7 @@ module microstepper_top ( mytimer_8 minimumontimer0 ( .clk (clk), .resetn (resetn), - .start_enable(a_starting), + .start_enable(off_timer0_done), .start_time (config_minimum_on_time), .timer (minimum_on_timer0) ); @@ -118,7 +130,7 @@ module microstepper_top ( mytimer_8 minimumontimer1 ( .clk (clk), .resetn (resetn), - .start_enable(b_starting), + .start_enable(off_timer1_done), .start_time (config_minimum_on_time), .timer (minimum_on_timer1) ); diff --git a/src/microstepper/mytimer_10.v b/src/microstepper/mytimer_10.v index d8c94a1..dc1db0f 100644 --- a/src/microstepper/mytimer_10.v +++ b/src/microstepper/mytimer_10.v @@ -14,8 +14,10 @@ module mytimer_10 ( assign timer = counter; always @(posedge clk) begin - if (!resetn) + if (!resetn) begin counter <= 0; + done <= 0; + end else if( start_enable ) begin counter <= start_time; run <= 1; diff --git a/src/top.v b/src/top.v index e23da82..b294e38 100644 --- a/src/top.v +++ b/src/top.v @@ -209,8 +209,14 @@ module top ( microstepper_top microstepper0( .clk(CLK), .resetn( resetn), - .s_l ({PHASE_B2[1], PHASE_B1[1], PHASE_A2[1], PHASE_A1[1]}), - .s_h ({PHASE_B2_H[1], PHASE_B1_H[1], PHASE_A2_H[1], PHASE_A1_H[1]}), + .phase_a1_l(PHASE_A1), + .phase_a2_l(PHASE_A2), + .phase_b1_l(PHASE_B1), + .phase_b2_l(PHASE_B2), + .phase_a1_h(PHASE_A1_H), + .phase_a2_h(PHASE_A2_H), + .phase_b1_h(PHASE_B1_H), + .phase_b2_h(PHASE_B2_H), .analog_cmp1 (analog_cmp1), .analog_out1 (analog_out1), .analog_cmp2 (analog_cmp2), diff --git a/testbench/hbridge_coil.v b/testbench/hbridge_coil.v index e37462b..98e46d5 100644 --- a/testbench/hbridge_coil.v +++ b/testbench/hbridge_coil.v @@ -7,6 +7,8 @@ module hbridge_coil ( input low_2, input high_2, output signed [12:0] current, + output current_sum_polarity, + input polarity_invert_config, ); reg signed [12:0] current; reg polarity; // arbitrary polarity @@ -14,10 +16,13 @@ module hbridge_coil ( reg [8:0] cnt; reg alive; reg slow_decay; - reg signed [2:0] current_ramp_cnt; // rates are delay counter sizes + reg signed current_ramp_cnt; // rates are delay counter sizes reg signed [3:0] slow_decay_cnt; reg signed [1:0] fast_decay_cnt; reg open; // coils not connected. Should never occur? + wire current_sum_polarity; + + assign current_sum_polarity = (current >= 0); // For each coil of motor // Each coil is driven by 2 half bridges. _1 and _2 // Each half bridge is driven by two drivers. high_ and low_ @@ -41,16 +46,23 @@ module hbridge_coil ( slow_decay_cnt <= slow_decay_cnt + 1; fast_decay_cnt <= fast_decay_cnt + 1; on <= ( low_1 && high_2 ) | ( low_2 && high_1 ); - polarity <= high_2 && low_1; + if ( polarity_invert_config ) + polarity <= high_2 && low_1; + else + polarity <= low_2 && high_1; slow_decay <= ( low_1 && low_2 ) | ( high_1 && high_2 ); if ( on ) begin - if ( polarity && !current_ramp_cnt ) - current <= current + 1; - else if ( !polarity && current && !fast_decay_cnt ) - current <= current - 1; + if ( polarity ) + current <= current + !current_ramp_cnt; + else + current <= current - !current_ramp_cnt; // fast decay + end + else if ( slow_decay && current !== 0 && !slow_decay_cnt ) begin + if (current >= 0) // current is positive + current <= current - 1; // slow decay every 4th tick + else + current <= current + 1; end - else if ( slow_decay && current && !slow_decay_cnt ) - current <= current - 1; // slow decay every 4th tick end end endmodule diff --git a/testbench/microstepper_tb.v b/testbench/microstepper_tb.v index 7869484..1662f2c 100644 --- a/testbench/microstepper_tb.v +++ b/testbench/microstepper_tb.v @@ -13,6 +13,7 @@ module testbench( output analog_out2, output chargepump_pin, output faultn, + output current_sum_polarity, ); reg step; @@ -43,11 +44,13 @@ module testbench( reg analog_cmp2; reg [40:0] step_clock; reg [20:0] cnt; + reg [12:0] current_abs1; + reg [12:0] current_abs2; always @(posedge clk) begin if (!resetn) begin cnt <= 0; - analog_cmp1 <= 0; - analog_cmp2 <= 0; + analog_cmp1 <= 1; + analog_cmp2 <= 1; step <= 1; enable_in <= 1; config_offtime = 810; @@ -56,25 +59,34 @@ module testbench( config_minimum_on_time = 54; config_current_threshold = 1024; config_chargepump_period = 91; - config_invert_highside = 0; - config_invert_lowside = 0; + config_invert_highside = 1; + config_invert_lowside = 1; step_clock = 0; end else begin cnt <= cnt + 1; enable_in <= 1; + if (current1[12] == 1'b1) begin + current_abs1 = -current; + end + else begin + current_abs1 = current1; + end + if (current2[12] == 1'b1) begin + current_abs2 = -current2; + end + else begin + current_abs2 = current2; + end step_clock <= step_clock + 1; - step <= step_clock[11]; - if (current1[12:0] > target_current1) analog_cmp1 <= 1; // compare unsigned - else analog_cmp1 <= 0; - if (current2[12:0] > target_current2) analog_cmp2 <= 1; - else analog_cmp2 <= 0; - if (cnt <= 20'hAEC) begin + step <= step_clock[10]; + analog_cmp1 <= (current_abs1[11:0] >= target_current1[11:0]); // compare unsigned + analog_cmp2 <= (current_abs2[11:0] >= target_current2[11:0]); + if (cnt <= 20'h4CA9) begin dir <= 1; end - else if (cnt <= 20'hEBE) begin + else dir <= 0; - end end end @@ -126,7 +138,9 @@ module testbench( .high_1(phase_a1_h), .low_2(phase_a2_l), .high_2(phase_a2_h), - .current(current1) + .current(current1), + .current_sum_polarity(current_sum_polarity), + .polarity_invert_config(1) ); hbridge_coil hbridge_coil2( .clk(clk), @@ -135,7 +149,9 @@ module testbench( .high_1(phase_b1_h), .low_2(phase_b2_l), .high_2(phase_b2_h), - .current(current2) + .current(current2), + .current_sum_polarity(current_sum_polarity), + .polarity_invert_config(1) ); endmodule From 17e4e67e4f576b252366f24fcd5181b2142a5b5f Mon Sep 17 00:00:00 2001 From: johnnyr Date: Sun, 6 Dec 2020 21:45:22 -0600 Subject: [PATCH 16/71] fix undeclared errors. add default_nettype none. --- src/microstepper/analog_out.v | 1 + src/microstepper/chargepump.v | 1 + src/microstepper/cosine.v | 1 + src/microstepper/microstep_counter.v | 1 + src/microstepper/microstepper_control.v | 32 ++++++++++--------------- src/microstepper/microstepper_top.v | 3 ++- src/microstepper/mytimer.v | 1 + src/microstepper/mytimer_10.v | 1 + src/microstepper/mytimer_8.v | 1 + src/quad_enc.v | 22 ----------------- src/top.v | 2 +- testbench/microstepper_tb.v | 22 ++++++++++++----- 12 files changed, 38 insertions(+), 50 deletions(-) diff --git a/src/microstepper/analog_out.v b/src/microstepper/analog_out.v index 1b55c55..b0a3305 100644 --- a/src/microstepper/analog_out.v +++ b/src/microstepper/analog_out.v @@ -1,3 +1,4 @@ +`default_nettype none module analog_out ( input wire clk, input wire resetn, diff --git a/src/microstepper/chargepump.v b/src/microstepper/chargepump.v index 9fad9c0..8550ddb 100644 --- a/src/microstepper/chargepump.v +++ b/src/microstepper/chargepump.v @@ -1,3 +1,4 @@ +`default_nettype none module chargepump ( input clk, input resetn, diff --git a/src/microstepper/cosine.v b/src/microstepper/cosine.v index 460e5cf..07d9631 100644 --- a/src/microstepper/cosine.v +++ b/src/microstepper/cosine.v @@ -1,3 +1,4 @@ +`default_nettype none module cosine ( input wire [5:0] cos_index, output wire [7:0] cos_value diff --git a/src/microstepper/microstep_counter.v b/src/microstepper/microstep_counter.v index 7ea6f0c..0453a57 100644 --- a/src/microstepper/microstep_counter.v +++ b/src/microstepper/microstep_counter.v @@ -1,3 +1,4 @@ +`default_nettype none module microstep_counter ( input [7:0] pos, output [5:0] cos_index1, diff --git a/src/microstepper/microstepper_control.v b/src/microstepper/microstepper_control.v index cba55af..cafe08b 100644 --- a/src/microstepper/microstepper_control.v +++ b/src/microstepper/microstepper_control.v @@ -1,3 +1,4 @@ +`default_nettype none module microstepper_control ( input clk, input resetn, @@ -71,8 +72,8 @@ module microstepper_control ( // Fault latches until reset always @(posedge clk) begin if (!resetn) begin - fault0 <= 0; - fault1 <= 0; +// fault0 <= 0; +// fault1 <= 0; faultn <= 1; end else if (faultn) begin @@ -104,35 +105,26 @@ module microstepper_control ( wire slowDecay0 = off_timer0 && !fastDecay0; wire slowDecay1 = off_timer1 && !fastDecay1; - // This portion of code sets up output to drive mosfets. - // Output ON = 1 when config_invert_lowside and config_invert_highside == 0 - - // High side is ON if slow decay is NOT active + // Half bridge high side is active + // WHEN slow decay is NOT active // AND - // ( - // In fast decay AND would normally be off this phase + // ( fast decay active AND would normally be off this phase ) // OR - // Should be on this phase / polarity + // Should be on to drive this phase / polarity (microstepper_counter) assign phase_a1_h = !slowDecay0 && ( fastDecay0 ? !s1 : s1 ); assign phase_a2_h = !slowDecay0 && ( fastDecay0 ? !s2 : s2 ); assign phase_b1_h = !slowDecay1 && ( fastDecay1 ? !s3 : s3 ); assign phase_b2_h = !slowDecay1 && ( fastDecay1 ? !s4 : s4 ); - // Low side output logic - // Invert signal if fast decay commands. - // If slow decay Then the output is low. - // Else output = as commanded by microstep counter - - // Low side is ON if slow decay is active + // Low side is active + // WHEN slow decay is active // OR - // Fast decay and would normally be off this phase + // ( Fast decay active AND would normally be off this phase ) assign phase_a1_l = slowDecay0 | ( fastDecay0 ? s1 : !s1 ); assign phase_a2_l = slowDecay0 | ( fastDecay0 ? s2 : !s2 ); assign phase_b1_l = slowDecay1 | ( fastDecay1 ? s3 : !s3 ); assign phase_b2_l = slowDecay1 | ( fastDecay1 ? s4 : !s4 ); - - // Fixed off time peak current controller - // Start Off Time - // Target peak current detected. Blank timer and Off timer not active + + // Fixed off time peak current controller off time start assign offtimer_en0 = analog_cmp1 & !blank_timer0 & !off_timer0; assign offtimer_en1 = analog_cmp2 & !blank_timer1 & !off_timer1; diff --git a/src/microstepper/microstepper_top.v b/src/microstepper/microstepper_top.v index b4535f7..e14e7a2 100644 --- a/src/microstepper/microstepper_top.v +++ b/src/microstepper/microstepper_top.v @@ -1,4 +1,4 @@ - +`default_nettype none module microstepper_top ( input clk, input resetn, @@ -46,6 +46,7 @@ module microstepper_top ( wire [9:0] off_timer1; wire [7:0] minimum_on_timer0; wire [7:0] minimum_on_timer1; + wire off_timer1_done; microstepper_control microstepper_control0( .clk(clk), diff --git a/src/microstepper/mytimer.v b/src/microstepper/mytimer.v index 4c11f73..1f5112b 100644 --- a/src/microstepper/mytimer.v +++ b/src/microstepper/mytimer.v @@ -1,3 +1,4 @@ +`default_nettype none module mytimer ( input clk, input resetn, diff --git a/src/microstepper/mytimer_10.v b/src/microstepper/mytimer_10.v index dc1db0f..d285dd4 100644 --- a/src/microstepper/mytimer_10.v +++ b/src/microstepper/mytimer_10.v @@ -1,3 +1,4 @@ +`default_nettype none module mytimer_10 ( input clk, input resetn, diff --git a/src/microstepper/mytimer_8.v b/src/microstepper/mytimer_8.v index 5519e6b..aacfcf8 100644 --- a/src/microstepper/mytimer_8.v +++ b/src/microstepper/mytimer_8.v @@ -1,3 +1,4 @@ +`default_nettype none module mytimer_8 ( input clk, input resetn, diff --git a/src/quad_enc.v b/src/quad_enc.v index e8ee9ab..7cabd2a 100755 --- a/src/quad_enc.v +++ b/src/quad_enc.v @@ -1,25 +1,3 @@ -/* UltiCores -- IP Cores for Mechatronic Control Systems - * - * Copyright (C) 2019 UltiMachine - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -/* quad_enc.v - * Quadrature decoder inspired by https://www.fpga4fun.com/QuadratureDecoder.html - * Converted to 32 bit. Added reset and fault logic. Changed some names to fit us. - */ - `default_nettype none module quad_enc #( diff --git a/src/top.v b/src/top.v index b294e38..fb9b8ab 100644 --- a/src/top.v +++ b/src/top.v @@ -233,7 +233,7 @@ module top ( //.cos_table (cos_table), .step (step), .dir (dir), - .enable(enable), + .enable_in(enable), ); `endif diff --git a/testbench/microstepper_tb.v b/testbench/microstepper_tb.v index 1662f2c..a71aed7 100644 --- a/testbench/microstepper_tb.v +++ b/testbench/microstepper_tb.v @@ -1,3 +1,4 @@ +`default_nettype none `include "../src/microstepper/microstepper_top.v" `include "hbridge_coil.v" `include "pwm_duty.v" @@ -18,7 +19,7 @@ module testbench( reg step; reg dir; - reg enable; + reg enable_in; reg [12:0] target_current1; reg [12:0] target_current2; reg signed [12:0] current1; @@ -46,6 +47,15 @@ module testbench( reg [20:0] cnt; reg [12:0] current_abs1; reg [12:0] current_abs2; + wire phase_a1_l; + wire phase_a2_l; + wire phase_b1_l; + wire phase_b2_l; + wire phase_a1_h; + wire phase_a2_h; + wire phase_b1_h; + wire phase_b2_h; + always @(posedge clk) begin if (!resetn) begin cnt <= 0; @@ -59,15 +69,15 @@ module testbench( config_minimum_on_time = 54; config_current_threshold = 1024; config_chargepump_period = 91; - config_invert_highside = 1; - config_invert_lowside = 1; + config_invert_highside = 0; + config_invert_lowside = 0; step_clock = 0; end else begin cnt <= cnt + 1; enable_in <= 1; if (current1[12] == 1'b1) begin - current_abs1 = -current; + current_abs1 = -current1; end else begin current_abs1 = current1; @@ -140,7 +150,7 @@ module testbench( .high_2(phase_a2_h), .current(current1), .current_sum_polarity(current_sum_polarity), - .polarity_invert_config(1) + .polarity_invert_config(0) ); hbridge_coil hbridge_coil2( .clk(clk), @@ -151,7 +161,7 @@ module testbench( .high_2(phase_b2_h), .current(current2), .current_sum_polarity(current_sum_polarity), - .polarity_invert_config(1) + .polarity_invert_config(0) ); endmodule From ef5d3478d787084192e50fa8cf9b7f00ee978c47 Mon Sep 17 00:00:00 2001 From: Steve Kelly Date: Sun, 6 Dec 2020 22:54:46 -0500 Subject: [PATCH 17/71] refactor wip --- Makefile | 2 +- src/rapcore.v | 252 ++++++------------------------------ src/spi_state_machine.v | 278 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 316 insertions(+), 216 deletions(-) create mode 100644 src/spi_state_machine.v diff --git a/Makefile b/Makefile index 2ddf69e..9fd8dc6 100755 --- a/Makefile +++ b/Makefile @@ -24,7 +24,7 @@ GENERATEDDIR = ./src/generated/ SRCDIR = ./src/ BUILDDIR = ./build/ BUILD = $(BUILDDIR)$(BOARD) -RAPCOREFILES := boards/$(BOARD)/$(BOARD).v src/constants.v src/macro_params.v src/pwm.v src/quad_enc.v src/spi.v src/stepper.v src/dda_timer.v src/rapcore.v $(wildcard src/microstepper/*.v) +RAPCOREFILES := boards/$(BOARD)/$(BOARD).v src/constants.v src/macro_params.v src/spi_state_machine.v src/pwm.v src/quad_enc.v src/spi.v src/stepper.v src/dda_timer.v src/rapcore.v $(wildcard src/microstepper/*.v) all: $(BUILD).bit diff --git a/src/rapcore.v b/src/rapcore.v index c8f206e..d8dfdec 100644 --- a/src/rapcore.v +++ b/src/rapcore.v @@ -68,33 +68,6 @@ module rapcore ( assign USBPU = 0; `endif - `ifdef SPIPLL - // PLL for SPI Bus - wire spi_clock; - wire spipll_locked; - spi_pll spll (.clock_in(CLK), - .clock_out(spi_clock), - .locked(spipll_locked)); - `else - wire spi_clock = CLK; - `endif - - // Word handler - // The system operates on 64 bit little endian words - // This should make it easier to send 64 bit chunks from the host controller - reg [63:0] word_send_data; - reg [63:0] word_data_received; - wire word_received; - SPIWord word_proc ( - .clk(spi_clock), - .SCK(SCK), - .CS(CS), - .COPI(COPI), - .CIPO(CIPO), - .word_send_data(word_send_data), - .word_received(word_received), - .word_data_received(word_data_received)); - //Reset wire resetn; reg [7:0] resetn_counter = 0; @@ -124,7 +97,6 @@ module rapcore ( wire dir; reg enable; - initial begin cos_table [ 7 : 0 ] = 255 ; cos_table [ 15 : 8 ] = 255 ; @@ -242,7 +214,6 @@ module rapcore ( // Encoder // reg signed [63:0] encoder_count; - reg signed [63:0] encoder_store; // Snapshot for SPI comms reg [7:0] encoder_multiplier = 1; wire encoder_fault; `ifdef QUAD_ENC @@ -259,193 +230,44 @@ module rapcore ( `endif // - // Stepper Timing Setup - // - - reg [`MOVE_BUFFER_BITS:0] moveind; // Move index cursor - - // Latching mechanism for engaging the buffered move. - reg [`MOVE_BUFFER_SIZE:0] stepready; - reg [`MOVE_BUFFER_SIZE:0] stepfinished; - - reg [63:0] move_duration [`MOVE_BUFFER_SIZE:0]; - reg [`MOVE_BUFFER_SIZE:0] dir_r; - - reg signed [63:0] increment [`MOVE_BUFFER_SIZE:0]; - reg signed [63:0] incrementincrement [`MOVE_BUFFER_SIZE:0]; - - reg [7:0] clock_divisor = 40; // should be 40 for 400 khz at 16Mhz Clk - - // DDA module input wires determined from buffer - wire [63:0] move_duration_w = move_duration[moveind]; - wire [63:0] increment_w = increment[moveind]; - wire [63:0] incrementincrement_w = incrementincrement[moveind]; - - wire dda_step; - - // Implement flow control and event pins if specified - `ifdef BUFFER_DTR - assign BUFFER_DTR = ~(~stepfinished == stepready); - `endif - - `ifndef STEPINPUT - assign dir = dir_r[moveind]; // set direction - assign step = dda_step; - `else - assign dir = dir_r[moveind] | DIRINPUT; // set direction - assign step = dda_step | STEPINPUT; - `endif - - `ifdef STEPOUTPUT - assign STEPOUTPUT = step; - assign DIROUTPUT = dir; - `endif - - dda_timer dda (.CLK(CLK), - .clock_divisor(clock_divisor), - .move_duration(move_duration_w), - .increment(increment_w), - .incrementincrement(incrementincrement_w), - .stepready(stepready), - .stepfinished(stepfinished), - .moveind(moveind), - .writemoveind(writemoveind), - .step(dda_step), - `ifdef HALT - .halt(HALT), - `endif - `ifdef MOVE_DONE - .move_done(MOVE_DONE), - `endif); - - // - // State Machine for handling SPI Messages + // SPI State Machine // - reg [7:0] message_word_count = 0; - reg [7:0] message_header; - reg [`MOVE_BUFFER_BITS:0] writemoveind = 0; - - // check if the Header indicated multi-word transfer - wire awaiting_more_words = (message_header == `CMD_COORDINATED_STEP) | - (message_header == `CMD_API_VERSION); - - always @(posedge word_received) begin - - // Zero out send data register - word_send_data <= 64'b0; - - // Header Processing - if (!awaiting_more_words) begin - - // Save CMD header incase multi word transaction - message_header <= word_data_received[63:56]; // Header is 8 MSB - - // First word so message count zero - message_word_count <= 1; - - case (word_data_received[63:56]) - - // Coordinated Move - `CMD_COORDINATED_STEP: begin - - // Get Direction Bits - dir_r[writemoveind] <= word_data_received[0]; - - // Store encoder values across all axes Now - encoder_store <= encoder_count; - - end - - // Motor Enable/disable - `CMD_MOTOR_ENABLE: begin - enable <= word_data_received[0]; - end - - // Clock divisor (24 bit) - `CMD_CLK_DIVISOR: begin - clock_divisor[7:0] <= word_data_received[7:0]; - end - - // Set Microstepping - `CMD_MOTORCONFIG: begin - // TODO needs to be power of two - current[7:0] <= word_data_received[15:8]; - microsteps[2:0] <= word_data_received[2:0]; - end - - // Set Microstepping Parameters - `CMD_MICROSTEPPER_CONFIG: begin - config_offtime[9:0] <= word_data_received[39:30]; - config_blanktime[7:0] <= word_data_received[29:22]; - config_fastdecay_threshold[9:0] <= word_data_received[21:12]; - config_minimum_on_time[7:0] <= word_data_received[18:11]; - config_current_threshold[10:0] <= word_data_received[10:0]; - end - - // Set chargepump period - `CMD_CHARGEPUMP: begin - config_chargepump_period[7:0] <= word_data_received[7:0]; - end - - // Invert Bridge outputs - `CMD_BRIDGEINVERT: begin - config_invert_highside <= word_data_received[1]; - config_invert_lowside <= word_data_received[0]; - end - - // Write to Cosine Table - `CMD_COSINE_CONFIG: begin - //config_cosine_table[word_data_received[35:32]] <= word_data_received[31:0]; - cos_table[word_data_received[37:32]] <= word_data_received[7:0]; - //cos_table[word_data_received[35:32]+3] <= word_data_received[31:25]; - //cos_table[word_data_received[35:32]+2] <= word_data_received[24:16]; - //cos_table[word_data_received[35:32]+1] <= word_data_received[15:8]; - //cos_table[word_data_received[35:32]] <= word_data_received[7:0]; - end - - // API Version - `CMD_API_VERSION: begin - word_send_data[7:0] <= `VERSION_PATCH; - word_send_data[15:8] <= `VERSION_MINOR; - word_send_data[23:16] <= `VERSION_MAJOR; - end - - endcase - - // Addition Word Processing - end else begin - - message_word_count <= message_word_count + 1; - - case (message_header) - // Move Routine - `CMD_COORDINATED_STEP: begin - // the first non-header word is the move duration - case (message_word_count) - 1: begin - move_duration[writemoveind][63:0] <= word_data_received[63:0]; - //word_send_data[63:0] = last_steps_taken[63:0]; // Prep to send steps - end - 2: begin - increment[writemoveind][63:0] <= word_data_received[63:0]; - word_send_data[63:0] <= encoder_store[63:0]; // Prep to send encoder read - end - 3: begin - incrementincrement[writemoveind][63:0] <= word_data_received[63:0]; - message_word_count <= 0; - stepready[writemoveind] <= ~stepready[writemoveind]; - writemoveind <= writemoveind + 1'b1; - message_header <= 8'b0; // Reset Message Header - `ifdef FORMAL - assert(writemoveind <= `MOVE_BUFFER_SIZE); - `endif - end - endcase - end - endcase - end - end - + spi_state_machine spifsm ( + .CLK(CLK), + .SCK(SCK), + .CS(CS), + .COPI(COPI), + .CIPO(CIPO), + .microsteps(microsteps), + .current(current), + .config_offtime(config_offtime), + .config_blanktime(config_blanktime), + .config_fastdecay_threshold(config_fastdecay_threshold), + .config_minimum_on_time(config_minimum_on_time), + .config_current_threshold(config_current_threshold), + .config_chargepump_period(config_chargepump_period), + .config_invert_highside(config_invert_highside), + .config_invert_lowside(config_invert_lowside), + //.cos_table(cos_table), // TODO + .encoder_count(encoder_count), + `ifdef BUFFER_DTR + .BUFFER_DTR(BUFFER_DTR), + `endif + `ifdef MOVE_DONE + .MOVE_DONE(MOVE_DONE), + `endif + `ifdef HALT + .HALT(HALT), + `endif + `ifdef STEPINPUT + .STEPINPUT(STEPINPUT), + .DIRINPUT(DIRINPUT), + `endif + `ifdef STEPOUTPUT + .STEPOUTPUT(STEPOUTPUT), + .DIROUTPUT(DIROUTPUT), + `endif + ); endmodule diff --git a/src/spi_state_machine.v b/src/spi_state_machine.v new file mode 100644 index 0000000..ba156a6 --- /dev/null +++ b/src/spi_state_machine.v @@ -0,0 +1,278 @@ +`default_nettype none + + +module spi_state_machine( + input CLK, + + // SPI pins + input SCK, + input CS, + input COPI, + output CIPO, + + // Step IO + output step, + output dir, + output enable, + + // Stepper Config + output reg [2:0] microsteps, + output reg [7:0] current, + output reg [9:0] config_offtime, + output reg [7:0] config_blanktime, + output reg [9:0] config_fastdecay_threshold, + output reg [7:0] config_minimum_on_time, + output reg [10:0] config_current_threshold, + output reg [7:0] config_chargepump_period, + output reg config_invert_highside, + output reg config_invert_lowside, + //output reg [511:0] cos_table, + + // encoder + input [63:0] encoder_count, + + // Event IO + `ifdef BUFFER_DTR + output BUFFER_DTR, + `endif + `ifdef MOVE_DONE + output MOVE_DONE, + `endif + `ifdef HALT + input HALT, + `endif + `ifdef STEPINPUT + input STEPINPUT, + input DIRINPUT, + `endif + `ifdef STEPOUTPUT + output STEPOUTPUT, + output DIROUTPUT, + `endif +); + + `ifdef SPIPLL + // PLL for SPI Bus + wire spi_clock; + wire spipll_locked; + spi_pll spll (.clock_in(CLK), + .clock_out(spi_clock), + .locked(spipll_locked)); + `else + wire spi_clock = CLK; + `endif + + // Word handler + // The system operates on 64 bit little endian words + // This should make it easier to send 64 bit chunks from the host controller + reg [63:0] word_send_data; + reg [63:0] word_data_received; + wire word_received; + SPIWord word_proc ( + .clk(spi_clock), + .SCK(SCK), + .CS(CS), + .COPI(COPI), + .CIPO(CIPO), + .word_send_data(word_send_data), + .word_received(word_received), + .word_data_received(word_data_received)); + + + + // + // Stepper Timing Setup + // + + reg [`MOVE_BUFFER_BITS:0] moveind; // Move index cursor + + // Latching mechanism for engaging the buffered move. + reg [`MOVE_BUFFER_SIZE:0] stepready; + reg [`MOVE_BUFFER_SIZE:0] stepfinished; + + reg [63:0] move_duration [`MOVE_BUFFER_SIZE:0]; + reg [`MOVE_BUFFER_SIZE:0] dir_r; + + reg signed [63:0] increment [`MOVE_BUFFER_SIZE:0]; + reg signed [63:0] incrementincrement [`MOVE_BUFFER_SIZE:0]; + + reg [7:0] clock_divisor = 40; // should be 40 for 400 khz at 16Mhz Clk + + // DDA module input wires determined from buffer + wire [63:0] move_duration_w = move_duration[moveind]; + wire [63:0] increment_w = increment[moveind]; + wire [63:0] incrementincrement_w = incrementincrement[moveind]; + + wire dda_step; + + // Implement flow control and event pins if specified + `ifdef BUFFER_DTR + assign BUFFER_DTR = ~(~stepfinished == stepready); + `endif + + `ifndef STEPINPUT + assign dir = dir_r[moveind]; // set direction + assign step = dda_step; + `else + assign dir = dir_r[moveind] | DIRINPUT; // set direction + assign step = dda_step | STEPINPUT; + `endif + + `ifdef STEPOUTPUT + assign STEPOUTPUT = step; + assign DIROUTPUT = dir; + `endif + + dda_timer dda (.CLK(CLK), + .clock_divisor(clock_divisor), + .move_duration(move_duration_w), + .increment(increment_w), + .incrementincrement(incrementincrement_w), + .stepready(stepready), + .stepfinished(stepfinished), + .moveind(moveind), + .writemoveind(writemoveind), + .step(dda_step), + `ifdef HALT + .halt(HALT), + `endif + `ifdef MOVE_DONE + .move_done(MOVE_DONE), + `endif); + + // + // State Machine for handling SPI Messages + // + + reg [7:0] message_word_count = 0; + reg [7:0] message_header; + reg [`MOVE_BUFFER_BITS:0] writemoveind = 0; + + // Encoder + reg signed [63:0] encoder_store; // Snapshot for SPI comms + + // check if the Header indicated multi-word transfer + wire awaiting_more_words = (message_header == `CMD_COORDINATED_STEP) | + (message_header == `CMD_API_VERSION); + + always @(posedge word_received) begin + + // Zero out send data register + word_send_data <= 64'b0; + + // Header Processing + if (!awaiting_more_words) begin + + // Save CMD header incase multi word transaction + message_header <= word_data_received[63:56]; // Header is 8 MSB + + // First word so message count zero + message_word_count <= 1; + + case (word_data_received[63:56]) + + // Coordinated Move + `CMD_COORDINATED_STEP: begin + + // Get Direction Bits + dir_r[writemoveind] <= word_data_received[0]; + + // Store encoder values across all axes Now + encoder_store <= encoder_count; + + end + + // Motor Enable/disable + `CMD_MOTOR_ENABLE: begin + enable <= word_data_received[0]; + end + + // Clock divisor (24 bit) + `CMD_CLK_DIVISOR: begin + clock_divisor[7:0] <= word_data_received[7:0]; + end + + // Set Microstepping + `CMD_MOTORCONFIG: begin + // TODO needs to be power of two + current[7:0] <= word_data_received[15:8]; + microsteps[2:0] <= word_data_received[2:0]; + end + + // Set Microstepping Parameters + `CMD_MICROSTEPPER_CONFIG: begin + config_offtime[9:0] <= word_data_received[39:30]; + config_blanktime[7:0] <= word_data_received[29:22]; + config_fastdecay_threshold[9:0] <= word_data_received[21:12]; + config_minimum_on_time[7:0] <= word_data_received[18:11]; + config_current_threshold[10:0] <= word_data_received[10:0]; + end + + // Set chargepump period + `CMD_CHARGEPUMP: begin + config_chargepump_period[7:0] <= word_data_received[7:0]; + end + + // Invert Bridge outputs + `CMD_BRIDGEINVERT: begin + config_invert_highside <= word_data_received[1]; + config_invert_lowside <= word_data_received[0]; + end + + // Write to Cosine Table + // TODO Cosine Net is broken + `CMD_COSINE_CONFIG: begin + //config_cosine_table[word_data_received[35:32]] <= word_data_received[31:0]; + //cos_table[word_data_received[37:32]] <= word_data_received[7:0]; + //cos_table[word_data_received[35:32]+3] <= word_data_received[31:25]; + //cos_table[word_data_received[35:32]+2] <= word_data_received[24:16]; + //cos_table[word_data_received[35:32]+1] <= word_data_received[15:8]; + //cos_table[word_data_received[35:32]] <= word_data_received[7:0]; + end + + // API Version + `CMD_API_VERSION: begin + word_send_data[7:0] <= `VERSION_PATCH; + word_send_data[15:8] <= `VERSION_MINOR; + word_send_data[23:16] <= `VERSION_MAJOR; + end + + endcase + + // Addition Word Processing + end else begin + + message_word_count <= message_word_count + 1; + + case (message_header) + // Move Routine + `CMD_COORDINATED_STEP: begin + // the first non-header word is the move duration + case (message_word_count) + 1: begin + move_duration[writemoveind][63:0] <= word_data_received[63:0]; + //word_send_data[63:0] = last_steps_taken[63:0]; // Prep to send steps + end + 2: begin + increment[writemoveind][63:0] <= word_data_received[63:0]; + word_send_data[63:0] <= encoder_store[63:0]; // Prep to send encoder read + end + 3: begin + incrementincrement[writemoveind][63:0] <= word_data_received[63:0]; + message_word_count <= 0; + stepready[writemoveind] <= ~stepready[writemoveind]; + writemoveind <= writemoveind + 1'b1; + message_header <= 8'b0; // Reset Message Header + `ifdef FORMAL + assert(writemoveind <= `MOVE_BUFFER_SIZE); + `endif + end + endcase + end + endcase + end + end + + + +endmodule From 579012097d723ae0146b451f0d469f50de842603 Mon Sep 17 00:00:00 2001 From: johnnyr Date: Sun, 6 Dec 2020 22:23:39 -0600 Subject: [PATCH 18/71] merget tb_m --- src/rapcore.v | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/rapcore.v b/src/rapcore.v index c8f206e..7e51a81 100644 --- a/src/rapcore.v +++ b/src/rapcore.v @@ -117,6 +117,7 @@ module rapcore ( reg [7:0] config_chargepump_period = 91; reg config_invert_highside = 0; reg config_invert_lowside = 0; + /* reg [511:0] cos_table; // Stepper control lines @@ -230,7 +231,7 @@ module rapcore ( .config_chargepump_period (config_chargepump_period), .config_invert_highside (config_invert_highside), .config_invert_lowside (config_invert_lowside), - .cos_table (cos_table), + //.cos_table (cos_table), .step (step), .dir (dir), .enable(enable), @@ -393,7 +394,7 @@ module rapcore ( config_invert_highside <= word_data_received[1]; config_invert_lowside <= word_data_received[0]; end - +/* // Write to Cosine Table `CMD_COSINE_CONFIG: begin //config_cosine_table[word_data_received[35:32]] <= word_data_received[31:0]; @@ -403,7 +404,7 @@ module rapcore ( //cos_table[word_data_received[35:32]+1] <= word_data_received[15:8]; //cos_table[word_data_received[35:32]] <= word_data_received[7:0]; end - +*/ // API Version `CMD_API_VERSION: begin word_send_data[7:0] <= `VERSION_PATCH; From d7e586d2fac3d5d088b613a50a09a6057f74b083 Mon Sep 17 00:00:00 2001 From: Tonokip Date: Mon, 30 Nov 2020 19:36:25 -0600 Subject: [PATCH 19/71] static cosine table --- src/microstepper/cosine.v | 206 +++++++++------------------- src/microstepper/microstepper_top.v | 6 +- 2 files changed, 68 insertions(+), 144 deletions(-) diff --git a/src/microstepper/cosine.v b/src/microstepper/cosine.v index 4a09583..460e5cf 100644 --- a/src/microstepper/cosine.v +++ b/src/microstepper/cosine.v @@ -1,150 +1,74 @@ module cosine ( input wire [5:0] cos_index, - output wire [7:0] cos_value, - input wire [511:0] cos_table + output wire [7:0] cos_value ); - - //reg [31:0] cos_table[0:255]; - - //assign cos_value = cos_table[cos_index*8+7:cos_index*8]; - reg [7:0] cos_r; assign cos_value = cos_r; - always @(*) case (cos_index) - 1'd0 : cos_r <= cos_table [ 7 : 0 ]; - 1'd1 : cos_r <= cos_table [ 15 : 8 ]; - 2'd2 : cos_r <= cos_table [ 23 : 16 ]; - 2'd3 : cos_r <= cos_table [ 31 : 24 ]; - 3'd4 : cos_r <= cos_table [ 39 : 32 ]; - 3'd5 : cos_r <= cos_table [ 47 : 40 ]; - 3'd6 : cos_r <= cos_table [ 55 : 48 ]; - 3'd7 : cos_r <= cos_table [ 63 : 56 ]; - 4'd8 : cos_r <= cos_table [ 71 : 64 ]; - 4'd9 : cos_r <= cos_table [ 79 : 72 ]; - 4'd10 : cos_r <= cos_table [ 87 : 80 ]; - 4'd11 : cos_r <= cos_table [ 95 : 88 ]; - 4'd12 : cos_r <= cos_table [ 103 : 96 ]; - 4'd13 : cos_r <= cos_table [ 111 : 104 ]; - 4'd14 : cos_r <= cos_table [ 119 : 112 ]; - 4'd15 : cos_r <= cos_table [ 127 : 120 ]; - 5'd16 : cos_r <= cos_table [ 135 : 128 ]; - 5'd17 : cos_r <= cos_table [ 143 : 136 ]; - 5'd18 : cos_r <= cos_table [ 151 : 144 ]; - 5'd19 : cos_r <= cos_table [ 159 : 152 ]; - 5'd20 : cos_r <= cos_table [ 167 : 160 ]; - 5'd21 : cos_r <= cos_table [ 175 : 168 ]; - 5'd22 : cos_r <= cos_table [ 183 : 176 ]; - 5'd23 : cos_r <= cos_table [ 191 : 184 ]; - 5'd24 : cos_r <= cos_table [ 199 : 192 ]; - 5'd25 : cos_r <= cos_table [ 207 : 200 ]; - 5'd26 : cos_r <= cos_table [ 215 : 208 ]; - 5'd27 : cos_r <= cos_table [ 223 : 216 ]; - 5'd28 : cos_r <= cos_table [ 231 : 224 ]; - 5'd29 : cos_r <= cos_table [ 239 : 232 ]; - 5'd30 : cos_r <= cos_table [ 247 : 240 ]; - 5'd31 : cos_r <= cos_table [ 255 : 248 ]; - 6'd32 : cos_r <= cos_table [ 263 : 256 ]; - 6'd33 : cos_r <= cos_table [ 271 : 264 ]; - 6'd34 : cos_r <= cos_table [ 279 : 272 ]; - 6'd35 : cos_r <= cos_table [ 287 : 280 ]; - 6'd36 : cos_r <= cos_table [ 295 : 288 ]; - 6'd37 : cos_r <= cos_table [ 303 : 296 ]; - 6'd38 : cos_r <= cos_table [ 311 : 304 ]; - 6'd39 : cos_r <= cos_table [ 319 : 312 ]; - 6'd40 : cos_r <= cos_table [ 327 : 320 ]; - 6'd41 : cos_r <= cos_table [ 335 : 328 ]; - 6'd42 : cos_r <= cos_table [ 343 : 336 ]; - 6'd43 : cos_r <= cos_table [ 351 : 344 ]; - 6'd44 : cos_r <= cos_table [ 359 : 352 ]; - 6'd45 : cos_r <= cos_table [ 367 : 360 ]; - 6'd46 : cos_r <= cos_table [ 375 : 368 ]; - 6'd47 : cos_r <= cos_table [ 383 : 376 ]; - 6'd48 : cos_r <= cos_table [ 391 : 384 ]; - 6'd49 : cos_r <= cos_table [ 399 : 392 ]; - 6'd50 : cos_r <= cos_table [ 407 : 400 ]; - 6'd51 : cos_r <= cos_table [ 415 : 408 ]; - 6'd52 : cos_r <= cos_table [ 423 : 416 ]; - 6'd53 : cos_r <= cos_table [ 431 : 424 ]; - 6'd54 : cos_r <= cos_table [ 439 : 432 ]; - 6'd55 : cos_r <= cos_table [ 447 : 440 ]; - 6'd56 : cos_r <= cos_table [ 455 : 448 ]; - 6'd57 : cos_r <= cos_table [ 463 : 456 ]; - 6'd58 : cos_r <= cos_table [ 471 : 464 ]; - 6'd59 : cos_r <= cos_table [ 479 : 472 ]; - 6'd60 : cos_r <= cos_table [ 487 : 480 ]; - 6'd61 : cos_r <= cos_table [ 495 : 488 ]; - 6'd62 : cos_r <= cos_table [ 503 : 496 ]; - default : cos_r <= cos_table [ 511 : 504 ]; + 1'd0: cos_r <= 255; + 1'd1: cos_r <= 255; + 2'd2: cos_r <= 255; + 2'd3: cos_r <= 254; + 3'd4: cos_r <= 254; + 3'd5: cos_r <= 253; + 3'd6: cos_r <= 252; + 3'd7: cos_r <= 251; + 4'd8: cos_r <= 250; + 4'd9: cos_r <= 249; + 4'd10: cos_r <= 247; + 4'd11: cos_r <= 246; + 4'd12: cos_r <= 244; + 4'd13: cos_r <= 242; + 4'd14: cos_r <= 240; + 4'd15: cos_r <= 238; + 5'd16: cos_r <= 236; + 5'd17: cos_r <= 233; + 5'd18: cos_r <= 231; + 5'd19: cos_r <= 228; + 5'd20: cos_r <= 225; + 5'd21: cos_r <= 222; + 5'd22: cos_r <= 219; + 5'd23: cos_r <= 215; + 5'd24: cos_r <= 212; + 5'd25: cos_r <= 208; + 5'd26: cos_r <= 205; + 5'd27: cos_r <= 201; + 5'd28: cos_r <= 197; + 5'd29: cos_r <= 193; + 5'd30: cos_r <= 189; + 5'd31: cos_r <= 185; + 6'd32: cos_r <= 180; + 6'd33: cos_r <= 176; + 6'd34: cos_r <= 171; + 6'd35: cos_r <= 167; + 6'd36: cos_r <= 162; + 6'd37: cos_r <= 157; + 6'd38: cos_r <= 152; + 6'd39: cos_r <= 147; + 6'd40: cos_r <= 142; + 6'd41: cos_r <= 136; + 6'd42: cos_r <= 131; + 6'd43: cos_r <= 126; + 6'd44: cos_r <= 120; + 6'd45: cos_r <= 115; + 6'd46: cos_r <= 109; + 6'd47: cos_r <= 103; + 6'd48: cos_r <= 98; + 6'd49: cos_r <= 92; + 6'd50: cos_r <= 86; + 6'd51: cos_r <= 80; + 6'd52: cos_r <= 74; + 6'd53: cos_r <= 68; + 6'd54: cos_r <= 62; + 6'd55: cos_r <= 56; + 6'd56: cos_r <= 50; + 6'd57: cos_r <= 44; + 6'd58: cos_r <= 37; + 6'd59: cos_r <= 31; + 6'd60: cos_r <= 25; + 6'd61: cos_r <= 19; + 6'd62: cos_r <= 13; + default: cos_r <= 6; endcase - -/* - initial begin - cos_table[0] = 8'd255; - cos_table[1] = 8'd255; - cos_table[2] = 8'd255; - cos_table[3] = 8'd254; - cos_table[4] = 8'd254; - cos_table[5] = 8'd253; - cos_table[6] = 8'd252; - cos_table[7] = 8'd251; - cos_table[8] = 8'd250; - cos_table[9] = 8'd249; - cos_table[10] = 8'd247; - cos_table[11] = 8'd246; - cos_table[12] = 8'd244; - cos_table[13] = 8'd242; - cos_table[14] = 8'd240; - cos_table[15] = 8'd238; - cos_table[16] = 8'd236; - cos_table[17] = 8'd233; - cos_table[18] = 8'd231; - cos_table[19] = 8'd228; - cos_table[20] = 8'd225; - cos_table[21] = 8'd222; - cos_table[22] = 8'd219; - cos_table[23] = 8'd215; - cos_table[24] = 8'd212; - cos_table[25] = 8'd208; - cos_table[26] = 8'd205; - cos_table[27] = 8'd201; - cos_table[28] = 8'd197; - cos_table[29] = 8'd193; - cos_table[30] = 8'd189; - cos_table[31] = 8'd185; - cos_table[32] = 8'd180; - cos_table[33] = 8'd176; - cos_table[34] = 8'd171; - cos_table[35] = 8'd167; - cos_table[36] = 8'd162; - cos_table[37] = 8'd157; - cos_table[38] = 8'd152; - cos_table[39] = 8'd147; - cos_table[40] = 8'd142; - cos_table[41] = 8'd136; - cos_table[42] = 8'd131; - cos_table[43] = 8'd126; - cos_table[44] = 8'd120; - cos_table[45] = 8'd115; - cos_table[46] = 8'd109; - cos_table[47] = 8'd103; - cos_table[48] = 8'd98; - cos_table[49] = 8'd92; - cos_table[50] = 8'd86; - cos_table[51] = 8'd80; - cos_table[52] = 8'd74; - cos_table[53] = 8'd68; - cos_table[54] = 8'd62; - cos_table[55] = 8'd56; - cos_table[56] = 8'd50; - cos_table[57] = 8'd44; - cos_table[58] = 8'd37; - cos_table[59] = 8'd31; - cos_table[60] = 8'd25; - cos_table[61] = 8'd19; - cos_table[62] = 8'd13; - cos_table[63] = 8'd6; - end - */ endmodule diff --git a/src/microstepper/microstepper_top.v b/src/microstepper/microstepper_top.v index e2438aa..7f33371 100644 --- a/src/microstepper/microstepper_top.v +++ b/src/microstepper/microstepper_top.v @@ -17,7 +17,7 @@ module microstepper_top ( input [7:0] config_chargepump_period, input config_invert_highside, input config_invert_lowside, - input [511:0] cos_table, + //input [511:0] cos_table, input step, input dir, input enable @@ -180,13 +180,13 @@ end cosine cosine0 ( .cos_index(cos_index1), .cos_value(pwm1), - .cos_table(cos_table) + //.cos_table(cos_table) ); cosine cosine1 ( .cos_index(cos_index2), .cos_value(pwm2), - .cos_table(cos_table) + //.cos_table(cos_table) ); analog_out ao0 ( From 6ce491f9f6ebd5f9c6103acc4d09a5940eeaa77d Mon Sep 17 00:00:00 2001 From: johnnyr Date: Tue, 1 Dec 2020 01:41:35 -0600 Subject: [PATCH 20/71] preset params for mytimers --- src/microstepper/microstepper_top.v | 12 ++++++------ src/microstepper/mytimer_10.v | 29 +++++++++++++++++++++++++++++ src/microstepper/mytimer_8.v | 29 +++++++++++++++++++++++++++++ 3 files changed, 64 insertions(+), 6 deletions(-) create mode 100644 src/microstepper/mytimer_10.v create mode 100644 src/microstepper/mytimer_8.v diff --git a/src/microstepper/microstepper_top.v b/src/microstepper/microstepper_top.v index 7f33371..5df12af 100644 --- a/src/microstepper/microstepper_top.v +++ b/src/microstepper/microstepper_top.v @@ -103,7 +103,7 @@ end s4r <= {s4r[0], s4}; end - mytimer #( + mytimer_10 #( .WIDTH(10) ) offtimer0 ( .clk (clk), @@ -113,7 +113,7 @@ end .timer (off_timer0) ); - mytimer #( + mytimer_10 #( .WIDTH(10) ) offtimer1 ( .clk (clk), @@ -123,7 +123,7 @@ end .timer (off_timer1) ); - mytimer #( + mytimer_8 #( .WIDTH(8) ) blanktimer0 ( .clk (clk), @@ -133,7 +133,7 @@ end .timer (blank_timer0) ); - mytimer #( + mytimer_8 #( .WIDTH(8) ) blanktimer1 ( .clk (clk), @@ -143,7 +143,7 @@ end .timer (blank_timer1) ); - mytimer #( + mytimer_8 #( .WIDTH(8) ) minimumontimer0 ( .clk (clk), @@ -153,7 +153,7 @@ end .timer (minimum_on_timer0) ); - mytimer #( + mytimer_8 #( .WIDTH(8) ) minimumontimer1 ( .clk (clk), diff --git a/src/microstepper/mytimer_10.v b/src/microstepper/mytimer_10.v new file mode 100644 index 0000000..6648329 --- /dev/null +++ b/src/microstepper/mytimer_10.v @@ -0,0 +1,29 @@ +module mytimer_10 ( + clk, + resetn, + start_enable, + start_time, + timer +); + parameter WIDTH = 10; + + input clk; + input resetn; + input start_enable; + input [WIDTH-1:0] start_time; + output [WIDTH-1:0] timer; + + reg [WIDTH-1:0] counter; + + assign timer = counter; + + always @(posedge clk) begin + if (!resetn) + counter <= 0; + else if( start_enable ) + counter <= start_time; + else if( counter > 0 ) + counter <= counter - 1'b1; +end + +endmodule diff --git a/src/microstepper/mytimer_8.v b/src/microstepper/mytimer_8.v new file mode 100644 index 0000000..1710bab --- /dev/null +++ b/src/microstepper/mytimer_8.v @@ -0,0 +1,29 @@ +module mytimer_8 ( + clk, + resetn, + start_enable, + start_time, + timer +); + parameter WIDTH = 8; + + input clk; + input resetn; + input start_enable; + input [WIDTH-1:0] start_time; + output [WIDTH-1:0] timer; + + reg [WIDTH-1:0] counter; + + assign timer = counter; + + always @(posedge clk) begin + if (!resetn) + counter <= 0; + else if( start_enable ) + counter <= start_time; + else if( counter > 0 ) + counter <= counter - 1'b1; +end + +endmodule From 08bfe85b9accd7989264cb6abac16ee89be00fd6 Mon Sep 17 00:00:00 2001 From: johnnyr Date: Tue, 1 Dec 2020 18:28:01 -0600 Subject: [PATCH 21/71] mscontrol --- src/microstepper/microstepper_control.v | 105 +++++++++++++++++++ src/microstepper/microstepper_top.v | 129 ++++++++---------------- 2 files changed, 147 insertions(+), 87 deletions(-) create mode 100644 src/microstepper/microstepper_control.v diff --git a/src/microstepper/microstepper_control.v b/src/microstepper/microstepper_control.v new file mode 100644 index 0000000..68e9c04 --- /dev/null +++ b/src/microstepper/microstepper_control.v @@ -0,0 +1,105 @@ +module microstepper_control ( + input clk, + output [3:0] s_l, + output [3:0] s_h, + input [9:0] config_fastdecay_threshold, + input config_invert_highside, + input config_invert_lowside, + input step, + input dir, + input enable, + input analog_cmp1, + input analog_cmp2, + output fault, + input s1, + input s2, + input s3, + input s4, + output offtimer_en0, + output offtimer_en0, + output a_starting, + output b_starting, + output [7:0] phase_ct, + input [7:0] blank_timer0, + input [7:0] blank_timer1, + input [9:0] off_timer0, + input [9:0] off_timer1, + input [7:0] minimum_on_timer0, + input [7:0] minimum_on_timer1, +); + reg [7:0] phase_ct; + + always @(posedge step) begin + phase_ct <= phase_ct + (dir ? 1 : -1); + end + + wire s1; + wire s2; + wire s3; + wire s4; + + wire overCurrent0 = off_timer0 > 0; + wire overCurrent1 = off_timer1 > 0; + + wire fastDecay0 = off_timer0 >= config_fastdecay_threshold; + wire fastDecay1 = off_timer1 >= config_fastdecay_threshold; + + wire slowDecay0 = overCurrent0 && fastDecay0 == 0; + wire slowDecay1 = overCurrent1 && fastDecay1 == 0; + + wire fault0 = (minimum_on_timer0 > 0) && overCurrent0; + wire fault1 = (minimum_on_timer1 > 0) && overCurrent1; + wire fault = fault0 | fault1; + + reg [1:0] s1r, s2r, s3r, s4r; + wire phase_a1_h, phase_a1_l, phase_a2_h, phase_a2_l; + wire phase_b1_h, phase_b1_l, phase_b2_h, phase_b2_l; + + assign s_l[0] = !(phase_a1_l | fault); + assign s_l[1] = !(phase_a2_l | fault); + assign s_l[2] = !(phase_b1_l | fault); + assign s_l[3] = !(phase_b2_l | fault); + + assign s_h[0] = !(phase_a1_h | fault); + assign s_h[1] = !(phase_a2_h | fault); + assign s_h[2] = !(phase_b1_h | fault); + assign s_h[3] = !(phase_b2_h | fault); + + assign phase_a1_h = config_invert_highside ^ (slowDecay0 | (fastDecay0 ? s1r[1] : ~s1r[1])); + assign phase_a1_l = config_invert_lowside ^ (fastDecay0 ? ~s1r[1] : (slowDecay0 ? 1'b0 : s1r[1])); + assign phase_a2_h = config_invert_highside ^ (slowDecay0 | (fastDecay0 ? s2r[1] : ~s2r[1])); + assign phase_a2_l = config_invert_lowside ^ (fastDecay0 ? ~s2r[1] : (slowDecay0 ? 1'b0 : s2r[1])); + + assign phase_b1_h = config_invert_highside ^ (slowDecay1 | (fastDecay1 ? s3r[1] : ~s3r[1])); + assign phase_b1_l = config_invert_lowside ^ (fastDecay1 ? ~s3r[1] : (slowDecay1 ? 1'b0 : s3r[1])); + assign phase_b2_h = config_invert_highside ^ (slowDecay1 | (fastDecay1 ? s4r[1] : ~s4r[1])); + assign phase_b2_l = config_invert_lowside ^ (fastDecay1 ? ~s4r[1] : (slowDecay1 ? 1'b0 : s4r[1])); + + + wire s1_starting = s1r == 2'b10; + wire s2_starting = s2r == 2'b10; + wire s3_starting = s3r == 2'b10; + wire s4_starting = s4r == 2'b10; + + assign offtimer_en0 = analog_cmp1 & blank_timer0 == 0 & overCurrent0 == 0; + assign offtimer_en0 = analog_cmp2 & blank_timer1 == 0 & overCurrent1 == 0; + assign a_starting = s1_starting | s2_starting; + assign b_starting = s3_starting | s4_starting; + +`ifdef FORMAL + always @(*) begin + assert (!(phase_a1_l == 0 && phase_a1_h == 0)); + assert (!(phase_a2_l == 0 && phase_a2_h == 0)); + assert (!(phase_b1_l == 0 && phase_b1_h == 0)); + assert (!(phase_b2_l == 0 && phase_b2_h == 0)); + end +`endif + + always @(posedge clk) begin + s1r <= {s1r[0], s1}; + s2r <= {s2r[0], s2}; + s3r <= {s3r[0], s3}; + s4r <= {s4r[0], s4}; + end + +endmodule \ No newline at end of file diff --git a/src/microstepper/microstepper_top.v b/src/microstepper/microstepper_top.v index 5df12af..f9df678 100644 --- a/src/microstepper/microstepper_top.v +++ b/src/microstepper/microstepper_top.v @@ -20,95 +20,50 @@ module microstepper_top ( //input [511:0] cos_table, input step, input dir, - input enable + input enable, + output fault, +); + wire [5:0] cos_index1; + wire [5:0] cos_index2; + wire [7:0] pwm1; + wire [7:0] pwm2; + + microstepper_control m_control_0( + .clk(clk), + .s_l(s_l), + .s_h(s_h), + .config_fastdecay_threshold(config_fastdecay_threshold), + .config_invert_highside(config_invert_highside), + .config_invert_lowside(config_invert_lowside), + .step(step), + .dir(dir), + .enable(enable), + .analog_cmp1(analog_cmp1), + .analog_cmp2(analog_cmp2), + .fault(fault), + .s1(s1), + .s2(s2), + .s3(s3), + .s4(s4), + .offtimer_en0(offtimer_en0), + .offtimer_en0(offtimer_en0), + .a_starting(a_starting), + .b_starting(b_starting), + .phase_ct(phase_ct), + .blank_timer0(blank_timer0), + .blank_timer1(blank_timer1), + .off_timer0(off_timer0), + .off_timer1(off_timer1), + .minimum_on_timer0(minimum_on_timer0), + .minimum_on_timer1(minimum_on_timer1), ); - - reg [7:0] phase_ct; - - always @(posedge step) begin - phase_ct <= phase_ct + (dir ? 1 : -1); -end - - wire [5:0] cos_index1; - wire [5:0] cos_index2; - wire s1; - wire s2; - wire s3; - wire s4; - wire [7:0] pwm1; - wire [7:0] pwm2; - - reg [7:0] blank_timer0; - reg [7:0] blank_timer1; - reg [9:0] off_timer0; - reg [9:0] off_timer1; - reg [7:0] minimum_on_timer0; - reg [7:0] minimum_on_timer1; - - wire overCurrent0 = off_timer0 > 0; - wire overCurrent1 = off_timer1 > 0; - - wire fastDecay0 = off_timer0 >= config_fastdecay_threshold; - wire fastDecay1 = off_timer1 >= config_fastdecay_threshold; - - wire slowDecay0 = overCurrent0 && fastDecay0 == 0; - wire slowDecay1 = overCurrent1 && fastDecay1 == 0; - - wire fault0 = (minimum_on_timer0 > 0) && overCurrent0; - wire fault1 = (minimum_on_timer1 > 0) && overCurrent1; - wire fault = fault0 | fault1; - - reg [1:0] s1r, s2r, s3r, s4r; - wire phase_a1_h, phase_a1_l, phase_a2_h, phase_a2_l; - wire phase_b1_h, phase_b1_l, phase_b2_h, phase_b2_l; - - assign s_l[0] = !(phase_a1_l | fault); - assign s_l[1] = !(phase_a2_l | fault); - assign s_l[2] = !(phase_b1_l | fault); - assign s_l[3] = !(phase_b2_l | fault); - - assign s_h[0] = !(phase_a1_h | fault); - assign s_h[1] = !(phase_a2_h | fault); - assign s_h[2] = !(phase_b1_h | fault); - assign s_h[3] = !(phase_b2_h | fault); - - assign phase_a1_h = config_invert_highside ^ (slowDecay0 | (fastDecay0 ? s1r[1] : ~s1r[1])); - assign phase_a1_l = config_invert_lowside ^ (fastDecay0 ? ~s1r[1] : (slowDecay0 ? 1'b0 : s1r[1])); - assign phase_a2_h = config_invert_highside ^ (slowDecay0 | (fastDecay0 ? s2r[1] : ~s2r[1])); - assign phase_a2_l = config_invert_lowside ^ (fastDecay0 ? ~s2r[1] : (slowDecay0 ? 1'b0 : s2r[1])); - - assign phase_b1_h = config_invert_highside ^ (slowDecay1 | (fastDecay1 ? s3r[1] : ~s3r[1])); - assign phase_b1_l = config_invert_lowside ^ (fastDecay1 ? ~s3r[1] : (slowDecay1 ? 1'b0 : s3r[1])); - assign phase_b2_h = config_invert_highside ^ (slowDecay1 | (fastDecay1 ? s4r[1] : ~s4r[1])); - assign phase_b2_l = config_invert_lowside ^ (fastDecay1 ? ~s4r[1] : (slowDecay1 ? 1'b0 : s4r[1])); - - wire s1_starting = s1r == 2'b10; - wire s2_starting = s2r == 2'b10; - wire s3_starting = s3r == 2'b10; - wire s4_starting = s4r == 2'b10; - -`ifdef FORMAL - always @(*) begin - assert (!(phase_a1_l == 0 && phase_a1_h == 0)); - assert (!(phase_a2_l == 0 && phase_a2_h == 0)); - assert (!(phase_b1_l == 0 && phase_b1_h == 0)); - assert (!(phase_b2_l == 0 && phase_b2_h == 0)); - end -`endif - - always @(posedge clk) begin - s1r <= {s1r[0], s1}; - s2r <= {s2r[0], s2}; - s3r <= {s3r[0], s3}; - s4r <= {s4r[0], s4}; - end mytimer_10 #( .WIDTH(10) ) offtimer0 ( .clk (clk), .resetn (resetn), - .start_enable(analog_cmp1 & blank_timer0 == 0 & overCurrent0 == 0), + .start_enable(offtimer_en0), .start_time (config_offtime), .timer (off_timer0) ); @@ -118,7 +73,7 @@ end ) offtimer1 ( .clk (clk), .resetn (resetn), - .start_enable(analog_cmp2 & blank_timer1 == 0 & overCurrent1 == 0), + .start_enable(offtimer_en1), .start_time (config_offtime), .timer (off_timer1) ); @@ -128,7 +83,7 @@ end ) blanktimer0 ( .clk (clk), .resetn (resetn), - .start_enable(s1_starting | s2_starting), + .start_enable(a_starting), .start_time (config_blanktime), .timer (blank_timer0) ); @@ -138,7 +93,7 @@ end ) blanktimer1 ( .clk (clk), .resetn (resetn), - .start_enable(s3_starting | s4_starting), + .start_enable(b_starting), .start_time (config_blanktime), .timer (blank_timer1) ); @@ -148,7 +103,7 @@ end ) minimumontimer0 ( .clk (clk), .resetn (resetn), - .start_enable(s1_starting | s2_starting), + .start_enable(a_starting), .start_time (config_minimum_on_time), .timer (minimum_on_timer0) ); @@ -158,7 +113,7 @@ end ) minimumontimer1 ( .clk (clk), .resetn (resetn), - .start_enable(s3_starting | s4_starting), + .start_enable(b_starting), .start_time (config_minimum_on_time), .timer (minimum_on_timer1) ); From f78d0f663f2afa169097a529c695dbe90e9c7b6f Mon Sep 17 00:00:00 2001 From: Tonokip Date: Tue, 1 Dec 2020 20:03:15 -0600 Subject: [PATCH 22/71] reuse mytimer for mytimer_8 and mytimer_10 --- src/microstepper/mytimer_10.v | 28 +++++++++------------------- src/microstepper/mytimer_8.v | 28 +++++++++------------------- 2 files changed, 18 insertions(+), 38 deletions(-) diff --git a/src/microstepper/mytimer_10.v b/src/microstepper/mytimer_10.v index 6648329..93a73ad 100644 --- a/src/microstepper/mytimer_10.v +++ b/src/microstepper/mytimer_10.v @@ -5,25 +5,15 @@ module mytimer_10 ( start_time, timer ); - parameter WIDTH = 10; - input clk; - input resetn; - input start_enable; - input [WIDTH-1:0] start_time; - output [WIDTH-1:0] timer; - - reg [WIDTH-1:0] counter; - - assign timer = counter; - - always @(posedge clk) begin - if (!resetn) - counter <= 0; - else if( start_enable ) - counter <= start_time; - else if( counter > 0 ) - counter <= counter - 1'b1; -end + mytimer #( + .WIDTH(8) + ) mytimer8 ( + .clk (clk), + .resetn (resetn), + .start_enable(start_enable), + .start_time (start_time), + .timer (timer) + ); endmodule diff --git a/src/microstepper/mytimer_8.v b/src/microstepper/mytimer_8.v index 1710bab..c61be86 100644 --- a/src/microstepper/mytimer_8.v +++ b/src/microstepper/mytimer_8.v @@ -5,25 +5,15 @@ module mytimer_8 ( start_time, timer ); - parameter WIDTH = 8; - input clk; - input resetn; - input start_enable; - input [WIDTH-1:0] start_time; - output [WIDTH-1:0] timer; - - reg [WIDTH-1:0] counter; - - assign timer = counter; - - always @(posedge clk) begin - if (!resetn) - counter <= 0; - else if( start_enable ) - counter <= start_time; - else if( counter > 0 ) - counter <= counter - 1'b1; -end + mytimer #( + .WIDTH(8) + ) mytimer8 ( + .clk (clk), + .resetn (resetn), + .start_enable(start_enable), + .start_time (start_time), + .timer (timer) + ); endmodule From 71abd03ca44a2fe35bc68d6f35a042a667be742f Mon Sep 17 00:00:00 2001 From: Tonokip Date: Tue, 1 Dec 2020 20:42:40 -0600 Subject: [PATCH 23/71] timer fixes and missing wires --- src/microstepper/microstepper_control.v | 6 ++-- src/microstepper/microstepper_top.v | 38 ++++++++++++------------- src/microstepper/mytimer_10.v | 11 +++++-- src/microstepper/mytimer_8.v | 9 +++++- 4 files changed, 39 insertions(+), 25 deletions(-) diff --git a/src/microstepper/microstepper_control.v b/src/microstepper/microstepper_control.v index 68e9c04..17e0576 100644 --- a/src/microstepper/microstepper_control.v +++ b/src/microstepper/microstepper_control.v @@ -16,7 +16,7 @@ module microstepper_control ( input s3, input s4, output offtimer_en0, - output offtimer_en0, + output offtimer_en1, output a_starting, output b_starting, output [7:0] phase_ct, @@ -82,7 +82,7 @@ module microstepper_control ( wire s4_starting = s4r == 2'b10; assign offtimer_en0 = analog_cmp1 & blank_timer0 == 0 & overCurrent0 == 0; - assign offtimer_en0 = analog_cmp2 & blank_timer1 == 0 & overCurrent1 == 0; + assign offtimer_en1 = analog_cmp2 & blank_timer1 == 0 & overCurrent1 == 0; assign a_starting = s1_starting | s2_starting; assign b_starting = s3_starting | s4_starting; @@ -102,4 +102,4 @@ module microstepper_control ( s4r <= {s4r[0], s4}; end -endmodule \ No newline at end of file +endmodule diff --git a/src/microstepper/microstepper_top.v b/src/microstepper/microstepper_top.v index f9df678..c6e92e5 100644 --- a/src/microstepper/microstepper_top.v +++ b/src/microstepper/microstepper_top.v @@ -27,6 +27,18 @@ module microstepper_top ( wire [5:0] cos_index2; wire [7:0] pwm1; wire [7:0] pwm2; + + wire s1, s2, s3, s4; + wire offtimer_en0, offtimer_en1; + + wire a_starting, b_starting; + wire [7:0] phase_ct; + wire [7:0] blank_timer0; + wire [7:0] blank_timer1; + wire [9:0] off_timer0; + wire [9:0] off_timer1; + wire [7:0] minimum_on_timer0; + wire [7:0] minimum_on_timer1; microstepper_control m_control_0( .clk(clk), @@ -46,7 +58,7 @@ module microstepper_top ( .s3(s3), .s4(s4), .offtimer_en0(offtimer_en0), - .offtimer_en0(offtimer_en0), + .offtimer_en1(offtimer_en1), .a_starting(a_starting), .b_starting(b_starting), .phase_ct(phase_ct), @@ -58,9 +70,7 @@ module microstepper_top ( .minimum_on_timer1(minimum_on_timer1), ); - mytimer_10 #( - .WIDTH(10) - ) offtimer0 ( + mytimer_10 offtimer0 ( .clk (clk), .resetn (resetn), .start_enable(offtimer_en0), @@ -68,9 +78,7 @@ module microstepper_top ( .timer (off_timer0) ); - mytimer_10 #( - .WIDTH(10) - ) offtimer1 ( + mytimer_10 offtimer1 ( .clk (clk), .resetn (resetn), .start_enable(offtimer_en1), @@ -78,9 +86,7 @@ module microstepper_top ( .timer (off_timer1) ); - mytimer_8 #( - .WIDTH(8) - ) blanktimer0 ( + mytimer_8 blanktimer0 ( .clk (clk), .resetn (resetn), .start_enable(a_starting), @@ -88,9 +94,7 @@ module microstepper_top ( .timer (blank_timer0) ); - mytimer_8 #( - .WIDTH(8) - ) blanktimer1 ( + mytimer_8 blanktimer1 ( .clk (clk), .resetn (resetn), .start_enable(b_starting), @@ -98,9 +102,7 @@ module microstepper_top ( .timer (blank_timer1) ); - mytimer_8 #( - .WIDTH(8) - ) minimumontimer0 ( + mytimer_8 minimumontimer0 ( .clk (clk), .resetn (resetn), .start_enable(a_starting), @@ -108,9 +110,7 @@ module microstepper_top ( .timer (minimum_on_timer0) ); - mytimer_8 #( - .WIDTH(8) - ) minimumontimer1 ( + mytimer_8 minimumontimer1 ( .clk (clk), .resetn (resetn), .start_enable(b_starting), diff --git a/src/microstepper/mytimer_10.v b/src/microstepper/mytimer_10.v index 93a73ad..5ce98e4 100644 --- a/src/microstepper/mytimer_10.v +++ b/src/microstepper/mytimer_10.v @@ -5,10 +5,17 @@ module mytimer_10 ( start_time, timer ); + localparam WIDTH = 10; + + input clk; + input resetn; + input start_enable; + input [WIDTH-1:0] start_time; + output [WIDTH-1:0] timer; mytimer #( - .WIDTH(8) - ) mytimer8 ( + .WIDTH(WIDTH) + ) mytimer10 ( .clk (clk), .resetn (resetn), .start_enable(start_enable), diff --git a/src/microstepper/mytimer_8.v b/src/microstepper/mytimer_8.v index c61be86..38f495d 100644 --- a/src/microstepper/mytimer_8.v +++ b/src/microstepper/mytimer_8.v @@ -5,9 +5,16 @@ module mytimer_8 ( start_time, timer ); + localparam WIDTH = 8; + + input clk; + input resetn; + input start_enable; + input [WIDTH-1:0] start_time; + output [WIDTH-1:0] timer; mytimer #( - .WIDTH(8) + .WIDTH(WIDTH) ) mytimer8 ( .clk (clk), .resetn (resetn), From 9fe4468d4ea2d7a25a1c82e74e714cf409f0b4d1 Mon Sep 17 00:00:00 2001 From: johnnyr Date: Fri, 4 Dec 2020 01:27:35 -0600 Subject: [PATCH 24/71] testbench upgrades. part 1 --- Makefile | 6 +- sim_microstepper.ys | 14 ++++ testbench/coil.v | 30 ++++++++ testbench/microstepper_tb.v | 133 ++++++++++++++++++++++++++++++++++++ testbench/pwm_duty.v | 40 +++++++++++ testbench/quad_tb.v | 2 +- 6 files changed, 223 insertions(+), 2 deletions(-) create mode 100644 sim_microstepper.ys create mode 100644 testbench/coil.v create mode 100644 testbench/microstepper_tb.v create mode 100644 testbench/pwm_duty.v diff --git a/Makefile b/Makefile index 2ddf69e..8e16d3e 100755 --- a/Makefile +++ b/Makefile @@ -57,8 +57,12 @@ formal: lint: verible-verilog-lint src/*.v -testbench: +testbench_quad_encoder: yosys sim.ys + gtkwave testbench/quad_enc.vcd +testbench_microstepper: + yosys sim_microstepper.ys + gtkwave testbench/microstepper.vcd .SECONDARY: .PHONY: all prog clean testbench formal diff --git a/sim_microstepper.ys b/sim_microstepper.ys new file mode 100644 index 0000000..3d86003 --- /dev/null +++ b/sim_microstepper.ys @@ -0,0 +1,14 @@ + +read_verilog -sv testbench/microstepper_tb.v \ + src/microstepper/analog_out.v \ + src/microstepper/chargepump.v \ + src/microstepper/cosine.v \ + src/microstepper/microstep_counter.v \ + src/microstepper/microstepper_control.v \ + src/microstepper/mytimer_8.v \ + src/microstepper/mytimer_10.v \ + src/microstepper/mytimer.v + +prep -top testbench +show microstepper_top +sim -n 40000 -clock clk -vcd testbench/microstepper.vcd diff --git a/testbench/coil.v b/testbench/coil.v new file mode 100644 index 0000000..3a2c1ce --- /dev/null +++ b/testbench/coil.v @@ -0,0 +1,30 @@ +// Linear current ramp +module coil ( + input clk, + input resetn, + input s_l1, + input s_h1, + input s_l2, + input s_h2, + output [12:0] current, +); + reg [12:0] current; + reg [7:0] cnt; + + wire on = (s_l1 && s_h2) | (s_l1 && s_h2); + + always @(posedge clk) begin + if (!resetn) begin + current <= 0; + end + else begin + if ( on ) begin + current <= current + 1; + end + else begin + current <= 0; + end + end + end +endmodule +//(cnt[2]== 1) \ No newline at end of file diff --git a/testbench/microstepper_tb.v b/testbench/microstepper_tb.v new file mode 100644 index 0000000..4c54dba --- /dev/null +++ b/testbench/microstepper_tb.v @@ -0,0 +1,133 @@ +`include "../src/microstepper/microstepper_top.v" +`include "coil.v" +`include "pwm_duty.v" +`timescale 1ns/100ps + +module testbench( + input clk, + output [3:0] s_l, + output [3:0] s_h, + output analog_cmp1, + output analog_out1, + output analog_cmp2, + output analog_out2, + output chargepump_pin, + output fault, + output [7:0] target_current1, +); + + reg step; + reg dir; + reg enable; + reg [7:0] target_current1; + reg [7:0] target_current2; + reg [7:0] current1; + reg [7:0] current2; + reg [9:0] config_offtime; + reg [7:0] config_blanktime; + reg [9:0] config_fastdecay_threshold; + reg [7:0] config_minimum_on_time; + reg [10:0] config_current_threshold; + reg [7:0] config_chargepump_period; + reg config_invert_highside; + reg config_invert_lowside; + + wire resetn; + reg [7:0] resetn_counter = 0; + + assign resetn = &resetn_counter; + always @(posedge clk) begin + if (!resetn) resetn_counter <= resetn_counter +1; + end + + reg analog_cmp1; + reg analog_cmp2; + reg [40:0] step_clock; + reg [20:0] cnt; + always @(posedge clk) begin + if (!resetn) begin + cnt <= 0; + analog_cmp1 <= 0; + analog_cmp2 <= 0; + step <= 1; + enable <= 1; + config_offtime = 810; + config_blanktime = 27; + config_fastdecay_threshold = 706; + config_minimum_on_time = 54; + config_current_threshold = 1024; + config_chargepump_period = 91; + config_invert_highside = 0; + config_invert_lowside = 0; + step_clock = 0; + end + else begin + cnt <= cnt + 1; + step_clock <= step_clock + 1; + step <= step_clock[9]; + if (current1 > target_current1) analog_cmp1 <= 1; + if (current2 > target_current2) analog_cmp2 <= 1; + if (cnt <= 20'hAEC) begin + dir <= 1; + end + else if (cnt <= 20'hEBE) begin + dir <= 0; + end + end + end + + microstepper_top stepper( + .resetn( resetn ), + .clk( clk ), + .fault( fault ), + .s_l( s_l ), + .s_h( s_h ), + .analog_cmp1( analog_cmp1 ), + .analog_out1( analog_out1 ), + .analog_cmp2( analog_cmp2 ), + .analog_out2( analog_out2 ), + .chargepump_pin( chargepump_pin ), + .step( step ), + .dir( dir ), + .enable( enable ), + .config_offtime( config_offtime ), + .config_blanktime( config_blanktime ), + .config_fastdecay_threshold( config_fastdecay_threshold ), + .config_minimum_on_time( config_minimum_on_time ), + .config_current_threshold( config_current_threshold ), + .config_chargepump_period( config_chargepump_period ), + .config_invert_highside( config_invert_highside ), + .config_invert_lowside( config_invert_lowside ), + ); + pwm_duty duty1( + .clk(clk), + .resetn(resetn), + .pwm(analog_out1), + .duty(target_current1) + ); + pwm_duty duty2( + .clk(clk), + .resetn(resetn), + .pwm(analog_out2), + .duty(target_current2) + ); + coil coil1( + .clk(clk), + .resetn(resetn), + .s_l1(s_l[0]), + .s_l2(s_l[1]), + .s_h1(s_h[0]), + .s_h2(s_h[1]), + .current(current1) + ); + coil coil2( + .clk(clk), + .resetn(resetn), + .s_l1(s_l[2]), + .s_l2(s_l[3]), + .s_h1(s_h[2]), + .s_h2(s_h[3]), + .current(current2) + ); +endmodule + diff --git a/testbench/pwm_duty.v b/testbench/pwm_duty.v new file mode 100644 index 0000000..ae8e245 --- /dev/null +++ b/testbench/pwm_duty.v @@ -0,0 +1,40 @@ +// Calculate PWM Duty - cycle by cycle +module pwm_duty( + input clk, + input pwm, + input resetn, + output [12:0] duty, + ); + reg [1:0] edge_b; + reg [11:0] cnt_h; + reg [11:0] cnt_l; + wire tc_edge = edge_b[1] ^ edge_b[0]; + wire pwm; + + reg [12:0] duty; + + always @(posedge clk) begin + if (!resetn) begin + cnt_h <= 0; + cnt_l <= 0; + duty <= 0; + end + else begin + if (tc_edge && edge_b[0]) begin // Rising edge + duty <= ( 255 * cnt_h / (cnt_h + cnt_l) ); + cnt_h <= 0; + cnt_l <= 0; + end + else begin + if (edge_b[1]) begin + cnt_h <= cnt_h + 1; + end + else if (!edge_b[1]) begin + cnt_l <= cnt_l + 1; + end + end + end + edge_b = {edge_b[0], pwm}; + end + +endmodule diff --git a/testbench/quad_tb.v b/testbench/quad_tb.v index 95f7eef..da85005 100644 --- a/testbench/quad_tb.v +++ b/testbench/quad_tb.v @@ -74,7 +74,7 @@ module testbench( end faultn <= &fault; cnt <= cnt + 1; - if (cnt <= 20'h90) begin + if (cnt <= 20'h85) begin enccntA <= enccntA + 1; enc1a <= enccntA[3]; enccntB <= enccntB - 1; From 99a5ae79b7ddb5622d4d1fc0a466b43e80d74ba1 Mon Sep 17 00:00:00 2001 From: johnnyr Date: Fri, 4 Dec 2020 01:35:29 -0600 Subject: [PATCH 25/71] reset logic for analog out, phase_ct, step dir buffer, instantiation name expansion. --- src/microstepper/analog_out.v | 18 +++++++++++------- src/microstepper/microstepper_control.v | 22 ++++++++++++++++++++-- src/microstepper/microstepper_top.v | 9 +++++---- 3 files changed, 36 insertions(+), 13 deletions(-) diff --git a/src/microstepper/analog_out.v b/src/microstepper/analog_out.v index 3494907..1b55c55 100644 --- a/src/microstepper/analog_out.v +++ b/src/microstepper/analog_out.v @@ -10,13 +10,17 @@ module analog_out ( reg [10:0] pwm_counter; - always @(posedge clk) - if (resetn) - if (pwm_counter <= current_threshold) - pwm_counter <= pwm_counter + 1'b1; - else - pwm_counter <= 0; - + always @(posedge clk) begin + if (!resetn) begin + pwm_counter <= 0; + end + else begin + if (pwm_counter <= current_threshold) + pwm_counter <= pwm_counter + 1'b1; + else + pwm_counter <= 0; + end + end assign analog_out1 = pwm_counter <= pwm1; assign analog_out2 = pwm_counter <= pwm2; diff --git a/src/microstepper/microstepper_control.v b/src/microstepper/microstepper_control.v index 17e0576..653fe34 100644 --- a/src/microstepper/microstepper_control.v +++ b/src/microstepper/microstepper_control.v @@ -1,5 +1,6 @@ module microstepper_control ( input clk, + input resetn, output [3:0] s_l, output [3:0] s_h, input [9:0] config_fastdecay_threshold, @@ -26,11 +27,28 @@ module microstepper_control ( input [9:0] off_timer1, input [7:0] minimum_on_timer0, input [7:0] minimum_on_timer1, +// output step_b_out, ); reg [7:0] phase_ct; +// reg [1:0] step_b; - always @(posedge step) begin - phase_ct <= phase_ct + (dir ? 1 : -1); +// wire step_edge = (step_b[2] ^ step_b[1]) && step_b[2]; + // step edge rising falling + + reg [2:0] step_b; + reg [1:0] dir_b; +// wire step_b_out = step_b[2]; + wire step_rising = (step_b == 2'b01); + + always @(posedge clk) begin + if (!resetn) begin + phase_ct <= 0; + end + else if (step_rising) begin + phase_ct <= phase_ct + dir_b[1]; + end + step_b <= {step_b[1:0], step}; + dir_b <= {dir[0], dir}; end wire s1; diff --git a/src/microstepper/microstepper_top.v b/src/microstepper/microstepper_top.v index c6e92e5..9ddcfb9 100644 --- a/src/microstepper/microstepper_top.v +++ b/src/microstepper/microstepper_top.v @@ -40,8 +40,9 @@ module microstepper_top ( wire [7:0] minimum_on_timer0; wire [7:0] minimum_on_timer1; - microstepper_control m_control_0( + microstepper_control microstepper_control0( .clk(clk), + .resetn(resetn), .s_l(s_l), .s_h(s_h), .config_fastdecay_threshold(config_fastdecay_threshold), @@ -118,14 +119,14 @@ module microstepper_top ( .timer (minimum_on_timer1) ); - chargepump cp0 ( + chargepump chargepump0 ( .clk (clk), .resetn (resetn), .period (config_chargepump_period), .chargepump_pin(chargepump_pin) ); - microstep_counter mc0 ( + microstep_counter microstep_counter0 ( .pos (phase_ct), .cos_index1(cos_index1), .cos_index2(cos_index2), @@ -144,7 +145,7 @@ module microstepper_top ( //.cos_table(cos_table) ); - analog_out ao0 ( + analog_out analog_out0 ( .clk (clk), .resetn (resetn), .pwm1 (pwm1), From d8fd6a530e12bf3a4e427645cff7fa4117b64a8a Mon Sep 17 00:00:00 2001 From: johnnyr Date: Fri, 4 Dec 2020 19:10:59 -0600 Subject: [PATCH 26/71] testbench debugging --- testbench/coil.v | 7 +++---- testbench/microstepper_tb.v | 24 +++++++++++++----------- testbench/pwm_duty.v | 6 +++--- 3 files changed, 19 insertions(+), 18 deletions(-) diff --git a/testbench/coil.v b/testbench/coil.v index 3a2c1ce..dd8c6fe 100644 --- a/testbench/coil.v +++ b/testbench/coil.v @@ -2,16 +2,15 @@ module coil ( input clk, input resetn, + input s_l0, + input s_h0, input s_l1, input s_h1, - input s_l2, - input s_h2, output [12:0] current, ); reg [12:0] current; - reg [7:0] cnt; - wire on = (s_l1 && s_h2) | (s_l1 && s_h2); + wire on = (s_l0 && s_h1) | (s_l1 && s_h0); always @(posedge clk) begin if (!resetn) begin diff --git a/testbench/microstepper_tb.v b/testbench/microstepper_tb.v index 4c54dba..231556d 100644 --- a/testbench/microstepper_tb.v +++ b/testbench/microstepper_tb.v @@ -64,9 +64,11 @@ module testbench( else begin cnt <= cnt + 1; step_clock <= step_clock + 1; - step <= step_clock[9]; + step <= step_clock[11]; if (current1 > target_current1) analog_cmp1 <= 1; + else analog_cmp1 <= 0; if (current2 > target_current2) analog_cmp2 <= 1; + else analog_cmp2 <= 0; if (cnt <= 20'hAEC) begin dir <= 1; end @@ -111,22 +113,22 @@ module testbench( .pwm(analog_out2), .duty(target_current2) ); - coil coil1( + coil coil2( .clk(clk), .resetn(resetn), - .s_l1(s_l[0]), - .s_l2(s_l[1]), - .s_h1(s_h[0]), - .s_h2(s_h[1]), + .s_l0(s_l[0]), + .s_l1(s_l[1]), + .s_h0(s_h[0]), + .s_h1(s_h[1]), .current(current1) ); - coil coil2( + coil coil1( .clk(clk), .resetn(resetn), - .s_l1(s_l[2]), - .s_l2(s_l[3]), - .s_h1(s_h[2]), - .s_h2(s_h[3]), + .s_l0(s_l[2]), + .s_l1(s_l[3]), + .s_h0(s_h[2]), + .s_h1(s_h[3]), .current(current2) ); endmodule diff --git a/testbench/pwm_duty.v b/testbench/pwm_duty.v index ae8e245..24d0289 100644 --- a/testbench/pwm_duty.v +++ b/testbench/pwm_duty.v @@ -8,7 +8,7 @@ module pwm_duty( reg [1:0] edge_b; reg [11:0] cnt_h; reg [11:0] cnt_l; - wire tc_edge = edge_b[1] ^ edge_b[0]; + wire s_edge = edge_b[1] ^ edge_b[0]; wire pwm; reg [12:0] duty; @@ -20,8 +20,8 @@ module pwm_duty( duty <= 0; end else begin - if (tc_edge && edge_b[0]) begin // Rising edge - duty <= ( 255 * cnt_h / (cnt_h + cnt_l) ); + if (s_edge && edge_b[0]) begin // Rising edge + duty <= 8191 * cnt_h / (cnt_h + cnt_l) ; cnt_h <= 0; cnt_l <= 0; end From 6f7d319ac7530c84b6426ce773d52d1d7db39d90 Mon Sep 17 00:00:00 2001 From: johnnyr Date: Fri, 4 Dec 2020 19:11:47 -0600 Subject: [PATCH 27/71] tb debug --- sim_microstepper.ys | 2 +- src/microstepper/microstepper_control.v | 17 ++++++++++++++--- src/rapcore.v | 4 ++-- 3 files changed, 17 insertions(+), 6 deletions(-) diff --git a/sim_microstepper.ys b/sim_microstepper.ys index 3d86003..dda1280 100644 --- a/sim_microstepper.ys +++ b/sim_microstepper.ys @@ -11,4 +11,4 @@ read_verilog -sv testbench/microstepper_tb.v \ prep -top testbench show microstepper_top -sim -n 40000 -clock clk -vcd testbench/microstepper.vcd +sim -n 400000 -clock clk -vcd testbench/microstepper.vcd diff --git a/src/microstepper/microstepper_control.v b/src/microstepper/microstepper_control.v index 653fe34..85d75f6 100644 --- a/src/microstepper/microstepper_control.v +++ b/src/microstepper/microstepper_control.v @@ -45,7 +45,7 @@ module microstepper_control ( phase_ct <= 0; end else if (step_rising) begin - phase_ct <= phase_ct + dir_b[1]; + phase_ct <= dir_b[1] ? phase_ct + 1 : phase_ct - 1; end step_b <= {step_b[1:0], step}; dir_b <= {dir[0], dir}; @@ -56,8 +56,9 @@ module microstepper_control ( wire s3; wire s4; + // Off Timer active flag wire overCurrent0 = off_timer0 > 0; - wire overCurrent1 = off_timer1 > 0; + wire overCurrent1 = off_timer1 > 0; wire fastDecay0 = off_timer0 >= config_fastdecay_threshold; wire fastDecay1 = off_timer1 >= config_fastdecay_threshold; @@ -73,11 +74,14 @@ module microstepper_control ( wire phase_a1_h, phase_a1_l, phase_a2_h, phase_a2_l; wire phase_b1_h, phase_b1_l, phase_b2_h, phase_b2_l; + // Switch output Low + assign s_l[0] = !(phase_a1_l | fault); assign s_l[1] = !(phase_a2_l | fault); assign s_l[2] = !(phase_b1_l | fault); assign s_l[3] = !(phase_b2_l | fault); + // Switch output High assign s_h[0] = !(phase_a1_h | fault); assign s_h[1] = !(phase_a2_h | fault); assign s_h[2] = !(phase_b1_h | fault); @@ -93,14 +97,19 @@ module microstepper_control ( assign phase_b2_h = config_invert_highside ^ (slowDecay1 | (fastDecay1 ? s4r[1] : ~s4r[1])); assign phase_b2_l = config_invert_lowside ^ (fastDecay1 ? ~s4r[1] : (slowDecay1 ? 1'b0 : s4r[1])); - + // Start on time per half bridge wire s1_starting = s1r == 2'b10; wire s2_starting = s2r == 2'b10; wire s3_starting = s3r == 2'b10; wire s4_starting = s4r == 2'b10; + // start Off Time + // Target peak current detected. Blank timer and Off timer not active assign offtimer_en0 = analog_cmp1 & blank_timer0 == 0 & overCurrent0 == 0; assign offtimer_en1 = analog_cmp2 & blank_timer1 == 0 & overCurrent1 == 0; + + // Bridge On Time start + // Blank timer and minimum on timer enable assign a_starting = s1_starting | s2_starting; assign b_starting = s3_starting | s4_starting; @@ -113,6 +122,8 @@ module microstepper_control ( end `endif + // Shift register buffer switch output + // Triger start on time always @(posedge clk) begin s1r <= {s1r[0], s1}; s2r <= {s2r[0], s2}; diff --git a/src/rapcore.v b/src/rapcore.v index 7e51a81..b881af8 100644 --- a/src/rapcore.v +++ b/src/rapcore.v @@ -115,8 +115,8 @@ module rapcore ( reg [7:0] config_minimum_on_time = 54; reg [10:0] config_current_threshold = 1024; reg [7:0] config_chargepump_period = 91; - reg config_invert_highside = 0; - reg config_invert_lowside = 0; + reg config_invert_highside = 1; + reg config_invert_lowside = 1; /* reg [511:0] cos_table; From fa73687b99ce21fa8f5b35ef22f89dd32f9a795a Mon Sep 17 00:00:00 2001 From: johnnyr Date: Fri, 4 Dec 2020 21:11:12 -0600 Subject: [PATCH 28/71] testbench with Jason and Steve round 3 --- testbench/coil.v | 6 +++++- testbench/microstepper_tb.v | 4 ++-- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/testbench/coil.v b/testbench/coil.v index dd8c6fe..72fc19f 100644 --- a/testbench/coil.v +++ b/testbench/coil.v @@ -7,10 +7,14 @@ module coil ( input s_l1, input s_h1, output [12:0] current, + output positive, + output negative, ); reg [12:0] current; - wire on = (s_l0 && s_h1) | (s_l1 && s_h0); + wire on = (!s_l0 && !s_h1) | (!s_l1 && !s_h0); + wire positive = (!s_l0 && !s_h1); + wire negative = (!s_l1 && !s_h0); always @(posedge clk) begin if (!resetn) begin diff --git a/testbench/microstepper_tb.v b/testbench/microstepper_tb.v index 231556d..6da7730 100644 --- a/testbench/microstepper_tb.v +++ b/testbench/microstepper_tb.v @@ -113,7 +113,7 @@ module testbench( .pwm(analog_out2), .duty(target_current2) ); - coil coil2( + coil coil1( .clk(clk), .resetn(resetn), .s_l0(s_l[0]), @@ -122,7 +122,7 @@ module testbench( .s_h1(s_h[1]), .current(current1) ); - coil coil1( + coil coil2( .clk(clk), .resetn(resetn), .s_l0(s_l[2]), From 6bc32cefb14babb6909bd3f75dd3051e7276a7d9 Mon Sep 17 00:00:00 2001 From: johnnyr Date: Fri, 4 Dec 2020 21:11:39 -0600 Subject: [PATCH 29/71] patches / hacks from testbench working session --- src/microstepper/microstepper_control.v | 44 +++++++++++++++-------- src/microstepper/microstepper_top.v | 12 ++++--- src/microstepper/mytimer.v | 30 +++++++++------- src/microstepper/mytimer_10.v | 47 ++++++++++++++----------- src/microstepper/mytimer_8.v | 47 ++++++++++++++----------- src/rapcore.v | 4 +-- 6 files changed, 110 insertions(+), 74 deletions(-) diff --git a/src/microstepper/microstepper_control.v b/src/microstepper/microstepper_control.v index 85d75f6..d040407 100644 --- a/src/microstepper/microstepper_control.v +++ b/src/microstepper/microstepper_control.v @@ -27,6 +27,8 @@ module microstepper_control ( input [9:0] off_timer1, input [7:0] minimum_on_timer0, input [7:0] minimum_on_timer1, +// input off_timer0_done, +// input off_timer1_done, // output step_b_out, ); reg [7:0] phase_ct; @@ -56,18 +58,18 @@ module microstepper_control ( wire s3; wire s4; - // Off Timer active flag - wire overCurrent0 = off_timer0 > 0; - wire overCurrent1 = off_timer1 > 0; + // Off Timer active flag + wire off_timer_active0 = off_timer0 > 0; + wire off_timer_active1 = off_timer1 > 0; wire fastDecay0 = off_timer0 >= config_fastdecay_threshold; wire fastDecay1 = off_timer1 >= config_fastdecay_threshold; - wire slowDecay0 = overCurrent0 && fastDecay0 == 0; - wire slowDecay1 = overCurrent1 && fastDecay1 == 0; + wire slowDecay0 = off_timer_active0 && fastDecay0 == 0; + wire slowDecay1 = off_timer_active1 && fastDecay1 == 0; - wire fault0 = (minimum_on_timer0 > 0) && overCurrent0; - wire fault1 = (minimum_on_timer1 > 0) && overCurrent1; + wire fault0 = (minimum_on_timer0 > 0) && off_timer_active0; + wire fault1 = (minimum_on_timer1 > 0) && off_timer_active1; wire fault = fault0 | fault1; reg [1:0] s1r, s2r, s3r, s4r; @@ -75,7 +77,6 @@ module microstepper_control ( wire phase_b1_h, phase_b1_l, phase_b2_h, phase_b2_l; // Switch output Low - assign s_l[0] = !(phase_a1_l | fault); assign s_l[1] = !(phase_a2_l | fault); assign s_l[2] = !(phase_b1_l | fault); @@ -98,20 +99,21 @@ module microstepper_control ( assign phase_b2_l = config_invert_lowside ^ (fastDecay1 ? ~s4r[1] : (slowDecay1 ? 1'b0 : s4r[1])); // Start on time per half bridge + // todo concatanate config inverting for active high or low wire s1_starting = s1r == 2'b10; wire s2_starting = s2r == 2'b10; wire s3_starting = s3r == 2'b10; wire s4_starting = s4r == 2'b10; - // start Off Time - // Target peak current detected. Blank timer and Off timer not active - assign offtimer_en0 = analog_cmp1 & blank_timer0 == 0 & overCurrent0 == 0; - assign offtimer_en1 = analog_cmp2 & blank_timer1 == 0 & overCurrent1 == 0; - // Bridge On Time start // Blank timer and minimum on timer enable - assign a_starting = s1_starting | s2_starting; - assign b_starting = s3_starting | s4_starting; + //assign a_starting = s1_starting | s2_starting; + //assign b_starting = s3_starting | s4_starting; + + // start Off Time + // Target peak current detected. Blank timer and Off timer not active + assign offtimer_en0 = analog_cmp1 & blank_timer0 == 0 & off_timer_active0 == 0; + assign offtimer_en1 = analog_cmp2 & blank_timer1 == 0 & off_timer_active1 == 0; `ifdef FORMAL always @(*) begin @@ -130,5 +132,17 @@ module microstepper_control ( s3r <= {s3r[0], s3}; s4r <= {s4r[0], s4}; end +// +// wire [1:0] off_time_b; +// reg a_starting; +// reg b_starting; + +// always @(posedge clk) begin + //start on time +// if +// a_starting <= ~off_timer0; +// b_starting <= ~off_timer1; + +// end endmodule diff --git a/src/microstepper/microstepper_top.v b/src/microstepper/microstepper_top.v index 9ddcfb9..cd43862 100644 --- a/src/microstepper/microstepper_top.v +++ b/src/microstepper/microstepper_top.v @@ -69,6 +69,8 @@ module microstepper_top ( .off_timer1(off_timer1), .minimum_on_timer0(minimum_on_timer0), .minimum_on_timer1(minimum_on_timer1), +// .off_timer0_done (off_timer0_done), +// .off_timer0_done (off_timer1_done), ); mytimer_10 offtimer0 ( @@ -76,7 +78,8 @@ module microstepper_top ( .resetn (resetn), .start_enable(offtimer_en0), .start_time (config_offtime), - .timer (off_timer0) + .timer (off_timer0), + .done (off_timer0_done) ); mytimer_10 offtimer1 ( @@ -84,13 +87,14 @@ module microstepper_top ( .resetn (resetn), .start_enable(offtimer_en1), .start_time (config_offtime), - .timer (off_timer1) + .timer (off_timer1), + .done (off_timer1_done) ); mytimer_8 blanktimer0 ( .clk (clk), .resetn (resetn), - .start_enable(a_starting), + .start_enable(off_timer0_done), .start_time (config_blanktime), .timer (blank_timer0) ); @@ -98,7 +102,7 @@ module microstepper_top ( mytimer_8 blanktimer1 ( .clk (clk), .resetn (resetn), - .start_enable(b_starting), + .start_enable(off_timer1_done), .start_time (config_blanktime), .timer (blank_timer1) ); diff --git a/src/microstepper/mytimer.v b/src/microstepper/mytimer.v index dd87b02..4c11f73 100644 --- a/src/microstepper/mytimer.v +++ b/src/microstepper/mytimer.v @@ -1,29 +1,33 @@ module mytimer ( - clk, - resetn, - start_enable, - start_time, - timer + input clk, + input resetn, + input start_enable, + input [WIDTH-1:0] start_time, + output [WIDTH-1:0] timer, + output done // single cycle timer done event ); parameter WIDTH = 10; - input clk; - input resetn; - input start_enable; - input [WIDTH-1:0] start_time; - output [WIDTH-1:0] timer; - + reg done = 0; reg [WIDTH-1:0] counter; - + reg run = 1; assign timer = counter; always @(posedge clk) begin if (!resetn) counter <= 0; - else if( start_enable ) + else if( start_enable ) begin counter <= start_time; + run <= 1; + end else if( counter > 0 ) counter <= counter - 1'b1; + else if (run) + done <= 1; + if (done) begin + run <= 0; + done <= 0; + end end endmodule diff --git a/src/microstepper/mytimer_10.v b/src/microstepper/mytimer_10.v index 5ce98e4..d8c94a1 100644 --- a/src/microstepper/mytimer_10.v +++ b/src/microstepper/mytimer_10.v @@ -1,26 +1,33 @@ module mytimer_10 ( - clk, - resetn, - start_enable, - start_time, - timer + input clk, + input resetn, + input start_enable, + input [WIDTH-1:0] start_time, + output [WIDTH-1:0] timer, + output done // single cycle timer done event ); - localparam WIDTH = 10; + parameter WIDTH = 10; - input clk; - input resetn; - input start_enable; - input [WIDTH-1:0] start_time; - output [WIDTH-1:0] timer; + reg done = 0; + reg [WIDTH-1:0] counter; + reg run = 1; + assign timer = counter; - mytimer #( - .WIDTH(WIDTH) - ) mytimer10 ( - .clk (clk), - .resetn (resetn), - .start_enable(start_enable), - .start_time (start_time), - .timer (timer) - ); + always @(posedge clk) begin + if (!resetn) + counter <= 0; + else if( start_enable ) begin + counter <= start_time; + run <= 1; + end + else if( counter > 0 ) + counter <= counter - 1'b1; + else if (run) + done <= 1; + if (done) begin + run <= 0; + done <= 0; + end +end endmodule diff --git a/src/microstepper/mytimer_8.v b/src/microstepper/mytimer_8.v index 38f495d..5519e6b 100644 --- a/src/microstepper/mytimer_8.v +++ b/src/microstepper/mytimer_8.v @@ -1,26 +1,33 @@ module mytimer_8 ( - clk, - resetn, - start_enable, - start_time, - timer + input clk, + input resetn, + input start_enable, + input [WIDTH-1:0] start_time, + output [WIDTH-1:0] timer, + output done // single cycle timer done event ); - localparam WIDTH = 8; + parameter WIDTH = 8; - input clk; - input resetn; - input start_enable; - input [WIDTH-1:0] start_time; - output [WIDTH-1:0] timer; + reg done = 0; + reg [WIDTH-1:0] counter; + reg run = 1; + assign timer = counter; - mytimer #( - .WIDTH(WIDTH) - ) mytimer8 ( - .clk (clk), - .resetn (resetn), - .start_enable(start_enable), - .start_time (start_time), - .timer (timer) - ); + always @(posedge clk) begin + if (!resetn) + counter <= 0; + else if( start_enable ) begin + counter <= start_time; + run <= 1; + end + else if( counter > 0 ) + counter <= counter - 1'b1; + else if (run) + done <= 1; + if (done) begin + run <= 0; + done <= 0; + end +end endmodule diff --git a/src/rapcore.v b/src/rapcore.v index b881af8..7e51a81 100644 --- a/src/rapcore.v +++ b/src/rapcore.v @@ -115,8 +115,8 @@ module rapcore ( reg [7:0] config_minimum_on_time = 54; reg [10:0] config_current_threshold = 1024; reg [7:0] config_chargepump_period = 91; - reg config_invert_highside = 1; - reg config_invert_lowside = 1; + reg config_invert_highside = 0; + reg config_invert_lowside = 0; /* reg [511:0] cos_table; From 7de2ff7d97ad9a26de1db43eb375504587e4b26d Mon Sep 17 00:00:00 2001 From: johnnyr Date: Sat, 5 Dec 2020 00:14:50 -0600 Subject: [PATCH 30/71] more test bench patches --- testbench/coil.v | 6 ++++++ testbench/microstepper_tb.v | 10 +++++----- 2 files changed, 11 insertions(+), 5 deletions(-) diff --git a/testbench/coil.v b/testbench/coil.v index 72fc19f..54742dc 100644 --- a/testbench/coil.v +++ b/testbench/coil.v @@ -12,6 +12,12 @@ module coil ( ); reg [12:0] current; + // For each coil of motor + // Each coil is driven by s_x1 and s_x2 + // One side s_x1 or s_x2 must be high when the other is low to be on +// wire phase_a_positive = !s_l0 && !s_h1; +// wire phase_a_negative = !s_l1 && !s_h0; +// wire off = s_l0; wire on = (!s_l0 && !s_h1) | (!s_l1 && !s_h0); wire positive = (!s_l0 && !s_h1); wire negative = (!s_l1 && !s_h0); diff --git a/testbench/microstepper_tb.v b/testbench/microstepper_tb.v index 6da7730..a08c485 100644 --- a/testbench/microstepper_tb.v +++ b/testbench/microstepper_tb.v @@ -13,16 +13,16 @@ module testbench( output analog_out2, output chargepump_pin, output fault, - output [7:0] target_current1, + output [12:0] target_current1, ); reg step; reg dir; reg enable; - reg [7:0] target_current1; - reg [7:0] target_current2; - reg [7:0] current1; - reg [7:0] current2; + reg [12:0] target_current1; + reg [12:0] target_current2; + reg [12:0] current1; + reg [12:0] current2; reg [9:0] config_offtime; reg [7:0] config_blanktime; reg [9:0] config_fastdecay_threshold; From 515cd5c9d1e135ffa6c1b7b9286579bee57a3055 Mon Sep 17 00:00:00 2001 From: johnnyr Date: Sat, 5 Dec 2020 00:15:44 -0600 Subject: [PATCH 31/71] Comments and microstepper refactor from testbench party with Steve and Jason --- src/microstepper/microstepper_control.v | 102 +++++++++++------------- 1 file changed, 46 insertions(+), 56 deletions(-) diff --git a/src/microstepper/microstepper_control.v b/src/microstepper/microstepper_control.v index d040407..7249925 100644 --- a/src/microstepper/microstepper_control.v +++ b/src/microstepper/microstepper_control.v @@ -62,11 +62,6 @@ module microstepper_control ( wire off_timer_active0 = off_timer0 > 0; wire off_timer_active1 = off_timer1 > 0; - wire fastDecay0 = off_timer0 >= config_fastdecay_threshold; - wire fastDecay1 = off_timer1 >= config_fastdecay_threshold; - - wire slowDecay0 = off_timer_active0 && fastDecay0 == 0; - wire slowDecay1 = off_timer_active1 && fastDecay1 == 0; wire fault0 = (minimum_on_timer0 > 0) && off_timer_active0; wire fault1 = (minimum_on_timer1 > 0) && off_timer_active1; @@ -77,38 +72,54 @@ module microstepper_control ( wire phase_b1_h, phase_b1_l, phase_b2_h, phase_b2_l; // Switch output Low - assign s_l[0] = !(phase_a1_l | fault); - assign s_l[1] = !(phase_a2_l | fault); - assign s_l[2] = !(phase_b1_l | fault); - assign s_l[3] = !(phase_b2_l | fault); + assign s_l[0] = config_invert_lowside ^ (phase_a1_l | fault); + assign s_l[1] = config_invert_lowside ^ (phase_a2_l | fault); + assign s_l[2] = config_invert_lowside ^ (phase_b1_l | fault); + assign s_l[3] = config_invert_lowside ^ (phase_b2_l | fault); // Switch output High - assign s_h[0] = !(phase_a1_h | fault); - assign s_h[1] = !(phase_a2_h | fault); - assign s_h[2] = !(phase_b1_h | fault); - assign s_h[3] = !(phase_b2_h | fault); - - assign phase_a1_h = config_invert_highside ^ (slowDecay0 | (fastDecay0 ? s1r[1] : ~s1r[1])); - assign phase_a1_l = config_invert_lowside ^ (fastDecay0 ? ~s1r[1] : (slowDecay0 ? 1'b0 : s1r[1])); - assign phase_a2_h = config_invert_highside ^ (slowDecay0 | (fastDecay0 ? s2r[1] : ~s2r[1])); - assign phase_a2_l = config_invert_lowside ^ (fastDecay0 ? ~s2r[1] : (slowDecay0 ? 1'b0 : s2r[1])); - - assign phase_b1_h = config_invert_highside ^ (slowDecay1 | (fastDecay1 ? s3r[1] : ~s3r[1])); - assign phase_b1_l = config_invert_lowside ^ (fastDecay1 ? ~s3r[1] : (slowDecay1 ? 1'b0 : s3r[1])); - assign phase_b2_h = config_invert_highside ^ (slowDecay1 | (fastDecay1 ? s4r[1] : ~s4r[1])); - assign phase_b2_l = config_invert_lowside ^ (fastDecay1 ? ~s4r[1] : (slowDecay1 ? 1'b0 : s4r[1])); - - // Start on time per half bridge - // todo concatanate config inverting for active high or low - wire s1_starting = s1r == 2'b10; - wire s2_starting = s2r == 2'b10; - wire s3_starting = s3r == 2'b10; - wire s4_starting = s4r == 2'b10; - - // Bridge On Time start - // Blank timer and minimum on timer enable - //assign a_starting = s1_starting | s2_starting; - //assign b_starting = s3_starting | s4_starting; + assign s_h[0] = config_invert_highside ^ (phase_a1_h | fault); + assign s_h[1] = config_invert_highside ^ (phase_a2_h | fault); + assign s_h[2] = config_invert_highside ^ (phase_b1_h | fault); + assign s_h[3] = config_invert_highside ^ (phase_b2_h | fault); + + // Fast decay is first x ticks of off time + // default fast decay = 706 + wire fastDecay0 = off_timer0 >= config_fastdecay_threshold; + wire fastDecay1 = off_timer1 >= config_fastdecay_threshold; + + // Slow decay remainder of off time + wire slowDecay0 = off_timer_active0 && fastDecay0 == 0; + wire slowDecay1 = off_timer_active1 && fastDecay1 == 0; + + // This portion of code sets up output to drive mosfets. Output ON = 0 + + // High side output logic + // If in slow decay =1 + // OR + // ( fast decay and commanded to be OFF ) = 1 + // Then OFF + // Else If Not slow decay (Never in slow decay at same time as fast decay) + // OR + // ( not fast decay ) + // Then + // Follow commanded output + // Else if fast decay + // invert commanded polarity + assign phase_a1_h = slowDecay0 | ( fastDecay0 ? s1 : ~s1 ); + // Low side output logic + // low side output (invert if configured with XOR) + // Invert signal if fast decay commands. + // if slow decay the output is low. Else output = as commanded by microstep counter + assign phase_a1_l = fastDecay0 ? ~s1 : ( slowDecay0 ? 1'b0 : s1 ); + assign phase_a2_h = slowDecay0 | ( fastDecay0 ? s2 : ~s2 ); + assign phase_a2_l = fastDecay0 ? ~s2 : ( slowDecay0 ? 1'b0 : s2 ); + assign phase_b1_h = slowDecay1 | ( fastDecay1 ? s3 : ~s3 ); + assign phase_b1_l = fastDecay1 ? ~s3 : ( slowDecay1 ? 1'b0 : s3 ); + assign phase_b2_h = slowDecay1 | ( fastDecay1 ? s4 : ~s4 ); + assign phase_b2_l = fastDecay1 ? ~s4 : ( slowDecay1 ? 1'b0 : s4 ); + + // NEED DEAD TIME // start Off Time // Target peak current detected. Blank timer and Off timer not active @@ -124,25 +135,4 @@ module microstepper_control ( end `endif - // Shift register buffer switch output - // Triger start on time - always @(posedge clk) begin - s1r <= {s1r[0], s1}; - s2r <= {s2r[0], s2}; - s3r <= {s3r[0], s3}; - s4r <= {s4r[0], s4}; - end -// -// wire [1:0] off_time_b; -// reg a_starting; -// reg b_starting; - -// always @(posedge clk) begin - //start on time -// if -// a_starting <= ~off_timer0; -// b_starting <= ~off_timer1; - -// end - endmodule From febe72deea707e9af48dec8d11953b8a401c1ed8 Mon Sep 17 00:00:00 2001 From: johnnyr Date: Sun, 6 Dec 2020 16:38:46 -0600 Subject: [PATCH 32/71] default output active high, slow decay on low side, improve testbench motor model --- sim_microstepper.tcl | 8 +++ sim_microstepper.ys | 2 +- src/microstepper/microstepper_control.v | 19 +++---- testbench/coil.v | 39 ------------- testbench/hbridge_coil.v | 57 +++++++++++++++++++ testbench/microstepper_tb.v | 76 +++++++++++++------------ 6 files changed, 116 insertions(+), 85 deletions(-) create mode 100644 sim_microstepper.tcl delete mode 100644 testbench/coil.v create mode 100644 testbench/hbridge_coil.v diff --git a/sim_microstepper.tcl b/sim_microstepper.tcl new file mode 100644 index 0000000..85bfc4d --- /dev/null +++ b/sim_microstepper.tcl @@ -0,0 +1,8 @@ +yosys -import + +set + +read_verilog -sv testbench/microstepper_tb.v src/microstepper/*.v +prep -top testbench +show m_control_0 +sim -n 4000 -clock clk -vcd testbench/microstepper.vcd diff --git a/sim_microstepper.ys b/sim_microstepper.ys index dda1280..fe0fbff 100644 --- a/sim_microstepper.ys +++ b/sim_microstepper.ys @@ -11,4 +11,4 @@ read_verilog -sv testbench/microstepper_tb.v \ prep -top testbench show microstepper_top -sim -n 400000 -clock clk -vcd testbench/microstepper.vcd +sim -n 4000 -clock clk -vcd testbench/microstepper.vcd diff --git a/src/microstepper/microstepper_control.v b/src/microstepper/microstepper_control.v index 7249925..94d8576 100644 --- a/src/microstepper/microstepper_control.v +++ b/src/microstepper/microstepper_control.v @@ -53,6 +53,7 @@ module microstepper_control ( dir_b <= {dir[0], dir}; end + // Switch outputs wire s1; wire s2; wire s3; @@ -67,7 +68,7 @@ module microstepper_control ( wire fault1 = (minimum_on_timer1 > 0) && off_timer_active1; wire fault = fault0 | fault1; - reg [1:0] s1r, s2r, s3r, s4r; + reg [1:0] s1r, s2r, s3r, s4r; // Switch output history [ previous : now ] wire phase_a1_h, phase_a1_l, phase_a2_h, phase_a2_l; wire phase_b1_h, phase_b1_l, phase_b2_h, phase_b2_l; @@ -95,22 +96,20 @@ module microstepper_control ( // This portion of code sets up output to drive mosfets. Output ON = 0 // High side output logic - // If in slow decay =1 - // OR - // ( fast decay and commanded to be OFF ) = 1 + // If in slow decay = 1 + // OR ( fast decay and commanded to be OFF ) = 1 // Then OFF // Else If Not slow decay (Never in slow decay at same time as fast decay) - // OR - // ( not fast decay ) - // Then - // Follow commanded output + // OR ( not fast decay ) + // Then Follow commanded output // Else if fast decay // invert commanded polarity assign phase_a1_h = slowDecay0 | ( fastDecay0 ? s1 : ~s1 ); // Low side output logic // low side output (invert if configured with XOR) // Invert signal if fast decay commands. - // if slow decay the output is low. Else output = as commanded by microstep counter + // If slow decay Then the output is low. + // Else output = as commanded by microstep counter assign phase_a1_l = fastDecay0 ? ~s1 : ( slowDecay0 ? 1'b0 : s1 ); assign phase_a2_h = slowDecay0 | ( fastDecay0 ? s2 : ~s2 ); assign phase_a2_l = fastDecay0 ? ~s2 : ( slowDecay0 ? 1'b0 : s2 ); @@ -121,7 +120,7 @@ module microstepper_control ( // NEED DEAD TIME - // start Off Time + // Start Off Time // Target peak current detected. Blank timer and Off timer not active assign offtimer_en0 = analog_cmp1 & blank_timer0 == 0 & off_timer_active0 == 0; assign offtimer_en1 = analog_cmp2 & blank_timer1 == 0 & off_timer_active1 == 0; diff --git a/testbench/coil.v b/testbench/coil.v deleted file mode 100644 index 54742dc..0000000 --- a/testbench/coil.v +++ /dev/null @@ -1,39 +0,0 @@ -// Linear current ramp -module coil ( - input clk, - input resetn, - input s_l0, - input s_h0, - input s_l1, - input s_h1, - output [12:0] current, - output positive, - output negative, -); - reg [12:0] current; - - // For each coil of motor - // Each coil is driven by s_x1 and s_x2 - // One side s_x1 or s_x2 must be high when the other is low to be on -// wire phase_a_positive = !s_l0 && !s_h1; -// wire phase_a_negative = !s_l1 && !s_h0; -// wire off = s_l0; - wire on = (!s_l0 && !s_h1) | (!s_l1 && !s_h0); - wire positive = (!s_l0 && !s_h1); - wire negative = (!s_l1 && !s_h0); - - always @(posedge clk) begin - if (!resetn) begin - current <= 0; - end - else begin - if ( on ) begin - current <= current + 1; - end - else begin - current <= 0; - end - end - end -endmodule -//(cnt[2]== 1) \ No newline at end of file diff --git a/testbench/hbridge_coil.v b/testbench/hbridge_coil.v new file mode 100644 index 0000000..e37462b --- /dev/null +++ b/testbench/hbridge_coil.v @@ -0,0 +1,57 @@ +// Built to work in one polarity +module hbridge_coil ( + input clk, + input resetn, + input low_1, + input high_1, + input low_2, + input high_2, + output signed [12:0] current, +); + reg signed [12:0] current; + reg polarity; // arbitrary polarity + reg on; + reg [8:0] cnt; + reg alive; + reg slow_decay; + reg signed [2:0] current_ramp_cnt; // rates are delay counter sizes + reg signed [3:0] slow_decay_cnt; + reg signed [1:0] fast_decay_cnt; + reg open; // coils not connected. Should never occur? + // For each coil of motor + // Each coil is driven by 2 half bridges. _1 and _2 + // Each half bridge is driven by two drivers. high_ and low_ + // Current goes in one direction when low_0 is on and high_1 is on. + // Current goes the opposite direction when high_0 is on and low_1 is on. + // set state of on for next tick +// wire phase_negative = low_1 && high_0; + always @(posedge clk) begin + if (!resetn) begin + current <= 0; + on <= 0; + polarity <= 0; + cnt <= 0; + current_ramp_cnt <= 0; + slow_decay_cnt <= 0; + fast_decay_cnt <= 0; + end + else begin + cnt <= cnt + 1; + current_ramp_cnt <= current_ramp_cnt + 1; + slow_decay_cnt <= slow_decay_cnt + 1; + fast_decay_cnt <= fast_decay_cnt + 1; + on <= ( low_1 && high_2 ) | ( low_2 && high_1 ); + polarity <= high_2 && low_1; + slow_decay <= ( low_1 && low_2 ) | ( high_1 && high_2 ); + if ( on ) begin + if ( polarity && !current_ramp_cnt ) + current <= current + 1; + else if ( !polarity && current && !fast_decay_cnt ) + current <= current - 1; + end + else if ( slow_decay && current && !slow_decay_cnt ) + current <= current - 1; // slow decay every 4th tick + end + end +endmodule +//(cnt[2]== 1) \ No newline at end of file diff --git a/testbench/microstepper_tb.v b/testbench/microstepper_tb.v index a08c485..7869484 100644 --- a/testbench/microstepper_tb.v +++ b/testbench/microstepper_tb.v @@ -1,5 +1,5 @@ `include "../src/microstepper/microstepper_top.v" -`include "coil.v" +`include "hbridge_coil.v" `include "pwm_duty.v" `timescale 1ns/100ps @@ -12,25 +12,24 @@ module testbench( output analog_cmp2, output analog_out2, output chargepump_pin, - output fault, - output [12:0] target_current1, + output faultn, ); - reg step; - reg dir; - reg enable; - reg [12:0] target_current1; - reg [12:0] target_current2; - reg [12:0] current1; - reg [12:0] current2; - reg [9:0] config_offtime; - reg [7:0] config_blanktime; - reg [9:0] config_fastdecay_threshold; - reg [7:0] config_minimum_on_time; - reg [10:0] config_current_threshold; - reg [7:0] config_chargepump_period; - reg config_invert_highside; - reg config_invert_lowside; + reg step; + reg dir; + reg enable; + reg [12:0] target_current1; + reg [12:0] target_current2; + reg signed [12:0] current1; + reg signed [12:0] current2; + reg [9:0] config_offtime; + reg [7:0] config_blanktime; + reg [9:0] config_fastdecay_threshold; + reg [7:0] config_minimum_on_time; + reg [10:0] config_current_threshold; + reg [7:0] config_chargepump_period; + reg config_invert_highside; + reg config_invert_lowside; wire resetn; reg [7:0] resetn_counter = 0; @@ -50,7 +49,7 @@ module testbench( analog_cmp1 <= 0; analog_cmp2 <= 0; step <= 1; - enable <= 1; + enable_in <= 1; config_offtime = 810; config_blanktime = 27; config_fastdecay_threshold = 706; @@ -63,11 +62,12 @@ module testbench( end else begin cnt <= cnt + 1; + enable_in <= 1; step_clock <= step_clock + 1; step <= step_clock[11]; - if (current1 > target_current1) analog_cmp1 <= 1; + if (current1[12:0] > target_current1) analog_cmp1 <= 1; // compare unsigned else analog_cmp1 <= 0; - if (current2 > target_current2) analog_cmp2 <= 1; + if (current2[12:0] > target_current2) analog_cmp2 <= 1; else analog_cmp2 <= 0; if (cnt <= 20'hAEC) begin dir <= 1; @@ -81,9 +81,15 @@ module testbench( microstepper_top stepper( .resetn( resetn ), .clk( clk ), - .fault( fault ), - .s_l( s_l ), - .s_h( s_h ), + .faultn( faultn ), + .phase_a1_l( phase_a1_l ), + .phase_a2_l( phase_a2_l ), + .phase_b1_l( phase_b1_l ), + .phase_b2_l( phase_b2_l ), + .phase_a1_h( phase_a1_h ), + .phase_a2_h( phase_a2_h ), + .phase_b1_h( phase_b1_h ), + .phase_b2_h( phase_b2_h ), .analog_cmp1( analog_cmp1 ), .analog_out1( analog_out1 ), .analog_cmp2( analog_cmp2 ), @@ -91,7 +97,7 @@ module testbench( .chargepump_pin( chargepump_pin ), .step( step ), .dir( dir ), - .enable( enable ), + .enable_in( enable_in ), .config_offtime( config_offtime ), .config_blanktime( config_blanktime ), .config_fastdecay_threshold( config_fastdecay_threshold ), @@ -113,22 +119,22 @@ module testbench( .pwm(analog_out2), .duty(target_current2) ); - coil coil1( + hbridge_coil hbridge_coil1( .clk(clk), .resetn(resetn), - .s_l0(s_l[0]), - .s_l1(s_l[1]), - .s_h0(s_h[0]), - .s_h1(s_h[1]), + .low_1(phase_a1_l), + .high_1(phase_a1_h), + .low_2(phase_a2_l), + .high_2(phase_a2_h), .current(current1) ); - coil coil2( + hbridge_coil hbridge_coil2( .clk(clk), .resetn(resetn), - .s_l0(s_l[2]), - .s_l1(s_l[3]), - .s_h0(s_h[2]), - .s_h1(s_h[3]), + .low_1(phase_b1_l), + .high_1(phase_b1_h), + .low_2(phase_b2_l), + .high_2(phase_b2_h), .current(current2) ); endmodule From 2bc8779b243a46685908f8fdde08199690078b59 Mon Sep 17 00:00:00 2001 From: johnnyr Date: Sun, 6 Dec 2020 21:01:10 -0600 Subject: [PATCH 33/71] debug microstepper test bench. --- sim_microstepper.tcl | 2 +- sim_microstepper.ys | 2 +- src/microstepper/microstepper_control.v | 151 +++++++++++++----------- src/microstepper/microstepper_top.v | 40 ++++--- src/microstepper/mytimer_10.v | 4 +- src/rapcore.v | 10 +- testbench/hbridge_coil.v | 28 +++-- testbench/microstepper_tb.v | 44 ++++--- 8 files changed, 170 insertions(+), 111 deletions(-) diff --git a/sim_microstepper.tcl b/sim_microstepper.tcl index 85bfc4d..a3713ee 100644 --- a/sim_microstepper.tcl +++ b/sim_microstepper.tcl @@ -5,4 +5,4 @@ set read_verilog -sv testbench/microstepper_tb.v src/microstepper/*.v prep -top testbench show m_control_0 -sim -n 4000 -clock clk -vcd testbench/microstepper.vcd +sim -n 40000 -clock clk -vcd testbench/microstepper.vcd diff --git a/sim_microstepper.ys b/sim_microstepper.ys index fe0fbff..dda1280 100644 --- a/sim_microstepper.ys +++ b/sim_microstepper.ys @@ -11,4 +11,4 @@ read_verilog -sv testbench/microstepper_tb.v \ prep -top testbench show microstepper_top -sim -n 4000 -clock clk -vcd testbench/microstepper.vcd +sim -n 400000 -clock clk -vcd testbench/microstepper.vcd diff --git a/src/microstepper/microstepper_control.v b/src/microstepper/microstepper_control.v index 94d8576..cba55af 100644 --- a/src/microstepper/microstepper_control.v +++ b/src/microstepper/microstepper_control.v @@ -1,25 +1,29 @@ module microstepper_control ( input clk, input resetn, - output [3:0] s_l, - output [3:0] s_h, + output phase_a1_l_out, + output phase_a2_l_out, + output phase_b1_l_out, + output phase_b2_l_out, + output phase_a1_h_out, + output phase_a2_h_out, + output phase_b1_h_out, + output phase_b2_h_out, input [9:0] config_fastdecay_threshold, input config_invert_highside, input config_invert_lowside, input step, input dir, - input enable, + input enable_in, input analog_cmp1, input analog_cmp2, - output fault, + output faultn, input s1, input s2, input s3, input s4, output offtimer_en0, output offtimer_en1, - output a_starting, - output b_starting, output [7:0] phase_ct, input [7:0] blank_timer0, input [7:0] blank_timer1, @@ -27,103 +31,110 @@ module microstepper_control ( input [9:0] off_timer1, input [7:0] minimum_on_timer0, input [7:0] minimum_on_timer1, -// input off_timer0_done, -// input off_timer1_done, -// output step_b_out, +// input mixed_decay_enable, ); reg [7:0] phase_ct; -// reg [1:0] step_b; - -// wire step_edge = (step_b[2] ^ step_b[1]) && step_b[2]; - // step edge rising falling + reg [2:0] step_r; + reg [1:0] dir_r; + + reg enable; + + always @(posedge clk) begin + if (!resetn) + enable <= 0; + else + enable <= enable_in; + step_r <= {step_r[1:0], step}; + dir_r <= {dir_r[0], dir}; + end - reg [2:0] step_b; - reg [1:0] dir_b; -// wire step_b_out = step_b[2]; - wire step_rising = (step_b == 2'b01); + wire step_rising = (step_r == 2'b01); always @(posedge clk) begin if (!resetn) begin phase_ct <= 0; end - else if (step_rising) begin - phase_ct <= dir_b[1] ? phase_ct + 1 : phase_ct - 1; - end - step_b <= {step_b[1:0], step}; - dir_b <= {dir[0], dir}; + else if (step_rising) + phase_ct <= dir_r[1] ? phase_ct + 1 : phase_ct - 1; end - // Switch outputs + // Phase polarity control signal from microstep counter wire s1; wire s2; wire s3; wire s4; - // Off Timer active flag - wire off_timer_active0 = off_timer0 > 0; - wire off_timer_active1 = off_timer1 > 0; - - - wire fault0 = (minimum_on_timer0 > 0) && off_timer_active0; - wire fault1 = (minimum_on_timer1 > 0) && off_timer_active1; - wire fault = fault0 | fault1; + // Fault (active low) if off timer starts before minimum on timer expires + wire fault0 = off_timer0 && minimum_on_timer0 && enable; + wire fault1 = off_timer1 && minimum_on_timer1 && enable; + reg faultn; + // Fault latches until reset + always @(posedge clk) begin + if (!resetn) begin + fault0 <= 0; + fault1 <= 0; + faultn <= 1; + end + else if (faultn) begin + faultn <= ( fault0 | fault1 ) && enable; + end + end - reg [1:0] s1r, s2r, s3r, s4r; // Switch output history [ previous : now ] wire phase_a1_h, phase_a1_l, phase_a2_h, phase_a2_l; wire phase_b1_h, phase_b1_l, phase_b2_h, phase_b2_l; - // Switch output Low - assign s_l[0] = config_invert_lowside ^ (phase_a1_l | fault); - assign s_l[1] = config_invert_lowside ^ (phase_a2_l | fault); - assign s_l[2] = config_invert_lowside ^ (phase_b1_l | fault); - assign s_l[3] = config_invert_lowside ^ (phase_b2_l | fault); + // Low side output polarity, enable, and fault shutdown + assign phase_a1_l_out = config_invert_lowside ^ ( phase_a1_l | !enable ); + assign phase_a2_l_out = config_invert_lowside ^ ( phase_a2_l | !enable ); + assign phase_b1_l_out = config_invert_lowside ^ ( phase_b1_l | !enable ); + assign phase_b2_l_out = config_invert_lowside ^ ( phase_b2_l | !enable ); - // Switch output High - assign s_h[0] = config_invert_highside ^ (phase_a1_h | fault); - assign s_h[1] = config_invert_highside ^ (phase_a2_h | fault); - assign s_h[2] = config_invert_highside ^ (phase_b1_h | fault); - assign s_h[3] = config_invert_highside ^ (phase_b2_h | fault); + // High side + assign phase_a1_h_out = config_invert_highside ^ ( phase_a1_h && !faultn && enable ); + assign phase_a2_h_out = config_invert_highside ^ ( phase_a2_h && !faultn && enable ); + assign phase_b1_h_out = config_invert_highside ^ ( phase_b1_h && !faultn && enable ); + assign phase_b2_h_out = config_invert_highside ^ ( phase_b2_h && !faultn && enable ); // Fast decay is first x ticks of off time // default fast decay = 706 wire fastDecay0 = off_timer0 >= config_fastdecay_threshold; wire fastDecay1 = off_timer1 >= config_fastdecay_threshold; - // Slow decay remainder of off time - wire slowDecay0 = off_timer_active0 && fastDecay0 == 0; - wire slowDecay1 = off_timer_active1 && fastDecay1 == 0; - - // This portion of code sets up output to drive mosfets. Output ON = 0 - - // High side output logic - // If in slow decay = 1 - // OR ( fast decay and commanded to be OFF ) = 1 - // Then OFF - // Else If Not slow decay (Never in slow decay at same time as fast decay) - // OR ( not fast decay ) - // Then Follow commanded output - // Else if fast decay - // invert commanded polarity - assign phase_a1_h = slowDecay0 | ( fastDecay0 ? s1 : ~s1 ); + // Slow decay remainder of off time - Active high + wire slowDecay0 = off_timer0 && !fastDecay0; + wire slowDecay1 = off_timer1 && !fastDecay1; + + // This portion of code sets up output to drive mosfets. + // Output ON = 1 when config_invert_lowside and config_invert_highside == 0 + + // High side is ON if slow decay is NOT active + // AND + // ( + // In fast decay AND would normally be off this phase + // OR + // Should be on this phase / polarity + assign phase_a1_h = !slowDecay0 && ( fastDecay0 ? !s1 : s1 ); + assign phase_a2_h = !slowDecay0 && ( fastDecay0 ? !s2 : s2 ); + assign phase_b1_h = !slowDecay1 && ( fastDecay1 ? !s3 : s3 ); + assign phase_b2_h = !slowDecay1 && ( fastDecay1 ? !s4 : s4 ); // Low side output logic - // low side output (invert if configured with XOR) // Invert signal if fast decay commands. // If slow decay Then the output is low. // Else output = as commanded by microstep counter - assign phase_a1_l = fastDecay0 ? ~s1 : ( slowDecay0 ? 1'b0 : s1 ); - assign phase_a2_h = slowDecay0 | ( fastDecay0 ? s2 : ~s2 ); - assign phase_a2_l = fastDecay0 ? ~s2 : ( slowDecay0 ? 1'b0 : s2 ); - assign phase_b1_h = slowDecay1 | ( fastDecay1 ? s3 : ~s3 ); - assign phase_b1_l = fastDecay1 ? ~s3 : ( slowDecay1 ? 1'b0 : s3 ); - assign phase_b2_h = slowDecay1 | ( fastDecay1 ? s4 : ~s4 ); - assign phase_b2_l = fastDecay1 ? ~s4 : ( slowDecay1 ? 1'b0 : s4 ); - - // NEED DEAD TIME + // Low side is ON if slow decay is active + // OR + // Fast decay and would normally be off this phase + assign phase_a1_l = slowDecay0 | ( fastDecay0 ? s1 : !s1 ); + assign phase_a2_l = slowDecay0 | ( fastDecay0 ? s2 : !s2 ); + assign phase_b1_l = slowDecay1 | ( fastDecay1 ? s3 : !s3 ); + assign phase_b2_l = slowDecay1 | ( fastDecay1 ? s4 : !s4 ); + + // Fixed off time peak current controller // Start Off Time // Target peak current detected. Blank timer and Off timer not active - assign offtimer_en0 = analog_cmp1 & blank_timer0 == 0 & off_timer_active0 == 0; - assign offtimer_en1 = analog_cmp2 & blank_timer1 == 0 & off_timer_active1 == 0; + assign offtimer_en0 = analog_cmp1 & !blank_timer0 & !off_timer0; + assign offtimer_en1 = analog_cmp2 & !blank_timer1 & !off_timer1; `ifdef FORMAL always @(*) begin diff --git a/src/microstepper/microstepper_top.v b/src/microstepper/microstepper_top.v index cd43862..b4535f7 100644 --- a/src/microstepper/microstepper_top.v +++ b/src/microstepper/microstepper_top.v @@ -2,8 +2,14 @@ module microstepper_top ( input clk, input resetn, - output [3:0] s_l, - output [3:0] s_h, + output phase_a1_l, + output phase_a2_l, + output phase_b1_l, + output phase_b2_l, + output phase_a1_h, + output phase_a2_h, + output phase_b1_h, + output phase_b2_h, input analog_cmp1, output analog_out1, input analog_cmp2, @@ -11,6 +17,7 @@ module microstepper_top ( output chargepump_pin, input [9:0] config_offtime, input [7:0] config_blanktime, + input [2:0] config_deadtime, input [9:0] config_fastdecay_threshold, input [7:0] config_minimum_on_time, input [10:0] config_current_threshold, @@ -20,8 +27,8 @@ module microstepper_top ( //input [511:0] cos_table, input step, input dir, - input enable, - output fault, + input enable_in, + output faultn, ); wire [5:0] cos_index1; wire [5:0] cos_index2; @@ -43,25 +50,29 @@ module microstepper_top ( microstepper_control microstepper_control0( .clk(clk), .resetn(resetn), - .s_l(s_l), - .s_h(s_h), + .phase_a1_l_out(phase_a1_l), + .phase_a2_l_out(phase_a2_l), + .phase_b1_l_out(phase_b1_l), + .phase_b2_l_out(phase_b2_l), + .phase_a1_h_out(phase_a1_h), + .phase_a2_h_out(phase_a2_h), + .phase_b1_h_out(phase_b1_h), + .phase_b2_h_out(phase_b2_h), .config_fastdecay_threshold(config_fastdecay_threshold), .config_invert_highside(config_invert_highside), .config_invert_lowside(config_invert_lowside), .step(step), .dir(dir), - .enable(enable), + .enable_in(enable_in), .analog_cmp1(analog_cmp1), .analog_cmp2(analog_cmp2), - .fault(fault), + .faultn(faultn), .s1(s1), .s2(s2), .s3(s3), .s4(s4), .offtimer_en0(offtimer_en0), .offtimer_en1(offtimer_en1), - .a_starting(a_starting), - .b_starting(b_starting), .phase_ct(phase_ct), .blank_timer0(blank_timer0), .blank_timer1(blank_timer1), @@ -69,10 +80,11 @@ module microstepper_top ( .off_timer1(off_timer1), .minimum_on_timer0(minimum_on_timer0), .minimum_on_timer1(minimum_on_timer1), -// .off_timer0_done (off_timer0_done), -// .off_timer0_done (off_timer1_done), ); +wire [10:0] Woff_timer0_done; +wire [10:0] off_timer0_done; + mytimer_10 offtimer0 ( .clk (clk), .resetn (resetn), @@ -110,7 +122,7 @@ module microstepper_top ( mytimer_8 minimumontimer0 ( .clk (clk), .resetn (resetn), - .start_enable(a_starting), + .start_enable(off_timer0_done), .start_time (config_minimum_on_time), .timer (minimum_on_timer0) ); @@ -118,7 +130,7 @@ module microstepper_top ( mytimer_8 minimumontimer1 ( .clk (clk), .resetn (resetn), - .start_enable(b_starting), + .start_enable(off_timer1_done), .start_time (config_minimum_on_time), .timer (minimum_on_timer1) ); diff --git a/src/microstepper/mytimer_10.v b/src/microstepper/mytimer_10.v index d8c94a1..dc1db0f 100644 --- a/src/microstepper/mytimer_10.v +++ b/src/microstepper/mytimer_10.v @@ -14,8 +14,10 @@ module mytimer_10 ( assign timer = counter; always @(posedge clk) begin - if (!resetn) + if (!resetn) begin counter <= 0; + done <= 0; + end else if( start_enable ) begin counter <= start_time; run <= 1; diff --git a/src/rapcore.v b/src/rapcore.v index 7e51a81..c4e418b 100644 --- a/src/rapcore.v +++ b/src/rapcore.v @@ -216,8 +216,14 @@ module rapcore ( microstepper_top microstepper0( .clk(CLK), .resetn( resetn), - .s_l ({PHASE_B2[1], PHASE_B1[1], PHASE_A2[1], PHASE_A1[1]}), - .s_h ({PHASE_B2_H[1], PHASE_B1_H[1], PHASE_A2_H[1], PHASE_A1_H[1]}), + .phase_a1_l(PHASE_A1), + .phase_a2_l(PHASE_A2), + .phase_b1_l(PHASE_B1), + .phase_b2_l(PHASE_B2), + .phase_a1_h(PHASE_A1_H), + .phase_a2_h(PHASE_A2_H), + .phase_b1_h(PHASE_B1_H), + .phase_b2_h(PHASE_B2_H), .analog_cmp1 (analog_cmp1), .analog_out1 (analog_out1), .analog_cmp2 (analog_cmp2), diff --git a/testbench/hbridge_coil.v b/testbench/hbridge_coil.v index e37462b..98e46d5 100644 --- a/testbench/hbridge_coil.v +++ b/testbench/hbridge_coil.v @@ -7,6 +7,8 @@ module hbridge_coil ( input low_2, input high_2, output signed [12:0] current, + output current_sum_polarity, + input polarity_invert_config, ); reg signed [12:0] current; reg polarity; // arbitrary polarity @@ -14,10 +16,13 @@ module hbridge_coil ( reg [8:0] cnt; reg alive; reg slow_decay; - reg signed [2:0] current_ramp_cnt; // rates are delay counter sizes + reg signed current_ramp_cnt; // rates are delay counter sizes reg signed [3:0] slow_decay_cnt; reg signed [1:0] fast_decay_cnt; reg open; // coils not connected. Should never occur? + wire current_sum_polarity; + + assign current_sum_polarity = (current >= 0); // For each coil of motor // Each coil is driven by 2 half bridges. _1 and _2 // Each half bridge is driven by two drivers. high_ and low_ @@ -41,16 +46,23 @@ module hbridge_coil ( slow_decay_cnt <= slow_decay_cnt + 1; fast_decay_cnt <= fast_decay_cnt + 1; on <= ( low_1 && high_2 ) | ( low_2 && high_1 ); - polarity <= high_2 && low_1; + if ( polarity_invert_config ) + polarity <= high_2 && low_1; + else + polarity <= low_2 && high_1; slow_decay <= ( low_1 && low_2 ) | ( high_1 && high_2 ); if ( on ) begin - if ( polarity && !current_ramp_cnt ) - current <= current + 1; - else if ( !polarity && current && !fast_decay_cnt ) - current <= current - 1; + if ( polarity ) + current <= current + !current_ramp_cnt; + else + current <= current - !current_ramp_cnt; // fast decay + end + else if ( slow_decay && current !== 0 && !slow_decay_cnt ) begin + if (current >= 0) // current is positive + current <= current - 1; // slow decay every 4th tick + else + current <= current + 1; end - else if ( slow_decay && current && !slow_decay_cnt ) - current <= current - 1; // slow decay every 4th tick end end endmodule diff --git a/testbench/microstepper_tb.v b/testbench/microstepper_tb.v index 7869484..1662f2c 100644 --- a/testbench/microstepper_tb.v +++ b/testbench/microstepper_tb.v @@ -13,6 +13,7 @@ module testbench( output analog_out2, output chargepump_pin, output faultn, + output current_sum_polarity, ); reg step; @@ -43,11 +44,13 @@ module testbench( reg analog_cmp2; reg [40:0] step_clock; reg [20:0] cnt; + reg [12:0] current_abs1; + reg [12:0] current_abs2; always @(posedge clk) begin if (!resetn) begin cnt <= 0; - analog_cmp1 <= 0; - analog_cmp2 <= 0; + analog_cmp1 <= 1; + analog_cmp2 <= 1; step <= 1; enable_in <= 1; config_offtime = 810; @@ -56,25 +59,34 @@ module testbench( config_minimum_on_time = 54; config_current_threshold = 1024; config_chargepump_period = 91; - config_invert_highside = 0; - config_invert_lowside = 0; + config_invert_highside = 1; + config_invert_lowside = 1; step_clock = 0; end else begin cnt <= cnt + 1; enable_in <= 1; + if (current1[12] == 1'b1) begin + current_abs1 = -current; + end + else begin + current_abs1 = current1; + end + if (current2[12] == 1'b1) begin + current_abs2 = -current2; + end + else begin + current_abs2 = current2; + end step_clock <= step_clock + 1; - step <= step_clock[11]; - if (current1[12:0] > target_current1) analog_cmp1 <= 1; // compare unsigned - else analog_cmp1 <= 0; - if (current2[12:0] > target_current2) analog_cmp2 <= 1; - else analog_cmp2 <= 0; - if (cnt <= 20'hAEC) begin + step <= step_clock[10]; + analog_cmp1 <= (current_abs1[11:0] >= target_current1[11:0]); // compare unsigned + analog_cmp2 <= (current_abs2[11:0] >= target_current2[11:0]); + if (cnt <= 20'h4CA9) begin dir <= 1; end - else if (cnt <= 20'hEBE) begin + else dir <= 0; - end end end @@ -126,7 +138,9 @@ module testbench( .high_1(phase_a1_h), .low_2(phase_a2_l), .high_2(phase_a2_h), - .current(current1) + .current(current1), + .current_sum_polarity(current_sum_polarity), + .polarity_invert_config(1) ); hbridge_coil hbridge_coil2( .clk(clk), @@ -135,7 +149,9 @@ module testbench( .high_1(phase_b1_h), .low_2(phase_b2_l), .high_2(phase_b2_h), - .current(current2) + .current(current2), + .current_sum_polarity(current_sum_polarity), + .polarity_invert_config(1) ); endmodule From 7ea048520a01e6345f87d18e404ab295a9d88774 Mon Sep 17 00:00:00 2001 From: johnnyr Date: Sun, 6 Dec 2020 21:45:22 -0600 Subject: [PATCH 34/71] fix undeclared errors. add default_nettype none. --- src/microstepper/analog_out.v | 1 + src/microstepper/chargepump.v | 1 + src/microstepper/cosine.v | 1 + src/microstepper/microstep_counter.v | 1 + src/microstepper/microstepper_control.v | 32 ++++++++++--------------- src/microstepper/microstepper_top.v | 3 ++- src/microstepper/mytimer.v | 1 + src/microstepper/mytimer_10.v | 1 + src/microstepper/mytimer_8.v | 1 + src/quad_enc.v | 22 ----------------- src/rapcore.v | 2 +- testbench/microstepper_tb.v | 22 ++++++++++++----- 12 files changed, 38 insertions(+), 50 deletions(-) diff --git a/src/microstepper/analog_out.v b/src/microstepper/analog_out.v index 1b55c55..b0a3305 100644 --- a/src/microstepper/analog_out.v +++ b/src/microstepper/analog_out.v @@ -1,3 +1,4 @@ +`default_nettype none module analog_out ( input wire clk, input wire resetn, diff --git a/src/microstepper/chargepump.v b/src/microstepper/chargepump.v index 9fad9c0..8550ddb 100644 --- a/src/microstepper/chargepump.v +++ b/src/microstepper/chargepump.v @@ -1,3 +1,4 @@ +`default_nettype none module chargepump ( input clk, input resetn, diff --git a/src/microstepper/cosine.v b/src/microstepper/cosine.v index 460e5cf..07d9631 100644 --- a/src/microstepper/cosine.v +++ b/src/microstepper/cosine.v @@ -1,3 +1,4 @@ +`default_nettype none module cosine ( input wire [5:0] cos_index, output wire [7:0] cos_value diff --git a/src/microstepper/microstep_counter.v b/src/microstepper/microstep_counter.v index 7ea6f0c..0453a57 100644 --- a/src/microstepper/microstep_counter.v +++ b/src/microstepper/microstep_counter.v @@ -1,3 +1,4 @@ +`default_nettype none module microstep_counter ( input [7:0] pos, output [5:0] cos_index1, diff --git a/src/microstepper/microstepper_control.v b/src/microstepper/microstepper_control.v index cba55af..cafe08b 100644 --- a/src/microstepper/microstepper_control.v +++ b/src/microstepper/microstepper_control.v @@ -1,3 +1,4 @@ +`default_nettype none module microstepper_control ( input clk, input resetn, @@ -71,8 +72,8 @@ module microstepper_control ( // Fault latches until reset always @(posedge clk) begin if (!resetn) begin - fault0 <= 0; - fault1 <= 0; +// fault0 <= 0; +// fault1 <= 0; faultn <= 1; end else if (faultn) begin @@ -104,35 +105,26 @@ module microstepper_control ( wire slowDecay0 = off_timer0 && !fastDecay0; wire slowDecay1 = off_timer1 && !fastDecay1; - // This portion of code sets up output to drive mosfets. - // Output ON = 1 when config_invert_lowside and config_invert_highside == 0 - - // High side is ON if slow decay is NOT active + // Half bridge high side is active + // WHEN slow decay is NOT active // AND - // ( - // In fast decay AND would normally be off this phase + // ( fast decay active AND would normally be off this phase ) // OR - // Should be on this phase / polarity + // Should be on to drive this phase / polarity (microstepper_counter) assign phase_a1_h = !slowDecay0 && ( fastDecay0 ? !s1 : s1 ); assign phase_a2_h = !slowDecay0 && ( fastDecay0 ? !s2 : s2 ); assign phase_b1_h = !slowDecay1 && ( fastDecay1 ? !s3 : s3 ); assign phase_b2_h = !slowDecay1 && ( fastDecay1 ? !s4 : s4 ); - // Low side output logic - // Invert signal if fast decay commands. - // If slow decay Then the output is low. - // Else output = as commanded by microstep counter - - // Low side is ON if slow decay is active + // Low side is active + // WHEN slow decay is active // OR - // Fast decay and would normally be off this phase + // ( Fast decay active AND would normally be off this phase ) assign phase_a1_l = slowDecay0 | ( fastDecay0 ? s1 : !s1 ); assign phase_a2_l = slowDecay0 | ( fastDecay0 ? s2 : !s2 ); assign phase_b1_l = slowDecay1 | ( fastDecay1 ? s3 : !s3 ); assign phase_b2_l = slowDecay1 | ( fastDecay1 ? s4 : !s4 ); - - // Fixed off time peak current controller - // Start Off Time - // Target peak current detected. Blank timer and Off timer not active + + // Fixed off time peak current controller off time start assign offtimer_en0 = analog_cmp1 & !blank_timer0 & !off_timer0; assign offtimer_en1 = analog_cmp2 & !blank_timer1 & !off_timer1; diff --git a/src/microstepper/microstepper_top.v b/src/microstepper/microstepper_top.v index b4535f7..e14e7a2 100644 --- a/src/microstepper/microstepper_top.v +++ b/src/microstepper/microstepper_top.v @@ -1,4 +1,4 @@ - +`default_nettype none module microstepper_top ( input clk, input resetn, @@ -46,6 +46,7 @@ module microstepper_top ( wire [9:0] off_timer1; wire [7:0] minimum_on_timer0; wire [7:0] minimum_on_timer1; + wire off_timer1_done; microstepper_control microstepper_control0( .clk(clk), diff --git a/src/microstepper/mytimer.v b/src/microstepper/mytimer.v index 4c11f73..1f5112b 100644 --- a/src/microstepper/mytimer.v +++ b/src/microstepper/mytimer.v @@ -1,3 +1,4 @@ +`default_nettype none module mytimer ( input clk, input resetn, diff --git a/src/microstepper/mytimer_10.v b/src/microstepper/mytimer_10.v index dc1db0f..d285dd4 100644 --- a/src/microstepper/mytimer_10.v +++ b/src/microstepper/mytimer_10.v @@ -1,3 +1,4 @@ +`default_nettype none module mytimer_10 ( input clk, input resetn, diff --git a/src/microstepper/mytimer_8.v b/src/microstepper/mytimer_8.v index 5519e6b..aacfcf8 100644 --- a/src/microstepper/mytimer_8.v +++ b/src/microstepper/mytimer_8.v @@ -1,3 +1,4 @@ +`default_nettype none module mytimer_8 ( input clk, input resetn, diff --git a/src/quad_enc.v b/src/quad_enc.v index e8ee9ab..7cabd2a 100755 --- a/src/quad_enc.v +++ b/src/quad_enc.v @@ -1,25 +1,3 @@ -/* UltiCores -- IP Cores for Mechatronic Control Systems - * - * Copyright (C) 2019 UltiMachine - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -/* quad_enc.v - * Quadrature decoder inspired by https://www.fpga4fun.com/QuadratureDecoder.html - * Converted to 32 bit. Added reset and fault logic. Changed some names to fit us. - */ - `default_nettype none module quad_enc #( diff --git a/src/rapcore.v b/src/rapcore.v index c4e418b..fa11582 100644 --- a/src/rapcore.v +++ b/src/rapcore.v @@ -240,7 +240,7 @@ module rapcore ( //.cos_table (cos_table), .step (step), .dir (dir), - .enable(enable), + .enable_in(enable), ); `endif diff --git a/testbench/microstepper_tb.v b/testbench/microstepper_tb.v index 1662f2c..a71aed7 100644 --- a/testbench/microstepper_tb.v +++ b/testbench/microstepper_tb.v @@ -1,3 +1,4 @@ +`default_nettype none `include "../src/microstepper/microstepper_top.v" `include "hbridge_coil.v" `include "pwm_duty.v" @@ -18,7 +19,7 @@ module testbench( reg step; reg dir; - reg enable; + reg enable_in; reg [12:0] target_current1; reg [12:0] target_current2; reg signed [12:0] current1; @@ -46,6 +47,15 @@ module testbench( reg [20:0] cnt; reg [12:0] current_abs1; reg [12:0] current_abs2; + wire phase_a1_l; + wire phase_a2_l; + wire phase_b1_l; + wire phase_b2_l; + wire phase_a1_h; + wire phase_a2_h; + wire phase_b1_h; + wire phase_b2_h; + always @(posedge clk) begin if (!resetn) begin cnt <= 0; @@ -59,15 +69,15 @@ module testbench( config_minimum_on_time = 54; config_current_threshold = 1024; config_chargepump_period = 91; - config_invert_highside = 1; - config_invert_lowside = 1; + config_invert_highside = 0; + config_invert_lowside = 0; step_clock = 0; end else begin cnt <= cnt + 1; enable_in <= 1; if (current1[12] == 1'b1) begin - current_abs1 = -current; + current_abs1 = -current1; end else begin current_abs1 = current1; @@ -140,7 +150,7 @@ module testbench( .high_2(phase_a2_h), .current(current1), .current_sum_polarity(current_sum_polarity), - .polarity_invert_config(1) + .polarity_invert_config(0) ); hbridge_coil hbridge_coil2( .clk(clk), @@ -151,7 +161,7 @@ module testbench( .high_2(phase_b2_h), .current(current2), .current_sum_polarity(current_sum_polarity), - .polarity_invert_config(1) + .polarity_invert_config(0) ); endmodule From 0b16c3896a52487bc7ccd2031cff2c64980276ac Mon Sep 17 00:00:00 2001 From: Steve Kelly Date: Sun, 6 Dec 2020 23:33:16 -0500 Subject: [PATCH 35/71] fix reg init --- src/rapcore.v | 98 ++++++++--------------------------- src/spi_state_machine.v | 111 +++++++++++++++++++++++++++++++++++----- 2 files changed, 118 insertions(+), 91 deletions(-) diff --git a/src/rapcore.v b/src/rapcore.v index d8dfdec..f8b4139 100644 --- a/src/rapcore.v +++ b/src/rapcore.v @@ -80,89 +80,23 @@ module rapcore ( // Stepper Setup // TODO: Generate statement? // Stepper Config - reg [2:0] microsteps = 2; - reg [7:0] current = 140; - reg [9:0] config_offtime = 810; - reg [7:0] config_blanktime = 27; - reg [9:0] config_fastdecay_threshold = 706; - reg [7:0] config_minimum_on_time = 54; - reg [10:0] config_current_threshold = 1024; - reg [7:0] config_chargepump_period = 91; - reg config_invert_highside = 0; - reg config_invert_lowside = 0; - reg [511:0] cos_table; + wire [2:0] microsteps; + wire [7:0] current; + wire [9:0] config_offtime; + wire [7:0] config_blanktime; + wire [9:0] config_fastdecay_threshold; + wire [7:0] config_minimum_on_time; + wire [10:0] config_current_threshold; + wire [7:0] config_chargepump_period; + wire config_invert_highside; + wire config_invert_lowside; + wire [511:0] cos_table; // Stepper control lines wire step; wire dir; reg enable; - initial begin - cos_table [ 7 : 0 ] = 255 ; - cos_table [ 15 : 8 ] = 255 ; - cos_table [ 23 : 16 ] = 255 ; - cos_table [ 31 : 24 ] = 254 ; - cos_table [ 39 : 32 ] = 254 ; - cos_table [ 47 : 40 ] = 253 ; - cos_table [ 55 : 48 ] = 252 ; - cos_table [ 63 : 56 ] = 251 ; - cos_table [ 71 : 64 ] = 250 ; - cos_table [ 79 : 72 ] = 249 ; - cos_table [ 87 : 80 ] = 247 ; - cos_table [ 95 : 88 ] = 246 ; - cos_table [ 103 : 96 ] = 244 ; - cos_table [ 111 : 104 ] = 242 ; - cos_table [ 119 : 112 ] = 240 ; - cos_table [ 127 : 120 ] = 238 ; - cos_table [ 135 : 128 ] = 236 ; - cos_table [ 143 : 136 ] = 233 ; - cos_table [ 151 : 144 ] = 231 ; - cos_table [ 159 : 152 ] = 228 ; - cos_table [ 167 : 160 ] = 225 ; - cos_table [ 175 : 168 ] = 222 ; - cos_table [ 183 : 176 ] = 219 ; - cos_table [ 191 : 184 ] = 215 ; - cos_table [ 199 : 192 ] = 212 ; - cos_table [ 207 : 200 ] = 208 ; - cos_table [ 215 : 208 ] = 205 ; - cos_table [ 223 : 216 ] = 201 ; - cos_table [ 231 : 224 ] = 197 ; - cos_table [ 239 : 232 ] = 193 ; - cos_table [ 247 : 240 ] = 189 ; - cos_table [ 255 : 248 ] = 185 ; - cos_table [ 263 : 256 ] = 180 ; - cos_table [ 271 : 264 ] = 176 ; - cos_table [ 279 : 272 ] = 171 ; - cos_table [ 287 : 280 ] = 167 ; - cos_table [ 295 : 288 ] = 162 ; - cos_table [ 303 : 296 ] = 157 ; - cos_table [ 311 : 304 ] = 152 ; - cos_table [ 319 : 312 ] = 147 ; - cos_table [ 327 : 320 ] = 142 ; - cos_table [ 335 : 328 ] = 136 ; - cos_table [ 343 : 336 ] = 131 ; - cos_table [ 351 : 344 ] = 126 ; - cos_table [ 359 : 352 ] = 120 ; - cos_table [ 367 : 360 ] = 115 ; - cos_table [ 375 : 368 ] = 109 ; - cos_table [ 383 : 376 ] = 103 ; - cos_table [ 391 : 384 ] = 98 ; - cos_table [ 399 : 392 ] = 92 ; - cos_table [ 407 : 400 ] = 86 ; - cos_table [ 415 : 408 ] = 80 ; - cos_table [ 423 : 416 ] = 74 ; - cos_table [ 431 : 424 ] = 68 ; - cos_table [ 439 : 432 ] = 62 ; - cos_table [ 447 : 440 ] = 56 ; - cos_table [ 455 : 448 ] = 50 ; - cos_table [ 463 : 456 ] = 44 ; - cos_table [ 471 : 464 ] = 37 ; - cos_table [ 479 : 472 ] = 31 ; - cos_table [ 487 : 480 ] = 25 ; - cos_table [ 495 : 488 ] = 19 ; - cos_table [ 503 : 496 ] = 13 ; - cos_table [ 511 : 504 ] = 6 ; - end // // Stepper Modules @@ -235,10 +169,12 @@ module rapcore ( spi_state_machine spifsm ( .CLK(CLK), + .SCK(SCK), .CS(CS), .COPI(COPI), .CIPO(CIPO), + .microsteps(microsteps), .current(current), .config_offtime(config_offtime), @@ -249,8 +185,14 @@ module rapcore ( .config_chargepump_period(config_chargepump_period), .config_invert_highside(config_invert_highside), .config_invert_lowside(config_invert_lowside), - //.cos_table(cos_table), // TODO + .cos_table(cos_table), + .encoder_count(encoder_count), + + .step(step), + .dir(dir), + .enable(enable), + `ifdef BUFFER_DTR .BUFFER_DTR(BUFFER_DTR), `endif diff --git a/src/spi_state_machine.v b/src/spi_state_machine.v index ba156a6..b7f2b29 100644 --- a/src/spi_state_machine.v +++ b/src/spi_state_machine.v @@ -16,17 +16,17 @@ module spi_state_machine( output enable, // Stepper Config - output reg [2:0] microsteps, - output reg [7:0] current, - output reg [9:0] config_offtime, - output reg [7:0] config_blanktime, - output reg [9:0] config_fastdecay_threshold, - output reg [7:0] config_minimum_on_time, - output reg [10:0] config_current_threshold, - output reg [7:0] config_chargepump_period, - output reg config_invert_highside, - output reg config_invert_lowside, - //output reg [511:0] cos_table, + output [2:0] microsteps, + output [7:0] current, + output [9:0] config_offtime, + output [7:0] config_blanktime, + output [9:0] config_fastdecay_threshold, + output [7:0] config_minimum_on_time, + output [10:0] config_current_threshold, + output [7:0] config_chargepump_period, + output config_invert_highside, + output config_invert_lowside, + output [511:0] cos_table, // encoder input [63:0] encoder_count, @@ -79,6 +79,88 @@ module spi_state_machine( .word_data_received(word_data_received)); + // + // Stepper Config + // + + reg [2:0] microsteps = 2; + reg [7:0] current = 140; + reg [9:0] config_offtime = 810; + reg [7:0] config_blanktime = 27; + reg [9:0] config_fastdecay_threshold = 706; + reg [7:0] config_minimum_on_time = 54; + reg [10:0] config_current_threshold = 1024; + reg [7:0] config_chargepump_period = 91; + reg config_invert_highside = 0; + reg config_invert_lowside = 0; + reg [511:0] cos_table; + + initial begin + cos_table [ 7 : 0 ] = 255 ; + cos_table [ 15 : 8 ] = 255 ; + cos_table [ 23 : 16 ] = 255 ; + cos_table [ 31 : 24 ] = 254 ; + cos_table [ 39 : 32 ] = 254 ; + cos_table [ 47 : 40 ] = 253 ; + cos_table [ 55 : 48 ] = 252 ; + cos_table [ 63 : 56 ] = 251 ; + cos_table [ 71 : 64 ] = 250 ; + cos_table [ 79 : 72 ] = 249 ; + cos_table [ 87 : 80 ] = 247 ; + cos_table [ 95 : 88 ] = 246 ; + cos_table [ 103 : 96 ] = 244 ; + cos_table [ 111 : 104 ] = 242 ; + cos_table [ 119 : 112 ] = 240 ; + cos_table [ 127 : 120 ] = 238 ; + cos_table [ 135 : 128 ] = 236 ; + cos_table [ 143 : 136 ] = 233 ; + cos_table [ 151 : 144 ] = 231 ; + cos_table [ 159 : 152 ] = 228 ; + cos_table [ 167 : 160 ] = 225 ; + cos_table [ 175 : 168 ] = 222 ; + cos_table [ 183 : 176 ] = 219 ; + cos_table [ 191 : 184 ] = 215 ; + cos_table [ 199 : 192 ] = 212 ; + cos_table [ 207 : 200 ] = 208 ; + cos_table [ 215 : 208 ] = 205 ; + cos_table [ 223 : 216 ] = 201 ; + cos_table [ 231 : 224 ] = 197 ; + cos_table [ 239 : 232 ] = 193 ; + cos_table [ 247 : 240 ] = 189 ; + cos_table [ 255 : 248 ] = 185 ; + cos_table [ 263 : 256 ] = 180 ; + cos_table [ 271 : 264 ] = 176 ; + cos_table [ 279 : 272 ] = 171 ; + cos_table [ 287 : 280 ] = 167 ; + cos_table [ 295 : 288 ] = 162 ; + cos_table [ 303 : 296 ] = 157 ; + cos_table [ 311 : 304 ] = 152 ; + cos_table [ 319 : 312 ] = 147 ; + cos_table [ 327 : 320 ] = 142 ; + cos_table [ 335 : 328 ] = 136 ; + cos_table [ 343 : 336 ] = 131 ; + cos_table [ 351 : 344 ] = 126 ; + cos_table [ 359 : 352 ] = 120 ; + cos_table [ 367 : 360 ] = 115 ; + cos_table [ 375 : 368 ] = 109 ; + cos_table [ 383 : 376 ] = 103 ; + cos_table [ 391 : 384 ] = 98 ; + cos_table [ 399 : 392 ] = 92 ; + cos_table [ 407 : 400 ] = 86 ; + cos_table [ 415 : 408 ] = 80 ; + cos_table [ 423 : 416 ] = 74 ; + cos_table [ 431 : 424 ] = 68 ; + cos_table [ 439 : 432 ] = 62 ; + cos_table [ 447 : 440 ] = 56 ; + cos_table [ 455 : 448 ] = 50 ; + cos_table [ 463 : 456 ] = 44 ; + cos_table [ 471 : 464 ] = 37 ; + cos_table [ 479 : 472 ] = 31 ; + cos_table [ 487 : 480 ] = 25 ; + cos_table [ 495 : 488 ] = 19 ; + cos_table [ 503 : 496 ] = 13 ; + cos_table [ 511 : 504 ] = 6 ; + end // // Stepper Timing Setup @@ -103,7 +185,10 @@ module spi_state_machine( wire [63:0] increment_w = increment[moveind]; wire [63:0] incrementincrement_w = incrementincrement[moveind]; + // Step IO wire dda_step; + reg enable_r; + assign enable = enable_r; // Implement flow control and event pins if specified `ifdef BUFFER_DTR @@ -184,7 +269,7 @@ module spi_state_machine( // Motor Enable/disable `CMD_MOTOR_ENABLE: begin - enable <= word_data_received[0]; + enable_r <= word_data_received[0]; end // Clock divisor (24 bit) @@ -222,7 +307,7 @@ module spi_state_machine( // Write to Cosine Table // TODO Cosine Net is broken `CMD_COSINE_CONFIG: begin - //config_cosine_table[word_data_received[35:32]] <= word_data_received[31:0]; + cos_table[word_data_received[35:32]] <= word_data_received[31:0]; //cos_table[word_data_received[37:32]] <= word_data_received[7:0]; //cos_table[word_data_received[35:32]+3] <= word_data_received[31:25]; //cos_table[word_data_received[35:32]+2] <= word_data_received[24:16]; From 1babaa58357cbe87d9f3e6635c5c4bda38458670 Mon Sep 17 00:00:00 2001 From: Steve Kelly Date: Sun, 6 Dec 2020 23:42:29 -0500 Subject: [PATCH 36/71] fix formal --- symbiyosys.sby | 2 ++ 1 file changed, 2 insertions(+) diff --git a/symbiyosys.sby b/symbiyosys.sby index cf27c3b..5df2822 100644 --- a/symbiyosys.sby +++ b/symbiyosys.sby @@ -13,6 +13,7 @@ read -formal spi.v read -formal stepper.v read -formal quad_enc.v read -formal pwm.v +read -formal spi_state_machine.v read -formal microstepper_top.v read -formal analog_out.v read -formal chargepump.v @@ -29,6 +30,7 @@ src/constants.v src/dda_timer.v src/spi.v src/stepper.v +src/spi_state_machine.v src/rapcore.v src/quad_enc.v src/pwm.v From 9957e6cf7ce51cd20a5c59f48d331faf2f6316f5 Mon Sep 17 00:00:00 2001 From: johnnyr Date: Sun, 6 Dec 2020 23:00:53 -0600 Subject: [PATCH 37/71] fix merged end comment --- src/rapcore.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/rapcore.v b/src/rapcore.v index fa11582..6ad4bd7 100644 --- a/src/rapcore.v +++ b/src/rapcore.v @@ -192,7 +192,7 @@ module rapcore ( cos_table [ 503 : 496 ] = 13 ; cos_table [ 511 : 504 ] = 6 ; end - +*/ // // Stepper Modules // From ad77a0abcc7f22f3148e9ab07308f6896b9e441d Mon Sep 17 00:00:00 2001 From: johnnyr Date: Sun, 6 Dec 2020 22:23:39 -0600 Subject: [PATCH 38/71] merget tb_m --- src/rapcore.v | 120 +++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 119 insertions(+), 1 deletion(-) diff --git a/src/rapcore.v b/src/rapcore.v index f8b4139..27a1fdb 100644 --- a/src/rapcore.v +++ b/src/rapcore.v @@ -80,6 +80,7 @@ module rapcore ( // Stepper Setup // TODO: Generate statement? // Stepper Config +<<<<<<< HEAD wire [2:0] microsteps; wire [7:0] current; wire [9:0] config_offtime; @@ -91,6 +92,20 @@ module rapcore ( wire config_invert_highside; wire config_invert_lowside; wire [511:0] cos_table; +======= + reg [2:0] microsteps = 2; + reg [7:0] current = 140; + reg [9:0] config_offtime = 810; + reg [7:0] config_blanktime = 27; + reg [9:0] config_fastdecay_threshold = 706; + reg [7:0] config_minimum_on_time = 54; + reg [10:0] config_current_threshold = 1024; + reg [7:0] config_chargepump_period = 91; + reg config_invert_highside = 0; + reg config_invert_lowside = 0; + /* + reg [511:0] cos_table; +>>>>>>> merget tb_m // Stepper control lines wire step; @@ -136,7 +151,7 @@ module rapcore ( .config_chargepump_period (config_chargepump_period), .config_invert_highside (config_invert_highside), .config_invert_lowside (config_invert_lowside), - .cos_table (cos_table), + //.cos_table (cos_table), .step (step), .dir (dir), .enable(enable), @@ -189,9 +204,112 @@ module rapcore ( .encoder_count(encoder_count), +<<<<<<< HEAD .step(step), .dir(dir), .enable(enable), +======= + // Coordinated Move + `CMD_COORDINATED_STEP: begin + + // Get Direction Bits + dir_r[writemoveind] <= word_data_received[0]; + + // Store encoder values across all axes Now + encoder_store <= encoder_count; + + end + + // Motor Enable/disable + `CMD_MOTOR_ENABLE: begin + enable <= word_data_received[0]; + end + + // Clock divisor (24 bit) + `CMD_CLK_DIVISOR: begin + clock_divisor[7:0] <= word_data_received[7:0]; + end + + // Set Microstepping + `CMD_MOTORCONFIG: begin + // TODO needs to be power of two + current[7:0] <= word_data_received[15:8]; + microsteps[2:0] <= word_data_received[2:0]; + end + + // Set Microstepping Parameters + `CMD_MICROSTEPPER_CONFIG: begin + config_offtime[9:0] <= word_data_received[39:30]; + config_blanktime[7:0] <= word_data_received[29:22]; + config_fastdecay_threshold[9:0] <= word_data_received[21:12]; + config_minimum_on_time[7:0] <= word_data_received[18:11]; + config_current_threshold[10:0] <= word_data_received[10:0]; + end + + // Set chargepump period + `CMD_CHARGEPUMP: begin + config_chargepump_period[7:0] <= word_data_received[7:0]; + end + + // Invert Bridge outputs + `CMD_BRIDGEINVERT: begin + config_invert_highside <= word_data_received[1]; + config_invert_lowside <= word_data_received[0]; + end +/* + // Write to Cosine Table + `CMD_COSINE_CONFIG: begin + //config_cosine_table[word_data_received[35:32]] <= word_data_received[31:0]; + cos_table[word_data_received[37:32]] <= word_data_received[7:0]; + //cos_table[word_data_received[35:32]+3] <= word_data_received[31:25]; + //cos_table[word_data_received[35:32]+2] <= word_data_received[24:16]; + //cos_table[word_data_received[35:32]+1] <= word_data_received[15:8]; + //cos_table[word_data_received[35:32]] <= word_data_received[7:0]; + end +*/ + // API Version + `CMD_API_VERSION: begin + word_send_data[7:0] <= `VERSION_PATCH; + word_send_data[15:8] <= `VERSION_MINOR; + word_send_data[23:16] <= `VERSION_MAJOR; + end + + endcase + + // Addition Word Processing + end else begin + + message_word_count <= message_word_count + 1; + + case (message_header) + // Move Routine + `CMD_COORDINATED_STEP: begin + // the first non-header word is the move duration + case (message_word_count) + 1: begin + move_duration[writemoveind][63:0] <= word_data_received[63:0]; + //word_send_data[63:0] = last_steps_taken[63:0]; // Prep to send steps + end + 2: begin + increment[writemoveind][63:0] <= word_data_received[63:0]; + word_send_data[63:0] <= encoder_store[63:0]; // Prep to send encoder read + end + 3: begin + incrementincrement[writemoveind][63:0] <= word_data_received[63:0]; + message_word_count <= 0; + stepready[writemoveind] <= ~stepready[writemoveind]; + writemoveind <= writemoveind + 1'b1; + message_header <= 8'b0; // Reset Message Header + `ifdef FORMAL + assert(writemoveind <= `MOVE_BUFFER_SIZE); + `endif + end + endcase + end + endcase + end + end +>>>>>>> merget tb_m `ifdef BUFFER_DTR .BUFFER_DTR(BUFFER_DTR), From a0eaa0d9e5aa028bb25f1b4182a7d466ea3c0073 Mon Sep 17 00:00:00 2001 From: Tonokip Date: Mon, 30 Nov 2020 19:36:25 -0600 Subject: [PATCH 39/71] static cosine table --- src/microstepper/cosine.v | 206 +++++++++------------------- src/microstepper/microstepper_top.v | 6 +- 2 files changed, 68 insertions(+), 144 deletions(-) diff --git a/src/microstepper/cosine.v b/src/microstepper/cosine.v index 4a09583..460e5cf 100644 --- a/src/microstepper/cosine.v +++ b/src/microstepper/cosine.v @@ -1,150 +1,74 @@ module cosine ( input wire [5:0] cos_index, - output wire [7:0] cos_value, - input wire [511:0] cos_table + output wire [7:0] cos_value ); - - //reg [31:0] cos_table[0:255]; - - //assign cos_value = cos_table[cos_index*8+7:cos_index*8]; - reg [7:0] cos_r; assign cos_value = cos_r; - always @(*) case (cos_index) - 1'd0 : cos_r <= cos_table [ 7 : 0 ]; - 1'd1 : cos_r <= cos_table [ 15 : 8 ]; - 2'd2 : cos_r <= cos_table [ 23 : 16 ]; - 2'd3 : cos_r <= cos_table [ 31 : 24 ]; - 3'd4 : cos_r <= cos_table [ 39 : 32 ]; - 3'd5 : cos_r <= cos_table [ 47 : 40 ]; - 3'd6 : cos_r <= cos_table [ 55 : 48 ]; - 3'd7 : cos_r <= cos_table [ 63 : 56 ]; - 4'd8 : cos_r <= cos_table [ 71 : 64 ]; - 4'd9 : cos_r <= cos_table [ 79 : 72 ]; - 4'd10 : cos_r <= cos_table [ 87 : 80 ]; - 4'd11 : cos_r <= cos_table [ 95 : 88 ]; - 4'd12 : cos_r <= cos_table [ 103 : 96 ]; - 4'd13 : cos_r <= cos_table [ 111 : 104 ]; - 4'd14 : cos_r <= cos_table [ 119 : 112 ]; - 4'd15 : cos_r <= cos_table [ 127 : 120 ]; - 5'd16 : cos_r <= cos_table [ 135 : 128 ]; - 5'd17 : cos_r <= cos_table [ 143 : 136 ]; - 5'd18 : cos_r <= cos_table [ 151 : 144 ]; - 5'd19 : cos_r <= cos_table [ 159 : 152 ]; - 5'd20 : cos_r <= cos_table [ 167 : 160 ]; - 5'd21 : cos_r <= cos_table [ 175 : 168 ]; - 5'd22 : cos_r <= cos_table [ 183 : 176 ]; - 5'd23 : cos_r <= cos_table [ 191 : 184 ]; - 5'd24 : cos_r <= cos_table [ 199 : 192 ]; - 5'd25 : cos_r <= cos_table [ 207 : 200 ]; - 5'd26 : cos_r <= cos_table [ 215 : 208 ]; - 5'd27 : cos_r <= cos_table [ 223 : 216 ]; - 5'd28 : cos_r <= cos_table [ 231 : 224 ]; - 5'd29 : cos_r <= cos_table [ 239 : 232 ]; - 5'd30 : cos_r <= cos_table [ 247 : 240 ]; - 5'd31 : cos_r <= cos_table [ 255 : 248 ]; - 6'd32 : cos_r <= cos_table [ 263 : 256 ]; - 6'd33 : cos_r <= cos_table [ 271 : 264 ]; - 6'd34 : cos_r <= cos_table [ 279 : 272 ]; - 6'd35 : cos_r <= cos_table [ 287 : 280 ]; - 6'd36 : cos_r <= cos_table [ 295 : 288 ]; - 6'd37 : cos_r <= cos_table [ 303 : 296 ]; - 6'd38 : cos_r <= cos_table [ 311 : 304 ]; - 6'd39 : cos_r <= cos_table [ 319 : 312 ]; - 6'd40 : cos_r <= cos_table [ 327 : 320 ]; - 6'd41 : cos_r <= cos_table [ 335 : 328 ]; - 6'd42 : cos_r <= cos_table [ 343 : 336 ]; - 6'd43 : cos_r <= cos_table [ 351 : 344 ]; - 6'd44 : cos_r <= cos_table [ 359 : 352 ]; - 6'd45 : cos_r <= cos_table [ 367 : 360 ]; - 6'd46 : cos_r <= cos_table [ 375 : 368 ]; - 6'd47 : cos_r <= cos_table [ 383 : 376 ]; - 6'd48 : cos_r <= cos_table [ 391 : 384 ]; - 6'd49 : cos_r <= cos_table [ 399 : 392 ]; - 6'd50 : cos_r <= cos_table [ 407 : 400 ]; - 6'd51 : cos_r <= cos_table [ 415 : 408 ]; - 6'd52 : cos_r <= cos_table [ 423 : 416 ]; - 6'd53 : cos_r <= cos_table [ 431 : 424 ]; - 6'd54 : cos_r <= cos_table [ 439 : 432 ]; - 6'd55 : cos_r <= cos_table [ 447 : 440 ]; - 6'd56 : cos_r <= cos_table [ 455 : 448 ]; - 6'd57 : cos_r <= cos_table [ 463 : 456 ]; - 6'd58 : cos_r <= cos_table [ 471 : 464 ]; - 6'd59 : cos_r <= cos_table [ 479 : 472 ]; - 6'd60 : cos_r <= cos_table [ 487 : 480 ]; - 6'd61 : cos_r <= cos_table [ 495 : 488 ]; - 6'd62 : cos_r <= cos_table [ 503 : 496 ]; - default : cos_r <= cos_table [ 511 : 504 ]; + 1'd0: cos_r <= 255; + 1'd1: cos_r <= 255; + 2'd2: cos_r <= 255; + 2'd3: cos_r <= 254; + 3'd4: cos_r <= 254; + 3'd5: cos_r <= 253; + 3'd6: cos_r <= 252; + 3'd7: cos_r <= 251; + 4'd8: cos_r <= 250; + 4'd9: cos_r <= 249; + 4'd10: cos_r <= 247; + 4'd11: cos_r <= 246; + 4'd12: cos_r <= 244; + 4'd13: cos_r <= 242; + 4'd14: cos_r <= 240; + 4'd15: cos_r <= 238; + 5'd16: cos_r <= 236; + 5'd17: cos_r <= 233; + 5'd18: cos_r <= 231; + 5'd19: cos_r <= 228; + 5'd20: cos_r <= 225; + 5'd21: cos_r <= 222; + 5'd22: cos_r <= 219; + 5'd23: cos_r <= 215; + 5'd24: cos_r <= 212; + 5'd25: cos_r <= 208; + 5'd26: cos_r <= 205; + 5'd27: cos_r <= 201; + 5'd28: cos_r <= 197; + 5'd29: cos_r <= 193; + 5'd30: cos_r <= 189; + 5'd31: cos_r <= 185; + 6'd32: cos_r <= 180; + 6'd33: cos_r <= 176; + 6'd34: cos_r <= 171; + 6'd35: cos_r <= 167; + 6'd36: cos_r <= 162; + 6'd37: cos_r <= 157; + 6'd38: cos_r <= 152; + 6'd39: cos_r <= 147; + 6'd40: cos_r <= 142; + 6'd41: cos_r <= 136; + 6'd42: cos_r <= 131; + 6'd43: cos_r <= 126; + 6'd44: cos_r <= 120; + 6'd45: cos_r <= 115; + 6'd46: cos_r <= 109; + 6'd47: cos_r <= 103; + 6'd48: cos_r <= 98; + 6'd49: cos_r <= 92; + 6'd50: cos_r <= 86; + 6'd51: cos_r <= 80; + 6'd52: cos_r <= 74; + 6'd53: cos_r <= 68; + 6'd54: cos_r <= 62; + 6'd55: cos_r <= 56; + 6'd56: cos_r <= 50; + 6'd57: cos_r <= 44; + 6'd58: cos_r <= 37; + 6'd59: cos_r <= 31; + 6'd60: cos_r <= 25; + 6'd61: cos_r <= 19; + 6'd62: cos_r <= 13; + default: cos_r <= 6; endcase - -/* - initial begin - cos_table[0] = 8'd255; - cos_table[1] = 8'd255; - cos_table[2] = 8'd255; - cos_table[3] = 8'd254; - cos_table[4] = 8'd254; - cos_table[5] = 8'd253; - cos_table[6] = 8'd252; - cos_table[7] = 8'd251; - cos_table[8] = 8'd250; - cos_table[9] = 8'd249; - cos_table[10] = 8'd247; - cos_table[11] = 8'd246; - cos_table[12] = 8'd244; - cos_table[13] = 8'd242; - cos_table[14] = 8'd240; - cos_table[15] = 8'd238; - cos_table[16] = 8'd236; - cos_table[17] = 8'd233; - cos_table[18] = 8'd231; - cos_table[19] = 8'd228; - cos_table[20] = 8'd225; - cos_table[21] = 8'd222; - cos_table[22] = 8'd219; - cos_table[23] = 8'd215; - cos_table[24] = 8'd212; - cos_table[25] = 8'd208; - cos_table[26] = 8'd205; - cos_table[27] = 8'd201; - cos_table[28] = 8'd197; - cos_table[29] = 8'd193; - cos_table[30] = 8'd189; - cos_table[31] = 8'd185; - cos_table[32] = 8'd180; - cos_table[33] = 8'd176; - cos_table[34] = 8'd171; - cos_table[35] = 8'd167; - cos_table[36] = 8'd162; - cos_table[37] = 8'd157; - cos_table[38] = 8'd152; - cos_table[39] = 8'd147; - cos_table[40] = 8'd142; - cos_table[41] = 8'd136; - cos_table[42] = 8'd131; - cos_table[43] = 8'd126; - cos_table[44] = 8'd120; - cos_table[45] = 8'd115; - cos_table[46] = 8'd109; - cos_table[47] = 8'd103; - cos_table[48] = 8'd98; - cos_table[49] = 8'd92; - cos_table[50] = 8'd86; - cos_table[51] = 8'd80; - cos_table[52] = 8'd74; - cos_table[53] = 8'd68; - cos_table[54] = 8'd62; - cos_table[55] = 8'd56; - cos_table[56] = 8'd50; - cos_table[57] = 8'd44; - cos_table[58] = 8'd37; - cos_table[59] = 8'd31; - cos_table[60] = 8'd25; - cos_table[61] = 8'd19; - cos_table[62] = 8'd13; - cos_table[63] = 8'd6; - end - */ endmodule diff --git a/src/microstepper/microstepper_top.v b/src/microstepper/microstepper_top.v index e2438aa..7f33371 100644 --- a/src/microstepper/microstepper_top.v +++ b/src/microstepper/microstepper_top.v @@ -17,7 +17,7 @@ module microstepper_top ( input [7:0] config_chargepump_period, input config_invert_highside, input config_invert_lowside, - input [511:0] cos_table, + //input [511:0] cos_table, input step, input dir, input enable @@ -180,13 +180,13 @@ end cosine cosine0 ( .cos_index(cos_index1), .cos_value(pwm1), - .cos_table(cos_table) + //.cos_table(cos_table) ); cosine cosine1 ( .cos_index(cos_index2), .cos_value(pwm2), - .cos_table(cos_table) + //.cos_table(cos_table) ); analog_out ao0 ( From bb48062a3c946c96c465e8243d79316281851867 Mon Sep 17 00:00:00 2001 From: johnnyr Date: Tue, 1 Dec 2020 01:41:35 -0600 Subject: [PATCH 40/71] preset params for mytimers --- src/microstepper/microstepper_top.v | 12 ++++++------ src/microstepper/mytimer_10.v | 29 +++++++++++++++++++++++++++++ src/microstepper/mytimer_8.v | 29 +++++++++++++++++++++++++++++ 3 files changed, 64 insertions(+), 6 deletions(-) create mode 100644 src/microstepper/mytimer_10.v create mode 100644 src/microstepper/mytimer_8.v diff --git a/src/microstepper/microstepper_top.v b/src/microstepper/microstepper_top.v index 7f33371..5df12af 100644 --- a/src/microstepper/microstepper_top.v +++ b/src/microstepper/microstepper_top.v @@ -103,7 +103,7 @@ end s4r <= {s4r[0], s4}; end - mytimer #( + mytimer_10 #( .WIDTH(10) ) offtimer0 ( .clk (clk), @@ -113,7 +113,7 @@ end .timer (off_timer0) ); - mytimer #( + mytimer_10 #( .WIDTH(10) ) offtimer1 ( .clk (clk), @@ -123,7 +123,7 @@ end .timer (off_timer1) ); - mytimer #( + mytimer_8 #( .WIDTH(8) ) blanktimer0 ( .clk (clk), @@ -133,7 +133,7 @@ end .timer (blank_timer0) ); - mytimer #( + mytimer_8 #( .WIDTH(8) ) blanktimer1 ( .clk (clk), @@ -143,7 +143,7 @@ end .timer (blank_timer1) ); - mytimer #( + mytimer_8 #( .WIDTH(8) ) minimumontimer0 ( .clk (clk), @@ -153,7 +153,7 @@ end .timer (minimum_on_timer0) ); - mytimer #( + mytimer_8 #( .WIDTH(8) ) minimumontimer1 ( .clk (clk), diff --git a/src/microstepper/mytimer_10.v b/src/microstepper/mytimer_10.v new file mode 100644 index 0000000..6648329 --- /dev/null +++ b/src/microstepper/mytimer_10.v @@ -0,0 +1,29 @@ +module mytimer_10 ( + clk, + resetn, + start_enable, + start_time, + timer +); + parameter WIDTH = 10; + + input clk; + input resetn; + input start_enable; + input [WIDTH-1:0] start_time; + output [WIDTH-1:0] timer; + + reg [WIDTH-1:0] counter; + + assign timer = counter; + + always @(posedge clk) begin + if (!resetn) + counter <= 0; + else if( start_enable ) + counter <= start_time; + else if( counter > 0 ) + counter <= counter - 1'b1; +end + +endmodule diff --git a/src/microstepper/mytimer_8.v b/src/microstepper/mytimer_8.v new file mode 100644 index 0000000..1710bab --- /dev/null +++ b/src/microstepper/mytimer_8.v @@ -0,0 +1,29 @@ +module mytimer_8 ( + clk, + resetn, + start_enable, + start_time, + timer +); + parameter WIDTH = 8; + + input clk; + input resetn; + input start_enable; + input [WIDTH-1:0] start_time; + output [WIDTH-1:0] timer; + + reg [WIDTH-1:0] counter; + + assign timer = counter; + + always @(posedge clk) begin + if (!resetn) + counter <= 0; + else if( start_enable ) + counter <= start_time; + else if( counter > 0 ) + counter <= counter - 1'b1; +end + +endmodule From 75412b58bf87fb43e69001217c7d027cdb2f7121 Mon Sep 17 00:00:00 2001 From: johnnyr Date: Tue, 1 Dec 2020 18:28:01 -0600 Subject: [PATCH 41/71] mscontrol --- src/microstepper/microstepper_control.v | 105 +++++++++++++++++++ src/microstepper/microstepper_top.v | 129 ++++++++---------------- 2 files changed, 147 insertions(+), 87 deletions(-) create mode 100644 src/microstepper/microstepper_control.v diff --git a/src/microstepper/microstepper_control.v b/src/microstepper/microstepper_control.v new file mode 100644 index 0000000..68e9c04 --- /dev/null +++ b/src/microstepper/microstepper_control.v @@ -0,0 +1,105 @@ +module microstepper_control ( + input clk, + output [3:0] s_l, + output [3:0] s_h, + input [9:0] config_fastdecay_threshold, + input config_invert_highside, + input config_invert_lowside, + input step, + input dir, + input enable, + input analog_cmp1, + input analog_cmp2, + output fault, + input s1, + input s2, + input s3, + input s4, + output offtimer_en0, + output offtimer_en0, + output a_starting, + output b_starting, + output [7:0] phase_ct, + input [7:0] blank_timer0, + input [7:0] blank_timer1, + input [9:0] off_timer0, + input [9:0] off_timer1, + input [7:0] minimum_on_timer0, + input [7:0] minimum_on_timer1, +); + reg [7:0] phase_ct; + + always @(posedge step) begin + phase_ct <= phase_ct + (dir ? 1 : -1); + end + + wire s1; + wire s2; + wire s3; + wire s4; + + wire overCurrent0 = off_timer0 > 0; + wire overCurrent1 = off_timer1 > 0; + + wire fastDecay0 = off_timer0 >= config_fastdecay_threshold; + wire fastDecay1 = off_timer1 >= config_fastdecay_threshold; + + wire slowDecay0 = overCurrent0 && fastDecay0 == 0; + wire slowDecay1 = overCurrent1 && fastDecay1 == 0; + + wire fault0 = (minimum_on_timer0 > 0) && overCurrent0; + wire fault1 = (minimum_on_timer1 > 0) && overCurrent1; + wire fault = fault0 | fault1; + + reg [1:0] s1r, s2r, s3r, s4r; + wire phase_a1_h, phase_a1_l, phase_a2_h, phase_a2_l; + wire phase_b1_h, phase_b1_l, phase_b2_h, phase_b2_l; + + assign s_l[0] = !(phase_a1_l | fault); + assign s_l[1] = !(phase_a2_l | fault); + assign s_l[2] = !(phase_b1_l | fault); + assign s_l[3] = !(phase_b2_l | fault); + + assign s_h[0] = !(phase_a1_h | fault); + assign s_h[1] = !(phase_a2_h | fault); + assign s_h[2] = !(phase_b1_h | fault); + assign s_h[3] = !(phase_b2_h | fault); + + assign phase_a1_h = config_invert_highside ^ (slowDecay0 | (fastDecay0 ? s1r[1] : ~s1r[1])); + assign phase_a1_l = config_invert_lowside ^ (fastDecay0 ? ~s1r[1] : (slowDecay0 ? 1'b0 : s1r[1])); + assign phase_a2_h = config_invert_highside ^ (slowDecay0 | (fastDecay0 ? s2r[1] : ~s2r[1])); + assign phase_a2_l = config_invert_lowside ^ (fastDecay0 ? ~s2r[1] : (slowDecay0 ? 1'b0 : s2r[1])); + + assign phase_b1_h = config_invert_highside ^ (slowDecay1 | (fastDecay1 ? s3r[1] : ~s3r[1])); + assign phase_b1_l = config_invert_lowside ^ (fastDecay1 ? ~s3r[1] : (slowDecay1 ? 1'b0 : s3r[1])); + assign phase_b2_h = config_invert_highside ^ (slowDecay1 | (fastDecay1 ? s4r[1] : ~s4r[1])); + assign phase_b2_l = config_invert_lowside ^ (fastDecay1 ? ~s4r[1] : (slowDecay1 ? 1'b0 : s4r[1])); + + + wire s1_starting = s1r == 2'b10; + wire s2_starting = s2r == 2'b10; + wire s3_starting = s3r == 2'b10; + wire s4_starting = s4r == 2'b10; + + assign offtimer_en0 = analog_cmp1 & blank_timer0 == 0 & overCurrent0 == 0; + assign offtimer_en0 = analog_cmp2 & blank_timer1 == 0 & overCurrent1 == 0; + assign a_starting = s1_starting | s2_starting; + assign b_starting = s3_starting | s4_starting; + +`ifdef FORMAL + always @(*) begin + assert (!(phase_a1_l == 0 && phase_a1_h == 0)); + assert (!(phase_a2_l == 0 && phase_a2_h == 0)); + assert (!(phase_b1_l == 0 && phase_b1_h == 0)); + assert (!(phase_b2_l == 0 && phase_b2_h == 0)); + end +`endif + + always @(posedge clk) begin + s1r <= {s1r[0], s1}; + s2r <= {s2r[0], s2}; + s3r <= {s3r[0], s3}; + s4r <= {s4r[0], s4}; + end + +endmodule \ No newline at end of file diff --git a/src/microstepper/microstepper_top.v b/src/microstepper/microstepper_top.v index 5df12af..f9df678 100644 --- a/src/microstepper/microstepper_top.v +++ b/src/microstepper/microstepper_top.v @@ -20,95 +20,50 @@ module microstepper_top ( //input [511:0] cos_table, input step, input dir, - input enable + input enable, + output fault, +); + wire [5:0] cos_index1; + wire [5:0] cos_index2; + wire [7:0] pwm1; + wire [7:0] pwm2; + + microstepper_control m_control_0( + .clk(clk), + .s_l(s_l), + .s_h(s_h), + .config_fastdecay_threshold(config_fastdecay_threshold), + .config_invert_highside(config_invert_highside), + .config_invert_lowside(config_invert_lowside), + .step(step), + .dir(dir), + .enable(enable), + .analog_cmp1(analog_cmp1), + .analog_cmp2(analog_cmp2), + .fault(fault), + .s1(s1), + .s2(s2), + .s3(s3), + .s4(s4), + .offtimer_en0(offtimer_en0), + .offtimer_en0(offtimer_en0), + .a_starting(a_starting), + .b_starting(b_starting), + .phase_ct(phase_ct), + .blank_timer0(blank_timer0), + .blank_timer1(blank_timer1), + .off_timer0(off_timer0), + .off_timer1(off_timer1), + .minimum_on_timer0(minimum_on_timer0), + .minimum_on_timer1(minimum_on_timer1), ); - - reg [7:0] phase_ct; - - always @(posedge step) begin - phase_ct <= phase_ct + (dir ? 1 : -1); -end - - wire [5:0] cos_index1; - wire [5:0] cos_index2; - wire s1; - wire s2; - wire s3; - wire s4; - wire [7:0] pwm1; - wire [7:0] pwm2; - - reg [7:0] blank_timer0; - reg [7:0] blank_timer1; - reg [9:0] off_timer0; - reg [9:0] off_timer1; - reg [7:0] minimum_on_timer0; - reg [7:0] minimum_on_timer1; - - wire overCurrent0 = off_timer0 > 0; - wire overCurrent1 = off_timer1 > 0; - - wire fastDecay0 = off_timer0 >= config_fastdecay_threshold; - wire fastDecay1 = off_timer1 >= config_fastdecay_threshold; - - wire slowDecay0 = overCurrent0 && fastDecay0 == 0; - wire slowDecay1 = overCurrent1 && fastDecay1 == 0; - - wire fault0 = (minimum_on_timer0 > 0) && overCurrent0; - wire fault1 = (minimum_on_timer1 > 0) && overCurrent1; - wire fault = fault0 | fault1; - - reg [1:0] s1r, s2r, s3r, s4r; - wire phase_a1_h, phase_a1_l, phase_a2_h, phase_a2_l; - wire phase_b1_h, phase_b1_l, phase_b2_h, phase_b2_l; - - assign s_l[0] = !(phase_a1_l | fault); - assign s_l[1] = !(phase_a2_l | fault); - assign s_l[2] = !(phase_b1_l | fault); - assign s_l[3] = !(phase_b2_l | fault); - - assign s_h[0] = !(phase_a1_h | fault); - assign s_h[1] = !(phase_a2_h | fault); - assign s_h[2] = !(phase_b1_h | fault); - assign s_h[3] = !(phase_b2_h | fault); - - assign phase_a1_h = config_invert_highside ^ (slowDecay0 | (fastDecay0 ? s1r[1] : ~s1r[1])); - assign phase_a1_l = config_invert_lowside ^ (fastDecay0 ? ~s1r[1] : (slowDecay0 ? 1'b0 : s1r[1])); - assign phase_a2_h = config_invert_highside ^ (slowDecay0 | (fastDecay0 ? s2r[1] : ~s2r[1])); - assign phase_a2_l = config_invert_lowside ^ (fastDecay0 ? ~s2r[1] : (slowDecay0 ? 1'b0 : s2r[1])); - - assign phase_b1_h = config_invert_highside ^ (slowDecay1 | (fastDecay1 ? s3r[1] : ~s3r[1])); - assign phase_b1_l = config_invert_lowside ^ (fastDecay1 ? ~s3r[1] : (slowDecay1 ? 1'b0 : s3r[1])); - assign phase_b2_h = config_invert_highside ^ (slowDecay1 | (fastDecay1 ? s4r[1] : ~s4r[1])); - assign phase_b2_l = config_invert_lowside ^ (fastDecay1 ? ~s4r[1] : (slowDecay1 ? 1'b0 : s4r[1])); - - wire s1_starting = s1r == 2'b10; - wire s2_starting = s2r == 2'b10; - wire s3_starting = s3r == 2'b10; - wire s4_starting = s4r == 2'b10; - -`ifdef FORMAL - always @(*) begin - assert (!(phase_a1_l == 0 && phase_a1_h == 0)); - assert (!(phase_a2_l == 0 && phase_a2_h == 0)); - assert (!(phase_b1_l == 0 && phase_b1_h == 0)); - assert (!(phase_b2_l == 0 && phase_b2_h == 0)); - end -`endif - - always @(posedge clk) begin - s1r <= {s1r[0], s1}; - s2r <= {s2r[0], s2}; - s3r <= {s3r[0], s3}; - s4r <= {s4r[0], s4}; - end mytimer_10 #( .WIDTH(10) ) offtimer0 ( .clk (clk), .resetn (resetn), - .start_enable(analog_cmp1 & blank_timer0 == 0 & overCurrent0 == 0), + .start_enable(offtimer_en0), .start_time (config_offtime), .timer (off_timer0) ); @@ -118,7 +73,7 @@ end ) offtimer1 ( .clk (clk), .resetn (resetn), - .start_enable(analog_cmp2 & blank_timer1 == 0 & overCurrent1 == 0), + .start_enable(offtimer_en1), .start_time (config_offtime), .timer (off_timer1) ); @@ -128,7 +83,7 @@ end ) blanktimer0 ( .clk (clk), .resetn (resetn), - .start_enable(s1_starting | s2_starting), + .start_enable(a_starting), .start_time (config_blanktime), .timer (blank_timer0) ); @@ -138,7 +93,7 @@ end ) blanktimer1 ( .clk (clk), .resetn (resetn), - .start_enable(s3_starting | s4_starting), + .start_enable(b_starting), .start_time (config_blanktime), .timer (blank_timer1) ); @@ -148,7 +103,7 @@ end ) minimumontimer0 ( .clk (clk), .resetn (resetn), - .start_enable(s1_starting | s2_starting), + .start_enable(a_starting), .start_time (config_minimum_on_time), .timer (minimum_on_timer0) ); @@ -158,7 +113,7 @@ end ) minimumontimer1 ( .clk (clk), .resetn (resetn), - .start_enable(s3_starting | s4_starting), + .start_enable(b_starting), .start_time (config_minimum_on_time), .timer (minimum_on_timer1) ); From 2806f4407ca78fde4d20fc8de2a45830ae28b50c Mon Sep 17 00:00:00 2001 From: Tonokip Date: Tue, 1 Dec 2020 20:03:15 -0600 Subject: [PATCH 42/71] reuse mytimer for mytimer_8 and mytimer_10 --- src/microstepper/mytimer_10.v | 28 +++++++++------------------- src/microstepper/mytimer_8.v | 28 +++++++++------------------- 2 files changed, 18 insertions(+), 38 deletions(-) diff --git a/src/microstepper/mytimer_10.v b/src/microstepper/mytimer_10.v index 6648329..93a73ad 100644 --- a/src/microstepper/mytimer_10.v +++ b/src/microstepper/mytimer_10.v @@ -5,25 +5,15 @@ module mytimer_10 ( start_time, timer ); - parameter WIDTH = 10; - input clk; - input resetn; - input start_enable; - input [WIDTH-1:0] start_time; - output [WIDTH-1:0] timer; - - reg [WIDTH-1:0] counter; - - assign timer = counter; - - always @(posedge clk) begin - if (!resetn) - counter <= 0; - else if( start_enable ) - counter <= start_time; - else if( counter > 0 ) - counter <= counter - 1'b1; -end + mytimer #( + .WIDTH(8) + ) mytimer8 ( + .clk (clk), + .resetn (resetn), + .start_enable(start_enable), + .start_time (start_time), + .timer (timer) + ); endmodule diff --git a/src/microstepper/mytimer_8.v b/src/microstepper/mytimer_8.v index 1710bab..c61be86 100644 --- a/src/microstepper/mytimer_8.v +++ b/src/microstepper/mytimer_8.v @@ -5,25 +5,15 @@ module mytimer_8 ( start_time, timer ); - parameter WIDTH = 8; - input clk; - input resetn; - input start_enable; - input [WIDTH-1:0] start_time; - output [WIDTH-1:0] timer; - - reg [WIDTH-1:0] counter; - - assign timer = counter; - - always @(posedge clk) begin - if (!resetn) - counter <= 0; - else if( start_enable ) - counter <= start_time; - else if( counter > 0 ) - counter <= counter - 1'b1; -end + mytimer #( + .WIDTH(8) + ) mytimer8 ( + .clk (clk), + .resetn (resetn), + .start_enable(start_enable), + .start_time (start_time), + .timer (timer) + ); endmodule From f46d9ab0ba4262d91648490d86fbffa5b63ea3dd Mon Sep 17 00:00:00 2001 From: Tonokip Date: Tue, 1 Dec 2020 20:42:40 -0600 Subject: [PATCH 43/71] timer fixes and missing wires --- src/microstepper/microstepper_control.v | 6 ++-- src/microstepper/microstepper_top.v | 38 ++++++++++++------------- src/microstepper/mytimer_10.v | 11 +++++-- src/microstepper/mytimer_8.v | 9 +++++- 4 files changed, 39 insertions(+), 25 deletions(-) diff --git a/src/microstepper/microstepper_control.v b/src/microstepper/microstepper_control.v index 68e9c04..17e0576 100644 --- a/src/microstepper/microstepper_control.v +++ b/src/microstepper/microstepper_control.v @@ -16,7 +16,7 @@ module microstepper_control ( input s3, input s4, output offtimer_en0, - output offtimer_en0, + output offtimer_en1, output a_starting, output b_starting, output [7:0] phase_ct, @@ -82,7 +82,7 @@ module microstepper_control ( wire s4_starting = s4r == 2'b10; assign offtimer_en0 = analog_cmp1 & blank_timer0 == 0 & overCurrent0 == 0; - assign offtimer_en0 = analog_cmp2 & blank_timer1 == 0 & overCurrent1 == 0; + assign offtimer_en1 = analog_cmp2 & blank_timer1 == 0 & overCurrent1 == 0; assign a_starting = s1_starting | s2_starting; assign b_starting = s3_starting | s4_starting; @@ -102,4 +102,4 @@ module microstepper_control ( s4r <= {s4r[0], s4}; end -endmodule \ No newline at end of file +endmodule diff --git a/src/microstepper/microstepper_top.v b/src/microstepper/microstepper_top.v index f9df678..c6e92e5 100644 --- a/src/microstepper/microstepper_top.v +++ b/src/microstepper/microstepper_top.v @@ -27,6 +27,18 @@ module microstepper_top ( wire [5:0] cos_index2; wire [7:0] pwm1; wire [7:0] pwm2; + + wire s1, s2, s3, s4; + wire offtimer_en0, offtimer_en1; + + wire a_starting, b_starting; + wire [7:0] phase_ct; + wire [7:0] blank_timer0; + wire [7:0] blank_timer1; + wire [9:0] off_timer0; + wire [9:0] off_timer1; + wire [7:0] minimum_on_timer0; + wire [7:0] minimum_on_timer1; microstepper_control m_control_0( .clk(clk), @@ -46,7 +58,7 @@ module microstepper_top ( .s3(s3), .s4(s4), .offtimer_en0(offtimer_en0), - .offtimer_en0(offtimer_en0), + .offtimer_en1(offtimer_en1), .a_starting(a_starting), .b_starting(b_starting), .phase_ct(phase_ct), @@ -58,9 +70,7 @@ module microstepper_top ( .minimum_on_timer1(minimum_on_timer1), ); - mytimer_10 #( - .WIDTH(10) - ) offtimer0 ( + mytimer_10 offtimer0 ( .clk (clk), .resetn (resetn), .start_enable(offtimer_en0), @@ -68,9 +78,7 @@ module microstepper_top ( .timer (off_timer0) ); - mytimer_10 #( - .WIDTH(10) - ) offtimer1 ( + mytimer_10 offtimer1 ( .clk (clk), .resetn (resetn), .start_enable(offtimer_en1), @@ -78,9 +86,7 @@ module microstepper_top ( .timer (off_timer1) ); - mytimer_8 #( - .WIDTH(8) - ) blanktimer0 ( + mytimer_8 blanktimer0 ( .clk (clk), .resetn (resetn), .start_enable(a_starting), @@ -88,9 +94,7 @@ module microstepper_top ( .timer (blank_timer0) ); - mytimer_8 #( - .WIDTH(8) - ) blanktimer1 ( + mytimer_8 blanktimer1 ( .clk (clk), .resetn (resetn), .start_enable(b_starting), @@ -98,9 +102,7 @@ module microstepper_top ( .timer (blank_timer1) ); - mytimer_8 #( - .WIDTH(8) - ) minimumontimer0 ( + mytimer_8 minimumontimer0 ( .clk (clk), .resetn (resetn), .start_enable(a_starting), @@ -108,9 +110,7 @@ module microstepper_top ( .timer (minimum_on_timer0) ); - mytimer_8 #( - .WIDTH(8) - ) minimumontimer1 ( + mytimer_8 minimumontimer1 ( .clk (clk), .resetn (resetn), .start_enable(b_starting), diff --git a/src/microstepper/mytimer_10.v b/src/microstepper/mytimer_10.v index 93a73ad..5ce98e4 100644 --- a/src/microstepper/mytimer_10.v +++ b/src/microstepper/mytimer_10.v @@ -5,10 +5,17 @@ module mytimer_10 ( start_time, timer ); + localparam WIDTH = 10; + + input clk; + input resetn; + input start_enable; + input [WIDTH-1:0] start_time; + output [WIDTH-1:0] timer; mytimer #( - .WIDTH(8) - ) mytimer8 ( + .WIDTH(WIDTH) + ) mytimer10 ( .clk (clk), .resetn (resetn), .start_enable(start_enable), diff --git a/src/microstepper/mytimer_8.v b/src/microstepper/mytimer_8.v index c61be86..38f495d 100644 --- a/src/microstepper/mytimer_8.v +++ b/src/microstepper/mytimer_8.v @@ -5,9 +5,16 @@ module mytimer_8 ( start_time, timer ); + localparam WIDTH = 8; + + input clk; + input resetn; + input start_enable; + input [WIDTH-1:0] start_time; + output [WIDTH-1:0] timer; mytimer #( - .WIDTH(8) + .WIDTH(WIDTH) ) mytimer8 ( .clk (clk), .resetn (resetn), From b7c9a129f474f855baee6ef530658eb1f7a0bc0e Mon Sep 17 00:00:00 2001 From: johnnyr Date: Fri, 4 Dec 2020 01:27:35 -0600 Subject: [PATCH 44/71] testbench upgrades. part 1 --- Makefile | 6 +- sim_microstepper.ys | 14 ++++ testbench/coil.v | 30 ++++++++ testbench/microstepper_tb.v | 133 ++++++++++++++++++++++++++++++++++++ testbench/pwm_duty.v | 40 +++++++++++ testbench/quad_tb.v | 2 +- 6 files changed, 223 insertions(+), 2 deletions(-) create mode 100644 sim_microstepper.ys create mode 100644 testbench/coil.v create mode 100644 testbench/microstepper_tb.v create mode 100644 testbench/pwm_duty.v diff --git a/Makefile b/Makefile index 9fd8dc6..f3d4a4f 100755 --- a/Makefile +++ b/Makefile @@ -57,8 +57,12 @@ formal: lint: verible-verilog-lint src/*.v -testbench: +testbench_quad_encoder: yosys sim.ys + gtkwave testbench/quad_enc.vcd +testbench_microstepper: + yosys sim_microstepper.ys + gtkwave testbench/microstepper.vcd .SECONDARY: .PHONY: all prog clean testbench formal diff --git a/sim_microstepper.ys b/sim_microstepper.ys new file mode 100644 index 0000000..3d86003 --- /dev/null +++ b/sim_microstepper.ys @@ -0,0 +1,14 @@ + +read_verilog -sv testbench/microstepper_tb.v \ + src/microstepper/analog_out.v \ + src/microstepper/chargepump.v \ + src/microstepper/cosine.v \ + src/microstepper/microstep_counter.v \ + src/microstepper/microstepper_control.v \ + src/microstepper/mytimer_8.v \ + src/microstepper/mytimer_10.v \ + src/microstepper/mytimer.v + +prep -top testbench +show microstepper_top +sim -n 40000 -clock clk -vcd testbench/microstepper.vcd diff --git a/testbench/coil.v b/testbench/coil.v new file mode 100644 index 0000000..3a2c1ce --- /dev/null +++ b/testbench/coil.v @@ -0,0 +1,30 @@ +// Linear current ramp +module coil ( + input clk, + input resetn, + input s_l1, + input s_h1, + input s_l2, + input s_h2, + output [12:0] current, +); + reg [12:0] current; + reg [7:0] cnt; + + wire on = (s_l1 && s_h2) | (s_l1 && s_h2); + + always @(posedge clk) begin + if (!resetn) begin + current <= 0; + end + else begin + if ( on ) begin + current <= current + 1; + end + else begin + current <= 0; + end + end + end +endmodule +//(cnt[2]== 1) \ No newline at end of file diff --git a/testbench/microstepper_tb.v b/testbench/microstepper_tb.v new file mode 100644 index 0000000..4c54dba --- /dev/null +++ b/testbench/microstepper_tb.v @@ -0,0 +1,133 @@ +`include "../src/microstepper/microstepper_top.v" +`include "coil.v" +`include "pwm_duty.v" +`timescale 1ns/100ps + +module testbench( + input clk, + output [3:0] s_l, + output [3:0] s_h, + output analog_cmp1, + output analog_out1, + output analog_cmp2, + output analog_out2, + output chargepump_pin, + output fault, + output [7:0] target_current1, +); + + reg step; + reg dir; + reg enable; + reg [7:0] target_current1; + reg [7:0] target_current2; + reg [7:0] current1; + reg [7:0] current2; + reg [9:0] config_offtime; + reg [7:0] config_blanktime; + reg [9:0] config_fastdecay_threshold; + reg [7:0] config_minimum_on_time; + reg [10:0] config_current_threshold; + reg [7:0] config_chargepump_period; + reg config_invert_highside; + reg config_invert_lowside; + + wire resetn; + reg [7:0] resetn_counter = 0; + + assign resetn = &resetn_counter; + always @(posedge clk) begin + if (!resetn) resetn_counter <= resetn_counter +1; + end + + reg analog_cmp1; + reg analog_cmp2; + reg [40:0] step_clock; + reg [20:0] cnt; + always @(posedge clk) begin + if (!resetn) begin + cnt <= 0; + analog_cmp1 <= 0; + analog_cmp2 <= 0; + step <= 1; + enable <= 1; + config_offtime = 810; + config_blanktime = 27; + config_fastdecay_threshold = 706; + config_minimum_on_time = 54; + config_current_threshold = 1024; + config_chargepump_period = 91; + config_invert_highside = 0; + config_invert_lowside = 0; + step_clock = 0; + end + else begin + cnt <= cnt + 1; + step_clock <= step_clock + 1; + step <= step_clock[9]; + if (current1 > target_current1) analog_cmp1 <= 1; + if (current2 > target_current2) analog_cmp2 <= 1; + if (cnt <= 20'hAEC) begin + dir <= 1; + end + else if (cnt <= 20'hEBE) begin + dir <= 0; + end + end + end + + microstepper_top stepper( + .resetn( resetn ), + .clk( clk ), + .fault( fault ), + .s_l( s_l ), + .s_h( s_h ), + .analog_cmp1( analog_cmp1 ), + .analog_out1( analog_out1 ), + .analog_cmp2( analog_cmp2 ), + .analog_out2( analog_out2 ), + .chargepump_pin( chargepump_pin ), + .step( step ), + .dir( dir ), + .enable( enable ), + .config_offtime( config_offtime ), + .config_blanktime( config_blanktime ), + .config_fastdecay_threshold( config_fastdecay_threshold ), + .config_minimum_on_time( config_minimum_on_time ), + .config_current_threshold( config_current_threshold ), + .config_chargepump_period( config_chargepump_period ), + .config_invert_highside( config_invert_highside ), + .config_invert_lowside( config_invert_lowside ), + ); + pwm_duty duty1( + .clk(clk), + .resetn(resetn), + .pwm(analog_out1), + .duty(target_current1) + ); + pwm_duty duty2( + .clk(clk), + .resetn(resetn), + .pwm(analog_out2), + .duty(target_current2) + ); + coil coil1( + .clk(clk), + .resetn(resetn), + .s_l1(s_l[0]), + .s_l2(s_l[1]), + .s_h1(s_h[0]), + .s_h2(s_h[1]), + .current(current1) + ); + coil coil2( + .clk(clk), + .resetn(resetn), + .s_l1(s_l[2]), + .s_l2(s_l[3]), + .s_h1(s_h[2]), + .s_h2(s_h[3]), + .current(current2) + ); +endmodule + diff --git a/testbench/pwm_duty.v b/testbench/pwm_duty.v new file mode 100644 index 0000000..ae8e245 --- /dev/null +++ b/testbench/pwm_duty.v @@ -0,0 +1,40 @@ +// Calculate PWM Duty - cycle by cycle +module pwm_duty( + input clk, + input pwm, + input resetn, + output [12:0] duty, + ); + reg [1:0] edge_b; + reg [11:0] cnt_h; + reg [11:0] cnt_l; + wire tc_edge = edge_b[1] ^ edge_b[0]; + wire pwm; + + reg [12:0] duty; + + always @(posedge clk) begin + if (!resetn) begin + cnt_h <= 0; + cnt_l <= 0; + duty <= 0; + end + else begin + if (tc_edge && edge_b[0]) begin // Rising edge + duty <= ( 255 * cnt_h / (cnt_h + cnt_l) ); + cnt_h <= 0; + cnt_l <= 0; + end + else begin + if (edge_b[1]) begin + cnt_h <= cnt_h + 1; + end + else if (!edge_b[1]) begin + cnt_l <= cnt_l + 1; + end + end + end + edge_b = {edge_b[0], pwm}; + end + +endmodule diff --git a/testbench/quad_tb.v b/testbench/quad_tb.v index 95f7eef..da85005 100644 --- a/testbench/quad_tb.v +++ b/testbench/quad_tb.v @@ -74,7 +74,7 @@ module testbench( end faultn <= &fault; cnt <= cnt + 1; - if (cnt <= 20'h90) begin + if (cnt <= 20'h85) begin enccntA <= enccntA + 1; enc1a <= enccntA[3]; enccntB <= enccntB - 1; From 50468a23e49074670f126e524be1996ebc26d7be Mon Sep 17 00:00:00 2001 From: johnnyr Date: Fri, 4 Dec 2020 01:35:29 -0600 Subject: [PATCH 45/71] reset logic for analog out, phase_ct, step dir buffer, instantiation name expansion. --- src/microstepper/analog_out.v | 18 +++++++++++------- src/microstepper/microstepper_control.v | 22 ++++++++++++++++++++-- src/microstepper/microstepper_top.v | 9 +++++---- 3 files changed, 36 insertions(+), 13 deletions(-) diff --git a/src/microstepper/analog_out.v b/src/microstepper/analog_out.v index 3494907..1b55c55 100644 --- a/src/microstepper/analog_out.v +++ b/src/microstepper/analog_out.v @@ -10,13 +10,17 @@ module analog_out ( reg [10:0] pwm_counter; - always @(posedge clk) - if (resetn) - if (pwm_counter <= current_threshold) - pwm_counter <= pwm_counter + 1'b1; - else - pwm_counter <= 0; - + always @(posedge clk) begin + if (!resetn) begin + pwm_counter <= 0; + end + else begin + if (pwm_counter <= current_threshold) + pwm_counter <= pwm_counter + 1'b1; + else + pwm_counter <= 0; + end + end assign analog_out1 = pwm_counter <= pwm1; assign analog_out2 = pwm_counter <= pwm2; diff --git a/src/microstepper/microstepper_control.v b/src/microstepper/microstepper_control.v index 17e0576..653fe34 100644 --- a/src/microstepper/microstepper_control.v +++ b/src/microstepper/microstepper_control.v @@ -1,5 +1,6 @@ module microstepper_control ( input clk, + input resetn, output [3:0] s_l, output [3:0] s_h, input [9:0] config_fastdecay_threshold, @@ -26,11 +27,28 @@ module microstepper_control ( input [9:0] off_timer1, input [7:0] minimum_on_timer0, input [7:0] minimum_on_timer1, +// output step_b_out, ); reg [7:0] phase_ct; +// reg [1:0] step_b; - always @(posedge step) begin - phase_ct <= phase_ct + (dir ? 1 : -1); +// wire step_edge = (step_b[2] ^ step_b[1]) && step_b[2]; + // step edge rising falling + + reg [2:0] step_b; + reg [1:0] dir_b; +// wire step_b_out = step_b[2]; + wire step_rising = (step_b == 2'b01); + + always @(posedge clk) begin + if (!resetn) begin + phase_ct <= 0; + end + else if (step_rising) begin + phase_ct <= phase_ct + dir_b[1]; + end + step_b <= {step_b[1:0], step}; + dir_b <= {dir[0], dir}; end wire s1; diff --git a/src/microstepper/microstepper_top.v b/src/microstepper/microstepper_top.v index c6e92e5..9ddcfb9 100644 --- a/src/microstepper/microstepper_top.v +++ b/src/microstepper/microstepper_top.v @@ -40,8 +40,9 @@ module microstepper_top ( wire [7:0] minimum_on_timer0; wire [7:0] minimum_on_timer1; - microstepper_control m_control_0( + microstepper_control microstepper_control0( .clk(clk), + .resetn(resetn), .s_l(s_l), .s_h(s_h), .config_fastdecay_threshold(config_fastdecay_threshold), @@ -118,14 +119,14 @@ module microstepper_top ( .timer (minimum_on_timer1) ); - chargepump cp0 ( + chargepump chargepump0 ( .clk (clk), .resetn (resetn), .period (config_chargepump_period), .chargepump_pin(chargepump_pin) ); - microstep_counter mc0 ( + microstep_counter microstep_counter0 ( .pos (phase_ct), .cos_index1(cos_index1), .cos_index2(cos_index2), @@ -144,7 +145,7 @@ module microstepper_top ( //.cos_table(cos_table) ); - analog_out ao0 ( + analog_out analog_out0 ( .clk (clk), .resetn (resetn), .pwm1 (pwm1), From ae71dcad2c4579ff0a32b0c9f48a0e833e4d7cb2 Mon Sep 17 00:00:00 2001 From: johnnyr Date: Fri, 4 Dec 2020 19:10:59 -0600 Subject: [PATCH 46/71] testbench debugging --- testbench/coil.v | 7 +++---- testbench/microstepper_tb.v | 24 +++++++++++++----------- testbench/pwm_duty.v | 6 +++--- 3 files changed, 19 insertions(+), 18 deletions(-) diff --git a/testbench/coil.v b/testbench/coil.v index 3a2c1ce..dd8c6fe 100644 --- a/testbench/coil.v +++ b/testbench/coil.v @@ -2,16 +2,15 @@ module coil ( input clk, input resetn, + input s_l0, + input s_h0, input s_l1, input s_h1, - input s_l2, - input s_h2, output [12:0] current, ); reg [12:0] current; - reg [7:0] cnt; - wire on = (s_l1 && s_h2) | (s_l1 && s_h2); + wire on = (s_l0 && s_h1) | (s_l1 && s_h0); always @(posedge clk) begin if (!resetn) begin diff --git a/testbench/microstepper_tb.v b/testbench/microstepper_tb.v index 4c54dba..231556d 100644 --- a/testbench/microstepper_tb.v +++ b/testbench/microstepper_tb.v @@ -64,9 +64,11 @@ module testbench( else begin cnt <= cnt + 1; step_clock <= step_clock + 1; - step <= step_clock[9]; + step <= step_clock[11]; if (current1 > target_current1) analog_cmp1 <= 1; + else analog_cmp1 <= 0; if (current2 > target_current2) analog_cmp2 <= 1; + else analog_cmp2 <= 0; if (cnt <= 20'hAEC) begin dir <= 1; end @@ -111,22 +113,22 @@ module testbench( .pwm(analog_out2), .duty(target_current2) ); - coil coil1( + coil coil2( .clk(clk), .resetn(resetn), - .s_l1(s_l[0]), - .s_l2(s_l[1]), - .s_h1(s_h[0]), - .s_h2(s_h[1]), + .s_l0(s_l[0]), + .s_l1(s_l[1]), + .s_h0(s_h[0]), + .s_h1(s_h[1]), .current(current1) ); - coil coil2( + coil coil1( .clk(clk), .resetn(resetn), - .s_l1(s_l[2]), - .s_l2(s_l[3]), - .s_h1(s_h[2]), - .s_h2(s_h[3]), + .s_l0(s_l[2]), + .s_l1(s_l[3]), + .s_h0(s_h[2]), + .s_h1(s_h[3]), .current(current2) ); endmodule diff --git a/testbench/pwm_duty.v b/testbench/pwm_duty.v index ae8e245..24d0289 100644 --- a/testbench/pwm_duty.v +++ b/testbench/pwm_duty.v @@ -8,7 +8,7 @@ module pwm_duty( reg [1:0] edge_b; reg [11:0] cnt_h; reg [11:0] cnt_l; - wire tc_edge = edge_b[1] ^ edge_b[0]; + wire s_edge = edge_b[1] ^ edge_b[0]; wire pwm; reg [12:0] duty; @@ -20,8 +20,8 @@ module pwm_duty( duty <= 0; end else begin - if (tc_edge && edge_b[0]) begin // Rising edge - duty <= ( 255 * cnt_h / (cnt_h + cnt_l) ); + if (s_edge && edge_b[0]) begin // Rising edge + duty <= 8191 * cnt_h / (cnt_h + cnt_l) ; cnt_h <= 0; cnt_l <= 0; end From edb70a109d813dd4da35926029bd66260465302f Mon Sep 17 00:00:00 2001 From: johnnyr Date: Fri, 4 Dec 2020 19:11:47 -0600 Subject: [PATCH 47/71] tb debug --- sim_microstepper.ys | 2 +- src/microstepper/microstepper_control.v | 17 ++++++++++++++--- src/rapcore.v | 4 ++-- 3 files changed, 17 insertions(+), 6 deletions(-) diff --git a/sim_microstepper.ys b/sim_microstepper.ys index 3d86003..dda1280 100644 --- a/sim_microstepper.ys +++ b/sim_microstepper.ys @@ -11,4 +11,4 @@ read_verilog -sv testbench/microstepper_tb.v \ prep -top testbench show microstepper_top -sim -n 40000 -clock clk -vcd testbench/microstepper.vcd +sim -n 400000 -clock clk -vcd testbench/microstepper.vcd diff --git a/src/microstepper/microstepper_control.v b/src/microstepper/microstepper_control.v index 653fe34..85d75f6 100644 --- a/src/microstepper/microstepper_control.v +++ b/src/microstepper/microstepper_control.v @@ -45,7 +45,7 @@ module microstepper_control ( phase_ct <= 0; end else if (step_rising) begin - phase_ct <= phase_ct + dir_b[1]; + phase_ct <= dir_b[1] ? phase_ct + 1 : phase_ct - 1; end step_b <= {step_b[1:0], step}; dir_b <= {dir[0], dir}; @@ -56,8 +56,9 @@ module microstepper_control ( wire s3; wire s4; + // Off Timer active flag wire overCurrent0 = off_timer0 > 0; - wire overCurrent1 = off_timer1 > 0; + wire overCurrent1 = off_timer1 > 0; wire fastDecay0 = off_timer0 >= config_fastdecay_threshold; wire fastDecay1 = off_timer1 >= config_fastdecay_threshold; @@ -73,11 +74,14 @@ module microstepper_control ( wire phase_a1_h, phase_a1_l, phase_a2_h, phase_a2_l; wire phase_b1_h, phase_b1_l, phase_b2_h, phase_b2_l; + // Switch output Low + assign s_l[0] = !(phase_a1_l | fault); assign s_l[1] = !(phase_a2_l | fault); assign s_l[2] = !(phase_b1_l | fault); assign s_l[3] = !(phase_b2_l | fault); + // Switch output High assign s_h[0] = !(phase_a1_h | fault); assign s_h[1] = !(phase_a2_h | fault); assign s_h[2] = !(phase_b1_h | fault); @@ -93,14 +97,19 @@ module microstepper_control ( assign phase_b2_h = config_invert_highside ^ (slowDecay1 | (fastDecay1 ? s4r[1] : ~s4r[1])); assign phase_b2_l = config_invert_lowside ^ (fastDecay1 ? ~s4r[1] : (slowDecay1 ? 1'b0 : s4r[1])); - + // Start on time per half bridge wire s1_starting = s1r == 2'b10; wire s2_starting = s2r == 2'b10; wire s3_starting = s3r == 2'b10; wire s4_starting = s4r == 2'b10; + // start Off Time + // Target peak current detected. Blank timer and Off timer not active assign offtimer_en0 = analog_cmp1 & blank_timer0 == 0 & overCurrent0 == 0; assign offtimer_en1 = analog_cmp2 & blank_timer1 == 0 & overCurrent1 == 0; + + // Bridge On Time start + // Blank timer and minimum on timer enable assign a_starting = s1_starting | s2_starting; assign b_starting = s3_starting | s4_starting; @@ -113,6 +122,8 @@ module microstepper_control ( end `endif + // Shift register buffer switch output + // Triger start on time always @(posedge clk) begin s1r <= {s1r[0], s1}; s2r <= {s2r[0], s2}; diff --git a/src/rapcore.v b/src/rapcore.v index 27a1fdb..2b156ed 100644 --- a/src/rapcore.v +++ b/src/rapcore.v @@ -101,8 +101,8 @@ module rapcore ( reg [7:0] config_minimum_on_time = 54; reg [10:0] config_current_threshold = 1024; reg [7:0] config_chargepump_period = 91; - reg config_invert_highside = 0; - reg config_invert_lowside = 0; + reg config_invert_highside = 1; + reg config_invert_lowside = 1; /* reg [511:0] cos_table; >>>>>>> merget tb_m From cd55d87792c1052af960f79ba56253fbb6f8e071 Mon Sep 17 00:00:00 2001 From: johnnyr Date: Fri, 4 Dec 2020 21:11:12 -0600 Subject: [PATCH 48/71] testbench with Jason and Steve round 3 --- testbench/coil.v | 6 +++++- testbench/microstepper_tb.v | 4 ++-- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/testbench/coil.v b/testbench/coil.v index dd8c6fe..72fc19f 100644 --- a/testbench/coil.v +++ b/testbench/coil.v @@ -7,10 +7,14 @@ module coil ( input s_l1, input s_h1, output [12:0] current, + output positive, + output negative, ); reg [12:0] current; - wire on = (s_l0 && s_h1) | (s_l1 && s_h0); + wire on = (!s_l0 && !s_h1) | (!s_l1 && !s_h0); + wire positive = (!s_l0 && !s_h1); + wire negative = (!s_l1 && !s_h0); always @(posedge clk) begin if (!resetn) begin diff --git a/testbench/microstepper_tb.v b/testbench/microstepper_tb.v index 231556d..6da7730 100644 --- a/testbench/microstepper_tb.v +++ b/testbench/microstepper_tb.v @@ -113,7 +113,7 @@ module testbench( .pwm(analog_out2), .duty(target_current2) ); - coil coil2( + coil coil1( .clk(clk), .resetn(resetn), .s_l0(s_l[0]), @@ -122,7 +122,7 @@ module testbench( .s_h1(s_h[1]), .current(current1) ); - coil coil1( + coil coil2( .clk(clk), .resetn(resetn), .s_l0(s_l[2]), From 34f80e3436d83452a711c746b3e37d8dc0f8c529 Mon Sep 17 00:00:00 2001 From: johnnyr Date: Fri, 4 Dec 2020 21:11:39 -0600 Subject: [PATCH 49/71] patches / hacks from testbench working session --- src/microstepper/microstepper_control.v | 44 +++++++++++++++-------- src/microstepper/microstepper_top.v | 12 ++++--- src/microstepper/mytimer.v | 30 +++++++++------- src/microstepper/mytimer_10.v | 47 ++++++++++++++----------- src/microstepper/mytimer_8.v | 47 ++++++++++++++----------- src/rapcore.v | 4 +-- 6 files changed, 110 insertions(+), 74 deletions(-) diff --git a/src/microstepper/microstepper_control.v b/src/microstepper/microstepper_control.v index 85d75f6..d040407 100644 --- a/src/microstepper/microstepper_control.v +++ b/src/microstepper/microstepper_control.v @@ -27,6 +27,8 @@ module microstepper_control ( input [9:0] off_timer1, input [7:0] minimum_on_timer0, input [7:0] minimum_on_timer1, +// input off_timer0_done, +// input off_timer1_done, // output step_b_out, ); reg [7:0] phase_ct; @@ -56,18 +58,18 @@ module microstepper_control ( wire s3; wire s4; - // Off Timer active flag - wire overCurrent0 = off_timer0 > 0; - wire overCurrent1 = off_timer1 > 0; + // Off Timer active flag + wire off_timer_active0 = off_timer0 > 0; + wire off_timer_active1 = off_timer1 > 0; wire fastDecay0 = off_timer0 >= config_fastdecay_threshold; wire fastDecay1 = off_timer1 >= config_fastdecay_threshold; - wire slowDecay0 = overCurrent0 && fastDecay0 == 0; - wire slowDecay1 = overCurrent1 && fastDecay1 == 0; + wire slowDecay0 = off_timer_active0 && fastDecay0 == 0; + wire slowDecay1 = off_timer_active1 && fastDecay1 == 0; - wire fault0 = (minimum_on_timer0 > 0) && overCurrent0; - wire fault1 = (minimum_on_timer1 > 0) && overCurrent1; + wire fault0 = (minimum_on_timer0 > 0) && off_timer_active0; + wire fault1 = (minimum_on_timer1 > 0) && off_timer_active1; wire fault = fault0 | fault1; reg [1:0] s1r, s2r, s3r, s4r; @@ -75,7 +77,6 @@ module microstepper_control ( wire phase_b1_h, phase_b1_l, phase_b2_h, phase_b2_l; // Switch output Low - assign s_l[0] = !(phase_a1_l | fault); assign s_l[1] = !(phase_a2_l | fault); assign s_l[2] = !(phase_b1_l | fault); @@ -98,20 +99,21 @@ module microstepper_control ( assign phase_b2_l = config_invert_lowside ^ (fastDecay1 ? ~s4r[1] : (slowDecay1 ? 1'b0 : s4r[1])); // Start on time per half bridge + // todo concatanate config inverting for active high or low wire s1_starting = s1r == 2'b10; wire s2_starting = s2r == 2'b10; wire s3_starting = s3r == 2'b10; wire s4_starting = s4r == 2'b10; - // start Off Time - // Target peak current detected. Blank timer and Off timer not active - assign offtimer_en0 = analog_cmp1 & blank_timer0 == 0 & overCurrent0 == 0; - assign offtimer_en1 = analog_cmp2 & blank_timer1 == 0 & overCurrent1 == 0; - // Bridge On Time start // Blank timer and minimum on timer enable - assign a_starting = s1_starting | s2_starting; - assign b_starting = s3_starting | s4_starting; + //assign a_starting = s1_starting | s2_starting; + //assign b_starting = s3_starting | s4_starting; + + // start Off Time + // Target peak current detected. Blank timer and Off timer not active + assign offtimer_en0 = analog_cmp1 & blank_timer0 == 0 & off_timer_active0 == 0; + assign offtimer_en1 = analog_cmp2 & blank_timer1 == 0 & off_timer_active1 == 0; `ifdef FORMAL always @(*) begin @@ -130,5 +132,17 @@ module microstepper_control ( s3r <= {s3r[0], s3}; s4r <= {s4r[0], s4}; end +// +// wire [1:0] off_time_b; +// reg a_starting; +// reg b_starting; + +// always @(posedge clk) begin + //start on time +// if +// a_starting <= ~off_timer0; +// b_starting <= ~off_timer1; + +// end endmodule diff --git a/src/microstepper/microstepper_top.v b/src/microstepper/microstepper_top.v index 9ddcfb9..cd43862 100644 --- a/src/microstepper/microstepper_top.v +++ b/src/microstepper/microstepper_top.v @@ -69,6 +69,8 @@ module microstepper_top ( .off_timer1(off_timer1), .minimum_on_timer0(minimum_on_timer0), .minimum_on_timer1(minimum_on_timer1), +// .off_timer0_done (off_timer0_done), +// .off_timer0_done (off_timer1_done), ); mytimer_10 offtimer0 ( @@ -76,7 +78,8 @@ module microstepper_top ( .resetn (resetn), .start_enable(offtimer_en0), .start_time (config_offtime), - .timer (off_timer0) + .timer (off_timer0), + .done (off_timer0_done) ); mytimer_10 offtimer1 ( @@ -84,13 +87,14 @@ module microstepper_top ( .resetn (resetn), .start_enable(offtimer_en1), .start_time (config_offtime), - .timer (off_timer1) + .timer (off_timer1), + .done (off_timer1_done) ); mytimer_8 blanktimer0 ( .clk (clk), .resetn (resetn), - .start_enable(a_starting), + .start_enable(off_timer0_done), .start_time (config_blanktime), .timer (blank_timer0) ); @@ -98,7 +102,7 @@ module microstepper_top ( mytimer_8 blanktimer1 ( .clk (clk), .resetn (resetn), - .start_enable(b_starting), + .start_enable(off_timer1_done), .start_time (config_blanktime), .timer (blank_timer1) ); diff --git a/src/microstepper/mytimer.v b/src/microstepper/mytimer.v index dd87b02..4c11f73 100644 --- a/src/microstepper/mytimer.v +++ b/src/microstepper/mytimer.v @@ -1,29 +1,33 @@ module mytimer ( - clk, - resetn, - start_enable, - start_time, - timer + input clk, + input resetn, + input start_enable, + input [WIDTH-1:0] start_time, + output [WIDTH-1:0] timer, + output done // single cycle timer done event ); parameter WIDTH = 10; - input clk; - input resetn; - input start_enable; - input [WIDTH-1:0] start_time; - output [WIDTH-1:0] timer; - + reg done = 0; reg [WIDTH-1:0] counter; - + reg run = 1; assign timer = counter; always @(posedge clk) begin if (!resetn) counter <= 0; - else if( start_enable ) + else if( start_enable ) begin counter <= start_time; + run <= 1; + end else if( counter > 0 ) counter <= counter - 1'b1; + else if (run) + done <= 1; + if (done) begin + run <= 0; + done <= 0; + end end endmodule diff --git a/src/microstepper/mytimer_10.v b/src/microstepper/mytimer_10.v index 5ce98e4..d8c94a1 100644 --- a/src/microstepper/mytimer_10.v +++ b/src/microstepper/mytimer_10.v @@ -1,26 +1,33 @@ module mytimer_10 ( - clk, - resetn, - start_enable, - start_time, - timer + input clk, + input resetn, + input start_enable, + input [WIDTH-1:0] start_time, + output [WIDTH-1:0] timer, + output done // single cycle timer done event ); - localparam WIDTH = 10; + parameter WIDTH = 10; - input clk; - input resetn; - input start_enable; - input [WIDTH-1:0] start_time; - output [WIDTH-1:0] timer; + reg done = 0; + reg [WIDTH-1:0] counter; + reg run = 1; + assign timer = counter; - mytimer #( - .WIDTH(WIDTH) - ) mytimer10 ( - .clk (clk), - .resetn (resetn), - .start_enable(start_enable), - .start_time (start_time), - .timer (timer) - ); + always @(posedge clk) begin + if (!resetn) + counter <= 0; + else if( start_enable ) begin + counter <= start_time; + run <= 1; + end + else if( counter > 0 ) + counter <= counter - 1'b1; + else if (run) + done <= 1; + if (done) begin + run <= 0; + done <= 0; + end +end endmodule diff --git a/src/microstepper/mytimer_8.v b/src/microstepper/mytimer_8.v index 38f495d..5519e6b 100644 --- a/src/microstepper/mytimer_8.v +++ b/src/microstepper/mytimer_8.v @@ -1,26 +1,33 @@ module mytimer_8 ( - clk, - resetn, - start_enable, - start_time, - timer + input clk, + input resetn, + input start_enable, + input [WIDTH-1:0] start_time, + output [WIDTH-1:0] timer, + output done // single cycle timer done event ); - localparam WIDTH = 8; + parameter WIDTH = 8; - input clk; - input resetn; - input start_enable; - input [WIDTH-1:0] start_time; - output [WIDTH-1:0] timer; + reg done = 0; + reg [WIDTH-1:0] counter; + reg run = 1; + assign timer = counter; - mytimer #( - .WIDTH(WIDTH) - ) mytimer8 ( - .clk (clk), - .resetn (resetn), - .start_enable(start_enable), - .start_time (start_time), - .timer (timer) - ); + always @(posedge clk) begin + if (!resetn) + counter <= 0; + else if( start_enable ) begin + counter <= start_time; + run <= 1; + end + else if( counter > 0 ) + counter <= counter - 1'b1; + else if (run) + done <= 1; + if (done) begin + run <= 0; + done <= 0; + end +end endmodule diff --git a/src/rapcore.v b/src/rapcore.v index 2b156ed..27a1fdb 100644 --- a/src/rapcore.v +++ b/src/rapcore.v @@ -101,8 +101,8 @@ module rapcore ( reg [7:0] config_minimum_on_time = 54; reg [10:0] config_current_threshold = 1024; reg [7:0] config_chargepump_period = 91; - reg config_invert_highside = 1; - reg config_invert_lowside = 1; + reg config_invert_highside = 0; + reg config_invert_lowside = 0; /* reg [511:0] cos_table; >>>>>>> merget tb_m From 3dd23fc0bcbf070cd34ea0b16eec2f6388612146 Mon Sep 17 00:00:00 2001 From: johnnyr Date: Sat, 5 Dec 2020 00:14:50 -0600 Subject: [PATCH 50/71] more test bench patches --- testbench/coil.v | 6 ++++++ testbench/microstepper_tb.v | 10 +++++----- 2 files changed, 11 insertions(+), 5 deletions(-) diff --git a/testbench/coil.v b/testbench/coil.v index 72fc19f..54742dc 100644 --- a/testbench/coil.v +++ b/testbench/coil.v @@ -12,6 +12,12 @@ module coil ( ); reg [12:0] current; + // For each coil of motor + // Each coil is driven by s_x1 and s_x2 + // One side s_x1 or s_x2 must be high when the other is low to be on +// wire phase_a_positive = !s_l0 && !s_h1; +// wire phase_a_negative = !s_l1 && !s_h0; +// wire off = s_l0; wire on = (!s_l0 && !s_h1) | (!s_l1 && !s_h0); wire positive = (!s_l0 && !s_h1); wire negative = (!s_l1 && !s_h0); diff --git a/testbench/microstepper_tb.v b/testbench/microstepper_tb.v index 6da7730..a08c485 100644 --- a/testbench/microstepper_tb.v +++ b/testbench/microstepper_tb.v @@ -13,16 +13,16 @@ module testbench( output analog_out2, output chargepump_pin, output fault, - output [7:0] target_current1, + output [12:0] target_current1, ); reg step; reg dir; reg enable; - reg [7:0] target_current1; - reg [7:0] target_current2; - reg [7:0] current1; - reg [7:0] current2; + reg [12:0] target_current1; + reg [12:0] target_current2; + reg [12:0] current1; + reg [12:0] current2; reg [9:0] config_offtime; reg [7:0] config_blanktime; reg [9:0] config_fastdecay_threshold; From 8f9fb4012cf090de622a024b1fe1183f4cde043b Mon Sep 17 00:00:00 2001 From: johnnyr Date: Sat, 5 Dec 2020 00:15:44 -0600 Subject: [PATCH 51/71] Comments and microstepper refactor from testbench party with Steve and Jason --- src/microstepper/microstepper_control.v | 102 +++++++++++------------- 1 file changed, 46 insertions(+), 56 deletions(-) diff --git a/src/microstepper/microstepper_control.v b/src/microstepper/microstepper_control.v index d040407..7249925 100644 --- a/src/microstepper/microstepper_control.v +++ b/src/microstepper/microstepper_control.v @@ -62,11 +62,6 @@ module microstepper_control ( wire off_timer_active0 = off_timer0 > 0; wire off_timer_active1 = off_timer1 > 0; - wire fastDecay0 = off_timer0 >= config_fastdecay_threshold; - wire fastDecay1 = off_timer1 >= config_fastdecay_threshold; - - wire slowDecay0 = off_timer_active0 && fastDecay0 == 0; - wire slowDecay1 = off_timer_active1 && fastDecay1 == 0; wire fault0 = (minimum_on_timer0 > 0) && off_timer_active0; wire fault1 = (minimum_on_timer1 > 0) && off_timer_active1; @@ -77,38 +72,54 @@ module microstepper_control ( wire phase_b1_h, phase_b1_l, phase_b2_h, phase_b2_l; // Switch output Low - assign s_l[0] = !(phase_a1_l | fault); - assign s_l[1] = !(phase_a2_l | fault); - assign s_l[2] = !(phase_b1_l | fault); - assign s_l[3] = !(phase_b2_l | fault); + assign s_l[0] = config_invert_lowside ^ (phase_a1_l | fault); + assign s_l[1] = config_invert_lowside ^ (phase_a2_l | fault); + assign s_l[2] = config_invert_lowside ^ (phase_b1_l | fault); + assign s_l[3] = config_invert_lowside ^ (phase_b2_l | fault); // Switch output High - assign s_h[0] = !(phase_a1_h | fault); - assign s_h[1] = !(phase_a2_h | fault); - assign s_h[2] = !(phase_b1_h | fault); - assign s_h[3] = !(phase_b2_h | fault); - - assign phase_a1_h = config_invert_highside ^ (slowDecay0 | (fastDecay0 ? s1r[1] : ~s1r[1])); - assign phase_a1_l = config_invert_lowside ^ (fastDecay0 ? ~s1r[1] : (slowDecay0 ? 1'b0 : s1r[1])); - assign phase_a2_h = config_invert_highside ^ (slowDecay0 | (fastDecay0 ? s2r[1] : ~s2r[1])); - assign phase_a2_l = config_invert_lowside ^ (fastDecay0 ? ~s2r[1] : (slowDecay0 ? 1'b0 : s2r[1])); - - assign phase_b1_h = config_invert_highside ^ (slowDecay1 | (fastDecay1 ? s3r[1] : ~s3r[1])); - assign phase_b1_l = config_invert_lowside ^ (fastDecay1 ? ~s3r[1] : (slowDecay1 ? 1'b0 : s3r[1])); - assign phase_b2_h = config_invert_highside ^ (slowDecay1 | (fastDecay1 ? s4r[1] : ~s4r[1])); - assign phase_b2_l = config_invert_lowside ^ (fastDecay1 ? ~s4r[1] : (slowDecay1 ? 1'b0 : s4r[1])); - - // Start on time per half bridge - // todo concatanate config inverting for active high or low - wire s1_starting = s1r == 2'b10; - wire s2_starting = s2r == 2'b10; - wire s3_starting = s3r == 2'b10; - wire s4_starting = s4r == 2'b10; - - // Bridge On Time start - // Blank timer and minimum on timer enable - //assign a_starting = s1_starting | s2_starting; - //assign b_starting = s3_starting | s4_starting; + assign s_h[0] = config_invert_highside ^ (phase_a1_h | fault); + assign s_h[1] = config_invert_highside ^ (phase_a2_h | fault); + assign s_h[2] = config_invert_highside ^ (phase_b1_h | fault); + assign s_h[3] = config_invert_highside ^ (phase_b2_h | fault); + + // Fast decay is first x ticks of off time + // default fast decay = 706 + wire fastDecay0 = off_timer0 >= config_fastdecay_threshold; + wire fastDecay1 = off_timer1 >= config_fastdecay_threshold; + + // Slow decay remainder of off time + wire slowDecay0 = off_timer_active0 && fastDecay0 == 0; + wire slowDecay1 = off_timer_active1 && fastDecay1 == 0; + + // This portion of code sets up output to drive mosfets. Output ON = 0 + + // High side output logic + // If in slow decay =1 + // OR + // ( fast decay and commanded to be OFF ) = 1 + // Then OFF + // Else If Not slow decay (Never in slow decay at same time as fast decay) + // OR + // ( not fast decay ) + // Then + // Follow commanded output + // Else if fast decay + // invert commanded polarity + assign phase_a1_h = slowDecay0 | ( fastDecay0 ? s1 : ~s1 ); + // Low side output logic + // low side output (invert if configured with XOR) + // Invert signal if fast decay commands. + // if slow decay the output is low. Else output = as commanded by microstep counter + assign phase_a1_l = fastDecay0 ? ~s1 : ( slowDecay0 ? 1'b0 : s1 ); + assign phase_a2_h = slowDecay0 | ( fastDecay0 ? s2 : ~s2 ); + assign phase_a2_l = fastDecay0 ? ~s2 : ( slowDecay0 ? 1'b0 : s2 ); + assign phase_b1_h = slowDecay1 | ( fastDecay1 ? s3 : ~s3 ); + assign phase_b1_l = fastDecay1 ? ~s3 : ( slowDecay1 ? 1'b0 : s3 ); + assign phase_b2_h = slowDecay1 | ( fastDecay1 ? s4 : ~s4 ); + assign phase_b2_l = fastDecay1 ? ~s4 : ( slowDecay1 ? 1'b0 : s4 ); + + // NEED DEAD TIME // start Off Time // Target peak current detected. Blank timer and Off timer not active @@ -124,25 +135,4 @@ module microstepper_control ( end `endif - // Shift register buffer switch output - // Triger start on time - always @(posedge clk) begin - s1r <= {s1r[0], s1}; - s2r <= {s2r[0], s2}; - s3r <= {s3r[0], s3}; - s4r <= {s4r[0], s4}; - end -// -// wire [1:0] off_time_b; -// reg a_starting; -// reg b_starting; - -// always @(posedge clk) begin - //start on time -// if -// a_starting <= ~off_timer0; -// b_starting <= ~off_timer1; - -// end - endmodule From d9913dfde5eeb19dc3ae6877f5e84880b4e11aa6 Mon Sep 17 00:00:00 2001 From: johnnyr Date: Sun, 6 Dec 2020 16:38:46 -0600 Subject: [PATCH 52/71] default output active high, slow decay on low side, improve testbench motor model --- sim_microstepper.tcl | 8 +++ sim_microstepper.ys | 2 +- src/microstepper/microstepper_control.v | 19 +++---- testbench/coil.v | 39 ------------- testbench/hbridge_coil.v | 57 +++++++++++++++++++ testbench/microstepper_tb.v | 76 +++++++++++++------------ 6 files changed, 116 insertions(+), 85 deletions(-) create mode 100644 sim_microstepper.tcl delete mode 100644 testbench/coil.v create mode 100644 testbench/hbridge_coil.v diff --git a/sim_microstepper.tcl b/sim_microstepper.tcl new file mode 100644 index 0000000..85bfc4d --- /dev/null +++ b/sim_microstepper.tcl @@ -0,0 +1,8 @@ +yosys -import + +set + +read_verilog -sv testbench/microstepper_tb.v src/microstepper/*.v +prep -top testbench +show m_control_0 +sim -n 4000 -clock clk -vcd testbench/microstepper.vcd diff --git a/sim_microstepper.ys b/sim_microstepper.ys index dda1280..fe0fbff 100644 --- a/sim_microstepper.ys +++ b/sim_microstepper.ys @@ -11,4 +11,4 @@ read_verilog -sv testbench/microstepper_tb.v \ prep -top testbench show microstepper_top -sim -n 400000 -clock clk -vcd testbench/microstepper.vcd +sim -n 4000 -clock clk -vcd testbench/microstepper.vcd diff --git a/src/microstepper/microstepper_control.v b/src/microstepper/microstepper_control.v index 7249925..94d8576 100644 --- a/src/microstepper/microstepper_control.v +++ b/src/microstepper/microstepper_control.v @@ -53,6 +53,7 @@ module microstepper_control ( dir_b <= {dir[0], dir}; end + // Switch outputs wire s1; wire s2; wire s3; @@ -67,7 +68,7 @@ module microstepper_control ( wire fault1 = (minimum_on_timer1 > 0) && off_timer_active1; wire fault = fault0 | fault1; - reg [1:0] s1r, s2r, s3r, s4r; + reg [1:0] s1r, s2r, s3r, s4r; // Switch output history [ previous : now ] wire phase_a1_h, phase_a1_l, phase_a2_h, phase_a2_l; wire phase_b1_h, phase_b1_l, phase_b2_h, phase_b2_l; @@ -95,22 +96,20 @@ module microstepper_control ( // This portion of code sets up output to drive mosfets. Output ON = 0 // High side output logic - // If in slow decay =1 - // OR - // ( fast decay and commanded to be OFF ) = 1 + // If in slow decay = 1 + // OR ( fast decay and commanded to be OFF ) = 1 // Then OFF // Else If Not slow decay (Never in slow decay at same time as fast decay) - // OR - // ( not fast decay ) - // Then - // Follow commanded output + // OR ( not fast decay ) + // Then Follow commanded output // Else if fast decay // invert commanded polarity assign phase_a1_h = slowDecay0 | ( fastDecay0 ? s1 : ~s1 ); // Low side output logic // low side output (invert if configured with XOR) // Invert signal if fast decay commands. - // if slow decay the output is low. Else output = as commanded by microstep counter + // If slow decay Then the output is low. + // Else output = as commanded by microstep counter assign phase_a1_l = fastDecay0 ? ~s1 : ( slowDecay0 ? 1'b0 : s1 ); assign phase_a2_h = slowDecay0 | ( fastDecay0 ? s2 : ~s2 ); assign phase_a2_l = fastDecay0 ? ~s2 : ( slowDecay0 ? 1'b0 : s2 ); @@ -121,7 +120,7 @@ module microstepper_control ( // NEED DEAD TIME - // start Off Time + // Start Off Time // Target peak current detected. Blank timer and Off timer not active assign offtimer_en0 = analog_cmp1 & blank_timer0 == 0 & off_timer_active0 == 0; assign offtimer_en1 = analog_cmp2 & blank_timer1 == 0 & off_timer_active1 == 0; diff --git a/testbench/coil.v b/testbench/coil.v deleted file mode 100644 index 54742dc..0000000 --- a/testbench/coil.v +++ /dev/null @@ -1,39 +0,0 @@ -// Linear current ramp -module coil ( - input clk, - input resetn, - input s_l0, - input s_h0, - input s_l1, - input s_h1, - output [12:0] current, - output positive, - output negative, -); - reg [12:0] current; - - // For each coil of motor - // Each coil is driven by s_x1 and s_x2 - // One side s_x1 or s_x2 must be high when the other is low to be on -// wire phase_a_positive = !s_l0 && !s_h1; -// wire phase_a_negative = !s_l1 && !s_h0; -// wire off = s_l0; - wire on = (!s_l0 && !s_h1) | (!s_l1 && !s_h0); - wire positive = (!s_l0 && !s_h1); - wire negative = (!s_l1 && !s_h0); - - always @(posedge clk) begin - if (!resetn) begin - current <= 0; - end - else begin - if ( on ) begin - current <= current + 1; - end - else begin - current <= 0; - end - end - end -endmodule -//(cnt[2]== 1) \ No newline at end of file diff --git a/testbench/hbridge_coil.v b/testbench/hbridge_coil.v new file mode 100644 index 0000000..e37462b --- /dev/null +++ b/testbench/hbridge_coil.v @@ -0,0 +1,57 @@ +// Built to work in one polarity +module hbridge_coil ( + input clk, + input resetn, + input low_1, + input high_1, + input low_2, + input high_2, + output signed [12:0] current, +); + reg signed [12:0] current; + reg polarity; // arbitrary polarity + reg on; + reg [8:0] cnt; + reg alive; + reg slow_decay; + reg signed [2:0] current_ramp_cnt; // rates are delay counter sizes + reg signed [3:0] slow_decay_cnt; + reg signed [1:0] fast_decay_cnt; + reg open; // coils not connected. Should never occur? + // For each coil of motor + // Each coil is driven by 2 half bridges. _1 and _2 + // Each half bridge is driven by two drivers. high_ and low_ + // Current goes in one direction when low_0 is on and high_1 is on. + // Current goes the opposite direction when high_0 is on and low_1 is on. + // set state of on for next tick +// wire phase_negative = low_1 && high_0; + always @(posedge clk) begin + if (!resetn) begin + current <= 0; + on <= 0; + polarity <= 0; + cnt <= 0; + current_ramp_cnt <= 0; + slow_decay_cnt <= 0; + fast_decay_cnt <= 0; + end + else begin + cnt <= cnt + 1; + current_ramp_cnt <= current_ramp_cnt + 1; + slow_decay_cnt <= slow_decay_cnt + 1; + fast_decay_cnt <= fast_decay_cnt + 1; + on <= ( low_1 && high_2 ) | ( low_2 && high_1 ); + polarity <= high_2 && low_1; + slow_decay <= ( low_1 && low_2 ) | ( high_1 && high_2 ); + if ( on ) begin + if ( polarity && !current_ramp_cnt ) + current <= current + 1; + else if ( !polarity && current && !fast_decay_cnt ) + current <= current - 1; + end + else if ( slow_decay && current && !slow_decay_cnt ) + current <= current - 1; // slow decay every 4th tick + end + end +endmodule +//(cnt[2]== 1) \ No newline at end of file diff --git a/testbench/microstepper_tb.v b/testbench/microstepper_tb.v index a08c485..7869484 100644 --- a/testbench/microstepper_tb.v +++ b/testbench/microstepper_tb.v @@ -1,5 +1,5 @@ `include "../src/microstepper/microstepper_top.v" -`include "coil.v" +`include "hbridge_coil.v" `include "pwm_duty.v" `timescale 1ns/100ps @@ -12,25 +12,24 @@ module testbench( output analog_cmp2, output analog_out2, output chargepump_pin, - output fault, - output [12:0] target_current1, + output faultn, ); - reg step; - reg dir; - reg enable; - reg [12:0] target_current1; - reg [12:0] target_current2; - reg [12:0] current1; - reg [12:0] current2; - reg [9:0] config_offtime; - reg [7:0] config_blanktime; - reg [9:0] config_fastdecay_threshold; - reg [7:0] config_minimum_on_time; - reg [10:0] config_current_threshold; - reg [7:0] config_chargepump_period; - reg config_invert_highside; - reg config_invert_lowside; + reg step; + reg dir; + reg enable; + reg [12:0] target_current1; + reg [12:0] target_current2; + reg signed [12:0] current1; + reg signed [12:0] current2; + reg [9:0] config_offtime; + reg [7:0] config_blanktime; + reg [9:0] config_fastdecay_threshold; + reg [7:0] config_minimum_on_time; + reg [10:0] config_current_threshold; + reg [7:0] config_chargepump_period; + reg config_invert_highside; + reg config_invert_lowside; wire resetn; reg [7:0] resetn_counter = 0; @@ -50,7 +49,7 @@ module testbench( analog_cmp1 <= 0; analog_cmp2 <= 0; step <= 1; - enable <= 1; + enable_in <= 1; config_offtime = 810; config_blanktime = 27; config_fastdecay_threshold = 706; @@ -63,11 +62,12 @@ module testbench( end else begin cnt <= cnt + 1; + enable_in <= 1; step_clock <= step_clock + 1; step <= step_clock[11]; - if (current1 > target_current1) analog_cmp1 <= 1; + if (current1[12:0] > target_current1) analog_cmp1 <= 1; // compare unsigned else analog_cmp1 <= 0; - if (current2 > target_current2) analog_cmp2 <= 1; + if (current2[12:0] > target_current2) analog_cmp2 <= 1; else analog_cmp2 <= 0; if (cnt <= 20'hAEC) begin dir <= 1; @@ -81,9 +81,15 @@ module testbench( microstepper_top stepper( .resetn( resetn ), .clk( clk ), - .fault( fault ), - .s_l( s_l ), - .s_h( s_h ), + .faultn( faultn ), + .phase_a1_l( phase_a1_l ), + .phase_a2_l( phase_a2_l ), + .phase_b1_l( phase_b1_l ), + .phase_b2_l( phase_b2_l ), + .phase_a1_h( phase_a1_h ), + .phase_a2_h( phase_a2_h ), + .phase_b1_h( phase_b1_h ), + .phase_b2_h( phase_b2_h ), .analog_cmp1( analog_cmp1 ), .analog_out1( analog_out1 ), .analog_cmp2( analog_cmp2 ), @@ -91,7 +97,7 @@ module testbench( .chargepump_pin( chargepump_pin ), .step( step ), .dir( dir ), - .enable( enable ), + .enable_in( enable_in ), .config_offtime( config_offtime ), .config_blanktime( config_blanktime ), .config_fastdecay_threshold( config_fastdecay_threshold ), @@ -113,22 +119,22 @@ module testbench( .pwm(analog_out2), .duty(target_current2) ); - coil coil1( + hbridge_coil hbridge_coil1( .clk(clk), .resetn(resetn), - .s_l0(s_l[0]), - .s_l1(s_l[1]), - .s_h0(s_h[0]), - .s_h1(s_h[1]), + .low_1(phase_a1_l), + .high_1(phase_a1_h), + .low_2(phase_a2_l), + .high_2(phase_a2_h), .current(current1) ); - coil coil2( + hbridge_coil hbridge_coil2( .clk(clk), .resetn(resetn), - .s_l0(s_l[2]), - .s_l1(s_l[3]), - .s_h0(s_h[2]), - .s_h1(s_h[3]), + .low_1(phase_b1_l), + .high_1(phase_b1_h), + .low_2(phase_b2_l), + .high_2(phase_b2_h), .current(current2) ); endmodule From cd77468eefdbee9d4664656c812b62f603038bbc Mon Sep 17 00:00:00 2001 From: johnnyr Date: Sun, 6 Dec 2020 21:01:10 -0600 Subject: [PATCH 53/71] debug microstepper test bench. --- sim_microstepper.tcl | 2 +- sim_microstepper.ys | 2 +- src/microstepper/microstepper_control.v | 151 +++++++++++++----------- src/microstepper/microstepper_top.v | 40 ++++--- src/microstepper/mytimer_10.v | 4 +- src/rapcore.v | 10 +- testbench/hbridge_coil.v | 28 +++-- testbench/microstepper_tb.v | 44 ++++--- 8 files changed, 170 insertions(+), 111 deletions(-) diff --git a/sim_microstepper.tcl b/sim_microstepper.tcl index 85bfc4d..a3713ee 100644 --- a/sim_microstepper.tcl +++ b/sim_microstepper.tcl @@ -5,4 +5,4 @@ set read_verilog -sv testbench/microstepper_tb.v src/microstepper/*.v prep -top testbench show m_control_0 -sim -n 4000 -clock clk -vcd testbench/microstepper.vcd +sim -n 40000 -clock clk -vcd testbench/microstepper.vcd diff --git a/sim_microstepper.ys b/sim_microstepper.ys index fe0fbff..dda1280 100644 --- a/sim_microstepper.ys +++ b/sim_microstepper.ys @@ -11,4 +11,4 @@ read_verilog -sv testbench/microstepper_tb.v \ prep -top testbench show microstepper_top -sim -n 4000 -clock clk -vcd testbench/microstepper.vcd +sim -n 400000 -clock clk -vcd testbench/microstepper.vcd diff --git a/src/microstepper/microstepper_control.v b/src/microstepper/microstepper_control.v index 94d8576..cba55af 100644 --- a/src/microstepper/microstepper_control.v +++ b/src/microstepper/microstepper_control.v @@ -1,25 +1,29 @@ module microstepper_control ( input clk, input resetn, - output [3:0] s_l, - output [3:0] s_h, + output phase_a1_l_out, + output phase_a2_l_out, + output phase_b1_l_out, + output phase_b2_l_out, + output phase_a1_h_out, + output phase_a2_h_out, + output phase_b1_h_out, + output phase_b2_h_out, input [9:0] config_fastdecay_threshold, input config_invert_highside, input config_invert_lowside, input step, input dir, - input enable, + input enable_in, input analog_cmp1, input analog_cmp2, - output fault, + output faultn, input s1, input s2, input s3, input s4, output offtimer_en0, output offtimer_en1, - output a_starting, - output b_starting, output [7:0] phase_ct, input [7:0] blank_timer0, input [7:0] blank_timer1, @@ -27,103 +31,110 @@ module microstepper_control ( input [9:0] off_timer1, input [7:0] minimum_on_timer0, input [7:0] minimum_on_timer1, -// input off_timer0_done, -// input off_timer1_done, -// output step_b_out, +// input mixed_decay_enable, ); reg [7:0] phase_ct; -// reg [1:0] step_b; - -// wire step_edge = (step_b[2] ^ step_b[1]) && step_b[2]; - // step edge rising falling + reg [2:0] step_r; + reg [1:0] dir_r; + + reg enable; + + always @(posedge clk) begin + if (!resetn) + enable <= 0; + else + enable <= enable_in; + step_r <= {step_r[1:0], step}; + dir_r <= {dir_r[0], dir}; + end - reg [2:0] step_b; - reg [1:0] dir_b; -// wire step_b_out = step_b[2]; - wire step_rising = (step_b == 2'b01); + wire step_rising = (step_r == 2'b01); always @(posedge clk) begin if (!resetn) begin phase_ct <= 0; end - else if (step_rising) begin - phase_ct <= dir_b[1] ? phase_ct + 1 : phase_ct - 1; - end - step_b <= {step_b[1:0], step}; - dir_b <= {dir[0], dir}; + else if (step_rising) + phase_ct <= dir_r[1] ? phase_ct + 1 : phase_ct - 1; end - // Switch outputs + // Phase polarity control signal from microstep counter wire s1; wire s2; wire s3; wire s4; - // Off Timer active flag - wire off_timer_active0 = off_timer0 > 0; - wire off_timer_active1 = off_timer1 > 0; - - - wire fault0 = (minimum_on_timer0 > 0) && off_timer_active0; - wire fault1 = (minimum_on_timer1 > 0) && off_timer_active1; - wire fault = fault0 | fault1; + // Fault (active low) if off timer starts before minimum on timer expires + wire fault0 = off_timer0 && minimum_on_timer0 && enable; + wire fault1 = off_timer1 && minimum_on_timer1 && enable; + reg faultn; + // Fault latches until reset + always @(posedge clk) begin + if (!resetn) begin + fault0 <= 0; + fault1 <= 0; + faultn <= 1; + end + else if (faultn) begin + faultn <= ( fault0 | fault1 ) && enable; + end + end - reg [1:0] s1r, s2r, s3r, s4r; // Switch output history [ previous : now ] wire phase_a1_h, phase_a1_l, phase_a2_h, phase_a2_l; wire phase_b1_h, phase_b1_l, phase_b2_h, phase_b2_l; - // Switch output Low - assign s_l[0] = config_invert_lowside ^ (phase_a1_l | fault); - assign s_l[1] = config_invert_lowside ^ (phase_a2_l | fault); - assign s_l[2] = config_invert_lowside ^ (phase_b1_l | fault); - assign s_l[3] = config_invert_lowside ^ (phase_b2_l | fault); + // Low side output polarity, enable, and fault shutdown + assign phase_a1_l_out = config_invert_lowside ^ ( phase_a1_l | !enable ); + assign phase_a2_l_out = config_invert_lowside ^ ( phase_a2_l | !enable ); + assign phase_b1_l_out = config_invert_lowside ^ ( phase_b1_l | !enable ); + assign phase_b2_l_out = config_invert_lowside ^ ( phase_b2_l | !enable ); - // Switch output High - assign s_h[0] = config_invert_highside ^ (phase_a1_h | fault); - assign s_h[1] = config_invert_highside ^ (phase_a2_h | fault); - assign s_h[2] = config_invert_highside ^ (phase_b1_h | fault); - assign s_h[3] = config_invert_highside ^ (phase_b2_h | fault); + // High side + assign phase_a1_h_out = config_invert_highside ^ ( phase_a1_h && !faultn && enable ); + assign phase_a2_h_out = config_invert_highside ^ ( phase_a2_h && !faultn && enable ); + assign phase_b1_h_out = config_invert_highside ^ ( phase_b1_h && !faultn && enable ); + assign phase_b2_h_out = config_invert_highside ^ ( phase_b2_h && !faultn && enable ); // Fast decay is first x ticks of off time // default fast decay = 706 wire fastDecay0 = off_timer0 >= config_fastdecay_threshold; wire fastDecay1 = off_timer1 >= config_fastdecay_threshold; - // Slow decay remainder of off time - wire slowDecay0 = off_timer_active0 && fastDecay0 == 0; - wire slowDecay1 = off_timer_active1 && fastDecay1 == 0; - - // This portion of code sets up output to drive mosfets. Output ON = 0 - - // High side output logic - // If in slow decay = 1 - // OR ( fast decay and commanded to be OFF ) = 1 - // Then OFF - // Else If Not slow decay (Never in slow decay at same time as fast decay) - // OR ( not fast decay ) - // Then Follow commanded output - // Else if fast decay - // invert commanded polarity - assign phase_a1_h = slowDecay0 | ( fastDecay0 ? s1 : ~s1 ); + // Slow decay remainder of off time - Active high + wire slowDecay0 = off_timer0 && !fastDecay0; + wire slowDecay1 = off_timer1 && !fastDecay1; + + // This portion of code sets up output to drive mosfets. + // Output ON = 1 when config_invert_lowside and config_invert_highside == 0 + + // High side is ON if slow decay is NOT active + // AND + // ( + // In fast decay AND would normally be off this phase + // OR + // Should be on this phase / polarity + assign phase_a1_h = !slowDecay0 && ( fastDecay0 ? !s1 : s1 ); + assign phase_a2_h = !slowDecay0 && ( fastDecay0 ? !s2 : s2 ); + assign phase_b1_h = !slowDecay1 && ( fastDecay1 ? !s3 : s3 ); + assign phase_b2_h = !slowDecay1 && ( fastDecay1 ? !s4 : s4 ); // Low side output logic - // low side output (invert if configured with XOR) // Invert signal if fast decay commands. // If slow decay Then the output is low. // Else output = as commanded by microstep counter - assign phase_a1_l = fastDecay0 ? ~s1 : ( slowDecay0 ? 1'b0 : s1 ); - assign phase_a2_h = slowDecay0 | ( fastDecay0 ? s2 : ~s2 ); - assign phase_a2_l = fastDecay0 ? ~s2 : ( slowDecay0 ? 1'b0 : s2 ); - assign phase_b1_h = slowDecay1 | ( fastDecay1 ? s3 : ~s3 ); - assign phase_b1_l = fastDecay1 ? ~s3 : ( slowDecay1 ? 1'b0 : s3 ); - assign phase_b2_h = slowDecay1 | ( fastDecay1 ? s4 : ~s4 ); - assign phase_b2_l = fastDecay1 ? ~s4 : ( slowDecay1 ? 1'b0 : s4 ); - - // NEED DEAD TIME + // Low side is ON if slow decay is active + // OR + // Fast decay and would normally be off this phase + assign phase_a1_l = slowDecay0 | ( fastDecay0 ? s1 : !s1 ); + assign phase_a2_l = slowDecay0 | ( fastDecay0 ? s2 : !s2 ); + assign phase_b1_l = slowDecay1 | ( fastDecay1 ? s3 : !s3 ); + assign phase_b2_l = slowDecay1 | ( fastDecay1 ? s4 : !s4 ); + + // Fixed off time peak current controller // Start Off Time // Target peak current detected. Blank timer and Off timer not active - assign offtimer_en0 = analog_cmp1 & blank_timer0 == 0 & off_timer_active0 == 0; - assign offtimer_en1 = analog_cmp2 & blank_timer1 == 0 & off_timer_active1 == 0; + assign offtimer_en0 = analog_cmp1 & !blank_timer0 & !off_timer0; + assign offtimer_en1 = analog_cmp2 & !blank_timer1 & !off_timer1; `ifdef FORMAL always @(*) begin diff --git a/src/microstepper/microstepper_top.v b/src/microstepper/microstepper_top.v index cd43862..b4535f7 100644 --- a/src/microstepper/microstepper_top.v +++ b/src/microstepper/microstepper_top.v @@ -2,8 +2,14 @@ module microstepper_top ( input clk, input resetn, - output [3:0] s_l, - output [3:0] s_h, + output phase_a1_l, + output phase_a2_l, + output phase_b1_l, + output phase_b2_l, + output phase_a1_h, + output phase_a2_h, + output phase_b1_h, + output phase_b2_h, input analog_cmp1, output analog_out1, input analog_cmp2, @@ -11,6 +17,7 @@ module microstepper_top ( output chargepump_pin, input [9:0] config_offtime, input [7:0] config_blanktime, + input [2:0] config_deadtime, input [9:0] config_fastdecay_threshold, input [7:0] config_minimum_on_time, input [10:0] config_current_threshold, @@ -20,8 +27,8 @@ module microstepper_top ( //input [511:0] cos_table, input step, input dir, - input enable, - output fault, + input enable_in, + output faultn, ); wire [5:0] cos_index1; wire [5:0] cos_index2; @@ -43,25 +50,29 @@ module microstepper_top ( microstepper_control microstepper_control0( .clk(clk), .resetn(resetn), - .s_l(s_l), - .s_h(s_h), + .phase_a1_l_out(phase_a1_l), + .phase_a2_l_out(phase_a2_l), + .phase_b1_l_out(phase_b1_l), + .phase_b2_l_out(phase_b2_l), + .phase_a1_h_out(phase_a1_h), + .phase_a2_h_out(phase_a2_h), + .phase_b1_h_out(phase_b1_h), + .phase_b2_h_out(phase_b2_h), .config_fastdecay_threshold(config_fastdecay_threshold), .config_invert_highside(config_invert_highside), .config_invert_lowside(config_invert_lowside), .step(step), .dir(dir), - .enable(enable), + .enable_in(enable_in), .analog_cmp1(analog_cmp1), .analog_cmp2(analog_cmp2), - .fault(fault), + .faultn(faultn), .s1(s1), .s2(s2), .s3(s3), .s4(s4), .offtimer_en0(offtimer_en0), .offtimer_en1(offtimer_en1), - .a_starting(a_starting), - .b_starting(b_starting), .phase_ct(phase_ct), .blank_timer0(blank_timer0), .blank_timer1(blank_timer1), @@ -69,10 +80,11 @@ module microstepper_top ( .off_timer1(off_timer1), .minimum_on_timer0(minimum_on_timer0), .minimum_on_timer1(minimum_on_timer1), -// .off_timer0_done (off_timer0_done), -// .off_timer0_done (off_timer1_done), ); +wire [10:0] Woff_timer0_done; +wire [10:0] off_timer0_done; + mytimer_10 offtimer0 ( .clk (clk), .resetn (resetn), @@ -110,7 +122,7 @@ module microstepper_top ( mytimer_8 minimumontimer0 ( .clk (clk), .resetn (resetn), - .start_enable(a_starting), + .start_enable(off_timer0_done), .start_time (config_minimum_on_time), .timer (minimum_on_timer0) ); @@ -118,7 +130,7 @@ module microstepper_top ( mytimer_8 minimumontimer1 ( .clk (clk), .resetn (resetn), - .start_enable(b_starting), + .start_enable(off_timer1_done), .start_time (config_minimum_on_time), .timer (minimum_on_timer1) ); diff --git a/src/microstepper/mytimer_10.v b/src/microstepper/mytimer_10.v index d8c94a1..dc1db0f 100644 --- a/src/microstepper/mytimer_10.v +++ b/src/microstepper/mytimer_10.v @@ -14,8 +14,10 @@ module mytimer_10 ( assign timer = counter; always @(posedge clk) begin - if (!resetn) + if (!resetn) begin counter <= 0; + done <= 0; + end else if( start_enable ) begin counter <= start_time; run <= 1; diff --git a/src/rapcore.v b/src/rapcore.v index 27a1fdb..7a95627 100644 --- a/src/rapcore.v +++ b/src/rapcore.v @@ -136,8 +136,14 @@ module rapcore ( microstepper_top microstepper0( .clk(CLK), .resetn( resetn), - .s_l ({PHASE_B2[1], PHASE_B1[1], PHASE_A2[1], PHASE_A1[1]}), - .s_h ({PHASE_B2_H[1], PHASE_B1_H[1], PHASE_A2_H[1], PHASE_A1_H[1]}), + .phase_a1_l(PHASE_A1), + .phase_a2_l(PHASE_A2), + .phase_b1_l(PHASE_B1), + .phase_b2_l(PHASE_B2), + .phase_a1_h(PHASE_A1_H), + .phase_a2_h(PHASE_A2_H), + .phase_b1_h(PHASE_B1_H), + .phase_b2_h(PHASE_B2_H), .analog_cmp1 (analog_cmp1), .analog_out1 (analog_out1), .analog_cmp2 (analog_cmp2), diff --git a/testbench/hbridge_coil.v b/testbench/hbridge_coil.v index e37462b..98e46d5 100644 --- a/testbench/hbridge_coil.v +++ b/testbench/hbridge_coil.v @@ -7,6 +7,8 @@ module hbridge_coil ( input low_2, input high_2, output signed [12:0] current, + output current_sum_polarity, + input polarity_invert_config, ); reg signed [12:0] current; reg polarity; // arbitrary polarity @@ -14,10 +16,13 @@ module hbridge_coil ( reg [8:0] cnt; reg alive; reg slow_decay; - reg signed [2:0] current_ramp_cnt; // rates are delay counter sizes + reg signed current_ramp_cnt; // rates are delay counter sizes reg signed [3:0] slow_decay_cnt; reg signed [1:0] fast_decay_cnt; reg open; // coils not connected. Should never occur? + wire current_sum_polarity; + + assign current_sum_polarity = (current >= 0); // For each coil of motor // Each coil is driven by 2 half bridges. _1 and _2 // Each half bridge is driven by two drivers. high_ and low_ @@ -41,16 +46,23 @@ module hbridge_coil ( slow_decay_cnt <= slow_decay_cnt + 1; fast_decay_cnt <= fast_decay_cnt + 1; on <= ( low_1 && high_2 ) | ( low_2 && high_1 ); - polarity <= high_2 && low_1; + if ( polarity_invert_config ) + polarity <= high_2 && low_1; + else + polarity <= low_2 && high_1; slow_decay <= ( low_1 && low_2 ) | ( high_1 && high_2 ); if ( on ) begin - if ( polarity && !current_ramp_cnt ) - current <= current + 1; - else if ( !polarity && current && !fast_decay_cnt ) - current <= current - 1; + if ( polarity ) + current <= current + !current_ramp_cnt; + else + current <= current - !current_ramp_cnt; // fast decay + end + else if ( slow_decay && current !== 0 && !slow_decay_cnt ) begin + if (current >= 0) // current is positive + current <= current - 1; // slow decay every 4th tick + else + current <= current + 1; end - else if ( slow_decay && current && !slow_decay_cnt ) - current <= current - 1; // slow decay every 4th tick end end endmodule diff --git a/testbench/microstepper_tb.v b/testbench/microstepper_tb.v index 7869484..1662f2c 100644 --- a/testbench/microstepper_tb.v +++ b/testbench/microstepper_tb.v @@ -13,6 +13,7 @@ module testbench( output analog_out2, output chargepump_pin, output faultn, + output current_sum_polarity, ); reg step; @@ -43,11 +44,13 @@ module testbench( reg analog_cmp2; reg [40:0] step_clock; reg [20:0] cnt; + reg [12:0] current_abs1; + reg [12:0] current_abs2; always @(posedge clk) begin if (!resetn) begin cnt <= 0; - analog_cmp1 <= 0; - analog_cmp2 <= 0; + analog_cmp1 <= 1; + analog_cmp2 <= 1; step <= 1; enable_in <= 1; config_offtime = 810; @@ -56,25 +59,34 @@ module testbench( config_minimum_on_time = 54; config_current_threshold = 1024; config_chargepump_period = 91; - config_invert_highside = 0; - config_invert_lowside = 0; + config_invert_highside = 1; + config_invert_lowside = 1; step_clock = 0; end else begin cnt <= cnt + 1; enable_in <= 1; + if (current1[12] == 1'b1) begin + current_abs1 = -current; + end + else begin + current_abs1 = current1; + end + if (current2[12] == 1'b1) begin + current_abs2 = -current2; + end + else begin + current_abs2 = current2; + end step_clock <= step_clock + 1; - step <= step_clock[11]; - if (current1[12:0] > target_current1) analog_cmp1 <= 1; // compare unsigned - else analog_cmp1 <= 0; - if (current2[12:0] > target_current2) analog_cmp2 <= 1; - else analog_cmp2 <= 0; - if (cnt <= 20'hAEC) begin + step <= step_clock[10]; + analog_cmp1 <= (current_abs1[11:0] >= target_current1[11:0]); // compare unsigned + analog_cmp2 <= (current_abs2[11:0] >= target_current2[11:0]); + if (cnt <= 20'h4CA9) begin dir <= 1; end - else if (cnt <= 20'hEBE) begin + else dir <= 0; - end end end @@ -126,7 +138,9 @@ module testbench( .high_1(phase_a1_h), .low_2(phase_a2_l), .high_2(phase_a2_h), - .current(current1) + .current(current1), + .current_sum_polarity(current_sum_polarity), + .polarity_invert_config(1) ); hbridge_coil hbridge_coil2( .clk(clk), @@ -135,7 +149,9 @@ module testbench( .high_1(phase_b1_h), .low_2(phase_b2_l), .high_2(phase_b2_h), - .current(current2) + .current(current2), + .current_sum_polarity(current_sum_polarity), + .polarity_invert_config(1) ); endmodule From 10d0b410f573c57f07584dd7f119bcb22ffc8657 Mon Sep 17 00:00:00 2001 From: johnnyr Date: Sun, 6 Dec 2020 21:45:22 -0600 Subject: [PATCH 54/71] fix undeclared errors. add default_nettype none. --- src/microstepper/analog_out.v | 1 + src/microstepper/chargepump.v | 1 + src/microstepper/cosine.v | 1 + src/microstepper/microstep_counter.v | 1 + src/microstepper/microstepper_control.v | 32 ++++++++++--------------- src/microstepper/microstepper_top.v | 3 ++- src/microstepper/mytimer.v | 1 + src/microstepper/mytimer_10.v | 1 + src/microstepper/mytimer_8.v | 1 + src/quad_enc.v | 22 ----------------- src/rapcore.v | 2 +- testbench/microstepper_tb.v | 22 ++++++++++++----- 12 files changed, 38 insertions(+), 50 deletions(-) diff --git a/src/microstepper/analog_out.v b/src/microstepper/analog_out.v index 1b55c55..b0a3305 100644 --- a/src/microstepper/analog_out.v +++ b/src/microstepper/analog_out.v @@ -1,3 +1,4 @@ +`default_nettype none module analog_out ( input wire clk, input wire resetn, diff --git a/src/microstepper/chargepump.v b/src/microstepper/chargepump.v index 9fad9c0..8550ddb 100644 --- a/src/microstepper/chargepump.v +++ b/src/microstepper/chargepump.v @@ -1,3 +1,4 @@ +`default_nettype none module chargepump ( input clk, input resetn, diff --git a/src/microstepper/cosine.v b/src/microstepper/cosine.v index 460e5cf..07d9631 100644 --- a/src/microstepper/cosine.v +++ b/src/microstepper/cosine.v @@ -1,3 +1,4 @@ +`default_nettype none module cosine ( input wire [5:0] cos_index, output wire [7:0] cos_value diff --git a/src/microstepper/microstep_counter.v b/src/microstepper/microstep_counter.v index 7ea6f0c..0453a57 100644 --- a/src/microstepper/microstep_counter.v +++ b/src/microstepper/microstep_counter.v @@ -1,3 +1,4 @@ +`default_nettype none module microstep_counter ( input [7:0] pos, output [5:0] cos_index1, diff --git a/src/microstepper/microstepper_control.v b/src/microstepper/microstepper_control.v index cba55af..cafe08b 100644 --- a/src/microstepper/microstepper_control.v +++ b/src/microstepper/microstepper_control.v @@ -1,3 +1,4 @@ +`default_nettype none module microstepper_control ( input clk, input resetn, @@ -71,8 +72,8 @@ module microstepper_control ( // Fault latches until reset always @(posedge clk) begin if (!resetn) begin - fault0 <= 0; - fault1 <= 0; +// fault0 <= 0; +// fault1 <= 0; faultn <= 1; end else if (faultn) begin @@ -104,35 +105,26 @@ module microstepper_control ( wire slowDecay0 = off_timer0 && !fastDecay0; wire slowDecay1 = off_timer1 && !fastDecay1; - // This portion of code sets up output to drive mosfets. - // Output ON = 1 when config_invert_lowside and config_invert_highside == 0 - - // High side is ON if slow decay is NOT active + // Half bridge high side is active + // WHEN slow decay is NOT active // AND - // ( - // In fast decay AND would normally be off this phase + // ( fast decay active AND would normally be off this phase ) // OR - // Should be on this phase / polarity + // Should be on to drive this phase / polarity (microstepper_counter) assign phase_a1_h = !slowDecay0 && ( fastDecay0 ? !s1 : s1 ); assign phase_a2_h = !slowDecay0 && ( fastDecay0 ? !s2 : s2 ); assign phase_b1_h = !slowDecay1 && ( fastDecay1 ? !s3 : s3 ); assign phase_b2_h = !slowDecay1 && ( fastDecay1 ? !s4 : s4 ); - // Low side output logic - // Invert signal if fast decay commands. - // If slow decay Then the output is low. - // Else output = as commanded by microstep counter - - // Low side is ON if slow decay is active + // Low side is active + // WHEN slow decay is active // OR - // Fast decay and would normally be off this phase + // ( Fast decay active AND would normally be off this phase ) assign phase_a1_l = slowDecay0 | ( fastDecay0 ? s1 : !s1 ); assign phase_a2_l = slowDecay0 | ( fastDecay0 ? s2 : !s2 ); assign phase_b1_l = slowDecay1 | ( fastDecay1 ? s3 : !s3 ); assign phase_b2_l = slowDecay1 | ( fastDecay1 ? s4 : !s4 ); - - // Fixed off time peak current controller - // Start Off Time - // Target peak current detected. Blank timer and Off timer not active + + // Fixed off time peak current controller off time start assign offtimer_en0 = analog_cmp1 & !blank_timer0 & !off_timer0; assign offtimer_en1 = analog_cmp2 & !blank_timer1 & !off_timer1; diff --git a/src/microstepper/microstepper_top.v b/src/microstepper/microstepper_top.v index b4535f7..e14e7a2 100644 --- a/src/microstepper/microstepper_top.v +++ b/src/microstepper/microstepper_top.v @@ -1,4 +1,4 @@ - +`default_nettype none module microstepper_top ( input clk, input resetn, @@ -46,6 +46,7 @@ module microstepper_top ( wire [9:0] off_timer1; wire [7:0] minimum_on_timer0; wire [7:0] minimum_on_timer1; + wire off_timer1_done; microstepper_control microstepper_control0( .clk(clk), diff --git a/src/microstepper/mytimer.v b/src/microstepper/mytimer.v index 4c11f73..1f5112b 100644 --- a/src/microstepper/mytimer.v +++ b/src/microstepper/mytimer.v @@ -1,3 +1,4 @@ +`default_nettype none module mytimer ( input clk, input resetn, diff --git a/src/microstepper/mytimer_10.v b/src/microstepper/mytimer_10.v index dc1db0f..d285dd4 100644 --- a/src/microstepper/mytimer_10.v +++ b/src/microstepper/mytimer_10.v @@ -1,3 +1,4 @@ +`default_nettype none module mytimer_10 ( input clk, input resetn, diff --git a/src/microstepper/mytimer_8.v b/src/microstepper/mytimer_8.v index 5519e6b..aacfcf8 100644 --- a/src/microstepper/mytimer_8.v +++ b/src/microstepper/mytimer_8.v @@ -1,3 +1,4 @@ +`default_nettype none module mytimer_8 ( input clk, input resetn, diff --git a/src/quad_enc.v b/src/quad_enc.v index e8ee9ab..7cabd2a 100755 --- a/src/quad_enc.v +++ b/src/quad_enc.v @@ -1,25 +1,3 @@ -/* UltiCores -- IP Cores for Mechatronic Control Systems - * - * Copyright (C) 2019 UltiMachine - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -/* quad_enc.v - * Quadrature decoder inspired by https://www.fpga4fun.com/QuadratureDecoder.html - * Converted to 32 bit. Added reset and fault logic. Changed some names to fit us. - */ - `default_nettype none module quad_enc #( diff --git a/src/rapcore.v b/src/rapcore.v index 7a95627..44726b2 100644 --- a/src/rapcore.v +++ b/src/rapcore.v @@ -160,7 +160,7 @@ module rapcore ( //.cos_table (cos_table), .step (step), .dir (dir), - .enable(enable), + .enable_in(enable), ); `endif diff --git a/testbench/microstepper_tb.v b/testbench/microstepper_tb.v index 1662f2c..a71aed7 100644 --- a/testbench/microstepper_tb.v +++ b/testbench/microstepper_tb.v @@ -1,3 +1,4 @@ +`default_nettype none `include "../src/microstepper/microstepper_top.v" `include "hbridge_coil.v" `include "pwm_duty.v" @@ -18,7 +19,7 @@ module testbench( reg step; reg dir; - reg enable; + reg enable_in; reg [12:0] target_current1; reg [12:0] target_current2; reg signed [12:0] current1; @@ -46,6 +47,15 @@ module testbench( reg [20:0] cnt; reg [12:0] current_abs1; reg [12:0] current_abs2; + wire phase_a1_l; + wire phase_a2_l; + wire phase_b1_l; + wire phase_b2_l; + wire phase_a1_h; + wire phase_a2_h; + wire phase_b1_h; + wire phase_b2_h; + always @(posedge clk) begin if (!resetn) begin cnt <= 0; @@ -59,15 +69,15 @@ module testbench( config_minimum_on_time = 54; config_current_threshold = 1024; config_chargepump_period = 91; - config_invert_highside = 1; - config_invert_lowside = 1; + config_invert_highside = 0; + config_invert_lowside = 0; step_clock = 0; end else begin cnt <= cnt + 1; enable_in <= 1; if (current1[12] == 1'b1) begin - current_abs1 = -current; + current_abs1 = -current1; end else begin current_abs1 = current1; @@ -140,7 +150,7 @@ module testbench( .high_2(phase_a2_h), .current(current1), .current_sum_polarity(current_sum_polarity), - .polarity_invert_config(1) + .polarity_invert_config(0) ); hbridge_coil hbridge_coil2( .clk(clk), @@ -151,7 +161,7 @@ module testbench( .high_2(phase_b2_h), .current(current2), .current_sum_polarity(current_sum_polarity), - .polarity_invert_config(1) + .polarity_invert_config(0) ); endmodule From 7610a7b836d2a3d07642ca34a84fd6fa640eef8b Mon Sep 17 00:00:00 2001 From: johnnyr Date: Sun, 6 Dec 2020 23:00:53 -0600 Subject: [PATCH 55/71] fix merged end comment --- src/rapcore.v | 119 -------------------------------------------------- 1 file changed, 119 deletions(-) diff --git a/src/rapcore.v b/src/rapcore.v index 44726b2..2d4f393 100644 --- a/src/rapcore.v +++ b/src/rapcore.v @@ -80,7 +80,6 @@ module rapcore ( // Stepper Setup // TODO: Generate statement? // Stepper Config -<<<<<<< HEAD wire [2:0] microsteps; wire [7:0] current; wire [9:0] config_offtime; @@ -91,21 +90,6 @@ module rapcore ( wire [7:0] config_chargepump_period; wire config_invert_highside; wire config_invert_lowside; - wire [511:0] cos_table; -======= - reg [2:0] microsteps = 2; - reg [7:0] current = 140; - reg [9:0] config_offtime = 810; - reg [7:0] config_blanktime = 27; - reg [9:0] config_fastdecay_threshold = 706; - reg [7:0] config_minimum_on_time = 54; - reg [10:0] config_current_threshold = 1024; - reg [7:0] config_chargepump_period = 91; - reg config_invert_highside = 0; - reg config_invert_lowside = 0; - /* - reg [511:0] cos_table; ->>>>>>> merget tb_m // Stepper control lines wire step; @@ -210,112 +194,9 @@ module rapcore ( .encoder_count(encoder_count), -<<<<<<< HEAD .step(step), .dir(dir), .enable(enable), -======= - // Coordinated Move - `CMD_COORDINATED_STEP: begin - - // Get Direction Bits - dir_r[writemoveind] <= word_data_received[0]; - - // Store encoder values across all axes Now - encoder_store <= encoder_count; - - end - - // Motor Enable/disable - `CMD_MOTOR_ENABLE: begin - enable <= word_data_received[0]; - end - - // Clock divisor (24 bit) - `CMD_CLK_DIVISOR: begin - clock_divisor[7:0] <= word_data_received[7:0]; - end - - // Set Microstepping - `CMD_MOTORCONFIG: begin - // TODO needs to be power of two - current[7:0] <= word_data_received[15:8]; - microsteps[2:0] <= word_data_received[2:0]; - end - - // Set Microstepping Parameters - `CMD_MICROSTEPPER_CONFIG: begin - config_offtime[9:0] <= word_data_received[39:30]; - config_blanktime[7:0] <= word_data_received[29:22]; - config_fastdecay_threshold[9:0] <= word_data_received[21:12]; - config_minimum_on_time[7:0] <= word_data_received[18:11]; - config_current_threshold[10:0] <= word_data_received[10:0]; - end - - // Set chargepump period - `CMD_CHARGEPUMP: begin - config_chargepump_period[7:0] <= word_data_received[7:0]; - end - - // Invert Bridge outputs - `CMD_BRIDGEINVERT: begin - config_invert_highside <= word_data_received[1]; - config_invert_lowside <= word_data_received[0]; - end -/* - // Write to Cosine Table - `CMD_COSINE_CONFIG: begin - //config_cosine_table[word_data_received[35:32]] <= word_data_received[31:0]; - cos_table[word_data_received[37:32]] <= word_data_received[7:0]; - //cos_table[word_data_received[35:32]+3] <= word_data_received[31:25]; - //cos_table[word_data_received[35:32]+2] <= word_data_received[24:16]; - //cos_table[word_data_received[35:32]+1] <= word_data_received[15:8]; - //cos_table[word_data_received[35:32]] <= word_data_received[7:0]; - end -*/ - // API Version - `CMD_API_VERSION: begin - word_send_data[7:0] <= `VERSION_PATCH; - word_send_data[15:8] <= `VERSION_MINOR; - word_send_data[23:16] <= `VERSION_MAJOR; - end - - endcase - - // Addition Word Processing - end else begin - - message_word_count <= message_word_count + 1; - - case (message_header) - // Move Routine - `CMD_COORDINATED_STEP: begin - // the first non-header word is the move duration - case (message_word_count) - 1: begin - move_duration[writemoveind][63:0] <= word_data_received[63:0]; - //word_send_data[63:0] = last_steps_taken[63:0]; // Prep to send steps - end - 2: begin - increment[writemoveind][63:0] <= word_data_received[63:0]; - word_send_data[63:0] <= encoder_store[63:0]; // Prep to send encoder read - end - 3: begin - incrementincrement[writemoveind][63:0] <= word_data_received[63:0]; - message_word_count <= 0; - stepready[writemoveind] <= ~stepready[writemoveind]; - writemoveind <= writemoveind + 1'b1; - message_header <= 8'b0; // Reset Message Header - `ifdef FORMAL - assert(writemoveind <= `MOVE_BUFFER_SIZE); - `endif - end - endcase - end - endcase - end - end ->>>>>>> merget tb_m `ifdef BUFFER_DTR .BUFFER_DTR(BUFFER_DTR), From da7ef4a4c202c376a14e29513223118ca5753234 Mon Sep 17 00:00:00 2001 From: Tonokip Date: Mon, 30 Nov 2020 19:36:25 -0600 Subject: [PATCH 56/71] static cosine table --- src/spi_state_machine.v | 1 + 1 file changed, 1 insertion(+) diff --git a/src/spi_state_machine.v b/src/spi_state_machine.v index b7f2b29..d03f76b 100644 --- a/src/spi_state_machine.v +++ b/src/spi_state_machine.v @@ -93,6 +93,7 @@ module spi_state_machine( reg [7:0] config_chargepump_period = 91; reg config_invert_highside = 0; reg config_invert_lowside = 0; + reg [511:0] cos_table; initial begin From f82c29601efe184b5d8916c677292c31c5ad6808 Mon Sep 17 00:00:00 2001 From: johnnyr Date: Tue, 1 Dec 2020 01:41:35 -0600 Subject: [PATCH 57/71] preset params for mytimers --- src/microstepper/microstepper_top.v | 24 ++++++++++++++++++------ 1 file changed, 18 insertions(+), 6 deletions(-) diff --git a/src/microstepper/microstepper_top.v b/src/microstepper/microstepper_top.v index e14e7a2..01f71c5 100644 --- a/src/microstepper/microstepper_top.v +++ b/src/microstepper/microstepper_top.v @@ -86,7 +86,9 @@ module microstepper_top ( wire [10:0] Woff_timer0_done; wire [10:0] off_timer0_done; - mytimer_10 offtimer0 ( + mytimer_10 #( + .WIDTH(10) + ) offtimer0 ( .clk (clk), .resetn (resetn), .start_enable(offtimer_en0), @@ -95,7 +97,9 @@ wire [10:0] off_timer0_done; .done (off_timer0_done) ); - mytimer_10 offtimer1 ( + mytimer_10 #( + .WIDTH(10) + ) offtimer1 ( .clk (clk), .resetn (resetn), .start_enable(offtimer_en1), @@ -104,7 +108,9 @@ wire [10:0] off_timer0_done; .done (off_timer1_done) ); - mytimer_8 blanktimer0 ( + mytimer_8 #( + .WIDTH(8) + ) blanktimer0 ( .clk (clk), .resetn (resetn), .start_enable(off_timer0_done), @@ -112,7 +118,9 @@ wire [10:0] off_timer0_done; .timer (blank_timer0) ); - mytimer_8 blanktimer1 ( + mytimer_8 #( + .WIDTH(8) + ) blanktimer1 ( .clk (clk), .resetn (resetn), .start_enable(off_timer1_done), @@ -120,7 +128,9 @@ wire [10:0] off_timer0_done; .timer (blank_timer1) ); - mytimer_8 minimumontimer0 ( + mytimer_8 #( + .WIDTH(8) + ) minimumontimer0 ( .clk (clk), .resetn (resetn), .start_enable(off_timer0_done), @@ -128,7 +138,9 @@ wire [10:0] off_timer0_done; .timer (minimum_on_timer0) ); - mytimer_8 minimumontimer1 ( + mytimer_8 #( + .WIDTH(8) + ) minimumontimer1 ( .clk (clk), .resetn (resetn), .start_enable(off_timer1_done), From f99e01ed7fee4804a8845b9d374eef2d9ec0a8c0 Mon Sep 17 00:00:00 2001 From: Tonokip Date: Tue, 1 Dec 2020 20:03:15 -0600 Subject: [PATCH 58/71] reuse mytimer for mytimer_8 and mytimer_10 --- src/microstepper/mytimer_10.v | 33 +++++++++------------------------ src/microstepper/mytimer_8.v | 31 +++++++++---------------------- 2 files changed, 18 insertions(+), 46 deletions(-) diff --git a/src/microstepper/mytimer_10.v b/src/microstepper/mytimer_10.v index d285dd4..5e2ca23 100644 --- a/src/microstepper/mytimer_10.v +++ b/src/microstepper/mytimer_10.v @@ -7,30 +7,15 @@ module mytimer_10 ( output [WIDTH-1:0] timer, output done // single cycle timer done event ); - parameter WIDTH = 10; - reg done = 0; - reg [WIDTH-1:0] counter; - reg run = 1; - assign timer = counter; - - always @(posedge clk) begin - if (!resetn) begin - counter <= 0; - done <= 0; - end - else if( start_enable ) begin - counter <= start_time; - run <= 1; - end - else if( counter > 0 ) - counter <= counter - 1'b1; - else if (run) - done <= 1; - if (done) begin - run <= 0; - done <= 0; - end -end + mytimer #( + .WIDTH(8) + ) mytimer8 ( + .clk (clk), + .resetn (resetn), + .start_enable(start_enable), + .start_time (start_time), + .timer (timer) + ); endmodule diff --git a/src/microstepper/mytimer_8.v b/src/microstepper/mytimer_8.v index aacfcf8..c07c98a 100644 --- a/src/microstepper/mytimer_8.v +++ b/src/microstepper/mytimer_8.v @@ -7,28 +7,15 @@ module mytimer_8 ( output [WIDTH-1:0] timer, output done // single cycle timer done event ); - parameter WIDTH = 8; - reg done = 0; - reg [WIDTH-1:0] counter; - reg run = 1; - assign timer = counter; - - always @(posedge clk) begin - if (!resetn) - counter <= 0; - else if( start_enable ) begin - counter <= start_time; - run <= 1; - end - else if( counter > 0 ) - counter <= counter - 1'b1; - else if (run) - done <= 1; - if (done) begin - run <= 0; - done <= 0; - end -end + mytimer #( + .WIDTH(8) + ) mytimer8 ( + .clk (clk), + .resetn (resetn), + .start_enable(start_enable), + .start_time (start_time), + .timer (timer) + ); endmodule From c8f2174c7f84a9a8d64e703bf13642274fc3b178 Mon Sep 17 00:00:00 2001 From: Tonokip Date: Tue, 1 Dec 2020 20:42:40 -0600 Subject: [PATCH 59/71] timer fixes and missing wires --- src/microstepper/microstepper_top.v | 32 +++++++++++++++-------------- src/microstepper/mytimer_10.v | 11 ++++++++-- src/microstepper/mytimer_8.v | 9 +++++++- 3 files changed, 34 insertions(+), 18 deletions(-) diff --git a/src/microstepper/microstepper_top.v b/src/microstepper/microstepper_top.v index 01f71c5..e2823cf 100644 --- a/src/microstepper/microstepper_top.v +++ b/src/microstepper/microstepper_top.v @@ -46,7 +46,10 @@ module microstepper_top ( wire [9:0] off_timer1; wire [7:0] minimum_on_timer0; wire [7:0] minimum_on_timer1; +<<<<<<< HEAD wire off_timer1_done; +======= +>>>>>>> timer fixes and missing wires microstepper_control microstepper_control0( .clk(clk), @@ -74,6 +77,11 @@ module microstepper_top ( .s4(s4), .offtimer_en0(offtimer_en0), .offtimer_en1(offtimer_en1), +<<<<<<< HEAD +======= + .a_starting(a_starting), + .b_starting(b_starting), +>>>>>>> timer fixes and missing wires .phase_ct(phase_ct), .blank_timer0(blank_timer0), .blank_timer1(blank_timer1), @@ -83,12 +91,16 @@ module microstepper_top ( .minimum_on_timer1(minimum_on_timer1), ); +<<<<<<< HEAD wire [10:0] Woff_timer0_done; wire [10:0] off_timer0_done; mytimer_10 #( .WIDTH(10) ) offtimer0 ( +======= + mytimer_10 offtimer0 ( +>>>>>>> timer fixes and missing wires .clk (clk), .resetn (resetn), .start_enable(offtimer_en0), @@ -97,9 +109,7 @@ wire [10:0] off_timer0_done; .done (off_timer0_done) ); - mytimer_10 #( - .WIDTH(10) - ) offtimer1 ( + mytimer_10 offtimer1 ( .clk (clk), .resetn (resetn), .start_enable(offtimer_en1), @@ -108,9 +118,7 @@ wire [10:0] off_timer0_done; .done (off_timer1_done) ); - mytimer_8 #( - .WIDTH(8) - ) blanktimer0 ( + mytimer_8 blanktimer0 ( .clk (clk), .resetn (resetn), .start_enable(off_timer0_done), @@ -118,9 +126,7 @@ wire [10:0] off_timer0_done; .timer (blank_timer0) ); - mytimer_8 #( - .WIDTH(8) - ) blanktimer1 ( + mytimer_8 blanktimer1 ( .clk (clk), .resetn (resetn), .start_enable(off_timer1_done), @@ -128,9 +134,7 @@ wire [10:0] off_timer0_done; .timer (blank_timer1) ); - mytimer_8 #( - .WIDTH(8) - ) minimumontimer0 ( + mytimer_8 minimumontimer0 ( .clk (clk), .resetn (resetn), .start_enable(off_timer0_done), @@ -138,9 +142,7 @@ wire [10:0] off_timer0_done; .timer (minimum_on_timer0) ); - mytimer_8 #( - .WIDTH(8) - ) minimumontimer1 ( + mytimer_8 minimumontimer1 ( .clk (clk), .resetn (resetn), .start_enable(off_timer1_done), diff --git a/src/microstepper/mytimer_10.v b/src/microstepper/mytimer_10.v index 5e2ca23..a2860fc 100644 --- a/src/microstepper/mytimer_10.v +++ b/src/microstepper/mytimer_10.v @@ -7,10 +7,17 @@ module mytimer_10 ( output [WIDTH-1:0] timer, output done // single cycle timer done event ); + localparam WIDTH = 10; + + input clk; + input resetn; + input start_enable; + input [WIDTH-1:0] start_time; + output [WIDTH-1:0] timer; mytimer #( - .WIDTH(8) - ) mytimer8 ( + .WIDTH(WIDTH) + ) mytimer10 ( .clk (clk), .resetn (resetn), .start_enable(start_enable), diff --git a/src/microstepper/mytimer_8.v b/src/microstepper/mytimer_8.v index c07c98a..f1d65fe 100644 --- a/src/microstepper/mytimer_8.v +++ b/src/microstepper/mytimer_8.v @@ -7,9 +7,16 @@ module mytimer_8 ( output [WIDTH-1:0] timer, output done // single cycle timer done event ); + localparam WIDTH = 8; + + input clk; + input resetn; + input start_enable; + input [WIDTH-1:0] start_time; + output [WIDTH-1:0] timer; mytimer #( - .WIDTH(8) + .WIDTH(WIDTH) ) mytimer8 ( .clk (clk), .resetn (resetn), From 834dba42e75c7970c0953d6cbd7f3d46dad10038 Mon Sep 17 00:00:00 2001 From: johnnyr Date: Fri, 4 Dec 2020 01:27:35 -0600 Subject: [PATCH 60/71] testbench upgrades. part 1 --- sim_microstepper.ys | 4 ++++ testbench/coil.v | 30 ++++++++++++++++++++++++++++++ 2 files changed, 34 insertions(+) create mode 100644 testbench/coil.v diff --git a/sim_microstepper.ys b/sim_microstepper.ys index dda1280..029da96 100644 --- a/sim_microstepper.ys +++ b/sim_microstepper.ys @@ -11,4 +11,8 @@ read_verilog -sv testbench/microstepper_tb.v \ prep -top testbench show microstepper_top +<<<<<<< HEAD sim -n 400000 -clock clk -vcd testbench/microstepper.vcd +======= +sim -n 40000 -clock clk -vcd testbench/microstepper.vcd +>>>>>>> testbench upgrades. part 1 diff --git a/testbench/coil.v b/testbench/coil.v new file mode 100644 index 0000000..3a2c1ce --- /dev/null +++ b/testbench/coil.v @@ -0,0 +1,30 @@ +// Linear current ramp +module coil ( + input clk, + input resetn, + input s_l1, + input s_h1, + input s_l2, + input s_h2, + output [12:0] current, +); + reg [12:0] current; + reg [7:0] cnt; + + wire on = (s_l1 && s_h2) | (s_l1 && s_h2); + + always @(posedge clk) begin + if (!resetn) begin + current <= 0; + end + else begin + if ( on ) begin + current <= current + 1; + end + else begin + current <= 0; + end + end + end +endmodule +//(cnt[2]== 1) \ No newline at end of file From 6a9f76479914db66bddb64b2dd5854a7576ae808 Mon Sep 17 00:00:00 2001 From: johnnyr Date: Fri, 4 Dec 2020 01:35:29 -0600 Subject: [PATCH 61/71] reset logic for analog out, phase_ct, step dir buffer, instantiation name expansion. --- src/microstepper/microstepper_control.v | 5 +++++ src/microstepper/microstepper_top.v | 14 +------------- 2 files changed, 6 insertions(+), 13 deletions(-) diff --git a/src/microstepper/microstepper_control.v b/src/microstepper/microstepper_control.v index cafe08b..e250938 100644 --- a/src/microstepper/microstepper_control.v +++ b/src/microstepper/microstepper_control.v @@ -2,6 +2,7 @@ module microstepper_control ( input clk, input resetn, +<<<<<<< HEAD output phase_a1_l_out, output phase_a2_l_out, output phase_b1_l_out, @@ -10,6 +11,10 @@ module microstepper_control ( output phase_a2_h_out, output phase_b1_h_out, output phase_b2_h_out, +======= + output [3:0] s_l, + output [3:0] s_h, +>>>>>>> reset logic for analog out, phase_ct, step dir buffer, instantiation name expansion. input [9:0] config_fastdecay_threshold, input config_invert_highside, input config_invert_lowside, diff --git a/src/microstepper/microstepper_top.v b/src/microstepper/microstepper_top.v index e2823cf..20cc6cb 100644 --- a/src/microstepper/microstepper_top.v +++ b/src/microstepper/microstepper_top.v @@ -46,10 +46,7 @@ module microstepper_top ( wire [9:0] off_timer1; wire [7:0] minimum_on_timer0; wire [7:0] minimum_on_timer1; -<<<<<<< HEAD wire off_timer1_done; -======= ->>>>>>> timer fixes and missing wires microstepper_control microstepper_control0( .clk(clk), @@ -77,11 +74,6 @@ module microstepper_top ( .s4(s4), .offtimer_en0(offtimer_en0), .offtimer_en1(offtimer_en1), -<<<<<<< HEAD -======= - .a_starting(a_starting), - .b_starting(b_starting), ->>>>>>> timer fixes and missing wires .phase_ct(phase_ct), .blank_timer0(blank_timer0), .blank_timer1(blank_timer1), @@ -91,16 +83,12 @@ module microstepper_top ( .minimum_on_timer1(minimum_on_timer1), ); -<<<<<<< HEAD -wire [10:0] Woff_timer0_done; wire [10:0] off_timer0_done; +wire [10:0] off_timer1_done; mytimer_10 #( .WIDTH(10) ) offtimer0 ( -======= - mytimer_10 offtimer0 ( ->>>>>>> timer fixes and missing wires .clk (clk), .resetn (resetn), .start_enable(offtimer_en0), From d4bfad754e340292a47660907fea20e78073ed1e Mon Sep 17 00:00:00 2001 From: johnnyr Date: Fri, 4 Dec 2020 19:10:59 -0600 Subject: [PATCH 62/71] testbench debugging --- testbench/coil.v | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/testbench/coil.v b/testbench/coil.v index 3a2c1ce..dd8c6fe 100644 --- a/testbench/coil.v +++ b/testbench/coil.v @@ -2,16 +2,15 @@ module coil ( input clk, input resetn, + input s_l0, + input s_h0, input s_l1, input s_h1, - input s_l2, - input s_h2, output [12:0] current, ); reg [12:0] current; - reg [7:0] cnt; - wire on = (s_l1 && s_h2) | (s_l1 && s_h2); + wire on = (s_l0 && s_h1) | (s_l1 && s_h0); always @(posedge clk) begin if (!resetn) begin From 1c37721fae628db8a2df3dfa53350da6cce41d96 Mon Sep 17 00:00:00 2001 From: johnnyr Date: Fri, 4 Dec 2020 19:11:47 -0600 Subject: [PATCH 63/71] tb debug --- sim_microstepper.ys | 5 +---- src/microstepper/microstepper_control.v | 5 ----- 2 files changed, 1 insertion(+), 9 deletions(-) diff --git a/sim_microstepper.ys b/sim_microstepper.ys index 029da96..c3a032a 100644 --- a/sim_microstepper.ys +++ b/sim_microstepper.ys @@ -11,8 +11,5 @@ read_verilog -sv testbench/microstepper_tb.v \ prep -top testbench show microstepper_top -<<<<<<< HEAD sim -n 400000 -clock clk -vcd testbench/microstepper.vcd -======= -sim -n 40000 -clock clk -vcd testbench/microstepper.vcd ->>>>>>> testbench upgrades. part 1 + diff --git a/src/microstepper/microstepper_control.v b/src/microstepper/microstepper_control.v index e250938..cafe08b 100644 --- a/src/microstepper/microstepper_control.v +++ b/src/microstepper/microstepper_control.v @@ -2,7 +2,6 @@ module microstepper_control ( input clk, input resetn, -<<<<<<< HEAD output phase_a1_l_out, output phase_a2_l_out, output phase_b1_l_out, @@ -11,10 +10,6 @@ module microstepper_control ( output phase_a2_h_out, output phase_b1_h_out, output phase_b2_h_out, -======= - output [3:0] s_l, - output [3:0] s_h, ->>>>>>> reset logic for analog out, phase_ct, step dir buffer, instantiation name expansion. input [9:0] config_fastdecay_threshold, input config_invert_highside, input config_invert_lowside, From df56bcc03560f8982a290f38d3ecebf10ab79d86 Mon Sep 17 00:00:00 2001 From: johnnyr Date: Fri, 4 Dec 2020 21:11:12 -0600 Subject: [PATCH 64/71] testbench with Jason and Steve round 3 --- testbench/coil.v | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/testbench/coil.v b/testbench/coil.v index dd8c6fe..72fc19f 100644 --- a/testbench/coil.v +++ b/testbench/coil.v @@ -7,10 +7,14 @@ module coil ( input s_l1, input s_h1, output [12:0] current, + output positive, + output negative, ); reg [12:0] current; - wire on = (s_l0 && s_h1) | (s_l1 && s_h0); + wire on = (!s_l0 && !s_h1) | (!s_l1 && !s_h0); + wire positive = (!s_l0 && !s_h1); + wire negative = (!s_l1 && !s_h0); always @(posedge clk) begin if (!resetn) begin From 1cadadba597dbd52b1b927da747874c869baea18 Mon Sep 17 00:00:00 2001 From: johnnyr Date: Fri, 4 Dec 2020 21:11:39 -0600 Subject: [PATCH 65/71] patches / hacks from testbench working session --- src/microstepper/microstepper_top.v | 2 ++ src/microstepper/mytimer_10.v | 36 +++++++++++++++++------------ src/microstepper/mytimer_8.v | 36 +++++++++++++++++------------ 3 files changed, 44 insertions(+), 30 deletions(-) diff --git a/src/microstepper/microstepper_top.v b/src/microstepper/microstepper_top.v index 20cc6cb..e7c2ac8 100644 --- a/src/microstepper/microstepper_top.v +++ b/src/microstepper/microstepper_top.v @@ -81,6 +81,8 @@ module microstepper_top ( .off_timer1(off_timer1), .minimum_on_timer0(minimum_on_timer0), .minimum_on_timer1(minimum_on_timer1), +// .off_timer0_done (off_timer0_done), +// .off_timer0_done (off_timer1_done), ); wire [10:0] off_timer0_done; diff --git a/src/microstepper/mytimer_10.v b/src/microstepper/mytimer_10.v index a2860fc..431e84e 100644 --- a/src/microstepper/mytimer_10.v +++ b/src/microstepper/mytimer_10.v @@ -7,22 +7,28 @@ module mytimer_10 ( output [WIDTH-1:0] timer, output done // single cycle timer done event ); - localparam WIDTH = 10; + parameter WIDTH = 10; - input clk; - input resetn; - input start_enable; - input [WIDTH-1:0] start_time; - output [WIDTH-1:0] timer; + reg done = 0; + reg [WIDTH-1:0] counter; + reg run = 1; + assign timer = counter; - mytimer #( - .WIDTH(WIDTH) - ) mytimer10 ( - .clk (clk), - .resetn (resetn), - .start_enable(start_enable), - .start_time (start_time), - .timer (timer) - ); + always @(posedge clk) begin + if (!resetn) + counter <= 0; + else if( start_enable ) begin + counter <= start_time; + run <= 1; + end + else if( counter > 0 ) + counter <= counter - 1'b1; + else if (run) + done <= 1; + if (done) begin + run <= 0; + done <= 0; + end +end endmodule diff --git a/src/microstepper/mytimer_8.v b/src/microstepper/mytimer_8.v index f1d65fe..aacfcf8 100644 --- a/src/microstepper/mytimer_8.v +++ b/src/microstepper/mytimer_8.v @@ -7,22 +7,28 @@ module mytimer_8 ( output [WIDTH-1:0] timer, output done // single cycle timer done event ); - localparam WIDTH = 8; + parameter WIDTH = 8; - input clk; - input resetn; - input start_enable; - input [WIDTH-1:0] start_time; - output [WIDTH-1:0] timer; + reg done = 0; + reg [WIDTH-1:0] counter; + reg run = 1; + assign timer = counter; - mytimer #( - .WIDTH(WIDTH) - ) mytimer8 ( - .clk (clk), - .resetn (resetn), - .start_enable(start_enable), - .start_time (start_time), - .timer (timer) - ); + always @(posedge clk) begin + if (!resetn) + counter <= 0; + else if( start_enable ) begin + counter <= start_time; + run <= 1; + end + else if( counter > 0 ) + counter <= counter - 1'b1; + else if (run) + done <= 1; + if (done) begin + run <= 0; + done <= 0; + end +end endmodule From 5fd384ded4c08f2d18bacc941723796a3a50b299 Mon Sep 17 00:00:00 2001 From: johnnyr Date: Sat, 5 Dec 2020 00:14:50 -0600 Subject: [PATCH 66/71] more test bench patches --- testbench/coil.v | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/testbench/coil.v b/testbench/coil.v index 72fc19f..54742dc 100644 --- a/testbench/coil.v +++ b/testbench/coil.v @@ -12,6 +12,12 @@ module coil ( ); reg [12:0] current; + // For each coil of motor + // Each coil is driven by s_x1 and s_x2 + // One side s_x1 or s_x2 must be high when the other is low to be on +// wire phase_a_positive = !s_l0 && !s_h1; +// wire phase_a_negative = !s_l1 && !s_h0; +// wire off = s_l0; wire on = (!s_l0 && !s_h1) | (!s_l1 && !s_h0); wire positive = (!s_l0 && !s_h1); wire negative = (!s_l1 && !s_h0); From 82ec5a37a4093a2dbd0d9d94fac6423bcb914c0f Mon Sep 17 00:00:00 2001 From: johnnyr Date: Sun, 6 Dec 2020 21:01:10 -0600 Subject: [PATCH 67/71] debug microstepper test bench. --- sim_microstepper.ys | 1 - src/microstepper/microstepper_top.v | 2 -- src/microstepper/mytimer_10.v | 4 +++- testbench/microstepper_tb.v | 4 ++-- 4 files changed, 5 insertions(+), 6 deletions(-) diff --git a/sim_microstepper.ys b/sim_microstepper.ys index c3a032a..dda1280 100644 --- a/sim_microstepper.ys +++ b/sim_microstepper.ys @@ -12,4 +12,3 @@ read_verilog -sv testbench/microstepper_tb.v \ prep -top testbench show microstepper_top sim -n 400000 -clock clk -vcd testbench/microstepper.vcd - diff --git a/src/microstepper/microstepper_top.v b/src/microstepper/microstepper_top.v index e7c2ac8..20cc6cb 100644 --- a/src/microstepper/microstepper_top.v +++ b/src/microstepper/microstepper_top.v @@ -81,8 +81,6 @@ module microstepper_top ( .off_timer1(off_timer1), .minimum_on_timer0(minimum_on_timer0), .minimum_on_timer1(minimum_on_timer1), -// .off_timer0_done (off_timer0_done), -// .off_timer0_done (off_timer1_done), ); wire [10:0] off_timer0_done; diff --git a/src/microstepper/mytimer_10.v b/src/microstepper/mytimer_10.v index 431e84e..d285dd4 100644 --- a/src/microstepper/mytimer_10.v +++ b/src/microstepper/mytimer_10.v @@ -15,8 +15,10 @@ module mytimer_10 ( assign timer = counter; always @(posedge clk) begin - if (!resetn) + if (!resetn) begin counter <= 0; + done <= 0; + end else if( start_enable ) begin counter <= start_time; run <= 1; diff --git a/testbench/microstepper_tb.v b/testbench/microstepper_tb.v index a71aed7..f224062 100644 --- a/testbench/microstepper_tb.v +++ b/testbench/microstepper_tb.v @@ -69,8 +69,8 @@ module testbench( config_minimum_on_time = 54; config_current_threshold = 1024; config_chargepump_period = 91; - config_invert_highside = 0; - config_invert_lowside = 0; + config_invert_highside = 1; + config_invert_lowside = 1; step_clock = 0; end else begin From 8d5cce62019076f3a1a863fea8cdf91a9a23082f Mon Sep 17 00:00:00 2001 From: johnnyr Date: Sun, 6 Dec 2020 21:45:22 -0600 Subject: [PATCH 68/71] fix undeclared errors. add default_nettype none. --- testbench/microstepper_tb.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/testbench/microstepper_tb.v b/testbench/microstepper_tb.v index f224062..a71aed7 100644 --- a/testbench/microstepper_tb.v +++ b/testbench/microstepper_tb.v @@ -69,8 +69,8 @@ module testbench( config_minimum_on_time = 54; config_current_threshold = 1024; config_chargepump_period = 91; - config_invert_highside = 1; - config_invert_lowside = 1; + config_invert_highside = 0; + config_invert_lowside = 0; step_clock = 0; end else begin From af60f0cb86c77fbcfed848426de2c9faaa21c320 Mon Sep 17 00:00:00 2001 From: johnnyr Date: Mon, 7 Dec 2020 01:14:06 -0600 Subject: [PATCH 69/71] off_timer done 1 bit. cosine table static (for now); --- src/microstepper/microstepper_top.v | 4 ++-- src/rapcore.v | 1 - 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/src/microstepper/microstepper_top.v b/src/microstepper/microstepper_top.v index 20cc6cb..7bee119 100644 --- a/src/microstepper/microstepper_top.v +++ b/src/microstepper/microstepper_top.v @@ -83,8 +83,8 @@ module microstepper_top ( .minimum_on_timer1(minimum_on_timer1), ); -wire [10:0] off_timer0_done; -wire [10:0] off_timer1_done; +wire off_timer0_done; +wire off_timer1_done; mytimer_10 #( .WIDTH(10) diff --git a/src/rapcore.v b/src/rapcore.v index e6ebabf..2fea007 100644 --- a/src/rapcore.v +++ b/src/rapcore.v @@ -193,7 +193,6 @@ module rapcore ( .config_chargepump_period(config_chargepump_period), .config_invert_highside(config_invert_highside), .config_invert_lowside(config_invert_lowside), - .cos_table(cos_table), .encoder_count(encoder_count), From 5e993994bce647207fd95ce8ad7fb215cb56a149 Mon Sep 17 00:00:00 2001 From: Steve Kelly Date: Tue, 8 Dec 2020 11:08:58 -0500 Subject: [PATCH 70/71] [spifsm] cleanup state handling --- src/dda_timer.v | 8 ++++++-- src/microstepper/microstepper_control.v | 6 +++--- src/rapcore.v | 5 +---- src/spi_state_machine.v | 18 ++++++++++-------- 4 files changed, 20 insertions(+), 17 deletions(-) diff --git a/src/dda_timer.v b/src/dda_timer.v index 290553f..3a8e2d6 100644 --- a/src/dda_timer.v +++ b/src/dda_timer.v @@ -7,8 +7,8 @@ module dda_timer( input [63:0] increment, input [63:0] incrementincrement, input [`MOVE_BUFFER_SIZE:0] stepready, - output reg [`MOVE_BUFFER_SIZE:0] stepfinished, - output reg [`MOVE_BUFFER_BITS:0] moveind, // DDA buffer index + output [`MOVE_BUFFER_SIZE:0] stepfinished, + output [`MOVE_BUFFER_BITS:0] moveind, // DDA buffer index input [`MOVE_BUFFER_BITS:0] writemoveind, // State Machine index output step, `ifdef HALT @@ -27,6 +27,10 @@ module dda_timer( reg signed [63:0] increment_r; reg finishedmove = 1; // flag inidicating a move has been finished, so load next + // Buffer managment + reg [`MOVE_BUFFER_BITS:0] moveind = 0; // Move index cursor + reg [`MOVE_BUFFER_SIZE:0] stepfinished = 0; + // State managment wire processing_move = (stepfinished[moveind] ^ stepready[moveind]); wire loading_move = finishedmove & processing_move; diff --git a/src/microstepper/microstepper_control.v b/src/microstepper/microstepper_control.v index cafe08b..e755d44 100644 --- a/src/microstepper/microstepper_control.v +++ b/src/microstepper/microstepper_control.v @@ -37,9 +37,9 @@ module microstepper_control ( reg [7:0] phase_ct; reg [2:0] step_r; reg [1:0] dir_r; - + reg enable; - + always @(posedge clk) begin if (!resetn) enable <= 0; @@ -107,7 +107,7 @@ module microstepper_control ( // Half bridge high side is active // WHEN slow decay is NOT active - // AND + // AND // ( fast decay active AND would normally be off this phase ) // OR // Should be on to drive this phase / polarity (microstepper_counter) diff --git a/src/rapcore.v b/src/rapcore.v index 2fea007..6664d40 100644 --- a/src/rapcore.v +++ b/src/rapcore.v @@ -94,7 +94,7 @@ module rapcore ( // Stepper control lines wire step; wire dir; - reg enable; + wire enable; // @@ -117,9 +117,6 @@ module rapcore ( `endif `ifdef ULTIBRIDGE - wire step; - wire dir; - reg enable; microstepper_top microstepper0( .clk(CLK), .resetn( resetn), diff --git a/src/spi_state_machine.v b/src/spi_state_machine.v index d03f76b..0204fb1 100644 --- a/src/spi_state_machine.v +++ b/src/spi_state_machine.v @@ -93,7 +93,7 @@ module spi_state_machine( reg [7:0] config_chargepump_period = 91; reg config_invert_highside = 0; reg config_invert_lowside = 0; - + reg [511:0] cos_table; initial begin @@ -164,14 +164,16 @@ module spi_state_machine( end // - // Stepper Timing Setup + // Stepper Timing and Buffer Setup // - reg [`MOVE_BUFFER_BITS:0] moveind; // Move index cursor + // Move buffer + reg [`MOVE_BUFFER_BITS:0] writemoveind = 0; + wire [`MOVE_BUFFER_BITS:0] moveind; // Latching mechanism for engaging the buffered move. - reg [`MOVE_BUFFER_SIZE:0] stepready; - reg [`MOVE_BUFFER_SIZE:0] stepfinished; + reg [`MOVE_BUFFER_SIZE:0] stepready = 0; + wire [`MOVE_BUFFER_SIZE:0] stepfinished; reg [63:0] move_duration [`MOVE_BUFFER_SIZE:0]; reg [`MOVE_BUFFER_SIZE:0] dir_r; @@ -188,7 +190,7 @@ module spi_state_machine( // Step IO wire dda_step; - reg enable_r; + reg enable_r = 0; assign enable = enable_r; // Implement flow control and event pins if specified @@ -231,8 +233,7 @@ module spi_state_machine( // reg [7:0] message_word_count = 0; - reg [7:0] message_header; - reg [`MOVE_BUFFER_BITS:0] writemoveind = 0; + reg [7:0] message_header = 0; // Encoder reg signed [63:0] encoder_store; // Snapshot for SPI comms @@ -348,6 +349,7 @@ module spi_state_machine( message_word_count <= 0; stepready[writemoveind] <= ~stepready[writemoveind]; writemoveind <= writemoveind + 1'b1; + enable_r <= 1; message_header <= 8'b0; // Reset Message Header `ifdef FORMAL assert(writemoveind <= `MOVE_BUFFER_SIZE); From 767e1a79ead673397c5ae00a8947a2552c2b8931 Mon Sep 17 00:00:00 2001 From: Steve Kelly Date: Tue, 8 Dec 2020 12:00:40 -0500 Subject: [PATCH 71/71] [spifsm] dont enable after move send --- src/spi_state_machine.v | 1 - 1 file changed, 1 deletion(-) diff --git a/src/spi_state_machine.v b/src/spi_state_machine.v index 0204fb1..480d845 100644 --- a/src/spi_state_machine.v +++ b/src/spi_state_machine.v @@ -349,7 +349,6 @@ module spi_state_machine( message_word_count <= 0; stepready[writemoveind] <= ~stepready[writemoveind]; writemoveind <= writemoveind + 1'b1; - enable_r <= 1; message_header <= 8'b0; // Reset Message Header `ifdef FORMAL assert(writemoveind <= `MOVE_BUFFER_SIZE);