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psp-iom.c
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psp-iom.c
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/** @file
* PSP Emulator - I/O manager.
*/
/*
* Copyright (C) 2020 Alexander Eichner <[email protected]>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <stdlib.h>
#include <string.h>
#include <stdio.h>
#include <common/types.h>
#include <common/cdefs.h>
#include <common/status.h>
#include <psp-iom.h>
#include <psp-trace.h>
/** Pointer to the internal I/O manager state. */
typedef struct PSPIOMINT *PPSPIOMINT;
/**
* Trace handler type.
*/
typedef enum PSPIOMTRACETYPE
{
/** Invalid type. */
PSPIOMTRACETYPE_INVALID = 0,
/** MMIO trace handler. */
PSPIOMTRACETYPE_MMIO,
/** SMN trace handler. */
PSPIOMTRACETYPE_SMN,
/** X86 trace handler. */
PSPIOMTRACETYPE_X86,
/** 32bit hack. */
PSPIOMTRACETYPE_32BIT_HACK = 0x7fffffff
} PSPIOMTRACETYPE;
/** Pointer to a trace handler type. */
typedef PSPIOMTRACETYPE *PPSPIOMTRACETYPE;
/**
* Trace handler record.
*/
typedef struct PSPIOMTPINT
{
/** Pointer to the next record. */
struct PSPIOMTPINT *pNext;
/** I/O manager this belongs to. */
PPSPIOMINT pIoMgr;
/** Access size. */
size_t cbAccess;
/** Flags given during registration. */
uint32_t fFlags;
/** Opaque user data to pass to the handler. */
void *pvUser;
/** Trace type. */
PSPIOMTRACETYPE enmType;
/** Type dependent data. */
union
{
/** MMIO trace. */
struct
{
/** The start MMIO address to hit at. */
PSPADDR PspAddrMmioStart;
/** The start MMIO address to stop hitting at. */
PSPADDR PspAddrMmioEnd;
/** The handler to call. */
PFNPSPIOMMMIOTRACE pfnTrace;
} Mmio;
/** SMN trace. */
struct
{
/** The start SMN address to hit at. */
SMNADDR SmnAddrStart;
/** The start SMN address to stop hitting at. */
SMNADDR SmnAddrEnd;
/** The handler to call. */
PFNPSPIOMSMNTRACE pfnTrace;
} Smn;
/** x86 trace. */
struct
{
/** The start x86 physical address to hit at. */
X86PADDR PhysX86AddrStart;
/** The start x86 physical address to stop hitting at. */
X86PADDR PhysX86AddrEnd;
/** The handler to call. */
PFNPSPIOMX86TRACE pfnTrace;
} X86;
} u;
} PSPIOMTPINT;
/** Pointer to a trace handler record. */
typedef PSPIOMTPINT *PPSPIOMTPINT;
/** Pointer to a const trace handler record. */
typedef const PSPIOMTPINT *PCPSPIOMTPINT;
/**
* A region type
*/
typedef enum PSPIOMREGIONTYPE
{
/** Invalid type, do not use. */
PSPIOMREGIONTYPE_INVALID = 0,
/** PSP MMIO region. */
PSPIOMREGIONTYPE_PSP_MMIO,
/** SMN region. */
PSPIOMREGIONTYPE_SMN,
/** X86 MMIO region. */
PSPIOMREGIONTYPE_X86_MMIO,
/** X86 memory region. */
PSPIOMREGIONTYPE_X86_MEM,
/** 32bit hack. */
PSPIOMREGIONTYPE_32BIT_HACK = 0x7fffffff
} PSPIOMREGIONTYPE;
/** Pointer to a region type. */
typedef PSPIOMREGIONTYPE *PPSPIOMREGIONTYPE;
/**
* A internal region handle.
*/
typedef struct PSPIOMREGIONHANDLEINT
{
/** Owning I/O manager instance. */
PPSPIOMINT pIoMgr;
/** Region type. */
PSPIOMREGIONTYPE enmType;
/** Pointer to the next region. */
struct PSPIOMREGIONHANDLEINT *pNext;
/** Opaque user data to pass in the callbacks. */
void *pvUser;
/** Description for this region. */
const char *pszDesc;
/** Flags for this region. */
uint32_t fFlags;
/** Type dependent data. */
union
{
/** MMIO region. */
struct
{
/** Start address. */
PSPADDR PspAddrMmioStart;
/** Size of the region. */
size_t cbMmio;
/** Read callback. */
PFNPSPIOMMMIOREAD pfnRead;
/** Write callback. */
PFNPSPIOMMMIOWRITE pfnWrite;
} Mmio;
/** SMN region. */
struct
{
/** Start address. */
SMNADDR SmnAddrStart;
/** Size of the region. */
size_t cbSmn;
/** Read callback. */
PFNPSPIOMSMNREAD pfnRead;
/** Write callback. */
PFNPSPIOMSMNWRITE pfnWrite;
} Smn;
/** X86 MMIO/Memory region. */
struct
{
/** Start address. */
X86PADDR PhysX86AddrStart;
/** Size of the region. */
size_t cbX86;
/** Type dependent data. */
union
{
/** MMIO specific data. */
struct
{
/** Read callback. */
PFNPSPIOMX86MMIOREAD pfnRead;
/** Write callback. */
PFNPSPIOMX86MMIOWRITE pfnWrite;
} Mmio;
/** Memory specific data. */
struct
{
/** Pointer to the next exectuable memory region (only valid if fCanExec is true). */
struct PSPIOMREGIONHANDLEINT *pExecNext;
/** Fetch callback. */
PFNPSPIOMX86MEMFETCH pfnFetch;
/** Pointer to memory backing this region. */
void *pvMapping;
/** Amount of memory currently allocated. */
size_t cbAlloc;
/** Size of the region initialized with valid data so far. */
size_t cbValid;
/** Size of the highest written area so far (exclusive, defines range of memory to sync back). */
size_t cbWritten;
/** Flag whether the memory should be made executable to the core. */
bool fCanExec;
} Mem;
} u;
} X86;
} u;
} PSPIOMREGIONHANDLEINT;
/** Pointer to an internal region handle. */
typedef PSPIOMREGIONHANDLEINT *PPSPIOMREGIONHANDLEINT;
/** The region has a read handler. */
#define PSP_IOM_REGION_F_READ BIT(0)
/** The region has a write handler. */
#define PSP_IOM_REGION_F_WRITE BIT(1)
/** Forward declaration of a X86 mapping control slot pointer. */
typedef struct PSPIOMX86MAPCTRLSLOT *PPSPIOMX86MAPCTRLSLOT;
/**
* X86 split MMIO descriptor.
*/
typedef struct PSPIOMX86MMIOSPLIT
{
/** Owning x86 mapping control slot. */
PPSPIOMX86MAPCTRLSLOT pX86MapSlot;
/** Start PSP MMIO address of the split region. */
PSPADDR PspAddrMmioStart;
/** Size of the split region. */
size_t cbMmio;
} PSPIOMX86MMIOSPLIT;
/** Pointer to a X86 split MMIO descriptor. */
typedef PSPIOMX86MMIOSPLIT *PPSPIOMX86MMIOSPLIT;
/** Pointer to a const X86 split MMIO descriptor. */
typedef const PSPIOMX86MMIOSPLIT *PCPSPIOMX86MMIOSPLIT;
/**
* X86 mapping control slot.
*/
typedef struct PSPIOMX86MAPCTRLSLOT
{
/** Pointer to the owning I/O manager instance. */
PPSPIOMINT pIoMgr;
/** Base MMIO address this slot starts at. */
PSPADDR PspAddrMmioStart;
/** Size of the slot (should be equal for all). */
size_t cbMmio;
/** The x86 physical base address currently mapped. */
X86PADDR PhysX86Base;
/** The x86 memory region mapped executable,
* We only allow only one for now. */
PPSPIOMREGIONHANDLEINT pX86MemExec;
/** PSP address the memory region is mapped to. */
PSPADDR PspAddrMemExecStart;
/** Size of the executable memory region. */
size_t cbMemExec;
/** The core tracepoint handle to be able to catch reads and writes for registered
* I/O trace points when a memory region is mapped executable. */
PSPCORETP hMemExecTpRw;
/* Split MMIO region data if any (before and after executable region). */
PSPIOMX86MMIOSPLIT aSplitMmio[2];
/** @name Register interface accessible from MMIO space.
* @{ */
uint32_t u32RegX86BaseAddr;
uint32_t u32RegUnk1;
uint32_t u32RegUnk2;
uint32_t u32RegUnk3;
uint32_t u32RegUnk4;
uint32_t u32RegUnk5;
/** @} */
} PSPIOMX86MAPCTRLSLOT;
/**
* The internal I/O manager manager state.
*/
typedef struct PSPIOMINT
{
/** The head of list of MMIO regions (@todo AVL tree?). */
PPSPIOMREGIONHANDLEINT pMmioHead;
/** The head of list of SMN regions (@todo AVL tree?). */
PPSPIOMREGIONHANDLEINT pSmnHead;
/** The head of list of X86 regions (@todo AVL tree?). */
PPSPIOMREGIONHANDLEINT pX86Head;
/** The head of list of X86 memory regions with exec permissions. */
PPSPIOMREGIONHANDLEINT pX86MemExecHead;
/** Lowest MMIO address assigned to a region (for faster lookup). */
PSPADDR PspAddrMmioLowest;
/** Highes MMIO address assigned to a region (inclusive). */
PSPADDR PspAddrMmioHighest;
/** Lowest SMN address assigned to a device (for faster lookup). */
SMNADDR SmnAddrLowest;
/** Highes SMN address assigned to a device (inclusive). */
SMNADDR SmnAddrHighest;
/** Lowest X86 address assigned to a region (for faster lookup). */
X86PADDR PhysX86AddrLowest;
/** Highes X86 address assigned to a region (inclusive). */
X86PADDR PhysX86AddrHighest;
/** The PSP core handle this I/O manager is assigned to. */
PSPCORE hPspCore;
/** The currently mapped SMN base address for each slot (written by the control interface). */
SMNADDR aSmnAddrBaseSlots[32];
/** The MMIO region handle for the SMN control register interface. */
PPSPIOMREGIONHANDLEINT pMmioRegionSmnCtrl;
/** The MMIO region handle for the X86 mapping control register interface. */
PPSPIOMREGIONHANDLEINT pMmioRegionX86MapCtrl;
/** The MMIO region handle for the X86 mapping control register interface - second part. */
PPSPIOMREGIONHANDLEINT pMmioRegionX86MapCtrl2;
/** The MMIO region handle for the X86 mapping control register interface - third part. */
PPSPIOMREGIONHANDLEINT pMmioRegionX86MapCtrl3;
/** X86 mapping control slots. */
PSPIOMX86MAPCTRLSLOT aX86MapCtrlSlots[62];
/** Callback for unassigned MMIO reads. */
PFNPSPIOMMMIOREAD pfnMmioUnassignedRead;
/** Callback for unassigned MMIO writes. */
PFNPSPIOMMMIOWRITE pfnMmioUnassignedWrite;
/** Opaque user data for the unassigned MMIO read/write callbacks. */
void *pvUserMmioUnassigned;
/** Description used for access tracing. */
const char *pszMmioUnassignedDesc;
/** Callback for unassigned SMN reads. */
PFNPSPIOMSMNREAD pfnSmnUnassignedRead;
/** Callback for unassigned SMN writes. */
PFNPSPIOMSMNWRITE pfnSmnUnassignedWrite;
/** Opaque user data for the unassigned SMN read/write callbacks. */
void *pvUserSmnUnassigned;
/** Description used for access tracing. */
const char *pszSmnUnassignedDesc;
/** Callback for unassigned x86 reads. */
PFNPSPIOMX86READ pfnX86UnassignedRead;
/** Callback for unassigned x86 writes. */
PFNPSPIOMX86WRITE pfnX86UnassignedWrite;
/** Opaque user data for the unassigned x86 read/write callbacks. */
void *pvUserX86Unassigned;
/** Description used for access tracing. */
const char *pszX86UnassignedDesc;
/** Registered trace points. */
PPSPIOMTPINT pTpHead;
/** Flag whether to log all accesses or only ones to unassigned regions. */
bool fLogAllAccesses;
} PSPIOMINT;
/**
* Finds the device assigned to the given MMIO address or NULL if there is nothing assigned.
*
* @returns Pointer to the device assigned to the MMIO address or NULL if none was found.
* @param pThis The I/O manager.
* @param PspAddrMmio The absolute MMIO address to look for.
*/
static PPSPIOMREGIONHANDLEINT pspEmuIomMmioFindRegion(PPSPIOMINT pThis, PSPADDR PspAddrMmio)
{
if ( PspAddrMmio < pThis->PspAddrMmioLowest
|| PspAddrMmio > pThis->PspAddrMmioHighest)
return NULL;
/* Slow path. */
PPSPIOMREGIONHANDLEINT pCur = pThis->pMmioHead;
while (pCur)
{
if ( PspAddrMmio >= pCur->u.Mmio.PspAddrMmioStart
&& PspAddrMmio < pCur->u.Mmio.PspAddrMmioStart + pCur->u.Mmio.cbMmio)
return pCur;
pCur = pCur->pNext;
}
return NULL;
}
/**
* Finds the device assigned to the given SMN address or NULL if there is nothing assigned.
*
* @returns Pointer to the device assigned to the SMN address or NULL if none was found.
* @param pThis The I/O manager.
* @param SmnAddr The absolute SMN address to look for.
*/
static PPSPIOMREGIONHANDLEINT pspEmuIomSmnFindRegion(PPSPIOMINT pThis, SMNADDR SmnAddr)
{
if ( SmnAddr < pThis->SmnAddrLowest
|| SmnAddr > pThis->SmnAddrHighest)
return NULL;
/* Slow path. */
PPSPIOMREGIONHANDLEINT pCur = pThis->pSmnHead;
while (pCur)
{
if ( SmnAddr >= pCur->u.Smn.SmnAddrStart
&& SmnAddr < pCur->u.Smn.SmnAddrStart + pCur->u.Smn.cbSmn)
return pCur;
pCur = pCur->pNext;
}
return NULL;
}
/**
* Returns the next trace point from the given start matching the given parameters.
*
* @returns Pointer to matching trace point or NULL if none exists.
* @param pFirst The first trace pint record to check.
* @param enmType Trace point should match the given type.
* @param cbAccess Access width, 1, 2 or 4 byte.
* @param fFlagsRw Read/Write flags matching the trace point.
* @param fFlagsAp Access point (before/after) flags matching the trace point.
*/
static PCPSPIOMTPINT pspEmuIomTpFindNext(PCPSPIOMTPINT pFirst, PSPIOMTRACETYPE enmType, size_t cbAccess,
uint32_t fFlagsRw, uint32_t fFlagsAp)
{
while (pFirst)
{
if ( pFirst->enmType == enmType
&& ( pFirst->cbAccess == cbAccess
|| !pFirst->cbAccess) /* 0 matches all access widths. */
&& (pFirst->fFlags & fFlagsRw) != 0
&& (pFirst->fFlags & fFlagsAp) != 0)
return pFirst;
pFirst = pFirst->pNext;
}
return NULL;
}
static SMNADDR pspEmuIomGetSmnAddrFromSlotAndOffset(PPSPIOMINT pThis, PSPADDR offMmio)
{
/* Each slot is 1MB big, so get the slot number by shifting the appropriate bits to the right. */
uint32_t idxSlot = offMmio >> 20;
uint32_t offSlot = offMmio & (_1M - 1);
if (idxSlot < ELEMENTS(pThis->aSmnAddrBaseSlots))
return pThis->aSmnAddrBaseSlots[idxSlot] | offSlot;
else
printf("ERROR: SMN slot index out of range (is %u, max is %lu)\n", idxSlot, ELEMENTS(pThis->aSmnAddrBaseSlots));
return 0;
}
/**
* Logs a read from the given region to the tracer.
*
* @returns nothing.
* @param pThis I/O manager instance.
* @param pRegion The region or NULL if unassigned.
* @param enmOrigin The trace event origin.
* @param u64Addr The address of the region being read from.
* @param pvDst The data being read.
* @param cbRead Number of bytes read.
*/
static void pspEmuIomTraceRegionRead(PPSPIOMINT pThis, PPSPIOMREGIONHANDLEINT pRegion, PSPTRACEEVTORIGIN enmEvtOrigin,
uint64_t u64Addr, const void *pvDst, size_t cbRead)
{
PSPTRACEEVTSEVERITY enmSeverity = PSPTRACEEVTSEVERITY_INFO;
const char *pszRegId = NULL;
if ( !pRegion
|| !(pRegion->fFlags & PSP_IOM_REGION_F_READ)) /* Writeonly regions get treated as unassigned for now. */
{
pszRegId = "<UNASSIGNED>";
switch (enmEvtOrigin)
{
case PSPTRACEEVTORIGIN_MMIO:
if (pThis->pszMmioUnassignedDesc)
pszRegId = pThis->pszMmioUnassignedDesc;
break;
case PSPTRACEEVTORIGIN_SMN:
if (pThis->pszSmnUnassignedDesc)
pszRegId = pThis->pszSmnUnassignedDesc;
break;
case PSPTRACEEVTORIGIN_X86:
if (pThis->pszX86UnassignedDesc)
pszRegId = pThis->pszX86UnassignedDesc;
break;
default:
break;
}
enmSeverity = PSPTRACEEVTSEVERITY_WARNING;
}
else if (pThis->fLogAllAccesses)
{
if (!pRegion->pszDesc)
pszRegId = "<UNKNOWN>";
else
pszRegId = pRegion->pszDesc;
}
if (pszRegId)
PSPEmuTraceEvtAddDevRead(NULL, enmSeverity, enmEvtOrigin, pszRegId, u64Addr, pvDst, cbRead);
}
/**
* Logs a write to the given region to the tracer.
*
* @returns nothing.
* @param pThis I/O manager instance.
* @param pRegion The region or NULL if unassigned.
* @param enmOrigin The trace event origin.
* @param u64Addr The address of the region being written to.
* @param pvData The data being written.
* @param cbWrite Number of bytes written.
*/
static void pspEmuIomTraceRegionWrite(PPSPIOMINT pThis, PPSPIOMREGIONHANDLEINT pRegion, PSPTRACEEVTORIGIN enmEvtOrigin,
uint64_t u64Addr, const void *pvData, size_t cbWrite)
{
PSPTRACEEVTSEVERITY enmSeverity = PSPTRACEEVTSEVERITY_INFO;
const char *pszRegId = NULL;
if ( !pRegion
|| !(pRegion->fFlags & PSP_IOM_REGION_F_WRITE)) /* Readonly regions get treated as unassigned for now. */
{
pszRegId = "<UNASSIGNED>";
switch (enmEvtOrigin)
{
case PSPTRACEEVTORIGIN_MMIO:
if (pThis->pszMmioUnassignedDesc)
pszRegId = pThis->pszMmioUnassignedDesc;
break;
case PSPTRACEEVTORIGIN_SMN:
if (pThis->pszSmnUnassignedDesc)
pszRegId = pThis->pszSmnUnassignedDesc;
break;
case PSPTRACEEVTORIGIN_X86:
if (pThis->pszX86UnassignedDesc)
pszRegId = pThis->pszX86UnassignedDesc;
break;
default:
break;
}
enmSeverity = PSPTRACEEVTSEVERITY_WARNING;
}
else if (pThis->fLogAllAccesses)
{
if (!pRegion->pszDesc)
pszRegId = "<UNKNOWN>";
else
pszRegId = pRegion->pszDesc;
}
if (pszRegId)
PSPEmuTraceEvtAddDevWrite(NULL, enmSeverity, enmEvtOrigin, pszRegId, u64Addr, pvData, cbWrite);
}
/**
* Calls all matching SMN trace points for the given access pattern.
*
* @returns nothing.
* @param pThis The I/O manager.
* @param SmnAddr SMN address which got hit.
* @param pRegion The region registered for this address if any, NULL if unassigned.
* @param cbAccess Access width.
* @param pvVal The value for the access.
* @param fFlagsRw Read/Write flags matching the trace point.
* @param fFlagsAp Access point (before/after) flags matching the trace point.
*/
static void pspEmuIomSmnTpCall(PPSPIOMINT pThis, SMNADDR SmnAddr, PPSPIOMREGIONHANDLEINT pRegion, size_t cbAccess, const void *pvVal,
uint32_t fFlagsRw, uint32_t fFlagsAp)
{
PCPSPIOMTPINT pTp = pThis->pTpHead;
for (;;)
{
pTp = pspEmuIomTpFindNext(pTp, PSPIOMTRACETYPE_SMN, cbAccess, fFlagsRw, fFlagsAp);
if (!pTp)
break;
if ( SmnAddr >= pTp->u.Smn.SmnAddrStart
&& SmnAddr <= pTp->u.Smn.SmnAddrEnd)
pTp->u.Smn.pfnTrace(SmnAddr,
pRegion ? NULL : NULL, /** @todo Description */
pRegion ? SmnAddr - pRegion->u.Smn.SmnAddrStart : 0,
cbAccess,
pvVal,
fFlagsRw | fFlagsAp,
pTp->pvUser);
pTp = pTp->pNext;
}
}
/**
* Calls all matching MMIO trace points for the given access pattern.
*
* @returns nothing.
* @param pThis The I/O manager.
* @param PspAddrMmio MMIO address which got hit.
* @param pRegion The region registered for this address if any, NULL if unassigned.
* @param cbAccess Access width.
* @param pvVal The value for the access.
* @param fFlagsRw Read/Write flags matching the trace point.
* @param fFlagsAp Access point (before/after) flags matching the trace point.
*/
static void pspEmuIomMmioTpCall(PPSPIOMINT pThis, PSPADDR PspAddrMmio, PPSPIOMREGIONHANDLEINT pRegion, size_t cbAccess, const void *pvVal,
uint32_t fFlagsRw, uint32_t fFlagsAp)
{
PCPSPIOMTPINT pTp = pThis->pTpHead;
for (;;)
{
pTp = pspEmuIomTpFindNext(pTp, PSPIOMTRACETYPE_MMIO, cbAccess, fFlagsRw, fFlagsAp);
if (!pTp)
break;
if ( PspAddrMmio >= pTp->u.Mmio.PspAddrMmioStart
&& PspAddrMmio <= pTp->u.Mmio.PspAddrMmioEnd)
pTp->u.Mmio.pfnTrace(PspAddrMmio,
pRegion ? NULL : NULL, /** @todo Description */
pRegion ? PspAddrMmio - pRegion->u.Mmio.PspAddrMmioStart : 0,
cbAccess,
pvVal,
fFlagsRw | fFlagsAp,
pTp->pvUser);
pTp = pTp->pNext;
}
}
/**
* Calls all matching x86 trace points for the given access pattern.
*
* @returns nothing.
* @param pThis The I/O manager.
* @param PhysX86Addr Physical X86 address which got hit.
* @param pRegion The region registered for this address if any, NULL if unassigned.
* @param cbAccess Access width.
* @param pvVal The value for the access.
* @param fFlagsRw Read/Write flags matching the trace point.
* @param fFlagsAp Access point (before/after) flags matching the trace point.
*/
static void pspEmuIomX86TpCall(PPSPIOMINT pThis, X86PADDR PhysX86Addr, PPSPIOMREGIONHANDLEINT pRegion, size_t cbAccess, const void *pvVal,
uint32_t fFlagsRw, uint32_t fFlagsAp)
{
PCPSPIOMTPINT pTp = pThis->pTpHead;
for (;;)
{
pTp = pspEmuIomTpFindNext(pTp, PSPIOMTRACETYPE_X86, cbAccess, fFlagsRw, fFlagsAp);
if (!pTp)
break;
if ( PhysX86Addr >= pTp->u.X86.PhysX86AddrStart
&& PhysX86Addr <= pTp->u.X86.PhysX86AddrEnd)
pTp->u.X86.pfnTrace(PhysX86Addr,
pRegion ? NULL : NULL, /** @todo Description */
pRegion ? PhysX86Addr - pRegion->u.X86.PhysX86AddrStart : 0,
cbAccess,
pvVal,
fFlagsRw | fFlagsAp,
pTp->pvUser);
pTp = pTp->pNext;
}
}
/**
* Ensures that the mapping is initialized properly for the given access.
*
* @returns Status code.
* @param pX86Region The region being acccessed.
* @param offX86Mem Offset where the access starts.
* @param cbAccess Number of bytes being accessed.
*/
static int pspEmuIoMgrX86MemEnsureMapping(PPSPIOMREGIONHANDLEINT pX86Region, X86PADDR offX86Mem, size_t cbAccess)
{
int rc = 0;
/* Check whether the data at that address is already in memory and fetch it if required. */
if (offX86Mem + cbAccess > pX86Region->u.X86.u.Mem.cbValid)
{
/* We cache always at 1K aligned segments. */
size_t cbFetch = offX86Mem + cbAccess - pX86Region->u.X86.u.Mem.cbValid;
cbFetch = MIN((cbFetch + _1K) & ~(_1K - 1), pX86Region->u.X86.cbX86 - pX86Region->u.X86.u.Mem.cbValid);
/* Increase the mapping memory. */
void *pvNew = realloc(pX86Region->u.X86.u.Mem.pvMapping, pX86Region->u.X86.u.Mem.cbAlloc + cbFetch);
if (pvNew)
{
void *pvInit = (uint8_t *)pvNew + pX86Region->u.X86.u.Mem.cbValid;
pX86Region->u.X86.u.Mem.pvMapping = pvNew;
pX86Region->u.X86.u.Mem.cbAlloc += cbFetch;
/* Fetch initial memory content or just zero the memory if no callback is provided. */
if (pX86Region->u.X86.u.Mem.pfnFetch)
pX86Region->u.X86.u.Mem.pfnFetch(pX86Region->u.X86.u.Mem.cbValid, cbFetch, pvInit,
pX86Region->pvUser);
else
memset(pvInit, 0, cbFetch);
pX86Region->u.X86.u.Mem.cbValid += cbFetch;
return rc;
}
else
rc = -1;
}
return rc;
}
/**
* Read worker for a given X86 memory region, doing the fetching etc.
*
* @returns Status code.
* @param pThis The I/O manager instance owning the given X86 region.
* @param pX86Region The X86 memory region to read from.
* @param offX86Mem Offset from the start of the region to read from.
* @param pvDst Where to read into.
* @param cbRead Number of bytes to read.
*/
static int pspEmuIoMgrX86MemReadWorker(PPSPIOMINT pThis, PPSPIOMREGIONHANDLEINT pX86Region, X86PADDR offX86Mem, void *pvDst, size_t cbRead)
{
int rc = pspEmuIoMgrX86MemEnsureMapping(pX86Region, offX86Mem, cbRead);
if (!rc)
memcpy(pvDst, (uint8_t *)pX86Region->u.X86.u.Mem.pvMapping + offX86Mem, cbRead);
return rc;
}
/**
* Write worker for a given X86 memory region.
*
* @returns Status code.
* @param pThis The I/O manager instance owning the given X86 region.
* @param pX86Region The X86 memory region to write to.
* @param offX86Mem Offset from the start of the region to write to.
* @param pvSrc What to write.
* @param cbWrite Number of bytes to write.
*/
static int pspEmuIoMgrX86MemWriteWorker(PPSPIOMINT pThis, PPSPIOMREGIONHANDLEINT pX86Region, X86PADDR offX86Mem, const void *pvSrc, size_t cbWrite)
{
int rc = pspEmuIoMgrX86MemEnsureMapping(pX86Region, offX86Mem, cbWrite);
if (!rc)
{
memcpy((uint8_t *)pX86Region->u.X86.u.Mem.pvMapping + offX86Mem, pvSrc, cbWrite);
if (offX86Mem + cbWrite > pX86Region->u.X86.u.Mem.cbWritten)
pX86Region->u.X86.u.Mem.cbWritten = offX86Mem + cbWrite;
}
return rc;
}
/**
* Reads from the given SMN based region.
*
* @returns nothing.
* @param pThis The I/O manager instance data.
* @param pRegion The region to read from.
* @param SmnAddr Absolute SMN address being read from.
* @param cbRead How much to read.
* @param pvDst Where to store the read data.
*/
static void pspEmuIomSmnRegionRead(PPSPIOMINT pThis, PPSPIOMREGIONHANDLEINT pRegion, SMNADDR SmnAddr, size_t cbRead, void *pvDst)
{
pspEmuIomSmnTpCall(pThis, SmnAddr, pRegion, cbRead, pvDst, PSPEMU_IOM_TRACE_F_READ, PSPEMU_IOM_TRACE_F_BEFORE);
if (pRegion)
{
if (pRegion->u.Smn.pfnRead)
pRegion->u.Smn.pfnRead(SmnAddr - pRegion->u.Smn.SmnAddrStart, cbRead, pvDst, pRegion->pvUser);
else
memset(pvDst, 0, cbRead);
}
else if (pThis->pfnSmnUnassignedRead)
pThis->pfnSmnUnassignedRead(SmnAddr, cbRead, pvDst, pThis->pvUserSmnUnassigned);
else
memset(pvDst, 0, cbRead);
pspEmuIomTraceRegionRead(pThis, pRegion, PSPTRACEEVTORIGIN_SMN, SmnAddr, pvDst, cbRead);
pspEmuIomSmnTpCall(pThis, SmnAddr, pRegion, cbRead, pvDst, PSPEMU_IOM_TRACE_F_READ, PSPEMU_IOM_TRACE_F_AFTER);
}
/**
* Writes to the given SMN based region.
*
* @returns nothing.
* @param pThis The I/O manager instance data.
* @param pRegion The region to read from.
* @param SmnAddr Absolute SMN address being written to.
* @param cbWrite How much to write.
* @param pvSrc The data to write.
*/
static void pspEmuIomSmnRegionWrite(PPSPIOMINT pThis, PPSPIOMREGIONHANDLEINT pRegion, SMNADDR SmnAddr, size_t cbWrite, const void *pvSrc)
{
pspEmuIomTraceRegionWrite(pThis, pRegion, PSPTRACEEVTORIGIN_SMN, SmnAddr, pvSrc, cbWrite);
pspEmuIomSmnTpCall(pThis, SmnAddr, pRegion, cbWrite, pvSrc, PSPEMU_IOM_TRACE_F_WRITE, PSPEMU_IOM_TRACE_F_BEFORE);
if (pRegion)
{
if (pRegion->u.Smn.pfnWrite)
pRegion->u.Smn.pfnWrite(SmnAddr - pRegion->u.Smn.SmnAddrStart, cbWrite, pvSrc, pRegion->pvUser);
}
else if (pThis->pfnSmnUnassignedWrite)
pThis->pfnSmnUnassignedWrite(SmnAddr, cbWrite, pvSrc, pThis->pvUserSmnUnassigned);
pspEmuIomSmnTpCall(pThis, SmnAddr, pRegion, cbWrite, pvSrc, PSPEMU_IOM_TRACE_F_WRITE, PSPEMU_IOM_TRACE_F_AFTER);
}
/**
* Reads from the given MMIO based region.
*
* @returns nothing.
* @param pThis The I/O manager instance data.
* @param pRegion The region to read from.
* @param PspAddrMmio Absolute MMIO address being read from.
* @param cbRead How much to read.
* @param pvDst Where to store the read data.
*/
static void pspEmuIomMmioRegionRead(PPSPIOMINT pThis, PPSPIOMREGIONHANDLEINT pRegion, PSPADDR PspAddrMmio, size_t cbRead, void *pvDst)
{
pspEmuIomMmioTpCall(pThis, PspAddrMmio, pRegion, cbRead, pvDst, PSPEMU_IOM_TRACE_F_READ, PSPEMU_IOM_TRACE_F_BEFORE);
if (pRegion)
{
if (pRegion->u.Mmio.pfnRead)
pRegion->u.Mmio.pfnRead(PspAddrMmio - pRegion->u.Mmio.PspAddrMmioStart, cbRead, pvDst, pRegion->pvUser);
else
memset(pvDst, 0, cbRead);
}
else if (pThis->pfnMmioUnassignedRead)
pThis->pfnMmioUnassignedRead(PspAddrMmio, cbRead, pvDst, pThis->pvUserMmioUnassigned);
else
memset(pvDst, 0, cbRead);
pspEmuIomTraceRegionRead(pThis, pRegion, PSPTRACEEVTORIGIN_MMIO, PspAddrMmio, pvDst, cbRead);
pspEmuIomMmioTpCall(pThis, PspAddrMmio, pRegion, cbRead, pvDst, PSPEMU_IOM_TRACE_F_READ, PSPEMU_IOM_TRACE_F_AFTER);
}
/**
* Writes to the given MMIO based region.
*
* @returns nothing.
* @param pThis The I/O manager instance data.
* @param pRegion The region to read from.
* @param PspAddrMmio Absolute MMIO address being written to.
* @param cbWrite How much to write.
* @param pvSrc The data to write.
*/
static void pspEmuIomMmioRegionWrite(PPSPIOMINT pThis, PPSPIOMREGIONHANDLEINT pRegion, PSPADDR PspAddrMmio, size_t cbWrite, const void *pvSrc)
{
pspEmuIomTraceRegionWrite(pThis, pRegion, PSPTRACEEVTORIGIN_MMIO, PspAddrMmio, pvSrc, cbWrite);
pspEmuIomMmioTpCall(pThis, PspAddrMmio, pRegion, cbWrite, pvSrc, PSPEMU_IOM_TRACE_F_WRITE, PSPEMU_IOM_TRACE_F_BEFORE);
if (pRegion)
{
if (pRegion->u.Mmio.pfnWrite)
pRegion->u.Mmio.pfnWrite(PspAddrMmio - pRegion->u.Mmio.PspAddrMmioStart, cbWrite, pvSrc, pRegion->pvUser);
}
else if (pThis->pfnMmioUnassignedWrite)
pThis->pfnMmioUnassignedWrite(PspAddrMmio, cbWrite, pvSrc, pThis->pvUserMmioUnassigned);
pspEmuIomMmioTpCall(pThis, PspAddrMmio, pRegion, cbWrite, pvSrc, PSPEMU_IOM_TRACE_F_WRITE, PSPEMU_IOM_TRACE_F_AFTER);
}
/**
* Reads from the given MMIO based region.
*
* @returns nothing.
* @param pThis The I/O manager instance data.
* @param pX86MapSlot The x86 mapping slot triggering the read.
* @param pRegion The region to read from.
* @param PhysX86Addr Absolute x86 physical address being read from.
* @param cbRead How much to read.
* @param pvDst Where to store the read data.
*/
static void pspEmuIomX86RegionRead(PPSPIOMINT pThis, PPSPIOMX86MAPCTRLSLOT pX86MapSlot,
PPSPIOMREGIONHANDLEINT pRegion, X86PADDR PhysX86Addr, size_t cbRead, void *pvDst)
{
PSPTRACEEVTORIGIN enmEvtOrigin = PSPTRACEEVTORIGIN_X86;
pspEmuIomX86TpCall(pThis, PhysX86Addr, pRegion, cbRead, pvDst, PSPEMU_IOM_TRACE_F_READ, PSPEMU_IOM_TRACE_F_BEFORE);
if (pRegion)
{
if (pRegion->enmType == PSPIOMREGIONTYPE_X86_MMIO)
{
enmEvtOrigin = PSPTRACEEVTORIGIN_X86_MMIO;
if (pRegion->u.X86.u.Mmio.pfnRead)
pRegion->u.X86.u.Mmio.pfnRead(PhysX86Addr - pRegion->u.X86.PhysX86AddrStart, cbRead, pvDst, pRegion->pvUser);
else
memset(pvDst, 0, cbRead);
}
else if (pRegion->enmType == PSPIOMREGIONTYPE_X86_MEM)
{
enmEvtOrigin = PSPTRACEEVTORIGIN_X86_MEM;
pspEmuIoMgrX86MemReadWorker(pThis, pRegion, PhysX86Addr - pRegion->u.X86.PhysX86AddrStart, pvDst, cbRead);
}
}
else if (pThis->pfnX86UnassignedRead)
pThis->pfnX86UnassignedRead(PhysX86Addr, cbRead, pvDst, pX86MapSlot->u32RegUnk2 == 6 ? true : false /*fMmio*/,
pX86MapSlot->u32RegUnk5, pThis->pvUserX86Unassigned);
else
memset(pvDst, 0, cbRead);
pspEmuIomTraceRegionRead(pThis, pRegion, enmEvtOrigin, PhysX86Addr, pvDst, cbRead);
pspEmuIomX86TpCall(pThis, PhysX86Addr, pRegion, cbRead, pvDst, PSPEMU_IOM_TRACE_F_READ, PSPEMU_IOM_TRACE_F_AFTER);
}
/**
* Writes to the given x86 based region.
*
* @returns nothing.
* @param pThis The I/O manager instance data.
* @param pX86MapSlot The x86 mapping slot triggering the write.
* @param pRegion The region to write to.
* @param PhysX86Addr Absolute x86 physical address being written to.
* @param cbWrite How much to write.
* @param pvSrc The data to write.
*/
static void pspEmuIomX86RegionWrite(PPSPIOMINT pThis, PPSPIOMX86MAPCTRLSLOT pX86MapSlot, PPSPIOMREGIONHANDLEINT pRegion,
X86PADDR PhysX86Addr, size_t cbWrite, const void *pvSrc)
{
PSPTRACEEVTORIGIN enmEvtOrigin = PSPTRACEEVTORIGIN_X86;
if (pRegion)
{
if (pRegion->enmType == PSPIOMREGIONTYPE_X86_MMIO)
enmEvtOrigin = PSPTRACEEVTORIGIN_X86_MMIO;
else if (pRegion->enmType == PSPIOMREGIONTYPE_X86_MEM)
enmEvtOrigin = PSPTRACEEVTORIGIN_X86_MEM;
}
pspEmuIomTraceRegionWrite(pThis, pRegion, enmEvtOrigin, PhysX86Addr, pvSrc, cbWrite);
pspEmuIomX86TpCall(pThis, PhysX86Addr, pRegion, cbWrite, pvSrc, PSPEMU_IOM_TRACE_F_WRITE, PSPEMU_IOM_TRACE_F_BEFORE);
if (pRegion)
{
if (pRegion->enmType == PSPIOMREGIONTYPE_X86_MMIO)
{
if (pRegion->u.X86.u.Mmio.pfnWrite)
pRegion->u.X86.u.Mmio.pfnWrite(PhysX86Addr - pRegion->u.X86.PhysX86AddrStart, cbWrite, pvSrc, pRegion->pvUser);
}
else if (pRegion->enmType == PSPIOMREGIONTYPE_X86_MEM)
pspEmuIoMgrX86MemWriteWorker(pThis, pRegion, PhysX86Addr - pRegion->u.X86.PhysX86AddrStart, pvSrc, cbWrite);
}
else if (pThis->pfnX86UnassignedWrite)
pThis->pfnX86UnassignedWrite(PhysX86Addr, cbWrite, pvSrc, pX86MapSlot->u32RegUnk2 == 6 ? true : false /*fMmio*/,
pX86MapSlot->u32RegUnk5, pThis->pvUserX86Unassigned);
pspEmuIomX86TpCall(pThis, PhysX86Addr, pRegion, cbWrite, pvSrc, PSPEMU_IOM_TRACE_F_WRITE, PSPEMU_IOM_TRACE_F_AFTER);
}
static void pspEmuIomSmnSlotsRead(PSPCORE hCore, PSPADDR uPspAddr, size_t cbRead, void *pvDst, void *pvUser)
{
PPSPIOMINT pThis = (PPSPIOMINT)pvUser;
SMNADDR SmnAddr = pspEmuIomGetSmnAddrFromSlotAndOffset(pThis, uPspAddr);
PPSPIOMREGIONHANDLEINT pRegion = pspEmuIomSmnFindRegion(pThis, SmnAddr);
pspEmuIomSmnRegionRead(pThis, pRegion, SmnAddr, cbRead, pvDst);
}
static void pspEmuIomSmnSlotsWrite(PSPCORE hCore, PSPADDR uPspAddr, size_t cbWrite, const void *pvSrc, void *pvUser)
{
PPSPIOMINT pThis = (PPSPIOMINT)pvUser;
SMNADDR SmnAddr = pspEmuIomGetSmnAddrFromSlotAndOffset(pThis, uPspAddr);
PPSPIOMREGIONHANDLEINT pRegion = pspEmuIomSmnFindRegion(pThis, SmnAddr);
pspEmuIomSmnRegionWrite(pThis, pRegion, SmnAddr, cbWrite, pvSrc);
}
static void pspEmuIomMmioRead(PSPCORE hCore, PSPADDR uPspAddr, size_t cbRead, void *pvDst, void *pvUser)
{
PPSPIOMINT pThis = (PPSPIOMINT)pvUser;
uPspAddr += 0x01000000 + 32 * _1M; /* The address contains the offset from the beginning of the registered range */
PPSPIOMREGIONHANDLEINT pRegion = pspEmuIomMmioFindRegion(pThis, uPspAddr);
pspEmuIomMmioRegionRead(pThis, pRegion, uPspAddr, cbRead, pvDst);