Zeyu Wang*, Xiaowu He*, Xiangwen Zhuge, Shen Xu, Fan Dang, Jingao Xu and Zheng Yang
"Enabling Network Diagnostics in Time-Sensitive Networking:Protocol, Algorithm, and Hardware", IEEE IWQoS, 2024.
- [PDF]
+ [PDF]
Xiangwen Zhuge, Xinjun Cai, Xiaowu He, Zeyu Wang, Fan Dang, Wang Xu and Zheng Yang
"InNetScheduler:In-network scheduling for time- and event-triggered critical traffic in TSN", IEEE INFOCOM, 2024.
- [PDF]
+ [PDF]
Zeyu Wang, Jingao Xu, Xu Wang, Xiangwen Zhuge, Xiaowu He, Zheng Yang
"Industrial Knee-jerk:In-Network Simultaneous Planning and Control on a TSN Switch", ACM MobiSys, 2023.
- [PDF]
+ [PDF]
Zheng Yang, Yi Zhao, Fan Dang, Xiaowu He, Jiahang Wu, Hao Cao, Zeyu Wang, Yunhao Liu
"CaaS:Enabling Control-as-a-Service for Time-Sensitive Networking", IEEE INFOCOM, 2023.
- [PDF]
+ [PDF]
Xiaowu He, Xiangwen Zhuge, Fan Dang, Wang Xu, Zheng Yang
"DeepScheduler:Enabling Flow-Aware Scheduling in Time-Sensitive Networking", IEEE INFOCOM, 2023.
- [PDF]
+ [PDF]
Yi Zhao, Zheng Yang, Xiaowu He, Jiahang Wu, Hao Cao, Liang Dong, Fan Dang, Yunhao Liu
"E-TSN:Enabling Event-triggered Critical Traffic in Time-Sensitive Networking for Industrial Applications", IEEE ICDCS, 2022.
- [PDF]
+ [PDF]
diff --git a/content/switch/system_design/index.md b/content/switch/system_design/index.md
index 2b40b67..be9c738 100644
--- a/content/switch/system_design/index.md
+++ b/content/switch/system_design/index.md
@@ -39,7 +39,7 @@ The overall design of the time synchronization module is shown in the diagram be
After the data frame enters the PL from the input port of the switch, the timestamp cache module will record and cache the timestamp when the data frame enters the hardware. The switch's exchange module will determine whether the data frame is related to time synchronization. Time synchronization data frames will be forwarded from the PL to the PS for processing through the Direct Memory Access (DMA) channel. In the PS, the time synchronization state machine module needs to obtain the real-time clock information of the underlying PL and the hardware timestamps corresponding to different data frames through the AXI4-Lite interface. When the switch needs to send time synchronization-related data frames, the PS is responsible for encapsulating the sent data frames and then forwarding them to the PL for processing through the DMA channel. Since time synchronization also needs to record the sending time of messages such as Sync and Pdelay_Req, the timestamp cache module will still cache the sending timestamp before the data frame is sent from the output port, so that the PS can use it later.
-### Switch Fabric & Gate Control
+## Switch Fabric & Gate Control
The overall design of the switch fabric and gate control module is shown in the diagram below. The PS part mainly includes a configuration module, which is used for software-level configuration of the switch's Gate Control List (GCL) and MAC forwarding table; the PL part mainly consists of the switch fabric and the gate control module, which are responsible for port forwarding and real-time control of traffic.
diff --git a/hugo_stats.json b/hugo_stats.json
index 15d6b37..5f373eb 100644
--- a/hugo_stats.json
+++ b/hugo_stats.json
@@ -8,7 +8,6 @@
"b",
"blockquote",
"body",
- "br",
"button",
"circle",
"code",
@@ -17,12 +16,10 @@
"figcaption",
"figure",
"footer",
- "g",
"h1",
"h2",
"h3",
"h4",
- "h6",
"head",
"header",
"hr",
@@ -83,7 +80,6 @@
"blox-features",
"blox-hero",
"blox-markdown",
- "blox-stats",
"border",
"border-black",
"border-current",
@@ -166,8 +162,6 @@
"gap-x-1.5",
"gap-x-6",
"gap-y-2",
- "grid",
- "grid-cols-3",
"group",
"group-hover:-translate-x-[2px]",
"group-hover:decoration-primary-500",
@@ -223,14 +217,11 @@
"leading-tight",
"lg:flex",
"lg:grid-cols-3",
- "lg:group-hover:opacity-100",
- "lg:group-hover:visible",
"lg:h-12",
"lg:h-6",
"lg:h-[calc(100vh-var(--navbar-height))]",
"lg:hidden",
"lg:inline-block",
- "lg:max-w-screen-xl",
"lg:mb-16",
"lg:ml-0",
"lg:order-1",
@@ -240,12 +231,9 @@
"lg:px-6",
"lg:px-8",
"lg:py-2",
- "lg:py-20",
"lg:py-56",
"lg:space-x-2",
- "lg:text-5xl",
"lg:text-6xl",
- "lg:text-base",
"lg:w-12",
"lg:w-6",
"lg:w-auto",
@@ -269,19 +257,16 @@
"mb-5",
"mb-6",
"mb-8",
- "md:border-r",
"md:flex",
"md:flex-row",
"md:flex-shrink-0",
"md:gap-12",
"md:grid",
"md:grid-cols-2",
- "md:max-w-full",
"md:ml-4",
"md:mt-0",
"md:order-2",
"md:px-12",
- "md:px-24",
"md:space-y-0",
"md:text-lg",
"md:w-48",
@@ -311,10 +296,6 @@
"my-10",
"my-2",
"my-5",
- "nav-dropdown",
- "nav-dropdown-item",
- "nav-dropdown-link",
- "nav-dropdown-list",
"nav-item",
"nav-link",
"navbar",
@@ -373,7 +354,6 @@
"py-0.5",
"py-1",
"py-1.5",
- "py-16",
"py-2",
"py-2.5",
"py-32",
@@ -387,7 +367,6 @@
"rounded-md",
"rounded-sm",
"rounded-xl",
- "row-gap-8",
"rtl:-ml-4",
"rtl:-rotate-180",
"rtl:hidden",
@@ -402,7 +381,6 @@
"sidebar-active-item",
"sm:flex",
"sm:justify-center",
- "sm:max-w-xl",
"sm:mb-8",
"sm:py-16",
"sm:py-48",
@@ -421,7 +399,6 @@
"text-dark",
"text-gray-500",
"text-gray-600",
- "text-gray-800",
"text-gray-900",
"text-lg",
"text-md",
@@ -443,7 +420,6 @@
"top-16",
"tracking-tight",
"tracking-wide",
- "tracking-widest",
"transition",
"transition-transform",
"uppercase",
@@ -457,7 +433,6 @@
"xl:block",
"xl:gap-16",
"xl:space-x-8",
- "xl:text-6xl",
"z-30"
],
"ids": [
@@ -535,7 +510,6 @@
"search",
"search_toggle",
"section-hero",
- "section-stats",
"share-link-email",
"share-link-facebook",
"share-link-linkedin",
diff --git a/layouts/dfdffff/index.html b/layouts/dfdffff/index.html
new file mode 100644
index 0000000..fbee122
--- /dev/null
+++ b/layouts/dfdffff/index.html
@@ -0,0 +1,11 @@
+
+
+
+
+ Welcome to My Site
+
+
+
Hello, Welcome to My Custom Page!
+
This is a custom HTML page for my Hugo site.
+
+
\ No newline at end of file
diff --git a/public/404.html b/public/404.html
index 5a9df25..3e5685c 100644
--- a/public/404.html
+++ b/public/404.html
@@ -3926,22 +3926,10 @@
Home
-
-
-
-
-
-
-
-
+
+ >> ZIGGO Test Report for A Brand Switch (in Chinese)
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
PUBLICATIONS
+
+
+
+
+
+
Zeyu Wang*, Xiaowu He*, Xiangwen Zhuge, Shen Xu, Fan Dang, Jingao Xu and Zheng Yang
+ "Enabling Network Diagnostics in Time-Sensitive Networking: Protocol, Algorithm, and Hardware", IEEE IWQoS, 2024.
+ [PDF]
+
+
Xiangwen Zhuge, Xinjun Cai, Xiaowu He, Zeyu Wang, Fan Dang, Wang Xu and Zheng Yang
+ "InNetScheduler: In-network scheduling for time- and event-triggered critical traffic in TSN", IEEE INFOCOM, 2024.
+ [PDF]
+
+
Zeyu Wang, Jingao Xu, Xu Wang, Xiangwen Zhuge, Xiaowu He, Zheng Yang
+ "Industrial Knee-jerk: In-Network Simultaneous Planning and Control on a TSN Switch", ACM MobiSys, 2023.
+ [PDF]
+
+
Zheng Yang, Yi Zhao, Fan Dang, Xiaowu He, Jiahang Wu, Hao Cao, Zeyu Wang, Yunhao Liu
+ "CaaS: Enabling Control-as-a-Service for Time-Sensitive Networking", IEEE INFOCOM, 2023.
+ [PDF]
+
+
Xiaowu He, Xiangwen Zhuge, Fan Dang, Wang Xu, Zheng Yang
+ "DeepScheduler: Enabling Flow-Aware Scheduling in Time-Sensitive Networking", IEEE INFOCOM, 2023.
+ [PDF]
+
+
Yi Zhao, Zheng Yang, Xiaowu He, Jiahang Wu, Hao Cao, Liang Dong, Fan Dang, Yunhao Liu
+ "E-TSN: Enabling Event-triggered Critical Traffic in Time-Sensitive Networking for Industrial Applications", IEEE ICDCS, 2022.
+ [PDF]
+
+ CSI file name is in this form: id-a-b-c-d-rx.dat, where 'id' represents user's id,
+ 'a' represents room id, 'b' represents position id, 'c' represents orientation id, 'd' represents instance id,
+ 'rx' range between 'r1' and 'r6', corresponding to 6 receivers. CSI data can be loaded by
+ CSITool.
+
+
+ DFS file name is in this form: id-a-b-c-d.mat, where 'id' represents user's id,
+ 'a' represents room id, 'b' represents position id, 'c' represents orientation id, 'd' represents instance id.
+ The data structure of each file is 6*121*T, where
+ '6' represent the 6 receivers,
+ '121' represents the 121 frequency bins ranging between [-60, 60] Hz.
+ 'T' represents the consecutive sampling timestamps.
+
+
+ BVP file name is in this form: id-a-b-c-d.mat, where 'id' represents user's id,
+ 'a' represents room id, 'b' represents position id, 'c' represents orientation id, 'd' represents instance id.
+ The data structure of each file is 20*20*T, where
+ the first '20' represent the velocity alongside the x direction,
+ the second '20' represent the velocity alongside the y direction.
+ 'T' represents the consecutive sampling timestamps.
+
ZIGGO presents a hardware-software co-designed TSN device
- Dedicated support channel
+ Critical traffic replay and record with high-precision
- 3,000+ users on Discord
+ Gigabit bandwidth support
- Share your site and get feedback
+ IEEE 802.1AS and Qcc support
@@ -4961,7 +4882,7 @@
Zeyu Wang*, Xiaowu He*, Xiangwen Zhuge, Shen Xu, Fan Dang, Jingao Xu and Zheng Yang "Enabling Network Diagnostics in Time-Sensitive Networking:Protocol, Algorithm, and Hardware", IEEE IWQoS, 2024. [PDF]
Xiangwen Zhuge, Xinjun Cai, Xiaowu He, Zeyu Wang, Fan Dang, Wang Xu and Zheng Yang "InNetScheduler:In-network scheduling for time- and event-triggered critical traffic in TSN", IEEE INFOCOM, 2024. [PDF]
Zeyu Wang, Jingao Xu, Xu Wang, Xiangwen Zhuge, Xiaowu He, Zheng Yang "Industrial Knee-jerk:In-Network Simultaneous Planning and Control on a TSN Switch", ACM MobiSys, 2023. [PDF]
Zheng Yang, Yi Zhao, Fan Dang, Xiaowu He, Jiahang Wu, Hao Cao, Zeyu Wang, Yunhao Liu "CaaS:Enabling Control-as-a-Service for Time-Sensitive Networking", IEEE INFOCOM, 2023. [PDF]
Xiaowu He, Xiangwen Zhuge, Fan Dang, Wang Xu, Zheng Yang "DeepScheduler:Enabling Flow-Aware Scheduling in Time-Sensitive Networking", IEEE INFOCOM, 2023. [PDF]
Yi Zhao, Zheng Yang, Xiaowu He, Jiahang Wu, Hao Cao, Liang Dong, Fan Dang, Yunhao Liu "E-TSN:Enabling Event-triggered Critical Traffic in Time-Sensitive Networking for Industrial Applications", IEEE ICDCS, 2022. [PDF]
+
Zeyu Wang*, Xiaowu He*, Xiangwen Zhuge, Shen Xu, Fan Dang, Jingao Xu and Zheng Yang "Enabling Network Diagnostics in Time-Sensitive Networking:Protocol, Algorithm, and Hardware", IEEE IWQoS, 2024. [PDF]
Xiangwen Zhuge, Xinjun Cai, Xiaowu He, Zeyu Wang, Fan Dang, Wang Xu and Zheng Yang "InNetScheduler:In-network scheduling for time- and event-triggered critical traffic in TSN", IEEE INFOCOM, 2024. [PDF]
Zeyu Wang, Jingao Xu, Xu Wang, Xiangwen Zhuge, Xiaowu He, Zheng Yang "Industrial Knee-jerk:In-Network Simultaneous Planning and Control on a TSN Switch", ACM MobiSys, 2023. [PDF]
Zheng Yang, Yi Zhao, Fan Dang, Xiaowu He, Jiahang Wu, Hao Cao, Zeyu Wang, Yunhao Liu "CaaS:Enabling Control-as-a-Service for Time-Sensitive Networking", IEEE INFOCOM, 2023. [PDF]
Xiaowu He, Xiangwen Zhuge, Fan Dang, Wang Xu, Zheng Yang "DeepScheduler:Enabling Flow-Aware Scheduling in Time-Sensitive Networking", IEEE INFOCOM, 2023. [PDF]
Yi Zhao, Zheng Yang, Xiaowu He, Jiahang Wu, Hao Cao, Liang Dong, Fan Dang, Yunhao Liu "E-TSN:Enabling Event-triggered Critical Traffic in Time-Sensitive Networking for Industrial Applications", IEEE ICDCS, 2022. [PDF]
diff --git a/public/index.xml b/public/index.xml
index 2119b88..3185862 100644
--- a/public/index.xml
+++ b/public/index.xml
@@ -2165,7 +2165,7 @@ Device1每次发送1个1500B的数据包,每个Switch都预留了1个时隙,
</div></figure>
</p>
<p>After the data frame enters the PL from the input port of the switch, the timestamp cache module will record and cache the timestamp when the data frame enters the hardware. The switch’s exchange module will determine whether the data frame is related to time synchronization. Time synchronization data frames will be forwarded from the PL to the PS for processing through the Direct Memory Access (DMA) channel. In the PS, the time synchronization state machine module needs to obtain the real-time clock information of the underlying PL and the hardware timestamps corresponding to different data frames through the AXI4-Lite interface. When the switch needs to send time synchronization-related data frames, the PS is responsible for encapsulating the sent data frames and then forwarding them to the PL for processing through the DMA channel. Since time synchronization also needs to record the sending time of messages such as Sync and Pdelay_Req, the timestamp cache module will still cache the sending timestamp before the data frame is sent from the output port, so that the PS can use it later.</p>
-<h3 id="switch-fabric--gate-control">Switch Fabric & Gate Control</h3>
+<h2 id="switch-fabric--gate-control">Switch Fabric & Gate Control</h2>
<p>The overall design of the switch fabric and gate control module is shown in the diagram below. The PS part mainly includes a configuration module, which is used for software-level configuration of the switch’s Gate Control List (GCL) and MAC forwarding table; the PL part mainly consists of the switch fabric and the gate control module, which are responsible for port forwarding and real-time control of traffic.</p>
<p>
diff --git a/public/media/bg-triangles-backup.svg b/public/media/bg-triangles-backup.svg
new file mode 100644
index 0000000..3d303d5
--- /dev/null
+++ b/public/media/bg-triangles-backup.svg
@@ -0,0 +1,136 @@
+
+
\ No newline at end of file
diff --git a/public/media/bg-triangles-bg.svg b/public/media/bg-triangles-bg.svg
new file mode 100644
index 0000000..c2d584a
--- /dev/null
+++ b/public/media/bg-triangles-bg.svg
@@ -0,0 +1 @@
+
diff --git a/public/privacy/index.html b/public/privacy/index.html
index 06e6f5a..acf97bb 100644
--- a/public/privacy/index.html
+++ b/public/privacy/index.html
@@ -3934,22 +3934,10 @@
Home
-
-
-
-
-
-
-
-
After the data frame enters the PL from the input port of the switch, the timestamp cache module will record and cache the timestamp when the data frame enters the hardware. The switch’s exchange module will determine whether the data frame is related to time synchronization. Time synchronization data frames will be forwarded from the PL to the PS for processing through the Direct Memory Access (DMA) channel. In the PS, the time synchronization state machine module needs to obtain the real-time clock information of the underlying PL and the hardware timestamps corresponding to different data frames through the AXI4-Lite interface. When the switch needs to send time synchronization-related data frames, the PS is responsible for encapsulating the sent data frames and then forwarding them to the PL for processing through the DMA channel. Since time synchronization also needs to record the sending time of messages such as Sync and Pdelay_Req, the timestamp cache module will still cache the sending timestamp before the data frame is sent from the output port, so that the PS can use it later.
-
Switch Fabric & Gate Control
+
Switch Fabric & Gate Control
The overall design of the switch fabric and gate control module is shown in the diagram below. The PS part mainly includes a configuration module, which is used for software-level configuration of the switch’s Gate Control List (GCL) and MAC forwarding table; the PL part mainly consists of the switch fabric and the gate control module, which are responsible for port forwarding and real-time control of traffic.