I don't understand something about the notes of InstanceSymbol::resolvePortConnections #374
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MikePopoloski
luckyhorse1
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the notes of InstanceSymbol::resolvePortConnections // interface I #(parameter int i) (); endinterface
// module M(I iface, input logic [iface.i - 1 : 0] foo);
// localparam int j = $bits(foo);
// endmodule
//
// In order to resolve connections for an instance of M, we elaborate its body,
// which then requires evaluating $bits(foo) which then depends on the connection
// provided to `iface`.
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Answered by
MikePopoloski
Dec 26, 2020
Replies: 2 comments 2 replies
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Non-ansi interface ports are allowed in SystemVerilog. I haven't added support for them yet but I will at some point. |
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I'm not sure what to tell you; the function is in fact reentrant when making port connections. The full test example that shows this is:
Setting a break point in resolvePortConnections will show you the call stack where this occurs. |
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luckyhorse1
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I'm not sure what to tell you; the function is in fact reentrant when making port connections. The full test example that shows this is:
Setting a break point in resolvePortConnections will show you the call stack where this occurs.