From 4cf954760143e0932818947af7313ae5e1a7705e Mon Sep 17 00:00:00 2001 From: Aakash Date: Wed, 11 Sep 2024 16:39:49 +0530 Subject: [PATCH] Move MTVEC_BASE_ADDR_MASK out of the ifdefs This makes the preprocessor macro available in all processor configurations. Prevents compile error Jira-Id: ESWBM_RV32-380 --- miv_rv32_hal/miv_rv32_hal.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/miv_rv32_hal/miv_rv32_hal.h b/miv_rv32_hal/miv_rv32_hal.h index 6307159..24328e0 100644 --- a/miv_rv32_hal/miv_rv32_hal.h +++ b/miv_rv32_hal/miv_rv32_hal.h @@ -333,14 +333,14 @@ NOTE: All these macros must not be defined if you are using a MIV_RV32 core. */ #define MIMPID read_csr(mimpid) -/*Used as a mask to read and write to mte mtvec.BASE address*/ -#define MTVEC_BASE_ADDR_MASK 0xFFFFFFFC - #else #define MTIME (0u) #define MTIMEH (0u) #endif /*MIV_RV32_EXT_TIMER*/ +/* Used as a mask to read and write to mtvec.BASE address */ +#define MTVEC_BASE_ADDR_MASK 0xFFFFFFFC + /*-------------------------------------------------------------------------*//** RISC-V Specification Interrupts =======================================