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design_1.hwh
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design_1.hwh
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Mon Jan 24 17:47:53 2022" VIVADOVERSION="2020.1">
<SYSTEMINFO ARCH="zynq" BOARD="tul.com.tw:pynq-z2:part0:1.0" DEVICE="7z020" NAME="design_1" PACKAGE="clg400" SPEEDGRADE="-1"/>
<EXTERNALPORTS>
<PORT DIR="O" NAME="RESET_DEBUG" POLARITY="ACTIVE_HIGH" SIGIS="undef" SIGNAME="CustomIOP_rst_ps7_0_100M_mb_reset">
<CONNECTIONS>
<CONNECTION INSTANCE="CustomIOP_rst_ps7_0_100M" PORT="mb_reset"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="0" NAME="LED" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_gpio_io_o">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_gpio_0" PORT="gpio_io_o"/>
</CONNECTIONS>
</PORT>
<PORT DIR="IO" LEFT="53" NAME="FIXED_IO_mio" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_MIO">
<CONNECTIONS>
<CONNECTION INSTANCE="processing_system7_0" PORT="MIO"/>
</CONNECTIONS>
</PORT>
<PORT DIR="IO" NAME="FIXED_IO_ddr_vrn" SIGIS="undef" SIGNAME="processing_system7_0_DDR_VRN">
<CONNECTIONS>
<CONNECTION INSTANCE="processing_system7_0" PORT="DDR_VRN"/>
</CONNECTIONS>
</PORT>
<PORT DIR="IO" NAME="FIXED_IO_ddr_vrp" SIGIS="undef" SIGNAME="processing_system7_0_DDR_VRP">
<CONNECTIONS>
<CONNECTION INSTANCE="processing_system7_0" PORT="DDR_VRP"/>
</CONNECTIONS>
</PORT>
<PORT DIR="IO" NAME="FIXED_IO_ps_srstb" SIGIS="undef" SIGNAME="processing_system7_0_PS_SRSTB">
<CONNECTIONS>
<CONNECTION INSTANCE="processing_system7_0" PORT="PS_SRSTB"/>
</CONNECTIONS>
</PORT>
<PORT DIR="IO" NAME="FIXED_IO_ps_clk" SIGIS="undef" SIGNAME="processing_system7_0_PS_CLK">
<CONNECTIONS>
<CONNECTION INSTANCE="processing_system7_0" PORT="PS_CLK"/>
</CONNECTIONS>
</PORT>
<PORT DIR="IO" NAME="FIXED_IO_ps_porb" SIGIS="undef" SIGNAME="processing_system7_0_PS_PORB">
<CONNECTIONS>
<CONNECTION INSTANCE="processing_system7_0" PORT="PS_PORB"/>
</CONNECTIONS>
</PORT>
<PORT DIR="IO" NAME="DDR_cas_n" SIGIS="undef" SIGNAME="processing_system7_0_DDR_CAS_n">
<CONNECTIONS>
<CONNECTION INSTANCE="processing_system7_0" PORT="DDR_CAS_n"/>
</CONNECTIONS>
</PORT>
<PORT DIR="IO" NAME="DDR_cke" SIGIS="undef" SIGNAME="processing_system7_0_DDR_CKE">
<CONNECTIONS>
<CONNECTION INSTANCE="processing_system7_0" PORT="DDR_CKE"/>
</CONNECTIONS>
</PORT>
<PORT CLKFREQUENCY="100000000" DIR="IO" NAME="DDR_ck_n" SIGIS="clk" SIGNAME="processing_system7_0_DDR_Clk_n">
<CONNECTIONS>
<CONNECTION INSTANCE="processing_system7_0" PORT="DDR_Clk_n"/>
</CONNECTIONS>
</PORT>
<PORT CLKFREQUENCY="100000000" DIR="IO" NAME="DDR_ck_p" SIGIS="clk" SIGNAME="processing_system7_0_DDR_Clk">
<CONNECTIONS>
<CONNECTION INSTANCE="processing_system7_0" PORT="DDR_Clk"/>
</CONNECTIONS>
</PORT>
<PORT DIR="IO" NAME="DDR_cs_n" SIGIS="undef" SIGNAME="processing_system7_0_DDR_CS_n">
<CONNECTIONS>
<CONNECTION INSTANCE="processing_system7_0" PORT="DDR_CS_n"/>
</CONNECTIONS>
</PORT>
<PORT DIR="IO" NAME="DDR_reset_n" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="processing_system7_0_DDR_DRSTB">
<CONNECTIONS>
<CONNECTION INSTANCE="processing_system7_0" PORT="DDR_DRSTB"/>
</CONNECTIONS>
</PORT>
<PORT DIR="IO" NAME="DDR_odt" SIGIS="undef" SIGNAME="processing_system7_0_DDR_ODT">
<CONNECTIONS>
<CONNECTION INSTANCE="processing_system7_0" PORT="DDR_ODT"/>
</CONNECTIONS>
</PORT>
<PORT DIR="IO" NAME="DDR_ras_n" SIGIS="undef" SIGNAME="processing_system7_0_DDR_RAS_n">
<CONNECTIONS>
<CONNECTION INSTANCE="processing_system7_0" PORT="DDR_RAS_n"/>
</CONNECTIONS>
</PORT>
<PORT DIR="IO" NAME="DDR_we_n" SIGIS="undef" SIGNAME="processing_system7_0_DDR_WEB">
<CONNECTIONS>
<CONNECTION INSTANCE="processing_system7_0" PORT="DDR_WEB"/>
</CONNECTIONS>
</PORT>
<PORT DIR="IO" LEFT="2" NAME="DDR_ba" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_DDR_BankAddr">
<CONNECTIONS>
<CONNECTION INSTANCE="processing_system7_0" PORT="DDR_BankAddr"/>
</CONNECTIONS>
</PORT>
<PORT DIR="IO" LEFT="14" NAME="DDR_addr" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_DDR_Addr">
<CONNECTIONS>
<CONNECTION INSTANCE="processing_system7_0" PORT="DDR_Addr"/>
</CONNECTIONS>
</PORT>
<PORT DIR="IO" LEFT="3" NAME="DDR_dm" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_DDR_DM">
<CONNECTIONS>
<CONNECTION INSTANCE="processing_system7_0" PORT="DDR_DM"/>
</CONNECTIONS>
</PORT>
<PORT DIR="IO" LEFT="31" NAME="DDR_dq" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_DDR_DQ">
<CONNECTIONS>
<CONNECTION INSTANCE="processing_system7_0" PORT="DDR_DQ"/>
</CONNECTIONS>
</PORT>
<PORT DIR="IO" LEFT="3" NAME="DDR_dqs_n" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_DDR_DQS_n">
<CONNECTIONS>
<CONNECTION INSTANCE="processing_system7_0" PORT="DDR_DQS_n"/>
</CONNECTIONS>
</PORT>
<PORT DIR="IO" LEFT="3" NAME="DDR_dqs_p" RIGHT="0" SIGIS="undef" SIGNAME="processing_system7_0_DDR_DQS">
<CONNECTIONS>
<CONNECTION INSTANCE="processing_system7_0" PORT="DDR_DQS"/>
</CONNECTIONS>
</PORT>
</EXTERNALPORTS>
<EXTERNALINTERFACES>
<BUSINTERFACE BUSNAME="processing_system7_0_DDR" DATAWIDTH="8" NAME="DDR" TYPE="INITIATOR">
<PARAMETER NAME="CAN_DEBUG" VALUE="false"/>
<PARAMETER NAME="TIMEPERIOD_PS" VALUE="1250"/>
<PARAMETER NAME="MEMORY_TYPE" VALUE="COMPONENTS"/>
<PARAMETER NAME="MEMORY_PART"/>
<PARAMETER NAME="DATA_WIDTH" VALUE="8"/>
<PARAMETER NAME="CS_ENABLED" VALUE="true"/>
<PARAMETER NAME="DATA_MASK_ENABLED" VALUE="true"/>
<PARAMETER NAME="SLOT" VALUE="Single"/>
<PARAMETER NAME="CUSTOM_PARTS"/>
<PARAMETER NAME="MEM_ADDR_MAP" VALUE="ROW_COLUMN_BANK"/>
<PARAMETER NAME="BURST_LENGTH" VALUE="8"/>
<PARAMETER NAME="AXI_ARBITRATION_SCHEME" VALUE="TDM"/>
<PARAMETER NAME="CAS_LATENCY" VALUE="11"/>
<PARAMETER NAME="CAS_WRITE_LATENCY" VALUE="11"/>
<PORTMAPS>
<PORTMAP LOGICAL="CAS_N" PHYSICAL="DDR_cas_n"/>
<PORTMAP LOGICAL="CKE" PHYSICAL="DDR_cke"/>
<PORTMAP LOGICAL="CK_N" PHYSICAL="DDR_ck_n"/>
<PORTMAP LOGICAL="CK_P" PHYSICAL="DDR_ck_p"/>
<PORTMAP LOGICAL="CS_N" PHYSICAL="DDR_cs_n"/>
<PORTMAP LOGICAL="RESET_N" PHYSICAL="DDR_reset_n"/>
<PORTMAP LOGICAL="ODT" PHYSICAL="DDR_odt"/>
<PORTMAP LOGICAL="RAS_N" PHYSICAL="DDR_ras_n"/>
<PORTMAP LOGICAL="WE_N" PHYSICAL="DDR_we_n"/>
<PORTMAP LOGICAL="BA" PHYSICAL="DDR_ba"/>
<PORTMAP LOGICAL="ADDR" PHYSICAL="DDR_addr"/>
<PORTMAP LOGICAL="DM" PHYSICAL="DDR_dm"/>
<PORTMAP LOGICAL="DQ" PHYSICAL="DDR_dq"/>
<PORTMAP LOGICAL="DQS_N" PHYSICAL="DDR_dqs_n"/>
<PORTMAP LOGICAL="DQS_P" PHYSICAL="DDR_dqs_p"/>
</PORTMAPS>
</BUSINTERFACE>
<BUSINTERFACE BUSNAME="processing_system7_0_FIXED_IO" NAME="FIXED_IO" TYPE="INITIATOR">
<PARAMETER NAME="CAN_DEBUG" VALUE="false"/>
<PORTMAPS>
<PORTMAP LOGICAL="MIO" PHYSICAL="FIXED_IO_mio"/>
<PORTMAP LOGICAL="DDR_VRN" PHYSICAL="FIXED_IO_ddr_vrn"/>
<PORTMAP LOGICAL="DDR_VRP" PHYSICAL="FIXED_IO_ddr_vrp"/>
<PORTMAP LOGICAL="PS_SRSTB" PHYSICAL="FIXED_IO_ps_srstb"/>
<PORTMAP LOGICAL="PS_CLK" PHYSICAL="FIXED_IO_ps_clk"/>
<PORTMAP LOGICAL="PS_PORB" PHYSICAL="FIXED_IO_ps_porb"/>
</PORTMAPS>
</BUSINTERFACE>
</EXTERNALINTERFACES>
<MODULES>
<MODULE COREREVISION="3" FULLNAME="/CustomIOP/axi_bram_ctrl_0" HWVERSION="4.1" INSTANCE="CustomIOP_axi_bram_ctrl_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="MEMORY_CNTLR" MODTYPE="axi_bram_ctrl" VLNV="xilinx.com:ip:axi_bram_ctrl:4.1">
<DOCUMENTS>
<DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_bram_ctrl;v=v4_1;d=pg078-axi-bram-ctrl.pdf"/>
</DOCUMENTS>
<ADDRESSBLOCKS>
<ADDRESSBLOCK ACCESS="read-write" INTERFACE="S_AXI" NAME="Mem0" RANGE="4096" USAGE="memory">
<REGISTERS>
<REGISTER NAME="ECC_STATUS">
<PROPERTY NAME="DESCRIPTION" VALUE="ECC Status Register"/>
<PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x000"/>
<PROPERTY NAME="SIZE" VALUE="1"/>
<PROPERTY NAME="ACCESS" VALUE="read-write"/>
<PROPERTY NAME="IS_ENABLED" VALUE="false"/>
<PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
<FIELDS>
<FIELD NAME="UE_STATUS">
<PROPERTY NAME="DESCRIPTION" VALUE="If 1 an uncorrectable error has occurred. Cleared when 1 is written to this bit position
"/>
<PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
<PROPERTY NAME="ACCESS" VALUE="read-write"/>
<PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToClear"/>
<PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
<PROPERTY NAME="READ_ACTION" VALUE=""/>
<PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
<PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
</FIELD>
<FIELD NAME="CE_STATUS">
<PROPERTY NAME="DESCRIPTION" VALUE="If 1 a correctable error has occurred. Cleared when 1 is written to this bit position
"/>
<PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
<PROPERTY NAME="ACCESS" VALUE="read-write"/>
<PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToClear"/>
<PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
<PROPERTY NAME="READ_ACTION" VALUE=""/>
<PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
<PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
</FIELD>
</FIELDS>
</REGISTER>
<REGISTER NAME="ECC_EN_IRQ">
<PROPERTY NAME="DESCRIPTION" VALUE="ECC Enable Interrupt Register"/>
<PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x004"/>
<PROPERTY NAME="SIZE" VALUE="1"/>
<PROPERTY NAME="ACCESS" VALUE="read-write"/>
<PROPERTY NAME="IS_ENABLED" VALUE="false"/>
<PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
<FIELDS>
<FIELD NAME="UE_EN_IRQ">
<PROPERTY NAME="DESCRIPTION" VALUE="1 - The value of the UE_STATUS bit of the ECC Status Register is propagated to the Interrupt signal.
0 - The value of the UE_STATUS bit of the ECC Status Register is not propagated to the Interrupt signal.
"/>
<PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
<PROPERTY NAME="ACCESS" VALUE="read-write"/>
<PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
<PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
<PROPERTY NAME="READ_ACTION" VALUE=""/>
<PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
<PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
</FIELD>
<FIELD NAME="CE_EN_IRQ">
<PROPERTY NAME="DESCRIPTION" VALUE="1 - The value of the CE_STATUS bit of the ECC Status Register is propagated to the Interrupt signal.
0 - The value of the CE_STATUS bit of the ECC Status Register is not propagated to the Interrupt signal.
"/>
<PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
<PROPERTY NAME="ACCESS" VALUE="read-write"/>
<PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
<PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
<PROPERTY NAME="READ_ACTION" VALUE=""/>
<PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
<PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
</FIELD>
</FIELDS>
</REGISTER>
<REGISTER NAME="ECC_ON_OFF">
<PROPERTY NAME="DESCRIPTION" VALUE="ECC On/Off Register"/>
<PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x008"/>
<PROPERTY NAME="SIZE" VALUE="1"/>
<PROPERTY NAME="ACCESS" VALUE="read-write"/>
<PROPERTY NAME="IS_ENABLED" VALUE="false"/>
<PROPERTY NAME="RESET_VALUE" VALUE="0"/>
<FIELDS>
<FIELD NAME="ECC_ON_OFF">
<PROPERTY NAME="DESCRIPTION" VALUE="0 - ECC checking is disabled on read operations. (ECC generation is enabled on write operations when C_ECC = 1).
1 - ECC checking is enabled on read operations. All correctable and uncorrectable error conditions are captured and status updated.
"/>
<PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
<PROPERTY NAME="ACCESS" VALUE="read-write"/>
<PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
<PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
<PROPERTY NAME="READ_ACTION" VALUE=""/>
<PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
<PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
</FIELD>
</FIELDS>
</REGISTER>
<REGISTER NAME="CE_CNT">
<PROPERTY NAME="DESCRIPTION" VALUE="Correctable Error Counter Register"/>
<PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x00C"/>
<PROPERTY NAME="SIZE" VALUE="1"/>
<PROPERTY NAME="ACCESS" VALUE="read-write"/>
<PROPERTY NAME="IS_ENABLED" VALUE="false"/>
<PROPERTY NAME="RESET_VALUE" VALUE="0"/>
<FIELDS>
<FIELD NAME="CE_CNT">
<PROPERTY NAME="DESCRIPTION" VALUE="Registers holds number of correctable errors encountered
"/>
<PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
<PROPERTY NAME="ACCESS" VALUE="read-write"/>
<PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
<PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
<PROPERTY NAME="READ_ACTION" VALUE=""/>
<PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
<PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
</FIELD>
</FIELDS>
</REGISTER>
<REGISTER NAME="CE_FFA0">
<PROPERTY NAME="DESCRIPTION" VALUE="Correctable Error First Failing Address Register, bits [31:0]"/>
<PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x1C0"/>
<PROPERTY NAME="SIZE" VALUE="1"/>
<PROPERTY NAME="ACCESS" VALUE="read-only"/>
<PROPERTY NAME="IS_ENABLED" VALUE="false"/>
<PROPERTY NAME="RESET_VALUE" VALUE="0"/>
<FIELDS>
<FIELD NAME="CE_FFA0">
<PROPERTY NAME="DESCRIPTION" VALUE="Address (bits [31:0]) of the first occurrence of a correctable error
"/>
<PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
<PROPERTY NAME="ACCESS" VALUE="read-only"/>
<PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
<PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
<PROPERTY NAME="READ_ACTION" VALUE=""/>
<PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
<PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
</FIELD>
</FIELDS>
</REGISTER>
<REGISTER NAME="CE_FFA1">
<PROPERTY NAME="DESCRIPTION" VALUE="Correctable Error First Failing Address Register, bits [63:32]"/>
<PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x1C4"/>
<PROPERTY NAME="SIZE" VALUE="1"/>
<PROPERTY NAME="ACCESS" VALUE="read-only"/>
<PROPERTY NAME="IS_ENABLED" VALUE="false"/>
<PROPERTY NAME="RESET_VALUE" VALUE="0"/>
<FIELDS>
<FIELD NAME="CE_FFA1">
<PROPERTY NAME="DESCRIPTION" VALUE="Address (bits [63:32]) of the first occurrence of a correctable error
"/>
<PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
<PROPERTY NAME="ACCESS" VALUE="read-only"/>
<PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
<PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
<PROPERTY NAME="READ_ACTION" VALUE=""/>
<PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
<PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
</FIELD>
</FIELDS>
</REGISTER>
<REGISTER NAME="UE_FFD1">
<PROPERTY NAME="DESCRIPTION" VALUE="Uncorrectable Error First Failing Data Register , bits [63:32]"/>
<PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x204"/>
<PROPERTY NAME="SIZE" VALUE="1"/>
<PROPERTY NAME="ACCESS" VALUE="read-only"/>
<PROPERTY NAME="IS_ENABLED" VALUE="false"/>
<PROPERTY NAME="RESET_VALUE" VALUE="0"/>
<FIELDS>
<FIELD NAME="UE_FFD">
<PROPERTY NAME="DESCRIPTION" VALUE="Data (bits [63:32) of the first occurrence of an uncorrectable error
"/>
<PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
<PROPERTY NAME="ACCESS" VALUE="read-only"/>
<PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
<PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
<PROPERTY NAME="READ_ACTION" VALUE=""/>
<PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
<PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
</FIELD>
</FIELDS>
</REGISTER>
<REGISTER NAME="UE_FFD2">
<PROPERTY NAME="DESCRIPTION" VALUE="Uncorrectable Error First Failing Data Register , bits [95:64]"/>
<PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x208"/>
<PROPERTY NAME="SIZE" VALUE="1"/>
<PROPERTY NAME="ACCESS" VALUE="read-only"/>
<PROPERTY NAME="IS_ENABLED" VALUE="false"/>
<PROPERTY NAME="RESET_VALUE" VALUE="0"/>
<FIELDS>
<FIELD NAME="UE_FFD">
<PROPERTY NAME="DESCRIPTION" VALUE="Data (bits [95:64]) of the first occurrence of an uncorrectable error
"/>
<PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
<PROPERTY NAME="ACCESS" VALUE="read-only"/>
<PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
<PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
<PROPERTY NAME="READ_ACTION" VALUE=""/>
<PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
<PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
</FIELD>
</FIELDS>
</REGISTER>
<REGISTER NAME="UE_FFD3">
<PROPERTY NAME="DESCRIPTION" VALUE="Uncorrectable Error First Failing Data Register , bits [127:96]"/>
<PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x20C"/>
<PROPERTY NAME="SIZE" VALUE="1"/>
<PROPERTY NAME="ACCESS" VALUE="read-only"/>
<PROPERTY NAME="IS_ENABLED" VALUE="false"/>
<PROPERTY NAME="RESET_VALUE" VALUE="0"/>
<FIELDS>
<FIELD NAME="UE_FFD">
<PROPERTY NAME="DESCRIPTION" VALUE="Data (bits [127:96]) of the first occurrence of an uncorrectable error
"/>
<PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
<PROPERTY NAME="ACCESS" VALUE="read-only"/>
<PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
<PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
<PROPERTY NAME="READ_ACTION" VALUE=""/>
<PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
<PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
</FIELD>
</FIELDS>
</REGISTER>
<REGISTER NAME="FI_D0">
<PROPERTY NAME="DESCRIPTION" VALUE="Fault Inject Data Register, bits[31:0]"/>
<PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x300"/>
<PROPERTY NAME="SIZE" VALUE="1"/>
<PROPERTY NAME="ACCESS" VALUE="write-only"/>
<PROPERTY NAME="IS_ENABLED" VALUE="false"/>
<PROPERTY NAME="RESET_VALUE" VALUE="0"/>
<FIELDS>
<FIELD NAME="FI_D0">
<PROPERTY NAME="DESCRIPTION" VALUE="Bit positions set to 1 toggle the corresponding bits [31:0] of the next data word written to the block RAM.
The register is automatically cleared after the fault has been injected.
"/>
<PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
<PROPERTY NAME="ACCESS" VALUE="read-only"/>
<PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
<PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
<PROPERTY NAME="READ_ACTION" VALUE=""/>
<PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
<PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
</FIELD>
</FIELDS>
</REGISTER>
<REGISTER NAME="FI_D1">
<PROPERTY NAME="DESCRIPTION" VALUE="Fault Inject Data Register, bits[63:32]"/>
<PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x304"/>
<PROPERTY NAME="SIZE" VALUE="1"/>
<PROPERTY NAME="ACCESS" VALUE="write-only"/>
<PROPERTY NAME="IS_ENABLED" VALUE="false"/>
<PROPERTY NAME="RESET_VALUE" VALUE="0"/>
<FIELDS>
<FIELD NAME="FI_D1">
<PROPERTY NAME="DESCRIPTION" VALUE="Bit positions set to 1 toggle the corresponding bits [63:32] of the next data word written to the block RAM.
The register is automatically cleared after the fault has been injected.
"/>
<PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
<PROPERTY NAME="ACCESS" VALUE="read-only"/>
<PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
<PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
<PROPERTY NAME="READ_ACTION" VALUE=""/>
<PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
<PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
</FIELD>
</FIELDS>
</REGISTER>
<REGISTER NAME="FI_D2">
<PROPERTY NAME="DESCRIPTION" VALUE="Fault Inject Data Register, bits[95:64]"/>
<PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x308"/>
<PROPERTY NAME="SIZE" VALUE="1"/>
<PROPERTY NAME="ACCESS" VALUE="write-only"/>
<PROPERTY NAME="IS_ENABLED" VALUE="false"/>
<PROPERTY NAME="RESET_VALUE" VALUE="0"/>
<FIELDS>
<FIELD NAME="FI_D2">
<PROPERTY NAME="DESCRIPTION" VALUE="Bit positions set to 1 toggle the corresponding bits [95:64] of the next data word written to the block RAM.
The register is automatically cleared after the fault has been injected.
"/>
<PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
<PROPERTY NAME="ACCESS" VALUE="read-only"/>
<PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
<PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
<PROPERTY NAME="READ_ACTION" VALUE=""/>
<PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
<PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
</FIELD>
</FIELDS>
</REGISTER>
<REGISTER NAME="FI_D3">
<PROPERTY NAME="DESCRIPTION" VALUE="Fault Inject Data Register, bits[127:96]"/>
<PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x30C"/>
<PROPERTY NAME="SIZE" VALUE="1"/>
<PROPERTY NAME="ACCESS" VALUE="write-only"/>
<PROPERTY NAME="IS_ENABLED" VALUE="false"/>
<PROPERTY NAME="RESET_VALUE" VALUE="0"/>
<FIELDS>
<FIELD NAME="FI_D3">
<PROPERTY NAME="DESCRIPTION" VALUE="Bit positions set to 1 toggle the corresponding bits [127:96] of the next data word written to the block RAM.
The register is automatically cleared after the fault has been injected.
"/>
<PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
<PROPERTY NAME="ACCESS" VALUE="read-only"/>
<PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
<PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
<PROPERTY NAME="READ_ACTION" VALUE=""/>
<PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
<PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
</FIELD>
</FIELDS>
</REGISTER>
<REGISTER NAME="FI_ECC">
<PROPERTY NAME="DESCRIPTION" VALUE="Fault Inject ECC Register"/>
<PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x380"/>
<PROPERTY NAME="SIZE" VALUE="1"/>
<PROPERTY NAME="ACCESS" VALUE="write-only"/>
<PROPERTY NAME="IS_ENABLED" VALUE="false"/>
<PROPERTY NAME="RESET_VALUE" VALUE="0"/>
<FIELDS>
<FIELD NAME="FI_ECC">
<PROPERTY NAME="DESCRIPTION" VALUE="Bit positions set to 1 toggle the corresponding bit of the next ECC written to the block RAM.
The register is automatically cleared after the fault has been injected.
"/>
<PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
<PROPERTY NAME="ACCESS" VALUE="read-only"/>
<PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
<PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
<PROPERTY NAME="READ_ACTION" VALUE=""/>
<PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
<PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
</FIELD>
</FIELDS>
</REGISTER>
</REGISTERS>
</ADDRESSBLOCK>
</ADDRESSBLOCKS>
<PARAMETERS>
<PARAMETER NAME="C_BRAM_INST_MODE" VALUE="EXTERNAL"/>
<PARAMETER NAME="C_MEMORY_DEPTH" VALUE="16384"/>
<PARAMETER NAME="C_BRAM_ADDR_WIDTH" VALUE="14"/>
<PARAMETER NAME="C_S_AXI_ADDR_WIDTH" VALUE="16"/>
<PARAMETER NAME="C_S_AXI_DATA_WIDTH" VALUE="32"/>
<PARAMETER NAME="C_S_AXI_ID_WIDTH" VALUE="12"/>
<PARAMETER NAME="C_S_AXI_PROTOCOL" VALUE="AXI4"/>
<PARAMETER NAME="C_S_AXI_SUPPORTS_NARROW_BURST" VALUE="0"/>
<PARAMETER NAME="C_SINGLE_PORT_BRAM" VALUE="1"/>
<PARAMETER NAME="C_FAMILY" VALUE="zynq"/>
<PARAMETER NAME="C_READ_LATENCY" VALUE="1"/>
<PARAMETER NAME="C_RD_CMD_OPTIMIZATION" VALUE="0"/>
<PARAMETER NAME="C_S_AXI_CTRL_ADDR_WIDTH" VALUE="32"/>
<PARAMETER NAME="C_S_AXI_CTRL_DATA_WIDTH" VALUE="32"/>
<PARAMETER NAME="C_ECC" VALUE="0"/>
<PARAMETER NAME="C_ECC_TYPE" VALUE="0"/>
<PARAMETER NAME="C_FAULT_INJECT" VALUE="0"/>
<PARAMETER NAME="C_ECC_ONOFF_RESET_VALUE" VALUE="0"/>
<PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
<PARAMETER NAME="ID_WIDTH" VALUE="12"/>
<PARAMETER NAME="PROTOCOL" VALUE="AXI4"/>
<PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
<PARAMETER NAME="SINGLE_PORT_BRAM" VALUE="1"/>
<PARAMETER NAME="ECC_TYPE" VALUE="Hamming"/>
<PARAMETER NAME="USE_ECC" VALUE="0"/>
<PARAMETER NAME="FAULT_INJECT" VALUE="0"/>
<PARAMETER NAME="ECC_ONOFF_RESET_VALUE" VALUE="0"/>
<PARAMETER NAME="Component_Name" VALUE="design_1_axi_bram_ctrl_0_0"/>
<PARAMETER NAME="BMG_INSTANCE" VALUE="EXTERNAL"/>
<PARAMETER NAME="MEM_DEPTH" VALUE="16384"/>
<PARAMETER NAME="READ_LATENCY" VALUE="1"/>
<PARAMETER NAME="RD_CMD_OPTIMIZATION" VALUE="0"/>
<PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
<PARAMETER NAME="EDK_SPECIAL" VALUE="BRAM_CTRL"/>
<PARAMETER NAME="C_S_AXI_BASEADDR" VALUE="0x40000000"/>
<PARAMETER NAME="C_S_AXI_HIGHADDR" VALUE="0x4000FFFF"/>
</PARAMETERS>
<PORTS>
<PORT CLKFREQUENCY="1e+08" DIR="I" NAME="s_axi_aclk" SIGIS="clk" SIGNAME="processing_system7_0_FCLK_CLK0">
<CONNECTIONS>
<CONNECTION INSTANCE="processing_system7_0" PORT="FCLK_CLK0"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="s_axi_aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="processing_system7_0_FCLK_RESET0_N">
<CONNECTIONS>
<CONNECTION INSTANCE="processing_system7_0" PORT="FCLK_RESET0_N"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="11" NAME="s_axi_awid" RIGHT="0" SIGIS="undef" SIGNAME="CustomIOP_axi_bram_ctrl_0_s_axi_awid">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_0" PORT="M00_AXI_awid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="15" NAME="s_axi_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="CustomIOP_axi_bram_ctrl_0_s_axi_awaddr">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_0" PORT="M00_AXI_awaddr"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="7" NAME="s_axi_awlen" RIGHT="0" SIGIS="undef" SIGNAME="CustomIOP_axi_bram_ctrl_0_s_axi_awlen">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_0" PORT="M00_AXI_awlen"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="2" NAME="s_axi_awsize" RIGHT="0" SIGIS="undef" SIGNAME="CustomIOP_axi_bram_ctrl_0_s_axi_awsize">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_0" PORT="M00_AXI_awsize"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="1" NAME="s_axi_awburst" RIGHT="0" SIGIS="undef" SIGNAME="CustomIOP_axi_bram_ctrl_0_s_axi_awburst">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_0" PORT="M00_AXI_awburst"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="s_axi_awlock" SIGIS="undef" SIGNAME="CustomIOP_axi_bram_ctrl_0_s_axi_awlock">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_0" PORT="M00_AXI_awlock"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="3" NAME="s_axi_awcache" RIGHT="0" SIGIS="undef" SIGNAME="CustomIOP_axi_bram_ctrl_0_s_axi_awcache">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_0" PORT="M00_AXI_awcache"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="2" NAME="s_axi_awprot" RIGHT="0" SIGIS="undef" SIGNAME="CustomIOP_axi_bram_ctrl_0_s_axi_awprot">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_0" PORT="M00_AXI_awprot"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="s_axi_awvalid" SIGIS="undef" SIGNAME="CustomIOP_axi_bram_ctrl_0_s_axi_awvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_0" PORT="M00_AXI_awvalid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="s_axi_awready" SIGIS="undef" SIGNAME="CustomIOP_axi_bram_ctrl_0_s_axi_awready">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_0" PORT="M00_AXI_awready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="31" NAME="s_axi_wdata" RIGHT="0" SIGIS="undef" SIGNAME="CustomIOP_axi_bram_ctrl_0_s_axi_wdata">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_0" PORT="M00_AXI_wdata"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="3" NAME="s_axi_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="CustomIOP_axi_bram_ctrl_0_s_axi_wstrb">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_0" PORT="M00_AXI_wstrb"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="s_axi_wlast" SIGIS="undef" SIGNAME="CustomIOP_axi_bram_ctrl_0_s_axi_wlast">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_0" PORT="M00_AXI_wlast"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="s_axi_wvalid" SIGIS="undef" SIGNAME="CustomIOP_axi_bram_ctrl_0_s_axi_wvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_0" PORT="M00_AXI_wvalid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="s_axi_wready" SIGIS="undef" SIGNAME="CustomIOP_axi_bram_ctrl_0_s_axi_wready">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_0" PORT="M00_AXI_wready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="11" NAME="s_axi_bid" RIGHT="0" SIGIS="undef" SIGNAME="CustomIOP_axi_bram_ctrl_0_s_axi_bid">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_0" PORT="M00_AXI_bid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="1" NAME="s_axi_bresp" RIGHT="0" SIGIS="undef" SIGNAME="CustomIOP_axi_bram_ctrl_0_s_axi_bresp">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_0" PORT="M00_AXI_bresp"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="s_axi_bvalid" SIGIS="undef" SIGNAME="CustomIOP_axi_bram_ctrl_0_s_axi_bvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_0" PORT="M00_AXI_bvalid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="s_axi_bready" SIGIS="undef" SIGNAME="CustomIOP_axi_bram_ctrl_0_s_axi_bready">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_0" PORT="M00_AXI_bready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="11" NAME="s_axi_arid" RIGHT="0" SIGIS="undef" SIGNAME="CustomIOP_axi_bram_ctrl_0_s_axi_arid">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_0" PORT="M00_AXI_arid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="15" NAME="s_axi_araddr" RIGHT="0" SIGIS="undef" SIGNAME="CustomIOP_axi_bram_ctrl_0_s_axi_araddr">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_0" PORT="M00_AXI_araddr"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="7" NAME="s_axi_arlen" RIGHT="0" SIGIS="undef" SIGNAME="CustomIOP_axi_bram_ctrl_0_s_axi_arlen">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_0" PORT="M00_AXI_arlen"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="2" NAME="s_axi_arsize" RIGHT="0" SIGIS="undef" SIGNAME="CustomIOP_axi_bram_ctrl_0_s_axi_arsize">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_0" PORT="M00_AXI_arsize"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="1" NAME="s_axi_arburst" RIGHT="0" SIGIS="undef" SIGNAME="CustomIOP_axi_bram_ctrl_0_s_axi_arburst">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_0" PORT="M00_AXI_arburst"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="s_axi_arlock" SIGIS="undef" SIGNAME="CustomIOP_axi_bram_ctrl_0_s_axi_arlock">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_0" PORT="M00_AXI_arlock"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="3" NAME="s_axi_arcache" RIGHT="0" SIGIS="undef" SIGNAME="CustomIOP_axi_bram_ctrl_0_s_axi_arcache">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_0" PORT="M00_AXI_arcache"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="2" NAME="s_axi_arprot" RIGHT="0" SIGIS="undef" SIGNAME="CustomIOP_axi_bram_ctrl_0_s_axi_arprot">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_0" PORT="M00_AXI_arprot"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="s_axi_arvalid" SIGIS="undef" SIGNAME="CustomIOP_axi_bram_ctrl_0_s_axi_arvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_0" PORT="M00_AXI_arvalid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="s_axi_arready" SIGIS="undef" SIGNAME="CustomIOP_axi_bram_ctrl_0_s_axi_arready">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_0" PORT="M00_AXI_arready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="11" NAME="s_axi_rid" RIGHT="0" SIGIS="undef" SIGNAME="CustomIOP_axi_bram_ctrl_0_s_axi_rid">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_0" PORT="M00_AXI_rid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="31" NAME="s_axi_rdata" RIGHT="0" SIGIS="undef" SIGNAME="CustomIOP_axi_bram_ctrl_0_s_axi_rdata">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_0" PORT="M00_AXI_rdata"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="1" NAME="s_axi_rresp" RIGHT="0" SIGIS="undef" SIGNAME="CustomIOP_axi_bram_ctrl_0_s_axi_rresp">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_0" PORT="M00_AXI_rresp"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="s_axi_rlast" SIGIS="undef" SIGNAME="CustomIOP_axi_bram_ctrl_0_s_axi_rlast">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_0" PORT="M00_AXI_rlast"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="s_axi_rvalid" SIGIS="undef" SIGNAME="CustomIOP_axi_bram_ctrl_0_s_axi_rvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_0" PORT="M00_AXI_rvalid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="s_axi_rready" SIGIS="undef" SIGNAME="CustomIOP_axi_bram_ctrl_0_s_axi_rready">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_interconnect_0" PORT="M00_AXI_rready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="bram_rst_a" SIGIS="rst" SIGNAME="CustomIOP_axi_bram_ctrl_0_bram_rst_a">
<CONNECTIONS>
<CONNECTION INSTANCE="CustomIOP_microblaze_0_local_memory_lmb_bram" PORT="rstb"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="bram_clk_a" SIGIS="clk" SIGNAME="CustomIOP_axi_bram_ctrl_0_bram_clk_a">
<CONNECTIONS>
<CONNECTION INSTANCE="CustomIOP_microblaze_0_local_memory_lmb_bram" PORT="clkb"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="bram_en_a" SIGIS="undef" SIGNAME="CustomIOP_axi_bram_ctrl_0_bram_en_a">
<CONNECTIONS>
<CONNECTION INSTANCE="CustomIOP_microblaze_0_local_memory_lmb_bram" PORT="enb"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="3" NAME="bram_we_a" RIGHT="0" SIGIS="undef" SIGNAME="CustomIOP_axi_bram_ctrl_0_bram_we_a">
<CONNECTIONS>
<CONNECTION INSTANCE="CustomIOP_microblaze_0_local_memory_lmb_bram" PORT="web"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="15" NAME="bram_addr_a" RIGHT="0" SIGIS="undef" SIGNAME="CustomIOP_axi_bram_ctrl_0_bram_addr_a">
<CONNECTIONS>
<CONNECTION INSTANCE="CustomIOP_microblaze_0_local_memory_lmb_bram" PORT="addrb"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="31" NAME="bram_wrdata_a" RIGHT="0" SIGIS="undef" SIGNAME="CustomIOP_axi_bram_ctrl_0_bram_wrdata_a">
<CONNECTIONS>
<CONNECTION INSTANCE="CustomIOP_microblaze_0_local_memory_lmb_bram" PORT="dinb"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="31" NAME="bram_rddata_a" RIGHT="0" SIGIS="undef" SIGNAME="CustomIOP_axi_bram_ctrl_0_bram_rddata_a">
<CONNECTIONS>
<CONNECTION INSTANCE="CustomIOP_microblaze_0_local_memory_lmb_bram" PORT="doutb"/>
</CONNECTIONS>
</PORT>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="axi_interconnect_0_M00_AXI" DATAWIDTH="32" NAME="S_AXI" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
<PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
<PARAMETER NAME="PROTOCOL" VALUE="AXI4"/>
<PARAMETER NAME="FREQ_HZ" VALUE="1e+08"/>
<PARAMETER NAME="ID_WIDTH" VALUE="12"/>
<PARAMETER NAME="ADDR_WIDTH" VALUE="16"/>
<PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
<PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
<PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
<PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
<PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
<PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
<PARAMETER NAME="HAS_BURST" VALUE="1"/>
<PARAMETER NAME="HAS_LOCK" VALUE="1"/>
<PARAMETER NAME="HAS_PROT" VALUE="1"/>
<PARAMETER NAME="HAS_CACHE" VALUE="1"/>
<PARAMETER NAME="HAS_QOS" VALUE="0"/>
<PARAMETER NAME="HAS_REGION" VALUE="0"/>
<PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
<PARAMETER NAME="HAS_BRESP" VALUE="1"/>
<PARAMETER NAME="HAS_RRESP" VALUE="1"/>
<PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
<PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="8"/>
<PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="8"/>
<PARAMETER NAME="MAX_BURST_LENGTH" VALUE="16"/>
<PARAMETER NAME="PHASE" VALUE="0.000"/>
<PARAMETER NAME="CLK_DOMAIN" VALUE="design_1_processing_system7_0_0_FCLK_CLK0"/>
<PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
<PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
<PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
<PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
<PARAMETER NAME="INSERT_VIP" VALUE="0"/>
<PORTMAPS>
<PORTMAP LOGICAL="ARADDR" PHYSICAL="s_axi_araddr"/>
<PORTMAP LOGICAL="ARBURST" PHYSICAL="s_axi_arburst"/>
<PORTMAP LOGICAL="ARCACHE" PHYSICAL="s_axi_arcache"/>
<PORTMAP LOGICAL="ARID" PHYSICAL="s_axi_arid"/>
<PORTMAP LOGICAL="ARLEN" PHYSICAL="s_axi_arlen"/>
<PORTMAP LOGICAL="ARLOCK" PHYSICAL="s_axi_arlock"/>
<PORTMAP LOGICAL="ARPROT" PHYSICAL="s_axi_arprot"/>
<PORTMAP LOGICAL="ARREADY" PHYSICAL="s_axi_arready"/>
<PORTMAP LOGICAL="ARSIZE" PHYSICAL="s_axi_arsize"/>
<PORTMAP LOGICAL="ARVALID" PHYSICAL="s_axi_arvalid"/>
<PORTMAP LOGICAL="AWADDR" PHYSICAL="s_axi_awaddr"/>
<PORTMAP LOGICAL="AWBURST" PHYSICAL="s_axi_awburst"/>
<PORTMAP LOGICAL="AWCACHE" PHYSICAL="s_axi_awcache"/>
<PORTMAP LOGICAL="AWID" PHYSICAL="s_axi_awid"/>
<PORTMAP LOGICAL="AWLEN" PHYSICAL="s_axi_awlen"/>
<PORTMAP LOGICAL="AWLOCK" PHYSICAL="s_axi_awlock"/>
<PORTMAP LOGICAL="AWPROT" PHYSICAL="s_axi_awprot"/>
<PORTMAP LOGICAL="AWREADY" PHYSICAL="s_axi_awready"/>
<PORTMAP LOGICAL="AWSIZE" PHYSICAL="s_axi_awsize"/>
<PORTMAP LOGICAL="AWVALID" PHYSICAL="s_axi_awvalid"/>
<PORTMAP LOGICAL="BID" PHYSICAL="s_axi_bid"/>
<PORTMAP LOGICAL="BREADY" PHYSICAL="s_axi_bready"/>
<PORTMAP LOGICAL="BRESP" PHYSICAL="s_axi_bresp"/>
<PORTMAP LOGICAL="BVALID" PHYSICAL="s_axi_bvalid"/>
<PORTMAP LOGICAL="RDATA" PHYSICAL="s_axi_rdata"/>
<PORTMAP LOGICAL="RID" PHYSICAL="s_axi_rid"/>
<PORTMAP LOGICAL="RLAST" PHYSICAL="s_axi_rlast"/>
<PORTMAP LOGICAL="RREADY" PHYSICAL="s_axi_rready"/>
<PORTMAP LOGICAL="RRESP" PHYSICAL="s_axi_rresp"/>
<PORTMAP LOGICAL="RVALID" PHYSICAL="s_axi_rvalid"/>
<PORTMAP LOGICAL="WDATA" PHYSICAL="s_axi_wdata"/>
<PORTMAP LOGICAL="WLAST" PHYSICAL="s_axi_wlast"/>
<PORTMAP LOGICAL="WREADY" PHYSICAL="s_axi_wready"/>
<PORTMAP LOGICAL="WSTRB" PHYSICAL="s_axi_wstrb"/>
<PORTMAP LOGICAL="WVALID" PHYSICAL="s_axi_wvalid"/>
</PORTMAPS>
</BUSINTERFACE>
<BUSINTERFACE BUSNAME="CustomIOP_axi_bram_ctrl_0_BRAM_PORTA" NAME="BRAM_PORTA" TYPE="INITIATOR" VLNV="xilinx.com:interface:bram:1.0">
<PARAMETER NAME="MASTER_TYPE" VALUE="BRAM_CTRL"/>
<PARAMETER NAME="MEM_SIZE" VALUE="65536"/>
<PARAMETER NAME="MEM_WIDTH" VALUE="32"/>
<PARAMETER NAME="MEM_ECC" VALUE="NONE"/>
<PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
<PARAMETER NAME="READ_LATENCY" VALUE="1"/>
<PORTMAPS>
<PORTMAP LOGICAL="ADDR" PHYSICAL="bram_addr_a"/>
<PORTMAP LOGICAL="CLK" PHYSICAL="bram_clk_a"/>
<PORTMAP LOGICAL="DIN" PHYSICAL="bram_wrdata_a"/>
<PORTMAP LOGICAL="DOUT" PHYSICAL="bram_rddata_a"/>
<PORTMAP LOGICAL="EN" PHYSICAL="bram_en_a"/>
<PORTMAP LOGICAL="RST" PHYSICAL="bram_rst_a"/>
<PORTMAP LOGICAL="WE" PHYSICAL="bram_we_a"/>
</PORTMAPS>
</BUSINTERFACE>
</BUSINTERFACES>
</MODULE>
<MODULE COREREVISION="23" FULLNAME="/CustomIOP/axi_gpio_0" HWVERSION="2.0" INSTANCE="CustomIOP_axi_gpio_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axi_gpio" VLNV="xilinx.com:ip:axi_gpio:2.0">
<DOCUMENTS>
<DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_gpio;v=v2_0;d=pg144-axi-gpio.pdf"/>
</DOCUMENTS>
<ADDRESSBLOCKS>
<ADDRESSBLOCK ACCESS="read-write" INTERFACE="S_AXI" NAME="Reg" RANGE="4096" USAGE="register">
<REGISTERS>
<REGISTER NAME="GPIO_DATA">
<PROPERTY NAME="DESCRIPTION" VALUE="Channel-1 AXI GPIO Data register"/>
<PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0"/>
<PROPERTY NAME="SIZE" VALUE="1"/>
<PROPERTY NAME="ACCESS" VALUE="read-write"/>
<PROPERTY NAME="IS_ENABLED" VALUE="true"/>
<PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
<FIELDS>
<FIELD NAME="Channel_1_GPIO_DATA">
<PROPERTY NAME="DESCRIPTION" VALUE="AXI GPIO Data Register.
For each I/O bit programmed as input
 R - Reads value on the input pin.
 W - No effect.
For each I/O bit programmed as output
 R - Reads value on GPIO_O pins
 W - Writes value to the corresponding AXI GPIO 
 data register bit and output pin
"/>
<PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
<PROPERTY NAME="ACCESS" VALUE="read-write"/>
<PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
<PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
<PROPERTY NAME="READ_ACTION" VALUE=""/>
<PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
<PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
</FIELD>
</FIELDS>
</REGISTER>
<REGISTER NAME="GPIO_TRI">
<PROPERTY NAME="DESCRIPTION" VALUE="Channel-1 AXI GPIO 3-State Control register"/>
<PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x4"/>
<PROPERTY NAME="SIZE" VALUE="1"/>
<PROPERTY NAME="ACCESS" VALUE="read-write"/>
<PROPERTY NAME="IS_ENABLED" VALUE="true"/>
<PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
<FIELDS>
<FIELD NAME="Channel_1_GPIO_TRI">
<PROPERTY NAME="DESCRIPTION" VALUE="AXI GPIO 3-State Control Register
Each I/O pin of the AXI GPIO is individually programmable as an input or output For each of the bits 0 - I/O pin configured as output 1 - I/O pin configured as input
"/>
<PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
<PROPERTY NAME="ACCESS" VALUE="read-write"/>
<PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
<PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
<PROPERTY NAME="READ_ACTION" VALUE=""/>
<PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
<PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
</FIELD>
</FIELDS>
</REGISTER>
<REGISTER NAME="GPIO2_DATA">
<PROPERTY NAME="DESCRIPTION" VALUE="Channel-2 AXI GPIO Data register"/>
<PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x8"/>
<PROPERTY NAME="SIZE" VALUE="1"/>
<PROPERTY NAME="ACCESS" VALUE="read-write"/>
<PROPERTY NAME="IS_ENABLED" VALUE="true"/>
<PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
<FIELDS>
<FIELD NAME="Channel_2_GPIO_DATA">
<PROPERTY NAME="DESCRIPTION" VALUE="AXI GPIO Data Register.
For each I/O bit programmed as input
 R - Reads value on the input pin.
 W - No effect.
For each I/O bit programmed as output
 R - Reads value on GPIO_O pins
 W - Writes value to the corresponding AXI GPIO 
 data register bit and output pin
"/>
<PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
<PROPERTY NAME="ACCESS" VALUE="read-write"/>
<PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
<PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
<PROPERTY NAME="READ_ACTION" VALUE=""/>
<PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
<PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
</FIELD>
</FIELDS>
</REGISTER>
<REGISTER NAME="GPIO2_TRI">
<PROPERTY NAME="DESCRIPTION" VALUE="Channel-2 AXI GPIO 3-State Control register"/>
<PROPERTY NAME="ADDRESS_OFFSET" VALUE="0xC"/>
<PROPERTY NAME="SIZE" VALUE="1"/>
<PROPERTY NAME="ACCESS" VALUE="read-write"/>
<PROPERTY NAME="IS_ENABLED" VALUE="true"/>
<PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
<FIELDS>
<FIELD NAME="Channel_2_GPIO_TRI">
<PROPERTY NAME="DESCRIPTION" VALUE="AXI GPIO 3-State Control Register
Each I/O pin of the AXI GPIO is individually programmable as an input or output For each of the bits 0 - I/O pin configured as output 1 - I/O pin configured as input
"/>
<PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
<PROPERTY NAME="ACCESS" VALUE="read-write"/>
<PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
<PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
<PROPERTY NAME="READ_ACTION" VALUE=""/>
<PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
<PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
</FIELD>
</FIELDS>
</REGISTER>
<REGISTER NAME="GIER">
<PROPERTY NAME="DESCRIPTION" VALUE="Global_Interrupt_Enable register"/>
<PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x11C"/>
<PROPERTY NAME="SIZE" VALUE="32"/>
<PROPERTY NAME="ACCESS" VALUE="read-write"/>
<PROPERTY NAME="IS_ENABLED" VALUE="true"/>
<PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
<FIELDS>
<FIELD NAME="Global_Interrupt_Enable">
<PROPERTY NAME="DESCRIPTION" VALUE="Master enable for the device interrupt output
 0 - Disabled
 1 - Enabled
"/>
<PROPERTY NAME="ADDRESS_OFFSET" VALUE="31"/>
<PROPERTY NAME="ACCESS" VALUE="read-write"/>
<PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
<PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
<PROPERTY NAME="READ_ACTION" VALUE=""/>
<PROPERTY NAME="BIT_OFFSET" VALUE="31"/>
<PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
</FIELD>
</FIELDS>
</REGISTER>
<REGISTER NAME="IP_IER">
<PROPERTY NAME="DESCRIPTION" VALUE="IP Interrupt Enable register"/>
<PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x128"/>
<PROPERTY NAME="SIZE" VALUE="32"/>
<PROPERTY NAME="ACCESS" VALUE="read-write"/>
<PROPERTY NAME="IS_ENABLED" VALUE="true"/>
<PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
<FIELDS>
<FIELD NAME="Channel_1_Interrupt_Enable">
<PROPERTY NAME="DESCRIPTION" VALUE="Enable Channel 1 Interrupt
 0 - Disabled (masked)
 1 - Enabled
"/>
<PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
<PROPERTY NAME="ACCESS" VALUE="read-write"/>
<PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
<PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
<PROPERTY NAME="READ_ACTION" VALUE=""/>
<PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
<PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
</FIELD>
<FIELD NAME="Channel_2_Interrupt_Enable">
<PROPERTY NAME="DESCRIPTION" VALUE="Enable Channel 2 Interrupt
 0 - Disabled (masked)
 1 - Enabled
"/>
<PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
<PROPERTY NAME="ACCESS" VALUE="read-write"/>
<PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
<PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
<PROPERTY NAME="READ_ACTION" VALUE=""/>
<PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
<PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
</FIELD>
</FIELDS>
</REGISTER>
<REGISTER NAME="IP_ISR">
<PROPERTY NAME="DESCRIPTION" VALUE="IP Interrupt Status register"/>
<PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x120"/>
<PROPERTY NAME="SIZE" VALUE="32"/>
<PROPERTY NAME="ACCESS" VALUE="read-write"/>
<PROPERTY NAME="IS_ENABLED" VALUE="true"/>
<PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
<FIELDS>
<FIELD NAME="Channel_1_Interrupt_Status">
<PROPERTY NAME="DESCRIPTION" VALUE="Channel 1 Interrupt Status
 0 - No Channel 1 input interrupt
 1 - Channel 1 input interrupt
"/>
<PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
<PROPERTY NAME="ACCESS" VALUE="read-write"/>
<PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
<PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
<PROPERTY NAME="READ_ACTION" VALUE=""/>
<PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
<PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
</FIELD>
<FIELD NAME="Channel_2_Interrupt_Status">
<PROPERTY NAME="DESCRIPTION" VALUE="Channel 2 Interrupt Status
 0 - No Channel 2 input interrupt
 1 - Channel 2 input interrupt
"/>
<PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
<PROPERTY NAME="ACCESS" VALUE="read-write"/>
<PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
<PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
<PROPERTY NAME="READ_ACTION" VALUE=""/>
<PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
<PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
</FIELD>
</FIELDS>
</REGISTER>
</REGISTERS>
</ADDRESSBLOCK>