From e0a763c490d8ef58dca867e0ef834978ccf8e17d Mon Sep 17 00:00:00 2001 From: Jay Foad Date: Tue, 23 Apr 2024 14:38:45 +0100 Subject: [PATCH] [AMDGPU] Fix GFX12 encoding of s_wait_event export_ready (#89622) As well as flipping the sense of the bit, GFX12 moved it from bit 0 to bit 1 in the encoded simm16 operand. --- llvm/lib/Target/AMDGPU/SOPInstructions.td | 2 +- llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.wait.event.ll | 10 +++------- 2 files changed, 4 insertions(+), 8 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/SOPInstructions.td b/llvm/lib/Target/AMDGPU/SOPInstructions.td index 0b7d45ee8c02..93b7e86b5f29 100644 --- a/llvm/lib/Target/AMDGPU/SOPInstructions.td +++ b/llvm/lib/Target/AMDGPU/SOPInstructions.td @@ -1803,7 +1803,7 @@ def : GCNPat< let SubtargetPredicate = isNotGFX12Plus in def : GCNPat <(int_amdgcn_s_wait_event_export_ready), (S_WAIT_EVENT (i16 0))>; let SubtargetPredicate = isGFX12Plus in - def : GCNPat <(int_amdgcn_s_wait_event_export_ready), (S_WAIT_EVENT (i16 1))>; + def : GCNPat <(int_amdgcn_s_wait_event_export_ready), (S_WAIT_EVENT (i16 2))>; // The first 10 bits of the mode register are the core FP mode on all // subtargets. diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.wait.event.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.wait.event.ll index 08c77148f6ae..433fefa43498 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.wait.event.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.wait.event.ll @@ -5,14 +5,10 @@ ; GCN-LABEL: {{^}}test_wait_event: ; GFX11: s_wait_event 0x0 -; GFX12: s_wait_event 0x1 +; GFX12: s_wait_event 0x2 -define amdgpu_ps void @test_wait_event() #0 { +define amdgpu_ps void @test_wait_event() { entry: - call void @llvm.amdgcn.s.wait.event.export.ready() #0 + call void @llvm.amdgcn.s.wait.event.export.ready() ret void } - -declare void @llvm.amdgcn.s.wait.event.export.ready() #0 - -attributes #0 = { nounwind }