diff --git a/drivers/serial/uart_pl011_ambiq.h b/drivers/serial/uart_pl011_ambiq.h
index 2223cbed5773f92..470e0e35a9530b0 100644
--- a/drivers/serial/uart_pl011_ambiq.h
+++ b/drivers/serial/uart_pl011_ambiq.h
@@ -50,9 +50,9 @@ static inline int clk_enable_ambiq_uart(const struct device *dev, uint32_t clk)
 	return pl011_ambiq_clk_set(dev, clk);
 }
 
-/* Problem: writes to pwrcfg reg take at most PWCTRL_MAX_WAIT_US time to propagate.
- * Solution: busy wait for PWCTRL_MAX_WAIT_US microseconds to ensure that register
- * writes have propagated.
+/* Problem: writes to power configure register takes some time to take effective.
+ * Solution: Check device's power status to ensure that register has taken effective.
+ * Note: busy wait is not allowed to use here due to UART is initiated before timer starts.
  */
 
 #define QUIRK_AMBIQ_UART_DEFINE(n)                                                                 \
@@ -60,8 +60,12 @@ static inline int clk_enable_ambiq_uart(const struct device *dev, uint32_t clk)
 	{                                                                                          \
 		uint32_t addr = DT_REG_ADDR(DT_INST_PHANDLE(n, ambiq_pwrcfg)) +                    \
 				DT_INST_PHA(n, ambiq_pwrcfg, offset);                              \
+		uint32_t pwr_status_addr = addr + 4;                                               \
 		sys_write32((sys_read32(addr) | DT_INST_PHA(n, ambiq_pwrcfg, mask)), addr);        \
-		k_busy_wait(PWRCTRL_MAX_WAIT_US);                                                  \
+		while ((sys_read32(pwr_status_addr) & DT_INST_PHA(n, ambiq_pwrcfg, mask)) !=       \
+		       DT_INST_PHA(n, ambiq_pwrcfg, mask)) {                                       \
+			arch_nop();                                                                \
+		};                                                                                 \
 		return 0;                                                                          \
 	}