From 92999e1ad948016abe02a10d67f7d4d04fb8a074 Mon Sep 17 00:00:00 2001 From: Neil McNeight Date: Mon, 20 Jul 2020 08:29:57 -0500 Subject: [PATCH] Update ti-stellaris-boosterpack40 with KiCad 5.1.6 * Repointed all symbols and footprints to current libraries. * Updated header pinouts to match TI documentation. * Updated documentation. * Derived new template for 20-pin BoosterPack. --- .../boosterpack20.dcm | 11 + .../boosterpack20.lib | 54 ++ .../boosterpack20_min.kicad_pcb | 457 +++++++++++++++ .../boosterpack20_min.pro | 237 ++++++++ .../boosterpack20_min.sch | 100 ++++ .../meta/icon.png | Bin 0 -> 5246 bytes .../meta/info.html | 23 + .../meta/launchpad_standard20.png | Bin 0 -> 107099 bytes .../boosterpack.lib | 114 ---- .../boosterpack40.dcm | 19 + .../boosterpack40.lib | 104 ++++ .../boosterpack40_min.kicad_pcb | 552 +++++++++++------- .../boosterpack40_min.pro | 256 +++++++- .../boosterpack40_min.sch | 161 +++-- .../meta/icon.png | Bin 12485 -> 5482 bytes .../meta/info.html | 5 +- 16 files changed, 1662 insertions(+), 431 deletions(-) create mode 100644 Projects/ti-stellaris-boosterpack20_min/boosterpack20.dcm create mode 100644 Projects/ti-stellaris-boosterpack20_min/boosterpack20.lib create mode 100644 Projects/ti-stellaris-boosterpack20_min/boosterpack20_min.kicad_pcb create mode 100644 Projects/ti-stellaris-boosterpack20_min/boosterpack20_min.pro create mode 100644 Projects/ti-stellaris-boosterpack20_min/boosterpack20_min.sch create mode 100644 Projects/ti-stellaris-boosterpack20_min/meta/icon.png create mode 100644 Projects/ti-stellaris-boosterpack20_min/meta/info.html create mode 100644 Projects/ti-stellaris-boosterpack20_min/meta/launchpad_standard20.png delete mode 100644 Projects/ti-stellaris-boosterpack40_min/boosterpack.lib create mode 100644 Projects/ti-stellaris-boosterpack40_min/boosterpack40.dcm create mode 100644 Projects/ti-stellaris-boosterpack40_min/boosterpack40.lib diff --git a/Projects/ti-stellaris-boosterpack20_min/boosterpack20.dcm b/Projects/ti-stellaris-boosterpack20_min/boosterpack20.dcm new file mode 100644 index 0000000..b3b8df1 --- /dev/null +++ b/Projects/ti-stellaris-boosterpack20_min/boosterpack20.dcm @@ -0,0 +1,11 @@ +EESchema-DOCLIB Version 2.0 +# +$CMP Ti_Booster_20_J1 +F https://www.ti.com/lit/pdf/slaa542 +$ENDCMP +# +$CMP Ti_Booster_20_J2 +F https://www.ti.com/lit/pdf/slaa542 +$ENDCMP +# +#End Doc Library diff --git a/Projects/ti-stellaris-boosterpack20_min/boosterpack20.lib b/Projects/ti-stellaris-boosterpack20_min/boosterpack20.lib new file mode 100644 index 0000000..b5883cd --- /dev/null +++ b/Projects/ti-stellaris-boosterpack20_min/boosterpack20.lib @@ -0,0 +1,54 @@ +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# Ti_Booster_20_J1 +# +DEF Ti_Booster_20_J1 J1 0 40 Y Y 1 F N +F0 "J1" 0 650 50 H V C CNN +F1 "Ti_Booster_20_J1" 0 -650 50 H V C CNN +F2 "Connector_PinHeader_2.54mm:PinHeader_1x10_P2.54mm_Vertical" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + PinHeader*1x10*P2.54mm* +$ENDFPLIST +DRAW +S 300 550 -300 -550 0 1 10 f +X VCC 1 400 450 100 L 50 50 1 1 W +X GPIO2 10 400 -450 100 L 50 50 1 1 B +X Analog_In 2 400 350 100 L 50 50 1 1 B +X UART_RX 3 400 250 100 L 50 50 1 1 B +X UART_TX 4 400 150 100 L 50 50 1 1 B +X GPIO_IRQ0 5 400 50 100 L 50 50 1 1 B +X SCLK_A 6 400 -50 100 L 50 50 1 1 B +X SCLK_B 7 400 -150 100 L 50 50 1 1 B +X GPIO0 8 400 -250 100 L 50 50 1 1 B +X GPIO1 9 400 -350 100 L 50 50 1 1 B +ENDDRAW +ENDDEF +# +# Ti_Booster_20_J2 +# +DEF Ti_Booster_20_J2 J2 0 40 Y Y 1 F N +F0 "J2" 0 650 50 H V C CNN +F1 "Ti_Booster_20_J2" 0 -650 50 H V C CNN +F2 "Connector_PinHeader_2.54mm:PinHeader_1x10_P2.54mm_Vertical" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + PinHeader*1x10*P2.54mm* +$ENDFPLIST +DRAW +S -300 550 300 -550 0 1 10 f +X GND 1 -400 450 100 R 50 50 1 1 W +X GPIO3 10 -400 -450 100 R 50 50 1 1 B +X Timer_Out 2 -400 350 100 R 50 50 1 1 B +X GPIO_IRQ1 3 -400 250 100 R 50 50 1 1 B +X TEST 4 -400 150 100 R 50 50 1 1 B +X RESET 5 -400 50 100 R 50 50 1 1 B +X SIMO_B/SDA 6 -400 -50 100 R 50 50 1 1 B +X SOMI_B/SCL 7 -400 -150 100 R 50 50 1 1 B +X GPIO5 8 -400 -250 100 R 50 50 1 1 B +X GPIO4 9 -400 -350 100 R 50 50 1 1 B +ENDDRAW +ENDDEF +# +#End Library diff --git a/Projects/ti-stellaris-boosterpack20_min/boosterpack20_min.kicad_pcb b/Projects/ti-stellaris-boosterpack20_min/boosterpack20_min.kicad_pcb new file mode 100644 index 0000000..0d798c0 --- /dev/null +++ b/Projects/ti-stellaris-boosterpack20_min/boosterpack20_min.kicad_pcb @@ -0,0 +1,457 @@ +(kicad_pcb (version 20171130) (host pcbnew "(5.1.6)-1") + + (general + (thickness 1.6) + (drawings 14) + (tracks 0) + (zones 0) + (modules 3) + (nets 3) + ) + + (page A3) + (layers + (0 F.Cu signal) + (31 B.Cu signal) + (32 B.Adhes user) + (33 F.Adhes user) + (34 B.Paste user) + (35 F.Paste user) + (36 B.SilkS user) + (37 F.SilkS user) + (38 B.Mask user) + (39 F.Mask user) + (40 Dwgs.User user) + (41 Cmts.User user) + (42 Eco1.User user) + (43 Eco2.User user) + (44 Edge.Cuts user) + (45 Margin user) + (46 B.CrtYd user) + (47 F.CrtYd user) + ) + + (setup + (last_trace_width 0.254) + (trace_clearance 0.1524) + (zone_clearance 0.508) + (zone_45_only no) + (trace_min 0.254) + (via_size 0.889) + (via_drill 0.635) + (via_min_size 0.889) + (via_min_drill 0.508) + (uvia_size 0.508) + (uvia_drill 0.127) + (uvias_allowed no) + (uvia_min_size 0.508) + (uvia_min_drill 0.127) + (edge_width 0.14986) + (segment_width 0.20066) + (pcb_text_width 0.254) + (pcb_text_size 1.27 1.27) + (mod_edge_width 0.14986) + (mod_text_size 1 1) + (mod_text_width 0.15) + (pad_size 1 1) + (pad_drill 0.6) + (pad_to_mask_clearance 0) + (aux_axis_origin 182.88 113.03) + (grid_origin 182.88 113.03) + (visible_elements 7FFFFFFF) + (pcbplotparams + (layerselection 0x00030_ffffffff) + (usegerberextensions true) + (usegerberattributes false) + (usegerberadvancedattributes false) + (creategerberjobfile false) + (excludeedgelayer true) + (linewidth 0.150000) + (plotframeref false) + (viasonmask false) + (mode 1) + (useauxorigin false) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15.000000) + (psnegative false) + (psa4output false) + (plotreference true) + (plotvalue true) + (plotinvisibletext false) + (padsonsilk false) + (subtractmaskfromsilk false) + (outputformat 1) + (mirror false) + (drillshape 1) + (scaleselection 1) + (outputdirectory "")) + ) + + (net 0 "") + (net 1 GND) + (net 2 VCC) + + (net_class Default "This is the default net class." + (clearance 0.1524) + (trace_width 0.254) + (via_dia 0.889) + (via_drill 0.635) + (uvia_dia 0.508) + (uvia_drill 0.127) + (diff_pair_width 0.254) + (diff_pair_gap 0.1524) + (add_net GND) + (add_net VCC) + ) + + (module Connector_PinHeader_2.54mm:PinHeader_1x03_P2.54mm_Vertical (layer F.Cu) (tedit 59FED5CC) (tstamp 5F1419EC) + (at 231.14 149.86) + (descr "Through hole straight pin header, 1x03, 2.54mm pitch, single row") + (tags "Through hole pin header THT 1x03 2.54mm single row") + (path /5F13DC7C) + (fp_text reference J3 (at 0 -2.33) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value Conn_01x03 (at 0 7.41) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text user %R (at 0 2.54 90) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1)) + (fp_line (start 1.27 -1.27) (end 1.27 6.35) (layer F.Fab) (width 0.1)) + (fp_line (start 1.27 6.35) (end -1.27 6.35) (layer F.Fab) (width 0.1)) + (fp_line (start -1.27 6.35) (end -1.27 -0.635) (layer F.Fab) (width 0.1)) + (fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1)) + (fp_line (start -1.33 6.41) (end 1.33 6.41) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.33 1.27) (end -1.33 6.41) (layer F.SilkS) (width 0.12)) + (fp_line (start 1.33 1.27) (end 1.33 6.41) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.8 -1.8) (end -1.8 6.85) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.8 6.85) (end 1.8 6.85) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.8 6.85) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05)) + (pad 3 thru_hole oval (at 0 5.08) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 2 VCC)) + (pad 2 thru_hole oval (at 0 2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 1 GND)) + (pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 1 GND)) + (model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x03_P2.54mm_Vertical.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Connector_PinHeader_2.54mm:PinHeader_1x10_P2.54mm_Vertical (layer F.Cu) (tedit 59FED5CC) (tstamp 5A7B9D07) + (at 231.14 121.92) + (descr "Through hole straight pin header, 1x10, 2.54mm pitch, single row") + (tags "Through hole pin header THT 1x10 2.54mm single row") + (path /5080DBF4) + (fp_text reference J2 (at 0 -2.33) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value Ti_Booster_20_J2 (at 0 25.19) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text user %R (at 0 11.43 90) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1)) + (fp_line (start 1.27 -1.27) (end 1.27 24.13) (layer F.Fab) (width 0.1)) + (fp_line (start 1.27 24.13) (end -1.27 24.13) (layer F.Fab) (width 0.1)) + (fp_line (start -1.27 24.13) (end -1.27 -0.635) (layer F.Fab) (width 0.1)) + (fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1)) + (fp_line (start -1.33 24.19) (end 1.33 24.19) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.33 1.27) (end -1.33 24.19) (layer F.SilkS) (width 0.12)) + (fp_line (start 1.33 1.27) (end 1.33 24.19) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.8 -1.8) (end -1.8 24.65) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.8 24.65) (end 1.8 24.65) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.8 24.65) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05)) + (pad 10 thru_hole oval (at 0 22.86) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) + (pad 9 thru_hole oval (at 0 20.32) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) + (pad 8 thru_hole oval (at 0 17.78) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) + (pad 7 thru_hole oval (at 0 15.24) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) + (pad 6 thru_hole oval (at 0 12.7) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) + (pad 5 thru_hole oval (at 0 10.16) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) + (pad 4 thru_hole oval (at 0 7.62) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) + (pad 3 thru_hole oval (at 0 5.08) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) + (pad 2 thru_hole oval (at 0 2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) + (pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 1 GND)) + (model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x10_P2.54mm_Vertical.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Connector_PinHeader_2.54mm:PinHeader_1x10_P2.54mm_Vertical (layer F.Cu) (tedit 59FED5CC) (tstamp 5A7B9E0C) + (at 185.42 121.92) + (descr "Through hole straight pin header, 1x10, 2.54mm pitch, single row") + (tags "Through hole pin header THT 1x10 2.54mm single row") + (path /5080DB5C) + (fp_text reference J1 (at 0 -2.33) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value Ti_Booster_20_J1 (at 0 25.19) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text user %R (at 0 11.43 90) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1)) + (fp_line (start 1.27 -1.27) (end 1.27 24.13) (layer F.Fab) (width 0.1)) + (fp_line (start 1.27 24.13) (end -1.27 24.13) (layer F.Fab) (width 0.1)) + (fp_line (start -1.27 24.13) (end -1.27 -0.635) (layer F.Fab) (width 0.1)) + (fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1)) + (fp_line (start -1.33 24.19) (end 1.33 24.19) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.33 1.27) (end -1.33 24.19) (layer F.SilkS) (width 0.12)) + (fp_line (start 1.33 1.27) (end 1.33 24.19) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.8 -1.8) (end -1.8 24.65) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.8 24.65) (end 1.8 24.65) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.8 24.65) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05)) + (pad 10 thru_hole oval (at 0 22.86) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) + (pad 9 thru_hole oval (at 0 20.32) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) + (pad 8 thru_hole oval (at 0 17.78) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) + (pad 7 thru_hole oval (at 0 15.24) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) + (pad 6 thru_hole oval (at 0 12.7) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) + (pad 5 thru_hole oval (at 0 10.16) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) + (pad 4 thru_hole oval (at 0 7.62) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) + (pad 3 thru_hole oval (at 0 5.08) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) + (pad 2 thru_hole oval (at 0 2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) + (pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 2 VCC)) + (model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x10_P2.54mm_Vertical.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (dimension 45.72 (width 0.254) (layer Dwgs.User) + (gr_text "1800 mils" (at 208.28 108.712) (layer Dwgs.User) + (effects (font (size 1.27 1.27) (thickness 0.254))) + ) + (feature1 (pts (xy 231.14 121.92) (xy 231.14 109.903579))) + (feature2 (pts (xy 185.42 121.92) (xy 185.42 109.903579))) + (crossbar (pts (xy 185.42 110.49) (xy 231.14 110.49))) + (arrow1a (pts (xy 231.14 110.49) (xy 230.013496 111.076421))) + (arrow1b (pts (xy 231.14 110.49) (xy 230.013496 109.903579))) + (arrow2a (pts (xy 185.42 110.49) (xy 186.546504 111.076421))) + (arrow2b (pts (xy 185.42 110.49) (xy 186.546504 109.903579))) + ) + (gr_text 20 (at 228.6 121.92) (layer Cmts.User) + (effects (font (size 1.27 1.27) (thickness 0.254)) (justify right)) + ) + (gr_text 11 (at 228.6 144.78) (layer Cmts.User) + (effects (font (size 1.27 1.27) (thickness 0.254)) (justify right)) + ) + (gr_text 10 (at 187.96 144.78) (layer Cmts.User) + (effects (font (size 1.27 1.27) (thickness 0.254)) (justify left)) + ) + (gr_text 1 (at 187.96 121.92) (layer Cmts.User) + (effects (font (size 1.27 1.27) (thickness 0.254)) (justify left)) + ) + (gr_line (start 182.88 147.32) (end 233.68 147.32) (layer Dwgs.User) (width 0.15)) + (dimension 43.18 (width 0.254) (layer Dwgs.User) + (gr_text "1700 mils" (at 174.752 134.62 270) (layer Dwgs.User) + (effects (font (size 1.27 1.27) (thickness 0.254))) + ) + (feature1 (pts (xy 182.88 156.21) (xy 175.943579 156.21))) + (feature2 (pts (xy 182.88 113.03) (xy 175.943579 113.03))) + (crossbar (pts (xy 176.53 113.03) (xy 176.53 156.21))) + (arrow1a (pts (xy 176.53 156.21) (xy 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(xy 186.859502 120.82582) (xy 186.800537 120.715506) (xy 186.721185 120.618815) (xy 186.624494 120.539463) + (xy 186.51418 120.480498) (xy 186.394482 120.444188) (xy 186.27 120.431928) (xy 184.57 120.431928) (xy 184.445518 120.444188) + (xy 184.32582 120.480498) (xy 184.215506 120.539463) (xy 184.118815 120.618815) (xy 184.039463 120.715506) (xy 183.980498 120.82582) + (xy 183.944188 120.945518) (xy 183.931928 121.07) (xy 183.58993 121.07) (xy 183.58993 113.7412) (xy 232.9688 113.7412) + ) + ) + ) +) diff --git a/Projects/ti-stellaris-boosterpack20_min/boosterpack20_min.pro b/Projects/ti-stellaris-boosterpack20_min/boosterpack20_min.pro new file mode 100644 index 0000000..f807c75 --- /dev/null +++ b/Projects/ti-stellaris-boosterpack20_min/boosterpack20_min.pro @@ -0,0 +1,237 @@ +update=19/07/2020 09:58:10 +version=1 +last_client=kicad +[cvpcb] +version=1 +NetIExt=net +[cvpcb/libraries] +EquName1=devcms +[general] +version=1 +[eeschema] +version=1 +LibDir= +[pcbnew] +version=1 +PageLayoutDescrFile= +LastNetListRead=boosterpack20.net +CopperLayerCount=2 +BoardThickness=1.6 +AllowMicroVias=0 +AllowBlindVias=0 +RequireCourtyardDefinitions=0 +ProhibitOverlappingCourtyards=1 +MinTrackWidth=0.254 +MinViaDiameter=0.889 +MinViaDrill=0.508 +MinMicroViaDiameter=0.508 +MinMicroViaDrill=0.127 +MinHoleToHole=0.25 +TrackWidth1=0.254 +ViaDiameter1=0.889 +ViaDrill1=0.635 +dPairWidth1=0.254 +dPairGap1=0.254 +dPairViaGap1=0.25 +SilkLineWidth=0.14986 +SilkTextSizeV=1.27 +SilkTextSizeH=1.27 +SilkTextSizeThickness=0.254 +SilkTextItalic=0 +SilkTextUpright=1 +CopperLineWidth=0.20066 +CopperTextSizeV=1.27 +CopperTextSizeH=1.27 +CopperTextThickness=0.254 +CopperTextItalic=0 +CopperTextUpright=1 +EdgeCutLineWidth=0.14986 +CourtyardLineWidth=0.05 +OthersLineWidth=0.254 +OthersTextSizeV=1.27 +OthersTextSizeH=1.27 +OthersTextSizeThickness=0.254 +OthersTextItalic=0 +OthersTextUpright=1 +SolderMaskClearance=0 +SolderMaskMinWidth=0 +SolderPasteClearance=0 +SolderPasteRatio=-0 +[pcbnew/Layer.F.Cu] +Name=F.Cu +Type=0 +Enabled=1 +[pcbnew/Layer.In1.Cu] +Name=In1.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In2.Cu] +Name=In2.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In3.Cu] +Name=In3.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In4.Cu] +Name=In4.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In5.Cu] +Name=In5.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In6.Cu] +Name=In6.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In7.Cu] +Name=In7.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In8.Cu] +Name=In8.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In9.Cu] +Name=In9.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In10.Cu] +Name=In10.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In11.Cu] +Name=In11.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In12.Cu] +Name=In12.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In13.Cu] +Name=In13.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In14.Cu] +Name=In14.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In15.Cu] +Name=In15.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In16.Cu] +Name=In16.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In17.Cu] +Name=In17.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In18.Cu] +Name=In18.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In19.Cu] +Name=In19.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In20.Cu] +Name=In20.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In21.Cu] +Name=In21.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In22.Cu] +Name=In22.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In23.Cu] +Name=In23.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In24.Cu] +Name=In24.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In25.Cu] +Name=In25.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In26.Cu] +Name=In26.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In27.Cu] +Name=In27.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In28.Cu] +Name=In28.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In29.Cu] +Name=In29.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In30.Cu] +Name=In30.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.B.Cu] +Name=B.Cu +Type=0 +Enabled=1 +[pcbnew/Layer.B.Adhes] +Enabled=1 +[pcbnew/Layer.F.Adhes] +Enabled=1 +[pcbnew/Layer.B.Paste] +Enabled=1 +[pcbnew/Layer.F.Paste] +Enabled=1 +[pcbnew/Layer.B.SilkS] +Enabled=1 +[pcbnew/Layer.F.SilkS] +Enabled=1 +[pcbnew/Layer.B.Mask] +Enabled=1 +[pcbnew/Layer.F.Mask] +Enabled=1 +[pcbnew/Layer.Dwgs.User] +Enabled=1 +[pcbnew/Layer.Cmts.User] +Enabled=1 +[pcbnew/Layer.Eco1.User] +Enabled=1 +[pcbnew/Layer.Eco2.User] +Enabled=1 +[pcbnew/Layer.Edge.Cuts] +Enabled=1 +[pcbnew/Layer.Margin] +Enabled=1 +[pcbnew/Layer.B.CrtYd] +Enabled=1 +[pcbnew/Layer.F.CrtYd] +Enabled=1 +[pcbnew/Layer.B.Fab] +Enabled=0 +[pcbnew/Layer.F.Fab] +Enabled=0 +[pcbnew/Layer.Rescue] +Enabled=0 +[pcbnew/Netclasses] +[pcbnew/Netclasses/Default] +Name=Default +Clearance=0.254 +TrackWidth=0.254 +ViaDiameter=0.889 +ViaDrill=0.635 +uViaDiameter=0.508 +uViaDrill=0.127 +dPairWidth=0.254 +dPairGap=0.254 +dPairViaGap=0.25 diff --git a/Projects/ti-stellaris-boosterpack20_min/boosterpack20_min.sch b/Projects/ti-stellaris-boosterpack20_min/boosterpack20_min.sch new file mode 100644 index 0000000..09ec645 --- /dev/null +++ b/Projects/ti-stellaris-boosterpack20_min/boosterpack20_min.sch @@ -0,0 +1,100 @@ +EESchema Schematic File Version 4 +EELAYER 30 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "20-Pin LaunchPad and BoosterPack Standard" +Date "2020-07-19" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L power:GND #PWR0101 +U 1 1 5080AA99 +P 9550 850 +F 0 "#PWR0101" H 9550 600 50 0001 C CNN +F 1 "GND" H 9550 700 50 0000 C CNN +F 2 "" H 9550 850 50 0001 C CNN +F 3 "" H 9550 850 50 0001 C CNN + 1 9550 850 + 0 1 1 0 +$EndComp +$Comp +L boosterpack20:Ti_Booster_20_J1 J1 +U 1 1 5080DB5C +P 1550 1300 +F 0 "J1" H 1220 1346 50 0000 R CNN +F 1 "Ti_Booster_20_J1" H 1220 1255 50 0000 R CNN +F 2 "Connector_PinHeader_2.54mm:PinHeader_1x10_P2.54mm_Vertical" H 1550 1300 50 0001 C CNN +F 3 "https://www.ti.com/lit/pdf/slaa542" H 1550 1300 50 0001 C CNN + 1 1550 1300 + 1 0 0 -1 +$EndComp +$Comp +L boosterpack20:Ti_Booster_20_J2 J2 +U 1 1 5080DBF4 +P 9950 1300 +F 0 "J2" H 10280 1346 50 0000 L CNN +F 1 "Ti_Booster_20_J2" H 10280 1255 50 0000 L CNN +F 2 "Connector_PinHeader_2.54mm:PinHeader_1x10_P2.54mm_Vertical" H 9950 1300 50 0001 C CNN +F 3 "https://www.ti.com/lit/pdf/slaa542" H 9950 1300 50 0001 C CNN + 1 9950 1300 + 1 0 0 -1 +$EndComp +$Comp +L power:VCC #PWR0102 +U 1 1 5080AA9F +P 1950 850 +F 0 "#PWR0102" H 1950 700 50 0001 C CNN +F 1 "VCC" H 1950 1000 50 0000 C CNN +F 2 "" H 1950 850 50 0001 C CNN +F 3 "" H 1950 850 50 0001 C CNN + 1 1950 850 + 1 0 0 -1 +$EndComp +$Comp +L Connector_Generic:Conn_01x03 J3 +U 1 1 5F13DC7C +P 10200 2150 +F 0 "J3" H 10280 2192 50 0000 L CNN +F 1 "Conn_01x03" H 10280 2101 50 0000 L CNN +F 2 "Connector_PinHeader_2.54mm:PinHeader_1x03_P2.54mm_Vertical" H 10200 2150 50 0001 C CNN +F 3 "~" H 10200 2150 50 0001 C CNN + 1 10200 2150 + 1 0 0 -1 +$EndComp +$Comp +L power:VCC #PWR0103 +U 1 1 5F13E225 +P 9700 2200 +F 0 "#PWR0103" H 9700 2050 50 0001 C CNN +F 1 "VCC" H 9700 2350 50 0000 C CNN +F 2 "" H 9700 2200 50 0001 C CNN +F 3 "" H 9700 2200 50 0001 C CNN + 1 9700 2200 + 1 0 0 -1 +$EndComp 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Launchpad XL

+

Expansion Board

+This project template is the basis of an expansion board for the +TI Launchpad +board. +

+This board conforms to the 20-Pin LaunchPad and BoosterPack Standard, using the maximum height. +

+The board outline looks like the following: +
+20 Pin Launchpad +
+(c)2012 Brian Sidebotham
+(c)2012 Henry von Tresckow
+(c)2012 Kicad Developers
+©2020 Neil McNeight
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24bc6fd..0000000 --- a/Projects/ti-stellaris-boosterpack40_min/boosterpack.lib +++ /dev/null @@ -1,114 +0,0 @@ -EESchema-LIBRARY Version 2.3 Date: Thu 18 Oct 2012 09:37:56 PM PDT -#encoding utf-8 -# -# Ti_Booster_40_J1 -# -DEF Ti_Booster_40_J1 J 0 40 Y Y 1 F N -F0 "J" -50 650 60 H V C CNN -F1 "Ti_Booster_40_J1" 0 -650 60 H V C CNN -DRAW -S -300 550 400 -550 0 1 0 N -X 1.01/Vcc 1 -600 450 300 R 50 50 1 1 W -X 1.02/PB5 2 -600 350 300 R 50 50 1 1 B -X 1.03/PB0/Rxd 3 -600 250 300 R 50 50 1 1 B -X 1.04/PB1/TxD 4 -600 150 300 R 50 50 1 1 B -X 1.05/PE4 5 -600 50 300 R 50 50 1 1 B -X 1.06/PE5 6 -600 -50 300 R 50 50 1 1 B -X 1.07/PB4 7 -600 -150 300 R 50 50 1 1 B -X 1.08/PA5 8 -600 -250 300 R 50 50 1 1 B -X 1.09/PA6 9 -600 -350 300 R 50 50 1 1 B -X 1.10/PA7 10 -600 -450 300 R 50 50 1 1 B -ENDDRAW -ENDDEF -# -# Ti_Booster_40_J2 -# -DEF Ti_Booster_40_J2 J 0 40 Y Y 1 F N -F0 "J" -50 650 60 H V C CNN -F1 "Ti_Booster_40_J2" 0 -650 60 H V C CNN -DRAW -S -300 550 400 -550 0 1 0 N -X 2.01/GND 1 -600 450 300 R 50 50 1 1 W -X 2.02/PB2 2 -600 350 300 R 50 50 1 1 B -X 2.03/PE0 3 -600 250 300 R 50 50 1 1 B -X 2.04/PF0 4 -600 150 300 R 50 50 1 1 B -X 2.05/RESET 5 -600 50 300 R 50 50 1 1 B -X 2.06/PB7 6 -600 -50 300 R 50 50 1 1 B -X 2.07/PB6 7 -600 -150 300 R 50 50 1 1 B -X 2.08/PA4 8 -600 -250 300 R 50 50 1 1 B -X 2.09/PA3 9 -600 -350 300 R 50 50 1 1 B -X 2.10/PA2 10 -600 -450 300 R 50 50 1 1 B -ENDDRAW -ENDDEF -# -# Ti_Booster_40_J3 -# -DEF Ti_Booster_40_J3 J 0 40 Y Y 1 F N -F0 "J" -50 650 60 H V C CNN -F1 "Ti_Booster_40_J3" 0 -650 60 H V C CNN -DRAW -S -300 550 400 -550 0 1 0 N -X 3.01/+5V 1 -600 450 300 R 50 50 1 1 W -X 3.02/GND 2 -600 350 300 R 50 50 1 1 B -X 3.03/PD0 3 -600 250 300 R 50 50 1 1 B -X 3.04/PD1 4 -600 150 300 R 50 50 1 1 B -X 3.05/PD2 5 -600 50 300 R 50 50 1 1 B -X 3.06/PD3 6 -600 -50 300 R 50 50 1 1 B -X 3.07/PE1 7 -600 -150 300 R 50 50 1 1 B -X 3.08/PE2 8 -600 -250 300 R 50 50 1 1 B -X 3.09/PE3 9 -600 -350 300 R 50 50 1 1 B -X 3.10/PF1 10 -600 -450 300 R 50 50 1 1 B -ENDDRAW -ENDDEF -# -# Ti_Booster_40_J4 -# -DEF Ti_Booster_40_J4 J 0 40 Y Y 1 F N -F0 "J" -50 650 60 H V C CNN -F1 "Ti_Booster_40_J4" 0 -650 60 H V C CNN -DRAW -S -300 550 400 -550 0 1 0 N -X 4.01/PF2 1 -600 450 300 R 50 50 1 1 W -X 4.02/PF3 2 -600 350 300 R 50 50 1 1 B -X 4.03/PB3 3 -600 250 300 R 50 50 1 1 B -X 4.04/PC4 4 -600 150 300 R 50 50 1 1 B -X 4.05/PC5 5 -600 50 300 R 50 50 1 1 B -X 4.06/PC6 6 -600 -50 300 R 50 50 1 1 B -X 4.07/PC7 7 -600 -150 300 R 50 50 1 1 B -X 4.08/PD6 8 -600 -250 300 R 50 50 1 1 B -X 4.09/PD7 9 -600 -350 300 R 50 50 1 1 B -X 4.10/PF4 10 -600 -450 300 R 50 50 1 1 B -ENDDRAW -ENDDEF -# -# Ti_Booster_J1 -# -DEF Ti_Booster_J1 J 0 40 Y Y 1 F N -F0 "J" -300 1300 60 H V C CNN -F1 "Ti_Booster_J1" -100 -1250 60 H V C CNN -DRAW -S -450 1200 500 -1150 0 1 0 N -X Vcc 1 -750 -950 300 R 50 50 1 1 W -X P1.0/LED1 2 -750 1100 300 R 50 50 1 1 B -X P1.1/Rxd 3 -750 1000 300 R 50 50 1 1 B -X P1.2/TxD 4 -750 900 300 R 50 50 1 1 B -X P1.3/S2 5 -750 800 300 R 50 50 1 1 B -X p1.4 6 -750 700 300 R 50 50 1 1 B -X P1.5 7 -750 600 300 R 50 50 1 1 B -X P2.0 8 -750 200 300 R 50 50 1 1 B -X P2.1 9 -750 100 300 R 50 50 1 1 B -X P2.2 10 -750 0 300 R 50 50 1 1 B -X Gnd 20 -750 -1050 300 R 50 50 1 1 B -X P2.3 11 -750 -100 300 R 50 50 1 1 B -X P2.4 12 -750 -200 300 R 50 50 1 1 B -X P2.5 13 -750 -300 300 R 50 50 1 1 B -X P1.6/Led2 14 -750 500 300 R 50 50 1 1 B -X P1.7 15 -750 400 300 R 50 50 1 1 B -X RST/S1 16 -750 -750 300 R 50 50 1 1 B -X Test 17 -750 -650 300 R 50 50 1 1 B -X P2.7/Xout 18 -750 -550 300 R 50 50 1 1 B -X P2.6/Xin 19 -750 -450 300 R 50 50 1 1 B -ENDDRAW -ENDDEF -# -#End Library diff --git a/Projects/ti-stellaris-boosterpack40_min/boosterpack40.dcm b/Projects/ti-stellaris-boosterpack40_min/boosterpack40.dcm new file mode 100644 index 0000000..00352b4 --- /dev/null +++ b/Projects/ti-stellaris-boosterpack40_min/boosterpack40.dcm @@ -0,0 +1,19 @@ +EESchema-DOCLIB Version 2.0 +# +$CMP Ti_Booster_40_J1 +F https://www.ti.com/lit/pdf/slaa542 +$ENDCMP +# +$CMP Ti_Booster_40_J2 +F https://www.ti.com/lit/pdf/slaa542 +$ENDCMP +# +$CMP Ti_Booster_40_J3 +F https://www.ti.com/lit/pdf/slaa542 +$ENDCMP +# +$CMP Ti_Booster_40_J4 +F https://www.ti.com/lit/pdf/slaa542 +$ENDCMP +# +#End Doc Library diff --git a/Projects/ti-stellaris-boosterpack40_min/boosterpack40.lib b/Projects/ti-stellaris-boosterpack40_min/boosterpack40.lib new file mode 100644 index 0000000..c380e8e --- /dev/null +++ b/Projects/ti-stellaris-boosterpack40_min/boosterpack40.lib @@ -0,0 +1,104 @@ +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# Ti_Booster_40_J1 +# +DEF Ti_Booster_40_J1 J1 0 40 Y Y 1 F N +F0 "J1" 0 650 50 H V C CNN +F1 "Ti_Booster_40_J1" 0 -650 50 H V C CNN +F2 "Connector_PinHeader_2.54mm:PinHeader_1x10_P2.54mm_Vertical" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + PinHeader*1x10*P2.54mm* +$ENDFPLIST +DRAW +S 300 550 -300 -550 0 1 10 f +X VCC 1 400 450 100 L 50 50 1 1 W +X GPIO2 10 400 -450 100 L 50 50 1 1 B +X Analog_In 2 400 350 100 L 50 50 1 1 B +X UART_RX 3 400 250 100 L 50 50 1 1 B +X UART_TX 4 400 150 100 L 50 50 1 1 B +X GPIO_IRQ0 5 400 50 100 L 50 50 1 1 B +X SCLK_A 6 400 -50 100 L 50 50 1 1 B +X SCLK_B 7 400 -150 100 L 50 50 1 1 B +X GPIO0 8 400 -250 100 L 50 50 1 1 B +X GPIO1 9 400 -350 100 L 50 50 1 1 B +ENDDRAW +ENDDEF +# +# Ti_Booster_40_J2 +# +DEF Ti_Booster_40_J2 J2 0 40 Y Y 1 F N +F0 "J2" 0 650 50 H V C CNN +F1 "Ti_Booster_40_J2" 0 -650 50 H V C CNN +F2 "Connector_PinHeader_2.54mm:PinHeader_1x10_P2.54mm_Vertical" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + PinHeader*1x10*P2.54mm* +$ENDFPLIST +DRAW +S -300 550 300 -550 0 1 10 f +X GND 1 -400 450 100 R 50 50 1 1 W +X GPIO3 10 -400 -450 100 R 50 50 1 1 B +X Timer_Out 2 -400 350 100 R 50 50 1 1 B +X GPIO_IRQ1 3 -400 250 100 R 50 50 1 1 B +X TEST 4 -400 150 100 R 50 50 1 1 B +X RESET 5 -400 50 100 R 50 50 1 1 B +X SIMO_B/SDA 6 -400 -50 100 R 50 50 1 1 B +X SOMI_B/SCL 7 -400 -150 100 R 50 50 1 1 B +X GPIO5 8 -400 -250 100 R 50 50 1 1 B +X GPIO4 9 -400 -350 100 R 50 50 1 1 B +ENDDRAW +ENDDEF +# +# Ti_Booster_40_J3 +# +DEF Ti_Booster_40_J3 J3 0 40 Y Y 1 F N +F0 "J3" 0 650 50 H V C CNN +F1 "Ti_Booster_40_J3" 0 -650 50 H V C CNN +F2 "Connector_PinHeader_2.54mm:PinHeader_1x10_P2.54mm_Vertical" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + PinHeader*1x10*P2.54mm* +$ENDFPLIST +DRAW +S 300 550 -300 -550 0 1 10 f +X +5V 1 400 450 100 L 50 50 1 1 W +X Analog7 10 400 -450 100 L 50 50 1 1 B +X GND 2 400 350 100 L 50 50 1 1 W +X Analog0 3 400 250 100 L 50 50 1 1 B +X Analog1 4 400 150 100 L 50 50 1 1 B +X Analog2 5 400 50 100 L 50 50 1 1 B +X Analog3 6 400 -50 100 L 50 50 1 1 B +X Analog4 7 400 -150 100 L 50 50 1 1 B +X Analog5 8 400 -250 100 L 50 50 1 1 B +X Analog6 9 400 -350 100 L 50 50 1 1 B +ENDDRAW +ENDDEF +# +# Ti_Booster_40_J4 +# +DEF Ti_Booster_40_J4 J4 0 40 Y Y 1 F N +F0 "J4" 0 650 50 H V C CNN +F1 "Ti_Booster_40_J4" 0 -650 50 H V C CNN +F2 "Connector_PinHeader_2.54mm:PinHeader_1x10_P2.54mm_Vertical" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + PinHeader*1x10*P2.54mm* +$ENDFPLIST +DRAW +S -300 550 300 -550 0 1 10 f +X Timer0 1 -400 450 100 R 50 50 1 1 B +X Timer9 10 -400 -450 100 R 50 50 1 1 B +X Timer1 2 -400 350 100 R 50 50 1 1 B +X Timer2 3 -400 250 100 R 50 50 1 1 B +X Timer3 4 -400 150 100 R 50 50 1 1 B +X Timer4 5 -400 50 100 R 50 50 1 1 B +X Timer5 6 -400 -50 100 R 50 50 1 1 B +X Timer6 7 -400 -150 100 R 50 50 1 1 B +X Timer7 8 -400 -250 100 R 50 50 1 1 B +X Timer8 9 -400 -350 100 R 50 50 1 1 B +ENDDRAW +ENDDEF +# +#End Library diff --git a/Projects/ti-stellaris-boosterpack40_min/boosterpack40_min.kicad_pcb b/Projects/ti-stellaris-boosterpack40_min/boosterpack40_min.kicad_pcb index a893cd4..6acd00a 100644 --- a/Projects/ti-stellaris-boosterpack40_min/boosterpack40_min.kicad_pcb +++ b/Projects/ti-stellaris-boosterpack40_min/boosterpack40_min.kicad_pcb @@ -1,12 +1,12 @@ -(kicad_pcb (version 20171130) (host pcbnew no-vcs-found-c6d0075~61~ubuntu16.04.1) +(kicad_pcb (version 20171130) (host pcbnew "(5.1.6)-1") (general (thickness 1.6) - (drawings 7) + (drawings 10) (tracks 0) (zones 0) - (modules 4) - (nets 40) + (modules 5) + (nets 3) ) (page A3) @@ -26,6 +26,9 @@ (42 Eco1.User user) (43 Eco2.User user) (44 Edge.Cuts user) + (45 Margin user) + (46 B.CrtYd user) + (47 F.CrtYd user) ) (setup @@ -34,8 +37,6 @@ (zone_clearance 0.508) (zone_45_only no) (trace_min 0.254) - (segment_width 0.20066) - (edge_width 0.14986) (via_size 0.889) (via_drill 0.635) (via_min_size 0.889) @@ -45,11 +46,13 @@ (uvias_allowed no) (uvia_min_size 0.508) (uvia_min_drill 0.127) - (pcb_text_width 0.3) - (pcb_text_size 1 1) + (edge_width 0.14986) + (segment_width 0.20066) + (pcb_text_width 0.254) + (pcb_text_size 1.27 1.27) (mod_edge_width 0.14986) - (mod_text_size 1 1) - (mod_text_width 0.15) + (mod_text_size 1.27 1.27) + (mod_text_width 0.254) (pad_size 1 1) (pad_drill 0.6) (pad_to_mask_clearance 0) @@ -69,7 +72,7 @@ (useauxorigin false) (hpglpennumber 1) (hpglpenspeed 20) - (hpglpendiameter 15) + (hpglpendiameter 15.000000) (psnegative false) (psa4output false) (plotreference true) @@ -87,43 +90,6 @@ (net 0 "") (net 1 GND) (net 2 VCC) - (net 3 "Net-(J1-Pad2)") - (net 4 "Net-(J1-Pad3)") - (net 5 "Net-(J1-Pad4)") - (net 6 "Net-(J1-Pad5)") - (net 7 "Net-(J1-Pad6)") - (net 8 "Net-(J1-Pad7)") - (net 9 "Net-(J1-Pad8)") - (net 10 "Net-(J1-Pad9)") - (net 11 "Net-(J1-Pad10)") - (net 12 "Net-(J2-Pad10)") - (net 13 "Net-(J2-Pad9)") - (net 14 "Net-(J2-Pad8)") - (net 15 "Net-(J2-Pad7)") - (net 16 "Net-(J2-Pad6)") - (net 17 "Net-(J2-Pad5)") - (net 18 "Net-(J2-Pad4)") - (net 19 "Net-(J2-Pad3)") - (net 20 "Net-(J2-Pad2)") - (net 21 +5V) - (net 22 "Net-(J3-Pad3)") - (net 23 "Net-(J3-Pad4)") - (net 24 "Net-(J3-Pad5)") - (net 25 "Net-(J3-Pad6)") - (net 26 "Net-(J3-Pad7)") - (net 27 "Net-(J3-Pad8)") - (net 28 "Net-(J3-Pad9)") - (net 29 "Net-(J3-Pad10)") - (net 30 "Net-(J4-Pad10)") - (net 31 "Net-(J4-Pad9)") - (net 32 "Net-(J4-Pad8)") - (net 33 "Net-(J4-Pad7)") - (net 34 "Net-(J4-Pad6)") - (net 35 "Net-(J4-Pad5)") - (net 36 "Net-(J4-Pad4)") - (net 37 "Net-(J4-Pad3)") - (net 38 "Net-(J4-Pad2)") - (net 39 "Net-(J4-Pad1)") (net_class Default "This is the default net class." (clearance 0.254) @@ -132,47 +98,54 @@ (via_drill 0.635) (uvia_dia 0.508) (uvia_drill 0.127) - (add_net +5V) + (diff_pair_width 0.254) + (diff_pair_gap 0.254) (add_net GND) - (add_net "Net-(J1-Pad10)") - (add_net "Net-(J1-Pad2)") - (add_net "Net-(J1-Pad3)") - (add_net "Net-(J1-Pad4)") - (add_net "Net-(J1-Pad5)") - (add_net "Net-(J1-Pad6)") - (add_net "Net-(J1-Pad7)") - (add_net "Net-(J1-Pad8)") - (add_net "Net-(J1-Pad9)") - (add_net "Net-(J2-Pad10)") - (add_net "Net-(J2-Pad2)") - (add_net "Net-(J2-Pad3)") - (add_net "Net-(J2-Pad4)") - (add_net "Net-(J2-Pad5)") - (add_net "Net-(J2-Pad6)") - (add_net "Net-(J2-Pad7)") - (add_net "Net-(J2-Pad8)") - (add_net "Net-(J2-Pad9)") - (add_net "Net-(J3-Pad10)") - (add_net "Net-(J3-Pad3)") - (add_net "Net-(J3-Pad4)") - (add_net "Net-(J3-Pad5)") - (add_net "Net-(J3-Pad6)") - (add_net "Net-(J3-Pad7)") - (add_net "Net-(J3-Pad8)") - (add_net "Net-(J3-Pad9)") - (add_net "Net-(J4-Pad1)") - (add_net "Net-(J4-Pad10)") - (add_net "Net-(J4-Pad2)") - (add_net "Net-(J4-Pad3)") - (add_net "Net-(J4-Pad4)") - (add_net "Net-(J4-Pad5)") - (add_net "Net-(J4-Pad6)") - (add_net "Net-(J4-Pad7)") - (add_net "Net-(J4-Pad8)") - (add_net "Net-(J4-Pad9)") (add_net VCC) ) + (module Connector_PinHeader_2.54mm:PinHeader_1x03_P2.54mm_Vertical (layer F.Cu) (tedit 59FED5CC) (tstamp 5F1461EA) + (at 231.14 149.86) + (descr "Through hole straight pin header, 1x03, 2.54mm pitch, single row") + (tags "Through hole pin header THT 1x03 2.54mm single row") + (path /5F1555B0) + (fp_text reference J5 (at 0 -2.33) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value Conn_01x03 (at 0 7.41) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text user %R (at 0 2.54 90) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1)) + (fp_line (start 1.27 -1.27) (end 1.27 6.35) (layer F.Fab) (width 0.1)) + (fp_line (start 1.27 6.35) (end -1.27 6.35) (layer F.Fab) (width 0.1)) + (fp_line (start -1.27 6.35) (end -1.27 -0.635) (layer F.Fab) (width 0.1)) + (fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1)) + (fp_line (start -1.33 6.41) (end 1.33 6.41) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.33 1.27) (end -1.33 6.41) (layer F.SilkS) (width 0.12)) + (fp_line (start 1.33 1.27) (end 1.33 6.41) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.8 -1.8) (end -1.8 6.85) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.8 6.85) (end 1.8 6.85) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.8 6.85) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05)) + (pad 3 thru_hole oval (at 0 5.08) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 2 VCC)) + (pad 2 thru_hole oval (at 0 2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 1 GND)) + (pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 1 GND)) + (model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x03_P2.54mm_Vertical.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + (module Connector_PinHeader_2.54mm:PinHeader_1x10_P2.54mm_Vertical (layer F.Cu) (tedit 59FED5CC) (tstamp 5A7B9D5E) (at 228.6 121.92) (descr "Through hole straight pin header, 1x10, 2.54mm pitch, single row") @@ -181,47 +154,37 @@ (fp_text reference J4 (at 0 -2.33) (layer F.SilkS) (effects (font (size 1 1) (thickness 0.15))) ) - (fp_text value TI_BOOSTER_40_J4 (at 0 25.19) (layer F.Fab) + (fp_text value Ti_Booster_40_J4 (at 0 25.19) (layer F.Fab) (effects (font (size 1 1) (thickness 0.15))) ) (fp_text user %R (at 0 11.43 90) (layer F.Fab) (effects (font (size 1 1) (thickness 0.15))) ) - (fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05)) - (fp_line (start 1.8 24.65) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05)) - (fp_line (start -1.8 24.65) (end 1.8 24.65) (layer F.CrtYd) (width 0.05)) - (fp_line (start -1.8 -1.8) (end -1.8 24.65) (layer F.CrtYd) (width 0.05)) - (fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12)) - (fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12)) - (fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12)) - (fp_line (start 1.33 1.27) (end 1.33 24.19) (layer F.SilkS) (width 0.12)) - (fp_line (start -1.33 1.27) (end -1.33 24.19) (layer F.SilkS) (width 0.12)) - (fp_line (start -1.33 24.19) (end 1.33 24.19) (layer F.SilkS) (width 0.12)) - (fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1)) - (fp_line (start -1.27 24.13) (end -1.27 -0.635) (layer F.Fab) (width 0.1)) - (fp_line (start 1.27 24.13) (end -1.27 24.13) (layer F.Fab) (width 0.1)) - (fp_line (start 1.27 -1.27) (end 1.27 24.13) (layer F.Fab) (width 0.1)) (fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1)) - (pad 10 thru_hole oval (at 0 22.86) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 30 "Net-(J4-Pad10)")) - (pad 9 thru_hole oval (at 0 20.32) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 31 "Net-(J4-Pad9)")) - (pad 8 thru_hole oval (at 0 17.78) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 32 "Net-(J4-Pad8)")) - (pad 7 thru_hole oval (at 0 15.24) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 33 "Net-(J4-Pad7)")) - (pad 6 thru_hole oval (at 0 12.7) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 34 "Net-(J4-Pad6)")) - (pad 5 thru_hole oval (at 0 10.16) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 35 "Net-(J4-Pad5)")) - (pad 4 thru_hole oval (at 0 7.62) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 36 "Net-(J4-Pad4)")) - (pad 3 thru_hole oval (at 0 5.08) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 37 "Net-(J4-Pad3)")) - (pad 2 thru_hole oval (at 0 2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 38 "Net-(J4-Pad2)")) - (pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 39 "Net-(J4-Pad1)")) + (fp_line (start 1.27 -1.27) (end 1.27 24.13) (layer F.Fab) (width 0.1)) + (fp_line (start 1.27 24.13) (end -1.27 24.13) (layer F.Fab) (width 0.1)) + (fp_line (start -1.27 24.13) (end -1.27 -0.635) (layer F.Fab) (width 0.1)) + (fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1)) + (fp_line (start -1.33 24.19) (end 1.33 24.19) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.33 1.27) (end -1.33 24.19) (layer F.SilkS) (width 0.12)) + (fp_line (start 1.33 1.27) (end 1.33 24.19) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.8 -1.8) (end -1.8 24.65) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.8 24.65) (end 1.8 24.65) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.8 24.65) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05)) + (pad 10 thru_hole oval (at 0 22.86) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) + (pad 9 thru_hole oval (at 0 20.32) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) + (pad 8 thru_hole oval (at 0 17.78) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) + (pad 7 thru_hole oval (at 0 15.24) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) + (pad 6 thru_hole oval (at 0 12.7) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) + (pad 5 thru_hole oval (at 0 10.16) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) + (pad 4 thru_hole oval (at 0 7.62) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) + (pad 3 thru_hole oval (at 0 5.08) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) + (pad 2 thru_hole oval (at 0 2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) + (pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) (model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x10_P2.54mm_Vertical.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) @@ -237,7 +200,10 @@ (fp_text reference J3 (at 0 -2.33) (layer F.SilkS) (effects (font (size 1 1) (thickness 0.15))) ) - (fp_text value TI_BOOSTER_40_J3 (at 0 25.19) (layer F.Fab) + (fp_text value Ti_Booster_40_J3 (at 0 25.19) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text user %R (at 0 11.43 90) (layer F.Fab) (effects (font (size 1 1) (thickness 0.15))) ) (fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1)) @@ -255,29 +221,17 @@ (fp_line (start -1.8 24.65) (end 1.8 24.65) (layer F.CrtYd) (width 0.05)) (fp_line (start 1.8 24.65) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05)) (fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05)) - (fp_text user %R (at 0 11.43 90) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) - ) - (pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 21 +5V)) + (pad 10 thru_hole oval (at 0 22.86) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) + (pad 9 thru_hole oval (at 0 20.32) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) + (pad 8 thru_hole oval (at 0 17.78) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) + (pad 7 thru_hole oval (at 0 15.24) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) + (pad 6 thru_hole oval (at 0 12.7) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) + (pad 5 thru_hole oval (at 0 10.16) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) + (pad 4 thru_hole oval (at 0 7.62) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) + (pad 3 thru_hole oval (at 0 5.08) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) (pad 2 thru_hole oval (at 0 2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) (net 1 GND)) - (pad 3 thru_hole oval (at 0 5.08) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 22 "Net-(J3-Pad3)")) - (pad 4 thru_hole oval (at 0 7.62) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 23 "Net-(J3-Pad4)")) - (pad 5 thru_hole oval (at 0 10.16) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 24 "Net-(J3-Pad5)")) - (pad 6 thru_hole oval (at 0 12.7) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 25 "Net-(J3-Pad6)")) - (pad 7 thru_hole oval (at 0 15.24) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 26 "Net-(J3-Pad7)")) - (pad 8 thru_hole oval (at 0 17.78) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 27 "Net-(J3-Pad8)")) - (pad 9 thru_hole oval (at 0 20.32) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 28 "Net-(J3-Pad9)")) - (pad 10 thru_hole oval (at 0 22.86) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 29 "Net-(J3-Pad10)")) + (pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) (model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x10_P2.54mm_Vertical.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) @@ -293,45 +247,36 @@ (fp_text reference J2 (at 0 -2.33) (layer F.SilkS) (effects (font (size 1 1) (thickness 0.15))) ) - (fp_text value TI_BOOSTER_40_J2 (at 0 25.19) (layer F.Fab) + (fp_text value Ti_Booster_40_J2 (at 0 25.19) (layer F.Fab) (effects (font (size 1 1) (thickness 0.15))) ) (fp_text user %R (at 0 11.43 90) (layer F.Fab) (effects (font (size 1 1) (thickness 0.15))) ) - (fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05)) - (fp_line (start 1.8 24.65) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05)) - (fp_line (start -1.8 24.65) (end 1.8 24.65) (layer F.CrtYd) (width 0.05)) - (fp_line (start -1.8 -1.8) (end -1.8 24.65) (layer F.CrtYd) (width 0.05)) - (fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12)) - (fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12)) - (fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12)) - (fp_line (start 1.33 1.27) (end 1.33 24.19) (layer F.SilkS) (width 0.12)) - (fp_line (start -1.33 1.27) (end -1.33 24.19) (layer F.SilkS) (width 0.12)) - (fp_line (start -1.33 24.19) (end 1.33 24.19) (layer F.SilkS) (width 0.12)) - (fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1)) - (fp_line (start -1.27 24.13) (end -1.27 -0.635) (layer F.Fab) (width 0.1)) - (fp_line (start 1.27 24.13) (end -1.27 24.13) (layer F.Fab) (width 0.1)) - (fp_line (start 1.27 -1.27) (end 1.27 24.13) (layer F.Fab) (width 0.1)) (fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1)) - (pad 10 thru_hole oval (at 0 22.86) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 12 "Net-(J2-Pad10)")) - (pad 9 thru_hole oval (at 0 20.32) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 13 "Net-(J2-Pad9)")) - (pad 8 thru_hole oval (at 0 17.78) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 14 "Net-(J2-Pad8)")) - (pad 7 thru_hole oval (at 0 15.24) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 15 "Net-(J2-Pad7)")) - (pad 6 thru_hole oval (at 0 12.7) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 16 "Net-(J2-Pad6)")) - (pad 5 thru_hole oval (at 0 10.16) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 17 "Net-(J2-Pad5)")) - (pad 4 thru_hole oval (at 0 7.62) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 18 "Net-(J2-Pad4)")) - (pad 3 thru_hole oval (at 0 5.08) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 19 "Net-(J2-Pad3)")) - (pad 2 thru_hole oval (at 0 2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 20 "Net-(J2-Pad2)")) + (fp_line (start 1.27 -1.27) (end 1.27 24.13) (layer F.Fab) (width 0.1)) + (fp_line (start 1.27 24.13) (end -1.27 24.13) (layer F.Fab) (width 0.1)) + (fp_line (start -1.27 24.13) (end -1.27 -0.635) (layer F.Fab) (width 0.1)) + (fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1)) + (fp_line (start -1.33 24.19) (end 1.33 24.19) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.33 1.27) (end -1.33 24.19) (layer F.SilkS) (width 0.12)) + (fp_line (start 1.33 1.27) (end 1.33 24.19) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.8 -1.8) (end -1.8 24.65) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.8 24.65) (end 1.8 24.65) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.8 24.65) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05)) + (pad 10 thru_hole oval (at 0 22.86) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) + (pad 9 thru_hole oval (at 0 20.32) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) + (pad 8 thru_hole oval (at 0 17.78) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) + (pad 7 thru_hole oval (at 0 15.24) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) + (pad 6 thru_hole oval (at 0 12.7) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) + (pad 5 thru_hole oval (at 0 10.16) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) + (pad 4 thru_hole oval (at 0 7.62) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) + (pad 3 thru_hole oval (at 0 5.08) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) + (pad 2 thru_hole oval (at 0 2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) (pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) (net 1 GND)) (model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x10_P2.54mm_Vertical.wrl @@ -349,7 +294,10 @@ (fp_text reference J1 (at 0 -2.33) (layer F.SilkS) (effects (font (size 1 1) (thickness 0.15))) ) - (fp_text value TI_BOOSTER_40_J1 (at 0 25.19) (layer F.Fab) + (fp_text value Ti_Booster_40_J1 (at 0 25.19) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text user %R (at 0 11.43 90) (layer F.Fab) (effects (font (size 1 1) (thickness 0.15))) ) (fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1)) @@ -367,29 +315,17 @@ (fp_line (start -1.8 24.65) (end 1.8 24.65) (layer F.CrtYd) (width 0.05)) (fp_line (start 1.8 24.65) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05)) (fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05)) - (fp_text user %R (at 0 11.43 90) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) - ) + (pad 10 thru_hole oval (at 0 22.86) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) + (pad 9 thru_hole oval (at 0 20.32) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) + (pad 8 thru_hole oval (at 0 17.78) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) + (pad 7 thru_hole oval (at 0 15.24) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) + (pad 6 thru_hole oval (at 0 12.7) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) + (pad 5 thru_hole oval (at 0 10.16) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) + (pad 4 thru_hole oval (at 0 7.62) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) + (pad 3 thru_hole oval (at 0 5.08) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) + (pad 2 thru_hole oval (at 0 2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)) (pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) (net 2 VCC)) - (pad 2 thru_hole oval (at 0 2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 3 "Net-(J1-Pad2)")) - (pad 3 thru_hole oval (at 0 5.08) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 4 "Net-(J1-Pad3)")) - (pad 4 thru_hole oval (at 0 7.62) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 5 "Net-(J1-Pad4)")) - (pad 5 thru_hole oval (at 0 10.16) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 6 "Net-(J1-Pad5)")) - (pad 6 thru_hole oval (at 0 12.7) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 7 "Net-(J1-Pad6)")) - (pad 7 thru_hole oval (at 0 15.24) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 8 "Net-(J1-Pad7)")) - (pad 8 thru_hole oval (at 0 17.78) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 9 "Net-(J1-Pad8)")) - (pad 9 thru_hole oval (at 0 20.32) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 10 "Net-(J1-Pad9)")) - (pad 10 thru_hole oval (at 0 22.86) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 11 "Net-(J1-Pad10)")) (model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x10_P2.54mm_Vertical.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) @@ -397,21 +333,46 @@ ) ) - (dimension 34.29 (width 0.25) (layer Dwgs.User) - (gr_text "1.3500 in" (at 176.800001 130.175 270) (layer Dwgs.User) - (effects (font (size 1 1) (thickness 0.25))) + (dimension 45.72 (width 0.254) (layer Dwgs.User) + (gr_text "1800 mils" (at 208.28 108.712) (layer Dwgs.User) + (effects (font (size 1.27 1.27) (thickness 0.254))) ) - (feature1 (pts (xy 182.88 147.32) (xy 175.800001 147.32))) - (feature2 (pts (xy 182.88 113.03) (xy 175.800001 113.03))) - (crossbar (pts (xy 177.800001 113.03) (xy 177.800001 147.32))) - (arrow1a (pts (xy 177.800001 147.32) (xy 177.213581 146.193497))) - (arrow1b (pts (xy 177.800001 147.32) (xy 178.386421 146.193497))) - (arrow2a (pts (xy 177.800001 113.03) (xy 177.213581 114.156503))) - (arrow2b (pts (xy 177.800001 113.03) (xy 178.386421 114.156503))) + (feature1 (pts (xy 185.42 121.92) (xy 185.42 109.903579))) + (feature2 (pts (xy 231.14 121.92) (xy 231.14 109.903579))) + (crossbar (pts (xy 231.14 110.49) (xy 185.42 110.49))) + (arrow1a (pts (xy 185.42 110.49) (xy 186.546504 109.903579))) + (arrow1b (pts (xy 185.42 110.49) (xy 186.546504 111.076421))) + (arrow2a (pts (xy 231.14 110.49) (xy 230.013496 109.903579))) + (arrow2b (pts (xy 231.14 110.49) (xy 230.013496 111.076421))) ) - (dimension 8.89 (width 0.25) (layer Dwgs.User) - (gr_text "0.3500 in" (at 238.49 117.475 90) (layer Dwgs.User) - (effects (font (size 1 1) (thickness 0.25))) + (gr_line (start 182.88 147.32) (end 233.68 147.32) (layer Dwgs.User) (width 0.254)) + (dimension 43.18 (width 0.254) (layer Dwgs.User) + (gr_text "1700 mils" (at 174.752 134.62 270) (layer Dwgs.User) + (effects (font (size 1.27 1.27) (thickness 0.254))) + ) + (feature1 (pts (xy 182.88 156.21) (xy 175.943579 156.21))) + (feature2 (pts (xy 182.88 113.03) (xy 175.943579 113.03))) + (crossbar (pts (xy 176.53 113.03) (xy 176.53 156.21))) + (arrow1a (pts (xy 176.53 156.21) (xy 175.943579 155.083496))) + (arrow1b (pts (xy 176.53 156.21) (xy 177.116421 155.083496))) + (arrow2a (pts (xy 176.53 113.03) (xy 175.943579 114.156504))) + (arrow2b (pts (xy 176.53 113.03) (xy 177.116421 114.156504))) + ) + (dimension 34.29 (width 0.254) (layer Dwgs.User) + (gr_text "1350 mils" (at 178.84 130.175 270) (layer Dwgs.User) + (effects (font (size 1.27 1.27) (thickness 0.254))) + ) + (feature1 (pts (xy 182.88 147.32) (xy 179.753579 147.32))) + (feature2 (pts (xy 182.88 113.03) (xy 179.753579 113.03))) + (crossbar (pts (xy 180.34 113.03) (xy 180.34 147.32))) + (arrow1a (pts (xy 180.34 147.32) (xy 179.753579 146.193496))) + (arrow1b (pts (xy 180.34 147.32) (xy 180.926421 146.193496))) + (arrow2a (pts (xy 180.34 113.03) (xy 179.753579 114.156504))) + (arrow2b (pts (xy 180.34 113.03) (xy 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120.444188) (xy 188.81 120.431928) (xy 187.11 120.431928) (xy 186.985518 120.444188) (xy 186.86582 120.480498) + (xy 186.755506 120.539463) (xy 186.69 120.593222) (xy 186.624494 120.539463) (xy 186.51418 120.480498) (xy 186.394482 120.444188) + (xy 186.27 120.431928) (xy 184.57 120.431928) (xy 184.445518 120.444188) (xy 184.32582 120.480498) (xy 184.215506 120.539463) + (xy 184.118815 120.618815) (xy 184.039463 120.715506) (xy 183.980498 120.82582) (xy 183.944188 120.945518) (xy 183.931928 121.07) + (xy 183.58993 121.07) (xy 183.58993 113.74) (xy 232.97007 113.74) + ) + ) + ) ) diff --git a/Projects/ti-stellaris-boosterpack40_min/boosterpack40_min.pro b/Projects/ti-stellaris-boosterpack40_min/boosterpack40_min.pro index cb5026e..f807c75 100644 --- a/Projects/ti-stellaris-boosterpack40_min/boosterpack40_min.pro +++ b/Projects/ti-stellaris-boosterpack40_min/boosterpack40_min.pro @@ -1,4 +1,4 @@ -update=Son 28 Jän 2018 00:34:00 CET +update=19/07/2020 09:58:10 version=1 last_client=kicad [cvpcb] @@ -6,38 +6,232 @@ version=1 NetIExt=net [cvpcb/libraries] EquName1=devcms -[pcbnew] -version=1 -LastNetListRead=boosterpack20.net -PadDrill=1.016 -PadSizeH=1.524 -PadSizeV=1.524 -PcbTextSizeV=1 -PcbTextSizeH=1 -PcbTextThickness=0.3 -ModuleTextSizeV=1 -ModuleTextSizeH=1 -ModuleTextSizeThickness=0.15 -SolderMaskClearance=0 -DrawSegmentWidth=0.2 -BoardOutlineThickness=0.15 -ModuleOutlineThickness=0.15 -[pcbnew/libraries] -LibDir= -LibName1=boosterpack20 -LibName2=sockets -LibName3=connect -LibName4=discret -LibName5=pin_array -LibName6=divers -LibName7=libcms -LibName8=display -LibName9=led -LibName10=dip_sockets -LibName11=pga_sockets -LibName12=valves [general] version=1 [eeschema] version=1 LibDir= +[pcbnew] +version=1 +PageLayoutDescrFile= +LastNetListRead=boosterpack20.net +CopperLayerCount=2 +BoardThickness=1.6 +AllowMicroVias=0 +AllowBlindVias=0 +RequireCourtyardDefinitions=0 +ProhibitOverlappingCourtyards=1 +MinTrackWidth=0.254 +MinViaDiameter=0.889 +MinViaDrill=0.508 +MinMicroViaDiameter=0.508 +MinMicroViaDrill=0.127 +MinHoleToHole=0.25 +TrackWidth1=0.254 +ViaDiameter1=0.889 +ViaDrill1=0.635 +dPairWidth1=0.254 +dPairGap1=0.254 +dPairViaGap1=0.25 +SilkLineWidth=0.14986 +SilkTextSizeV=1.27 +SilkTextSizeH=1.27 +SilkTextSizeThickness=0.254 +SilkTextItalic=0 +SilkTextUpright=1 +CopperLineWidth=0.20066 +CopperTextSizeV=1.27 +CopperTextSizeH=1.27 +CopperTextThickness=0.254 +CopperTextItalic=0 +CopperTextUpright=1 +EdgeCutLineWidth=0.14986 +CourtyardLineWidth=0.05 +OthersLineWidth=0.254 +OthersTextSizeV=1.27 +OthersTextSizeH=1.27 +OthersTextSizeThickness=0.254 +OthersTextItalic=0 +OthersTextUpright=1 +SolderMaskClearance=0 +SolderMaskMinWidth=0 +SolderPasteClearance=0 +SolderPasteRatio=-0 +[pcbnew/Layer.F.Cu] +Name=F.Cu +Type=0 +Enabled=1 +[pcbnew/Layer.In1.Cu] +Name=In1.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In2.Cu] +Name=In2.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In3.Cu] +Name=In3.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In4.Cu] +Name=In4.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In5.Cu] +Name=In5.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In6.Cu] +Name=In6.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In7.Cu] +Name=In7.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In8.Cu] +Name=In8.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In9.Cu] +Name=In9.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In10.Cu] +Name=In10.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In11.Cu] +Name=In11.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In12.Cu] +Name=In12.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In13.Cu] +Name=In13.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In14.Cu] +Name=In14.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In15.Cu] +Name=In15.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In16.Cu] +Name=In16.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In17.Cu] +Name=In17.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In18.Cu] +Name=In18.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In19.Cu] +Name=In19.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In20.Cu] +Name=In20.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In21.Cu] +Name=In21.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In22.Cu] +Name=In22.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In23.Cu] +Name=In23.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In24.Cu] +Name=In24.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In25.Cu] +Name=In25.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In26.Cu] +Name=In26.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In27.Cu] +Name=In27.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In28.Cu] +Name=In28.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In29.Cu] +Name=In29.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In30.Cu] +Name=In30.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.B.Cu] +Name=B.Cu +Type=0 +Enabled=1 +[pcbnew/Layer.B.Adhes] +Enabled=1 +[pcbnew/Layer.F.Adhes] +Enabled=1 +[pcbnew/Layer.B.Paste] +Enabled=1 +[pcbnew/Layer.F.Paste] +Enabled=1 +[pcbnew/Layer.B.SilkS] +Enabled=1 +[pcbnew/Layer.F.SilkS] +Enabled=1 +[pcbnew/Layer.B.Mask] +Enabled=1 +[pcbnew/Layer.F.Mask] +Enabled=1 +[pcbnew/Layer.Dwgs.User] +Enabled=1 +[pcbnew/Layer.Cmts.User] +Enabled=1 +[pcbnew/Layer.Eco1.User] +Enabled=1 +[pcbnew/Layer.Eco2.User] +Enabled=1 +[pcbnew/Layer.Edge.Cuts] +Enabled=1 +[pcbnew/Layer.Margin] +Enabled=1 +[pcbnew/Layer.B.CrtYd] +Enabled=1 +[pcbnew/Layer.F.CrtYd] +Enabled=1 +[pcbnew/Layer.B.Fab] +Enabled=0 +[pcbnew/Layer.F.Fab] +Enabled=0 +[pcbnew/Layer.Rescue] +Enabled=0 +[pcbnew/Netclasses] +[pcbnew/Netclasses/Default] +Name=Default +Clearance=0.254 +TrackWidth=0.254 +ViaDiameter=0.889 +ViaDrill=0.635 +uViaDiameter=0.508 +uViaDrill=0.127 +dPairWidth=0.254 +dPairGap=0.254 +dPairViaGap=0.25 diff --git a/Projects/ti-stellaris-boosterpack40_min/boosterpack40_min.sch b/Projects/ti-stellaris-boosterpack40_min/boosterpack40_min.sch index a41914b..35b36eb 100644 --- a/Projects/ti-stellaris-boosterpack40_min/boosterpack40_min.sch +++ b/Projects/ti-stellaris-boosterpack40_min/boosterpack40_min.sch @@ -1,12 +1,11 @@ EESchema Schematic File Version 4 -LIBS:boosterpack40_min-cache -EELAYER 26 0 +EELAYER 30 0 EELAYER END $Descr A4 11693 8268 encoding utf-8 Sheet 1 1 -Title "" -Date "19 oct 2012" +Title "40-Pin LaunchPad and BoosterPack Standard" +Date "2020-07-19" Rev "" Comp "" Comment1 "" @@ -15,91 +14,131 @@ Comment3 "" Comment4 "" $EndDescr $Comp -L power:GND #PWR01 +L power:GND #PWR0101 U 1 1 5080AA99 -P 9150 2300 -F 0 "#PWR01" H 9150 2050 50 0001 C CNN -F 1 "GND" H 9150 2150 50 0000 C CNN -F 2 "" H 9150 2300 50 0000 C CNN -F 3 "" H 9150 2300 50 0000 C CNN - 1 9150 2300 +P 9550 850 +F 0 "#PWR0101" H 9550 600 50 0001 C CNN +F 1 "GND" H 9550 700 50 0000 C CNN +F 2 "" H 9550 850 50 0001 C CNN +F 3 "" H 9550 850 50 0001 C CNN + 1 9550 850 0 1 1 0 $EndComp $Comp -L power:VCC #PWR02 +L power:VCC #PWR0102 U 1 1 5080AA9F -P 9150 750 -F 0 "#PWR02" H 9150 600 50 0001 C CNN -F 1 "VCC" H 9150 900 50 0000 C CNN -F 2 "" H 9150 750 50 0000 C CNN -F 3 "" H 9150 750 50 0000 C CNN - 1 9150 750 +P 1950 850 +F 0 "#PWR0102" H 1950 700 50 0001 C CNN +F 1 "VCC" H 1950 1000 50 0000 C CNN +F 2 "" H 1950 850 50 0001 C CNN +F 3 "" H 1950 850 50 0001 C CNN + 1 1950 850 1 0 0 -1 $EndComp $Comp -L boosterpack:Ti_Booster_40_J1 J1 +L boosterpack40:Ti_Booster_40_J1 J1 U 1 1 5080DB5C -P 9750 1200 -F 0 "J1" H 9700 1850 60 0000 C CNN -F 1 "TI_BOOSTER_40_J1" H 9750 550 60 0000 C CNN -F 2 "Connector_PinHeader_2.54mm:PinHeader_1x10_P2.54mm_Vertical" V 10200 1200 60 0001 C CNN -F 3 "" H 9750 1200 60 0001 C CNN - 1 9750 1200 +P 1550 1300 +F 0 "J1" H 1220 1346 50 0000 R CNN +F 1 "Ti_Booster_40_J1" H 1220 1255 50 0000 R CNN +F 2 "Connector_PinHeader_2.54mm:PinHeader_1x10_P2.54mm_Vertical" H 1550 1300 50 0001 C CNN +F 3 "https://www.ti.com/lit/pdf/slaa542" H 1550 1300 50 0001 C CNN + 1 1550 1300 1 0 0 -1 $EndComp $Comp -L boosterpack:Ti_Booster_40_J2 J2 +L boosterpack40:Ti_Booster_40_J2 J2 U 1 1 5080DBF4 -P 9750 2750 -F 0 "J2" H 9700 3400 60 0000 C CNN -F 1 "TI_BOOSTER_40_J2" H 9750 2100 60 0000 C CNN -F 2 "Connector_PinHeader_2.54mm:PinHeader_1x10_P2.54mm_Vertical" V 10200 2750 60 0001 C CNN -F 3 "" H 9750 2750 60 0001 C CNN - 1 9750 2750 +P 9950 1300 +F 0 "J2" H 10280 1346 50 0000 L CNN +F 1 "Ti_Booster_40_J2" H 10280 1255 50 0000 L CNN +F 2 "Connector_PinHeader_2.54mm:PinHeader_1x10_P2.54mm_Vertical" H 9950 1300 50 0001 C CNN +F 3 "https://www.ti.com/lit/pdf/slaa542" H 9950 1300 50 0001 C CNN + 1 9950 1300 1 0 0 -1 $EndComp $Comp -L boosterpack:Ti_Booster_40_J3 J3 +L boosterpack40:Ti_Booster_40_J3 J3 U 1 1 5080DC03 -P 9750 4300 -F 0 "J3" H 9700 4950 60 0000 C CNN -F 1 "TI_BOOSTER_40_J3" H 9750 3650 60 0000 C CNN -F 2 "Connector_PinHeader_2.54mm:PinHeader_1x10_P2.54mm_Vertical" V 10200 4300 60 0001 C CNN -F 3 "" H 9750 4300 60 0001 C CNN - 1 9750 4300 +P 1550 2800 +F 0 "J3" H 1220 2846 50 0000 R CNN +F 1 "Ti_Booster_40_J3" H 1220 2755 50 0000 R CNN +F 2 "Connector_PinHeader_2.54mm:PinHeader_1x10_P2.54mm_Vertical" H 1550 2800 50 0001 C CNN +F 3 "https://www.ti.com/lit/pdf/slaa542" H 1550 2800 50 0001 C CNN + 1 1550 2800 1 0 0 -1 $EndComp $Comp -L boosterpack:Ti_Booster_40_J4 J4 +L boosterpack40:Ti_Booster_40_J4 J4 U 1 1 5080DC12 -P 9750 5850 -F 0 "J4" H 9700 6500 60 0000 C CNN -F 1 "TI_BOOSTER_40_J4" H 9750 5200 60 0000 C CNN -F 2 "Connector_PinHeader_2.54mm:PinHeader_1x10_P2.54mm_Vertical" V 10200 5850 60 0001 C CNN -F 3 "" H 9750 5850 60 0001 C CNN - 1 9750 5850 +P 9950 2800 +F 0 "J4" H 10280 2846 50 0000 L CNN +F 1 "Ti_Booster_40_J4" H 10280 2755 50 0000 L CNN +F 2 "Connector_PinHeader_2.54mm:PinHeader_1x10_P2.54mm_Vertical" H 9950 2800 50 0001 C CNN +F 3 "https://www.ti.com/lit/pdf/slaa542" H 9950 2800 50 0001 C CNN + 1 9950 2800 1 0 0 -1 $EndComp $Comp -L power:GND #PWR03 +L power:GND #PWR0103 U 1 1 5080DC79 -P 9150 3950 -F 0 "#PWR03" H 9150 3700 50 0001 C CNN -F 1 "GND" H 9150 3800 50 0000 C CNN -F 2 "" H 9150 3950 50 0000 C CNN -F 3 "" H 9150 3950 50 0000 C CNN - 1 9150 3950 - 0 1 1 0 +P 1950 2450 +F 0 "#PWR0103" H 1950 2200 50 0001 C CNN +F 1 "GND" H 1950 2300 50 0000 C CNN +F 2 "" H 1950 2450 50 0001 C CNN +F 3 "" H 1950 2450 50 0001 C CNN + 1 1950 2450 + 0 -1 -1 0 $EndComp $Comp -L power:+5V #PWR04 +L power:+5V #PWR0104 U 1 1 5080DC8B -P 9150 3850 -F 0 "#PWR04" H 9150 3700 50 0001 C CNN -F 1 "+5V" H 9150 3990 50 0000 C CNN -F 2 "" H 9150 3850 50 0000 C CNN -F 3 "" H 9150 3850 50 0000 C CNN - 1 9150 3850 +P 1950 2350 +F 0 "#PWR0104" H 1950 2200 50 0001 C CNN +F 1 "+5V" H 1950 2490 50 0000 C CNN +F 2 "" H 1950 2350 50 0001 C CNN +F 3 "" H 1950 2350 50 0001 C CNN + 1 1950 2350 + 1 0 0 -1 +$EndComp +$Comp +L Connector_Generic:Conn_01x03 J5 +U 1 1 5F1555B0 +P 10200 3650 +F 0 "J5" H 10280 3692 50 0000 L CNN +F 1 "Conn_01x03" H 10280 3601 50 0000 L CNN +F 2 "Connector_PinHeader_2.54mm:PinHeader_1x03_P2.54mm_Vertical" H 10200 3650 50 0001 C CNN +F 3 "~" H 10200 3650 50 0001 C CNN + 1 10200 3650 + 1 0 0 -1 +$EndComp +$Comp +L power:GND #PWR0105 +U 1 1 5F156102 +P 10000 3550 +F 0 "#PWR0105" H 10000 3300 50 0001 C CNN +F 1 "GND" H 10000 3400 50 0000 C CNN +F 2 "" H 10000 3550 50 0001 C CNN +F 3 "" H 10000 3550 50 0001 C CNN + 1 10000 3550 + 0 1 1 0 +$EndComp +Wire Wire Line + 10000 3650 10000 3550 +Connection ~ 10000 3550 +$Comp +L power:VCC #PWR0106 +U 1 1 5F1568A4 +P 9700 3700 +F 0 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    Launchpad XL

    @@ -9,7 +9,7 @@

    Expansion Board

    TI Launchpad board.

    -This Board conforms to the 40 pin Launchpad Standard, using the minimum size. +This board conforms to the 40-Pin LaunchPad and BoosterPack Standard, using the maximum height.

    The board outline looks like the following:
    @@ -18,5 +18,6 @@

    Expansion Board

    (c)2012 Brian Sidebotham
    (c)2012 Henry von Tresckow
    (c)2012 Kicad Developers
    +©2020 Neil McNeight