From f8f4f901eb3cd9616d1efe50a2d44d3a2807426c Mon Sep 17 00:00:00 2001 From: Aba Date: Sat, 18 Nov 2023 16:25:12 -0800 Subject: [PATCH] Reorganize tcl files --- deepsocflow/asic/constraints/dnn_engine.sdc | 6 ------ deepsocflow/asic/constraints/proc_engine_out.sdc | 6 ------ deepsocflow/py/hardware.py | 2 +- deepsocflow/{asic/scripts => tcl/asic}/clock.tcl | 0 .../{asic/scripts => tcl/asic}/initialFloorplan.tcl | 0 .../{asic/scripts => tcl/asic}/loadDesignTech.tcl | 0 deepsocflow/{asic/scripts => tcl/asic}/outputGen.tcl | 0 deepsocflow/{asic/scripts => tcl/asic}/pinPlacement.tcl | 0 deepsocflow/{asic/scripts => tcl/asic}/placement.tcl | 0 deepsocflow/{asic/scripts => tcl/asic}/pnr.tcl | 0 deepsocflow/{asic/scripts => tcl/asic}/reportDesign.tcl | 0 deepsocflow/{asic/scripts => tcl/asic}/route.tcl | 0 deepsocflow/{asic/scripts => tcl/asic}/run_dc.tcl | 0 deepsocflow/{asic/scripts => tcl/asic}/run_genus.tcl | 9 ++++++--- deepsocflow/{asic/scripts => tcl/asic}/view.tcl | 0 deepsocflow/{fpga/scripts => tcl/fpga}/pynq_z2.tcl | 0 deepsocflow/{fpga/scripts => tcl/fpga}/vivado.tcl | 0 deepsocflow/{fpga/scripts => tcl/fpga}/zcu104.tcl | 0 18 files changed, 7 insertions(+), 16 deletions(-) delete mode 100644 deepsocflow/asic/constraints/dnn_engine.sdc delete mode 100644 deepsocflow/asic/constraints/proc_engine_out.sdc rename deepsocflow/{asic/scripts => tcl/asic}/clock.tcl (100%) rename deepsocflow/{asic/scripts => tcl/asic}/initialFloorplan.tcl (100%) rename deepsocflow/{asic/scripts => tcl/asic}/loadDesignTech.tcl (100%) rename deepsocflow/{asic/scripts => tcl/asic}/outputGen.tcl (100%) rename deepsocflow/{asic/scripts => tcl/asic}/pinPlacement.tcl (100%) rename deepsocflow/{asic/scripts => tcl/asic}/placement.tcl (100%) rename deepsocflow/{asic/scripts => tcl/asic}/pnr.tcl (100%) rename deepsocflow/{asic/scripts => tcl/asic}/reportDesign.tcl (100%) rename deepsocflow/{asic/scripts => tcl/asic}/route.tcl (100%) rename deepsocflow/{asic/scripts => tcl/asic}/run_dc.tcl (100%) rename deepsocflow/{asic/scripts => tcl/asic}/run_genus.tcl (82%) rename deepsocflow/{asic/scripts => tcl/asic}/view.tcl (100%) rename deepsocflow/{fpga/scripts => tcl/fpga}/pynq_z2.tcl (100%) rename deepsocflow/{fpga/scripts => tcl/fpga}/vivado.tcl (100%) rename deepsocflow/{fpga/scripts => tcl/fpga}/zcu104.tcl (100%) diff --git a/deepsocflow/asic/constraints/dnn_engine.sdc b/deepsocflow/asic/constraints/dnn_engine.sdc deleted file mode 100644 index e666e99..0000000 --- a/deepsocflow/asic/constraints/dnn_engine.sdc +++ /dev/null @@ -1,6 +0,0 @@ -create_clock -name aclk -period $clock_cycle [get_ports aclk] -set_false_path -from [get_ports "aresetn"] - -set_input_delay -clock [get_clocks aclk] -add_delay -max $io_delay [all_inputs] -set_output_delay -clock [get_clocks aclk] -add_delay -max $io_delay [all_outputs] - \ No newline at end of file diff --git a/deepsocflow/asic/constraints/proc_engine_out.sdc b/deepsocflow/asic/constraints/proc_engine_out.sdc deleted file mode 100644 index 757d9a2..0000000 --- a/deepsocflow/asic/constraints/proc_engine_out.sdc +++ /dev/null @@ -1,6 +0,0 @@ -create_clock -name clk -period $clock_cycle [get_ports aclk] -set_false_path -from [get_ports "aresetn"] - -set_input_delay -clock [get_clocks clk] -add_delay -max $io_delay [all_inputs] -set_output_delay -clock [get_clocks clk] -add_delay -max $io_delay [all_outputs] - diff --git a/deepsocflow/py/hardware.py b/deepsocflow/py/hardware.py index 1400fcc..a1c0c36 100644 --- a/deepsocflow/py/hardware.py +++ b/deepsocflow/py/hardware.py @@ -220,7 +220,7 @@ def export_vivado_tcl(self, board='zcu104', rtl_dir_abspath=None, scripts_dir_ab if rtl_dir_abspath is None: rtl_dir_abspath = self.MODULE_DIR + '/rtl' if scripts_dir_abspath is None: - scripts_dir_abspath = self.MODULE_DIR + '/fpga/scripts' + scripts_dir_abspath = self.MODULE_DIR + '/tcl/fpga' if board_tcl_abspath is None: board_tcl_abspath = f'{scripts_dir_abspath}/{board}.tcl' diff --git a/deepsocflow/asic/scripts/clock.tcl b/deepsocflow/tcl/asic/clock.tcl similarity index 100% rename from deepsocflow/asic/scripts/clock.tcl rename to deepsocflow/tcl/asic/clock.tcl diff --git a/deepsocflow/asic/scripts/initialFloorplan.tcl b/deepsocflow/tcl/asic/initialFloorplan.tcl similarity index 100% rename from deepsocflow/asic/scripts/initialFloorplan.tcl rename to deepsocflow/tcl/asic/initialFloorplan.tcl diff --git a/deepsocflow/asic/scripts/loadDesignTech.tcl b/deepsocflow/tcl/asic/loadDesignTech.tcl similarity index 100% rename from deepsocflow/asic/scripts/loadDesignTech.tcl rename to deepsocflow/tcl/asic/loadDesignTech.tcl diff --git a/deepsocflow/asic/scripts/outputGen.tcl b/deepsocflow/tcl/asic/outputGen.tcl similarity index 100% rename from deepsocflow/asic/scripts/outputGen.tcl rename to deepsocflow/tcl/asic/outputGen.tcl diff --git a/deepsocflow/asic/scripts/pinPlacement.tcl b/deepsocflow/tcl/asic/pinPlacement.tcl similarity index 100% rename from deepsocflow/asic/scripts/pinPlacement.tcl rename to deepsocflow/tcl/asic/pinPlacement.tcl diff --git a/deepsocflow/asic/scripts/placement.tcl b/deepsocflow/tcl/asic/placement.tcl similarity index 100% rename from deepsocflow/asic/scripts/placement.tcl rename to deepsocflow/tcl/asic/placement.tcl diff --git a/deepsocflow/asic/scripts/pnr.tcl b/deepsocflow/tcl/asic/pnr.tcl similarity index 100% rename from deepsocflow/asic/scripts/pnr.tcl rename to deepsocflow/tcl/asic/pnr.tcl diff --git a/deepsocflow/asic/scripts/reportDesign.tcl b/deepsocflow/tcl/asic/reportDesign.tcl similarity index 100% rename from deepsocflow/asic/scripts/reportDesign.tcl rename to deepsocflow/tcl/asic/reportDesign.tcl diff --git a/deepsocflow/asic/scripts/route.tcl b/deepsocflow/tcl/asic/route.tcl similarity index 100% rename from deepsocflow/asic/scripts/route.tcl rename to deepsocflow/tcl/asic/route.tcl diff --git a/deepsocflow/asic/scripts/run_dc.tcl b/deepsocflow/tcl/asic/run_dc.tcl similarity index 100% rename from deepsocflow/asic/scripts/run_dc.tcl rename to deepsocflow/tcl/asic/run_dc.tcl diff --git a/deepsocflow/asic/scripts/run_genus.tcl b/deepsocflow/tcl/asic/run_genus.tcl similarity index 82% rename from deepsocflow/asic/scripts/run_genus.tcl rename to deepsocflow/tcl/asic/run_genus.tcl index 975a7b3..f680929 100755 --- a/deepsocflow/asic/scripts/run_genus.tcl +++ b/deepsocflow/tcl/asic/run_genus.tcl @@ -1,6 +1,6 @@ set TOP proc_engine_out -set FREQ_MHZ 1000 -set clock_cycle [expr 1000/$FREQ_MHZ] +set FREQ 1000 +set clock_cycle [expr 1000/$FREQ] set io_delay [expr $clock_cycle/5] #--------- CONFIG @@ -28,7 +28,10 @@ check_design > ${REPORT_DIR}/check_design.rpt uniquify $TOP #--------- CONSTRAINTS -read_sdc ../constraints/$TOP.sdc +create_clock -name aclk -period $clock_cycle [get_ports aclk] +set_false_path -from [get_ports "aresetn"] +set_input_delay -clock [get_clocks aclk] -add_delay -max $io_delay [all_inputs] +set_output_delay -clock [get_clocks aclk] -add_delay -max $io_delay [all_outputs] #--------- RETIME OPTIONS set_db retime_async_reset true diff --git a/deepsocflow/asic/scripts/view.tcl b/deepsocflow/tcl/asic/view.tcl similarity index 100% rename from deepsocflow/asic/scripts/view.tcl rename to deepsocflow/tcl/asic/view.tcl diff --git a/deepsocflow/fpga/scripts/pynq_z2.tcl b/deepsocflow/tcl/fpga/pynq_z2.tcl similarity index 100% rename from deepsocflow/fpga/scripts/pynq_z2.tcl rename to deepsocflow/tcl/fpga/pynq_z2.tcl diff --git a/deepsocflow/fpga/scripts/vivado.tcl b/deepsocflow/tcl/fpga/vivado.tcl similarity index 100% rename from deepsocflow/fpga/scripts/vivado.tcl rename to deepsocflow/tcl/fpga/vivado.tcl diff --git a/deepsocflow/fpga/scripts/zcu104.tcl b/deepsocflow/tcl/fpga/zcu104.tcl similarity index 100% rename from deepsocflow/fpga/scripts/zcu104.tcl rename to deepsocflow/tcl/fpga/zcu104.tcl