diff --git a/deepsocflow/rtl/proc_engine.sv b/deepsocflow/rtl/proc_engine.sv
index 830a2de..03c5b21 100644
--- a/deepsocflow/rtl/proc_engine.sv
+++ b/deepsocflow/rtl/proc_engine.sv
@@ -67,9 +67,8 @@ module proc_engine #(
 
   logic [COLS-1:0] en_outshift, sel_outshift, outshift_flag;
   logic shift_out_ready_last_col_prev;
-  logic [BITS_COLS-1:0] count_outshift;
-  logic cnt_en;
-
+  logic [BITS_COLS-1:0] cnt_outshift, cnt_acc;
+  logic cnt_outshift_valid, cnt_acc_valid;
   logic [COLS-1:0] s_axis_tvalid;
 
   genvar k2, c_1;
@@ -322,9 +321,63 @@ endgenerate
     assign m_last_pkt = shift_last_pkt [COLS-1];
 
     // -------------- OUTPUT SHIFTER ----------------      
+    //logic [BITS_COLS-1:0] highest_acc, lowest_outshift;
+    //logic cnt_acc_valid_next, cnt_outshift_valid_next;
+    // integer a, b;
+    // always_comb begin // priority encoder - used to find highest acc.
+    //   highest_acc = 0;
+    //   cnt_acc_valid_next = 0;
+    //   for (a = 0; a < COLS-1; a++) begin
+    //     if(acc_m_valid_next[a] == 1) begin
+    //       highest_acc = a;
+    //       cnt_acc_valid_next = 1;
+    //       break;
+    //     end
+    //   end
+    // end
+
+    // always_comb begin //TODO priority encoder - used to find lowest outshift.
+    //   lowest_outshift = 0;
+    //   cnt_outshift_valid_next = 0;
+    //   for (b = 0; b < COLS-1; b++) begin
+    //     if(~shift_out_ready[b]) begin
+    //       lowest_outshift = b;
+    //       cnt_outshift_valid_next = 1;
+    //       break;
+    //     end
+    //   end
+    // end
+    
+    always@(posedge clk `OR_NEGEDGE(resetn))begin
+      if(!resetn) begin
+        {cnt_acc_valid, cnt_outshift_valid, cnt_acc, cnt_outshift} <= 0;
+      end
+      else begin
+        if(en[0] && acc_m_valid_next[0]) cnt_acc_valid <= 1;
+        else if (shift_out_ready[COLS-1] && acc_m_valid[COLS-1]) cnt_acc_valid <= 0; // reset condition
+        
+        if (cnt_acc_valid && en[0]) begin 
+          if (cnt_acc==COLS-1) cnt_acc <=  0;
+          else cnt_acc <= cnt_acc + 1;
+        end
+
+        // cnt_acc_valid <= cnt_acc_valid_next;
+        // cnt_acc <= highest_acc;
 
-    //assign en_mac = &(~acc_m_valid | shift_out_ready);
-    //assign en[0] = ~acc_m_valid[0] | shift_out_ready[0];
+        // cnt_outshift_valid <= cnt_outshift_valid_next;
+        // cnt_outshift <= lowest_outshift;
+        if(~sel_outshift[0]) cnt_outshift_valid <= 1;
+        
+        if (m_ready & outshift_flag[COLS-1]) begin 
+          if (cnt_outshift==COLS-1) cnt_outshift <= 0;
+          else cnt_outshift <= cnt_outshift + 1;
+        end
+      end
+    end
+
+    wire freeze;
+    assign freeze = ((cnt_outshift <= cnt_acc) && cnt_acc_valid && cnt_outshift_valid);
+    
     for(c=0; c<COLS; c++) begin : C
       if(c<COLS-1) begin
         // If current column and next column output shifter regs both have valid data, and accumulator has valid data column gets frozen 
@@ -340,7 +393,7 @@ endgenerate
           end
       end
       else begin // Final Column
-        assign mac_freeze[c] = (acc_m_valid[c] & ~shift_out_ready[c]);
+        //assign mac_freeze[c] = (acc_m_valid[c] & ~shift_out_ready[c]);
         //assign en[c] = (~acc_m_valid[c] | shift_out_ready[c]);
         always_ff @(posedge clk `OR_NEGEDGE(resetn))
           if (!resetn) begin            
@@ -353,8 +406,8 @@ endgenerate
       end
 
       //assign en[c] = &(~mac_freeze);
-      assign en[c] = &(~mac_freeze[COLS-1:c]);  // all cols to the left of frozen column should freeze.
-
+      //assign en[c] = &(~mac_freeze[COLS-1:c]);  // all cols to the left of frozen column should freeze.
+      assign en[c] = ~(freeze && (c <= cnt_acc));
       assign acc_m_valid_next[c] = !sel_shift[c] & mul_m_valid[c] & (mul_m_user[c].is_config | mul_m_user[c].is_cin_last);
 
       always_ff @(posedge clk `OR_NEGEDGE(resetn))
diff --git a/deepsocflow/tcl/fpga/zcu104.tcl b/deepsocflow/tcl/fpga/zcu104.tcl
index 3e6f386..70fd09f 100644
--- a/deepsocflow/tcl/fpga/zcu104.tcl
+++ b/deepsocflow/tcl/fpga/zcu104.tcl
@@ -5,7 +5,7 @@ create_project ${PROJECT_NAME} ${PROJECT_NAME} -part xczu7ev-ffvc1156-2-e -force
 set_property board_part xilinx.com:zcu104:part0:1.1 [current_project]
 
 create_bd_design "design_1"
-create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.4 zynq_ultra_ps_e_0
+create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.5 zynq_ultra_ps_e_0
 apply_bd_automation -rule xilinx.com:bd_rule:zynq_ultra_ps_e -config {apply_board_preset "1" }  [get_bd_cells zynq_ultra_ps_e_0]
 set_property -dict [list CONFIG.PSU__USE__M_AXI_GP1 {1} CONFIG.PSU__USE__S_AXI_GP0 {1} CONFIG.PSU__USE__S_AXI_GP1 {1} CONFIG.PSU__USE__S_AXI_GP2 {1} CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ $FREQ CONFIG.PSU__USE__M_AXI_GP0 {0} CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {0} CONFIG.PSU__SAXIGP0__DATA_WIDTH $AXI_WIDTH CONFIG.PSU__SAXIGP1__DATA_WIDTH $AXI_WIDTH CONFIG.PSU__SAXIGP2__DATA_WIDTH $AXI_WIDTH] [get_bd_cells zynq_ultra_ps_e_0]
 
diff --git a/run/param_test.py b/run/param_test.py
index daea4e3..d0a3cac 100644
--- a/run/param_test.py
+++ b/run/param_test.py
@@ -11,12 +11,12 @@
 from keras.utils import to_categorical
 from qkeras.utils import load_qmodel
 import numpy as np
-# import tensorflow as tf
-#tf.keras.utils.set_random_seed(0)
+import tensorflow as tf
+tf.keras.utils.set_random_seed(0)
 
 from deepsocflow import *
 
-(SIM, SIM_PATH) = ('xsim', "F:/Xilinx/Vivado/2022.2/bin/") if os.name=='nt' else ('verilator', '')
+(SIM, SIM_PATH) = ('xsim', "E:/Vivado/2023.2/bin/") if os.name=='nt' else ('verilator', '')
 
 '''
 Dataset
@@ -175,24 +175,24 @@ def product_dict(**kwargs):
         yield dict(zip(kwargs.keys(), instance))
 
 @pytest.mark.parametrize("PARAMS", list(product_dict(
-                                        processing_elements  = [(8,24)   ],
+                                        processing_elements  = [(32,64)   ],
                                         frequency_mhz        = [ 250     ],
                                         bits_input           = [ 4       ],
                                         bits_weights         = [ 4       ],
-                                        bits_sum             = [ 32      ],
+                                        bits_sum             = [ 20      ],
                                         bits_bias            = [ 16      ],
                                         max_batch_size       = [ 64      ], 
                                         max_channels_in      = [ 2048    ],
                                         max_kernel_size      = [ 9       ],
                                         max_image_size       = [ 512     ],
                                         max_n_bundles        = [ 64      ],
-                                        ram_weights_depth    = [ 20      ],
+                                        ram_weights_depth    = [ 512      ],
                                         ram_edges_depth      = [ 288     ],
-                                        axi_width            = [ 128      ],
+                                        axi_width            = [ 64      ],
                                         config_baseaddr      = ["B0000000"],
                                         target_cpu_int_bits  = [ 32       ],
-                                        valid_prob           = [ 0.1       ],
-                                        ready_prob           = [ 0.01       ],
+                                        valid_prob           = [ 1       ],
+                                        ready_prob           = [ 1       ],
                                         data_dir             = ['vectors'],
                                     )))
 def test_dnn_engine(PARAMS):
diff --git a/run/work/config_fw.h b/run/work/config_fw.h
index a7545ad..37df8d3 100644
--- a/run/work/config_fw.h
+++ b/run/work/config_fw.h
@@ -1,35 +1,35 @@
 #define N_BUNDLES 7
 Bundle_t bundles [N_BUNDLES] = {
-   {.n=1  , .l=4  , .kw=7  , .coe=3  , .h=28 , .w=28 , .ci=1   , .co=8   , .w_kw2=25 , .t=3  , .p=1  , .cm=2  , .cm_p0=1  , .on=1  , .oh=7  , .ow=10 , .oc=8   , .ch=14 , .ph=7  , .cw=28 , .pw=10 , .xp_words=1344  , .b_offset=0    , .w_bpt=84   , .w_bpt_p0=84   , .x_bpt=672     , .x_bpt_p0=672     , .o_words=640     , .o_bytes=320     , .ib_out=1   , .in_buffer_idx=-1 , .out_buffer_idx=0  , .add_out_buffer_idx=0 , .add_in_buffer_idx=-1, .is_bias=1  , .is_flatten=0  , .is_softmax=0  , .x_pad=4  , .b_val_shift=9  , .b_bias_shift=0  , .ca_nzero=0  , .ca_shift=12 , .ca_pl_scale=0  , .aa_nzero=0  , .aa_shift=0  , .aa_pl_scale=0  , .pa_nzero=1  , .pa_shift=0  , .pa_pl_scale=0  , .softmax_frac=0  , .csh=2  , .csh_shift=1  , .pkh=3  , .psh=2  , .psh_shift=0  , .csw=1  , .csw_shift=0  , .pkw=4  , .psw=3  , .psw_shift=1  , .pool=POOL_AVG  , .softmax_max_f=0              , .header=      29695610579857627u, .debug_nhwc_words=560       },
-   {.n=1  , .l=1  , .kw=1  , .coe=24 , .h=7  , .w=10 , .ci=8   , .co=8   , .w_kw2=10 , .t=1  , .p=1  , .cm=20 , .cm_p0=8  , .on=1  , .oh=7  , .ow=10 , .oc=8   , .ch=7  , .ph=7  , .cw=10 , .pw=10 , .xp_words=80    , .b_offset=9    , .w_bpt=96   , .w_bpt_p0=96   , .x_bpt=320     , .x_bpt_p0=320     , .o_words=960     , .o_bytes=480     , .ib_out=2   , .in_buffer_idx=0  , .out_buffer_idx=1  , .add_out_buffer_idx=1 , .add_in_buffer_idx=0 , .is_bias=1  , .is_flatten=0  , .is_softmax=0  , .x_pad=0  , .b_val_shift=9  , .b_bias_shift=0  , .ca_nzero=1  , .ca_shift=12 , .ca_pl_scale=0  , .aa_nzero=1  , .aa_shift=3  , .aa_pl_scale=3  , .pa_nzero=0  , .pa_shift=0  , .pa_pl_scale=0  , .softmax_frac=0  , .csh=1  , .csh_shift=0  , .pkh=1  , .psh=1  , .psh_shift=0  , .csw=1  , .csw_shift=0  , .pkw=1  , .psw=1  , .psw_shift=0  , .pool=POOL_NONE , .softmax_max_f=0              , .header=      43276787871645768u, .debug_nhwc_words=560       },
-   {.n=1  , .l=1  , .kw=7  , .coe=3  , .h=7  , .w=10 , .ci=8   , .co=8   , .w_kw2=7  , .t=3  , .p=4  , .cm=2  , .cm_p0=2  , .on=1  , .oh=7  , .ow=10 , .oc=8   , .ch=7  , .ph=7  , .cw=10 , .pw=10 , .xp_words=120   , .b_offset=33   , .w_bpt=168  , .w_bpt_p0=168  , .x_bpt=120     , .x_bpt_p0=120     , .o_words=960     , .o_bytes=480     , .ib_out=3   , .in_buffer_idx=1  , .out_buffer_idx=0  , .add_out_buffer_idx=-1, .add_in_buffer_idx=1 , .is_bias=1  , .is_flatten=0  , .is_softmax=0  , .x_pad=4  , .b_val_shift=9  , .b_bias_shift=0  , .ca_nzero=1  , .ca_shift=12 , .ca_pl_scale=0  , .aa_nzero=0  , .aa_shift=0  , .aa_pl_scale=0  , .pa_nzero=0  , .pa_shift=0  , .pa_pl_scale=0  , .softmax_frac=0  , .csh=1  , .csh_shift=0  , .pkh=1  , .psh=1  , .psh_shift=0  , .csw=1  , .csw_shift=0  , .pkw=1  , .psw=1  , .psw_shift=0  , .pool=POOL_NONE , .softmax_max_f=0              , .header=      30188191789350987u, .debug_nhwc_words=560       },
-   {.n=1  , .l=1  , .kw=5  , .coe=4  , .h=7  , .w=10 , .ci=8   , .co=8   , .w_kw2=8  , .t=2  , .p=2  , .cm=4  , .cm_p0=4  , .on=1  , .oh=7  , .ow=10 , .oc=8   , .ch=7  , .ph=7  , .cw=10 , .pw=10 , .xp_words=120   , .b_offset=42   , .w_bpt=240  , .w_bpt_p0=240  , .x_bpt=240     , .x_bpt_p0=240     , .o_words=960     , .o_bytes=480     , .ib_out=4   , .in_buffer_idx=0  , .out_buffer_idx=1  , .add_out_buffer_idx=-1, .add_in_buffer_idx=0 , .is_bias=1  , .is_flatten=0  , .is_softmax=0  , .x_pad=4  , .b_val_shift=9  , .b_bias_shift=0  , .ca_nzero=1  , .ca_shift=12 , .ca_pl_scale=0  , .aa_nzero=0  , .aa_shift=0  , .aa_pl_scale=0  , .pa_nzero=0  , .pa_shift=0  , .pa_pl_scale=0  , .softmax_frac=0  , .csh=1  , .csh_shift=0  , .pkh=1  , .psh=1  , .psh_shift=0  , .csw=1  , .csw_shift=0  , .pkw=1  , .psw=1  , .psw_shift=0  , .pool=POOL_NONE , .softmax_max_f=0              , .header=      44121204210794570u, .debug_nhwc_words=560       },
-   {.n=1  , .l=1  , .kw=3  , .coe=8  , .h=7  , .w=10 , .ci=8   , .co=24  , .w_kw2=9  , .t=3  , .p=2  , .cm=6  , .cm_p0=2  , .on=1  , .oh=7  , .ow=10 , .oc=24  , .ch=7  , .ph=7  , .cw=10 , .pw=10 , .xp_words=120   , .b_offset=50   , .w_bpt=216  , .w_bpt_p0=72   , .x_bpt=360     , .x_bpt_p0=120     , .o_words=1920    , .o_bytes=960     , .ib_out=5   , .in_buffer_idx=1  , .out_buffer_idx=0  , .add_out_buffer_idx=-1, .add_in_buffer_idx=-1, .is_bias=1  , .is_flatten=0  , .is_softmax=0  , .x_pad=4  , .b_val_shift=9  , .b_bias_shift=0  , .ca_nzero=0  , .ca_shift=12 , .ca_pl_scale=0  , .aa_nzero=0  , .aa_shift=0  , .aa_pl_scale=0  , .pa_nzero=0  , .pa_shift=0  , .pa_pl_scale=0  , .softmax_frac=0  , .csh=1  , .csh_shift=0  , .pkh=1  , .psh=1  , .psh_shift=0  , .csw=1  , .csw_shift=0  , .pkw=1  , .psw=1  , .psw_shift=0  , .pool=POOL_NONE , .softmax_max_f=0              , .header=      38632443238154313u, .debug_nhwc_words=1680      },
-   {.n=1  , .l=1  , .kw=1  , .coe=24 , .h=7  , .w=10 , .ci=24  , .co=10  , .w_kw2=10 , .t=1  , .p=2  , .cm=20 , .cm_p0=4  , .on=1  , .oh=1  , .ow=1  , .oc=700 , .ch=7  , .ph=7  , .cw=10 , .pw=10 , .xp_words=80    , .b_offset=74   , .w_bpt=240  , .w_bpt_p0=48   , .x_bpt=800     , .x_bpt_p0=160     , .o_words=5600    , .o_bytes=2800    , .ib_out=6   , .in_buffer_idx=0  , .out_buffer_idx=1  , .add_out_buffer_idx=-1, .add_in_buffer_idx=-1, .is_bias=1  , .is_flatten=1  , .is_softmax=0  , .x_pad=0  , .b_val_shift=9  , .b_bias_shift=0  , .ca_nzero=0  , .ca_shift=12 , .ca_pl_scale=0  , .aa_nzero=0  , .aa_shift=0  , .aa_pl_scale=0  , .pa_nzero=0  , .pa_shift=0  , .pa_pl_scale=0  , .softmax_frac=0  , .csh=1  , .csh_shift=0  , .pkh=1  , .psh=1  , .psh_shift=0  , .csw=1  , .csw_shift=0  , .pkw=1  , .psw=1  , .psw_shift=0  , .pool=POOL_NONE , .softmax_max_f=0              , .header=      42995312893886536u, .debug_nhwc_words=700       },
-   {.n=1  , .l=1  , .kw=1  , .coe=24 , .h=1  , .w=1  , .ci=700 , .co=10  , .w_kw2=1  , .t=1  , .p=35 , .cm=20 , .cm_p0=20 , .on=1  , .oh=1  , .ow=1  , .oc=10  , .ch=1  , .ph=1  , .cw=1  , .pw=1  , .xp_words=8     , .b_offset=98   , .w_bpt=240  , .w_bpt_p0=240  , .x_bpt=80      , .x_bpt_p0=80      , .o_words=10      , .o_bytes=40      , .ib_out=-1  , .in_buffer_idx=1  , .out_buffer_idx=-1 , .add_out_buffer_idx=-1, .add_in_buffer_idx=-1, .is_bias=0  , .is_flatten=0  , .is_softmax=1  , .x_pad=0  , .b_val_shift=0  , .b_bias_shift=0  , .ca_nzero=1  , .ca_shift=3  , .ca_pl_scale=0  , .aa_nzero=0  , .aa_shift=0  , .aa_pl_scale=0  , .pa_nzero=0  , .pa_shift=0  , .pa_pl_scale=0  , .softmax_frac=3  , .csh=1  , .csh_shift=0  , .pkh=1  , .psh=1  , .psh_shift=0  , .csw=1  , .csw_shift=0  , .pkw=1  , .psw=1  , .psw_shift=0  , .pool=POOL_NONE , .softmax_max_f=0.875          , .header=      44121212804923392u, .debug_nhwc_words=10        }
+   {.n=1  , .l=1  , .kw=7  , .coe=9  , .h=28 , .w=28 , .ci=1   , .co=8   , .w_kw2=25 , .t=1  , .p=1  , .cm=73 , .cm_p0=1  , .on=1  , .oh=7  , .ow=10 , .oc=8   , .ch=14 , .ph=7  , .cw=28 , .pw=10 , .xp_words=1008  , .b_offset=0    , .w_bpt=224  , .w_bpt_p0=224  , .x_bpt=504     , .x_bpt_p0=504     , .o_words=2560    , .o_bytes=1280    , .ib_out=1   , .in_buffer_idx=-1 , .out_buffer_idx=0  , .add_out_buffer_idx=0 , .add_in_buffer_idx=-1, .is_bias=1  , .is_flatten=0  , .is_softmax=0  , .x_pad=4  , .b_val_shift=9  , .b_bias_shift=0  , .ca_nzero=0  , .ca_shift=12 , .ca_pl_scale=0  , .aa_nzero=0  , .aa_shift=0  , .aa_pl_scale=0  , .pa_nzero=1  , .pa_shift=0  , .pa_pl_scale=0  , .softmax_frac=0  , .csh=2  , .csh_shift=1  , .pkh=3  , .psh=2  , .psh_shift=0  , .csw=1  , .csw_shift=0  , .pkw=4  , .psw=3  , .psw_shift=1  , .pool=POOL_AVG  , .softmax_max_f=0              , .header=    4593777182697849051u, .debug_nhwc_words=560       },
+   {.n=1  , .l=1  , .kw=1  , .coe=64 , .h=7  , .w=10 , .ci=8   , .co=8   , .w_kw2=10 , .t=1  , .p=1  , .cm=512, .cm_p0=8  , .on=1  , .oh=7  , .ow=10 , .oc=8   , .ch=7  , .ph=7  , .cw=10 , .pw=10 , .xp_words=320   , .b_offset=9    , .w_bpt=256  , .w_bpt_p0=256  , .x_bpt=1280    , .x_bpt_p0=1280    , .o_words=2880    , .o_bytes=1440    , .ib_out=2   , .in_buffer_idx=0  , .out_buffer_idx=1  , .add_out_buffer_idx=1 , .add_in_buffer_idx=0 , .is_bias=1  , .is_flatten=0  , .is_softmax=0  , .x_pad=0  , .b_val_shift=9  , .b_bias_shift=0  , .ca_nzero=1  , .ca_shift=12 , .ca_pl_scale=0  , .aa_nzero=1  , .aa_shift=3  , .aa_pl_scale=3  , .pa_nzero=0  , .pa_shift=0  , .pa_pl_scale=0  , .softmax_frac=0  , .csh=1  , .csh_shift=0  , .pkh=1  , .psh=1  , .psh_shift=0  , .csw=1  , .csw_shift=0  , .pkw=1  , .psw=1  , .psw_shift=0  , .pool=POOL_NONE , .softmax_max_f=0              , .header=    4602802033060675656u, .debug_nhwc_words=560       },
+   {.n=1  , .l=1  , .kw=7  , .coe=9  , .h=7  , .w=10 , .ci=8   , .co=8   , .w_kw2=7  , .t=1  , .p=1  , .cm=73 , .cm_p0=8  , .on=1  , .oh=7  , .ow=10 , .oc=8   , .ch=7  , .ph=7  , .cw=10 , .pw=10 , .xp_words=360   , .b_offset=73   , .w_bpt=1792 , .w_bpt_p0=1792 , .x_bpt=1440    , .x_bpt_p0=1440    , .o_words=2880    , .o_bytes=1440    , .ib_out=3   , .in_buffer_idx=1  , .out_buffer_idx=0  , .add_out_buffer_idx=-1, .add_in_buffer_idx=1 , .is_bias=1  , .is_flatten=0  , .is_softmax=0  , .x_pad=4  , .b_val_shift=9  , .b_bias_shift=0  , .ca_nzero=1  , .ca_shift=12 , .ca_pl_scale=0  , .aa_nzero=0  , .aa_shift=0  , .aa_pl_scale=0  , .pa_nzero=0  , .pa_shift=0  , .pa_pl_scale=0  , .softmax_frac=0  , .csh=1  , .csh_shift=0  , .pkh=1  , .psh=1  , .psh_shift=0  , .csw=1  , .csw_shift=0  , .pkw=1  , .psw=1  , .psw_shift=0  , .pool=POOL_NONE , .softmax_max_f=0              , .header=    4594639199814484043u, .debug_nhwc_words=560       },
+   {.n=1  , .l=1  , .kw=5  , .coe=12 , .h=7  , .w=10 , .ci=8   , .co=8   , .w_kw2=8  , .t=1  , .p=1  , .cm=102, .cm_p0=8  , .on=1  , .oh=7  , .ow=10 , .oc=8   , .ch=7  , .ph=7  , .cw=10 , .pw=10 , .xp_words=360   , .b_offset=82   , .w_bpt=1280 , .w_bpt_p0=1280 , .x_bpt=1440    , .x_bpt_p0=1440    , .o_words=2880    , .o_bytes=1440    , .ib_out=4   , .in_buffer_idx=0  , .out_buffer_idx=1  , .add_out_buffer_idx=-1, .add_in_buffer_idx=0 , .is_bias=1  , .is_flatten=0  , .is_softmax=0  , .x_pad=4  , .b_val_shift=9  , .b_bias_shift=0  , .ca_nzero=1  , .ca_shift=12 , .ca_pl_scale=0  , .aa_nzero=0  , .aa_shift=0  , .aa_pl_scale=0  , .pa_nzero=0  , .pa_shift=0  , .pa_pl_scale=0  , .softmax_frac=0  , .csh=1  , .csh_shift=0  , .pkh=1  , .psh=1  , .psh_shift=0  , .csw=1  , .csw_shift=0  , .pkw=1  , .psw=1  , .psw_shift=0  , .pool=POOL_NONE , .softmax_max_f=0              , .header=    4585350529475346506u, .debug_nhwc_words=560       },
+   {.n=1  , .l=1  , .kw=3  , .coe=21 , .h=7  , .w=10 , .ci=8   , .co=24  , .w_kw2=9  , .t=2  , .p=1  , .cm=170, .cm_p0=8  , .on=1  , .oh=7  , .ow=10 , .oc=24  , .ch=7  , .ph=7  , .cw=10 , .pw=10 , .xp_words=360   , .b_offset=94   , .w_bpt=768  , .w_bpt_p0=768  , .x_bpt=1440    , .x_bpt_p0=1440    , .o_words=7680    , .o_bytes=3840    , .ib_out=5   , .in_buffer_idx=1  , .out_buffer_idx=0  , .add_out_buffer_idx=-1, .add_in_buffer_idx=-1, .is_bias=1  , .is_flatten=0  , .is_softmax=0  , .x_pad=4  , .b_val_shift=9  , .b_bias_shift=0  , .ca_nzero=0  , .ca_shift=12 , .ca_pl_scale=0  , .aa_nzero=0  , .aa_shift=0  , .aa_pl_scale=0  , .pa_nzero=0  , .pa_shift=0  , .pa_pl_scale=0  , .softmax_frac=0  , .csh=1  , .csh_shift=0  , .pkh=1  , .psh=1  , .psh_shift=0  , .csw=1  , .csw_shift=0  , .pkw=1  , .psw=1  , .psw_shift=0  , .pool=POOL_NONE , .softmax_max_f=0              , .header=    4585069063625441353u, .debug_nhwc_words=1680      },
+   {.n=1  , .l=1  , .kw=1  , .coe=64 , .h=7  , .w=10 , .ci=24  , .co=10  , .w_kw2=10 , .t=1  , .p=1  , .cm=512, .cm_p0=24 , .on=1  , .oh=1  , .ow=1  , .oc=700 , .ch=7  , .ph=7  , .cw=10 , .pw=10 , .xp_words=320   , .b_offset=136  , .w_bpt=768  , .w_bpt_p0=768  , .x_bpt=3840    , .x_bpt_p0=3840    , .o_words=22400   , .o_bytes=11200   , .ib_out=6   , .in_buffer_idx=0  , .out_buffer_idx=1  , .add_out_buffer_idx=-1, .add_in_buffer_idx=-1, .is_bias=1  , .is_flatten=1  , .is_softmax=0  , .x_pad=0  , .b_val_shift=9  , .b_bias_shift=0  , .ca_nzero=0  , .ca_shift=12 , .ca_pl_scale=0  , .aa_nzero=0  , .aa_shift=0  , .aa_pl_scale=0  , .pa_nzero=0  , .pa_shift=0  , .pa_pl_scale=0  , .softmax_frac=0  , .csh=1  , .csh_shift=0  , .pkh=1  , .psh=1  , .psh_shift=0  , .csw=1  , .csw_shift=0  , .pkw=1  , .psw=1  , .psw_shift=0  , .pool=POOL_NONE , .softmax_max_f=0              , .header=    4603083508038434888u, .debug_nhwc_words=700       },
+   {.n=1  , .l=1  , .kw=1  , .coe=64 , .h=1  , .w=1  , .ci=700 , .co=10  , .w_kw2=1  , .t=1  , .p=2  , .cm=512, .cm_p0=188, .on=1  , .oh=1  , .ow=1  , .oc=10  , .ch=1  , .ph=1  , .cw=1  , .pw=1  , .xp_words=32    , .b_offset=200  , .w_bpt=16384, .w_bpt_p0=6016 , .x_bpt=8192    , .x_bpt_p0=3008    , .o_words=10      , .o_bytes=40      , .ib_out=-1  , .in_buffer_idx=1  , .out_buffer_idx=-1 , .add_out_buffer_idx=-1, .add_in_buffer_idx=-1, .is_bias=0  , .is_flatten=0  , .is_softmax=1  , .x_pad=0  , .b_val_shift=0  , .b_bias_shift=0  , .ca_nzero=1  , .ca_shift=3  , .ca_pl_scale=0  , .aa_nzero=0  , .aa_shift=0  , .aa_pl_scale=0  , .pa_nzero=0  , .pa_shift=0  , .pa_pl_scale=0  , .softmax_frac=3  , .csh=1  , .csh_shift=0  , .pkh=1  , .psh=1  , .psh_shift=0  , .csw=1  , .csw_shift=0  , .pkw=1  , .psw=1  , .psw_shift=0  , .pool=POOL_NONE , .softmax_max_f=0.375          , .header=    4605968626560466944u, .debug_nhwc_words=10        }
 };
 
 #define X_BITS_L2   2
 #define W_BITS_L2   2
 #define KH_MAX      9
-#define PE_ROWS     8
-#define PE_COLS     24
+#define PE_ROWS     32
+#define PE_COLS     64
 
 #define N_OUT_BUF   2
 #define N_ADD_BUF   2
-#define WB_BYTES    13072
-#define W_BYTES     12876
-#define X_BYTES     672
+#define WB_BYTES    28656
+#define W_BYTES     28256
+#define X_BYTES     504
 #define O_WORDS     10
-#define O_WORDS_MAX 5600
-#define O_BYTES_MAX 2800
-#define X_BYTES_ALL 6192
+#define O_WORDS_MAX 22400
+#define O_BYTES_MAX 11200
+#define X_BYTES_ALL 21144
 #define NHWC_WORDS  6272
 #define Y_TYPE      int32_t
 #define B_TYPE      int16_t
 #define O_TYPE      float
-#define B_WORDS     98
-#define AXI_WIDTH   128
+#define B_WORDS     200
+#define AXI_WIDTH   64
 #define CONFIG_BASEADDR 0xB0000000
 #define DATA_DIR   "../vectors"
 
diff --git a/run/work/config_hw.svh b/run/work/config_hw.svh
index 34720a7..af54837 100644
--- a/run/work/config_hw.svh
+++ b/run/work/config_hw.svh
@@ -3,11 +3,11 @@
                     
 `define OR_NEGEDGE(RSTN)    or negedge RSTN
 
-`define ROWS                8           // PE rows, constrained by resources
-`define COLS                24          // PE cols, constrained by resources
+`define ROWS                32          // PE rows, constrained by resources
+`define COLS                64          // PE cols, constrained by resources
 `define X_BITS              4           // Bits per word in input
 `define K_BITS              4           // Bits per word in input
-`define Y_BITS              32          // Bits per word in output of conv
+`define Y_BITS              20          // Bits per word in output of conv
 `define Y_OUT_BITS          32          // Padded bits per word in output of conv
 
 `define KH_MAX              9           // max of kernel height, across layers
@@ -18,14 +18,14 @@
 `define CI_MAX              2048        // max of input channels, across layers
 `define MAX_N_BUNDLES       64          // max number of bundles in a network
 `define CONFIG_BEATS        0           // constant, for now
-`define RAM_WEIGHTS_DEPTH   20          // CONFIG_BEATS + max(KW * CI), across layers
+`define RAM_WEIGHTS_DEPTH   512         // CONFIG_BEATS + max(KW * CI), across layers
 `define RAM_EDGES_DEPTH     288         // max (KW * CI * XW), across layers when KW != 1
 `define W_BPT               32          // Width of output integer denoting bytes per transfer
 
 `define DELAY_MUL           3            // constant, for now 
 `define DELAY_W_RAM         2            // constant, for now 
 
-`define AXI_WIDTH           128       
+`define AXI_WIDTH           64        
 `define HEADER_WIDTH        64        
 `define AXI_MAX_BURST_LEN   16        
 `define CONFIG_BASEADDR     40'hB0000000  
diff --git a/run/work/config_hw.tcl b/run/work/config_hw.tcl
index c056000..08bcdf2 100644
--- a/run/work/config_hw.tcl
+++ b/run/work/config_hw.tcl
@@ -2,14 +2,14 @@
 # Written from Hardware.export()
 
 set FREQ               250
-set ROWS               8
-set COLS               24
+set ROWS               32
+set COLS               64
 set X_BITS             4
 set K_BITS             4
-set Y_BITS             32
+set Y_BITS             20
 set DELAY_W_RAM        2
-set RAM_WEIGHTS_DEPTH  20
+set RAM_WEIGHTS_DEPTH  512
 set RAM_EDGES_DEPTH    288
 set KH_MAX             9
-set AXI_WIDTH          128
+set AXI_WIDTH          64
 set CONFIG_BASEADDR    0xB0000000
diff --git a/run/work/config_tb.svh b/run/work/config_tb.svh
index 32b9724..d4cf904 100644
--- a/run/work/config_tb.svh
+++ b/run/work/config_tb.svh
@@ -1,6 +1,6 @@
 
-`define VALID_PROB 100 
-`define READY_PROB 10 
+`define VALID_PROB 1000 
+`define READY_PROB 1000 
 `define CLK_PERIOD 4.0 
 `define INPUT_DELAY_NS  0.8ns
 `define OUTPUT_DELAY_NS 0.8ns
diff --git a/run/work/hardware.json b/run/work/hardware.json
index 7ac1789..b682c92 100644
--- a/run/work/hardware.json
+++ b/run/work/hardware.json
@@ -1,27 +1,27 @@
 {
     "processing_elements": [
-        8,
-        24
+        32,
+        64
     ],
     "frequency_mhz": 250,
     "bits_input": 4,
     "bits_weights": 4,
-    "bits_sum": 32,
+    "bits_sum": 20,
     "bits_bias": 16,
     "max_batch_size": 64,
     "max_channels_in": 2048,
     "max_kernel_size": 9,
     "max_image_size": 512,
     "max_n_bundles": 64,
-    "ram_weights_depth": 20,
+    "ram_weights_depth": 512,
     "ram_edges_depth": 288,
-    "axi_width": 128,
+    "axi_width": 64,
     "header_width": 64,
     "config_baseaddr": "B0000000",
     "axi_max_burst_len": 16,
     "target_cpu_int_bits": 32,
     "async_resetn": true,
-    "valid_prob": 0.1,
-    "ready_prob": 0.01,
+    "valid_prob": 1,
+    "ready_prob": 1,
     "data_dir": "vectors"
 }
\ No newline at end of file
diff --git a/run/work/sources.txt b/run/work/sources.txt
index f33bd61..a73b835 100644
--- a/run/work/sources.txt
+++ b/run/work/sources.txt
@@ -1,29 +1,29 @@
-/mnt/d/dnn-engine/deepsocflow/test/sv/axi_sys_tb.sv
-/mnt/d/dnn-engine/deepsocflow/test/sv/cgra4ml_axi2ram_tb.sv
-/mnt/d/dnn-engine/deepsocflow/test/sv/ext/axi_addr.v
-/mnt/d/dnn-engine/deepsocflow/test/sv/ext/skidbuffer.v
-/mnt/d/dnn-engine/deepsocflow/test/sv/ext/zipcpu_axi2ram.v
-/mnt/d/dnn-engine/deepsocflow/rtl/axi_cgra4ml.v
-/mnt/d/dnn-engine/deepsocflow/rtl/dnn_engine.v
-/mnt/d/dnn-engine/deepsocflow/rtl/ext/alex_axis_pipeline_register.v
-/mnt/d/dnn-engine/deepsocflow/rtl/ext/alex_axis_register.v
-/mnt/d/dnn-engine/deepsocflow/rtl/ext/xilinx_spwf.v
-/mnt/d/dnn-engine/deepsocflow/rtl/axis_out_shift.sv
-/mnt/d/dnn-engine/deepsocflow/rtl/axis_pixels.sv
-/mnt/d/dnn-engine/deepsocflow/rtl/axis_weight_rotator.sv
-/mnt/d/dnn-engine/deepsocflow/rtl/counter.sv
-/mnt/d/dnn-engine/deepsocflow/rtl/cyclic_bram.sv
-/mnt/d/dnn-engine/deepsocflow/rtl/dma_controller.sv
-/mnt/d/dnn-engine/deepsocflow/rtl/n_delay.sv
-/mnt/d/dnn-engine/deepsocflow/rtl/proc_engine.sv
-/mnt/d/dnn-engine/deepsocflow/rtl/ram.sv
-/mnt/d/dnn-engine/deepsocflow/rtl/ext/alex_axilite_ram.sv
-/mnt/d/dnn-engine/deepsocflow/rtl/ext/alex_axilite_rd.sv
-/mnt/d/dnn-engine/deepsocflow/rtl/ext/alex_axilite_wr.sv
-/mnt/d/dnn-engine/deepsocflow/rtl/ext/alex_axis_adapter.sv
-/mnt/d/dnn-engine/deepsocflow/rtl/ext/alex_axis_adapter_any.sv
-/mnt/d/dnn-engine/deepsocflow/rtl/ext/alex_axi_dma_rd.sv
-/mnt/d/dnn-engine/deepsocflow/rtl/ext/alex_axi_dma_wr.sv
-/mnt/d/dnn-engine/deepsocflow/rtl/ext/xilinx_sdp.sv
-/mnt/d/dnn-engine/run/work/config_hw.svh
-/mnt/d/dnn-engine/run/work/config_tb.svh
\ No newline at end of file
+E:\SU24\cgra4ml\deepsocflow\test\sv\axi_sys_tb.sv
+E:\SU24\cgra4ml\deepsocflow\test\sv\cgra4ml_axi2ram_tb.sv
+E:\SU24\cgra4ml\deepsocflow\test\sv\ext\axi_addr.v
+E:\SU24\cgra4ml\deepsocflow\test\sv\ext\skidbuffer.v
+E:\SU24\cgra4ml\deepsocflow\test\sv\ext\zipcpu_axi2ram.v
+E:\SU24\cgra4ml\deepsocflow\rtl\axi_cgra4ml.v
+E:\SU24\cgra4ml\deepsocflow\rtl\dnn_engine.v
+E:\SU24\cgra4ml\deepsocflow\rtl\ext\alex_axis_pipeline_register.v
+E:\SU24\cgra4ml\deepsocflow\rtl\ext\alex_axis_register.v
+E:\SU24\cgra4ml\deepsocflow\rtl\ext\xilinx_spwf.v
+E:\SU24\cgra4ml\deepsocflow\rtl\axis_out_shift.sv
+E:\SU24\cgra4ml\deepsocflow\rtl\axis_pixels.sv
+E:\SU24\cgra4ml\deepsocflow\rtl\axis_weight_rotator.sv
+E:\SU24\cgra4ml\deepsocflow\rtl\counter.sv
+E:\SU24\cgra4ml\deepsocflow\rtl\cyclic_bram.sv
+E:\SU24\cgra4ml\deepsocflow\rtl\dma_controller.sv
+E:\SU24\cgra4ml\deepsocflow\rtl\n_delay.sv
+E:\SU24\cgra4ml\deepsocflow\rtl\proc_engine.sv
+E:\SU24\cgra4ml\deepsocflow\rtl\ram.sv
+E:\SU24\cgra4ml\deepsocflow\rtl\ext\alex_axilite_ram.sv
+E:\SU24\cgra4ml\deepsocflow\rtl\ext\alex_axilite_rd.sv
+E:\SU24\cgra4ml\deepsocflow\rtl\ext\alex_axilite_wr.sv
+E:\SU24\cgra4ml\deepsocflow\rtl\ext\alex_axis_adapter.sv
+E:\SU24\cgra4ml\deepsocflow\rtl\ext\alex_axis_adapter_any.sv
+E:\SU24\cgra4ml\deepsocflow\rtl\ext\alex_axi_dma_rd.sv
+E:\SU24\cgra4ml\deepsocflow\rtl\ext\alex_axi_dma_wr.sv
+E:\SU24\cgra4ml\deepsocflow\rtl\ext\xilinx_sdp.sv
+E:\SU24\cgra4ml\run\work\config_hw.svh
+E:\SU24\cgra4ml\run\work\config_tb.svh
\ No newline at end of file
diff --git a/run/work/vivado_flow.tcl b/run/work/vivado_flow.tcl
index 2237fad..3bcd388 100644
--- a/run/work/vivado_flow.tcl
+++ b/run/work/vivado_flow.tcl
@@ -1,8 +1,8 @@
 
 set PROJECT_NAME dsf_zcu104
-set RTL_DIR      /mnt/d/dnn-engine/deepsocflow/rtl
+set RTL_DIR      E:/SU24/cgra4ml/deepsocflow/rtl
 set CONFIG_DIR   .
 
 source config_hw.tcl
-source /mnt/d/dnn-engine/deepsocflow/tcl/fpga/zcu104.tcl
-source /mnt/d/dnn-engine/deepsocflow/tcl/fpga/vivado.tcl
+source E:/SU24/cgra4ml/deepsocflow/tcl/fpga/zcu104.tcl
+source E:/SU24/cgra4ml/deepsocflow/tcl/fpga/vivado.tcl