From 91066c812ba4e337948482c95912e8dd1e381b34 Mon Sep 17 00:00:00 2001 From: Aba Date: Tue, 28 Nov 2023 22:49:04 -0800 Subject: [PATCH] Fix verilator warnings - all except w_m_ready loop --- .github/workflows/verify.yml | 2 +- deepsocflow/c/runtime.h | 6 +- deepsocflow/py/hardware.py | 2 +- deepsocflow/rtl/axis_pixels.sv | 21 ++- deepsocflow/rtl/axis_weight_rotator.sv | 38 +++-- deepsocflow/rtl/dnn_engine.v | 12 +- deepsocflow/rtl/ext/alex_axis_adapter.v | 4 +- deepsocflow/rtl/ext/alex_axis_adapter_any.sv | 17 +-- deepsocflow/rtl/out_ram_switch.sv | 153 ------------------- deepsocflow/test/sv/dma.sv | 2 +- deepsocflow/test/sv/dnn_engine_tb.sv | 4 +- 11 files changed, 65 insertions(+), 196 deletions(-) delete mode 100644 deepsocflow/rtl/out_ram_switch.sv diff --git a/.github/workflows/verify.yml b/.github/workflows/verify.yml index 54a9e2f..6870855 100644 --- a/.github/workflows/verify.yml +++ b/.github/workflows/verify.yml @@ -26,7 +26,7 @@ jobs: - name: Install Verilator run: | sudo apt-get install git help2man perl python3 make autoconf g++ flex bison ccache libunwind-dev - sudo apt-get install libgoogle-perftools-dev numactl perl-doc + sudo apt-get install libgoogle-perftools-dev numactl #perl-doc sudo apt-get install libfl2 # Ubuntu only (ignore if gives error) sudo apt-get install libfl-dev # Ubuntu only (ignore if gives error) # sudo apt-get install zlibc zlib1g zlib1g-dev # Ubuntu only (ignore if gives error) diff --git a/deepsocflow/c/runtime.h b/deepsocflow/c/runtime.h index 99990b9..9ef10b8 100644 --- a/deepsocflow/c/runtime.h +++ b/deepsocflow/c/runtime.h @@ -481,8 +481,8 @@ extern EXT_C void load_y (uint8_t *p_done, uint64_t *p_base_addr_next, int32_t * FILE *fp_tiled = fopen(f_path_tiled, "w"); for (int32_t i=0; io_words; i++) if (ib == N_BUNDLES-1) - if (pb->is_softmax) fprintf(fp_tiled,"%f\n", mem.y[i]); - else fprintf(fp_tiled,"%d\n", mem.y[i]); + if (pb->is_softmax) fprintf(fp_tiled,"%f\n", (float )mem.y[i]); + else fprintf(fp_tiled,"%d\n", (int32_t)mem.y[i]); else fprintf(fp_tiled,"%d\n", mem.debug_tiled[i]); fclose(fp_tiled); @@ -555,7 +555,7 @@ extern EXT_C void fill_memory (uint64_t *p_w_base, uint64_t *p_x_base){ fp = fopen(f_path, "rb"); if(!fp) printf("ERROR! File not found: %s \n", f_path); - fread(mem.w, 1, WB_BYTES+X_BYTES, fp); + int bytes = fread(mem.w, 1, WB_BYTES+X_BYTES, fp); fclose(fp); for (int32_t i=0; i y) begin - max = x; - min = y; - end else begin - max = y; - min = x; - end - - for (i=max; i <= x*y; i=i+max) - if ( !found && (i % min == 0)) begin - lcm = i; - found = 1; - end + for (int m=x*y; m >= x; m=m-x) // Every multiple of x from x*y down to x + if (m % y == 0) lcm = m; // Return the smallest multiple of x that is divisible by y endfunction localparam I_DATA_WIDTH = lcm(S_DATA_WIDTH, M_DATA_WIDTH); diff --git a/deepsocflow/rtl/out_ram_switch.sv b/deepsocflow/rtl/out_ram_switch.sv deleted file mode 100644 index ec76d9e..0000000 --- a/deepsocflow/rtl/out_ram_switch.sv +++ /dev/null @@ -1,153 +0,0 @@ -`include "defines.svh" - -module out_ram_switch #( - localparam ROWS = `ROWS , - COLS = `COLS , - KW_MAX = `KW_MAX , - Y_BITS = `Y_BITS , - RAM_LATENCY = 2, - WORD_WIDTH = 32, // always 32, byte enable available for smaller width, but complicated - ADDR_WIDTH = 10 // word address -)( - input logic clk, rstn, - - output logic s_ready, - input logic [ROWS -1:0][Y_BITS -1:0] s_data, - input logic s_valid, s_last, - - input logic [(ADDR_WIDTH+2)-1:0] m_ram_addr_a, - output logic [ WORD_WIDTH -1:0] m_ram_rddata_a, - input logic m_ram_en_a, - - output logic m_done_fill, - input logic m_t_done_proc -); - - localparam BITS_COLS = $clog2(COLS), BITS_ROWS = $clog2(ROWS); - enum {W_IDLE_S, W_WRITE_S, W_FILL_S, W_SWITCH_S} state_write, state_write_next; - enum {R_IDLE_S, R_DONE_FILL_S, R_READ_S, R_WAIT_S, R_SWITCH_S} state_read, state_read_next; - - logic i_read, i_write, s_first, en_shift, last, dp_prev, lc_rows, l_rows; - - logic [ADDR_WIDTH-1:0] ram_w_addr, ram_r_addr; - logic [ROWS-1:0][Y_BITS -1:0] shift_reg; - logic [Y_BITS -1:0] ram_din; - - logic [1:0][ADDR_WIDTH-1:0] ram_addr; - logic [1:0][Y_BITS -1:0] ram_dout; - logic [1:0] done_read, done_write, ram_wen; - - // Switching RAMs - always_ff @(posedge clk) - if (!rstn) {i_write, i_read} <= 0; - else begin - if (state_write == W_SWITCH_S) i_write <= !i_write; - if (state_read == R_SWITCH_S) i_read <= !i_read; - end - - always_ff @(posedge clk) begin - state_write <= !rstn ? W_IDLE_S : state_write_next; - state_read <= !rstn ? R_IDLE_S : state_read_next; - end - - - // ----- - // WRITE - // ----- - always_comb - unique case (state_write) - W_IDLE_S : if (done_read [i_write]) state_write_next = W_WRITE_S; // counter - W_WRITE_S : if (lc_rows && last ) state_write_next = W_FILL_S; - W_FILL_S : state_write_next = W_SWITCH_S; - W_SWITCH_S : state_write_next = W_IDLE_S; - endcase - - always_ff @(posedge clk) // Special case - first beat of a packet. Bcz lc_rows = 0 at start - if (!rstn || (state_write == W_FILL_S)) s_first <= 1; - else if (s_valid && s_ready) s_first <= 0; - - always_comb begin - s_ready = (state_write == W_WRITE_S && state_write_next == W_WRITE_S) && (s_first || l_rows); // first or after shifting rows - en_shift = (state_write == W_WRITE_S) && (l_rows ? s_valid || last : 1) && !s_first; // if last, wait for valid - ram_din = shift_reg[0]; - end - - always_ff @(posedge clk) // SHIFT REG - write data - if (s_valid && s_ready) shift_reg <= s_data; - else if (en_shift) shift_reg <= shift_reg >> Y_BITS; - - counter #(.W(BITS_ROWS)) C_ROWS (.clk(clk), .reset(state_write == W_IDLE_S), .en(en_shift), .max_in(BITS_ROWS'(ROWS-1)), .last_clk(lc_rows), .last(l_rows)); - - always_ff @(posedge clk) // w_addr - if (!rstn || state_write==W_IDLE_S) ram_w_addr <= 0; - else if (en_shift) ram_w_addr <= ram_w_addr + 1'b1; - - always_ff @(posedge clk) // Store last - if (!rstn) last <= 0; - else if (s_valid && s_ready) last <= s_last; - - - - // ----- - // READ - // ----- - // 1. fw starts, waits for t_m_done_fill to toggle - // 2. mod toggles t_m_done_fill, moving to READ_S, waits for m_t_done_proc - // 3. fw continues, finishes processing, toggles m_t_done_proc - // 4. mod senses m_t_done_proc in READ_S, moves, waits for done_write, toggles t_m_done_fill - // 5. fw loops to beginning, waits for t_m_done_fill to toggle - - always_comb - unique case (state_read) - R_IDLE_S : if (done_write [i_read]) state_read_next = R_DONE_FILL_S; - R_DONE_FILL_S: state_read_next = R_READ_S; - R_READ_S : if (dp_prev != m_t_done_proc) state_read_next = R_WAIT_S; - R_WAIT_S : state_read_next = R_SWITCH_S; - R_SWITCH_S : state_read_next = R_IDLE_S; - endcase - - assign ram_r_addr = m_ram_addr_a[(ADDR_WIDTH+2)-1:2]; - assign m_ram_rddata_a = WORD_WIDTH'(signed'(ram_dout[i_read])); // pad to 32 - assign m_done_fill = state_read == R_DONE_FILL_S; // one clock for interrupt - - // always_ff @(posedge clk) - // if (!rstn) t_m_done_fill <= 0; - // else if (state_read == R_DONE_FILL_S) t_m_done_fill <= !t_m_done_fill; - - always_ff @(posedge clk) - if (!rstn) dp_prev <= 0; // m_t_done_proc starts at 0 - else if (state_read_next == R_WAIT_S) dp_prev <= m_t_done_proc; // sample dp_prev at end of reading - - // ----- - // PING PONG - // ----- - generate - for (genvar i=0; i<2; i++) begin: I - - always_ff @(posedge clk) - if (!rstn) done_write[i] <= 0; - else if (i==i_write) - if (state_write_next == W_WRITE_S) done_write[i] <= 0; - else if (state_write == W_SWITCH_S) done_write[i] <= 1; - - always_ff @(posedge clk) - if (!rstn) done_read [i] <= 1; - else if (i==i_read) - if (state_read_next == R_READ_S) done_read [i] <= 0; - else if (state_read == R_SWITCH_S) done_read [i] <= 1; - - assign ram_wen [i] = i == i_write && en_shift && !s_first; - assign ram_addr [i] = (i == i_write && state_write == W_WRITE_S) ? ram_w_addr : ram_r_addr; - - localparam RAM_ADDR_BITS = $clog2(COLS*ROWS); - ram_output RAM ( - .clka (clk), - .ena (1'b1), - .wea (ram_wen [i] ), - .addra (RAM_ADDR_BITS'(ram_addr[i])), - .dina (ram_din ), - .douta (ram_dout[i] ) - ); - end - endgenerate -endmodule \ No newline at end of file diff --git a/deepsocflow/test/sv/dma.sv b/deepsocflow/test/sv/dma.sv index db5d847..ed300ab 100644 --- a/deepsocflow/test/sv/dma.sv +++ b/deepsocflow/test/sv/dma.sv @@ -98,7 +98,7 @@ module DMA_S2M #( set_byte(base_addr + i_bytes, m_data[i]); i_bytes += 1; end - if (m_last) done <= 1; + if (m_last) done = 1; end #10ps // delay before writing diff --git a/deepsocflow/test/sv/dnn_engine_tb.sv b/deepsocflow/test/sv/dnn_engine_tb.sv index 49821cc..4ffd2b6 100644 --- a/deepsocflow/test/sv/dnn_engine_tb.sv +++ b/deepsocflow/test/sv/dnn_engine_tb.sv @@ -11,7 +11,7 @@ module dnn_engine_tb; // CLOCK GENERATION logic aclk = 0; localparam CLK_PERIOD = 10ns; - initial forever #(CLK_PERIOD/2) aclk <= ~aclk; + initial forever #(CLK_PERIOD/2) aclk = ~aclk; // SIGNALS @@ -76,7 +76,7 @@ module dnn_engine_tb; while (1) begin load_x (x_done, bundle_read_done, x_base, x_bpt); source_x.axis_push(x_base, x_bpt); - while(bundle_read_done && !get_is_bundle_write_done()) #10ps; + while(bundle_read_done && get_is_bundle_write_done()==8'b0) #10ps; $display("Done input dma at offset=%h, bpt=%d \n", x_base, x_bpt); if (x_done) break; end