From 62906209bdf361c266b43cc0ad4f984b21add9a4 Mon Sep 17 00:00:00 2001 From: Aba Date: Thu, 16 Nov 2023 15:50:36 -0800 Subject: [PATCH] Major Restructure: Move RTL,TCL,TB to deepsocflow for deployment. Keep config and build files outside --- .github/workflows/verify.yml | 8 +- .gitignore | 36 +++++---- deepsocflow/__init__.py | 4 +- .../asic}/constraints/dnn_engine.sdc | 0 .../asic}/constraints/proc_engine_out.sdc | 0 {asic => deepsocflow/asic}/scripts/clock.tcl | 0 .../asic}/scripts/initialFloorplan.tcl | 0 .../asic}/scripts/loadDesignTech.tcl | 0 .../asic}/scripts/outputGen.tcl | 0 .../asic}/scripts/pinPlacement.tcl | 0 .../asic}/scripts/placement.tcl | 0 {asic => deepsocflow/asic}/scripts/pnr.tcl | 0 .../asic}/scripts/reportDesign.tcl | 0 {asic => deepsocflow/asic}/scripts/route.tcl | 0 {asic => deepsocflow/asic}/scripts/run_dc.tcl | 0 .../asic}/scripts/run_genus.tcl | 0 {asic => deepsocflow/asic}/scripts/view.tcl | 0 {c => deepsocflow/c}/example.c | 0 {c => deepsocflow/c}/runtime.h | 2 +- .../fpga}/scripts/pynq_z2.tcl | 0 {fpga => deepsocflow/fpga}/scripts/vivado.tcl | 0 {fpga => deepsocflow/fpga}/scripts/zcu104.tcl | 0 deepsocflow/py/__init__.py | 3 + {test => deepsocflow}/py/bundle.py | 0 deepsocflow/py/hardware.py | 4 +- {rtl => deepsocflow/rtl}/axis_out_shift.sv | 2 +- {rtl => deepsocflow/rtl}/axis_pixels.sv | 2 +- .../rtl}/axis_weight_rotator.sv | 2 +- {rtl => deepsocflow/rtl}/counter.sv | 0 {rtl/sram => deepsocflow/rtl}/cyclic_bram.sv | 0 .../params.svh => deepsocflow/rtl/defines.svh | 2 +- {rtl => deepsocflow/rtl}/dnn_engine.v | 2 +- .../rtl}/ext/alex_axis_adapter.v | 0 .../rtl}/ext/alex_axis_adapter_any.sv | 0 .../rtl}/ext/alex_axis_pipeline_register.v | 0 .../rtl}/ext/alex_axis_register.v | 0 {rtl => deepsocflow/rtl}/huffman_2_decoder.sv | 0 {rtl => deepsocflow/rtl}/n_delay.sv | 0 {rtl => deepsocflow/rtl}/out_ram_switch.sv | 2 +- {rtl => deepsocflow/rtl}/proc_element.sv | 0 {rtl => deepsocflow/rtl}/proc_engine.sv | 2 +- .../test}/py/performance.ipynb | 0 .../test}/py/pooling_no_np.ipynb | 0 .../test}/py/resnet18_bundle_api.ipynb | 0 .../test}/py/resnet50_parser.ipynb | 0 .../test}/py/single_workload_check.ipynb | 0 {test => deepsocflow/test}/py/tiling.ipynb | 0 {test => deepsocflow/test}/sv/axis_tb.sv | 0 {test => deepsocflow/test}/sv/counter_tb.sv | 0 {test => deepsocflow/test}/sv/dma.sv | 0 .../test}/sv/dnn_engine_tb.sv | 4 +- {test => deepsocflow/test}/sv/ram_raw.sv | 2 +- .../test}/sv/skid_buffer_tb.sv | 0 .../test}/wave/dnn_engine_tb_behav.wcfg | 0 pyproject.toml | 2 +- rtl/sram/sdp_array.sv | 78 ------------------- {asic => run/asic}/reports/area.rpt | 0 {asic => run/asic}/reports/power.rpt | 0 {asic => run/asic}/reports/timing.rpt | 0 {test/py => run}/param_test.py | 61 +++++++-------- c/model.h => run/work/config_fw.h | 2 +- .../work/config_hw.svh | 0 .../work/config_hw.tcl | 0 run/work/config_tb.svh | 2 + run/work/sources.txt | 23 ++++++ 65 files changed, 100 insertions(+), 145 deletions(-) rename {asic => deepsocflow/asic}/constraints/dnn_engine.sdc (100%) rename {asic => deepsocflow/asic}/constraints/proc_engine_out.sdc (100%) rename {asic => deepsocflow/asic}/scripts/clock.tcl (100%) rename {asic => deepsocflow/asic}/scripts/initialFloorplan.tcl (100%) rename {asic => deepsocflow/asic}/scripts/loadDesignTech.tcl (100%) rename {asic => deepsocflow/asic}/scripts/outputGen.tcl (100%) rename {asic => deepsocflow/asic}/scripts/pinPlacement.tcl (100%) rename {asic => deepsocflow/asic}/scripts/placement.tcl (100%) rename {asic => deepsocflow/asic}/scripts/pnr.tcl (100%) rename {asic => deepsocflow/asic}/scripts/reportDesign.tcl (100%) rename {asic => deepsocflow/asic}/scripts/route.tcl (100%) rename {asic => deepsocflow/asic}/scripts/run_dc.tcl (100%) rename {asic => deepsocflow/asic}/scripts/run_genus.tcl (100%) rename {asic => deepsocflow/asic}/scripts/view.tcl (100%) rename {c => deepsocflow/c}/example.c (100%) rename {c => deepsocflow/c}/runtime.h (99%) rename {fpga => deepsocflow/fpga}/scripts/pynq_z2.tcl (100%) rename {fpga => deepsocflow/fpga}/scripts/vivado.tcl (100%) rename {fpga => deepsocflow/fpga}/scripts/zcu104.tcl (100%) rename {test => deepsocflow}/py/bundle.py (100%) rename {rtl => deepsocflow/rtl}/axis_out_shift.sv (98%) rename {rtl => deepsocflow/rtl}/axis_pixels.sv (99%) rename {rtl => deepsocflow/rtl}/axis_weight_rotator.sv (99%) rename {rtl => deepsocflow/rtl}/counter.sv (100%) rename {rtl/sram => deepsocflow/rtl}/cyclic_bram.sv (100%) rename rtl/include/params.svh => deepsocflow/rtl/defines.svh (93%) rename {rtl => deepsocflow/rtl}/dnn_engine.v (99%) rename {rtl => deepsocflow/rtl}/ext/alex_axis_adapter.v (100%) rename {rtl => deepsocflow/rtl}/ext/alex_axis_adapter_any.sv (100%) rename {rtl => deepsocflow/rtl}/ext/alex_axis_pipeline_register.v (100%) rename {rtl => deepsocflow/rtl}/ext/alex_axis_register.v (100%) rename {rtl => deepsocflow/rtl}/huffman_2_decoder.sv (100%) rename {rtl => deepsocflow/rtl}/n_delay.sv (100%) rename {rtl => deepsocflow/rtl}/out_ram_switch.sv (99%) rename {rtl => deepsocflow/rtl}/proc_element.sv (100%) rename {rtl => deepsocflow/rtl}/proc_engine.sv (99%) rename {test => deepsocflow/test}/py/performance.ipynb (100%) rename {test => deepsocflow/test}/py/pooling_no_np.ipynb (100%) rename {test => deepsocflow/test}/py/resnet18_bundle_api.ipynb (100%) rename {test => deepsocflow/test}/py/resnet50_parser.ipynb (100%) rename {test => deepsocflow/test}/py/single_workload_check.ipynb (100%) rename {test => deepsocflow/test}/py/tiling.ipynb (100%) rename {test => deepsocflow/test}/sv/axis_tb.sv (100%) rename {test => deepsocflow/test}/sv/counter_tb.sv (100%) rename {test => deepsocflow/test}/sv/dma.sv (100%) rename {test => deepsocflow/test}/sv/dnn_engine_tb.sv (98%) rename {test => deepsocflow/test}/sv/ram_raw.sv (98%) rename {test => deepsocflow/test}/sv/skid_buffer_tb.sv (100%) rename {test => deepsocflow/test}/wave/dnn_engine_tb_behav.wcfg (100%) delete mode 100644 rtl/sram/sdp_array.sv rename {asic => run/asic}/reports/area.rpt (100%) rename {asic => run/asic}/reports/power.rpt (100%) rename {asic => run/asic}/reports/timing.rpt (100%) rename {test/py => run}/param_test.py (91%) rename c/model.h => run/work/config_fw.h (99%) rename rtl/include/params_input.svh => run/work/config_hw.svh (100%) rename fpga/scripts/vivado_config.tcl => run/work/config_hw.tcl (100%) create mode 100644 run/work/config_tb.svh create mode 100644 run/work/sources.txt diff --git a/.github/workflows/verify.yml b/.github/workflows/verify.yml index 58d4705..902bb05 100644 --- a/.github/workflows/verify.yml +++ b/.github/workflows/verify.yml @@ -45,6 +45,8 @@ jobs: export PATH=${VERILATOR_ROOT}/bin:${PATH} export PYMTL_VERILATOR_INCLUDE_DIR=${VERILATOR_ROOT}/share/verilator/include verilator --version - - cd test - python -m pytest -s py/param_test.py \ No newline at end of file + + pip install . + mkdir -p run/work + cd run/work + python -m pytest -s ../param_test.py \ No newline at end of file diff --git a/.gitignore b/.gitignore index a1b8b5c..944426b 100644 --- a/.gitignore +++ b/.gitignore @@ -1,26 +1,27 @@ old/ __pycache__ -fpga/* -!fpga/scripts +run/fpga/* -asic/* -!asic/scripts -!asic/reports +run/asic/* +!deepsocflow/asic/reports *.pickle -test/vectors -test/xsim -test/dnn_engine_tb.vcd -test/xsc* -test/obj_dir -test/models -test/temp +deepsocflow/test/vectors +deepsocflow/test/xsim +deepsocflow/test/dnn_engine_tb.vcd +deepsocflow/test/xsc* +deepsocflow/test/obj_dir +deepsocflow/test/models +deepsocflow/test/temp -test/py/* +deepsocflow/test/py/* .svls.toml +run/work/vectors/* +run/work/build/* + # Distribution / packaging .Python @@ -50,6 +51,11 @@ MANIFEST # Sphinx documentation docs/** +!docs/source +docs/source/** !docs/source/conf.py -!docs/source/index.rst -!docs/source/modules.rst \ No newline at end of file +!docs/source/*.rst + +# VSCode +settings.json +.vscode \ No newline at end of file diff --git a/deepsocflow/__init__.py b/deepsocflow/__init__.py index 2db30dc..fb0dd5a 100644 --- a/deepsocflow/__init__.py +++ b/deepsocflow/__init__.py @@ -1,2 +1,2 @@ -from deepsocflow.py.hardware import * -from deepsocflow.py.utils import * \ No newline at end of file +from . import py +from .py import * \ No newline at end of file diff --git a/asic/constraints/dnn_engine.sdc b/deepsocflow/asic/constraints/dnn_engine.sdc similarity index 100% rename from asic/constraints/dnn_engine.sdc rename to deepsocflow/asic/constraints/dnn_engine.sdc diff --git a/asic/constraints/proc_engine_out.sdc b/deepsocflow/asic/constraints/proc_engine_out.sdc similarity index 100% rename from asic/constraints/proc_engine_out.sdc rename to deepsocflow/asic/constraints/proc_engine_out.sdc diff --git a/asic/scripts/clock.tcl b/deepsocflow/asic/scripts/clock.tcl similarity index 100% rename from asic/scripts/clock.tcl rename to deepsocflow/asic/scripts/clock.tcl diff --git a/asic/scripts/initialFloorplan.tcl b/deepsocflow/asic/scripts/initialFloorplan.tcl similarity index 100% rename from asic/scripts/initialFloorplan.tcl rename to deepsocflow/asic/scripts/initialFloorplan.tcl diff --git a/asic/scripts/loadDesignTech.tcl b/deepsocflow/asic/scripts/loadDesignTech.tcl similarity index 100% rename from asic/scripts/loadDesignTech.tcl rename to deepsocflow/asic/scripts/loadDesignTech.tcl diff --git a/asic/scripts/outputGen.tcl b/deepsocflow/asic/scripts/outputGen.tcl similarity index 100% rename from asic/scripts/outputGen.tcl rename to deepsocflow/asic/scripts/outputGen.tcl diff --git a/asic/scripts/pinPlacement.tcl b/deepsocflow/asic/scripts/pinPlacement.tcl similarity index 100% rename from asic/scripts/pinPlacement.tcl rename to deepsocflow/asic/scripts/pinPlacement.tcl diff --git a/asic/scripts/placement.tcl b/deepsocflow/asic/scripts/placement.tcl similarity index 100% rename from asic/scripts/placement.tcl rename to deepsocflow/asic/scripts/placement.tcl diff --git a/asic/scripts/pnr.tcl b/deepsocflow/asic/scripts/pnr.tcl similarity index 100% rename from asic/scripts/pnr.tcl rename to deepsocflow/asic/scripts/pnr.tcl diff --git a/asic/scripts/reportDesign.tcl b/deepsocflow/asic/scripts/reportDesign.tcl similarity index 100% rename from asic/scripts/reportDesign.tcl rename to deepsocflow/asic/scripts/reportDesign.tcl diff --git a/asic/scripts/route.tcl b/deepsocflow/asic/scripts/route.tcl similarity index 100% rename from asic/scripts/route.tcl rename to deepsocflow/asic/scripts/route.tcl diff --git a/asic/scripts/run_dc.tcl b/deepsocflow/asic/scripts/run_dc.tcl similarity index 100% rename from asic/scripts/run_dc.tcl rename to deepsocflow/asic/scripts/run_dc.tcl diff --git a/asic/scripts/run_genus.tcl b/deepsocflow/asic/scripts/run_genus.tcl similarity index 100% rename from asic/scripts/run_genus.tcl rename to deepsocflow/asic/scripts/run_genus.tcl diff --git a/asic/scripts/view.tcl b/deepsocflow/asic/scripts/view.tcl similarity index 100% rename from asic/scripts/view.tcl rename to deepsocflow/asic/scripts/view.tcl diff --git a/c/example.c b/deepsocflow/c/example.c similarity index 100% rename from c/example.c rename to deepsocflow/c/example.c diff --git a/c/runtime.h b/deepsocflow/c/runtime.h similarity index 99% rename from c/runtime.h rename to deepsocflow/c/runtime.h index 12bcecc..55bb407 100644 --- a/c/runtime.h +++ b/deepsocflow/c/runtime.h @@ -24,7 +24,7 @@ typedef const struct { typedef enum {POOL_NONE, POOL_MAX, POOL_AVG} Pool_t; -#include "model.h" +#include "config_fw.h" #define X_BITS (1 << X_BITS_L2) #define X_WORDS_PER_BYTE (8 / X_BITS) #define X_BITS_MASK ((1 << X_BITS) -1) diff --git a/fpga/scripts/pynq_z2.tcl b/deepsocflow/fpga/scripts/pynq_z2.tcl similarity index 100% rename from fpga/scripts/pynq_z2.tcl rename to deepsocflow/fpga/scripts/pynq_z2.tcl diff --git a/fpga/scripts/vivado.tcl b/deepsocflow/fpga/scripts/vivado.tcl similarity index 100% rename from fpga/scripts/vivado.tcl rename to deepsocflow/fpga/scripts/vivado.tcl diff --git a/fpga/scripts/zcu104.tcl b/deepsocflow/fpga/scripts/zcu104.tcl similarity index 100% rename from fpga/scripts/zcu104.tcl rename to deepsocflow/fpga/scripts/zcu104.tcl diff --git a/deepsocflow/py/__init__.py b/deepsocflow/py/__init__.py index e69de29..77079a9 100644 --- a/deepsocflow/py/__init__.py +++ b/deepsocflow/py/__init__.py @@ -0,0 +1,3 @@ +from . import hardware, bundle +from .hardware import * +from .bundle import * \ No newline at end of file diff --git a/test/py/bundle.py b/deepsocflow/py/bundle.py similarity index 100% rename from test/py/bundle.py rename to deepsocflow/py/bundle.py diff --git a/deepsocflow/py/hardware.py b/deepsocflow/py/hardware.py index e22f900..d142f65 100644 --- a/deepsocflow/py/hardware.py +++ b/deepsocflow/py/hardware.py @@ -58,8 +58,8 @@ def __init__( self.XN_MAX = max_batch_size self.CI_MAX = max_channels_in self.CO_MAX = max_channels_out - self.KH_MAX, self.KW_MAX = max_kernel_size if (type(max_kernel_size) == tuple) else (max_kernel_size, max_kernel_size) - self.XH_MAX, self.XW_MAX = max_image_size if (type(max_image_size) == tuple) else (max_image_size, max_image_size) + self.KH_MAX, self.KW_MAX = tuple(max_kernel_size) if (type(max_kernel_size) in [tuple, list]) else (max_kernel_size, max_kernel_size) + self.XH_MAX, self.XW_MAX = tuple(max_image_size ) if (type(max_image_size ) in [tuple, list]) else (max_image_size , max_image_size ) self.RAM_WEIGHTS_DEPTH = int((weights_cache_kbytes*1024)/(self.K_BITS*self.COLS*2)) ''' diff --git a/rtl/axis_out_shift.sv b/deepsocflow/rtl/axis_out_shift.sv similarity index 98% rename from rtl/axis_out_shift.sv rename to deepsocflow/rtl/axis_out_shift.sv index b7a83db..a7c3154 100644 --- a/rtl/axis_out_shift.sv +++ b/deepsocflow/rtl/axis_out_shift.sv @@ -1,4 +1,4 @@ -`include "../rtl/include/params.svh" +`include "defines.svh" module axis_out_shift #( localparam ROWS = `ROWS , diff --git a/rtl/axis_pixels.sv b/deepsocflow/rtl/axis_pixels.sv similarity index 99% rename from rtl/axis_pixels.sv rename to deepsocflow/rtl/axis_pixels.sv index f4b8bd0..8be1e8d 100644 --- a/rtl/axis_pixels.sv +++ b/deepsocflow/rtl/axis_pixels.sv @@ -1,5 +1,5 @@ `timescale 1ns/1ps -`include "../rtl/include/params.svh" +`include "defines.svh" module axis_pixels #( parameter ROWS = `ROWS , diff --git a/rtl/axis_weight_rotator.sv b/deepsocflow/rtl/axis_weight_rotator.sv similarity index 99% rename from rtl/axis_weight_rotator.sv rename to deepsocflow/rtl/axis_weight_rotator.sv index 120b94f..f6c4a14 100644 --- a/rtl/axis_weight_rotator.sv +++ b/deepsocflow/rtl/axis_weight_rotator.sv @@ -3,7 +3,7 @@ Engineer: Abarajithan G. Design Name: AXIS Weight Rotator */ `timescale 1ns/1ps -`include "../rtl/include/params.svh" +`include "defines.svh" module axis_weight_rotator #( parameter diff --git a/rtl/counter.sv b/deepsocflow/rtl/counter.sv similarity index 100% rename from rtl/counter.sv rename to deepsocflow/rtl/counter.sv diff --git a/rtl/sram/cyclic_bram.sv b/deepsocflow/rtl/cyclic_bram.sv similarity index 100% rename from rtl/sram/cyclic_bram.sv rename to deepsocflow/rtl/cyclic_bram.sv diff --git a/rtl/include/params.svh b/deepsocflow/rtl/defines.svh similarity index 93% rename from rtl/include/params.svh rename to deepsocflow/rtl/defines.svh index 915c85e..7ad7936 100644 --- a/rtl/include/params.svh +++ b/deepsocflow/rtl/defines.svh @@ -1,4 +1,4 @@ - `include "params_input.svh" + `include "config_hw.svh" `define BITS_KW2 $clog2((`KW_MAX+1)/2) diff --git a/rtl/dnn_engine.v b/deepsocflow/rtl/dnn_engine.v similarity index 99% rename from rtl/dnn_engine.v rename to deepsocflow/rtl/dnn_engine.v index 9fd5b97..5dc4da5 100644 --- a/rtl/dnn_engine.v +++ b/deepsocflow/rtl/dnn_engine.v @@ -1,6 +1,6 @@ `timescale 1ns/1ps `define VERILOG -`include "../rtl/include/params.svh" +`include "defines.svh" `undef VERILOG module dnn_engine #( diff --git a/rtl/ext/alex_axis_adapter.v b/deepsocflow/rtl/ext/alex_axis_adapter.v similarity index 100% rename from rtl/ext/alex_axis_adapter.v rename to deepsocflow/rtl/ext/alex_axis_adapter.v diff --git a/rtl/ext/alex_axis_adapter_any.sv b/deepsocflow/rtl/ext/alex_axis_adapter_any.sv similarity index 100% rename from rtl/ext/alex_axis_adapter_any.sv rename to deepsocflow/rtl/ext/alex_axis_adapter_any.sv diff --git a/rtl/ext/alex_axis_pipeline_register.v b/deepsocflow/rtl/ext/alex_axis_pipeline_register.v similarity index 100% rename from rtl/ext/alex_axis_pipeline_register.v rename to deepsocflow/rtl/ext/alex_axis_pipeline_register.v diff --git a/rtl/ext/alex_axis_register.v b/deepsocflow/rtl/ext/alex_axis_register.v similarity index 100% rename from rtl/ext/alex_axis_register.v rename to deepsocflow/rtl/ext/alex_axis_register.v diff --git a/rtl/huffman_2_decoder.sv b/deepsocflow/rtl/huffman_2_decoder.sv similarity index 100% rename from rtl/huffman_2_decoder.sv rename to deepsocflow/rtl/huffman_2_decoder.sv diff --git a/rtl/n_delay.sv b/deepsocflow/rtl/n_delay.sv similarity index 100% rename from rtl/n_delay.sv rename to deepsocflow/rtl/n_delay.sv diff --git a/rtl/out_ram_switch.sv b/deepsocflow/rtl/out_ram_switch.sv similarity index 99% rename from rtl/out_ram_switch.sv rename to deepsocflow/rtl/out_ram_switch.sv index 814cbe9..ec76d9e 100644 --- a/rtl/out_ram_switch.sv +++ b/deepsocflow/rtl/out_ram_switch.sv @@ -1,4 +1,4 @@ -`include "../rtl/include/params.svh" +`include "defines.svh" module out_ram_switch #( localparam ROWS = `ROWS , diff --git a/rtl/proc_element.sv b/deepsocflow/rtl/proc_element.sv similarity index 100% rename from rtl/proc_element.sv rename to deepsocflow/rtl/proc_element.sv diff --git a/rtl/proc_engine.sv b/deepsocflow/rtl/proc_engine.sv similarity index 99% rename from rtl/proc_engine.sv rename to deepsocflow/rtl/proc_engine.sv index 7443852..f39542b 100644 --- a/rtl/proc_engine.sv +++ b/deepsocflow/rtl/proc_engine.sv @@ -1,5 +1,5 @@ `timescale 1ns/1ps -`include "../rtl/include/params.svh" +`include "defines.svh" module proc_engine #( localparam COLS = `COLS , diff --git a/test/py/performance.ipynb b/deepsocflow/test/py/performance.ipynb similarity index 100% rename from test/py/performance.ipynb rename to deepsocflow/test/py/performance.ipynb diff --git a/test/py/pooling_no_np.ipynb b/deepsocflow/test/py/pooling_no_np.ipynb similarity index 100% rename from test/py/pooling_no_np.ipynb rename to deepsocflow/test/py/pooling_no_np.ipynb diff --git a/test/py/resnet18_bundle_api.ipynb b/deepsocflow/test/py/resnet18_bundle_api.ipynb similarity index 100% rename from test/py/resnet18_bundle_api.ipynb rename to deepsocflow/test/py/resnet18_bundle_api.ipynb diff --git a/test/py/resnet50_parser.ipynb b/deepsocflow/test/py/resnet50_parser.ipynb similarity index 100% rename from test/py/resnet50_parser.ipynb rename to deepsocflow/test/py/resnet50_parser.ipynb diff --git a/test/py/single_workload_check.ipynb b/deepsocflow/test/py/single_workload_check.ipynb similarity index 100% rename from test/py/single_workload_check.ipynb rename to deepsocflow/test/py/single_workload_check.ipynb diff --git a/test/py/tiling.ipynb b/deepsocflow/test/py/tiling.ipynb similarity index 100% rename from test/py/tiling.ipynb rename to deepsocflow/test/py/tiling.ipynb diff --git a/test/sv/axis_tb.sv b/deepsocflow/test/sv/axis_tb.sv similarity index 100% rename from test/sv/axis_tb.sv rename to deepsocflow/test/sv/axis_tb.sv diff --git a/test/sv/counter_tb.sv b/deepsocflow/test/sv/counter_tb.sv similarity index 100% rename from test/sv/counter_tb.sv rename to deepsocflow/test/sv/counter_tb.sv diff --git a/test/sv/dma.sv b/deepsocflow/test/sv/dma.sv similarity index 100% rename from test/sv/dma.sv rename to deepsocflow/test/sv/dma.sv diff --git a/test/sv/dnn_engine_tb.sv b/deepsocflow/test/sv/dnn_engine_tb.sv similarity index 98% rename from test/sv/dnn_engine_tb.sv rename to deepsocflow/test/sv/dnn_engine_tb.sv index 76aa754..1f8ea63 100644 --- a/test/sv/dnn_engine_tb.sv +++ b/deepsocflow/test/sv/dnn_engine_tb.sv @@ -1,7 +1,7 @@ `timescale 1ns/1ps -`include "../../rtl/include/params.svh" -`include "../xsim/sim_params.svh" +`include "../../rtl/defines.svh" +`include "config_tb.svh" module dnn_engine_tb; diff --git a/test/sv/ram_raw.sv b/deepsocflow/test/sv/ram_raw.sv similarity index 98% rename from test/sv/ram_raw.sv rename to deepsocflow/test/sv/ram_raw.sv index c16b3cc..29f9a85 100644 --- a/test/sv/ram_raw.sv +++ b/deepsocflow/test/sv/ram_raw.sv @@ -1,5 +1,5 @@ `timescale 1ns/1ps -`include "../../rtl/include/params.svh" +`include "../../rtl/defines.svh" module ram_raw #( parameter DEPTH = 1, diff --git a/test/sv/skid_buffer_tb.sv b/deepsocflow/test/sv/skid_buffer_tb.sv similarity index 100% rename from test/sv/skid_buffer_tb.sv rename to deepsocflow/test/sv/skid_buffer_tb.sv diff --git a/test/wave/dnn_engine_tb_behav.wcfg b/deepsocflow/test/wave/dnn_engine_tb_behav.wcfg similarity index 100% rename from test/wave/dnn_engine_tb_behav.wcfg rename to deepsocflow/test/wave/dnn_engine_tb_behav.wcfg diff --git a/pyproject.toml b/pyproject.toml index cba8cf7..0ae3166 100644 --- a/pyproject.toml +++ b/pyproject.toml @@ -4,7 +4,7 @@ build-backend = "flit_core.buildapi" [project] name = "deepsocflow" -authors = [{name = "Abarajithan G", email = "abarajithan07@gmail.com"}] +authors = [{name = "Abarajithan G", email = "abarajithan07@gmail.com"}, {name = "Zhenghua Ma", email = "zhm007@ucsd.edu"}] version = "0.0.1" description = "Your DNNs to FPGA/ASIC SoCs in minutes!" requires-python = ">=3.10" diff --git a/rtl/sram/sdp_array.sv b/rtl/sram/sdp_array.sv deleted file mode 100644 index 4a41ec4..0000000 --- a/rtl/sram/sdp_array.sv +++ /dev/null @@ -1,78 +0,0 @@ - -module sdp_array #( - parameter - WIDTH = 96*8, - DEPTH = 2048, - SDP_WIDTH = 32 -)( - clka , - ena , - wea , - addra, - dina , - clkb , - enb , - addrb, - doutb -); - - localparam BITS_DEPTH = $clog2(DEPTH); - localparam NUM_SDP = WIDTH/SDP_WIDTH; - - input logic clka, ena, wea, clkb, enb; - input logic [BITS_DEPTH -1:0] addra; - input logic [BITS_DEPTH -1:0] addrb; - input logic [NUM_SDP-1:0][SDP_WIDTH-1:0] dina ; - output logic [NUM_SDP-1:0][SDP_WIDTH-1:0] doutb; - - generate - for (genvar n=0; n