diff --git a/hw/vendor/pulp_platform_axi/src/axi_id_serialize.sv b/hw/vendor/pulp_platform_axi/src/axi_id_serialize.sv index 9a787dd25..30b662fed 100644 --- a/hw/vendor/pulp_platform_axi/src/axi_id_serialize.sv +++ b/hw/vendor/pulp_platform_axi/src/axi_id_serialize.sv @@ -65,8 +65,10 @@ module axi_id_serialize #( /// than one entry, it is matched to the *last* matching entry's output ID. /// Number of Entries in the explicit ID map (default: None) parameter int unsigned IdMapNumEntries = 32'd0, + /// Index of IdMap to avoid its underflow (Error reported in Synopsys VCS) + parameter int unsigned IdMapIndex = (IdMapNumEntries>0) ? (IdMapNumEntries - 1) : 0, /// Explicit ID map; index [0] in each entry is the input ID to match, index [1] the output ID. - parameter int unsigned IdMap [IdMapNumEntries-1:0][0:1] = '{default: {32'b0, 32'b0}} + parameter int unsigned IdMap [IdMapIndex:0][0:1] = '{default: {32'b0, 32'b0}} ) ( /// Rising-edge clock of both ports input logic clk_i, diff --git a/target/sim_chip/.gitignore b/target/sim_chip/.gitignore index 534ec2d2d..9713623e1 100644 --- a/target/sim_chip/.gitignore +++ b/target/sim_chip/.gitignore @@ -2,5 +2,10 @@ /work-vlt /bin /apps/*.bin +/apps/*.hex /testharness/testharness.sv /logs +/work-vcs +/work.lib++ +/AN.DB +/vc_hdrs.h diff --git a/target/sim_chip/Makefile b/target/sim_chip/Makefile index 62b3841d9..b7ce57400 100644 --- a/target/sim_chip/Makefile +++ b/target/sim_chip/Makefile @@ -54,11 +54,13 @@ CVA6_TRACE = trace_hart_0.log VSIM_BENDER += $(shell cat ../rtl/src/bender_targets.tmp) VLT_BENDER += $(shell cat ../rtl/src/bender_targets.tmp) +VCS_BENDER += $(shell cat ../rtl/src/bender_targets.tmp) VLT_BENDER += -t SYNTHESIS_SNAX_DEV_ONLY VSIM_BENDER += -t simulation_hemaia VLT_BENDER += -t simulation_hemaia +VCS_BENDER += -t simulation_hemaia VSIM_FLAGS += -t 1ps VSIM_FLAGS += -voptargs=+acc @@ -74,6 +76,19 @@ VLOG_FLAGS += -suppress 13314 VLOG_FLAGS += ${QUESTA_64BIT} VLOG_FLAGS += -timescale 1ns/1ps +VCS_FLAGS += +nospecify +VCS_FLAGS += -Mdir=work-vcs +VCS_FLAGS += -Mlib=work-vcs +VCS_FLAGS += -full64 +# Multi-core +VCS_FLAGS += -fgp +# Debug Options +VCS_FLAGS += -assert disable_cover +VCS_FLAGS += -kdb +VCS_FLAGS += +vcs+fsdbon +VCS_FLAGS += +lint=TFIPC-L +VCS_FLAGS += -debug_access+all + # Verilated and compiled Occamy system VLT_AR = ${VLT_BUILDDIR}/Vtestharness__ALL.a @@ -250,6 +265,30 @@ $(BIN_DIR)/occamy_chip.vsim: $(VSIM_BUILDDIR)/compile.vsim.tcl |$(BIN_DIR) clean-vsim: clean-work rm -rf $(BIN_DIR)/$(TARGET).vsim $(BIN_DIR)/$(TARGET).vsim.gui $(VSIM_BUILDDIR) vsim.wlf transcript + + +####### +# VCS # +####### + +$(VCS_BUILDDIR): + mkdir -p $@ + + +$(VCS_BUILDDIR)/compile.sh: $(BENDER_LOCK) | $(VCS_BUILDDIR) testharness/testharness.sv + mkdir -p $(VCS_BUILDDIR) + ${BENDER} script vcs ${VCS_BENDER} --vlog-arg="${VLOGAN_FLAGS}" --vcom-arg="${VHDLAN_FLAGS}" > $@ + # echo '${VCS} -sverilog -full64 -assert svaext -assert disable_cover -debug_acc+all+dmptf -kdb -ntb_opts sv -CCFLAGS="${TB_CC_FLAGS}" -o ../bin/hemaia_chip.simv -top testharness' >> $@ + chmod +x $@ + # $(VCS_SEPP) $@ > $(VCS_BUILDDIR)/compile.log + +$(BIN_DIR)/occamy_chip.vcs: $(VCS_BUILDDIR)/compile.sh + bash work-vcs/compile.sh + mkdir -p $(BIN_DIR) + $(VCS) $(VCS_FLAGS) -o $(BIN_DIR)/occamy_chip.vcs -cc $(CC) -cpp $(CXX) \ + -override_timescale=1ns/1ps -full64 -ignore initializer_driver_checks testharness $(TB_CC_SOURCES) $(RTL_CC_SOURCES) \ + -CFLAGS "$(TB_CC_FLAGS)" -lutil +error+100 + ######## # Util # ######## diff --git a/target/sim_chip/apps/bin2hex.py b/target/sim_chip/apps/bin2hex.py new file mode 100755 index 000000000..b9e836ffa --- /dev/null +++ b/target/sim_chip/apps/bin2hex.py @@ -0,0 +1,73 @@ +import argparse +import os + +# Convert a binary file to a hex string and save it to a text file +def binary_to_hex(input_binary_file, output_text_file, chunk_size): + try: + # Open the binary file in read-binary mode + with open(input_binary_file, 'rb') as bin_file: + binary_data = bin_file.read() # Read the entire binary file + + # Initialize a list to hold the lines + lines = [] + + total_length = len(binary_data) + index = 0 + + # Process the data in chunks of 64 bytes + while index < total_length: + chunk = binary_data[index:index + chunk_size] + + # Reverse the data in the chunk (MSB to LSB within the line) + reversed_chunk = chunk[::-1] + + # Convert the reversed chunk to a hexadecimal string + hex_chunk = reversed_chunk.hex() + + # For the last chunk, if it's less than 64 bytes, pad zeros at the end + if len(chunk) < chunk_size: + pad_length = chunk_size - len(chunk) + # Pad with zeros at the end to make up to 64 bytes (128 hex digits) + hex_chunk = '00' * pad_length + hex_chunk + + # Add the hex_chunk to the list of lines + lines.append(hex_chunk) + index += chunk_size + + # Write the lines to the output text file + with open(output_text_file, 'w') as text_file: + for line in lines: + text_file.write(line + '\n') + + print(f"Hex data has been written to {output_text_file}") + + except FileNotFoundError: + print(f"Error: File {input_binary_file} not found.") + except Exception as e: + print(f"An error occurred: {e}") + +def convert_all_bin_to_hex(directory): + # Traverse the directory + for root, _, files in os.walk(directory): + for file in files: + if file.endswith('.bin'): + input_file = os.path.join(root, file) + output_file = f"{input_file.rsplit('.', 1)[0]}.hex" + binary_to_hex(input_file, output_file, chunk_size=64) + +def main(): + # Set up argument parser + parser = argparse.ArgumentParser(description="Convert all binaries in strings and save it to a text file.") + parser.add_argument( + '-i', '--input', + type=str, + default='.', + help="Path to the folder of binary files. Defaults to the current folder." + ) + # Parse arguments + args = parser.parse_args() + # Execute the task + convert_all_bin_to_hex(args.input) + +if __name__ == "__main__": + main() diff --git a/target/sim_chip/apps/copybin.py b/target/sim_chip/apps/copy_m_n_times.py similarity index 95% rename from target/sim_chip/apps/copybin.py rename to target/sim_chip/apps/copy_m_n_times.py index 8a106ca78..b5f77a502 100755 --- a/target/sim_chip/apps/copybin.py +++ b/target/sim_chip/apps/copy_m_n_times.py @@ -15,7 +15,7 @@ def copy_file_m_n_times(input_file, m, n): for x in range(m): for y in range(n): # Define the new file name - output_file = f"../bin/app_chip_{x}_{y}.bin" + output_file = f"../bin/app_chip_{x}_{y}.hex" # Copy the file to the new location with the new name shutil.copy(input_file, output_file) diff --git a/target/sim_chip/sim.mk b/target/sim_chip/sim.mk index 082418f32..c7fde0f90 100644 --- a/target/sim_chip/sim.mk +++ b/target/sim_chip/sim.mk @@ -54,14 +54,17 @@ SYN_BENDER += -t test -t synthesis ifeq ($(MEM_TYPE), exclude_tcsram) VSIM_BENDER += -t tech_cells_generic_exclude_tc_sram SYN_BENDER += -t tech_cells_generic_exclude_tc_sram + VCS_BENDER += -t tech_cells_generic_exclude_tc_sram endif ifeq ($(MEM_TYPE), prep_syn_mem) VSIM_BENDER += -t tech_cells_generic_exclude_tc_sram + VCS_BENDER += -t tech_cells_generic_exclude_tc_sram SYN_BENDER += -t tech_cells_generic_exclude_tc_sram SYN_BENDER += -t prep_syn_mem endif ifeq ($(SIM_TYPE), gate_level_sim) VSIM_BENDER += -t gate_level_sim + VCS_BENDER += -t gate_level_sim endif SYN_SOURCES = $(shell ${BENDER} script synopsys ${SYN_BENDER}) SYN_BUILDDIR := work-syn @@ -123,10 +126,14 @@ endif VLOGAN_FLAGS := -assert svaext VLOGAN_FLAGS += -assert disable_cover -VLOGAN_FLAGS += -full64 VLOGAN_FLAGS += -kdb -VHDLAN_FLAGS := -full64 +VLOGAN_FLAGS += -timescale=1ns/1ps +VLOGAN_FLAGS += -override_timescale=1ns/1ps +# VLOGAN_FLAGS += -work ./work-vcs VHDLAN_FLAGS += -kdb +VHDLAN_FLAGS += -timescale=1ns/1ps +VHDLAN_FLAGS += -override_timescale=1ns/1ps +# VHDLAN_FLAGS += -work ./work-vcs ############# # Verilator # @@ -175,15 +182,6 @@ define QUESTASIM @chmod +x $@.gui endef -####### -# VCS # -####### -$(VCS_BUILDDIR)/compile.sh: - mkdir -p $(VCS_BUILDDIR) - ${BENDER} script vcs ${VCS_BENDER} --vlog-arg="${VLOGAN_FLAGS}" --vcom-arg="${VHDLAN_FLAGS}" > $@ - chmod +x $@ - $(VCS_SEPP) $@ > $(VCS_BUILDDIR)/compile.log - ######## # Util # ######## diff --git a/target/sim_chip/testharness/testharness.sv.tpl b/target/sim_chip/testharness/testharness.sv.tpl index d0de7fb37..e08cd3bd3 100644 --- a/target/sim_chip/testharness/testharness.sv.tpl +++ b/target/sim_chip/testharness/testharness.sv.tpl @@ -27,98 +27,6 @@ module testharness logic rst_ni; logic rtc_i; - - // Task to load binary file into memory array - task automatic load_binary_to_hardware(input string filepath, - ref logic [511:0] wide_sram_buffer[SRAM_DEPTH-1:0]); - integer fd; - integer i; - reg [7:0] buffer[SRAM_WIDTH*SRAM_DEPTH]; - foreach (buffer[i]) buffer[i] = 0; // Zero out the buffer - - // Open the binary file - fd = $fopen(filepath, "rb"); - if (fd == 0) begin - $display("Failed to open binary file: %s", filepath); - $finish(-1); - end - - // Read the binary data into the buffer - $fread(buffer, fd); - $fclose(fd); - - // Assemble bytes into 512-bit words - for (i = 0; i < SRAM_DEPTH; i = i + 1) begin - wide_sram_buffer[i] = { - buffer[i*SRAM_WIDTH+63], - buffer[i*SRAM_WIDTH+62], - buffer[i*SRAM_WIDTH+61], - buffer[i*SRAM_WIDTH+60], - buffer[i*SRAM_WIDTH+59], - buffer[i*SRAM_WIDTH+58], - buffer[i*SRAM_WIDTH+57], - buffer[i*SRAM_WIDTH+56], - buffer[i*SRAM_WIDTH+55], - buffer[i*SRAM_WIDTH+54], - buffer[i*SRAM_WIDTH+53], - buffer[i*SRAM_WIDTH+52], - buffer[i*SRAM_WIDTH+51], - buffer[i*SRAM_WIDTH+50], - buffer[i*SRAM_WIDTH+49], - buffer[i*SRAM_WIDTH+48], - buffer[i*SRAM_WIDTH+47], - buffer[i*SRAM_WIDTH+46], - buffer[i*SRAM_WIDTH+45], - buffer[i*SRAM_WIDTH+44], - buffer[i*SRAM_WIDTH+43], - buffer[i*SRAM_WIDTH+42], - buffer[i*SRAM_WIDTH+41], - buffer[i*SRAM_WIDTH+40], - buffer[i*SRAM_WIDTH+39], - buffer[i*SRAM_WIDTH+38], - buffer[i*SRAM_WIDTH+37], - buffer[i*SRAM_WIDTH+36], - buffer[i*SRAM_WIDTH+35], - buffer[i*SRAM_WIDTH+34], - buffer[i*SRAM_WIDTH+33], - buffer[i*SRAM_WIDTH+32], - buffer[i*SRAM_WIDTH+31], - buffer[i*SRAM_WIDTH+30], - buffer[i*SRAM_WIDTH+29], - buffer[i*SRAM_WIDTH+28], - buffer[i*SRAM_WIDTH+27], - buffer[i*SRAM_WIDTH+26], - buffer[i*SRAM_WIDTH+25], - buffer[i*SRAM_WIDTH+24], - buffer[i*SRAM_WIDTH+23], - buffer[i*SRAM_WIDTH+22], - buffer[i*SRAM_WIDTH+21], - buffer[i*SRAM_WIDTH+20], - buffer[i*SRAM_WIDTH+19], - buffer[i*SRAM_WIDTH+18], - buffer[i*SRAM_WIDTH+17], - buffer[i*SRAM_WIDTH+16], - buffer[i*SRAM_WIDTH+15], - buffer[i*SRAM_WIDTH+14], - buffer[i*SRAM_WIDTH+13], - buffer[i*SRAM_WIDTH+12], - buffer[i*SRAM_WIDTH+11], - buffer[i*SRAM_WIDTH+10], - buffer[i*SRAM_WIDTH+9], - buffer[i*SRAM_WIDTH+8], - buffer[i*SRAM_WIDTH+7], - buffer[i*SRAM_WIDTH+6], - buffer[i*SRAM_WIDTH+5], - buffer[i*SRAM_WIDTH+4], - buffer[i*SRAM_WIDTH+3], - buffer[i*SRAM_WIDTH+2], - buffer[i*SRAM_WIDTH+1], - buffer[i*SRAM_WIDTH+0] - }; - end - $display("Binary file '%s' loaded into memory.", filepath); - endtask - // Chip finish signal integer chip_finish[${max(x)}:${min(x)}][${max(y)}:${min(y)}]; @@ -126,7 +34,12 @@ module testharness initial begin rtc_i = 0; clk_i = 0; - + // Load the binaries +% for i in x: +% for j in y: + i_occamy_${i}_${j}.i_spm_wide_cut.i_mem.i_mem.i_tc_sram.load_data("app_chip_${i}_${j}.hex"); +% endfor +% endfor // Reset the chip foreach (chip_finish[i,j]) begin chip_finish[i][j] = 0; @@ -138,12 +51,6 @@ module testharness #(10 + $urandom % 10); $display("Reset released at %tns", $time / 1000); rst_ni = 1; - // Load the binaries -% for i in x: -% for j in y: - load_binary_to_hardware("app_chip_${i}_${j}.bin", i_occamy_${i}_${j}.i_spm_wide_cut.i_mem.i_mem.i_tc_sram.sram); -% endfor -% endfor end always_comb begin