diff --git a/hw/occamy/occamy_chip.sv.tpl b/hw/occamy/occamy_chip.sv.tpl index 8d95d215..3c1e8e77 100644 --- a/hw/occamy/occamy_chip.sv.tpl +++ b/hw/occamy/occamy_chip.sv.tpl @@ -19,6 +19,15 @@ import ${name}_pkg::*; input logic test_mode_i, input chip_id_t chip_id_i, input logic [1:0] boot_mode_i, +% if occamy_cfg['hemaia_multichip']['single_chip'] is False: + // HeMAiA D2D AXI Interface + // Chiplet Requst to Router + output ${soc2router_bus.req_type()} soc2router_req_o, + input ${soc2router_bus.rsp_type()} soc2router_rsp_i, + // Router Requst to Chiplet + input ${router2soc_bus.req_type()} router2soc_req_i, + output ${router2soc_bus.rsp_type()} router2soc_rsp_o, +% endif // `uart` Interface output logic uart_tx_o, input logic uart_rx_i, @@ -160,6 +169,14 @@ import ${name}_pkg::*; .rtc_i (rtc_i), .test_mode_i (test_mode_i), .chip_id_i (chip_id_i), +% if occamy_cfg['hemaia_multichip']['single_chip'] is False: + // Chiplet Requst to Router + .soc2router_req_o, + .soc2router_rsp_i, + // Router Requst to Chiplet + .router2soc_req_i, + .router2soc_rsp_o, +% endif .boot_mode_i (boot_mode_i), .uart_tx_o (uart_tx_o), .uart_cts_ni (uart_cts_ni), diff --git a/hw/occamy/occamy_soc.sv.tpl b/hw/occamy/occamy_soc.sv.tpl index 19af2421..9159200a 100644 --- a/hw/occamy/occamy_soc.sv.tpl +++ b/hw/occamy/occamy_soc.sv.tpl @@ -8,6 +8,8 @@ // AUTOMATICALLY GENERATED by genoccamy.py; edit the script instead. <% + cuts_soc_to_router = occamy_cfg["cuts"]["soc_to_router"] + cuts_router_to_soc = occamy_cfg["cuts"]["router_to_soc"] cuts_narrow_to_quad = occamy_cfg["cuts"]["narrow_to_quad"] cuts_quad_to_narrow = occamy_cfg["cuts"]["quad_to_narrow"] cuts_wide_to_quad = occamy_cfg["cuts"]["wide_to_quad"] @@ -59,6 +61,16 @@ module ${name}_soc output ${soc_wide_xbar.out_spm_wide.req_type()} spm_axi_wide_req_o, input ${soc_wide_xbar.out_spm_wide.rsp_type()} spm_axi_wide_rsp_i, +% if occamy_cfg['hemaia_multichip']['single_chip'] is False: + // HeMAiA Multi-Chip AXI Interface + // Chiplet Requst to Router + output ${soc2router_bus.req_type()} soc2router_req_o, + input ${soc2router_bus.rsp_type()} soc2router_rsp_i, + // Router Requst to Chiplet + input ${router2soc_bus.req_type()} router2soc_req_i, + output ${router2soc_bus.rsp_type()} router2soc_rsp_o, +% endif + // SoC control register IO output logic [1:0] spm_narrow_rerror_o, output logic [1:0] spm_wide_rerror_o, @@ -80,6 +92,24 @@ module ${name}_soc ${module} +% if occamy_cfg['hemaia_multichip']['single_chip'] is False: + /////////////////////////////////////// + // Connections between SoC to Router // + /////////////////////////////////////// + <% + soc2router = soc_wide_xbar.out_hemaia_multichip \ + .change_iw(context, soc2router_bus.iw, "soc2router_iwc") \ + .cut(context, cuts_soc_to_router, name="soc2router_cut") + router2soc = soc_wide_xbar.in_hemaia_multichip \ + .change_iw(context, router2soc_bus.iw, "router2soc_iwc") \ + .cut(context, cuts_router_to_soc, name="router2soc_cut") + %> \ + assign soc2router_req_o = ${soc2router.req_name()}; + assign ${soc2router.rsp_name()} = soc2router_rsp_i; + assign ${router2soc.req_name()} = router2soc_req_i; + assign router2soc_rsp_o = ${router2soc.rsp_name()}; +% endif + /////////////////////////////////// // Connections between crossbars // /////////////////////////////////// @@ -233,7 +263,7 @@ module ${name}_soc // SPM WIDE // ////////////// <% wide_spm_mst = soc_wide_xbar.out_spm_wide \ - .cut(context, cuts_wide_conv_to_spm_wide) + .cut(context, cuts_wide_conv_to_spm_wide, name="wide_spm_cut") %>\ assign spm_axi_wide_req_o = ${wide_spm_mst.req_name()}; diff --git a/hw/occamy/occamy_top.sv.tpl b/hw/occamy/occamy_top.sv.tpl index 13c63dfc..7ad83048 100644 --- a/hw/occamy/occamy_top.sv.tpl +++ b/hw/occamy/occamy_top.sv.tpl @@ -72,6 +72,16 @@ module ${name}_top output ${soc_wide_xbar.out_spm_wide.req_type()} spm_axi_wide_req_o, input ${soc_wide_xbar.out_spm_wide.rsp_type()} spm_axi_wide_rsp_i, +% if occamy_cfg['hemaia_multichip']['single_chip'] is False: + // HeMAiA Multi-Chip AXI Interface + // Chiplet Requst to Router + output ${soc2router_bus.req_type()} soc2router_req_o, + input ${soc2router_bus.rsp_type()} soc2router_rsp_i, + // Router Requst to Chiplet + input ${router2soc_bus.req_type()} router2soc_req_i, + output ${router2soc_bus.rsp_type()} router2soc_rsp_o, +% endif + /// Chip specific control registers output ${soc_axi_lite_narrow_periph_xbar.out_chip_ctrl.req_type()} chip_ctrl_req_o, input ${soc_axi_lite_narrow_periph_xbar.out_chip_ctrl.rsp_type()} chip_ctrl_rsp_i, @@ -83,7 +93,6 @@ module ${name}_top ); <% - cuts_clint_cfg = occamy_cfg["cuts"]["periph_axi_lite_narrow_clint_cfg"] cuts_soc_ctrl_cfg = occamy_cfg["cuts"]["periph_axi_lite_narrow_soc_ctrl_cfg"] cuts_chip_ctrl_cfg = occamy_cfg["cuts"]["periph_axi_lite_narrow_chip_ctrl_cfg"] @@ -153,6 +162,14 @@ module ${name}_top .periph_axi_lite_narrow_rsp_i ( periph_regbus_soc2per_rsp ), .spm_axi_wide_req_o, .spm_axi_wide_rsp_i, +% if occamy_cfg['hemaia_multichip']['single_chip'] is False: + // Chiplet Requst to Router + .soc2router_req_o, + .soc2router_rsp_i, + // Router Requst to Chiplet + .router2soc_req_i, + .router2soc_rsp_o, +% endif .spm_narrow_rerror_o (spm_narrow_rerror), .spm_wide_rerror_o (spm_wide_rerror), .mtip_i ( mtip ), diff --git a/target/rtl/cfg/hemaia.hjson b/target/rtl/cfg/hemaia.hjson index 5f46d90b..312019ad 100755 --- a/target/rtl/cfg/hemaia.hjson +++ b/target/rtl/cfg/hemaia.hjson @@ -6,7 +6,9 @@ // Multi-chip configuration hemaia_multichip: { chip_id_width: 8, - single_chip: false, + router_to_soc_iw: 8, + soc_to_router_iw: 4, + single_chip: true, single_chip_id: 0, testbench_cfg: { // Emulate a four-chips configuration @@ -34,6 +36,8 @@ fall_through: false, }, cuts: { + soc_to_router: 1, + router_to_soc: 1, narrow_to_quad: 3, quad_to_narrow: 3, wide_to_quad: 3, @@ -116,7 +120,6 @@ }, clusters:[ "snax_KUL_cluster", - "snax_KUL_xdma_cluster", "snax_hypercorex_cluster", // "snax_dimc_cluster" ], diff --git a/target/rtl/cfg/hemaia_tapeout.hjson b/target/rtl/cfg/hemaia_chiplet.hjson similarity index 93% rename from target/rtl/cfg/hemaia_tapeout.hjson rename to target/rtl/cfg/hemaia_chiplet.hjson index 076d6b3f..df9303f0 100755 --- a/target/rtl/cfg/hemaia_tapeout.hjson +++ b/target/rtl/cfg/hemaia_chiplet.hjson @@ -6,7 +6,9 @@ // Multi-chip configuration hemaia_multichip: { chip_id_width: 8, - single_chip: true, + router_to_soc_iw: 8, + soc_to_router_iw: 4, + single_chip: false, single_chip_id: 0, testbench_cfg: { // Emulate a four-chips configuration @@ -34,6 +36,8 @@ fall_through: false, }, cuts: { + soc_to_router: 1, + router_to_soc: 1, narrow_to_quad: 3, quad_to_narrow: 3, wide_to_quad: 3, @@ -115,10 +119,9 @@ cfg_base_offset: 65536 // 0x10000 }, clusters:[ - "snax_cgra_cluster", - "snax_KUL_xdma_cluster", + "snax_KUL_cluster", "snax_hypercorex_cluster", - "snax_dimc_cluster" + // "snax_dimc_cluster" ], // peripherals diff --git a/target/rtl/cfg/hemaia_minimal.hjson b/target/rtl/cfg/hemaia_minimal.hjson deleted file mode 100755 index 3e47f735..00000000 --- a/target/rtl/cfg/hemaia_minimal.hjson +++ /dev/null @@ -1,203 +0,0 @@ -{ - bender_target: ["cv64a6_imafdc_sv39", "occamy"], - // Remote CFG, about to be removed - is_remote_quadrant: false, - remote_quadrants: [], - // Multi-chip configuration - hemaia_multichip: { - chip_id_width: 8, - single_chip: true, - single_chip_id: 0, - testbench_cfg: { - // Emulate a four-chips configuration - upper_left_coordinate: [0, 0], - lower_right_coordinate: [1, 1] - } - } - addr_width: 48, - data_width: 64, - // XBARs - wide_xbar: { - max_slv_trans: 64, - max_mst_trans: 64, - fall_through: false, - }, - quadrant_inter_xbar_slv_id_width_no_rocache: 3, - quadrant_inter_xbar: { - max_slv_trans: 64, - max_mst_trans: 64, - fall_through: false, - }, - narrow_xbar: { - max_slv_trans: 32, - max_mst_trans: 32, - fall_through: false, - }, - cuts: { - narrow_to_quad: 3, - quad_to_narrow: 3, - wide_to_quad: 3, - quad_to_wide: 3, - narrow_to_cva6: 2, - narrow_conv_to_spm_narrow_pre: 2, - narrow_conv_to_spm_narrow: 1, - narrow_and_pcie: 3, - narrow_and_wide: 1, - wide_conv_to_spm_wide: 3, - wide_to_wide_zero_mem: 0, - wide_to_hbm: 3, - wide_and_inter: 3, - wide_and_hbi: 3, - narrow_and_hbi: 3, - pre_to_hbmx: 3, - hbmx_to_hbm: 3, - atomic_adapter_narrow: 1, - atomic_adapter_narrow_wide: 1, - // Give some flexibility in peripheral xbar placement - periph_axi_lite_narrow: 2, - periph_axi_lite: 2, - periph_axi_lite_narrow_hbm_xbar_cfg: 2, - // Non-right-side chip peripherals - periph_axi_lite_narrow_hbm_cfg: 3, - periph_axi_lite_narrow_pcie_cfg: 3, - periph_axi_lite_narrow_chip_ctrl_cfg: 3, - periph_axi_lite_narrow_hbi_narrow_cfg: 3, - periph_axi_lite_narrow_hbi_wide_cfg: 3, - periph_axi_lite_narrow_bootrom_cfg: 3, - periph_axi_lite_narrow_fll_system_cfg: 3, - periph_axi_lite_narrow_fll_periph_cfg: 3, - periph_axi_lite_narrow_fll_hbm2e_cfg: 3, - // Right-side or latency-invariant chip peripherals - periph_axi_lite_narrow_soc_ctrl_cfg: 1, - periph_axi_lite_narrow_uart_cfg: 1, - periph_axi_lite_narrow_i2c_cfg: 1, - periph_axi_lite_narrow_gpio_cfg: 1, - periph_axi_lite_narrow_clint_cfg: 1, - periph_axi_lite_narrow_plic_cfg: 1, - periph_axi_lite_narrow_spim_cfg: 1, - periph_axi_lite_narrow_timer_cfg: 1, - }, - txns: { - wide_and_inter: 128, - wide_to_hbm: 128, - narrow_and_wide: 16, - rmq: 4, - }, - narrow_xbar_slv_id_width: 4, - narrow_xbar_user_width: 3, // clog2(total number of clusters) - nr_s1_quadrant: 1, - s1_quadrant: { - // number of pending transactions on the narrow/wide network - narrow_trans: 32, - wide_trans: 32, - // Disable for easier flow trials. - ro_cache_cfg: { - width: 1024, - count: 128, - sets: 2, - max_trans: 32, - address_regions: 4, - } - wide_xbar: { - max_slv_trans: 32, - max_mst_trans: 32, - fall_through: false, - }, - wide_xbar_slv_id_width: 3 - narrow_xbar: { - max_slv_trans: 8, - max_mst_trans: 8, - fall_through: false, - }, - narrow_xbar_slv_id_width: 4, - narrow_xbar_user_width: 3, // clog2(total number of clusters) - cfg_base_addr: 184549376, // 0x0b000000 - cfg_base_offset: 65536 // 0x10000 - }, - clusters:[ - "snax_KUL_xdma_cluster" - ], - - // peripherals - peripherals: { - rom: { - address: 16777216, // 0x0100_0000 - length: 131072, // 128 kiB 0x2_0000 - }, - clint: { - address: 67108864, // 0x0400_0000 - length: 1048576, // 1 MiB 0x10_0000 - }, - axi_lite_peripherals: [ - { - name: "debug", - address: 0, // 0x0000_0000 - length: 4096, // 4 kiB 0x1000 - }, - { - name: "spis", // Only Master port, no slave port - } - ], - axi_lite_narrow_peripherals: [ - { - name: "soc_ctrl", - address: 33554432, // 0x0200_0000 - length: 4096, // 4 kiB 0x1000 - }, - { - name: "uart", - address: 33562624, // 0x0200_2000 - length: 4096, // 4 kiB 0x1000 - }, - { - name: "gpio", - address: 33566720, // 0x0200_3000 - length: 4096, // 4 kiB 0x1000 - }, - { - name: "i2c", - address: 33570816, // 0x0200_4000 - length: 4096, // 4 kiB 0x1000 - }, - { - name: "chip_ctrl", - address: 33574912, // 0x0200_5000 - length: 4096, // 4 kiB 0x1000 - }, - { - name: "timer", - address: 33579008, // 0x0200_6000 - length: 4096, // 4 kiB 0x1000 - }, - { - name: "spim", - address: 50331648, // 0x0300_0000 - length: 131072, // 4 kiB 0x2_0000 - }, - { - name: "plic", - address: 201326592, // 0x0C00_0000 - length: 67108864, // 64 MiB 0x400_0000 - }, - ], - }, - // non-peripheral IPs - spm_narrow: { - address: 1879048192, // 0x7000_0000 - length: 131072, // 128 kiB 0x2_0000 - }, - spm_wide: { - address: 2147483648, // 0x8000_0000 - length: 1048576, // 1 MiB 0x10_0000 - }, - wide_zero_mem: { - address: 68719476736, // 0x10_0000_0000 - length: 8589934592, // 8 GiB 0x11_0000_0000 - }, - sys_idma_cfg: { - address: 285212672, // 0x1100_0000 - length: 65536, // 64 kiB 0x1_0000 - }, - // backup boot address - backup_boot_addr: 2147483648 // 0x8000_0000 -} diff --git a/target/rtl/cfg/hemaia_two_clusters.hjson b/target/rtl/cfg/hemaia_two_clusters.hjson deleted file mode 100755 index 90b461ba..00000000 --- a/target/rtl/cfg/hemaia_two_clusters.hjson +++ /dev/null @@ -1,205 +0,0 @@ -{ - bender_target: ["cv64a6_imafdc_sv39", "occamy"], - // Remote CFG, about to be removed - is_remote_quadrant: false, - remote_quadrants: [], - // Multi-chip configuration - hemaia_multichip: { - chip_id_width: 8, - single_chip: true, - single_chip_id: 0, - testbench_cfg: { - // Emulate a four-chips configuration - upper_left_coordinate: [0, 0], - lower_right_coordinate: [1, 1] - } - } - addr_width: 48, - data_width: 64, - // XBARs - wide_xbar: { - max_slv_trans: 64, - max_mst_trans: 64, - fall_through: false, - }, - quadrant_inter_xbar_slv_id_width_no_rocache: 3, - quadrant_inter_xbar: { - max_slv_trans: 64, - max_mst_trans: 64, - fall_through: false, - }, - narrow_xbar: { - max_slv_trans: 32, - max_mst_trans: 32, - fall_through: false, - }, - cuts: { - narrow_to_quad: 3, - quad_to_narrow: 3, - wide_to_quad: 3, - quad_to_wide: 3, - narrow_to_cva6: 2, - narrow_conv_to_spm_narrow_pre: 2, - narrow_conv_to_spm_narrow: 1, - narrow_and_pcie: 3, - narrow_and_wide: 1, - wide_conv_to_spm_wide: 3, - wide_to_wide_zero_mem: 0, - wide_to_hbm: 3, - wide_and_inter: 3, - wide_and_hbi: 3, - narrow_and_hbi: 3, - pre_to_hbmx: 3, - hbmx_to_hbm: 3, - atomic_adapter_narrow: 1, - atomic_adapter_narrow_wide: 1, - // Give some flexibility in peripheral xbar placement - periph_axi_lite_narrow: 2, - periph_axi_lite: 2, - periph_axi_lite_narrow_hbm_xbar_cfg: 2, - // Non-right-side chip peripherals - periph_axi_lite_narrow_hbm_cfg: 3, - periph_axi_lite_narrow_pcie_cfg: 3, - periph_axi_lite_narrow_chip_ctrl_cfg: 3, - periph_axi_lite_narrow_hbi_narrow_cfg: 3, - periph_axi_lite_narrow_hbi_wide_cfg: 3, - periph_axi_lite_narrow_bootrom_cfg: 3, - periph_axi_lite_narrow_fll_system_cfg: 3, - periph_axi_lite_narrow_fll_periph_cfg: 3, - periph_axi_lite_narrow_fll_hbm2e_cfg: 3, - // Right-side or latency-invariant chip peripherals - periph_axi_lite_narrow_soc_ctrl_cfg: 1, - periph_axi_lite_narrow_uart_cfg: 1, - periph_axi_lite_narrow_i2c_cfg: 1, - periph_axi_lite_narrow_gpio_cfg: 1, - periph_axi_lite_narrow_clint_cfg: 1, - periph_axi_lite_narrow_plic_cfg: 1, - periph_axi_lite_narrow_spim_cfg: 1, - periph_axi_lite_narrow_timer_cfg: 1, - }, - txns: { - wide_and_inter: 128, - wide_to_hbm: 128, - narrow_and_wide: 16, - rmq: 4, - }, - narrow_xbar_slv_id_width: 4, - narrow_xbar_user_width: 3, // clog2(total number of clusters) - nr_s1_quadrant: 1, - s1_quadrant: { - // number of pending transactions on the narrow/wide network - narrow_trans: 32, - wide_trans: 32, - // Disable for easier flow trials. - ro_cache_cfg: { - width: 1024, - count: 128, - sets: 2, - max_trans: 32, - address_regions: 4, - } - wide_xbar: { - max_slv_trans: 32, - max_mst_trans: 32, - fall_through: false, - }, - wide_xbar_slv_id_width: 3 - narrow_xbar: { - max_slv_trans: 8, - max_mst_trans: 8, - fall_through: false, - }, - narrow_xbar_slv_id_width: 4, - narrow_xbar_user_width: 3, // clog2(total number of clusters) - cfg_base_addr: 184549376, // 0x0b000000 - cfg_base_offset: 65536 // 0x10000 - }, - clusters:[ - "snax_KUL_cluster", - "snax_KUL_xdma_cluster" - ], - - // peripherals - peripherals: { - rom: { - address: 16777216, // 0x0100_0000 - length: 131072, // 128 kiB 0x2_0000 - }, - clint: { - address: 67108864, // 0x0400_0000 - length: 1048576, // 1 MiB 0x10_0000 - }, - axi_lite_peripherals: [ - { - name: "debug", - address: 0, // 0x0000_0000 - length: 4096, // 4 kiB 0x1000 - }, - { - name: "spis", // Only Master port, no slave port - } - ], - axi_lite_narrow_peripherals: [ - { - name: "soc_ctrl", - address: 33554432, // 0x0200_0000 - length: 4096, // 4 kiB 0x1000 - }, - { - name: "uart", - address: 33562624, // 0x0200_2000 - length: 4096, // 4 kiB 0x1000 - }, - { - name: "gpio", - address: 33566720, // 0x0200_3000 - length: 4096, // 4 kiB 0x1000 - }, - { - name: "i2c", - address: 33570816, // 0x0200_4000 - length: 4096, // 4 kiB 0x1000 - }, - { - name: "chip_ctrl", - address: 33574912, // 0x0200_5000 - length: 4096, // 4 kiB 0x1000 - }, - { - name: "timer", - address: 33579008, // 0x0200_6000 - length: 4096, // 4 kiB 0x1000 - }, - { - name: "spim", - address: 50331648, // 0x0300_0000 - length: 131072, // 4 kiB 0x2_0000 - }, - { - name: "plic", - address: 201326592, // 0x0C00_0000 - length: 67108864, // 64 MiB 0x400_0000 - }, - ], - }, - // non-peripheral IPs - spm_narrow: { - address: 1879048192, // 0x7000_0000 - length: 131072, // 128 kiB 0x2_0000 - }, - spm_wide: { - address: 2147483648, // 0x8000_0000 - length: 1048576, // 1 MiB 0x10_0000 - }, - wide_zero_mem: { - address: 68719476736, // 0x10_0000_0000 - length: 8589934592, // 8 GiB 0x11_0000_0000 - }, - sys_idma_cfg: { - address: 285212672, // 0x1100_0000 - length: 65536, // 64 kiB 0x1_0000 - }, - // backup boot address - backup_boot_addr: 2147483648 // 0x8000_0000 - -} diff --git a/util/occamygen/occamy.py b/util/occamygen/occamy.py index f0262f45..58cc986d 100644 --- a/util/occamygen/occamy.py +++ b/util/occamygen/occamy.py @@ -363,6 +363,14 @@ def am_connect_soc_wide_xbar_quad(am, am_soc_narrow_xbar, am_wide_xbar_quadrant_ ) return am_clusters +def am_connect_hemaia_multichip(am, am_soc_wide_xbar): + # Connect HeMAiA multichip master to wide AXI: This rule matches with no address condition, acting as a default port + am_hemaia_multichip = am.new_leaf( + "hemaia_multichip", + 0x000000000000, + 0x000000000000).attach_to(am_soc_wide_xbar) + return am_hemaia_multichip + def get_dts(occamy_cfg, am_clint, am_axi_lite_peripherals, am_axi_lite_narrow_peripherals): dts = device_tree.DeviceTree() @@ -404,7 +412,7 @@ def get_dts(occamy_cfg, am_clint, am_axi_lite_peripherals, am_axi_lite_narrow_pe return dts -def get_top_kwargs(occamy_cfg, cluster_generators, soc_axi_lite_narrow_periph_xbar, soc_wide_xbar, soc_narrow_xbar, name): +def get_top_kwargs(occamy_cfg, cluster_generators, soc_axi_lite_narrow_periph_xbar, soc_wide_xbar, soc_narrow_xbar, soc2router_bus, router2soc_bus, name): core_per_cluster_list = [cluster_generator.cfg["nr_cores"] for cluster_generator in cluster_generators] nr_cores_quadrant = sum(core_per_cluster_list) @@ -415,12 +423,14 @@ def get_top_kwargs(occamy_cfg, cluster_generators, soc_axi_lite_narrow_periph_xb "soc_axi_lite_narrow_periph_xbar": soc_axi_lite_narrow_periph_xbar, "soc_wide_xbar": soc_wide_xbar, "soc_narrow_xbar": soc_narrow_xbar, + "soc2router_bus": soc2router_bus, + "router2soc_bus": router2soc_bus, "cores": nr_s1_quadrants * nr_cores_quadrant + 1, } return top_kwargs -def get_soc_kwargs(occamy_cfg, cluster_generators, soc_narrow_xbar, soc_wide_xbar, util, name): +def get_soc_kwargs(occamy_cfg, cluster_generators, soc_narrow_xbar, soc_wide_xbar, soc2router_bus, router2soc_bus, util, name): core_per_cluster_list = [cluster_generator.cfg["nr_cores"] for cluster_generator in cluster_generators] nr_cores_quadrant = sum(core_per_cluster_list) @@ -431,6 +441,8 @@ def get_soc_kwargs(occamy_cfg, cluster_generators, soc_narrow_xbar, soc_wide_xba "occamy_cfg": occamy_cfg, "soc_narrow_xbar": soc_narrow_xbar, "soc_wide_xbar": soc_wide_xbar, + "soc2router_bus": soc2router_bus, + "router2soc_bus": router2soc_bus, "cores": nr_s1_quadrants * nr_cores_quadrant + 1, "nr_s1_quadrants": nr_s1_quadrants, "nr_cores_quadrant": nr_cores_quadrant @@ -661,7 +673,7 @@ def get_multichip_testharness_kwargs(occamy_cfg, name): } return testharness_kwargs -def get_chip_kwargs(soc_wide_xbar, soc_axi_lite_narrow_periph_xbar, occamy_cfg, cluster_generators, util, name): +def get_chip_kwargs(soc_wide_xbar, soc_axi_lite_narrow_periph_xbar, soc2router_bus, router2soc_bus, occamy_cfg, cluster_generators, util, name): core_per_cluster_list = [cluster_generator.cfg["nr_cores"] for cluster_generator in cluster_generators] nr_cores_quadrant = sum(core_per_cluster_list) @@ -672,6 +684,8 @@ def get_chip_kwargs(soc_wide_xbar, soc_axi_lite_narrow_periph_xbar, occamy_cfg, "occamy_cfg": occamy_cfg, "soc_wide_xbar": soc_wide_xbar, "soc_axi_lite_narrow_periph_xbar": soc_axi_lite_narrow_periph_xbar, + "soc2router_bus": soc2router_bus, + "router2soc_bus": router2soc_bus, "cores": nr_s1_quadrants * nr_cores_quadrant + 1 } return chip_kwargs diff --git a/util/occamygen/occamygen.py b/util/occamygen/occamygen.py index 9b1dceb5..e64cae9d 100755 --- a/util/occamygen/occamygen.py +++ b/util/occamygen/occamygen.py @@ -228,6 +228,9 @@ def main(): am_spm_narrow, am_sys_idma_cfg = occamy.am_connect_soc_narrow_xbar( am, am_soc_narrow_xbar, occamy_cfg) + + am_hemaia_multichip = occamy.am_connect_hemaia_multichip(am, am_soc_wide_xbar) + am_spm_wide, am_wide_zero_mem = occamy.am_connect_soc_wide_xbar_mem( am, am_soc_wide_xbar, occamy_cfg) @@ -314,6 +317,9 @@ def main(): soc_axi_lite_narrow_periph_xbar.add_output_entry("bootrom", am_bootrom) soc_axi_lite_narrow_periph_xbar.add_output_entry("clint", am_clint) + ################# + # SoC Wide Xbar # + ################# soc_wide_xbar = solder.AxiXbar( 48, 512, @@ -332,6 +338,9 @@ def main(): context="soc", node=am_soc_wide_xbar) + if occamy_cfg["hemaia_multichip"]["single_chip"] is False: + soc_wide_xbar.add_output_entry("hemaia_multichip", am_hemaia_multichip) + soc_wide_xbar.add_input("hemaia_multichip") soc_wide_xbar.add_output_entry("soc_narrow", am_soc_narrow_xbar) soc_wide_xbar.add_input("soc_narrow") soc_wide_xbar.add_input("sys_idma_mst") @@ -489,19 +498,42 @@ def main(): "ClusterAddressSpace") narrow_xbar_quadrant_s1.add_input("cluster_{}".format(i)) - # Generate the Verilog code. + # Generate the Verilog code for occamy_pkg.sv (Only include the definition related to xbars) solder.render() - cluster_cfgs = list() - nr_clusters = len(occamy_cfg["clusters"]) - for i in range(nr_clusters): - cluster_cfgs.append(cluster_generators[i].cfg) + + ############################################## + # Die2Die AXI Bus For Module I/O Declaration # + ############################################## + # As the Die2Die communication is irrelevant to XBars inside one chip, it is declared in the standalone way, so it should be placed below solder.render() + soc2router_bus = solder.AxiBus( + clk=soc_wide_xbar.clk, + rst=soc_wide_xbar.rst, + aw=soc_wide_xbar.aw, + dw=soc_wide_xbar.dw, + iw=occamy_cfg["hemaia_multichip"]["soc_to_router_iw"], + uw=soc_wide_xbar.uw, + name="soc2router_bus", + # declared=True + ) + + router2soc_bus = solder.AxiBus( + clk=soc_wide_xbar.clk, + rst=soc_wide_xbar.rst, + aw=soc_wide_xbar.aw, + dw=soc_wide_xbar.dw, + iw=occamy_cfg["hemaia_multichip"]["router_to_soc_iw"], + uw=soc_wide_xbar.uw, + name="router2soc_bus", + # declared=True + ) + # Emit the code. ############# # Top-Level # ############# if args.top_sv: top_kwargs = occamy.get_top_kwargs(occamy_cfg, cluster_generators, - soc_axi_lite_narrow_periph_xbar, soc_wide_xbar, soc_narrow_xbar, args.name) + soc_axi_lite_narrow_periph_xbar, soc_wide_xbar, soc_narrow_xbar, soc2router_bus, router2soc_bus, args.name) write_template(args.top_sv, outdir, fname="{}_top.sv".format(args.name), @@ -513,7 +545,7 @@ def main(): ########################### if args.soc_sv: soc_kwargs = occamy.get_soc_kwargs( - occamy_cfg, cluster_generators, soc_narrow_xbar, soc_wide_xbar, util, args.name) + occamy_cfg, cluster_generators, soc_narrow_xbar, soc_wide_xbar, soc2router_bus, router2soc_bus, util, args.name) write_template(args.soc_sv, outdir, module=solder.code_module['soc'], @@ -627,7 +659,7 @@ def main(): ######## if args.chip: chip_kwargs = occamy.get_chip_kwargs( - soc_wide_xbar, soc_axi_lite_narrow_periph_xbar, occamy_cfg, cluster_generators, util, args.name) + soc_wide_xbar, soc_axi_lite_narrow_periph_xbar, soc2router_bus, router2soc_bus, occamy_cfg, cluster_generators, util, args.name) write_template(args.chip, outdir, **chip_kwargs) ########