diff --git a/hw/occamy/occamy_chip.sv.tpl b/hw/occamy/occamy_chip.sv.tpl
index 85664a95..8d95d215 100644
--- a/hw/occamy/occamy_chip.sv.tpl
+++ b/hw/occamy/occamy_chip.sv.tpl
@@ -78,6 +78,7 @@ import ${name}_pkg::*;
     .clk_i (${soc_wide_xbar.out_spm_wide.clk}),
     .rst_ni (${soc_wide_xbar.out_spm_wide.rst}),
     .busy_o (),
+    .test_i ('0),
     .axi_req_i (${ram_axi.req_name()}),
     .axi_resp_o (${ram_axi.rsp_name()}),
     .mem_req_o (spm_wide_req),
diff --git a/target/rtl/cfg/hemaia.hjson b/target/rtl/cfg/hemaia.hjson
index a5eb0a7c..5f46d90b 100755
--- a/target/rtl/cfg/hemaia.hjson
+++ b/target/rtl/cfg/hemaia.hjson
@@ -6,12 +6,12 @@
     // Multi-chip configuration
     hemaia_multichip: {
       chip_id_width: 8, 
-      single_chip: true,
+      single_chip: false,
       single_chip_id: 0, 
       testbench_cfg: {
         // Emulate a four-chips configuration
         upper_left_coordinate: [0, 0],
-        lower_right_coordinate: [2, 2]
+        lower_right_coordinate: [1, 1]
       }
     }
     addr_width: 48,
diff --git a/target/rtl/cfg/hemaia_minimal.hjson b/target/rtl/cfg/hemaia_minimal.hjson
index aadd5cf0..3e47f735 100755
--- a/target/rtl/cfg/hemaia_minimal.hjson
+++ b/target/rtl/cfg/hemaia_minimal.hjson
@@ -7,7 +7,12 @@
     hemaia_multichip: {
       chip_id_width: 8, 
       single_chip: true,
-      single_chip_id: 0
+      single_chip_id: 0, 
+      testbench_cfg: {
+        // Emulate a four-chips configuration
+        upper_left_coordinate: [0, 0],
+        lower_right_coordinate: [1, 1]
+      }
     }
     addr_width: 48,
     data_width: 64,
diff --git a/target/rtl/cfg/hemaia_tapeout.hjson b/target/rtl/cfg/hemaia_tapeout.hjson
index dbd4878c..076d6b3f 100755
--- a/target/rtl/cfg/hemaia_tapeout.hjson
+++ b/target/rtl/cfg/hemaia_tapeout.hjson
@@ -5,7 +5,14 @@
     remote_quadrants: [],
     // Multi-chip configuration
     hemaia_multichip: {
-      chip_id_width: 8
+      chip_id_width: 8, 
+      single_chip: true,
+      single_chip_id: 0, 
+      testbench_cfg: {
+        // Emulate a four-chips configuration
+        upper_left_coordinate: [0, 0],
+        lower_right_coordinate: [1, 1]
+      }
     }
     addr_width: 48,
     data_width: 64,
diff --git a/target/rtl/cfg/hemaia_two_clusters.hjson b/target/rtl/cfg/hemaia_two_clusters.hjson
index 6c922208..90b461ba 100755
--- a/target/rtl/cfg/hemaia_two_clusters.hjson
+++ b/target/rtl/cfg/hemaia_two_clusters.hjson
@@ -7,7 +7,12 @@
     hemaia_multichip: {
       chip_id_width: 8, 
       single_chip: true,
-      single_chip_id: 0
+      single_chip_id: 0, 
+      testbench_cfg: {
+        // Emulate a four-chips configuration
+        upper_left_coordinate: [0, 0],
+        lower_right_coordinate: [1, 1]
+      }
     }
     addr_width: 48,
     data_width: 64,
diff --git a/target/sim_chip/Makefile b/target/sim_chip/Makefile
index 00e91ab7..62b3841d 100644
--- a/target/sim_chip/Makefile
+++ b/target/sim_chip/Makefile
@@ -147,14 +147,14 @@ clean-apps:
 
 TARGET_RTL = $(ROOT)/target/rtl
 
-CFG = $(TARGET_RTL)/cfg/occamy_cfg/lru.hjson
+CFG = $(TARGET_RTL)/cfg/lru.hjson
 
 OCCAMYGEN ?= $(ROOT)/util/occamygen/occamygen.py
 
 $(CFG):
 	@# If the LRU config file doesn't exist, we use the default config.
 	@if [ ! -e $@ ] ; then \
-		DEFAULT_CFG="$(TARGET_RTL)/cfg/occamy_cfg/hemaia.hjson"; \
+		DEFAULT_CFG="$(TARGET_RTL)/cfg/hemaia.hjson"; \
 		echo "Using default config file: $$DEFAULT_CFG"; \
 		cp $$DEFAULT_CFG $@; \
 	fi
diff --git a/target/sim_chip/testharness/testharness.sv.tpl b/target/sim_chip/testharness/testharness.sv.tpl
index 6088c593..d0de7fb3 100644
--- a/target/sim_chip/testharness/testharness.sv.tpl
+++ b/target/sim_chip/testharness/testharness.sv.tpl
@@ -141,7 +141,7 @@ module testharness
     // Load the binaries
 % for i in x:
 %   for j in y:
-    load_binary_to_hardware("app_chip_${i}_${j}.bin", i_occamy_${i}_${j}.i_spm_wide_cut.i_mem.i_tc_sram.sram);
+    load_binary_to_hardware("app_chip_${i}_${j}.bin", i_occamy_${i}_${j}.i_spm_wide_cut.i_mem.i_mem.i_tc_sram.sram);
 %   endfor
 % endfor
   end
@@ -213,7 +213,7 @@ module testharness
       .rtc_i,
       .chip_id_i(8'h${i_hex_string}${j_hex_string}),
       .test_mode_i(1'b0),
-      .boot_mode_i(0),
+      .boot_mode_i('0),
       .uart_tx_o(tx_${i}_${j}),
       .uart_rx_i(rx_${i}_${j}),
       .uart_rts_no(),
@@ -226,12 +226,11 @@ module testharness
       .jtag_tms_i('0),
       .jtag_tdi_i('0),
       .jtag_tdo_o(),
-      .i2c_sda_io(),
-      .i2c_scl_io(),
-      .spim_sck_o(),
-      .spim_csb_o(),
-      .spim_sd_io(),
-      .ext_irq_i('0)
+      .spis_sd_i('1),
+      .spis_sd_en_o(),
+      .spis_sd_o(),
+      .spis_csb_i('1),
+      .spis_sck_i('0)
   );
 
   uartdpi #(
@@ -247,14 +246,14 @@ module testharness
   );
 
   // Chip Status Monitor Block
-  always @(i_occamy_${i}_${j}.i_spm_wide_cut.i_mem.i_tc_sram.sram[SRAM_DEPTH-1][(SRAM_WIDTH*8-1)-:32]) begin
-    if (i_occamy_${i}_${j}.i_spm_wide_cut.i_mem.i_tc_sram.sram[SRAM_DEPTH-1][(SRAM_WIDTH*8-1)-:32] != 0) begin
-      if (i_occamy_${i}_${j}.i_spm_wide_cut.i_mem.i_tc_sram.sram[SRAM_DEPTH-1][(SRAM_WIDTH*8-1)-:32] == 32'd1) begin
+  always @(i_occamy_${i}_${j}.i_spm_wide_cut.i_mem.i_mem.i_tc_sram.sram[SRAM_DEPTH-1][(SRAM_WIDTH*8-1)-:32]) begin
+    if (i_occamy_${i}_${j}.i_spm_wide_cut.i_mem.i_mem.i_tc_sram.sram[SRAM_DEPTH-1][(SRAM_WIDTH*8-1)-:32] != 0) begin
+      if (i_occamy_${i}_${j}.i_spm_wide_cut.i_mem.i_mem.i_tc_sram.sram[SRAM_DEPTH-1][(SRAM_WIDTH*8-1)-:32] == 32'd1) begin
         $display("Simulation of chip_${i}_${j} is finished at %tns", $time / 1000);
         chip_finish[${i}][${j}] = 1;
       end else begin
         $error("Simulation of chip_${i}_${j} is finished with errors %d at %tns",
-               i_occamy_${i}_${j}.i_spm_wide_cut.i_mem.i_tc_sram.sram[SRAM_DEPTH-1][(SRAM_WIDTH*8-1)-:32],
+               i_occamy_${i}_${j}.i_spm_wide_cut.i_mem.i_mem.i_tc_sram.sram[SRAM_DEPTH-1][(SRAM_WIDTH*8-1)-:32],
                $time / 1000);
         chip_finish[${i}][${j}] = -1;
       end