From 0eafe4fd8cf5b905be3b9c7e121e6f3331dbc425 Mon Sep 17 00:00:00 2001
From: IveanEx <yunhao.deng@kuleuven.be>
Date: Mon, 25 Nov 2024 23:09:49 +0100
Subject: [PATCH] Fix bugs in multichip testbench

---
 Bender.local             | 2 +-
 Bender.yml               | 2 +-
 target/sim_chip/Makefile | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/Bender.local b/Bender.local
index f384c404..cbbca5f2 100644
--- a/Bender.local
+++ b/Bender.local
@@ -6,4 +6,4 @@ overrides:
   axi:                { path: hw/vendor/pulp_platform_axi                                             }
   common_cells:       { git: https://github.com/pulp-platform/common_cells.git,       version: 1.31.1 }
   register_interface: { git: https://github.com/pulp-platform/register_interface.git, version:  0.4.2 }
-  tech_cells_generic:     { git:  https://github.com/KULeuven-MICAS/tech_cells_generic.git, version: 0.2.15 }
+  tech_cells_generic:     { git:  https://github.com/KULeuven-MICAS/tech_cells_generic.git, version: 0.2.16 }
diff --git a/Bender.yml b/Bender.yml
index d037737b..7454ded8 100644
--- a/Bender.yml
+++ b/Bender.yml
@@ -30,7 +30,7 @@ dependencies:
   opentitan_peripherals:  { path: hw/vendor/pulp_platform_opentitan_peripherals                             }
   register_interface:     { git:  https://github.com/pulp-platform/register_interface.git, version: 0.3.8   }
   snitch_cluster:         { git:  https://github.com/KULeuven-MICAS/snax_cluster.git,      rev:        main }
-  tech_cells_generic:     { git:  https://github.com/KULeuven-MICAS/tech_cells_generic.git, version: 0.2.15 }
+  tech_cells_generic:     { git:  https://github.com/KULeuven-MICAS/tech_cells_generic.git, version: 0.2.16 }
   cluster_icache:         { git:  https://github.com/KULeuven-MICAS/cluster_icache.git,     rev:  main }
   hemaia_axi_spi_slave:    { git: https://github.com/KULeuven-MICAS/hemaia_axi_spi_slave.git, rev: main }
 
diff --git a/target/sim_chip/Makefile b/target/sim_chip/Makefile
index 7b994fb4..95213224 100644
--- a/target/sim_chip/Makefile
+++ b/target/sim_chip/Makefile
@@ -189,7 +189,7 @@ testharness/testharness.sv: testharness/testharness.sv.tpl $(CFG)
 # Verilator #
 #############
 
-${VLT_AR}: ${VLT_SOURCES} ${TB_SRCS} testharness/testharness.sv
+${VLT_AR}: testharness/testharness.sv
 	$(call VERILATE,testharness)
 
 # Quick sanity check, not really meant for simulation.