From 0e2747f0c8ae84826e927c5d82c21cd477899bd8 Mon Sep 17 00:00:00 2001 From: Yunhao Deng Date: Wed, 16 Oct 2024 14:23:23 +0200 Subject: [PATCH] fix chip connection (#65) * Fix Chip Connection * Update HeMAiA FPGA Config --- hw/occamy/occamy_chip.sv.tpl | 6 +- target/fpga/occamy_vcu128_impl.xdc | 66 +++++++++---------- .../hemaia_system/hemaia_system_vcu128_bd.tcl | 45 +------------ .../hemaia_system_vcu128_impl.xdc | 33 ---------- .../hemaia_system/hemaia_system_vpk180_bd.tcl | 35 ---------- .../hemaia_system_vpk180_impl.xdc | 43 ------------ 6 files changed, 36 insertions(+), 192 deletions(-) diff --git a/hw/occamy/occamy_chip.sv.tpl b/hw/occamy/occamy_chip.sv.tpl index 98f430f4..85664a95 100644 --- a/hw/occamy/occamy_chip.sv.tpl +++ b/hw/occamy/occamy_chip.sv.tpl @@ -157,9 +157,9 @@ import ${name}_pkg::*; .clk_periph_i (clk_periph_i), .rst_periph_ni (rst_periph_ni), .rtc_i (rtc_i), - .test_mode_i (1'b0), - .chip_id_i (chip_id), - .boot_mode_i ('0), + .test_mode_i (test_mode_i), + .chip_id_i (chip_id_i), + .boot_mode_i (boot_mode_i), .uart_tx_o (uart_tx_o), .uart_cts_ni (uart_cts_ni), .uart_rts_no (uart_rts_no), diff --git a/target/fpga/occamy_vcu128_impl.xdc b/target/fpga/occamy_vcu128_impl.xdc index c6a9c062..e154d259 100644 --- a/target/fpga/occamy_vcu128_impl.xdc +++ b/target/fpga/occamy_vcu128_impl.xdc @@ -16,38 +16,38 @@ set_property IOSTANDARD LVCMOS18 [get_ports uart_cts_ni] set_property PACKAGE_PIN BP23 [get_ports uart_rts_no] set_property IOSTANDARD LVCMOS18 [get_ports uart_rts_no] -# Six-wires SPIx4 -# LA10_P - B23 -set_property PACKAGE_PIN B23 [get_ports spim_sd_io[0]] -set_property IOSTANDARD LVCMOS18 [get_ports spim_sd_io[0]] -# LA10_N - A23 -set_property PACKAGE_PIN A23 [get_ports spim_sd_io[1]] -set_property IOSTANDARD LVCMOS18 [get_ports spim_sd_io[1]] -# LA11_P - B26 -set_property PACKAGE_PIN B26 [get_ports spim_sd_io[2]] -set_property IOSTANDARD LVCMOS18 [get_ports spim_sd_io[2]] -# LA11_N - B25 -set_property PACKAGE_PIN B25 [get_ports spim_sd_io[3]] -set_property IOSTANDARD LVCMOS18 [get_ports spim_sd_io[3]] -# LA12_P - J22 -set_property PACKAGE_PIN J22 [get_ports spim_csb_o[0]] -set_property IOSTANDARD LVCMOS18 [get_ports spim_csb_o[0]] -# LA12_N - H22 -set_property PACKAGE_PIN H22 [get_ports spim_csb_o[1]] -set_property IOSTANDARD LVCMOS18 [get_ports spim_csb_o[1]] -# LA13_P - A25 -set_property PACKAGE_PIN A25 [get_ports spim_sck_o] -set_property IOSTANDARD LVCMOS18 [get_ports spim_sck_o] - -create_clock -period 20.000 -name spi_m_sck [get_ports spim_sck_o] - -# Two-wires I2C -# LA14_P - C23 -set_property PACKAGE_PIN C23 [get_ports i2c_sda_io] -set_property IOSTANDARD LVCMOS18 [get_ports i2c_sda_io] -# LA14_N - B22 -set_property PACKAGE_PIN B22 [get_ports i2c_scl_io] -set_property IOSTANDARD LVCMOS18 [get_ports i2c_scl_io] +# # Six-wires SPIx4 +# # LA10_P - B23 +# set_property PACKAGE_PIN B23 [get_ports spim_sd_io[0]] +# set_property IOSTANDARD LVCMOS18 [get_ports spim_sd_io[0]] +# # LA10_N - A23 +# set_property PACKAGE_PIN A23 [get_ports spim_sd_io[1]] +# set_property IOSTANDARD LVCMOS18 [get_ports spim_sd_io[1]] +# # LA11_P - B26 +# set_property PACKAGE_PIN B26 [get_ports spim_sd_io[2]] +# set_property IOSTANDARD LVCMOS18 [get_ports spim_sd_io[2]] +# # LA11_N - B25 +# set_property PACKAGE_PIN B25 [get_ports spim_sd_io[3]] +# set_property IOSTANDARD LVCMOS18 [get_ports spim_sd_io[3]] +# # LA12_P - J22 +# set_property PACKAGE_PIN J22 [get_ports spim_csb_o[0]] +# set_property IOSTANDARD LVCMOS18 [get_ports spim_csb_o[0]] +# # LA12_N - H22 +# set_property PACKAGE_PIN H22 [get_ports spim_csb_o[1]] +# set_property IOSTANDARD LVCMOS18 [get_ports spim_csb_o[1]] +# # LA13_P - A25 +# set_property PACKAGE_PIN A25 [get_ports spim_sck_o] +# set_property IOSTANDARD LVCMOS18 [get_ports spim_sck_o] + +# create_clock -period 20.000 -name spi_m_sck [get_ports spim_sck_o] + +# # Two-wires I2C +# # LA14_P - C23 +# set_property PACKAGE_PIN C23 [get_ports i2c_sda_io] +# set_property IOSTANDARD LVCMOS18 [get_ports i2c_sda_io] +# # LA14_N - B22 +# set_property PACKAGE_PIN B22 [get_ports i2c_scl_io] +# set_property IOSTANDARD LVCMOS18 [get_ports i2c_scl_io] # Six-wires SPIx4 (Slave) # LA15_N - H20 @@ -145,5 +145,3 @@ set_property BITSTREAM.CONFIG.SPI_FALL_EDGE Yes [current_design] set_property BITSTREAM.CONFIG.CONFIGRATE 127.5 [current_design] set_property CONFIG_VOLTAGE 1.8 [current_design] set_property CFGBVS GND [current_design] - - diff --git a/target/fpga_chip/hemaia_system/hemaia_system_vcu128_bd.tcl b/target/fpga_chip/hemaia_system/hemaia_system_vcu128_bd.tcl index ec0fafc6..750791d4 100644 --- a/target/fpga_chip/hemaia_system/hemaia_system_vcu128_bd.tcl +++ b/target/fpga_chip/hemaia_system/hemaia_system_vcu128_bd.tcl @@ -223,12 +223,7 @@ proc create_root_design { parentCell } { set jtag_tck_i [ create_bd_port -dir I -type clk -freq_hz 5000000 jtag_tck_i ] set uart_cts_ni [ create_bd_port -dir I uart_cts_ni ] set uart_rts_no [ create_bd_port -dir O uart_rts_no ] - set spim_sck_o [ create_bd_port -dir O spim_sck_o ] set gpio_d_o [ create_bd_port -dir O -from 7 -to 0 gpio_d_o ] - set spim_csb_o [ create_bd_port -dir O -from 1 -to 0 spim_csb_o ] - set i2c_sda_io [ create_bd_port -dir IO i2c_sda_io ] - set i2c_scl_io [ create_bd_port -dir IO i2c_scl_io ] - set spim_sd_io [ create_bd_port -dir IO -from 3 -to 0 spim_sd_io ] set spis_sck_i [ create_bd_port -dir I spis_sck_i ] set spis_csb_i [ create_bd_port -dir I spis_csb_i ] set spis_sd_io [ create_bd_port -dir IO -from 3 -to 0 spis_sd_io ] @@ -326,14 +321,6 @@ proc create_root_design { parentCell } { # Create instance: occamy_chip, and set properties set occamy_chip [ create_bd_cell -type ip -vlnv MICAS_KUL:user:occamy_chip:1.0 occamy_chip ] - # Create instance: spim_iobuf, and set properties - set spim_iobuf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 spim_iobuf ] - set_property -dict [list \ - CONFIG.C_BUF_TYPE {IOBUF} \ - CONFIG.C_SIZE {4} \ - ] $spim_iobuf - - # Create instance: spis_iobuf, and set properties set spis_iobuf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 spis_iobuf ] set_property -dict [list \ @@ -342,37 +329,16 @@ proc create_root_design { parentCell } { ] $spis_iobuf - # Create instance: i2c_sda_iobuf, and set properties - set i2c_sda_iobuf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 i2c_sda_iobuf ] - set_property -dict [list \ - CONFIG.C_BUF_TYPE {IOBUF} \ - CONFIG.C_SIZE {1} \ - ] $i2c_sda_iobuf - - - # Create instance: i2c_scl_iobuf, and set properties - set i2c_scl_iobuf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 i2c_scl_iobuf ] - set_property -dict [list \ - CONFIG.C_BUF_TYPE {IOBUF} \ - CONFIG.C_SIZE {1} \ - ] $i2c_scl_iobuf - - # Create interface connections connect_bd_intf_net -intf_net default_100mhz_clk_1 [get_bd_intf_ports default_100mhz_clk] [get_bd_intf_pins clk_wiz/CLK_IN1_D] # Create port connections connect_bd_net -net Net [get_bd_ports spis_sd_io] [get_bd_pins spis_iobuf/IOBUF_IO_IO] - connect_bd_net -net Net1 [get_bd_ports i2c_sda_io] [get_bd_pins i2c_sda_iobuf/IOBUF_IO_IO] - connect_bd_net -net Net2 [get_bd_ports i2c_scl_io] [get_bd_pins i2c_scl_iobuf/IOBUF_IO_IO] - connect_bd_net -net Net3 [get_bd_ports spim_sd_io] [get_bd_pins spim_iobuf/IOBUF_IO_IO] connect_bd_net -net bootmode [get_bd_pins vio_sys/probe_out1] [get_bd_pins occamy_chip/boot_mode_i] connect_bd_net -net c_high_dout [get_bd_pins c_high/dout] [get_bd_ports vref_vdd_o] [get_bd_pins occamy_chip/jtag_trst_ni] connect_bd_net -net clk_wiz_clk_core [get_bd_pins clk_wiz/clk_core] [get_bd_pins vio_sys/clk] [get_bd_pins occamy_chip/clk_i] [get_bd_pins occamy_chip/clk_periph_i] connect_bd_net -net clk_wiz_clk_rtc [get_bd_pins clk_wiz/clk_rtc] [get_bd_pins occamy_chip/rtc_i] - connect_bd_net -net const_low_dout [get_bd_pins c_low/dout] [get_bd_ports vref_gnd_o] [get_bd_pins occamy_chip/test_mode_i] [get_bd_pins occamy_chip/ext_irq_i] [get_bd_pins occamy_chip/gpio_d_i] - connect_bd_net -net i2c_scl_iobuf_IOBUF_IO_O [get_bd_pins i2c_sda_iobuf/IOBUF_IO_O] [get_bd_pins occamy_chip/i2c_sda_i] - connect_bd_net -net i2c_scl_iobuf_IOBUF_IO_O1 [get_bd_pins i2c_scl_iobuf/IOBUF_IO_O] [get_bd_pins occamy_chip/i2c_scl_i] + connect_bd_net -net const_low_dout [get_bd_pins c_low/dout] [get_bd_ports vref_gnd_o] [get_bd_pins occamy_chip/test_mode_i] [get_bd_pins occamy_chip/gpio_d_i] connect_bd_net -net jtag_tck_i_1 [get_bd_ports jtag_tck_i] [get_bd_pins occamy_chip/jtag_tck_i] set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_nets jtag_tck_i_1] connect_bd_net -net jtag_tdi_i_1 [get_bd_ports jtag_tdi_i] [get_bd_pins occamy_chip/jtag_tdi_i] @@ -382,25 +348,16 @@ proc create_root_design { parentCell } { connect_bd_net -net occamy_chip_0_gpio_d_o [get_bd_pins occamy_chip/gpio_d_o] [get_bd_pins xlslice_1/Din] connect_bd_net -net occamy_chip_0_jtag_tdo_o [get_bd_pins occamy_chip/jtag_tdo_o] [get_bd_ports jtag_tdo_o] set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_nets occamy_chip_0_jtag_tdo_o] - connect_bd_net -net occamy_chip_0_spim_csb_o [get_bd_pins occamy_chip/spim_csb_o] [get_bd_ports spim_csb_o] - connect_bd_net -net occamy_chip_0_spim_sck_o [get_bd_pins occamy_chip/spim_sck_o] [get_bd_ports spim_sck_o] connect_bd_net -net occamy_chip_0_uart_rts_no [get_bd_pins occamy_chip/uart_rts_no] [get_bd_ports uart_rts_no] set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_nets occamy_chip_0_uart_rts_no] connect_bd_net -net occamy_chip_0_uart_tx_o [get_bd_pins occamy_chip/uart_tx_o] [get_bd_ports uart_tx_o] set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_nets occamy_chip_0_uart_tx_o] - connect_bd_net -net occamy_chip_i2c_scl_en_o [get_bd_pins occamy_chip/i2c_scl_en_o] [get_bd_pins i2c_scl_iobuf/IOBUF_IO_T] - connect_bd_net -net occamy_chip_i2c_scl_o [get_bd_pins occamy_chip/i2c_scl_o] [get_bd_pins i2c_scl_iobuf/IOBUF_IO_I] - connect_bd_net -net occamy_chip_i2c_sda_en_o [get_bd_pins occamy_chip/i2c_sda_en_o] [get_bd_pins i2c_sda_iobuf/IOBUF_IO_T] - connect_bd_net -net occamy_chip_i2c_sda_o [get_bd_pins occamy_chip/i2c_sda_o] [get_bd_pins i2c_sda_iobuf/IOBUF_IO_I] - connect_bd_net -net occamy_chip_spim_sd_en_o [get_bd_pins occamy_chip/spim_sd_en_o] [get_bd_pins spim_iobuf/IOBUF_IO_T] - connect_bd_net -net occamy_chip_spim_sd_o [get_bd_pins occamy_chip/spim_sd_o] [get_bd_pins spim_iobuf/IOBUF_IO_I] connect_bd_net -net occamy_chip_spis_sd_en_o [get_bd_pins occamy_chip/spis_sd_en_o] [get_bd_pins spis_iobuf/IOBUF_IO_T] connect_bd_net -net occamy_chip_spis_sd_o [get_bd_pins occamy_chip/spis_sd_o] [get_bd_pins spis_iobuf/IOBUF_IO_I] connect_bd_net -net occamy_rst [get_bd_pins rst_or_core/Res] [get_bd_pins rst_core_inv/Op1] connect_bd_net -net occamy_rstn [get_bd_pins rst_core_inv/Res] [get_bd_pins occamy_chip/rst_ni] [get_bd_pins occamy_chip/rst_periph_ni] connect_bd_net -net reset [get_bd_pins vio_sys/probe_out0] [get_bd_pins concat_rst_core/In1] connect_bd_net -net reset_button [get_bd_ports reset] [get_bd_pins concat_rst_core/In0] - connect_bd_net -net spim_iobuf_IOBUF_IO_O [get_bd_pins spim_iobuf/IOBUF_IO_O] [get_bd_pins occamy_chip/spim_sd_i] connect_bd_net -net spis_csb_i_0_1 [get_bd_ports spis_csb_i] [get_bd_pins occamy_chip/spis_csb_i] connect_bd_net -net spis_iobuf_IOBUF_IO_O [get_bd_pins spis_iobuf/IOBUF_IO_O] [get_bd_pins occamy_chip/spis_sd_i] connect_bd_net -net spis_sck_i_0_1 [get_bd_ports spis_sck_i] [get_bd_pins occamy_chip/spis_sck_i] diff --git a/target/fpga_chip/hemaia_system/hemaia_system_vcu128_impl.xdc b/target/fpga_chip/hemaia_system/hemaia_system_vcu128_impl.xdc index 932427f6..ad55bc5a 100644 --- a/target/fpga_chip/hemaia_system/hemaia_system_vcu128_impl.xdc +++ b/target/fpga_chip/hemaia_system/hemaia_system_vcu128_impl.xdc @@ -33,39 +33,6 @@ set_property PULLUP TRUE [get_ports uart_cts_ni] set_property PACKAGE_PIN D21 [get_ports uart_rts_no] set_property IOSTANDARD LVCMOS18 [get_ports uart_rts_no] -# Six-wires SPIx4 (Master) -# LA10_P - B23 -set_property PACKAGE_PIN B23 [get_ports spim_sd_io[0]] -set_property IOSTANDARD LVCMOS18 [get_ports spim_sd_io[0]] -# LA10_N - A23 -set_property PACKAGE_PIN A23 [get_ports spim_sd_io[1]] -set_property IOSTANDARD LVCMOS18 [get_ports spim_sd_io[1]] -# LA11_P - B26 -set_property PACKAGE_PIN B26 [get_ports spim_sd_io[2]] -set_property IOSTANDARD LVCMOS18 [get_ports spim_sd_io[2]] -# LA11_N - B25 -set_property PACKAGE_PIN B25 [get_ports spim_sd_io[3]] -set_property IOSTANDARD LVCMOS18 [get_ports spim_sd_io[3]] -# LA12_P - J22 -set_property PACKAGE_PIN J22 [get_ports spim_csb_o[0]] -set_property IOSTANDARD LVCMOS18 [get_ports spim_csb_o[0]] -# LA12_N - H22 -set_property PACKAGE_PIN H22 [get_ports spim_csb_o[1]] -set_property IOSTANDARD LVCMOS18 [get_ports spim_csb_o[1]] -# LA13_P - A25 -set_property PACKAGE_PIN A25 [get_ports spim_sck_o] -set_property IOSTANDARD LVCMOS18 [get_ports spim_sck_o] - -create_clock -period 20.000 -name spi_m_sck [get_ports spim_sck_o] - -# Two-wires I2C -# LA14_P - C23 -set_property PACKAGE_PIN C23 [get_ports i2c_sda_io] -set_property IOSTANDARD LVCMOS18 [get_ports i2c_sda_io] -# LA14_N - B22 -set_property PACKAGE_PIN B22 [get_ports i2c_scl_io] -set_property IOSTANDARD LVCMOS18 [get_ports i2c_scl_io] - # Six-wires SPIx4 (Slave) # LA15_N - H20 set_property PACKAGE_PIN H20 [get_ports spis_sd_io[0]] diff --git a/target/fpga_chip/hemaia_system/hemaia_system_vpk180_bd.tcl b/target/fpga_chip/hemaia_system/hemaia_system_vpk180_bd.tcl index 08ba3802..5e327b01 100644 --- a/target/fpga_chip/hemaia_system/hemaia_system_vpk180_bd.tcl +++ b/target/fpga_chip/hemaia_system/hemaia_system_vpk180_bd.tcl @@ -218,12 +218,7 @@ proc create_root_design { parentCell } { set jtag_tck_i [ create_bd_port -dir I -type clk -freq_hz 5000000 jtag_tck_i ] set uart_cts_ni [ create_bd_port -dir I uart_cts_ni ] set uart_rts_no [ create_bd_port -dir O uart_rts_no ] - set spim_sck_o [ create_bd_port -dir O spim_sck_o ] set gpio_d_o [ create_bd_port -dir O -from 3 -to 0 gpio_d_o ] - set spim_csb_o [ create_bd_port -dir O -from 1 -to 0 spim_csb_o ] - set i2c_sda_io [ create_bd_port -dir IO i2c_sda_io ] - set i2c_scl_io [ create_bd_port -dir IO i2c_scl_io ] - set spim_sd_io [ create_bd_port -dir IO -from 3 -to 0 spim_sd_io ] set spis_sd_io [ create_bd_port -dir IO -from 3 -to 0 spis_sd_io ] set spis_sck_i [ create_bd_port -dir I spis_sck_i ] set spis_csb_i [ create_bd_port -dir I spis_csb_i ] @@ -338,24 +333,6 @@ proc create_root_design { parentCell } { ] $versal_cips_0 - # Create instance: i2c_scl_iobuf, and set properties - set i2c_scl_iobuf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 i2c_scl_iobuf ] - set_property CONFIG.C_BUF_TYPE {IOBUF} $i2c_scl_iobuf - - - # Create instance: i2c_sda_iobuf, and set properties - set i2c_sda_iobuf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 i2c_sda_iobuf ] - set_property CONFIG.C_BUF_TYPE {IOBUF} $i2c_sda_iobuf - - - # Create instance: spim_iobuf, and set properties - set spim_iobuf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 spim_iobuf ] - set_property -dict [list \ - CONFIG.C_BUF_TYPE {IOBUF} \ - CONFIG.C_SIZE {4} \ - ] $spim_iobuf - - # Create instance: spis_iobuf, and set properties set spis_iobuf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 spis_iobuf ] set_property -dict [list \ @@ -365,9 +342,6 @@ proc create_root_design { parentCell } { # Create port connections - connect_bd_net -net Net [get_bd_ports spim_sd_io] [get_bd_pins spim_iobuf/IOBUF_IO_IO] - connect_bd_net -net Net1 [get_bd_ports i2c_scl_io] [get_bd_pins i2c_scl_iobuf/IOBUF_IO_IO] - connect_bd_net -net Net2 [get_bd_ports i2c_sda_io] [get_bd_pins i2c_sda_iobuf/IOBUF_IO_IO] connect_bd_net -net Net3 [get_bd_ports spis_sd_io] [get_bd_pins spis_iobuf/IOBUF_IO_IO] connect_bd_net -net bootmode [get_bd_pins axis_vio_0/probe_out1] [get_bd_pins occamy_chip/boot_mode_i] connect_bd_net -net c_high_dout [get_bd_pins c_high/dout] [get_bd_ports vref_vdd_o] [get_bd_pins occamy_chip/jtag_trst_ni] @@ -384,25 +358,16 @@ proc create_root_design { parentCell } { connect_bd_net -net occamy_chip_0_gpio_d_o [get_bd_pins occamy_chip/gpio_d_o] [get_bd_pins xlslice_1/Din] connect_bd_net -net occamy_chip_0_jtag_tdo_o [get_bd_pins occamy_chip/jtag_tdo_o] [get_bd_ports jtag_tdo_o] set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_nets occamy_chip_0_jtag_tdo_o] - connect_bd_net -net occamy_chip_0_spim_csb_o [get_bd_pins occamy_chip/spim_csb_o] [get_bd_ports spim_csb_o] - connect_bd_net -net occamy_chip_0_spim_sck_o [get_bd_pins occamy_chip/spim_sck_o] [get_bd_ports spim_sck_o] connect_bd_net -net occamy_chip_0_uart_rts_no [get_bd_pins occamy_chip/uart_rts_no] [get_bd_ports uart_rts_no] set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_nets occamy_chip_0_uart_rts_no] connect_bd_net -net occamy_chip_0_uart_tx_o [get_bd_pins occamy_chip/uart_tx_o] [get_bd_ports uart_tx_o] set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_nets occamy_chip_0_uart_tx_o] - connect_bd_net -net occamy_chip_i2c_scl_en_o [get_bd_pins occamy_chip/i2c_scl_en_o] [get_bd_pins i2c_scl_iobuf/IOBUF_IO_T] - connect_bd_net -net occamy_chip_i2c_scl_o [get_bd_pins occamy_chip/i2c_scl_o] [get_bd_pins i2c_scl_iobuf/IOBUF_IO_I] - connect_bd_net -net occamy_chip_i2c_sda_en_o [get_bd_pins occamy_chip/i2c_sda_en_o] [get_bd_pins i2c_sda_iobuf/IOBUF_IO_T] - connect_bd_net -net occamy_chip_i2c_sda_o [get_bd_pins occamy_chip/i2c_sda_o] [get_bd_pins i2c_sda_iobuf/IOBUF_IO_I] - connect_bd_net -net occamy_chip_spim_sd_en_o [get_bd_pins occamy_chip/spim_sd_en_o] [get_bd_pins spim_iobuf/IOBUF_IO_T] - connect_bd_net -net occamy_chip_spim_sd_o [get_bd_pins occamy_chip/spim_sd_o] [get_bd_pins spim_iobuf/IOBUF_IO_I] connect_bd_net -net occamy_chip_spis_sd_en_o [get_bd_pins occamy_chip/spis_sd_en_o] [get_bd_pins spis_iobuf/IOBUF_IO_T] connect_bd_net -net occamy_chip_spis_sd_o [get_bd_pins occamy_chip/spis_sd_o] [get_bd_pins spis_iobuf/IOBUF_IO_I] connect_bd_net -net occamy_rst [get_bd_pins rst_or_core/Res] [get_bd_pins rst_core_inv/Op1] connect_bd_net -net occamy_rstn [get_bd_pins rst_core_inv/Res] [get_bd_pins occamy_chip/rst_ni] [get_bd_pins occamy_chip/rst_periph_ni] connect_bd_net -net reset [get_bd_pins axis_vio_0/probe_out0] [get_bd_pins concat_rst_core/In1] connect_bd_net -net reset_button [get_bd_ports reset] [get_bd_pins concat_rst_core/In0] - connect_bd_net -net spim_iobuf_IOBUF_IO_O [get_bd_pins spim_iobuf/IOBUF_IO_O] [get_bd_pins occamy_chip/spim_sd_i] connect_bd_net -net spis_csb_i_0_1 [get_bd_ports spis_csb_i] [get_bd_pins occamy_chip/spis_csb_i] connect_bd_net -net spis_iobuf_IOBUF_IO_O [get_bd_pins spis_iobuf/IOBUF_IO_O] [get_bd_pins occamy_chip/spis_sd_i] connect_bd_net -net spis_sck_i_0_1 [get_bd_ports spis_sck_i] [get_bd_pins occamy_chip/spis_sck_i] diff --git a/target/fpga_chip/hemaia_system/hemaia_system_vpk180_impl.xdc b/target/fpga_chip/hemaia_system/hemaia_system_vpk180_impl.xdc index 68fbd2ff..9a73fe66 100644 --- a/target/fpga_chip/hemaia_system/hemaia_system_vpk180_impl.xdc +++ b/target/fpga_chip/hemaia_system/hemaia_system_vpk180_impl.xdc @@ -17,13 +17,6 @@ set_property IOSTANDARD LVCMOS15 [get_ports vref_gnd_o] set_property DRIVE 12 [get_ports vref_gnd_o] # Four-wires UART with flow control -# set_property PACKAGE_PIN AY44 [get_ports uart_rx_i_0] -# set_property IOSTANDARD LVCMOS15 [get_ports uart_rx_i_0] -# set_property PACKAGE_PIN AW44 [get_ports uart_tx_o_0] -# set_property IOSTANDARD LVCMOS15 [get_ports uart_tx_o_0] -# FT4232HL's flow control is not connected to the FPGA... -# The external UART alternative -# Data # LA26P - CB41 set_property PACKAGE_PIN CB41 [get_ports uart_rx_i] set_property IOSTANDARD LVCMOS15 [get_ports uart_rx_i] @@ -39,42 +32,6 @@ set_property PULLUP TRUE [get_ports uart_cts_ni] set_property PACKAGE_PIN CB39 [get_ports uart_rts_no] set_property IOSTANDARD LVCMOS15 [get_ports uart_rts_no] -# Six-wires SPIx4 (Host) -# FMCP_HSPC_LA10_P -set_property PACKAGE_PIN CC44 [get_ports spim_sd_io[0]] -set_property IOSTANDARD LVCMOS15 [get_ports spim_sd_io[0]] -# FMCP_HSPC LA10_N -set_property PACKAGE_PIN CD45 [get_ports spim_sd_io[1]] -set_property IOSTANDARD LVCMOS15 [get_ports spim_sd_io[1]] -# FMCP_HSPC LA11_P -set_property PACKAGE_PIN CB51 [get_ports spim_sd_io[2]] -set_property IOSTANDARD LVCMOS15 [get_ports spim_sd_io[2]] -# FMCP_HSPC_LA11_N -set_property PACKAGE_PIN CC52 [get_ports spim_sd_io[3]] -set_property IOSTANDARD LVCMOS15 [get_ports spim_sd_io[3]] -# FMCP_HSPC_LA12_P -set_property PACKAGE_PIN BW49 [get_ports spim_csb_o[0]] -set_property IOSTANDARD LVCMOS15 [get_ports spim_csb_o[0]] -# FMCP_HSPC_LA12_N -set_property PACKAGE_PIN BW50 [get_ports spim_csb_o[1]] -set_property IOSTANDARD LVCMOS15 [get_ports spim_csb_o[1]] -# FMCP_HSPC_LA13_P -set_property PACKAGE_PIN CC49 [get_ports spim_sck_o] -set_property IOSTANDARD LVCMOS15 [get_ports spim_sck_o] - -create_clock -period 20.000 -name spi_m_sck [get_ports spim_sck_o] - -# Two-wires I2C -# FMCP_HSPC_LA14_P -set_property PACKAGE_PIN BY51 [get_ports i2c_sda_io] -set_property IOSTANDARD LVCMOS15 [get_ports i2c_sda_io] -set_property PULLUP TRUE [get_ports i2c_sda_io] - -# FMCP_HSPC_LA14_N -set_property PACKAGE_PIN CA52 [get_ports i2c_scl_io] -set_property IOSTANDARD LVCMOS15 [get_ports i2c_scl_io] -set_property PULLUP TRUE [get_ports i2c_scl_io] - # Six-wires SPIx4 (Slave) # LA15_N - CD52 set_property PACKAGE_PIN CD52 [get_ports spis_sd_io[0]]