From 05a4d5d202506ee944298504b573352223dc5941 Mon Sep 17 00:00:00 2001 From: IveanEx Date: Sun, 22 Sep 2024 22:17:07 +0200 Subject: [PATCH] FPGA CFG Update --- .../hemaia_system/hemaia_system_vcu128_bd.tcl | 33 ++++++++++--------- .../hemaia_system_vcu128_impl.xdc | 7 +++- .../hemaia_system/hemaia_system_vpk180_bd.tcl | 5 ++- .../hemaia_system_vpk180_impl.xdc | 7 +++- 4 files changed, 34 insertions(+), 18 deletions(-) diff --git a/target/fpga_chip/hemaia_system/hemaia_system_vcu128_bd.tcl b/target/fpga_chip/hemaia_system/hemaia_system_vcu128_bd.tcl index a7bb662bc..35b7c86ef 100644 --- a/target/fpga_chip/hemaia_system/hemaia_system_vcu128_bd.tcl +++ b/target/fpga_chip/hemaia_system/hemaia_system_vcu128_bd.tcl @@ -242,17 +242,17 @@ proc create_root_design { parentCell } { set_property -dict [list \ CONFIG.AXI_DRP {false} \ CONFIG.CLKOUT1_DRIVES {Buffer} \ - CONFIG.CLKOUT1_JITTER {132.683} \ - CONFIG.CLKOUT1_PHASE_ERROR {87.180} \ + CONFIG.CLKOUT1_JITTER {167.017} \ + CONFIG.CLKOUT1_PHASE_ERROR {114.212} \ CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {50} \ - CONFIG.CLKOUT2_JITTER {180.712} \ - CONFIG.CLKOUT2_PHASE_ERROR {87.180} \ + CONFIG.CLKOUT2_JITTER {219.618} \ + CONFIG.CLKOUT2_PHASE_ERROR {114.212} \ CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {12.5} \ CONFIG.CLKOUT2_USED {true} \ - CONFIG.CLKOUT3_JITTER {112.035} \ - CONFIG.CLKOUT3_PHASE_ERROR {87.180} \ - CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {120} \ - CONFIG.CLKOUT3_REQUESTED_PHASE {0} \ + CONFIG.CLKOUT3_JITTER {209.277} \ + CONFIG.CLKOUT3_PHASE_ERROR {114.212} \ + CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {16} \ + CONFIG.CLKOUT3_REQUESTED_PHASE {60} \ CONFIG.CLKOUT3_USED {true} \ CONFIG.CLKOUT4_JITTER {112.035} \ CONFIG.CLKOUT4_PHASE_ERROR {87.180} \ @@ -261,14 +261,16 @@ proc create_root_design { parentCell } { CONFIG.CLK_IN1_BOARD_INTERFACE {default_100mhz_clk} \ CONFIG.CLK_OUT1_PORT {clk_core} \ CONFIG.CLK_OUT2_PORT {clk_rtc} \ - CONFIG.CLK_OUT3_PORT {clk_hbm} \ + CONFIG.CLK_OUT3_PORT {clk_peri} \ CONFIG.CLK_OUT4_PORT {clk_out4} \ CONFIG.FEEDBACK_SOURCE {FDBK_AUTO} \ - CONFIG.MMCM_CLKFBOUT_MULT_F {12.000} \ - CONFIG.MMCM_CLKOUT0_DIVIDE_F {24.000} \ - CONFIG.MMCM_CLKOUT1_DIVIDE {96} \ - CONFIG.MMCM_CLKOUT2_DIVIDE {10} \ - CONFIG.MMCM_CLKOUT2_PHASE {0.000} \ + CONFIG.MMCM_CLKFBOUT_MULT_F {8.000} \ + CONFIG.MMCM_CLKIN1_PERIOD {10.0} \ + CONFIG.MMCM_CLKIN2_PERIOD {10.0} \ + CONFIG.MMCM_CLKOUT0_DIVIDE_F {16.000} \ + CONFIG.MMCM_CLKOUT1_DIVIDE {64} \ + CONFIG.MMCM_CLKOUT2_DIVIDE {50} \ + CONFIG.MMCM_CLKOUT2_PHASE {60.300} \ CONFIG.MMCM_CLKOUT3_DIVIDE {1} \ CONFIG.MMCM_DIVCLK_DIVIDE {1} \ CONFIG.NUM_OUT_CLKS {3} \ @@ -333,7 +335,8 @@ proc create_root_design { parentCell } { set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_nets Net2] connect_bd_net -net bootmode [get_bd_pins vio_sys/probe_out1] [get_bd_pins occamy_chip/boot_mode_i] connect_bd_net -net c_high_dout [get_bd_pins c_high/dout] [get_bd_ports vref_vdd_o] [get_bd_pins occamy_chip/jtag_trst_ni] - connect_bd_net -net clk_wiz_clk_core [get_bd_pins clk_wiz/clk_core] [get_bd_pins vio_sys/clk] [get_bd_pins occamy_chip/clk_i] [get_bd_pins occamy_chip/clk_periph_i] + connect_bd_net -net clk_wiz_clk_core [get_bd_pins clk_wiz/clk_core] [get_bd_pins vio_sys/clk] [get_bd_pins occamy_chip/clk_i] + connect_bd_net -net clk_wiz_clk_peri [get_bd_pins clk_wiz/clk_peri] [get_bd_pins occamy_chip/clk_periph_i] connect_bd_net -net clk_wiz_clk_rtc [get_bd_pins clk_wiz/clk_rtc] [get_bd_pins occamy_chip/rtc_i] connect_bd_net -net const_low_dout [get_bd_pins c_low/dout] [get_bd_ports vref_gnd_o] [get_bd_pins occamy_chip/test_mode_i] [get_bd_pins occamy_chip/gpio_d_i] [get_bd_pins occamy_chip/ext_irq_i] connect_bd_net -net jtag_tck_i_1 [get_bd_ports jtag_tck_i] [get_bd_pins occamy_chip/jtag_tck_i] diff --git a/target/fpga_chip/hemaia_system/hemaia_system_vcu128_impl.xdc b/target/fpga_chip/hemaia_system/hemaia_system_vcu128_impl.xdc index 17aa7f101..a86c29d05 100644 --- a/target/fpga_chip/hemaia_system/hemaia_system_vcu128_impl.xdc +++ b/target/fpga_chip/hemaia_system/hemaia_system_vcu128_impl.xdc @@ -94,9 +94,14 @@ set_property IOSTANDARD LVCMOS12 [get_ports reset] set_false_path -to [get_pins hemaia_system_i/occamy_chip/inst/i_occamy/i_clint/i_sync_edge/i_sync/reg_q_reg[0]/D] ################################################################################ -# JTAG +# Crossing Clock Domains ################################################################################ +create_clock -period 20.0 -name clk_core [get_pins hemaia_system_i/clk_wiz/clk_core] +create_clock -period 62.5 -name clk_peri [get_pins hemaia_system_i/clk_wiz/clk_peri] + +set_clock_groups -asynchronous -group [get_clocks -of [get_pins hemaia_system_i/occamy_chip/clk_i]] -group [get_clocks -of [get_pins hemaia_system_i/occamy_chip/clk_periph_i]] + # CDC 2phase clearable of DM: i_cdc_resp/i_cdc_req # CONSTRAINT: Requires max_delay of min_period(src_clk_i, dst_clk_i) through the paths async_req, async_ack, async_data. set_max_delay -through [get_nets -hier -filter {NAME =~ "*i_cdc_resp/async_req*"}] 10.000 diff --git a/target/fpga_chip/hemaia_system/hemaia_system_vpk180_bd.tcl b/target/fpga_chip/hemaia_system/hemaia_system_vpk180_bd.tcl index 610f1d0d9..8eb34b194 100644 --- a/target/fpga_chip/hemaia_system/hemaia_system_vpk180_bd.tcl +++ b/target/fpga_chip/hemaia_system/hemaia_system_vpk180_bd.tcl @@ -297,6 +297,7 @@ proc create_root_design { parentCell } { PMC_CRP_NOC_REF_CTRL_FREQMHZ {960} \ PMC_CRP_PL0_REF_CTRL_FREQMHZ {50} \ PMC_CRP_PL1_REF_CTRL_FREQMHZ {3.2768} \ + PMC_CRP_PL2_REF_CTRL_FREQMHZ {16} \ PMC_CRP_PL5_REF_CTRL_FREQMHZ {400} \ PMC_MIO0 {{AUX_IO 0} {DIRECTION in} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE Reserved}} \ PMC_MIO1 {{AUX_IO 0} {DIRECTION in} {DRIVE_STRENGTH 8mA} {OUTPUT_DATA default} {PULL pullup} {SCHMITT 0} {SLEW slow} {USAGE Reserved}} \ @@ -319,6 +320,7 @@ proc create_root_design { parentCell } { PS_USE_NOC_LPD_AXI0 {0} \ PS_USE_PMCPL_CLK0 {1} \ PS_USE_PMCPL_CLK1 {1} \ + PS_USE_PMCPL_CLK2 {1} \ PS_USE_PMCPL_IRO_CLK {0} \ SMON_ALARMS {Set_Alarms_On} \ SMON_ENABLE_TEMP_AVERAGING {0} \ @@ -342,7 +344,7 @@ proc create_root_design { parentCell } { set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_nets Net2] connect_bd_net -net bootmode [get_bd_pins axis_vio_0/probe_out1] [get_bd_pins occamy_chip/boot_mode_i] connect_bd_net -net c_high_dout [get_bd_pins c_high/dout] [get_bd_ports vref_vdd_o] [get_bd_pins occamy_chip/jtag_trst_ni] - connect_bd_net -net clk_wizard_0_clk_core [get_bd_pins versal_cips_0/pl0_ref_clk] [get_bd_pins axis_vio_0/clk] [get_bd_pins occamy_chip/clk_i] [get_bd_pins occamy_chip/clk_periph_i] + connect_bd_net -net clk_wizard_0_clk_core [get_bd_pins versal_cips_0/pl0_ref_clk] [get_bd_pins axis_vio_0/clk] [get_bd_pins occamy_chip/clk_i] connect_bd_net -net const_low_dout [get_bd_pins c_low/dout] [get_bd_ports vref_gnd_o] [get_bd_pins occamy_chip/test_mode_i] [get_bd_pins occamy_chip/gpio_d_i] [get_bd_pins occamy_chip/ext_irq_i] connect_bd_net -net jtag_tck_i_1 [get_bd_ports jtag_tck_i] [get_bd_pins occamy_chip/jtag_tck_i] set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_nets jtag_tck_i_1] @@ -368,6 +370,7 @@ proc create_root_design { parentCell } { connect_bd_net -net uart_rx_i_0_1 [get_bd_ports uart_rx_i_0] [get_bd_pins occamy_chip/uart_rx_i] set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_nets uart_rx_i_0_1] connect_bd_net -net versal_cips_0_pl1_ref_clk [get_bd_pins versal_cips_0/pl1_ref_clk] [get_bd_pins occamy_chip/rtc_i] + connect_bd_net -net versal_cips_0_pl2_ref_clk [get_bd_pins versal_cips_0/pl2_ref_clk] [get_bd_pins occamy_chip/clk_periph_i] connect_bd_net -net xlconcat_2_dout [get_bd_pins concat_rst_core/dout] [get_bd_pins rst_or_core/Op1] connect_bd_net -net xlslice_1_Dout [get_bd_pins xlslice_1/Dout] [get_bd_ports gpio_d_o] diff --git a/target/fpga_chip/hemaia_system/hemaia_system_vpk180_impl.xdc b/target/fpga_chip/hemaia_system/hemaia_system_vpk180_impl.xdc index 206874fda..7a49fbcaf 100644 --- a/target/fpga_chip/hemaia_system/hemaia_system_vpk180_impl.xdc +++ b/target/fpga_chip/hemaia_system/hemaia_system_vpk180_impl.xdc @@ -97,9 +97,14 @@ set_property IOSTANDARD LVCMOS15 [get_ports reset] set_false_path -to [get_pins hemaia_system_i/occamy_chip/inst/i_occamy/i_clint/i_sync_edge/i_sync/reg_q_reg[0]/D] ################################################################################ -# JTAG +# Crossing Clock Domains ################################################################################ +create_clock -period 20.0 -name clk_core [get_pins hemaia_system_i/versal_cips_0/pl0_ref_clk] +create_clock -period 62.5 -name clk_peri [get_pins hemaia_system_i/versal_cips_0/pl2_ref_clk] + +set_clock_groups -asynchronous -group [get_clocks -of [get_pins hemaia_system_i/occamy_chip/clk_i]] -group [get_clocks -of [get_pins hemaia_system_i/occamy_chip/clk_periph_i]] + # CDC 2phase clearable of DM: i_cdc_resp/i_cdc_req # CONSTRAINT: Requires max_delay of min_period(src_clk_i, dst_clk_i) through the paths async_req, async_ack, async_data. set_max_delay -through [get_nets -hier -filter {NAME =~ "*i_cdc_resp/async_req*"}] 10.000