From 6c0e3691a34693350a7962d7eb23b78fce1fdcfa Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ivar=20J=C3=B6nsson?= <ivar.jonsson@grepit.se>
Date: Tue, 28 Jun 2022 13:42:12 +0200
Subject: [PATCH] hal/pio/reg: into_peripheral: correctly set/clear abcdsr

Before this commit other pin bits were not preserved.

Closes #16.
---
 hal/src/pio/reg.rs | 20 +++++++++++++-------
 1 file changed, 13 insertions(+), 7 deletions(-)

diff --git a/hal/src/pio/reg.rs b/hal/src/pio/reg.rs
index 2291c81d..4f92a12f 100644
--- a/hal/src/pio/reg.rs
+++ b/hal/src/pio/reg.rs
@@ -31,16 +31,22 @@ pub(in crate::pio) unsafe trait RegisterInterface {
     fn into_peripheral(&mut self, cfg: DynPeripheral) {
         use DynPeripheral::*;
         let (sr0, sr1) = match cfg {
-            A => (0, 0),
-            B => (1, 0),
-            C => (0, 1),
-            D => (1, 1),
+            A => (false, false),
+            B => (true, false),
+            C => (false, true),
+            D => (true, true),
         };
         let idx = self.id().num;
 
-        // configure function
-        self.reg().pio_abcdsr[0].modify(|_, w| unsafe { w.bits(sr0 << idx) });
-        self.reg().pio_abcdsr[1].modify(|_, w| unsafe { w.bits(sr1 << idx) });
+        // configure function, preserving other pin bits
+        for (i, bit) in (0..=1).zip([sr0, sr1]) {
+            self.reg().pio_abcdsr[i].modify(|r, w| unsafe {
+                w.bits(match bit {
+                    true => r.bits() | 1 << idx,
+                    false => r.bits() & !(1 << idx),
+                })
+            });
+        }
 
         // give pin to peripheral
         self.reg().pio_pdr.write(|w| unsafe { w.bits(self.mask()) });