Debugging a SuperH4 target (Anritsu MS2721B)

[brainstorm]

While attempting repair of an Anritsu MS2721B 6GHz "portable" spectrum analyzer, I mapped out the JTAG pinout of its main SH4 (SH7750R) MCU on the board.

For context, the unit was working before but stopped booting up, so now I'm trying to figure out where exactly is the device halting within the (early) boot sequence.

Then I went for Glasgow to confirm the JTAG pinout and indeed, those pins are well identified:

(glasgow) rvalls@m1 glasgow % glasgow run jtag-pinout --port A --pins-jtag 1,3,5,6 -f 250 -V 1.8
I: g.device.hardware: building bitstream ID 32f2f979fe52e87384b67000968b34fa
I: g.cli: running handler for applet 'jtag-pinout'
I: g.applet.interface.jtag_pinout: port(s) A voltage set to 1.8 V
I: g.applet.interface.jtag_pinout: detecting pull resistors
I: g.applet.interface.jtag_pinout: pull-H: A1, A3, A5, A6
I: g.applet.interface.jtag_pinout: detecting TCK, TMS, and TDO
I: g.applet.interface.jtag_pinout: shifted 10 out of IR with TCK=A1 TMS=A5 TDO=A3
I: g.applet.interface.jtag_pinout: detecting TDI
I: g.applet.interface.jtag_pinout: shifted 32-bit IR with TCK=A1 TMS=A5 TDI=A6 TDO=A3
I: g.applet.interface.jtag_pinout: JTAG interface without reset detected
I: g.applet.interface.jtag_pinout: use `jtag-probe -V 1.8 --pin-tck 1 --pin-tms 5 --pin-tdi 6 --pin-tdo 3` as arguments

And they also spit some TAP info:

(glasgow) rvalls@m1 glasgow % glasgow run jtag-probe -V 1.8 --pin-tck 1 --pin-tms 5 --pin-tdi 6 --pin-tdo 3 scan
I: g.device.hardware: building bitstream ID a441e52aea68aafca8d02fa0007c27cf
I: g.cli: running handler for applet 'jtag-probe'
I: g.applet.interface.jtag_probe: port(s) A, B voltage set to 1.8 V
I: g.applet.interface.jtag_probe: shifted 1-bit DR=<0>
I: g.applet.interface.jtag_probe: shifted 32-bit IR=<10111111111111111111111111111111>
I: g.applet.interface.jtag_probe: discovered 1 TAPs
I: g.applet.interface.jtag_probe: TAP #0: IR[32] BYPASS

And even attempted to establish some JTAG bitbanged session for OpenOCD, similar to my previous attempts with an ESP32S2:

% glasgow run jtag-openocd -V 1.8 --pin-tck 1 --pin-tms 5 --pin-tdi 6 --pin-tdo 3 -f 100 -V 3.3 tcp:localhost:2222
I: g.device.hardware: building bitstream ID c850b1822f53f5fa7fc5e4ec24e21c87
I: g.cli: running handler for applet 'jtag-openocd'
I: g.applet.interface.jtag_openocd: port(s) A, B voltage set to 3.3 V
I: g.applet.interface.jtag_openocd: socket: listening at tcp:localhost:2222
I: g.applet.interface.jtag_openocd: socket: new connection from [::1]:58608

% openocd -c 'interface remote_bitbang; remote_bitbang_port 2222'
Open On-Chip Debugger 0.11.0+dev-00471-gcaa169813 (2021-11-20-01:35)
Licensed under GNU GPL v2
For bug reports, read
	http://openocd.org/doc/doxygen/bugs.html
DEPRECATED! use 'adapter driver' not 'interface'
Info : only one transport option; autoselect 'jtag'
DEPRECATED! use 'remote_bitbang port' not 'remote_bitbang_port'
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
Info : Initializing remote_bitbang driver
Info : Connecting to localhost:2222
Info : remote_bitbang driver initialized
Info : This adapter doesn't support configurable speed
Warn : There are no enabled taps.  AUTO PROBING MIGHT NOT WORK!!
Info : TAP auto0.tap does not have valid IDCODE (idcode=0xfffffffe)
Warn : AUTO auto0.tap - use "jtag newtap auto0 tap -irlen 2 -expected-id 0x00000000"
Warn : gdb services need one or more targets defined

But then after scanning OpenOCD for suitable targets, I couldn't find any SuperH4 related ones. So I went back to the datasheet linked above and sections 20 and 21 describe what seems to be a customization (extension?) of JTAG called "H-UDI" (and its debugging support called "UBC").

Also there seem to be some 12-y.o dead end threads on renesasrulz.com regarding BSDL availability for those targets.

Is there somebody experienced with this target within this community? Is there any prior art of OSS tooling for SH4 that somebody can point me to?

[whitequark]

I've looked Section 21 of the manual you've referenced. It doesn't quite provide enough information to build a complete debugger. Look at this diagram:

The peripheral module bus is what you'd actually use to stop the core and examine its state. To do this, you need to issue memory reads and writes on that bus. But there's no described way to do this. If I had to guess, there are undocumented SDIR bits that set transaction width and type and strobe accesses, though there could be other ways to do this.

Regarding BSDL files, those can be written from scratch using Table 21.3 and Section 21.2.1, if you need them.

[brainstorm]

I emailed a few of the J-core devs yesterday and here's a nice piece of info about those special SH4 JTAG debuggers:

I didn't find any documentation regarding JTAG for SH4. I basically
bought one of these: https://www.apnet.co.jp/product/superh/xf.html

I did investigate a bit on my own, and discover that this JTAG is a bit
complicated. First this the JTAG does is to upload a binary blob into
the SH4 (is called ASE memory). This provides specific/custom
functionality that the probe uses later on (like for example cache
misses ratio calculator). The point is that once you get one of these
you don't really need to reverse engineer anything, it just works like a
charm.

[freemin7]

Have you heard back from them?

[brainstorm]

Yes, we had a good discussion with them, referred to a couple of folks at Renesas, but after following those Renesas replied that they are not interested in non-paying customers :/

[brainstorm]

Happy to sponsor https://apnet.co.jp/product/superh/ap-sh4-1a.html dev board to elucidate H-UDI and have as much as possible supported on Glasgow as discussed over IRC.

Feel free to reach out to brainstorm at nopcode dot org for logistics, no rush ;)

[mtaalas]

Did this ever pan out? :)
Trying to reverse engineer a piece of SH3 hardware and came to the same wall of debuggers costing 1000€+/piece.

[brainstorm]

Not yet, but hopefully at some point in the future :)

I think that a very sensible summary that matches my personal situation (and possibly others) w.r.t to this particular project and time commitments is this from Catherine:

Please stay patient and keep in mind that hardware is made by people who have limited capacity and sometimes need to recover from extreme events.

If you want to show appreciation or help with Catherine's living costs, she has a personal Patreon. These donations will not impact the progress of the project since the limiting factor is health first and time second, but they are very much appreciated.

My available time and disposable income has changed quite a bit since I was tinkering and wrote all this. I'd love to work on it and see it unfold, but I've also have to be realistic about other life priorities, time and sources of income to sustain myself and others :)

[dossalab]

I had some experience debugging STi7105 with ST40 Micro Toolset, I think parts of this toolchain are available somewhere on the internet (you know whom to ask, wink-wink) The adapter is just a regular FT2232 mini module with changed device name and VID:PID pair....
It's laggy and aging though so I'd wish there was some FLOSS solution.
I sometimes work on this target so if there's some interest I can assist or document stuff that I'm doing.

[brainstorm]

Yes please! Document and capture (traces) as much as possible, I'd also like to see FLOSS support for SuperH... it's interesting that talks about this arch keep popping up on HN after so long.