diff --git a/arm9/source/emu/cpuArmLo.s b/arm9/source/emu/cpuArmLo.s
index 961b28d..f90791e 100644
--- a/arm9/source/emu/cpuArmLo.s
+++ b/arm9/source/emu/cpuArmLo.s
@@ -1,9 +1,10 @@
+#ifdef SELF_MODIFYING_MIX
 .section .itcm
 .altmacro
 
 #include "consts.s"
 
-.macro finish_handler_skip_op_self_modifying
+.macro arml_return
 	msr cpsr_c, #(CPSR_IRQ_FIQ_BITS | 0x17)
 
 	ldr lr, [r13, #4] //pu_data_permissions
@@ -15,149 +16,6 @@
 	subs pc, lr, #4
 .endm
 
-.macro make_arml_instLdrhStrh pre, up, imm, wrback, load, sign, half
-	.if (!\pre && \wrback) || (\load && !\sign && !\half) || (!\load && !(!\sign && \half)) 
-		.exitm
-	.endif
-.global arml_instLdrhStrh_\pre\up\imm\wrback\load\sign\half
-arml_instLdrhStrh_\pre\up\imm\wrback\load\sign\half:
-	.if \imm
-		//immediate, make add (r9/rd), rn, r8 or sub (r9/rd), rn, r8
-		mov r8, r10, lsl #12
-		mov r9, r8, lsr #28
-		.if \up
-			orr r8, r9, #0x80 //add
-		.else
-			orr r8, r9, #0x40 //sub
-		.endif
-		strb r8, (1f + 2)
-		.if !\pre || (\pre && \wrback)
-			.if !\pre //get the base address before writing back the new address for post
-				strb r9, 2f
-			.else //get the new base address from the writeback reg
-				strb r9, 3f
-			.endif
-			mov r8, r9, lsl #4 //rd = base register
-			strb r8, (1f + 1)
-		.endif
-		and r8, r10, #0x0000F000
-		.if \load
-			mov r8, r8, lsr #8
-			strb r8, (4f + 1)
-		.else
-			mov r8, r8, lsr #12
-			strb r8, 4f
-		.endif
-
-		and r8, r10, #0xF
-		and r9, r10, #0xF00
-		orr r8, r9, lsr #4
-		.if !\pre
-		2:
-			mov r9, r0
-		.endif
-	1:
-		add r9, r0, r8
-		.if \pre && \wrback
-		3:
-			mov r9, r0
-		.endif
-	.else
-		//shifted register, convert opcode to add r9, rn, rm or sub r9, rn, rm
-		ldr r8, [r12, #0x50] //0x000F000F
-		.if !\pre || (\pre && \wrback)
-			.if \up
-				ldr r11, [r12, #0x54] //0xE0800000 add
-			.else
-				ldr r11, [r12, #0x58] //0xE0400000 sub
-			.endif
-			and r8, r10, r8
-			mov r9, r8, lsr #16
-			orr r8, r8, lsr #4	//rd = base reg (rn)			
-			.if !\pre //get the base address before writing back the new address for post
-				strb r9, 2f
-			.else //get the new base address from the writeback reg
-				strb r9, 3f
-			.endif
-		.else
-			.if \up
-				ldr r11, [r12, #0x5C] //0xE0809000 add
-			.else
-				ldr r11, [r12, #0x60] //0xE0409000 sub
-			.endif
-			and r8, r10, r8
-		.endif		
-		orr r8, r11
-		str r8, 1f
-
-		and r8, r10, #0x0000F000
-		.if \load
-			mov r8, r8, lsr #8
-			strb r8, (4f + 1)
-		.else
-			mov r8, r8, lsr #12
-			strb r8, 4f
-		.endif
-
-		.if !\pre
-			b 2f
-		2:
-			mov r9, r0
-		.else
-			b 1f
-		.endif
-	1:
-		nop
-		.if \pre && \wrback
-		3:
-			mov r9, r0
-		.endif
-	.endif
-	.if \load
-		.if !\sign && \half
-			bl read_address_from_handler_16bit
-		.elseif \sign && !\half
-			bl read_address_from_handler_8bit
-			mov r10, r10, lsl #24
-			mov r10, r10, asr #24
-		.else
-			bl read_address_from_handler_16bit
-			tst r9, #1
-			movne r10, r10, lsl #8
-			mov r10, r10, lsl #16
-			mov r10, r10, asr #16
-			movne r10, r10, asr #8
-		.endif
-		4:
-			mov r0, r10
-	.else
-		.if \imm
-			b 4f //I hope I can get rid of this
-		.endif
-	4:
-		mov r11, r0
-		mov r11, r11, lsl #16
-		mov r11, r11, lsr #16
-		bl write_address_from_handler_16bit
-	.endif
-	finish_handler_skip_op_self_modifying
-.endm
-
-.macro makeAll_arml_instLdrhStrh pre, arg=0
-	make_arml_instLdrhStrh \pre,%((\arg>>5)&1),%((\arg>>4)&1),%((\arg>>3)&1),%((\arg>>2)&1),%((\arg>>1)&1),%((\arg>>0)&1)
-.if \arg<0x3F
-	makeAll_arml_instLdrhStrh \pre,%(\arg+1)
-.endif
-.endm
-
-makeAll_arml_instLdrhStrh 0
-
-.pool
-
-makeAll_arml_instLdrhStrh 1
-
-.pool
-
 .macro make_arml_instLdrStr reg, pre, up, byte, wrback, load
 	.if !\pre && \wrback
 		.exitm
@@ -190,7 +48,11 @@ arml_instLdrStr_\reg\pre\up\byte\wrback\load:
 			strb r8, (4f + 1)
 		.else
 			mov r8, r8, lsr #12
-			strb r8, 4f
+			.if \byte
+				strb r8, write_address_from_handler_8bit_selfmodify //4f
+			.else
+				strb r8, write_address_from_handler_32bit_selfmodify
+			.endif
 		.endif
 
 		mov r8, r10, lsl #20	
@@ -238,7 +100,11 @@ arml_instLdrStr_\reg\pre\up\byte\wrback\load:
 			strb r8, (4f + 1)
 		.else
 			mov r8, r8, lsr #12
-			strb r8, 4f
+			.if \byte
+				strb r8, write_address_from_handler_8bit_selfmodify
+			.else
+				strb r8, write_address_from_handler_32bit_selfmodify
+			.endif
 		.endif
 
 		//todo: fix c-flag
@@ -247,11 +113,8 @@ arml_instLdrStr_\reg\pre\up\byte\wrback\load:
 		//msr cpsr_c, #(CPSR_IRQ_FIQ_BITS | 0x11)
 		//msr cpsr_f, r8
 		.if !\pre
-			b 2f
 		2:
 			mov r9, r0
-		.else
-			b 1f
 		.endif
 	1:
 		nop
@@ -269,19 +132,13 @@ arml_instLdrStr_\reg\pre\up\byte\wrback\load:
 	4:
 		mov r0, r10
 	.else
-		.if !\reg
-			b 4f //I hope I can get rid of this
-		.endif
-	4:
-		mov r11, r0
-		.if \byte		
-			and r11, #0xFF //byte
-			bl write_address_from_handler_8bit
-		.else		
-			bl write_address_from_handler_32bit
+		.if \byte
+			bl write_address_from_handler_8bit_selfmodify
+		.else
+			bl write_address_from_handler_32bit_selfmodify
 		.endif
 	.endif
-	finish_handler_skip_op_self_modifying
+	arml_return
 .endm
 
 .macro makeAll_arml_instLdrStr arg=0
@@ -294,3 +151,4 @@ arml_instLdrStr_\reg\pre\up\byte\wrback\load:
 makeAll_arml_instLdrStr
 
 .pool
+#endif
\ No newline at end of file
diff --git a/arm9/source/emu/cpuArmLoHalfword.s b/arm9/source/emu/cpuArmLoHalfword.s
new file mode 100644
index 0000000..c3e3732
--- /dev/null
+++ b/arm9/source/emu/cpuArmLoHalfword.s
@@ -0,0 +1,139 @@
+#ifdef SELF_MODIFYING_MIX
+.section .itcm
+.altmacro
+
+#include "consts.s"
+
+.macro make_arml_instLdrhStrh pre, up, imm, wrback, load, sign, half
+	.if (!\pre && \wrback) || (\load && !\sign && !\half) || (!\load && !(!\sign && \half)) 
+		.exitm
+	.endif
+.global arml_instLdrhStrh_\pre\up\imm\wrback\load\sign\half
+arml_instLdrhStrh_\pre\up\imm\wrback\load\sign\half:
+	.if \imm
+		//immediate, make add (r9/rd), rn, r8 or sub (r9/rd), rn, r8
+		mov r8, r10, lsl #12
+		mov r9, r8, lsr #28
+		.if \up
+			orr r8, r9, #0x80 //add
+		.else
+			orr r8, r9, #0x40 //sub
+		.endif
+		strb r8, (1f + 2)
+		.if !\pre || (\pre && \wrback)
+			.if !\pre //get the base address before writing back the new address for post
+				strb r9, 2f
+			.else //get the new base address from the writeback reg
+				strb r9, 3f
+			.endif
+			mov r8, r9, lsl #4 //rd = base register
+			strb r8, (1f + 1)
+		.endif
+		and r8, r10, #0x0000F000
+		.if \load
+			mov r8, r8, lsr #8
+			strb r8, (4f + 1)
+		.else
+			mov r8, r8, lsr #12
+			strb r8, write_address_from_handler_16bit_selfmodify
+		.endif
+
+		and r8, r10, #0xF
+		and r9, r10, #0xF00
+		orr r8, r9, lsr #4
+		.if !\pre
+		2:
+			mov r9, r0
+		.endif
+	1:
+		add r9, r0, r8
+		.if \pre && \wrback
+		3:
+			mov r9, r0
+		.endif
+	.else
+		//shifted register, convert opcode to add r9, rn, rm or sub r9, rn, rm
+		ldr r8, [r12, #0x50] //0x000F000F
+		.if !\pre || (\pre && \wrback)
+			.if \up
+				ldr r11, [r12, #0x54] //0xE0800000 add
+			.else
+				ldr r11, [r12, #0x58] //0xE0400000 sub
+			.endif
+			and r8, r10, r8
+			mov r9, r8, lsr #16
+			orr r8, r8, lsr #4	//rd = base reg (rn)			
+			.if !\pre //get the base address before writing back the new address for post
+				strb r9, 2f
+			.else //get the new base address from the writeback reg
+				strb r9, 3f
+			.endif
+		.else
+			.if \up
+				ldr r11, [r12, #0x5C] //0xE0809000 add
+			.else
+				ldr r11, [r12, #0x60] //0xE0409000 sub
+			.endif
+			and r8, r10, r8
+		.endif		
+		orr r8, r11
+		str r8, 1f
+
+		and r8, r10, #0x0000F000
+		.if \load
+			mov r8, r8, lsr #8
+			strb r8, (4f + 1)
+		.else
+			mov r8, r8, lsr #12
+			strb r8, write_address_from_handler_16bit_selfmodify
+		.endif
+
+		.if !\pre
+		2:
+			mov r9, r0
+		.endif
+	1:
+		nop
+		.if \pre && \wrback
+		3:
+			mov r9, r0
+		.endif
+	.endif
+	.if \load
+		.if !\sign && \half
+			bl read_address_from_handler_16bit
+		.elseif \sign && !\half
+			bl read_address_from_handler_8bit
+			mov r10, r10, lsl #24
+			mov r10, r10, asr #24
+		.else
+			bl read_address_from_handler_16bit
+			tst r9, #1
+			movne r10, r10, lsl #8
+			mov r10, r10, lsl #16
+			mov r10, r10, asr #16
+			movne r10, r10, asr #8
+		.endif
+		4:
+			mov r0, r10
+	.else
+		bl write_address_from_handler_16bit_selfmodify
+	.endif
+	arml_return
+.endm
+
+.macro makeAll_arml_instLdrhStrh load, arg=0
+	make_arml_instLdrhStrh %((\arg>>5)&1),%((\arg>>4)&1),%((\arg>>3)&1),%((\arg>>2)&1),\load,%((\arg>>1)&1),%((\arg>>0)&1)
+.if \arg<0x3F
+	makeAll_arml_instLdrhStrh \load,%(\arg+1)
+.endif
+.endm
+
+makeAll_arml_instLdrhStrh 0
+
+.pool
+
+makeAll_arml_instLdrhStrh 1
+
+.pool
+#endif
\ No newline at end of file
diff --git a/arm9/source/emu/cpuThumb.s b/arm9/source/emu/cpuThumb.s
index d2f9fc7..26dce7c 100644
--- a/arm9/source/emu/cpuThumb.s
+++ b/arm9/source/emu/cpuThumb.s
@@ -1,9 +1,10 @@
+#ifdef SELF_MODIFYING_MIX
 .section .itcm
 .altmacro
 
 #include "consts.s"
 
-.macro finish_handler_skip_op_self_modifying
+.macro thumb_return
 	msr cpsr_c, #(CPSR_IRQ_FIQ_BITS | 0x17)
 
 	ldr lr, [r13, #4] //pu_data_permissions
@@ -28,7 +29,7 @@ thumb6_address_calc:
 	bl read_address_from_handler_32bit
 1:
 	mov r0, r10
-	finish_handler_skip_op_self_modifying
+	thumb_return
 
 .macro create_thumb7_variant l, bw
 .global thumb7_address_calc_\l\bw
@@ -41,12 +42,16 @@ thumb7_address_calc_\l\bw:
 	str r8, 1f
 	and r8, r10, #7
 .ifeq \l //write
-	strb r8, 2f
+	.if \bw
+		strb r8, write_address_from_handler_8bit_selfmodify
+	.else		
+		strb r8, write_address_from_handler_32bit_selfmodify
+	.endif
+	nop //to ensure the pipeline is not too far ahead for the 1f write
 .else
 	mov r8, r8, lsl #4
 	strb r8, (2f + 1)
 .endif
-	b 1f
 1:
 	.word 0
 //align if 32 bit write
@@ -54,13 +59,10 @@ thumb7_address_calc_\l\bw:
 	//bic r9, r9, #3
 .endif
 .ifeq \l //write
-2:
-	mov r11, r0
 	.ifeq \bw
-		bl write_address_from_handler_32bit
+		bl write_address_from_handler_32bit_selfmodify
 	.else
-		and r11, r11, #0xFF
-		bl write_address_from_handler_8bit
+		bl write_address_from_handler_8bit_selfmodify
 	.endif
 .else
 	.ifeq \bw
@@ -71,7 +73,7 @@ thumb7_address_calc_\l\bw:
 2:
 	mov r0, r10
 .endif
-	finish_handler_skip_op_self_modifying
+	thumb_return
 .endm
 
 create_thumb7_variant 0,0
@@ -91,19 +93,17 @@ thumb8_address_calc_\x\y:
 	str r8, 1f
 	and r8, r10, #7
 .if !\x && !\y //strh
-	strb r8, 2f
+	strb r8, write_address_from_handler_16bit_selfmodify
+	nop //to ensure the pipeline is not too far ahead for the 1f write
 .else
 	mov r8, r8, lsl #4
 	strb r8, (2f + 1)
 .endif
-	b 1f
 1:
 	.word 0
 .if !\x && !\y //strh
 2:
-	mov r11, r0, lsl #16
-	mov r11, r11, lsr #16
-	bl write_address_from_handler_16bit
+	bl write_address_from_handler_16bit_selfmodify
 .else
 	.if !\x && \y //ldrsb
 		bl read_address_from_handler_8bit
@@ -122,7 +122,7 @@ thumb8_address_calc_\x\y:
 2:
 	mov r0, r10
 .endif
-	finish_handler_skip_op_self_modifying
+	thumb_return
 .endm
 
 create_thumb8_variant 0,0
@@ -138,12 +138,16 @@ thumb9_address_calc_\bw\l:
 	strb r8, 1f
 	and r8, r10, #7
 .ifeq \l //write
-	strb r8, 2f
+	.if \bw
+		strb r8, write_address_from_handler_8bit_selfmodify
+	.else		
+		strb r8, write_address_from_handler_32bit_selfmodify
+	.endif
+	nop //to ensure the pipeline is not too far ahead for the 1f write
 .else
 	mov r8, r8, lsl #4
 	strb r8, (2f + 1)
 .endif
-	b 1f
 1:
 	mov lr, r0
 	and r12, r10, #(31 << 6)
@@ -157,13 +161,10 @@ thumb9_address_calc_\bw\l:
 	bic r9, r9, #3
 .endif
 .ifeq \l //write
-2:
-	mov r11, r0
 	.ifeq \bw
-		bl write_address_from_handler_32bit
+		bl write_address_from_handler_32bit_selfmodify
 	.else
-		and r11, r11, #0xFF
-		bl write_address_from_handler_8bit
+		bl write_address_from_handler_8bit_selfmodify
 	.endif
 .else
 	.ifeq \bw
@@ -174,7 +175,7 @@ thumb9_address_calc_\bw\l:
 2:
 	mov r0, r10
 .endif
-	finish_handler_skip_op_self_modifying
+	thumb_return
 .endm
 
 create_thumb9_variant 0,0
@@ -190,27 +191,23 @@ thumb10_address_calc_\l:
 	strb r8, 1f
 	and r8, r10, #7
 .ifeq \l //write
-	strb r8, 2f
+	strb r8, write_address_from_handler_16bit_selfmodify
 .else //read
 	mov r8, r8, lsl #4
 	strb r8, (2f + 1)
 .endif
 	and r12, r10, #(31 << 6)
-	b 1f
 1:
 	mov lr, r0
 	add r9, lr, r12, lsr #5
 .ifeq \l //write
-2:
-	mov r11, r0, lsl #16
-	mov r11, r11, lsr #16
-	bl write_address_from_handler_16bit
+	bl write_address_from_handler_16bit_selfmodify
 .else //read
 	bl read_address_from_handler_16bit
 2:
 	mov r0, r10
 .endif
-	finish_handler_skip_op_self_modifying
+	thumb_return
 .endm
 
 create_thumb10_variant 0
@@ -305,7 +302,7 @@ thumb15_address_calc_0:
 	mov r0, r9
 
 12:
-	finish_handler_skip_op_self_modifying
+	thumb_return
 
 .global thumb15_address_calc_1
 thumb15_address_calc_1:
@@ -374,7 +371,9 @@ thumb15_address_calc_1:
 	bl read_address_from_handler_32bit
 	mov r7, r10
 10:
-	finish_handler_skip_op_self_modifying
+	thumb_return
 
 address_calc_ignore_thumb:
-	finish_handler_skip_op_self_modifying
\ No newline at end of file
+	thumb_return
+
+#endif
\ No newline at end of file
diff --git a/arm9/source/emu/handle_address_write.s b/arm9/source/emu/handle_address_write.s
index 4ec67c9..090bd29 100644
--- a/arm9/source/emu/handle_address_write.s
+++ b/arm9/source/emu/handle_address_write.s
@@ -1,7 +1,12 @@
+#ifdef SELF_MODIFYING_MIX
 .section .itcm
 
 #include "consts.s"
 
+.global write_address_from_handler_32bit_selfmodify
+write_address_from_handler_32bit_selfmodify:
+	mov r11, r0
+
 .global write_address_from_handler_32bit
 write_address_from_handler_32bit:
 	cmp r9, #0x10000000
@@ -29,11 +34,11 @@ write_address_from_handler_io_32:
 	bic r9, #3 //force align
 	sub r13, r9, #0x04000000
 	cmp r13, #0x20C
-		bxge lr
-	ldr r12,= write_table_32bit_dtcm_new
-	mov r13, r13, lsr #1
-	ldrh r13, [r12, r13]
-	orr pc, r13, #0x01000000	//itcm
+		ldrlt r12,= write_table_32bit_dtcm_new
+		movlt r13, r13, lsr #1
+		ldrlth r13, [r12, r13]
+		orrlt pc, r13, #0x01000000	//itcm
+	bx lr
 
 write_address_from_handler_vram_32:
 	ldr r13,= DISPCNT_copy
@@ -85,93 +90,10 @@ write_address_from_handler_sram_32:
 	strb r11, [r12]
 	bx lr
 
-.global write_address_from_handler_16bit
-write_address_from_handler_16bit:
-	cmp r9, #0x10000000
-	ldrlo pc, [pc, r9, lsr #22]
-	bx lr
-
-	.word write_address_ignore
-	.word write_address_ignore
-	.word write_address_ignore
-	.word write_address_ignore
-	.word write_address_from_handler_io_16
-	.word write_address_ignore
-	.word write_address_from_handler_vram_16
-	.word write_address_ignore
-	.word write_address_from_handler_rom_gpio_16
-	.word write_address_ignore
-	.word write_address_ignore
-	.word write_address_ignore
-	.word write_address_ignore
-	.word write_address_ignore //write_address_from_handler_eeprom_16
-	.word write_address_from_handler_sram_16
-	.word write_address_from_handler_sram_16
-
-write_address_from_handler_io_16:
-	ldr r12,= write_table_16bit_dtcm_new
-	sub r13, r9, #0x04000000
-	cmp r13, #0x20C
-		bxge lr
-	ldrh r13, [r12, r13]
-	orr pc, r13, #0x01000000	//itcm
-
-write_address_from_handler_vram_16:
-	ldr r13,= DISPCNT_copy
-	bic r10, r9, #0xFE0000
-	ldr r12,= 0x06018000
-	ldrh r13, [r13]
-	cmp r10, r12
-		bicge r10, #0x8000
-
-	and r12, r13, #7
-	cmp r12, #3
-	ldrlt r13,= 0x06010000
-	ldrge r13,= 0x06014000
-	cmp r10, r13
-		bge 1f
-
-	//add alpha bit when in 15 bit bitmap mode
-	//caution: this is potentially dangerous!
-	cmp r12, #3
-	cmpne r12, #5
-		orreq r11, #0x8000
-	strh r11, [r10]
-	bx lr
-
-1:
-	add r10, #0x3F0000
-	strh r11, [r10]
-	bx lr
-
-write_address_from_handler_rom_gpio_16:
-	ldr r13,= 0x080000C4
-	subs r13, r9, r13
-		bxlt lr
-	cmp r13, #0x4
-		bxgt lr
-	ldr sp,= address_dtcm + (16 * 1024)
-	push {r0-r3,lr}
-	mov r0, r9
-	mov r1, r11
-	ldr r12,= rio_write
-	blx r12
-	pop {r0-r3,lr}
-	bx lr
-
-write_address_from_handler_sram_16:
-	ldr r12,= 0x01FF0000
-	bic r10, r9, r12
-	sub r10, r10, #((0x0E000000 - MAIN_MEMORY_ADDRESS_SAVE_DATA) & 0x0FF00000) //#0x0BC00000
-	sub r10, r10, #((0x0E000000 - MAIN_MEMORY_ADDRESS_SAVE_DATA) & 0x000FF000) //#0x00010000
-	tst r9, #1
-	movne r11, r11, ror #8
-	bic r10, r10, #1
-	strb r11, [r10]
-	ldr r12,= save_save_work_state_uncached
-	mov r11, #1
-	strb r11, [r12]
-	bx lr
+.global write_address_from_handler_8bit_selfmodify
+write_address_from_handler_8bit_selfmodify:
+	mov r11, r0
+	and r11, #0xFF //byte
 
 .global write_address_from_handler_8bit
 write_address_from_handler_8bit:
@@ -199,11 +121,11 @@ write_address_from_handler_8bit:
 write_address_from_handler_io_8:
 	sub r13, r9, #0x04000000
 	cmp r13, #0x20C
-	bxge lr
-	ldr r12,= write_table_8bit_dtcm_new
-	mov r13, r13, lsl #1
-	ldrh r13, [r12, r13]
-	orr pc, r13, #0x01000000	//itcm
+		ldrlt r12,= write_table_8bit_dtcm_new
+		movlt r13, r13, lsl #1
+		ldrlth r13, [r12, r13]
+		orrlt pc, r13, #0x01000000	//itcm
+	bx lr
 
 write_address_from_handler_vram_8:
 	ldr r13,= DISPCNT_copy
@@ -272,4 +194,6 @@ write_address_wait_control_top8:
 	ldr r13,= (WAITCNT_copy + 1)
 	bic r11, #0x80
 	strb r11, [r13]
-	bx lr
\ No newline at end of file
+	bx lr
+
+#endif
\ No newline at end of file
diff --git a/arm9/source/emu/memWrite16.s b/arm9/source/emu/memWrite16.s
new file mode 100644
index 0000000..bd6e386
--- /dev/null
+++ b/arm9/source/emu/memWrite16.s
@@ -0,0 +1,98 @@
+#ifdef SELF_MODIFYING_MIX
+.section .itcm
+
+#include "consts.s"
+
+.global write_address_from_handler_16bit_selfmodify
+write_address_from_handler_16bit_selfmodify:
+	mov r11, r0, lsl #16
+	mov r11, r11, lsr #16
+
+.global write_address_from_handler_16bit
+write_address_from_handler_16bit:
+	cmp r9, #0x10000000
+	ldrlo pc, [pc, r9, lsr #22]
+	bx lr
+
+	.word write_address_ignore
+	.word write_address_ignore
+	.word write_address_ignore
+	.word write_address_ignore
+	.word write_address_from_handler_io_16
+	.word write_address_ignore
+	.word write_address_from_handler_vram_16
+	.word write_address_ignore
+	.word write_address_from_handler_rom_gpio_16
+	.word write_address_ignore
+	.word write_address_ignore
+	.word write_address_ignore
+	.word write_address_ignore
+	.word write_address_ignore //write_address_from_handler_eeprom_16
+	.word write_address_from_handler_sram_16
+	.word write_address_from_handler_sram_16
+
+write_address_from_handler_io_16:
+	ldr r12,= write_table_16bit_dtcm_new
+	sub r13, r9, #0x04000000
+	cmp r13, #0x20C
+	    ldrlth r13, [r12, r13]
+	    orrlt pc, r13, #0x01000000	//itcm
+    bx lr
+
+write_address_from_handler_vram_16:
+	ldr r13,= DISPCNT_copy
+	bic r10, r9, #0xFE0000
+	ldr r12,= 0x06018000
+	ldrh r13, [r13]
+	cmp r10, r12
+		bicge r10, #0x8000
+
+	and r12, r13, #7
+	cmp r12, #3
+	ldrlt r13,= 0x06010000
+	ldrge r13,= 0x06014000
+	cmp r10, r13
+		bge 1f
+
+	//add alpha bit when in 15 bit bitmap mode
+	//caution: this is potentially dangerous!
+	cmp r12, #3
+	cmpne r12, #5
+		orreq r11, #0x8000
+	strh r11, [r10]
+	bx lr
+
+1:
+	add r10, #0x3F0000
+	strh r11, [r10]
+	bx lr
+
+write_address_from_handler_rom_gpio_16:
+	ldr r13,= 0x080000C4
+	subs r13, r9, r13
+		bxlt lr
+	cmp r13, #0x4
+		bxgt lr
+	ldr sp,= address_dtcm + (16 * 1024)
+	push {r0-r3,lr}
+	mov r0, r9
+	mov r1, r11
+	ldr r12,= rio_write
+	blx r12
+	pop {r0-r3,lr}
+	bx lr
+
+write_address_from_handler_sram_16:
+	ldr r12,= 0x01FF0000
+	bic r10, r9, r12
+	sub r10, r10, #((0x0E000000 - MAIN_MEMORY_ADDRESS_SAVE_DATA) & 0x0FF00000) //#0x0BC00000
+	sub r10, r10, #((0x0E000000 - MAIN_MEMORY_ADDRESS_SAVE_DATA) & 0x000FF000) //#0x00010000
+	tst r9, #1
+	movne r11, r11, ror #8
+	bic r10, r10, #1
+	strb r11, [r10]
+	ldr r12,= save_save_work_state_uncached
+	mov r11, #1
+	strb r11, [r12]
+	bx lr
+#endif
\ No newline at end of file
diff --git a/arm9/source/emu/selfModifyingMix.s b/arm9/source/emu/selfModifyingMix.s
new file mode 100644
index 0000000..77305b0
--- /dev/null
+++ b/arm9/source/emu/selfModifyingMix.s
@@ -0,0 +1,7 @@
+.section .itcm
+#define SELF_MODIFYING_MIX
+#include "cpuArmLo.s"
+#include "handle_address_write.s"
+#include "cpuThumb.s"
+#include "memWrite16.s"
+#include "cpuArmLoHalfword.s"
\ No newline at end of file