dummy_lwc_w32_ccw32.toml

name = "dummy_lwc_w32_ccw32"
description = "Implementation of the dummy_lwc cipher and hash with W=32 and CCW=32"

[language]
vhdl.standard = "2008"
vhdl.synopsys = false

[rtl]
sources = [
    "src_rtl/v1/design_pkg.vhd",
    "src_rtl/LWC_config_32.vhd",
    "src_rtl/LWC/NIST_LWAPI_pkg.vhd",
    "src_rtl/SPDRam.vhd",
    "src_rtl/CryptoCore.vhd",
    "src_rtl/LWC/SIPO.vhd",
    "src_rtl/LWC/PISO.vhd",
    "src_rtl/LWC/FIFO.vhd",
    "src_rtl/LWC/PreProcessor.vhd",
    "src_rtl/LWC/PostProcessor.vhd",
    "src_rtl/LWC/LWC.vhd",
]
top = "LWC"
# top = "LWC_wrapper" # if using LWC_wrapper
clock.port = "clk"

[tb]
top = 'LWC_TB'
sources = [
    # "../LWC_tb/std_logic_1164_additions.vhdl", 
    "../LWC_tb/LWC_TB.vhd"
]

[tb.generics]
G_FNAME_PDI.file = "KAT/32/pdi.txt"
G_FNAME_SDI.file = "KAT/32/sdi.txt"
G_FNAME_DO.file = "KAT/32/do.txt"
G_TEST_MODE = 0                     # 0: no stalls, 1: stall both inputs and output, 4: timing
G_MAX_FAILURES = 0
G_TIMEOUT_CYCLES = 1_000
G_PDI_STALLS = 7
G_SDI_STALLS = 13
G_DO_STALLS = 21
G_RANDOM_STALL = false              # true
# G_PRERESET_WAIT_PS = 100_000
G_CLK_PERIOD_PS = 10_000
# G_INPUT_DELAY_PS = 2_500

[lwc]
aead.algorithm = "dummy_lwc"
aead.key_reuse = true
hash.algorithm = "dummy_lwc"

ports.pdi.bit_width = 32
ports.sdi.bit_width = 32