AXISoCQuadCoreModule_TopLevel_CPUExtReset_axiSlave.v

`timescale 1ns/1ps
`default_nettype none
// PLEASE READ THIS, IT MAY SAVE YOU SOME TIME AND MONEY, THANK YOU!
// * This file was generated by Quokka FPGA Toolkit.
// * Generated code is your property, do whatever you want with it
// * Place custom code between [BEGIN USER ***] and [END USER ***].
// * CAUTION: All code outside of [USER] scope is subject to regeneration.
// * Bad things happen sometimes in developer's life,
//   it is recommended to use source control management software (e.g. git, bzr etc) to keep your custom code safe'n'sound.
// * Internal structure of code is subject to change.
//   You can use some of signals in custom code, but most likely they will not exist in future (e.g. will get shorter or gone completely)
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//
// DISCLAIMER:
//   Code comes AS-IS, it is your responsibility to make sure it is working as expected
//   no responsibility will be taken for any loss or damage caused by use of Quokka toolkit.
//
// System configuration name is AXISoCQuadCoreModule_TopLevel_CPUExtReset_axiSlave, clock frequency is 1Hz, Embedded
// FSM summary
// -- Packages
module AXISoCQuadCoreModule_TopLevel_CPUExtReset_axiSlave
(
	// [BEGIN USER PORTS]
	// [END USER PORTS]
	input wire BoardSignals_Clock,
	input wire BoardSignals_Reset,
	input wire BoardSignals_Running,
	input wire BoardSignals_Starting,
	input wire BoardSignals_Started,
	input wire inARREADY,
	input wire inAWREADY,
	input wire inBVALID,
	input wire [7:0] inRDATA0,
	input wire [7:0] inRDATA1,
	input wire [7:0] inRDATA2,
	input wire [7:0] inRDATA3,
	input wire inRVALID,
	input wire inWREADY,
	input wire [221:0] M2S,
	output wire [31:0] outARADDR,
	output wire outARREADYConfirming,
	output wire outARVALID,
	output wire [31:0] outAWADDR,
	output wire outAWREADYConfirming,
	output wire outAWVALID,
	output wire outReadTXCompleting,
	output wire [7:0] outWDATA0,
	output wire [7:0] outWDATA1,
	output wire [7:0] outWDATA2,
	output wire [7:0] outWDATA3,
	output wire outWREADYConfirming,
	output wire outWriteTXCompleting,
	output wire [3:0] outWSTRB,
	output wire outWVALID,
	output wire [73:0] S2M
);
	// [BEGIN USER SIGNALS]
	// [END USER SIGNALS]
	localparam HiSignal = 1'b1;
	localparam LoSignal = 1'b0;
	wire Zero = 1'b0;
	wire One = 1'b1;
	wire true = 1'b1;
	wire false = 1'b0;
	wire [1: 0] size = 2'b10;
	wire [1: 0] AXI4NonBufferedSlaveModule_L86F50T70_Expr = 2'b01;
	wire [1: 0] AXI4NonBufferedSlaveModule_L90F53T74_Expr = 2'b01;
	wire [1: 0] AXI4NonBufferedSlaveModule_L92F52T72_Expr = 2'b10;
	wire [1: 0] AXI4NonBufferedSlaveModule_L92F95T115_Expr = 2'b10;
	wire [1: 0] AXI4NonBufferedSlaveModule_L87F49T68_Expr = 2'b10;
	wire [1: 0] AXI4NonBufferedSlaveModule_L91F51T72_Expr = 2'b01;
	wire [1: 0] AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L117F13L130T14_AXI4NonBufferedSlaveModule_L119F22T43_Expr = 2'b00;
	wire [1: 0] AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L117F13L130T14_AXI4NonBufferedSlaveModule_L120F41T61_Expr = 2'b01;
	wire [1: 0] AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L117F13L130T14_AXI4NonBufferedSlaveModule_L122F22T42_Expr = 2'b01;
	wire [1: 0] AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L117F13L130T14_AXI4NonBufferedSlaveModule_L124F45T64_Expr = 2'b10;
	wire [1: 0] AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L117F13L130T14_AXI4NonBufferedSlaveModule_L126F22T41_Expr = 2'b10;
	wire [1: 0] AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L117F13L130T14_AXI4NonBufferedSlaveModule_L128F45T65_Expr = 2'b01;
	wire [1: 0] AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L132F13L145T14_AXI4NonBufferedSlaveModule_L134F22T44_Expr = 2'b00;
	wire [1: 0] AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L132F13L145T14_AXI4NonBufferedSlaveModule_L135F44T65_Expr = 2'b01;
	wire [1: 0] AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L132F13L145T14_AXI4NonBufferedSlaveModule_L137F22T43_Expr = 2'b01;
	wire [1: 0] AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L132F13L145T14_AXI4NonBufferedSlaveModule_L139F48T68_Expr = 2'b10;
	wire [1: 0] AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L132F13L145T14_AXI4NonBufferedSlaveModule_L141F22T42_Expr = 2'b10;
	wire [1: 0] AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L132F13L145T14_AXI4NonBufferedSlaveModule_L143F48T69_Expr = 2'b01;
	wire [1: 0] AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L147F13L160T14_AXI4NonBufferedSlaveModule_L149F22T44_Expr = 2'b00;
	wire [1: 0] AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L147F13L160T14_AXI4NonBufferedSlaveModule_L150F43T64_Expr = 2'b01;
	wire [1: 0] AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L147F13L160T14_AXI4NonBufferedSlaveModule_L152F22T43_Expr = 2'b01;
	wire [1: 0] AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L147F13L160T14_AXI4NonBufferedSlaveModule_L154F47T67_Expr = 2'b10;
	wire [1: 0] AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L147F13L160T14_AXI4NonBufferedSlaveModule_L156F22T42_Expr = 2'b10;
	wire [1: 0] AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L147F13L160T14_AXI4NonBufferedSlaveModule_L158F47T68_Expr = 2'b01;
	wire [1: 0] AXI4NonBufferedSlaveModule_L99F62T82_Expr = 2'b01;
	wire [1: 0] AXI4NonBufferedSlaveModule_L99F107T126_Expr = 2'b10;
	wire [1: 0] AXI4NonBufferedSlaveModule_L104F65T86_Expr = 2'b01;
	wire [1: 0] AXI4NonBufferedSlaveModule_L104F114T134_Expr = 2'b10;
	wire [1: 0] AXI4NonBufferedSlaveModule_L108F63T84_Expr = 2'b01;
	wire [1: 0] AXI4NonBufferedSlaveModule_L108F111T131_Expr = 2'b10;
	wire [1: 0] AXI4NonBufferedSlaveModule_L59F29T41_Expr = 2'b00;
	wire AXI4_S_R_L26F29T33_Expr = 1'b1;
	wire [1: 0] AXI4NonBufferedSlaveModule_L75F29T41_Expr = 2'b00;
	wire Inputs_inARREADY;
	wire Inputs_inAWREADY;
	wire Inputs_inBVALID;
	wire Inputs_inRVALID;
	wire Inputs_inWREADY;
	wire [7: 0] Inputs_M2S_R_AR_ARID;
	wire [31: 0] Inputs_M2S_R_AR_ARADDR;
	wire [7: 0] Inputs_M2S_R_AR_ARLEN;
	wire [2: 0] Inputs_M2S_R_AR_ARSIZE;
	wire [1: 0] Inputs_M2S_R_AR_ARBURST;
	wire [1: 0] Inputs_M2S_R_AR_ARLOCK;
	wire [3: 0] Inputs_M2S_R_AR_ARCACHE;
	wire [2: 0] Inputs_M2S_R_AR_ARPROT;
	wire [3: 0] Inputs_M2S_R_AR_ARQOS;
	wire [7: 0] Inputs_M2S_R_AR_ARREGION;
	wire [7: 0] Inputs_M2S_R_AR_ARUSER;
	wire Inputs_M2S_R_AR_ARVALID;
	wire Inputs_M2S_R_R_RREADY;
	wire [7: 0] Inputs_M2S_W_AW_AWID;
	wire [31: 0] Inputs_M2S_W_AW_AWADDR;
	wire [7: 0] Inputs_M2S_W_AW_AWLEN;
	wire [2: 0] Inputs_M2S_W_AW_AWSIZE;
	wire [1: 0] Inputs_M2S_W_AW_AWBURST;
	wire [1: 0] Inputs_M2S_W_AW_AWLOCK;
	wire [3: 0] Inputs_M2S_W_AW_AWCACHE;
	wire [2: 0] Inputs_M2S_W_AW_AWPROT;
	wire [3: 0] Inputs_M2S_W_AW_AWQOS;
	wire [7: 0] Inputs_M2S_W_AW_AWREGION;
	wire [7: 0] Inputs_M2S_W_AW_AWUSER;
	wire Inputs_M2S_W_AW_AWVALID;
	wire [7: 0] Inputs_M2S_W_W_WID;
	wire [3: 0] Inputs_M2S_W_W_WSTRB;
	wire Inputs_M2S_W_W_WLAST;
	wire [7: 0] Inputs_M2S_W_W_WUSER;
	wire Inputs_M2S_W_W_WVALID;
	wire Inputs_M2S_W_B_BREADY;
	reg [1: 0] NextState_readFSM;
	reg [1: 0] NextState_writeAWFSM;
	reg [1: 0] NextState_writeWFSM;
	wire internalARREADY;
	wire internalAWREADY;
	wire internalBVALID;
	wire internalRVALID;
	wire internalWREADY;
	wire readTXCompleting;
	wire writeTXCompleting;
	reg [1: 0] State_readFSM = 2'b00;
	wire [1: 0] State_readFSMDefault = 2'b00;
	reg [1: 0] State_writeAWFSM = 2'b00;
	wire [1: 0] State_writeAWFSMDefault = 2'b00;
	reg [1: 0] State_writeWFSM = 2'b00;
	wire [1: 0] State_writeWFSMDefault = 2'b00;
	wire AXI4NonBufferedSlaveModule_L86F33T90_Expr;
	wire AXI4NonBufferedSlaveModule_L86F33T90_Expr_1;
	wire AXI4NonBufferedSlaveModule_L86F33T90_Expr_2;
	wire AXI4NonBufferedSlaveModule_L90F33T94_Expr;
	wire AXI4NonBufferedSlaveModule_L90F33T94_Expr_1;
	wire AXI4NonBufferedSlaveModule_L90F33T94_Expr_2;
	wire AXI4NonBufferedSlaveModule_L92F32T134_Expr;
	wire AXI4NonBufferedSlaveModule_L92F32T134_Expr_1;
	wire AXI4NonBufferedSlaveModule_L92F32T134_Expr_2;
	wire AXI4NonBufferedSlaveModule_L92F32T115_Expr;
	wire AXI4NonBufferedSlaveModule_L92F32T115_Expr_1;
	wire AXI4NonBufferedSlaveModule_L92F32T115_Expr_2;
	wire AXI4NonBufferedSlaveModule_L87F32T87_Expr;
	wire AXI4NonBufferedSlaveModule_L87F32T87_Expr_1;
	wire AXI4NonBufferedSlaveModule_L87F32T87_Expr_2;
	wire AXI4NonBufferedSlaveModule_L91F32T91_Expr;
	wire AXI4NonBufferedSlaveModule_L91F32T91_Expr_1;
	wire AXI4NonBufferedSlaveModule_L91F32T91_Expr_2;
	wire AXI4NonBufferedSlaveModule_L83F34T73_Expr;
	wire AXI4NonBufferedSlaveModule_L83F34T73_Expr_1;
	wire AXI4NonBufferedSlaveModule_L83F34T73_Expr_2;
	wire AXI4NonBufferedSlaveModule_L84F35T74_Expr;
	wire AXI4NonBufferedSlaveModule_L84F35T74_Expr_1;
	wire AXI4NonBufferedSlaveModule_L84F35T74_Expr_2;
	wire AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L117F13L130T14_AXI4NonBufferedSlaveModule_L123F25T67_Expr;
	wire AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L117F13L130T14_AXI4NonBufferedSlaveModule_L123F25T67_Expr_1;
	wire AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L117F13L130T14_AXI4NonBufferedSlaveModule_L123F25T67_Expr_2;
	wire AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L132F13L145T14_AXI4NonBufferedSlaveModule_L138F25T67_Expr;
	wire AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L132F13L145T14_AXI4NonBufferedSlaveModule_L138F25T67_Expr_1;
	wire AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L132F13L145T14_AXI4NonBufferedSlaveModule_L138F25T67_Expr_2;
	wire AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L147F13L160T14_AXI4NonBufferedSlaveModule_L153F25T64_Expr;
	wire AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L147F13L160T14_AXI4NonBufferedSlaveModule_L153F25T64_Expr_1;
	wire AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L147F13L160T14_AXI4NonBufferedSlaveModule_L153F25T64_Expr_2;
	wire AXI4NonBufferedSlaveModule_L99F45T126_Expr;
	wire AXI4NonBufferedSlaveModule_L99F45T126_Expr_1;
	wire AXI4NonBufferedSlaveModule_L99F45T126_Expr_2;
	wire AXI4NonBufferedSlaveModule_L104F45T134_Expr;
	wire AXI4NonBufferedSlaveModule_L104F45T134_Expr_1;
	wire AXI4NonBufferedSlaveModule_L104F45T134_Expr_2;
	wire AXI4NonBufferedSlaveModule_L108F44T131_Expr;
	wire AXI4NonBufferedSlaveModule_L108F44T131_Expr_1;
	wire AXI4NonBufferedSlaveModule_L108F44T131_Expr_2;
	wire AXI4NonBufferedSlaveModule_L86F33T70_Expr;
	wire signed [2: 0] AXI4NonBufferedSlaveModule_L86F33T70_ExprLhs;
	wire signed [2: 0] AXI4NonBufferedSlaveModule_L86F33T70_ExprRhs;
	wire AXI4NonBufferedSlaveModule_L90F33T74_Expr;
	wire signed [2: 0] AXI4NonBufferedSlaveModule_L90F33T74_ExprLhs;
	wire signed [2: 0] AXI4NonBufferedSlaveModule_L90F33T74_ExprRhs;
	wire AXI4NonBufferedSlaveModule_L92F32T72_Expr;
	wire signed [2: 0] AXI4NonBufferedSlaveModule_L92F32T72_ExprLhs;
	wire signed [2: 0] AXI4NonBufferedSlaveModule_L92F32T72_ExprRhs;
	wire AXI4NonBufferedSlaveModule_L92F76T115_Expr;
	wire signed [2: 0] AXI4NonBufferedSlaveModule_L92F76T115_ExprLhs;
	wire signed [2: 0] AXI4NonBufferedSlaveModule_L92F76T115_ExprRhs;
	wire AXI4NonBufferedSlaveModule_L87F32T68_Expr;
	wire signed [2: 0] AXI4NonBufferedSlaveModule_L87F32T68_ExprLhs;
	wire signed [2: 0] AXI4NonBufferedSlaveModule_L87F32T68_ExprRhs;
	wire AXI4NonBufferedSlaveModule_L91F32T72_Expr;
	wire signed [2: 0] AXI4NonBufferedSlaveModule_L91F32T72_ExprLhs;
	wire signed [2: 0] AXI4NonBufferedSlaveModule_L91F32T72_ExprRhs;
	wire AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L117F13L130T14_AXI4NonBufferedSlaveModule_L119F17L121T27_Case;
	wire signed [2: 0] AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L117F13L130T14_AXI4NonBufferedSlaveModule_L119F17L121T27_CaseLhs;
	wire signed [2: 0] AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L117F13L130T14_AXI4NonBufferedSlaveModule_L119F17L121T27_CaseRhs;
	wire AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L117F13L130T14_AXI4NonBufferedSlaveModule_L122F17L125T27_Case;
	wire signed [2: 0] AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L117F13L130T14_AXI4NonBufferedSlaveModule_L122F17L125T27_CaseLhs;
	wire signed [2: 0] AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L117F13L130T14_AXI4NonBufferedSlaveModule_L122F17L125T27_CaseRhs;
	wire AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L117F13L130T14_AXI4NonBufferedSlaveModule_L126F17L129T27_Case;
	wire signed [2: 0] AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L117F13L130T14_AXI4NonBufferedSlaveModule_L126F17L129T27_CaseLhs;
	wire signed [2: 0] AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L117F13L130T14_AXI4NonBufferedSlaveModule_L126F17L129T27_CaseRhs;
	wire AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L132F13L145T14_AXI4NonBufferedSlaveModule_L134F17L136T27_Case;
	wire signed [2: 0] AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L132F13L145T14_AXI4NonBufferedSlaveModule_L134F17L136T27_CaseLhs;
	wire signed [2: 0] AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L132F13L145T14_AXI4NonBufferedSlaveModule_L134F17L136T27_CaseRhs;
	wire AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L132F13L145T14_AXI4NonBufferedSlaveModule_L137F17L140T27_Case;
	wire signed [2: 0] AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L132F13L145T14_AXI4NonBufferedSlaveModule_L137F17L140T27_CaseLhs;
	wire signed [2: 0] AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L132F13L145T14_AXI4NonBufferedSlaveModule_L137F17L140T27_CaseRhs;
	wire AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L132F13L145T14_AXI4NonBufferedSlaveModule_L141F17L144T27_Case;
	wire signed [2: 0] AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L132F13L145T14_AXI4NonBufferedSlaveModule_L141F17L144T27_CaseLhs;
	wire signed [2: 0] AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L132F13L145T14_AXI4NonBufferedSlaveModule_L141F17L144T27_CaseRhs;
	wire AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L147F13L160T14_AXI4NonBufferedSlaveModule_L149F17L151T27_Case;
	wire signed [2: 0] AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L147F13L160T14_AXI4NonBufferedSlaveModule_L149F17L151T27_CaseLhs;
	wire signed [2: 0] AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L147F13L160T14_AXI4NonBufferedSlaveModule_L149F17L151T27_CaseRhs;
	wire AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L147F13L160T14_AXI4NonBufferedSlaveModule_L152F17L155T27_Case;
	wire signed [2: 0] AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L147F13L160T14_AXI4NonBufferedSlaveModule_L152F17L155T27_CaseLhs;
	wire signed [2: 0] AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L147F13L160T14_AXI4NonBufferedSlaveModule_L152F17L155T27_CaseRhs;
	wire AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L147F13L160T14_AXI4NonBufferedSlaveModule_L156F17L159T27_Case;
	wire signed [2: 0] AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L147F13L160T14_AXI4NonBufferedSlaveModule_L156F17L159T27_CaseLhs;
	wire signed [2: 0] AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L147F13L160T14_AXI4NonBufferedSlaveModule_L156F17L159T27_CaseRhs;
	wire AXI4NonBufferedSlaveModule_L99F45T82_Expr;
	wire signed [2: 0] AXI4NonBufferedSlaveModule_L99F45T82_ExprLhs;
	wire signed [2: 0] AXI4NonBufferedSlaveModule_L99F45T82_ExprRhs;
	wire AXI4NonBufferedSlaveModule_L99F86T126_Expr;
	wire signed [2: 0] AXI4NonBufferedSlaveModule_L99F86T126_ExprLhs;
	wire signed [2: 0] AXI4NonBufferedSlaveModule_L99F86T126_ExprRhs;
	wire AXI4NonBufferedSlaveModule_L104F45T86_Expr;
	wire signed [2: 0] AXI4NonBufferedSlaveModule_L104F45T86_ExprLhs;
	wire signed [2: 0] AXI4NonBufferedSlaveModule_L104F45T86_ExprRhs;
	wire AXI4NonBufferedSlaveModule_L104F90T134_Expr;
	wire signed [2: 0] AXI4NonBufferedSlaveModule_L104F90T134_ExprLhs;
	wire signed [2: 0] AXI4NonBufferedSlaveModule_L104F90T134_ExprRhs;
	wire AXI4NonBufferedSlaveModule_L108F44T84_Expr;
	wire signed [2: 0] AXI4NonBufferedSlaveModule_L108F44T84_ExprLhs;
	wire signed [2: 0] AXI4NonBufferedSlaveModule_L108F44T84_ExprRhs;
	wire AXI4NonBufferedSlaveModule_L108F88T131_Expr;
	wire signed [2: 0] AXI4NonBufferedSlaveModule_L108F88T131_ExprLhs;
	wire signed [2: 0] AXI4NonBufferedSlaveModule_L108F88T131_ExprRhs;
	wire [7 : 0] Inputs_inRDATA [0 : 3];
	wire [7 : 0] Inputs_M2S_W_W_WDATA [0 : 3];
	always @ (posedge BoardSignals_Clock)
	begin
		if ((BoardSignals_Reset == 1))
		begin
			State_readFSM <= State_readFSMDefault;
			State_writeAWFSM <= State_writeAWFSMDefault;
			State_writeWFSM <= State_writeWFSMDefault;
		end
		else
		begin
			State_readFSM <= NextState_readFSM;
			State_writeAWFSM <= NextState_writeAWFSM;
			State_writeWFSM <= NextState_writeWFSM;
		end
	end
	assign AXI4NonBufferedSlaveModule_L86F33T70_Expr = AXI4NonBufferedSlaveModule_L86F33T70_ExprLhs == AXI4NonBufferedSlaveModule_L86F33T70_ExprRhs ? 1'b1 : 1'b0;
	assign AXI4NonBufferedSlaveModule_L90F33T74_Expr = AXI4NonBufferedSlaveModule_L90F33T74_ExprLhs == AXI4NonBufferedSlaveModule_L90F33T74_ExprRhs ? 1'b1 : 1'b0;
	assign AXI4NonBufferedSlaveModule_L92F32T72_Expr = AXI4NonBufferedSlaveModule_L92F32T72_ExprLhs == AXI4NonBufferedSlaveModule_L92F32T72_ExprRhs ? 1'b1 : 1'b0;
	assign AXI4NonBufferedSlaveModule_L92F76T115_Expr = AXI4NonBufferedSlaveModule_L92F76T115_ExprLhs == AXI4NonBufferedSlaveModule_L92F76T115_ExprRhs ? 1'b1 : 1'b0;
	assign AXI4NonBufferedSlaveModule_L87F32T68_Expr = AXI4NonBufferedSlaveModule_L87F32T68_ExprLhs == AXI4NonBufferedSlaveModule_L87F32T68_ExprRhs ? 1'b1 : 1'b0;
	assign AXI4NonBufferedSlaveModule_L91F32T72_Expr = AXI4NonBufferedSlaveModule_L91F32T72_ExprLhs == AXI4NonBufferedSlaveModule_L91F32T72_ExprRhs ? 1'b1 : 1'b0;
	assign AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L117F13L130T14_AXI4NonBufferedSlaveModule_L119F17L121T27_Case = AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L117F13L130T14_AXI4NonBufferedSlaveModule_L119F17L121T27_CaseLhs == AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L117F13L130T14_AXI4NonBufferedSlaveModule_L119F17L121T27_CaseRhs ? 1'b1 : 1'b0;
	assign AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L117F13L130T14_AXI4NonBufferedSlaveModule_L122F17L125T27_Case = AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L117F13L130T14_AXI4NonBufferedSlaveModule_L122F17L125T27_CaseLhs == AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L117F13L130T14_AXI4NonBufferedSlaveModule_L122F17L125T27_CaseRhs ? 1'b1 : 1'b0;
	assign AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L117F13L130T14_AXI4NonBufferedSlaveModule_L126F17L129T27_Case = AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L117F13L130T14_AXI4NonBufferedSlaveModule_L126F17L129T27_CaseLhs == AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L117F13L130T14_AXI4NonBufferedSlaveModule_L126F17L129T27_CaseRhs ? 1'b1 : 1'b0;
	assign AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L132F13L145T14_AXI4NonBufferedSlaveModule_L134F17L136T27_Case = AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L132F13L145T14_AXI4NonBufferedSlaveModule_L134F17L136T27_CaseLhs == AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L132F13L145T14_AXI4NonBufferedSlaveModule_L134F17L136T27_CaseRhs ? 1'b1 : 1'b0;
	assign AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L132F13L145T14_AXI4NonBufferedSlaveModule_L137F17L140T27_Case = AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L132F13L145T14_AXI4NonBufferedSlaveModule_L137F17L140T27_CaseLhs == AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L132F13L145T14_AXI4NonBufferedSlaveModule_L137F17L140T27_CaseRhs ? 1'b1 : 1'b0;
	assign AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L132F13L145T14_AXI4NonBufferedSlaveModule_L141F17L144T27_Case = AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L132F13L145T14_AXI4NonBufferedSlaveModule_L141F17L144T27_CaseLhs == AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L132F13L145T14_AXI4NonBufferedSlaveModule_L141F17L144T27_CaseRhs ? 1'b1 : 1'b0;
	assign AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L147F13L160T14_AXI4NonBufferedSlaveModule_L149F17L151T27_Case = AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L147F13L160T14_AXI4NonBufferedSlaveModule_L149F17L151T27_CaseLhs == AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L147F13L160T14_AXI4NonBufferedSlaveModule_L149F17L151T27_CaseRhs ? 1'b1 : 1'b0;
	assign AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L147F13L160T14_AXI4NonBufferedSlaveModule_L152F17L155T27_Case = AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L147F13L160T14_AXI4NonBufferedSlaveModule_L152F17L155T27_CaseLhs == AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L147F13L160T14_AXI4NonBufferedSlaveModule_L152F17L155T27_CaseRhs ? 1'b1 : 1'b0;
	assign AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L147F13L160T14_AXI4NonBufferedSlaveModule_L156F17L159T27_Case = AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L147F13L160T14_AXI4NonBufferedSlaveModule_L156F17L159T27_CaseLhs == AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L147F13L160T14_AXI4NonBufferedSlaveModule_L156F17L159T27_CaseRhs ? 1'b1 : 1'b0;
	assign AXI4NonBufferedSlaveModule_L99F45T82_Expr = AXI4NonBufferedSlaveModule_L99F45T82_ExprLhs == AXI4NonBufferedSlaveModule_L99F45T82_ExprRhs ? 1'b1 : 1'b0;
	assign AXI4NonBufferedSlaveModule_L99F86T126_Expr = AXI4NonBufferedSlaveModule_L99F86T126_ExprLhs == AXI4NonBufferedSlaveModule_L99F86T126_ExprRhs ? 1'b1 : 1'b0;
	assign AXI4NonBufferedSlaveModule_L104F45T86_Expr = AXI4NonBufferedSlaveModule_L104F45T86_ExprLhs == AXI4NonBufferedSlaveModule_L104F45T86_ExprRhs ? 1'b1 : 1'b0;
	assign AXI4NonBufferedSlaveModule_L104F90T134_Expr = AXI4NonBufferedSlaveModule_L104F90T134_ExprLhs == AXI4NonBufferedSlaveModule_L104F90T134_ExprRhs ? 1'b1 : 1'b0;
	assign AXI4NonBufferedSlaveModule_L108F44T84_Expr = AXI4NonBufferedSlaveModule_L108F44T84_ExprLhs == AXI4NonBufferedSlaveModule_L108F44T84_ExprRhs ? 1'b1 : 1'b0;
	assign AXI4NonBufferedSlaveModule_L108F88T131_Expr = AXI4NonBufferedSlaveModule_L108F88T131_ExprLhs == AXI4NonBufferedSlaveModule_L108F88T131_ExprRhs ? 1'b1 : 1'b0;
	assign AXI4NonBufferedSlaveModule_L86F33T90_Expr = AXI4NonBufferedSlaveModule_L86F33T90_Expr_1 & AXI4NonBufferedSlaveModule_L86F33T90_Expr_2;
	assign AXI4NonBufferedSlaveModule_L90F33T94_Expr = AXI4NonBufferedSlaveModule_L90F33T94_Expr_1 & AXI4NonBufferedSlaveModule_L90F33T94_Expr_2;
	assign AXI4NonBufferedSlaveModule_L92F32T134_Expr = AXI4NonBufferedSlaveModule_L92F32T134_Expr_1 & AXI4NonBufferedSlaveModule_L92F32T134_Expr_2;
	assign AXI4NonBufferedSlaveModule_L92F32T115_Expr = AXI4NonBufferedSlaveModule_L92F32T115_Expr_1 & AXI4NonBufferedSlaveModule_L92F32T115_Expr_2;
	assign AXI4NonBufferedSlaveModule_L87F32T87_Expr = AXI4NonBufferedSlaveModule_L87F32T87_Expr_1 & AXI4NonBufferedSlaveModule_L87F32T87_Expr_2;
	assign AXI4NonBufferedSlaveModule_L91F32T91_Expr = AXI4NonBufferedSlaveModule_L91F32T91_Expr_1 & AXI4NonBufferedSlaveModule_L91F32T91_Expr_2;
	assign AXI4NonBufferedSlaveModule_L83F34T73_Expr = AXI4NonBufferedSlaveModule_L83F34T73_Expr_1 & AXI4NonBufferedSlaveModule_L83F34T73_Expr_2;
	assign AXI4NonBufferedSlaveModule_L84F35T74_Expr = AXI4NonBufferedSlaveModule_L84F35T74_Expr_1 & AXI4NonBufferedSlaveModule_L84F35T74_Expr_2;
	assign AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L117F13L130T14_AXI4NonBufferedSlaveModule_L123F25T67_Expr = AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L117F13L130T14_AXI4NonBufferedSlaveModule_L123F25T67_Expr_1 & AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L117F13L130T14_AXI4NonBufferedSlaveModule_L123F25T67_Expr_2;
	assign AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L132F13L145T14_AXI4NonBufferedSlaveModule_L138F25T67_Expr = AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L132F13L145T14_AXI4NonBufferedSlaveModule_L138F25T67_Expr_1 & AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L132F13L145T14_AXI4NonBufferedSlaveModule_L138F25T67_Expr_2;
	assign AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L147F13L160T14_AXI4NonBufferedSlaveModule_L153F25T64_Expr = AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L147F13L160T14_AXI4NonBufferedSlaveModule_L153F25T64_Expr_1 & AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L147F13L160T14_AXI4NonBufferedSlaveModule_L153F25T64_Expr_2;
	assign AXI4NonBufferedSlaveModule_L99F45T126_Expr = AXI4NonBufferedSlaveModule_L99F45T126_Expr_1 & AXI4NonBufferedSlaveModule_L99F45T126_Expr_2;
	assign AXI4NonBufferedSlaveModule_L104F45T134_Expr = AXI4NonBufferedSlaveModule_L104F45T134_Expr_1 & AXI4NonBufferedSlaveModule_L104F45T134_Expr_2;
	assign AXI4NonBufferedSlaveModule_L108F44T131_Expr = AXI4NonBufferedSlaveModule_L108F44T131_Expr_1 & AXI4NonBufferedSlaveModule_L108F44T131_Expr_2;
	always @ (*)
	begin
		NextState_readFSM = State_readFSM;
		NextState_writeAWFSM = State_writeAWFSM;
		NextState_writeWFSM = State_writeWFSM;
		if ((AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L117F13L130T14_AXI4NonBufferedSlaveModule_L119F17L121T27_Case == 1))
		begin
			NextState_readFSM = AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L117F13L130T14_AXI4NonBufferedSlaveModule_L120F41T61_Expr;
		end
		else if ((AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L117F13L130T14_AXI4NonBufferedSlaveModule_L122F17L125T27_Case == 1))
		begin
			if ((AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L117F13L130T14_AXI4NonBufferedSlaveModule_L123F25T67_Expr == 1))
			begin
				NextState_readFSM = AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L117F13L130T14_AXI4NonBufferedSlaveModule_L124F45T64_Expr;
			end
		end
		else if ((AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L117F13L130T14_AXI4NonBufferedSlaveModule_L126F17L129T27_Case == 1))
		begin
			if ((readTXCompleting == 1))
			begin
				NextState_readFSM = AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L117F13L130T14_AXI4NonBufferedSlaveModule_L128F45T65_Expr;
			end
		end
		if ((AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L132F13L145T14_AXI4NonBufferedSlaveModule_L134F17L136T27_Case == 1))
		begin
			NextState_writeAWFSM = AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L132F13L145T14_AXI4NonBufferedSlaveModule_L135F44T65_Expr;
		end
		else if ((AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L132F13L145T14_AXI4NonBufferedSlaveModule_L137F17L140T27_Case == 1))
		begin
			if ((AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L132F13L145T14_AXI4NonBufferedSlaveModule_L138F25T67_Expr == 1))
			begin
				NextState_writeAWFSM = AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L132F13L145T14_AXI4NonBufferedSlaveModule_L139F48T68_Expr;
			end
		end
		else if ((AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L132F13L145T14_AXI4NonBufferedSlaveModule_L141F17L144T27_Case == 1))
		begin
			if ((writeTXCompleting == 1))
			begin
				NextState_writeAWFSM = AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L132F13L145T14_AXI4NonBufferedSlaveModule_L143F48T69_Expr;
			end
		end
		if ((AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L147F13L160T14_AXI4NonBufferedSlaveModule_L149F17L151T27_Case == 1))
		begin
			NextState_writeWFSM = AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L147F13L160T14_AXI4NonBufferedSlaveModule_L150F43T64_Expr;
		end
		else if ((AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L147F13L160T14_AXI4NonBufferedSlaveModule_L152F17L155T27_Case == 1))
		begin
			if ((AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L147F13L160T14_AXI4NonBufferedSlaveModule_L153F25T64_Expr == 1))
			begin
				NextState_writeWFSM = AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L147F13L160T14_AXI4NonBufferedSlaveModule_L154F47T67_Expr;
			end
		end
		else if ((AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L147F13L160T14_AXI4NonBufferedSlaveModule_L156F17L159T27_Case == 1))
		begin
			if ((writeTXCompleting == 1))
			begin
				NextState_writeWFSM = AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L147F13L160T14_AXI4NonBufferedSlaveModule_L158F47T68_Expr;
			end
		end
	end
	assign AXI4NonBufferedSlaveModule_L86F33T70_ExprLhs = {
		1'b0,
		State_readFSM
	}
	;
	assign AXI4NonBufferedSlaveModule_L86F33T70_ExprRhs = {
		1'b0,
		AXI4NonBufferedSlaveModule_L86F50T70_Expr
	}
	;
	assign AXI4NonBufferedSlaveModule_L90F33T74_ExprLhs = {
		1'b0,
		State_writeAWFSM
	}
	;
	assign AXI4NonBufferedSlaveModule_L90F33T74_ExprRhs = {
		1'b0,
		AXI4NonBufferedSlaveModule_L90F53T74_Expr
	}
	;
	assign AXI4NonBufferedSlaveModule_L92F32T72_ExprLhs = {
		1'b0,
		State_writeAWFSM
	}
	;
	assign AXI4NonBufferedSlaveModule_L92F32T72_ExprRhs = {
		1'b0,
		AXI4NonBufferedSlaveModule_L92F52T72_Expr
	}
	;
	assign AXI4NonBufferedSlaveModule_L92F76T115_ExprLhs = {
		1'b0,
		State_writeWFSM
	}
	;
	assign AXI4NonBufferedSlaveModule_L92F76T115_ExprRhs = {
		1'b0,
		AXI4NonBufferedSlaveModule_L92F95T115_Expr
	}
	;
	assign AXI4NonBufferedSlaveModule_L87F32T68_ExprLhs = {
		1'b0,
		State_readFSM
	}
	;
	assign AXI4NonBufferedSlaveModule_L87F32T68_ExprRhs = {
		1'b0,
		AXI4NonBufferedSlaveModule_L87F49T68_Expr
	}
	;
	assign AXI4NonBufferedSlaveModule_L91F32T72_ExprLhs = {
		1'b0,
		State_writeWFSM
	}
	;
	assign AXI4NonBufferedSlaveModule_L91F32T72_ExprRhs = {
		1'b0,
		AXI4NonBufferedSlaveModule_L91F51T72_Expr
	}
	;
	assign AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L117F13L130T14_AXI4NonBufferedSlaveModule_L119F17L121T27_CaseLhs = {
		1'b0,
		State_readFSM
	}
	;
	assign AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L117F13L130T14_AXI4NonBufferedSlaveModule_L119F17L121T27_CaseRhs = {
		1'b0,
		AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L117F13L130T14_AXI4NonBufferedSlaveModule_L119F22T43_Expr
	}
	;
	assign AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L117F13L130T14_AXI4NonBufferedSlaveModule_L122F17L125T27_CaseLhs = {
		1'b0,
		State_readFSM
	}
	;
	assign AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L117F13L130T14_AXI4NonBufferedSlaveModule_L122F17L125T27_CaseRhs = {
		1'b0,
		AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L117F13L130T14_AXI4NonBufferedSlaveModule_L122F22T42_Expr
	}
	;
	assign AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L117F13L130T14_AXI4NonBufferedSlaveModule_L126F17L129T27_CaseLhs = {
		1'b0,
		State_readFSM
	}
	;
	assign AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L117F13L130T14_AXI4NonBufferedSlaveModule_L126F17L129T27_CaseRhs = {
		1'b0,
		AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L117F13L130T14_AXI4NonBufferedSlaveModule_L126F22T41_Expr
	}
	;
	assign AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L132F13L145T14_AXI4NonBufferedSlaveModule_L134F17L136T27_CaseLhs = {
		1'b0,
		State_writeAWFSM
	}
	;
	assign AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L132F13L145T14_AXI4NonBufferedSlaveModule_L134F17L136T27_CaseRhs = {
		1'b0,
		AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L132F13L145T14_AXI4NonBufferedSlaveModule_L134F22T44_Expr
	}
	;
	assign AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L132F13L145T14_AXI4NonBufferedSlaveModule_L137F17L140T27_CaseLhs = {
		1'b0,
		State_writeAWFSM
	}
	;
	assign AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L132F13L145T14_AXI4NonBufferedSlaveModule_L137F17L140T27_CaseRhs = {
		1'b0,
		AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L132F13L145T14_AXI4NonBufferedSlaveModule_L137F22T43_Expr
	}
	;
	assign AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L132F13L145T14_AXI4NonBufferedSlaveModule_L141F17L144T27_CaseLhs = {
		1'b0,
		State_writeAWFSM
	}
	;
	assign AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L132F13L145T14_AXI4NonBufferedSlaveModule_L141F17L144T27_CaseRhs = {
		1'b0,
		AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L132F13L145T14_AXI4NonBufferedSlaveModule_L141F22T42_Expr
	}
	;
	assign AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L147F13L160T14_AXI4NonBufferedSlaveModule_L149F17L151T27_CaseLhs = {
		1'b0,
		State_writeWFSM
	}
	;
	assign AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L147F13L160T14_AXI4NonBufferedSlaveModule_L149F17L151T27_CaseRhs = {
		1'b0,
		AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L147F13L160T14_AXI4NonBufferedSlaveModule_L149F22T44_Expr
	}
	;
	assign AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L147F13L160T14_AXI4NonBufferedSlaveModule_L152F17L155T27_CaseLhs = {
		1'b0,
		State_writeWFSM
	}
	;
	assign AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L147F13L160T14_AXI4NonBufferedSlaveModule_L152F17L155T27_CaseRhs = {
		1'b0,
		AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L147F13L160T14_AXI4NonBufferedSlaveModule_L152F22T43_Expr
	}
	;
	assign AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L147F13L160T14_AXI4NonBufferedSlaveModule_L156F17L159T27_CaseLhs = {
		1'b0,
		State_writeWFSM
	}
	;
	assign AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L147F13L160T14_AXI4NonBufferedSlaveModule_L156F17L159T27_CaseRhs = {
		1'b0,
		AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L147F13L160T14_AXI4NonBufferedSlaveModule_L156F22T42_Expr
	}
	;
	assign AXI4NonBufferedSlaveModule_L99F45T82_ExprLhs = {
		1'b0,
		State_readFSM
	}
	;
	assign AXI4NonBufferedSlaveModule_L99F45T82_ExprRhs = {
		1'b0,
		AXI4NonBufferedSlaveModule_L99F62T82_Expr
	}
	;
	assign AXI4NonBufferedSlaveModule_L99F86T126_ExprLhs = {
		1'b0,
		NextState_readFSM
	}
	;
	assign AXI4NonBufferedSlaveModule_L99F86T126_ExprRhs = {
		1'b0,
		AXI4NonBufferedSlaveModule_L99F107T126_Expr
	}
	;
	assign AXI4NonBufferedSlaveModule_L104F45T86_ExprLhs = {
		1'b0,
		State_writeAWFSM
	}
	;
	assign AXI4NonBufferedSlaveModule_L104F45T86_ExprRhs = {
		1'b0,
		AXI4NonBufferedSlaveModule_L104F65T86_Expr
	}
	;
	assign AXI4NonBufferedSlaveModule_L104F90T134_ExprLhs = {
		1'b0,
		NextState_writeAWFSM
	}
	;
	assign AXI4NonBufferedSlaveModule_L104F90T134_ExprRhs = {
		1'b0,
		AXI4NonBufferedSlaveModule_L104F114T134_Expr
	}
	;
	assign AXI4NonBufferedSlaveModule_L108F44T84_ExprLhs = {
		1'b0,
		State_writeWFSM
	}
	;
	assign AXI4NonBufferedSlaveModule_L108F44T84_ExprRhs = {
		1'b0,
		AXI4NonBufferedSlaveModule_L108F63T84_Expr
	}
	;
	assign AXI4NonBufferedSlaveModule_L108F88T131_ExprLhs = {
		1'b0,
		NextState_writeWFSM
	}
	;
	assign AXI4NonBufferedSlaveModule_L108F88T131_ExprRhs = {
		1'b0,
		AXI4NonBufferedSlaveModule_L108F111T131_Expr
	}
	;
	assign AXI4NonBufferedSlaveModule_L86F33T90_Expr_1 = AXI4NonBufferedSlaveModule_L86F33T70_Expr;
	assign AXI4NonBufferedSlaveModule_L86F33T90_Expr_2 = Inputs_inARREADY;
	assign AXI4NonBufferedSlaveModule_L90F33T94_Expr_1 = AXI4NonBufferedSlaveModule_L90F33T74_Expr;
	assign AXI4NonBufferedSlaveModule_L90F33T94_Expr_2 = Inputs_inAWREADY;
	assign AXI4NonBufferedSlaveModule_L92F32T134_Expr_1 = AXI4NonBufferedSlaveModule_L92F32T115_Expr;
	assign AXI4NonBufferedSlaveModule_L92F32T134_Expr_2 = Inputs_inBVALID;
	assign AXI4NonBufferedSlaveModule_L92F32T115_Expr_1 = AXI4NonBufferedSlaveModule_L92F32T72_Expr;
	assign AXI4NonBufferedSlaveModule_L92F32T115_Expr_2 = AXI4NonBufferedSlaveModule_L92F76T115_Expr;
	assign AXI4NonBufferedSlaveModule_L87F32T87_Expr_1 = AXI4NonBufferedSlaveModule_L87F32T68_Expr;
	assign AXI4NonBufferedSlaveModule_L87F32T87_Expr_2 = Inputs_inRVALID;
	assign AXI4NonBufferedSlaveModule_L91F32T91_Expr_1 = AXI4NonBufferedSlaveModule_L91F32T72_Expr;
	assign AXI4NonBufferedSlaveModule_L91F32T91_Expr_2 = Inputs_inWREADY;
	assign AXI4NonBufferedSlaveModule_L83F34T73_Expr_1 = internalRVALID;
	assign AXI4NonBufferedSlaveModule_L83F34T73_Expr_2 = Inputs_M2S_R_R_RREADY;
	assign AXI4NonBufferedSlaveModule_L84F35T74_Expr_1 = internalBVALID;
	assign AXI4NonBufferedSlaveModule_L84F35T74_Expr_2 = Inputs_M2S_W_B_BREADY;
	assign AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L117F13L130T14_AXI4NonBufferedSlaveModule_L123F25T67_Expr_1 = internalARREADY;
	assign AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L117F13L130T14_AXI4NonBufferedSlaveModule_L123F25T67_Expr_2 = Inputs_M2S_R_AR_ARVALID;
	assign AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L132F13L145T14_AXI4NonBufferedSlaveModule_L138F25T67_Expr_1 = internalAWREADY;
	assign AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L132F13L145T14_AXI4NonBufferedSlaveModule_L138F25T67_Expr_2 = Inputs_M2S_W_AW_AWVALID;
	assign AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L147F13L160T14_AXI4NonBufferedSlaveModule_L153F25T64_Expr_1 = internalWREADY;
	assign AXI4NonBufferedSlaveModule_L114F9L161T10_AXI4NonBufferedSlaveModule_L147F13L160T14_AXI4NonBufferedSlaveModule_L153F25T64_Expr_2 = Inputs_M2S_W_W_WVALID;
	assign AXI4NonBufferedSlaveModule_L99F45T126_Expr_1 = AXI4NonBufferedSlaveModule_L99F45T82_Expr;
	assign AXI4NonBufferedSlaveModule_L99F45T126_Expr_2 = AXI4NonBufferedSlaveModule_L99F86T126_Expr;
	assign AXI4NonBufferedSlaveModule_L104F45T134_Expr_1 = AXI4NonBufferedSlaveModule_L104F45T86_Expr;
	assign AXI4NonBufferedSlaveModule_L104F45T134_Expr_2 = AXI4NonBufferedSlaveModule_L104F90T134_Expr;
	assign AXI4NonBufferedSlaveModule_L108F44T131_Expr_1 = AXI4NonBufferedSlaveModule_L108F44T84_Expr;
	assign AXI4NonBufferedSlaveModule_L108F44T131_Expr_2 = AXI4NonBufferedSlaveModule_L108F88T131_Expr;
	assign Inputs_inARREADY = inARREADY;
	assign Inputs_inAWREADY = inAWREADY;
	assign Inputs_inBVALID = inBVALID;
	assign Inputs_inRDATA[0] = inRDATA0;
	assign Inputs_inRDATA[1] = inRDATA1;
	assign Inputs_inRDATA[2] = inRDATA2;
	assign Inputs_inRDATA[3] = inRDATA3;
	assign Inputs_inRVALID = inRVALID;
	assign Inputs_inWREADY = inWREADY;
	assign Inputs_M2S_W_B_BREADY = M2S[221];
	assign Inputs_M2S_W_W_WVALID = M2S[220];
	assign Inputs_M2S_W_W_WUSER = M2S[219:212];
	assign Inputs_M2S_W_W_WLAST = M2S[211];
	assign Inputs_M2S_W_W_WSTRB = M2S[210:207];
	assign Inputs_M2S_W_W_WDATA[3] = M2S[206:199];
	assign Inputs_M2S_W_W_WDATA[2] = M2S[198:191];
	assign Inputs_M2S_W_W_WDATA[1] = M2S[190:183];
	assign Inputs_M2S_W_W_WDATA[0] = M2S[182:175];
	assign Inputs_M2S_W_W_WID = M2S[174:167];
	assign Inputs_M2S_W_AW_AWVALID = M2S[166];
	assign Inputs_M2S_W_AW_AWUSER = M2S[165:158];
	assign Inputs_M2S_W_AW_AWREGION = M2S[157:150];
	assign Inputs_M2S_W_AW_AWQOS = M2S[149:146];
	assign Inputs_M2S_W_AW_AWPROT = M2S[145:143];
	assign Inputs_M2S_W_AW_AWCACHE = M2S[142:139];
	assign Inputs_M2S_W_AW_AWLOCK = M2S[138:137];
	assign Inputs_M2S_W_AW_AWBURST = M2S[136:135];
	assign Inputs_M2S_W_AW_AWSIZE = M2S[134:132];
	assign Inputs_M2S_W_AW_AWLEN = M2S[131:124];
	assign Inputs_M2S_W_AW_AWADDR = M2S[123:92];
	assign Inputs_M2S_W_AW_AWID = M2S[91:84];
	assign Inputs_M2S_R_R_RREADY = M2S[83];
	assign Inputs_M2S_R_AR_ARVALID = M2S[82];
	assign Inputs_M2S_R_AR_ARUSER = M2S[81:74];
	assign Inputs_M2S_R_AR_ARREGION = M2S[73:66];
	assign Inputs_M2S_R_AR_ARQOS = M2S[65:62];
	assign Inputs_M2S_R_AR_ARPROT = M2S[61:59];
	assign Inputs_M2S_R_AR_ARCACHE = M2S[58:55];
	assign Inputs_M2S_R_AR_ARLOCK = M2S[54:53];
	assign Inputs_M2S_R_AR_ARBURST = M2S[52:51];
	assign Inputs_M2S_R_AR_ARSIZE = M2S[50:48];
	assign Inputs_M2S_R_AR_ARLEN = M2S[47:40];
	assign Inputs_M2S_R_AR_ARADDR = M2S[39:8];
	assign Inputs_M2S_R_AR_ARID = M2S[7:0];
	assign internalARREADY = AXI4NonBufferedSlaveModule_L86F33T90_Expr;
	assign internalAWREADY = AXI4NonBufferedSlaveModule_L90F33T94_Expr;
	assign internalBVALID = AXI4NonBufferedSlaveModule_L92F32T134_Expr;
	assign internalRVALID = AXI4NonBufferedSlaveModule_L87F32T87_Expr;
	assign internalWREADY = AXI4NonBufferedSlaveModule_L91F32T91_Expr;
	assign readTXCompleting = AXI4NonBufferedSlaveModule_L83F34T73_Expr;
	assign writeTXCompleting = AXI4NonBufferedSlaveModule_L84F35T74_Expr;
	assign outARADDR = Inputs_M2S_R_AR_ARADDR;
	assign outARREADYConfirming = AXI4NonBufferedSlaveModule_L99F45T126_Expr;
	assign outARVALID = Inputs_M2S_R_AR_ARVALID;
	assign outAWADDR = Inputs_M2S_W_AW_AWADDR;
	assign outAWREADYConfirming = AXI4NonBufferedSlaveModule_L104F45T134_Expr;
	assign outAWVALID = Inputs_M2S_W_AW_AWVALID;
	assign outReadTXCompleting = readTXCompleting;
	assign outWDATA0 = Inputs_M2S_W_W_WDATA[0];
	assign outWDATA1 = Inputs_M2S_W_W_WDATA[1];
	assign outWDATA2 = Inputs_M2S_W_W_WDATA[2];
	assign outWDATA3 = Inputs_M2S_W_W_WDATA[3];
	assign outWREADYConfirming = AXI4NonBufferedSlaveModule_L108F44T131_Expr;
	assign outWriteTXCompleting = writeTXCompleting;
	assign outWSTRB = Inputs_M2S_W_W_WSTRB;
	assign outWVALID = Inputs_M2S_W_W_WVALID;
	assign S2M[73] = internalWREADY;
	assign S2M[72] = internalBVALID;
	assign S2M[71:64] = Inputs_M2S_W_W_WUSER;
	assign S2M[63:62] = AXI4NonBufferedSlaveModule_L75F29T41_Expr;
	assign S2M[61:54] = Inputs_M2S_W_W_WID;
	assign S2M[53] = internalAWREADY;
	assign S2M[52] = internalRVALID;
	assign S2M[51:44] = Inputs_M2S_R_AR_ARUSER;
	assign S2M[43] = AXI4_S_R_L26F29T33_Expr;
	assign S2M[42:41] = AXI4NonBufferedSlaveModule_L59F29T41_Expr;
	assign S2M[40:33] = Inputs_inRDATA[3];
	assign S2M[32:25] = Inputs_inRDATA[2];
	assign S2M[24:17] = Inputs_inRDATA[1];
	assign S2M[16:9] = Inputs_inRDATA[0];
	assign S2M[8:1] = Inputs_M2S_R_AR_ARID;
	assign S2M[0] = internalARREADY;
	// [BEGIN USER ARCHITECTURE]
	// [END USER ARCHITECTURE]
endmodule