From 6a842fff879f4e57f1025cee23983d77b2f34aa5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 5 Nov 2024 17:58:31 +0100 Subject: [PATCH] mb/msi/ms7d25,7eo6: Fix USB 3.x port mapping MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The USB-C port is Gen2x2 and occupies two USB3.x line pairs. The missing second pair caused all the ports to be shifted by one and port 10 not being enabled as USB3.x capable. As a result one of the JUSB3 ports was working in HighSpeed only. Signed-off-by: Michał Żygowski --- src/mainboard/msi/ms7d25/devicetree.cb | 20 ++++++++++---------- src/mainboard/msi/ms7e06/devicetree.cb | 20 ++++++++++---------- 2 files changed, 20 insertions(+), 20 deletions(-) diff --git a/src/mainboard/msi/ms7d25/devicetree.cb b/src/mainboard/msi/ms7d25/devicetree.cb index 05edb550013..44f9bb89bab 100644 --- a/src/mainboard/msi/ms7d25/devicetree.cb +++ b/src/mainboard/msi/ms7d25/devicetree.cb @@ -74,16 +74,16 @@ chip soc/intel/alderlake register "usb2_ports[14]" = "USB2_PORT_EMPTY" # USB Redirection port 1 register "usb2_ports[15]" = "USB2_PORT_EMPTY" # USB Redirection port 2 - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # USB-C LAN_USB1 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # USB-A LAN_USB1 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # JUSB5 - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)" # USB-A USB2 - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC7)" # USB-A USB2 - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC7)" # JUSB4 - register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC2)" # JUSB4 - register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC2)" # JUSB3 - register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC0)" # JUSB3 - register "usb3_ports[9]" = "USB3_PORT_EMPTY" + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # USB-C Gen2x2 LAN_USB1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # USB-C Gen2x2 LAN_USB1 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # USB-A LAN_USB1 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # JUSB5 + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # USB-A USB2 + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC7)" # USB-A USB2 + register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC7)" # JUSB4 + register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC2)" # JUSB4 + register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC2)" # JUSB3 + register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC0)" # JUSB3 end device ref cnvi_wifi on # Enable CNVi BT diff --git a/src/mainboard/msi/ms7e06/devicetree.cb b/src/mainboard/msi/ms7e06/devicetree.cb index 754896ff62d..d42c3af49cf 100644 --- a/src/mainboard/msi/ms7e06/devicetree.cb +++ b/src/mainboard/msi/ms7e06/devicetree.cb @@ -76,16 +76,16 @@ chip soc/intel/alderlake register "usb2_ports[14]" = "USB2_PORT_EMPTY" # USB Redirection port 1 register "usb2_ports[15]" = "USB2_PORT_EMPTY" # USB Redirection port 2 - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # USB-C LAN_USB1 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # USB-A LAN_USB1 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # JUSB5 - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)" # USB-A USB2 - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC7)" # USB-A USB2 - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC7)" # JUSB4 - register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC2)" # JUSB4 - register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC2)" # JUSB3 - register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC0)" # JUSB3 - register "usb3_ports[9]" = "USB3_PORT_EMPTY" + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # USB-C Gen2x2 LAN_USB1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # USB-C Gen2x2 LAN_USB1 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # USB-A LAN_USB1 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # JUSB5 + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # USB-A USB2 + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC7)" # USB-A USB2 + register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC7)" # JUSB4 + register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC2)" # JUSB4 + register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC2)" # JUSB3 + register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC0)" # JUSB3 end device ref cnvi_wifi on # Enable CNVi BT