diff --git a/.gitmodules b/.gitmodules index a31a15629..7c5393bdb 100644 --- a/.gitmodules +++ b/.gitmodules @@ -10,3 +10,6 @@ path = SDAccel/examples/xilinx_2018.3 url = https://github.com/Xilinx/SDAccel_Examples.git branch = master +[submodule "SDAccel/examples/xilinx_2019.1"] + path = SDAccel/examples/xilinx_2019.1 + url = https://github.com/Xilinx/SDAccel_Examples.git diff --git a/ERRATA.md b/ERRATA.md index fc379d818..6bf605959 100644 --- a/ERRATA.md +++ b/ERRATA.md @@ -9,6 +9,15 @@ * DRAM Data retention is not supported for CL designs with less than 4 DDRs enabled * Combinatorial loops in CL designs are not supported. +### 2019.1 +* Vivado `compile_simlib` command fails to generate the following verilog IP libraries for the following simulators. + +| Library(verilog) | Simulator | +|---|---| +| `sync_ip` | Cadence IES | +| `hdmi_gt_controller_v1_0_0` | Synopsys VCS | +* We are working with Xilinx to provide a fix for these. + ## SDK ## SDAccel (For additional restrictions see [SDAccel ERRATA](./SDAccel/ERRATA.md)) diff --git a/FAQs.md b/FAQs.md index 4a12d4eba..46aec1b94 100644 --- a/FAQs.md +++ b/FAQs.md @@ -19,14 +19,13 @@ ## General F1 FAQs -**Q: How is developing a FPGA design for the cloud different from the common practice outside the cloud?** +**Q: How is developing an FPGA design for the cloud different from the common practice outside the cloud?** AWS designed its FPGA instances to provide a developer experience with ease of use and as similar as possible to on-premises development environment with the following differences (advantages): - - Developers don’t need to purchase / design / bringup or debug the physical hardware where the FPGA is hosted, nor the platform/server hardware: all the hardware is verified, monitored, and maintained by AWS. -- AWS provides an [FPGA Developer AMI](https://aws.amazon.com/marketplace/pp/B06VVYBLZZ) that contains Xilinx Vivado development environment, with all the needed licenses. By using the FPGA developer AMI developers have a choice to a wide range of instance (different CPU and Memory configuration) allowing developers to optimize their development flow. +- AWS provides an [FPGA Developer AMI](https://aws.amazon.com/marketplace/pp/B06VVYBLZZ) that contains Xilinx Vivado development environment, with all the needed licenses. By using the FPGA Developer AMI developers have a choice to a wide range of instance (different CPU and Memory configuration) allowing developers to optimize their development flow. - AWS provides cloud based debug tools: [Virtual JTAG](./hdk/docs/Virtual_JTAG_XVC.md) which is equivalent to debug using JTAG with on-premises development, and Virtual LED together with Virtual DIP Switch emulation the LED and DIP switches in typical development board. @@ -46,30 +45,32 @@ There are two parts to answer this question: For developers that are familiar with AWS, there is almost no additional time to get right into F1 development environment, as long as the documentation and guidances in the [FPGA HDK/SDK](https://github.com/aws/aws-fpga) are followed. -For developers who are new to AWS, there is typically a one to two days ramp on AWS general topics such as launching EC2 instance, setting up S3 storage and its permissions, using AWS console, etc… For new developers to AWS, we recommend to start with the [FPGA Developer Forum](https://forums.aws.amazon.com/ann.jspa?annID=4448) +For developers who are new to AWS, there is typically a one to two days ramp on AWS general topics such as launching EC2 instance, setting up S3 storage and its permissions, using AWS console, etc… For new developers to AWS, we recommend starting with the [FPGA Developer Forum](https://forums.aws.amazon.com/ann.jspa?annID=4448) - On-going development flow: -Once developers complete their DCP, they submit the design through an AWS EC2 API to create the Amazon FGPA Image (aka AFI, this API call can take a few hours to complete, and the status of the process is reported in the S3 log bucket provides by the developers. AWS is working to improve the turn time of AFI generation. +Once developers create their DCP, they submit the design through an AWS EC2 API to create the Amazon FPGA Image (aka AFI, this API call can take a few hours to complete, and the status of the process is reported in the S3 log bucket provides by the developers. AWS is working to improve the turn time of AFI generation. **Q: What new skill sets will be required from an FPGA developer in the cloud?** -As AWS has taken all the non-differentiating, heavy lifting of hardware design, debug and implementation of PCIe tuning, FPGA I/O assignment, power, thermal management, and runtime health monitoring. Therefore AWS FPGA developers can focus on their own differentiating logic, instead of spending time on hardware bringup/debug and maintenance. +AWS takes care of all the non-differentiating, heavy lifting of hardware design, debug and implementation of PCIe tuning, FPGA I/O assignment, power, thermal management, and runtime health monitoring. + +This enables AWS FPGA developers to focus on their own differentiating logic, instead of spending time on hardware bring-up/debug and maintenance. -On the business side, AWS Marketplace (MP) provides FPGA developers the opportunity to sell hardware accelerations to all of AWS users: Ramping on AWS MP services, capabilities and commercial opportunities are recommended knowledge for developers interested in selling their AFIs on AWS MP. Education and research institutes can use AWS MP to distribute their research work ; having access to vast amounts of free [public data-sets](https://aws.amazon.com/public-datasets/ ) can be of value when running research hardware accelerations on AWS. +On the business side, AWS Marketplace (MP) provides FPGA developers the opportunity to sell hardware accelerations to all of AWS users: Ramping on AWS MP services, capabilities and commercial opportunities are recommended knowledge for developers interested in selling their AFIs on AWS MP. Education and research institutes can use AWS MP to distribute their research work. Having access to vast amounts of free [public data-sets](https://aws.amazon.com/public-datasets/ ) can be of value when running research hardware accelerations on AWS. Finally, AWS consulting and technology partners can offer their services through the [AWS Partner Network](https://aws.amazon.com/ec2/instance-types/f1/partners/) to AWS users that don’t have specific FPGA development knowledge, in order to develop FPGA accelerations in the cloud by themselves. -**Q: How is deployment FPGA in the cloud different compared to on-premises?** +**Q: How is developing on FPGA's in the cloud different from on-premises?** With AWS, FPGAs developers have a few advantages: - Low entry bar: AWS FPGAs are charged on an hourly rate instead of the many thousands of dollars spent on hardware/licenses and 12+ months time it takes to design/manufacture and ship a production-ready FPGA hardware solution. -- Scalability and Elasticity: Developers can ramp up / down the number of deployed FPGAs within seconds based on offered load. +- Scalability and Elasticity: Developers can ramp up / down the number of deployed FPGAs within seconds based on required load. - Share: FPGA developers can share their designs easily through AWS Marketplace or APN. This is important for businesses as well as education and research use. @@ -80,11 +81,11 @@ With AWS, FPGAs developers have a few advantages: The HDK includes the following main components: -1) Documentation for the Shell interface and other Custom Logic implementation guidelines, the Shell models needed for Custom Logic development, simulation models for the Shell, software for exercising. +1) Documentation for the Shell interface and other Custom Logic implementation guidelines, shell models needed for Custom Logic development, simulation models for the shell, scripts for building and simulating, etc. 2) Custom Logic examples, a getting started guide for building your own Custom Logic, and examples for starting a Custom Logic Design. -3) Scripts for building and submitting Amazon FPGA Image (AFI) from a Custom Logic. +3) Scripts for building and creating Amazon FPGA Images (AFI) from a Custom Logic. 4) Reference software drivers to be used in conjunction with the Custom Logic examples. @@ -93,7 +94,7 @@ The HDK includes the following main components: **Q: What is in the AWS Shell?** -The AWS Shell is the part of the FPGA that is provided and managed by AWS: it implements the non-differentiated development and heavy lifting tasks like setting up the PCIe interface, FPGA image download, security, health monitoring, metrics and debug hooks. +The AWS Shell is the part of the FPGA that is provided and managed by AWS: it implements the non-differentiated development and heavy lifting tasks like setting up the PCIe interface, security, health monitoring, metrics and debug hooks. Every FPGA deployed in AWS cloud includes an AWS Shell, and the developer Custom Logic (CL) interfaces with the available AWS Shell interfaces. @@ -110,12 +111,12 @@ The developer can create multiple AFIs at no extra cost, up to a defined limited AWS FPGA generation and EC2 F1 instances are supported in us-east-1 (N. Virginia), us-west-2 (Oregon), eu-west-1 (Ireland) and us-gov-west-1 (GovCloud US). - **Q: What is the process for creating an AFI?** -The AFI process starts by creating Custom Logic (CL) code that conforms to the [Shell Specification](./hdk/docs/AWS_Shell_Interface_Specification.md). Then, the CL must be compiled using the HDK scripts which leverages Vivado tools to create a Design Checkpoint (DCP). That DCP is submitted to AWS for generating an AFI using the `aws ec2 create-fpga-image` API. - -Use the AWS CLI `describe-fpga-images` API to get information about the created AFIs using the AFI ID provided by `create-fpga-image`, or to list available AFIs for your account. See [describe-fpga-images](./hdk/docs/describe_fpga_images.md) document for details on how to use this API. +* The AFI process starts by creating Custom Logic (CL) code that conforms to the [Shell Specification](./hdk/docs/AWS_Shell_Interface_Specification.md). +* Then, the CL must be compiled using the HDK scripts which leverages Vivado tools to create a Design Checkpoint (DCP). +* That DCP is submitted to AWS for generating an AFI using the `aws ec2 create-fpga-image` API. + * Use the AWS CLI `describe-fpga-images` API to get information about the created AFIs using the AFI ID provided by `create-fpga-image`, or to list available AFIs for your account. See [describe-fpga-images](./hdk/docs/describe_fpga_images.md) document for details on how to use this API. **Q: Can I load an AFI on every region AWS FPGA is supported?** @@ -152,6 +153,15 @@ Yes, use [delete-fpga-image](./hdk/docs/delete_fpga_image.md) to delete an AFI i Use [delete-fpga-image](./hdk/docs/delete_fpga_image.md) carefully. Once all AFIs of the same global AFI ID are deleted, the AFIs cannot be recovered from deletion. Review [IAM policy best practices](http://docs.aws.amazon.com/IAM/latest/UserGuide/best-practices.html#grant-least-privilege) to resrict access to this API. + +**Q: How do I increase my AFI limit?** + +AFI limit increases may be requested by opening up a Support Case from your [EC2 Support Console](https://console.aws.amazon.com/support/cases#/create) + +Select a `Service limit increase` of the Limit Type - `EC2 FPGA` for the region where a limit increase is needed. + +You will hear back from our support team once the limit is increased. + **Q: Can I bring my own bitstream for loading on an F1 FPGA?** No. There is no mechanism for loading a bitstream directly onto the FPGAs of an F1 instance. All Custom Logic is loaded onto the FPGA by calling `$ fpga-local-load-image` tool at [AWS FPGA SDK](./sdk). @@ -185,20 +195,25 @@ No. AWS supports a cloud-only development model and provides the necessary eleme **Q: Do I need to design for a specific power envelope?** -Yes, the Xilinx UltraScale+ FPGA devices used on the F1 instances have a maximum power limit that must be maintained. If a loaded AFI consumes maximum power, the F1 instance will automatically gate the input clocks provided to the AFI in order to prevent errors within the FPGA. Developers are provided warnings when power (Vccint) is greater than 85 watts. Above that level, the CL is in danger of being clock gated. [Additional details on AFI power](hdk/docs/afi_power.md) - +Yes, the Xilinx UltraScale+ FPGA devices used on the F1 instances have a maximum power limit that must be maintained. +If a loaded AFI consumes maximum power, the F1 instance will automatically gate the input clocks provided to the AFI in order to prevent errors within the FPGA. +Developers are provided warnings when power (Vccint) is greater than 85 watts. Above that level, the CL is in danger of being clock gated. -**Q: What IP blocks are provided in the HDK?** +[Additional details on AFI power](hdk/docs/afi_power.md) -The HDK includes IP for AWS Shell and DRAM interface controllers. Inside the Shell, there is a PCIe interface, DMA Engine, and one DRAM interface controller. These blocks are only accessible via the AXI interfaces defined by the Shell-Custom Logic interface. The HDK provides additional IP blocks for the other DRAM interfaces, enabling up to 3 additional DRAM interfaces instantiated by the developer in the Custom Logic region. - **Note** * future versions of the HDK will include IP for the FPGA Link interface.* +**Q: What IP blocks are provided in the HDK?** +The HDK includes IP for AWS Shell and DRAM interface controllers. +Inside the Shell, there is a PCIe interface, DMA Engine, and one DRAM interface controller. +These blocks are only accessible via the AXI interfaces defined by the Shell-Custom Logic interface. +The HDK provides additional IP blocks for the other DRAM interfaces, enabling up to 3 additional DRAM interfaces instantiated by the developer in the Custom Logic region. **Q: Can I use other IP blocks from Xilinx or other 3rd parties?** -Yes. Developers are free to use any IP blocks within the Custom Logic region. Those can be 3rd party IPs or IP available in the Vivado IP catalog. +Yes. Developers are free to use any IP blocks within the Custom Logic region. +Those can be 3rd party IPs or IP available in the Vivado IP catalog. **Note** * AWS supports only the IP blocks contained in the HDK.* @@ -207,19 +222,23 @@ Yes. Developers are free to use any IP blocks within the Custom Logic region. Th ## Getting Started FAQs **Q: What AWS knowledge do I need to learn before I can develop accelerators and run on AWS F1 instances?** -[AWS Getting Started Resource Center](https://aws.amazon.com/getting-started/) has lots of resources to help developers get started. For F1 development, launching linux virtual machines (EC2) and storing and retrieving files from S3 are required skills. +[AWS Getting Started Resource Center](https://aws.amazon.com/getting-started/) has lots of resources to help developers get started. +For F1 development, launching EC2 instances and storing and retrieving files from S3 are required skills. **Q: What do I need to get started on building accelerators for FPGA instances?** -Getting started requires downloading the latest HDK and SDK from the AWS FPGA GitHub repository. The HDK and SDK provide the needed code and information for building FPGA code. The HDK provides all the information needed for developing an FPGA image from source code, while the SDK provides all the runtime software for managing the Amazon FPGA Image (AFI) loaded into the F1 instance FPGA. +Getting started requires downloading the latest HDK and SDK from the [AWS FPGA GitHub repository](https://github.com/aws/aws-fpga). +The HDK and SDK provide the needed code and information for building FPGA code. The HDK provides all the information needed for developing an FPGA image from source code, while the SDK provides all the runtime software for managing the Amazon FPGA Image (AFI) loaded into the F1 instance FPGA. -Typically, FPGA development process requires a simulator to perform functional test on the source code, and a Vivado tool set for synthesis of source code into compiled FPGA code. The FPGA Developer AMI provided by AWS includes the complete Xilinx Vivado tools for simulation (XSIM) and synthesis of FPGA. +Typically, FPGA development process requires a simulator to perform functional test on the source code, and a Vivado tool set for synthesis of source code into compiled FPGA code. +The FPGA Developer AMI provided by AWS includes the complete Xilinx Vivado tools for simulation (XSIM) and synthesis of FPGA. **Q: How do I develop accelerator code for an FPGA in an F1 instance?** -Start with the [Shell interface specification](./hdk/docs/AWS_Shell_Interface_Specification.md). This document describes the interface between Custom Logic and the AWS Shell. All Custom Logic for an accelerator resides within the Custom Logic region of the F1 FPGA. +Start with the [Shell interface specification](./hdk/docs/AWS_Shell_Interface_Specification.md). +This document describes the interface between Custom Logic and the AWS Shell. All Custom Logic for an accelerator resides within the Custom Logic region of the F1 FPGA. The [HDK README](./hdk/README.md) walks the developer through the steps to build an FPGA image from one of the provided examples as well as starting a new code. @@ -265,12 +284,19 @@ We recommend using the latest available version to be able to use the expanding ## Marketplace FAQs **Q: What does publishing my AFI/AMI to AWS Marketplace enables?** -FPGA Developers can share or sell their AFI/AMI using the AWS Marketplace to other AWS users. Once in Marketplace, AWS users can launch an F1 instance with that AFI/AMI combination with the 1-click deployment feature. Marketplace Sellers can take advantage of the Management Portal to better build and analyze their business, using it to drive marketing activities and customer adoption. The metering, billing, collections, and disbursement of payments are managed by AWS, allowing developers to focus on marketing their solution. Please check out [AWS Marketplace Tour](https://aws.amazon.com/marketplace/management/tour/) for more details on how to become an AWS Marketplace seller, how to set pricing and collect metrics. +FPGA Developers can share or sell their AFI/AMI using the AWS Marketplace to other AWS users. +Once in Marketplace, AWS users can launch an F1 instance with that AFI/AMI combination with the 1-click deployment feature. +Marketplace Sellers can take advantage of the Management Portal to better build and analyze their business, using it to drive marketing activities and customer adoption. +The metering, billing, collections, and disbursement of payments are managed by AWS, allowing developers to focus on marketing their solution. + +Please check out [AWS Marketplace Tour](https://aws.amazon.com/marketplace/management/tour/) for more details on how to become an AWS Marketplace seller, how to set pricing and collect metrics. **Q: How can I publish my AFI to AWS Marketplace?** -First, you need to [register as a Marketplace Seller](https://aws.amazon.com/marketplace/management/register/). In parallel you should create an AMI that includes the drivers and runtime libraries needed to use your AFI. Finally, follow the [standard flow](https://aws.amazon.com/marketplace/help/200940360) to publish your AMI on AWS marketplace, providing the associated AFI IDs. In other words, AFIs are not published directly on AWS marketplace, rather AFI(s) should be associated with an AMI that gets published. +* First, you need to [register as a Marketplace Seller](https://aws.amazon.com/marketplace/management/register/). +* In parallel you should create an AMI that includes the drivers and runtime libraries needed to use your AFI. +* Finally, follow the [standard flow](https://aws.amazon.com/marketplace/help/200940360) to publish your AMI on AWS marketplace, providing the associated AFI IDs. In other words, AFIs are not published directly on AWS marketplace, rather AFI(s) should be associated with an AMI that gets published. **Q: Do AWS Marketplace customers see FPGA source code or a bitstream?** @@ -281,7 +307,11 @@ Neither, no FPGA internal design code is exposed. AWS Marketplace customers that ## F1 Instance and Runtime Tools FAQs **Q: What OS can run on the F1 instance?** -CentOS 7.x is supported and tested on AWS EC2 F1 instance. Please see [release notes](./RELEASE_NOTES.md) for a description of compatible kernel & OS versions supported by a specific Developer kit version. Developers can utilize the source code in the SDK directory to compile other variants of Linux for use on F1. Windows OSs are not supported on F1. +CentOS 7.x is supported and tested on AWS EC2 F1 instance. +Please see [release notes](./RELEASE_NOTES.md) for a description of compatible Kernel & OS versions supported by a specific Developer kit version. +Developers can utilize the source code in the SDK directory to compile other variants of Linux for use on F1. + +NOTE: Windows OSs are not supported on F1. **Q: What are the interfaces between the F1 instance host CPU and the FPGAs?** @@ -293,7 +323,6 @@ The first is the FPGA Image Management Tools. These APIs are detailed in the [SD The second type of interface is direct address access to the Application PCIe Physical Functions (PF) of the FPGA. There is no API for this access. Rather, there is direct access to resources in the Custom Logic (CL) region or Shell that can be accessed by software written on the instance. For example, the ChipScope software (Virtual JTAG) uses address space in a PF to provide FPGA debug support. Developers can create any API to the resources in their CL. See the [Shell Interface Specification](./hdk/docs/AWS_Shell_Interface_Specification.md) for more details on the address space mapping as seen from the instance. - **Q: Can I integrate the FPGA Image Management Tools in my application?** Yes, In addition to providing the [FPGA Management Tools](./sdk/userspace/fpga_mgmt_tools) as linux shell commands, the [SDK Userspace](./sdk/userspace) directory includes files in the `include` and `hal` to integrate the FPGA Management Tools into the developer's application(a) and avoid calling linux shell commands. @@ -326,8 +355,8 @@ The AWS infrastructure scrubs FPGA state on termination of an F1 instance and an **Q: How do the FPGAs connect to the x86 CPU?** -Each FPGA in F1 is connected to the instance CPU via a x16 PCIe Gen3 interface. Physical Functions (PF) within the FPGA are directly mapped into the F1 instance. Software on the instance can directly access the address in the PF to take advantage of the high performance PCIe interface. - +Each FPGA in F1 is connected to the instance CPU via a x16 PCIe Gen3 interface. +Physical Functions (PF) within the FPGA are directly mapped into the F1 instance. Software on the instance can directly access the address in the PF to take advantage of the high performance PCIe interface. **Q: Can the FPGAs on F1 directly access Amazon’s network?** @@ -346,8 +375,10 @@ No. The FPGAs do not have direct access to the SSDs on F1. The SSDs on F1 are hi ## Development Languages FAQs **Q: Which HDL languages are supported?** -For RTL level development: Verilog and VHDL are both supported in the FPGA Developer AMI and in generating a Design Checkpoint. The Xilinx Vivado tools and simulator support mixed mode simulation of Verilog and VHDL. The AWS Shell is written in Verilog. Support for mixed mode simulation may vary if developers use other simulators. Check your simulator documentation for Verilog/VHDL/System Verilog support. - +For RTL level development: Verilog and VHDL are both supported in the FPGA Developer AMI and in generating a Design Checkpoint. +The Xilinx Vivado tools and simulator support mixed mode simulation of Verilog and VHDL. +The AWS Shell is written in Verilog. Support for mixed mode simulation may vary if developers use other simulators. +Check your simulator documentation for Verilog/VHDL/System Verilog support. **Q: Is OpenCL and/or SDAccel Supported?** @@ -355,41 +386,44 @@ For RTL level development: Verilog and VHDL are both supported in the FPGA Devel Yes. Please review the [SDAccel README to get started](SDAccel/README.md) - **Q: Can I use High Level Synthesis(HLS) Tools to generate an AFI?** -Yes. Vivado HLS and SDAccel are directly supported through the FPGA Developer AMI. Any other HLS tool that generates compatible Verilog or VHDL for Vivado input can also be used for writing in HLS. - +Yes. Vivado HLS and SDAccel are directly supported through the FPGA Developer AMI. +Any other HLS tool that generates compatible Verilog or VHDL for Vivado input can also be used for writing in HLS. **Q: What RTL simulators are supported?** The FPGA Developer AMI has built-in support for the Xilinx XSIM simulator. All licensing and software for XSIM is included in the FPGA Developer AMI when launched. -Support for other simulators is included through the bring-your-own license in the FPGA Developer AMI. AWS tests the HDK with Synopsys VCS, Mentor Questa/ModelSim, and Cadence Incisive. Licenses for these simulators must be acquired by the developer and are not available with AWS FPGA Developer AMI. +AWS tests the HDK with Synopsys VCS, Mentor Questa/ModelSim, and Cadence Incisive. Licenses for these simulators must be acquired by the developer and are not available with AWS FPGA Developer AMI. ## FPGA Specific FAQs **Q: What FPGA is used in AWS EC2 F1 instance?** -The FPGA for F1 is the Xilinx Ultrascale+ VU9P device with the -2 speed grade. The HDK scripts have the compile scripts needed for the VU9P device. +The FPGA for F1 is the Xilinx Ultrascale+ VU9P device with the -2 speed grade. +The HDK scripts have the compile scripts needed for the VU9P device. **Q: What is FPGA Direct and how fast is it?** -FPGA Direct is FPGA to FPGA low latency high throughput peer communication through the PCIe links on each FPGA, where all FPGAs shared the same memory space. The PCIe BAR space in the Application PF (see [Shell Interface specification](./hdk/docs/AWS_Shell_Interface_Specification.md) for more details) allows the developer to map regions of the Custom Logic, such as external DRAM space, to other FPGAs. The implementation of communication protocol and data transfer engine across the PCIe interface using FPGA direct is left to the developer. +FPGA Direct is FPGA to FPGA low latency high throughput peer communication through the PCIe links on each FPGA, where all FPGAs shared the same memory space. +The PCIe BAR space in the Application PF (see [Shell Interface specification](./hdk/docs/AWS_Shell_Interface_Specification.md) for more details) allows the developer to map regions of the Custom Logic, such as external DRAM space, to other FPGAs. +The implementation of communication protocol and data transfer engine across the PCIe interface using FPGA direct is left to the developer. **Q: What is FPGA Link and how fast is it?** -FPGA Link is based on 4 x 100Gbps links on each FPGA card. The FPGA Link is organized as a ring, with 2 x 100Gbps links to each adjacent card. This enables each FPGA card to send/receive data from an adjacent card at 200Gbps speeds. This is a unsupported feature planned for future release. Details on the FPGA Link interface will be provided in the Shell Interface specification when available. +FPGA Link is based on 4 x 100Gbps links on each FPGA card. The FPGA Link is organized as a ring, with 2 x 100Gbps links to each adjacent card. This enables each FPGA card to send/receive data from an adjacent card at 200Gbps speeds. +This is an unsupported feature planned for future release. Details on the FPGA Link interface will be provided in the Shell Interface specification when available. **Q: What protocol is used for FPGA link?** The FPGA link is a generic raw streaming interface, no transport protocol is provided for it by AWS. It is expected that developers would take advantage of standard PCIe protocol, Ethernet protocol, or Xilinx's (reliable) Aurora protocol layer for this interface. -This is a unsupported feature planned for future release. Details on the Shell Interface to the FPGA Link IP blocks are provided in the [Shell Interface specification](./hdk/docs/AWS_Shell_Interface_Specification.md) when available. +This is an unsupported feature planned for future release. Details on the Shell Interface to the FPGA Link IP blocks are provided in the [Shell Interface specification](./hdk/docs/AWS_Shell_Interface_Specification.md) when available. **Q: What clock speed does the FPGA utilize?** @@ -463,7 +497,6 @@ You would need a valid [on premise license](./hdk/docs/on_premise_licensing_help *For runs using the FPGA Developer AMI:* Please contact us through [AWS FPGA Developers forum](https://forums.aws.amazon.com/forum.jspa?forumID=243) - **Q: Why does Vivado in GUI mode show up blank ? or Why does Vivado in GUI mode show up as an empty window?** We have seen this issue when running RDP in 32 bit color mode where Vivado shows up as a blank window. diff --git a/Jenkinsfile b/Jenkinsfile index 3df7ee084..71a1d1729 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -122,7 +122,7 @@ task_label = [ ] // Put the latest version last -def xilinx_versions = [ '2017.4', '2018.2', '2018.3' ] +def xilinx_versions = [ '2017.4', '2018.2', '2018.3', '2019.1' ] // We want the default to be the latest. def default_xilinx_version = xilinx_versions.last() @@ -130,7 +130,8 @@ def default_xilinx_version = xilinx_versions.last() def dsa_map = [ '2017.4' : [ 'DYNAMIC_5_0' : 'dyn'], '2018.2' : [ 'DYNAMIC_5_0' : 'dyn'], - '2018.3' : [ 'DYNAMIC_5_0' : 'dyn'] + '2018.3' : [ 'DYNAMIC_5_0' : 'dyn'], + '2019.1' : [ 'DYNAMIC_5_0' : 'dyn'] ] def sdaccel_example_default_map = [ @@ -153,6 +154,12 @@ def sdaccel_example_default_map = [ 'Gmem_2Banks_2ddr': 'SDAccel/examples/xilinx/getting_started/kernel_to_gmem/gmem_2banks_ocl', 'Kernel_Global_Bw_4ddr': 'SDAccel/examples/xilinx/getting_started/kernel_to_gmem/kernel_global_bandwidth', 'RTL_Vadd_Debug': 'SDAccel/examples/xilinx/getting_started/rtl_kernel/rtl_vadd_hw_debug' + ], + '2019.1' : [ + 'Hello_World_1ddr': 'SDAccel/examples/xilinx/getting_started/hello_world/helloworld_ocl', + 'Gmem_2Banks_2ddr': 'SDAccel/examples/xilinx/getting_started/kernel_to_gmem/gmem_2banks_ocl_5.0_shell', + 'Kernel_Global_Bw_4ddr': 'SDAccel/examples/xilinx/getting_started/kernel_to_gmem/kernel_global_bandwidth_5.0_shell', + 'RTL_Vadd_Debug': 'SDAccel/examples/xilinx/getting_started/rtl_kernel/rtl_vadd_hw_debug' ] ] @@ -174,6 +181,12 @@ def simulator_tool_default_map = [ 'vcs': 'synopsys/vcs-mx/N-2017.12-SP2', 'questa': 'questa/10.6c_1', 'ies': 'incisive/15.20.063' + ], + '2019.1' : [ + 'vivado': 'xilinx/SDx/2019.1.op2552052', + 'vcs': 'synopsys/vcs-mx/N-2017.12-SP2', + 'questa': 'questa/10.6c_1', + 'ies': 'incisive/15.20.063' ] ] @@ -270,7 +283,7 @@ def test_run_py_bindings() { try { sh """ set -e - source $WORKSPACE/shared/tests/bin/setup_test_sdk_env_al2.sh "py_bindings" + source $WORKSPACE/shared/tests/bin/setup_test_sdk_env.sh "py_bindings" python2.7 -m pytest -v $WORKSPACE/${test} --junit-xml $WORKSPACE/${report_file} """ } catch (exc) { @@ -368,7 +381,7 @@ def test_fpga_all_slots() { } catch (exception) { echo "Test FPGA Tools All Slots failed" - input message: "1 slot FPGA Tools test failed. Click Proceed or Abort when you are done debugging on the instance." + input message: "All slot FPGA Tools test failed. Click Proceed or Abort when you are done debugging on the instance." throw exception } finally { @@ -396,7 +409,6 @@ def test_run_non_root_access() { source $WORKSPACE/shared/tests/bin/setup_test_sdk_env.sh newgrp fpgauser export SDK_DIR="${WORKSPACE}/sdk" - source $WORKSPACE/shared/tests/bin/setup_test_env.sh python2.7 -m pytest -v $WORKSPACE/${test} --junit-xml $WORKSPACE/${report_file} """ } catch (exc) { @@ -599,15 +611,15 @@ if (test_xdma) { //============================================================================= // Python Binding Test //============================================================================= -if (test_py_bindings) { - all_tests['Test Python Bindings'] = { - stage('Test Python Bindings') { - node('f1.2xl_runtime_test_al2') { - test_run_py_bindings() - } - } - } -} +// if (test_py_bindings) { +// all_tests['Test Python Bindings'] = { +// stage('Test Python Bindings') { +// node('f1.2xl_runtime_test_al2') { +// test_run_py_bindings() +// } +// } +// } +// } //============================================================================= // Precompiled Runtime Tests @@ -873,34 +885,34 @@ if (test_hdk_fdf) { // SDAccel Tests //============================================================================= -if (test_sdaccel_scripts) { - all_tests['Test SDAccel Scripts'] = { - stage('Test SDAccel Scripts') { - def nodes = [:] - for (def xilinx_version in xilinx_versions) { - - String node_label = get_task_label(task: 'source_scripts', xilinx_version: xilinx_version) - String node_name = "Test SDAccel Scripts ${xilinx_version}" - nodes[node_name] = { - node(node_label) { - String report_file = "test_sdaccel_scripts_${xilinx_version}.xml" - checkout scm - try { - sh """ - set -e - source $WORKSPACE/shared/tests/bin/setup_test_env.sh - python2.7 -m pytest -v $WORKSPACE/SDAccel/tests/test_sdaccel_scripts.py --junit-xml $WORKSPACE/${report_file} - """ - } finally { - run_junit(report_file) - } - } - } - } - parallel nodes - } - } -} +// if (test_sdaccel_scripts) { +// all_tests['Test SDAccel Scripts'] = { +// stage('Test SDAccel Scripts') { +// def nodes = [:] +// for (def xilinx_version in xilinx_versions) { +// +// String node_label = get_task_label(task: 'source_scripts', xilinx_version: xilinx_version) +// String node_name = "Test SDAccel Scripts ${xilinx_version}" +// nodes[node_name] = { +// node(node_label) { +// String report_file = "test_sdaccel_scripts_${xilinx_version}.xml" +// checkout scm +// try { +// sh """ +// set -e +// source $WORKSPACE/shared/tests/bin/setup_test_env.sh +// python2.7 -m pytest -v $WORKSPACE/SDAccel/tests/test_sdaccel_scripts.py --junit-xml $WORKSPACE/${report_file} +// """ +// } finally { +// run_junit(report_file) +// } +// } +// } +// } +// parallel nodes +// } +// } +// } if (test_helloworld_sdaccel_example_fdf || test_all_sdaccel_examples_fdf) { all_tests['Run SDAccel Tests'] = { @@ -995,6 +1007,7 @@ if (test_helloworld_sdaccel_example_fdf || test_all_sdaccel_examples_fdf) { } boolean test_sw_emu_supported = true + boolean test_hw_emu_supported = true if(description_json["targets"]) { if(description_json["targets"].contains("sw_emu")) { @@ -1004,6 +1017,13 @@ if (test_helloworld_sdaccel_example_fdf || test_all_sdaccel_examples_fdf) { test_sw_emu_supported = false echo "Description file ${description_file} does not have target sw_emu" } + if(description_json["targets"].contains("hw_emu")) { + test_hw_emu_supported = true + echo "Description file ${description_file} has target sw_emu" + } else { + test_hw_emu_supported = false + echo "Description file ${description_file} does not have target sw_emu" + } } else { echo "Description json did not have a 'target' key" } @@ -1032,23 +1052,25 @@ if (test_helloworld_sdaccel_example_fdf || test_all_sdaccel_examples_fdf) { } } - stage(hw_emu_stage_name) { - node(get_task_label(task: 'sdaccel_builds', xilinx_version: xilinx_version)) { - checkout scm - try { - sh """ - set -e - source $WORKSPACE/shared/tests/bin/setup_test_build_sdaccel_env.sh - export AWS_PLATFORM=\$AWS_PLATFORM_${dsa_name} - python2.7 -m pytest -v $WORKSPACE/SDAccel/tests/test_build_sdaccel_example.py::TestBuildSDAccelExample::test_hw_emu --examplePath ${example_path} --junit-xml $WORKSPACE/${hw_emu_report_file} --timeout=21600 --rteName ${dsa_rte_name} --xilinxVersion ${xilinx_version} - """ - } catch (error) { - echo "${hw_emu_stage_name} HW EMU Build generation failed" - archiveArtifacts artifacts: "${example_path}/**", fingerprint: true - throw error - } finally { - run_junit(hw_emu_report_file) - git_cleanup() + if(test_hw_emu_supported) { + stage(hw_emu_stage_name) { + node(get_task_label(task: 'sdaccel_builds', xilinx_version: xilinx_version)) { + checkout scm + try { + sh """ + set -e + source $WORKSPACE/shared/tests/bin/setup_test_build_sdaccel_env.sh + export AWS_PLATFORM=\$AWS_PLATFORM_${dsa_name} + python2.7 -m pytest -v $WORKSPACE/SDAccel/tests/test_build_sdaccel_example.py::TestBuildSDAccelExample::test_hw_emu --examplePath ${example_path} --junit-xml $WORKSPACE/${hw_emu_report_file} --timeout=21600 --rteName ${dsa_rte_name} --xilinxVersion ${xilinx_version} + """ + } catch (error) { + echo "${hw_emu_stage_name} HW EMU Build generation failed" + archiveArtifacts artifacts: "${example_path}/**", fingerprint: true + throw error + } finally { + run_junit(hw_emu_report_file) + git_cleanup() + } } } } diff --git a/Jenkinsfile_int_sims b/Jenkinsfile_int_sims index 093164a77..765235488 100644 --- a/Jenkinsfile_int_sims +++ b/Jenkinsfile_int_sims @@ -121,7 +121,7 @@ task_label = [ ] // Put the latest version last -def xilinx_versions = [ '2017.4', '2018.2', '2018.3' ] +def xilinx_versions = [ '2019.1' ] // We want the default to be the latest. def default_xilinx_version = xilinx_versions.last() @@ -173,6 +173,12 @@ def simulator_tool_default_map = [ 'vcs': 'synopsys/vcs-mx/N-2017.12-SP2', 'questa': 'questa/10.6c_1', 'ies': 'incisive/15.20.063' + ], + '2019.1' : [ + 'vivado': 'xilinx/SDx/2019.1.op2552052', + 'vcs': 'synopsys/vcs-mx/O-2018.09-SP1', + 'questa': 'questa/10.6c_1', + 'ies': 'incisive/15.20.063' ] ] @@ -253,239 +259,6 @@ def git_cleanup() { """ } -////////////////////////////////////////////////////// -////////////////////////////////////////////////////// -// Test Functions///////////////////////////////////// -////////////////////////////////////////////////////// -////////////////////////////////////////////////////// - -def test_run_py_bindings() { - echo "Test Python Bindings" - checkout scm - - String test = "sdk/tests/test_py_bindings.py" - String report_file = "test_py_bindings.xml" - - try { - sh """ - set -e - source $WORKSPACE/shared/tests/bin/setup_test_sdk_env_al2.sh "py_bindings" - python2.7 -m pytest -v $WORKSPACE/${test} --junit-xml $WORKSPACE/${report_file} - """ - } catch (exc) { - echo "${test} failed." - input message: "Python bindings test failed. Click Proceed or Abort when you are done debugging on the instance." - throw exc - } finally { - run_junit(report_file) - } -} - -def test_doc_markdown_links() { - String report_file = 'test_md_links.xml' - checkout scm - try { - sh """ - set -e - source $WORKSPACE/shared/tests/bin/setup_test_env.sh - python2.7 -m pytest -v $WORKSPACE/shared/tests/test_md_links.py --junit-xml $WORKSPACE/${report_file} - """ - } finally { - run_junit(report_file) - } -} - -def test_doc_src_headers() { - String report_file = 'test_check_src_headers.xml' - checkout scm - try { - sh """ - set -e - source $WORKSPACE/shared/tests/bin/setup_test_env.sh - python2.7 -m pytest -v $WORKSPACE/shared/tests/test_check_src_headers.py --junit-xml $WORKSPACE/${report_file} - """ - } finally { - run_junit(report_file) - } -} - -def test_run_hdk_scripts() { - checkout scm - String report_file = 'test_hdk_scripts.xml' - try { - sh """ - set -e - source $WORKSPACE/shared/tests/bin/setup_test_env.sh - python2.7 -m pytest -v $WORKSPACE/hdk/tests/test_hdk_scripts.py --junit-xml $WORKSPACE/${report_file} - """ - } finally { - run_junit(report_file) - } -} - -def test_fpga_1_slot() { - String report_file_tools = 'test_fpga_tools.xml' - String report_file_sdk = 'test_fpga_sdk.xml' - String report_file_combined = 'test_fpga_*.xml' - checkout scm - try { - sh """ - set -e - source $WORKSPACE/shared/tests/bin/setup_test_sdk_env.sh - python2.7 -m pytest -v $WORKSPACE/sdk/tests/test_fpga_tools.py --junit-xml $WORKSPACE/${report_file_tools} - sudo -E sh -c 'source $WORKSPACE/shared/tests/bin/setup_test_sdk_env.sh && python2.7 -m pytest -v $WORKSPACE/sdk/tests/test_sdk.py --junit-xml $WORKSPACE/${report_file_sdk}' - sudo -E chmod 666 $WORKSPACE/${report_file_sdk} - """ - } - catch (exception) { - echo "Test FPGA Tools 1 Slot failed" - input message: "1 slot FPGA Tools test failed. Click Proceed or Abort when you are done debugging on the instance." - throw exception - } - finally { - if (fileExists(report_file_tools)) { - junit healthScaleFactor: 10.0, testResults: report_file_combined - } else { - echo "Pytest wasn't run for stage. Report file not generated: ${report_file_combined}" - } - } -} - -def test_fpga_all_slots() { - String report_file_tools = 'test_fpga_tools_all_slots.xml' - String report_file_sdk = 'test_fpga_sdk_all_slots.xml' - String report_file_combined = 'test_fpga_*_all_slots.xml' - checkout scm - try { - sh """ - set -e - source $WORKSPACE/shared/tests/bin/setup_test_sdk_env.sh - python2.7 -m pytest -v $WORKSPACE/sdk/tests/test_fpga_tools.py --junit-xml $WORKSPACE/${report_file_tools} - sudo -E sh -c 'source $WORKSPACE/shared/tests/bin/setup_test_sdk_env.sh && python2.7 -m pytest -v $WORKSPACE/sdk/tests/test_sdk.py --junit-xml $WORKSPACE/${report_file_sdk}' - sudo -E chmod 666 $WORKSPACE/${report_file_sdk} - """ - } - catch (exception) { - echo "Test FPGA Tools All Slots failed" - input message: "1 slot FPGA Tools test failed. Click Proceed or Abort when you are done debugging on the instance." - throw exception - } - finally { - if (fileExists(report_file_tools)) { - junit healthScaleFactor: 10.0, testResults: report_file_combined - } else { - echo "Pytest wasn't run for stage. Report file not generated: ${report_file_combined}" - } - } -} - - -def test_run_non_root_access() { - echo "Test non-root access to FPGA tools" - checkout scm - - String test = "sdk/tests/test_non_root_access.py" - String report_file = "test_non_root_access.xml" - - try { - sh """ - set -e - export AWS_FPGA_ALLOW_NON_ROOT=y - export AWS_FPGA_SDK_OVERRIDE_GROUP=y - source $WORKSPACE/shared/tests/bin/setup_test_sdk_env.sh - newgrp fpgauser - export SDK_DIR="${WORKSPACE}/sdk" - source $WORKSPACE/shared/tests/bin/setup_test_env.sh - python2.7 -m pytest -v $WORKSPACE/${test} --junit-xml $WORKSPACE/${report_file} - """ - } catch (exc) { - input message: "Non-root access test failed. Click Proceed or Abort when you are done debugging on the instance." - throw exc - } finally { - run_junit(report_file) - } -} - -def test_xdma_driver() { - echo "Test XDMA Driver" - checkout scm - - String test = "sdk/tests/test_xdma.py" - String report_file = "test_xdma.xml" - - try { - sh """ - set -e - source $WORKSPACE/shared/tests/bin/setup_test_sdk_env.sh - python2.7 -m pytest -v ${test} --junit-xml $WORKSPACE/${report_file} - """ - } catch (exc) { - echo "${test} failed." - junit healthScaleFactor: 10.0, testResults: report_file - input message: "XDMA driver test failed. Click Proceed or Abort when you are done debugging on the instance." - throw exc - } finally { - run_junit(report_file) - } -} - -//============================================================================= -// Shared Tests -//============================================================================= - - -if (test_markdown_links || test_src_headers) { - all_tests['Documentation Tests'] = { - node(get_task_label(task: 'md_links', xilinx_version: default_xilinx_version)) { - if (test_markdown_links) { - stage('Test Markdown Links') { - test_doc_markdown_links() - } - } - - if (test_src_headers) { - stage('Test Source Headers') { - test_doc_src_headers() - } - } - } - } -} - -//============================================================================= -// HDK Tests -//============================================================================= - -if (test_hdk_scripts) { - all_tests['Test HDK Scripts'] = { - stage('Test HDK Scripts') { - node(get_task_label(task: 'source_scripts', xilinx_version: default_xilinx_version)) { - test_run_hdk_scripts() - } - } - } -} - -//============================================================================= -// FPGA Tool Tests -//============================================================================= -if (test_fpga_tools) { - all_tests['Test FPGA Tools 1 Slot'] = { - stage('Test FPGA Tools 1 Slot') { - node(get_task_label(task: 'runtime', xilinx_version: default_xilinx_version)) { - test_fpga_1_slot() - } - } - } - all_tests['Test FPGA Tools All Slots'] = { - stage('Test FPGA Tools All Slots') { - node(get_task_label(task: 'runtime_all_slots', xilinx_version: default_xilinx_version)) { - test_fpga_all_slots() - } - } - } -} - //============================================================================= // Simulations //============================================================================= @@ -568,578 +341,6 @@ if (test_sims) { } } -//============================================================================= -// Non root access Test -//============================================================================= -if (test_non_root_access) { - all_tests['Test non-root access to FPGA tools'] = { - stage('Test non-root access to FPGA tools') { - node(get_task_label(task: 'runtime', xilinx_version: default_xilinx_version)) { - test_run_non_root_access() - } - } - } -} - -//============================================================================= -// Driver Tests -//============================================================================= -if (test_xdma) { - all_tests['Test XDMA Driver'] = { - stage('Test XDMA Driver') { - node(get_task_label(task: 'runtime', xilinx_version: default_xilinx_version)) { - test_xdma_driver() - } - } - } -} - -//============================================================================= -// Python Binding Test -//============================================================================= -if (test_py_bindings) { - all_tests['Test Python Bindings'] = { - stage('Test Python Bindings') { - node('f1.2xl_runtime_test_al2') { - test_run_py_bindings() - } - } - } -} - -//============================================================================= -// Precompiled Runtime Tests -//============================================================================= -if(disable_runtime_tests) { - echo "Runtime tests disabled. Not running Test Runtime Software stages" -} else { - if (test_runtime_software) { - all_tests['Test Runtime Software'] = { - stage('Test Runtime Software') { - def nodes = [:] - def node_types = ['runtime', 'runtime_all_slots'] - for (n in node_types) { - node_type = n - for (x in runtime_sw_cl_names) { - String cl_name = x - String node_name = "Undefined" - switch (node_type) { - case "runtime": - node_name = "Test Runtime Software ${default_xilinx_version} f1.2xl ${cl_name}" - break; - case "runtime_all_slots": - node_name = "Test Runtime Software ${default_xilinx_version} f1.16xl ${cl_name}" - break; - } - String node_label = get_task_label(task: node_type, xilinx_version: default_xilinx_version) - nodes[node_name] = { - node(node_label) { - String test = "hdk/tests/test_load_afi.py::TestLoadAfi::test_precompiled_${cl_name}" - String report_file = "test_runtime_software_${cl_name}.xml" - checkout scm - - try { - sh """ - set -e - source $WORKSPACE/shared/tests/bin/setup_test_sdk_env.sh - python2.7 -m pytest -v ${test} --junit-xml $WORKSPACE/${report_file} - """ - } finally { - run_junit(report_file) - } - } - } - } - } - parallel nodes - } - } - } -} - -//============================================================================= -// DCP Recipe Tests -//============================================================================= -if (test_dcp_recipes) { - all_tests['Test DCP Recipes'] = { - stage('Test DCP Recipes') { - def nodes = [:] - for (version in xilinx_versions) { - String xilinx_version = version - - for (cl in dcp_recipe_cl_names) { - String cl_name = cl - for (s in dcp_recipe_scenarios) { - String recipe_scenario = s - String node_name = "Test DCP Recipe ${cl_name}[${xilinx_version}-${recipe_scenario}]" - nodes[node_name] = { - node(get_task_label(task: 'dcp_gen', xilinx_version: xilinx_version)) { - String test_name = "test_${cl_name}[${xilinx_version}-${recipe_scenario}]" - String report_file = "test_dcp_recipe_${cl_name}[${xilinx_version}-${recipe_scenario}].xml" - String build_dir = "hdk/cl/examples/${cl_name}/build" - checkout scm - try { - sh """ - set -e - source $WORKSPACE/shared/tests/bin/setup_test_hdk_env.sh - python2.7 -m pytest -s -v hdk/tests/test_gen_dcp.py::TestGenDcp::${test_name} --junit-xml $WORKSPACE/${report_file} --xilinxVersion ${xilinx_version} - """ - } catch(exc) { - echo "${test_name} DCP generation failed: archiving results" - archiveArtifacts artifacts: "${build_dir}/**", fingerprint: true - throw exc - } finally { - run_junit(report_file) - } - } - } - } - } - } - - parallel nodes - } - } -} - -//============================================================================= -// HDK Full Developer Flow Tests -//============================================================================= -if (test_hdk_fdf) { - // Top level stage for FDF - // Each CL will have its own parallel FDF stage under this one. - all_tests['HDK_FDF'] = { - stage('HDK FDF') { - def fdf_stages = [:] - for (version in xilinx_versions) { - String xilinx_version = version - - for (x in fdf_test_names) { - String fdf_test_name = x - String cl_name = "" - - if (fdf_test_name.contains('[')) { - def split_test = fdf_test_name.split(/\[/) - def test_base_name = split_test[0] - def test_args = split_test[1] - - fdf_test_name = "$test_base_name[$xilinx_version-$test_args" - cl_name = test_base_name - } - - String fdf_stage_name = "FDF ${xilinx_version} ${fdf_test_name}" - fdf_stages[fdf_stage_name] = { - stage(fdf_stage_name) { - echo "Generate DCP for ${xilinx_version} ${fdf_test_name}" - String build_dir = "hdk/cl/examples/${cl_name}/build" - String dcp_stash_name = "dcp_tarball_${fdf_test_name}_${xilinx_version}".replaceAll(/[\[\]]/, "_") - String dcp_stash_dir = "${build_dir}/checkpoints/to_aws" - String afi_stash_name = "afi_${fdf_test_name}_${xilinx_version}".replaceAll(/[\[\]]/, "_") - String afi_stash_dir = "${build_dir}/create_afi" - echo "dcp_stash_name=${dcp_stash_name}" - echo "afi_stash_name=$afi_stash_name}" - node(get_task_label(task: 'dcp_gen', xilinx_version: xilinx_version)) { - String test = "hdk/tests/test_gen_dcp.py::TestGenDcp::test_${fdf_test_name}" - String report_file = "test_dcp_${fdf_test_name}_${xilinx_version}.xml" - checkout scm - // Clean out the to_aws directory to make sure there are no artifacts left over from a previous build - try { - sh """ - rm -rf ${dcp_stash_dir} - """ - } catch(exc) { - // Ignore any errors - echo "Failed to clean ${dcp_stash_dir}" - } - try { - sh """ - set -e - source $WORKSPACE/shared/tests/bin/setup_test_hdk_env.sh - python2.7 -m pytest -v ${test} --junit-xml $WORKSPACE/${report_file} --xilinxVersion ${xilinx_version} - """ - } catch (exc) { - echo "${fdf_test_name} DCP generation failed: archiving results" - archiveArtifacts artifacts: "${build_dir}/**", fingerprint: true - throw exc - } finally { - run_junit(report_file) - } - try { - stash name: dcp_stash_name, includes: "${dcp_stash_dir}/**" - } catch (exc) { - echo "stash ${dcp_stash_name} failed:\n${exc}" - } - } - node(get_task_label(task: 'create_afi', xilinx_version: xilinx_version)) { - echo "Generate AFI for ${xilinx_version} ${fdf_test_name}" - checkout scm - String test = "hdk/tests/test_create_afi.py::TestCreateAfi::test_${fdf_test_name}" - String report_file = "test_create_afi_${fdf_test_name}_${xilinx_version}.xml" - // Clean out the stash directories to make sure there are no artifacts left over from a previous build - try { - sh """ - rm -rf ${dcp_stash_dir} - """ - } catch(exc) { - // Ignore any errors - echo "Failed to clean ${dcp_stash_dir}" - } - try { - sh """ - rm -rf ${afi_stash_dir} - """ - } catch(exc) { - // Ignore any errors - echo "Failed to clean ${afi_stash_dir}" - } - try { - unstash name: dcp_stash_name - } catch (exc) { - echo "unstash ${dcp_stash_name} failed:\n${exc}" - //throw exc - } - try { - // There is a Xilinx bug that causes the following error during hdk_setup.sh if multiple - // processes are doing it at the same time: - // WARNING: [Common 17-1221] Tcl app 'xsim' is out of date for this release. Please run tclapp::reset_tclstore and reinstall the app. - // ERROR: [Common 17-685] Unable to load Tcl app xilinx::xsim - // ERROR: [Common 17-69] Command failed: ERROR: [Common 17-685] Unable to load Tcl app xilinx::xsim - sh """ - set -e - source $WORKSPACE/shared/tests/bin/setup_test_env.sh - python2.7 -m pytest -v ${test} --junit-xml $WORKSPACE/${report_file} --xilinxVersion ${xilinx_version} - """ - } catch (exc) { - echo "${fdf_test_name} AFI generation failed: archiving results" - archiveArtifacts artifacts: "${build_dir}/to_aws/**", fingerprint: true - throw exc - } finally { - run_junit(report_file) - } - try { - stash name: afi_stash_name, includes: "${afi_stash_dir}/**" - } catch (exc) { - echo "stash ${afi_stash_name} failed:\n${exc}" - } - } - - if(disable_runtime_tests) { - echo "Runtime tests disabled. Not running runtime ${fdf_test_name}" - } else { - node(get_task_label(task: 'runtime', xilinx_version: xilinx_version)) { - String test = "hdk/tests/test_load_afi.py::TestLoadAfi::test_${fdf_test_name}" - String report_file = "test_load_afi_${fdf_test_name}_${xilinx_version}.xml" - checkout scm - echo "Test AFI for ${xilinx_version} ${fdf_test_name} on F1 instance" - // Clean out the stash directories to make sure there are no artifacts left over from a previous build - try { - sh """ - rm -rf ${afi_stash_dir} - """ - } catch(exc) { - // Ignore any errors - echo "Failed to clean ${afi_stash_dir}" - } - try { - unstash name: afi_stash_name - } catch (exc) { - echo "unstash ${afi_stash_name} failed:\n${exc}" - } - try { - sh """ - set -e - source $WORKSPACE/shared/tests/bin/setup_test_sdk_env.sh - python2.7 -m pytest -v ${test} --junit-xml $WORKSPACE/${report_file} --xilinxVersion ${xilinx_version} - """ - } finally { - run_junit(report_file) - } - } - } //else - } // stage( - } - } // for (x in fdf_test_names) - - } // for (xilinx_version in xilinx_versions) { - - parallel fdf_stages - } - } -} - -//============================================================================= -// SDAccel Tests -//============================================================================= - -if (test_sdaccel_scripts) { - all_tests['Test SDAccel Scripts'] = { - stage('Test SDAccel Scripts') { - def nodes = [:] - for (def xilinx_version in xilinx_versions) { - - String node_label = get_task_label(task: 'source_scripts', xilinx_version: xilinx_version) - String node_name = "Test SDAccel Scripts ${xilinx_version}" - nodes[node_name] = { - node(node_label) { - String report_file = "test_sdaccel_scripts_${xilinx_version}.xml" - checkout scm - try { - sh """ - set -e - source $WORKSPACE/shared/tests/bin/setup_test_env.sh - python2.7 -m pytest -v $WORKSPACE/SDAccel/tests/test_sdaccel_scripts.py --junit-xml $WORKSPACE/${report_file} - """ - } finally { - run_junit(report_file) - } - } - } - } - parallel nodes - } - } -} - -if (test_helloworld_sdaccel_example_fdf || test_all_sdaccel_examples_fdf) { - all_tests['Run SDAccel Tests'] = { - String sdaccel_examples_list = 'sdaccel_examples_list.json' - - def sdaccel_all_version_stages = [:] - - for (def version in xilinx_versions) { - - String xilinx_version = version - String sdaccel_base_stage_name = "SDx FDF $xilinx_version" - String sdaccel_find_stage_name = "SDx Find tests $xilinx_version" - - sdaccel_all_version_stages[sdaccel_base_stage_name] = { - stage (sdaccel_find_stage_name) { - - node(get_task_label(task: 'find_tests', xilinx_version: xilinx_version)) { - - checkout scm - String report_file = "test_find_sdaccel_examples_${xilinx_version}.xml" - - try { - sh """ - rm -rf ${sdaccel_examples_list} - """ - } catch(error) { - // Ignore any errors - echo "Failed to clean ${sdaccel_examples_list}" - } - - try { - sh """ - set -e - source $WORKSPACE/shared/tests/bin/setup_test_build_sdaccel_env.sh - python2.7 -m pytest -v $WORKSPACE/SDAccel/tests/test_find_sdaccel_examples.py --junit-xml $WORKSPACE/${report_file} - """ - } catch (exc) { - echo "Could not find tests. Please check the repository." - throw exc - } finally { - run_junit(report_file) - } - - // Only run the hello world test by default - //def example_map = [ 'Hello_World': 'SDAccel/examples/xilinx/getting_started/host/helloworld_ocl' ] - def example_map = sdaccel_example_default_map.get(xilinx_version) - - // Run all examples when parameter set - if (test_all_sdaccel_examples_fdf) { - example_map = readJSON file: sdaccel_examples_list - } - - def sdaccel_build_stages = [:] - - for ( def e in entrySet(example_map) ) { - - String test_key = e.key - def dsa_map_for_version = dsa_map.get(xilinx_version) - - // dsa = [ 4DDR: 4ddr ] - for ( def dsa in entrySet(dsa_map_for_version) ) { - - String build_name = "SDx ${e.key}_${dsa.value}_${xilinx_version}" - String example_path = e.value - - String dsa_name = dsa.key - String dsa_rte_name = dsa.value - - String sw_emu_stage_name = "SDx SW_EMU ${build_name}" - String hw_emu_stage_name = "SDx HW_EMU ${build_name}" - String hw_stage_name = "SDx HW ${build_name}" - String create_afi_stage_name = "SDx AFI ${build_name}" - String run_example_stage_name = "SDx RUN ${build_name}" - - String sw_emu_report_file = "sdaccel_sw_emu_${e.key}_${dsa.value}_${xilinx_version}.xml" - String hw_emu_report_file = "sdaccel_hw_emu_${e.key}_${dsa.value}_${xilinx_version}.xml" - String hw_report_file = "sdaccel_hw_${e.key}_${dsa.value}_${xilinx_version}.xml" - String create_afi_report_file = "sdaccel_create_afi_${e.key}_${dsa.value}_${xilinx_version}.xml" - String run_example_report_file = "sdaccel_run_${e.key}_${dsa.value}_${xilinx_version}.xml" - - String description_file = "${example_path}/description.json" - def description_json = ["targets":["hw","hw_emu","sw_emu"]] - - try { - description_json = readJSON file: description_file - } - catch (exc) { - echo "Could not read the file: ${description_file}" - throw exc - } - - boolean test_sw_emu_supported = true - - if(description_json["targets"]) { - if(description_json["targets"].contains("sw_emu")) { - test_sw_emu_supported = true - echo "Description file ${description_file} has target sw_emu" - } else { - test_sw_emu_supported = false - echo "Description file ${description_file} does not have target sw_emu" - } - } else { - echo "Description json did not have a 'target' key" - } - - sdaccel_build_stages[build_name] = { - if(test_sw_emu_supported) { - stage(sw_emu_stage_name) { - node(get_task_label(task: 'sdaccel_builds', xilinx_version: xilinx_version)) { - checkout scm - try { - sh """ - set -e - source $WORKSPACE/shared/tests/bin/setup_test_build_sdaccel_env.sh - export AWS_PLATFORM=\$AWS_PLATFORM_${dsa_name} - python2.7 -m pytest -v $WORKSPACE/SDAccel/tests/test_build_sdaccel_example.py::TestBuildSDAccelExample::test_sw_emu --examplePath ${example_path} --junit-xml $WORKSPACE/${sw_emu_report_file} --timeout=14400 --rteName ${dsa_rte_name} --xilinxVersion ${xilinx_version} - """ - } catch (error) { - echo "${sw_emu_stage_name} SW EMU Build generation failed" - archiveArtifacts artifacts: "${example_path}/**", fingerprint: true - throw error - } finally { - run_junit(sw_emu_report_file) - git_cleanup() - } - } - } - } - - stage(hw_emu_stage_name) { - node(get_task_label(task: 'sdaccel_builds', xilinx_version: xilinx_version)) { - checkout scm - try { - sh """ - set -e - source $WORKSPACE/shared/tests/bin/setup_test_build_sdaccel_env.sh - export AWS_PLATFORM=\$AWS_PLATFORM_${dsa_name} - python2.7 -m pytest -v $WORKSPACE/SDAccel/tests/test_build_sdaccel_example.py::TestBuildSDAccelExample::test_hw_emu --examplePath ${example_path} --junit-xml $WORKSPACE/${hw_emu_report_file} --timeout=21600 --rteName ${dsa_rte_name} --xilinxVersion ${xilinx_version} - """ - } catch (error) { - echo "${hw_emu_stage_name} HW EMU Build generation failed" - archiveArtifacts artifacts: "${example_path}/**", fingerprint: true - throw error - } finally { - run_junit(hw_emu_report_file) - git_cleanup() - } - } - } - - stage(hw_stage_name) { - node(get_task_label(task: 'sdaccel_builds', xilinx_version: xilinx_version)) { - checkout scm - try { - sh """ - set -e - source $WORKSPACE/shared/tests/bin/setup_test_build_sdaccel_env.sh - export AWS_PLATFORM=\$AWS_PLATFORM_${dsa_name} - python2.7 -m pytest -s -v $WORKSPACE/SDAccel/tests/test_build_sdaccel_example.py::TestBuildSDAccelExample::test_hw_build --examplePath ${example_path} --junit-xml $WORKSPACE/${hw_report_file} --timeout=36000 --rteName ${dsa_rte_name} --xilinxVersion ${xilinx_version} - """ - } catch (error) { - echo "${hw_stage_name} HW Build generation failed" - archiveArtifacts artifacts: "${example_path}/**", fingerprint: true - throw error - } finally { - run_junit(hw_report_file) - git_cleanup() - } - } - } - - stage(create_afi_stage_name) { - node(get_task_label(task: 'create_afi', xilinx_version: xilinx_version)) { - - checkout scm - try { - sh """ - set -e - source $WORKSPACE/shared/tests/bin/setup_test_build_sdaccel_env.sh - export AWS_PLATFORM=\$AWS_PLATFORM_${dsa_name} - python2.7 -m pytest -s -v $WORKSPACE/SDAccel/tests/test_create_sdaccel_afi.py::TestCreateSDAccelAfi::test_create_sdaccel_afi --examplePath ${example_path} --junit-xml $WORKSPACE/${create_afi_report_file} --timeout=18000 --rteName ${dsa_rte_name} --xilinxVersion ${xilinx_version} - """ - } catch (error) { - echo "${create_afi_stage_name} Create AFI failed" - archiveArtifacts artifacts: "${example_path}/**", fingerprint: true - throw error - } finally { - - String to_aws_dir = "${example_path}/to_aws" - - if (fileExists(to_aws_dir)) { - sh "rm -rf ${to_aws_dir}" - } - run_junit(create_afi_report_file) - git_cleanup() - } - } - } - - stage(run_example_stage_name) { - - if(disable_runtime_tests) { - echo "Runtime tests disabled. Not running ${run_example_stage_name}" - } else { - node(get_task_label(task: 'runtime', xilinx_version: xilinx_version)) { - - checkout scm - try { - sh """ - set -e - source $WORKSPACE/shared/tests/bin/setup_test_runtime_sdaccel_env.sh - export AWS_PLATFORM=\$AWS_PLATFORM_${dsa_name} - python2.7 -m pytest -v $WORKSPACE/SDAccel/tests/test_run_sdaccel_example.py::TestRunSDAccelExample::test_run_sdaccel_example --examplePath ${example_path} --junit-xml $WORKSPACE/${run_example_report_file} --timeout=14400 --rteName ${dsa_rte_name} --xilinxVersion ${xilinx_version} - """ - } catch (error) { - echo "${run_example_stage_name} Runtime example failed" - archiveArtifacts artifacts: "${example_path}/**", fingerprint: true - input message: "SDAccel Runtime test failed. Click Proceed or Abort when you are done debugging on the instance." - throw error - } finally { - run_junit(run_example_report_file) - git_cleanup() - } - } - } //else - - } - - } // sdaccel_build_stages[ e.key ] - - } //for ( def dsa in entrySet(dsa_map_for_version) ) { - } // for ( e in list_map ) - - parallel sdaccel_build_stages - } - } - } - } //for (def xilinx_version in xilinx_versions) { - parallel sdaccel_all_version_stages - } -} //============================================================================= // SDK Tests diff --git a/README.md b/README.md index f1cc5c259..914474889 100644 --- a/README.md +++ b/README.md @@ -20,7 +20,7 @@ # Overview of AWS EC2 FPGA Development Kit -The AWS EC2 FPGA Development Kit is provided by AWS to support development and runtime on [AWS FPGA instances](https://aws.amazon.com/ec2/instance-types/f1/). Amazon EC2 FPGA instances are high-performance compute instances with field programmable gate arrays (FPGAs) that are programmed to create custom hardware accelerations in EC2. F1 instances are easy to program and AWS provides everything needed to develop, simulate, debug, compile and run hardware accelerated applications. Using the [FPGA developer AMI](https://aws.amazon.com/marketplace/pp/B06VVYBLZZ), developers create an FPGA design. Once the FPGA design (also called CL - Custom logic) is complete, developers create the Amazon FPGA Image (AFI), and easily deploy it to the F1 instance. AFIs are reusable, shareable and can be deployed in a scalable and secure way. +The AWS EC2 FPGA Development Kit is provided by AWS to support development and runtime on [AWS FPGA instances](https://aws.amazon.com/ec2/instance-types/f1/). Amazon EC2 FPGA instances are high-performance compute instances with field programmable gate arrays (FPGAs) that are programmed to create custom hardware accelerations in EC2. F1 instances are easy to program and AWS provides everything needed to develop, simulate, debug, compile and run hardware accelerated applications. Using the [FPGA Developer AMI](https://aws.amazon.com/marketplace/pp/B06VVYBLZZ), developers create an FPGA design. Once the FPGA design (also called CL - Custom logic) is complete, developers create the Amazon FPGA Image (AFI), and easily deploy it to the F1 instance. AFIs are reusable, shareable and can be deployed in a scalable and secure way. ![Alt text](hdk/docs/images/f1-Instance-How-it-Works-flowchart.jpg) @@ -46,10 +46,10 @@ The AWS EC2 FPGA Development Kit is provided by AWS to support development and r | Tool | Development/Runtime | Tool location | Description | | --------|---------|---------|---------| -| SDx 2017.4, 2018.2 & 2018.3 | Development | [FPGA developer AMI](https://aws.amazon.com/marketplace/pp/B06VVYBLZZ) | Used for [Software Defined Accelerator Development](SDAccel/README.md) | -| Vivado 2017.4, 2018.2 & 2018.3 | Development | [FPGA developer AMI](https://aws.amazon.com/marketplace/pp/B06VVYBLZZ) | Used for [Hardware Accelerator Development](hdk/README.md) | +| SDx 2017.4, 2018.2, 2018.3 & 2019.1| Development | [FPGA Developer AMI](https://aws.amazon.com/marketplace/pp/B06VVYBLZZ) | Used for [Software Defined Accelerator Development](SDAccel/README.md) | +| Vivado 2017.4, 2018.2, 2018.3 & 2019.1 | Development | [FPGA Developer AMI](https://aws.amazon.com/marketplace/pp/B06VVYBLZZ) | Used for [Hardware Accelerator Development](hdk/README.md) | | FPGA AFI Management Tools | Runtime | [SDK - fpga\_mgmt\_tools](sdk/userspace/fpga_mgmt_tools) | Command-line tools used for FPGA management while running on the F1 instance | -| Virtual JTAG | Development (Debug) | [FPGA developer AMI](https://aws.amazon.com/marketplace/pp/B06VVYBLZZ) | Runtime debug waveform | +| Virtual JTAG | Development (Debug) | [FPGA Developer AMI](https://aws.amazon.com/marketplace/pp/B06VVYBLZZ) | Runtime debug waveform | | wait\_for\_afi | Development | [wait\_for\_afi.py](shared/bin/scripts/wait_for_afi.py) | Helper script that notifies via email on AFI generation completion | | notify\_via\_sns | Development | [notify\_via\_sns.py](shared/bin/scripts/notify_via_sns.py) | Notifies developer when design build process completes | | AFI Administration | Development | [Copy](hdk/docs/copy_fpga_image.md), [Delete](hdk/docs/delete_fpga_image.md), [Describe](hdk/docs/describe_fpga_images.md), [Attributes](hdk/docs/fpga_image_attributes.md) | AWS CLI EC2 commands for managing your AFIs | @@ -85,7 +85,10 @@ AWS FPGA generation and EC2 F1 instances are supported in the us-east-1 (N. Virg ### New to AWS FPGAs and setting up a development environment? -The developer kit is supported for Linux operating systems only. You have the choice to develop on AWS EC2 using the [FPGA developer AMI](https://aws.amazon.com/marketplace/pp/B06VVYBLZZ) or on-premises. Within a linux environment, you can execute `git clone https://github.com/aws/aws-fpga.git` to download the latest release to your EC2 Instance or local server. Help on cloning from github is available [here](https://help.github.com/articles/which-remote-url-should-i-use/). When using a SSH connection, execute `git clone git@github.com:aws/aws-fpga.git`. [To get help with connecting to Github via SSH](https://help.github.com/articles/connecting-to-github-with-ssh/). +The developer kit is supported for Linux operating systems only. +You have the choice to develop on AWS EC2 using the [FPGA Developer AMI](https://aws.amazon.com/marketplace/pp/B06VVYBLZZ) or on-premises. Within a linux environment, you can execute `git clone https://github.com/aws/aws-fpga.git` to download the latest release to your EC2 Instance or local server. Help on cloning from github is available [here](https://help.github.com/articles/which-remote-url-should-i-use/). When using a SSH connection, execute `git clone git@github.com:aws/aws-fpga.git`. [To get help with connecting to Github via SSH](https://help.github.com/articles/connecting-to-github-with-ssh/). + +To setup your instance for development, checkout our [Developer Resources](./developer_resources/README.md) where we provide Step-By-Step guides to setting up a GUI Desktop or a compute cluster. Before you start your first AWS FPGA design, we recommend that you go through one of the step-by-step guides. The guides will walk through development steps for hello world examples. Based on the tables above, pick the development environment that best fits your needs and use the guide to get started: * For fastest way to get started on FPGA accelerator development, start with the software defined development environment. The guide starts with the [SW Hello World example](SDAccel/README.md). @@ -106,20 +109,21 @@ Once you have completed your hello world examples, we recommend diving deeper in # FPGA Developer AMI -The [FPGA developer AMI](https://aws.amazon.com/marketplace/pp/B06VVYBLZZ) is available on the AWS marketplace without a software charge and includes free tools and drivers needed for FPGA development on EC2 instances. FPGA development runs on several [EC2 instance types](https://aws.amazon.com/ec2/instance-types/). Given the large size of the FPGA used inside the AWS FPGA instances, the implementation tools require 32GiB Memory (ex: z1d.xlarge, z1d.2xlarge, c5.4xlarge, m5.2xlarge, r5.xlarge, t2.2xlarge). z1d.xlarge/c5.4xlarge and z1d.2xlarge/c5.8xlarge would provide the fastest execution time with 30GiB+ and 60GiB+ of memory respectively. Developers who want to save on cost, could start coding and run simulations on low-cost instances, like t2.2xlarge, and move to the aforementioned larger instances to run the synthesis of their acceleration code. +The [FPGA Developer AMI](https://aws.amazon.com/marketplace/pp/B06VVYBLZZ) is available on the AWS marketplace without a software charge and includes free tools and drivers needed for FPGA development on EC2 instances. FPGA development runs on several [EC2 instance types](https://aws.amazon.com/ec2/instance-types/). Given the large size of the FPGA used inside the AWS FPGA instances, the implementation tools require 32GiB Memory (ex: z1d.xlarge, z1d.2xlarge, c5.4xlarge, m5.2xlarge, r5.xlarge, t2.2xlarge). z1d.xlarge/c5.4xlarge and z1d.2xlarge/c5.8xlarge would provide the fastest execution time with 30GiB+ and 60GiB+ of memory respectively. Developers who want to save on cost, could start coding and run simulations on low-cost instances, like t2.2xlarge, and move to the aforementioned larger instances to run the synthesis of their acceleration code. -Currently, AWS marketplace includes multiple versions of the FPGA developer AMI, supporting Xilinx SDx 2017.4, 2018.2 and 2018.3 toolchain versions. The following compatibility table describes the mapping of currently supported developer kit versions to AMI versions: +Currently, AWS marketplace includes multiple versions of the FPGA Developer AMI, supporting Xilinx SDx 2017.4, 2018.2, 2018.3 and 2019.1 toolchain versions. The following compatibility table describes the mapping of currently supported developer kit versions to AMI versions: -| Developer Kit Version | Tool Version Supported | Compatible FPGA developer AMI Version | +| Developer Kit Version | Tool Version Supported | Compatible FPGA Developer AMI Version | |-----------|-----------|------| | 1.3.7-1.3.X | 2017.4 | v1.4.0-v1.4.X (Xilinx Vivado/SDx 2017.4) | | 1.4.X | 2017.4 | v1.4.0-v1.4.X (Xilinx Vivado/SDx 2017.4) | | 1.4.3+ | 2018.2 | v1.5.0-v1.5.X (Xilinx Vivado/SDx 2018.2) | | 1.4.8+ | 2018.3 | v1.6.0-v1.6.X (Xilinx Vivado/SDx 2018.3) | +| 1.4.11+ | 2019.1 | v1.7.0-v1.7.X (Xilinx Vivado/SDx 2019.1) | Developer kit versions prior to v1.3.7 and Developer AMI prior to v1.4 (2017.1) reached end-of-life. See [AWS forum announcement](https://forums.aws.amazon.com/ann.jspa?annID=6068) for additional details. - If developing using SDAccel environment please refer to this [Runtime Compatibility Table](SDAccel/docs/Create_Runtime_AMI.md#runtime-ami-compatability-table) +If developing using SDAccel environment please refer to this [Runtime Compatibility Table](SDAccel/docs/Create_Runtime_AMI.md#runtime-ami-compatibility-table) # Hardware Development Kit (HDK) @@ -178,7 +182,7 @@ The documentation is located throughout this developer kit, therefore, to help d | AFI Management | [README](sdk/userspace/fpga_mgmt_tools/README.md) | CLI documentation for managing AFI on the F1 instance | | AFI Administration | [copy\_fpga\_image](hdk/docs/copy_fpga_image.md), [delete\_fpga\_image](hdk/docs/delete_fpga_image.md), [describe\_fpga\_images](hdk/docs/describe_fpga_images.md), [fpga\_image\_attributes](hdk/docs/fpga_image_attributes.md) | CLI documentation for administering AFIs | | AFI Creation Error Codes | [create\_fpga\_image\_error\_codes](hdk/docs/create_fpga_image_error_codes.md) | CLI documentation for managing AFIs | -| Developing on-premises | [HDK: on\_premise\_licensing\_help](hdk/docs/on_premise_licensing_help.md), [SDAccel: On\_Premises\_Development\_Steps](SDAccel/docs/On_Premises_Development_Steps.md) | Guidance for developer wanting to develop AFIs from on-premises instead of using the [FPGA developer AMI](https://aws.amazon.com/marketplace/pp/B06VVYBLZZ) running on AWS EC2 | +| Developing on-premises | [HDK: on\_premise\_licensing\_help](hdk/docs/on_premise_licensing_help.md), [SDAccel: On\_Premises\_Development\_Steps](SDAccel/docs/On_Premises_Development_Steps.md) | Guidance for developer wanting to develop AFIs from on-premises instead of using the [FPGA Developer AMI](https://aws.amazon.com/marketplace/pp/B06VVYBLZZ) running on AWS EC2 | diff --git a/RELEASE_NOTES.md b/RELEASE_NOTES.md index 0fdff1a3f..f500d1c6d 100644 --- a/RELEASE_NOTES.md +++ b/RELEASE_NOTES.md @@ -1,7 +1,5 @@ - # AWS EC2 FPGA HDK+SDK Release Notes - ## AWS EC2 F1 Platform Features: * 1-8 Xilinx UltraScale+ VU9P based FPGA slots * Per FPGA Slot, Interfaces available for Custom Logic(CL): @@ -26,6 +24,34 @@ * 1 DDR controller implemented in the SH (always available) * 3 DDR controllers implemented in the CL (configurable number of implemented controllers allowed) +## Release 1.4.11 (See [ERRATA](./ERRATA.md) for unsupported features) +* FPGA developer kit now supports Xilinx SDx/Vivado 2019.1 + * We recommend developers upgrade to v1.4.11 to benefit from the new features, bug fixes, and optimizations. + * To upgrade, use [Developer AMI v1.7.0](https://aws.amazon.com/marketplace/pp/B06VVYBLZZ) on the AWS Marketplace. The Developer Kit scripts (hdk_setup.sh or sdaccel_setup.sh) will detect the tool version and update the environment based on requirements needed for Xilinx 2019.1 tools. +* New functionality: + * Added a [developer resources section](./developer_resources/README.md) that provides guides on how to setup your own GUI Desktop and compute cluster environment. + * Developers can now ask for AFI limit increases via the [AWS Support Center Console](https://console.aws.amazon.com/support/cases#/create). + * Create a case to increase your `EC2 FPGA` service limit from the console. + * HLx IPI flow updates + * HLx support for AXI Fast Memory mode. + * HLx support for 3rd party simulations. + * HLx support for changes in shell and AWS IP updates(e.g. sh_ddr). +* Bug Fixes: + * Documentation fixes in the [Shell Interface Specification](./hdk/docs/AWS_Shell_Interface_Specification.md) + * Fixes for forum questions + * [Unable to compile aws_v1_0_vl_rfs.sv in Synopsys VCS](https://forums.aws.amazon.com/thread.jspa?threadID=308829&tstart=0) + * [Use fpga_mgmt init in HLx runtime](https://forums.aws.amazon.com/thread.jspa?messageID=912063) + * New XRT versions added to the [XRT Installation Instructions](./SDAccel/docs/XRT_installation_instructions.md) to fix segmentation faults when using xclbin instead of awsxclbin files. +* Deprecations: + * Removed GUI Setup scripts from AMI v1.7.0 onwards. See the [developer resources section](./developer_resources/README.md) that provides guides on how to setup your own GUI Desktop and compute cluster environment. +* Package versions used for validation + + | Package | AMI 1.7.0 [2019.1] | AMI 1.6.0 [2018.3] |AMI 1.5.0 [2018.2] | AMI 1.4.0 [2017.4] | + |---------|---|------------------------|------------------------|-----------------------| + | OS | Centos 7.6 | Centos 7.6 | Centos 7.5, 7.6 | Centos 7.4 | + | kernel | 3.10.0-957.27.2.el7.x86_64 | 3.10.0-957.5.1.el7.x86_64 | 3.10.0-862.11.6.el7.x86_64, 3.10.0-957.1.3.el7.x86_64 | 3.10.0-693.21.1.el7.x86_64 | + | kernel-devel | 3.10.0-957.27.2.el7.x86_64 | 3.10.0-957.5.1.el7.x86_64 | 3.10.0-862.11.6.el7.x86_64, 3.10.0-957.1.3.el7.x86_64 | 3.10.0-693.21.1.el7.x86_64 | + | LIBSTDC++ | libstdc++-4.8.5-36.el7_6.2.x86_64 | libstdc++-4.8.5-36.el7.x86_64 | libstdc++-4.8.5-36.el7.x86_64 | libstdc++-4.8.5-16.el7_4.2.x86_64 | ## Release 1.4.10 (See [ERRATA](./ERRATA.md) for unsupported features) * New functionality: @@ -148,7 +174,7 @@ ## Release 1.4.5 (See [ERRATA](./ERRATA.md) for unsupported features) -* [Documents SDAccel Runtime compatibility](SDAccel/docs/Create_Runtime_AMI.md#runtime-ami-compatability-table) +* [Documents SDAccel Runtime compatibility](SDAccel/docs/Create_Runtime_AMI.md#runtime-ami-compatibility-table) * [Enables SDK FPGA Mgmt tool access to Non-root users](sdk/README.md#using-fpga-as-non-root-user) * Fixed issues * [HLX simulation failure](https://forums.aws.amazon.com/thread.jspa?threadID=293313&tstart=0) @@ -161,7 +187,7 @@ ## Release 1.4.3 (See [ERRATA](./ERRATA.md) for unsupported features) * [DRAM Data Retention](hdk/docs/data_retention.md) - With DRAM data retention, developers can simply load a new AFI and continue using the data that is persistently kept in the DRAM attached to the FPGA, eliminating unnecessary data movements and greatly improving the overall application performance. * [Virtual Ethernet](./sdk/apps/virtual-ethernet/README.md) - Provides a low latency network interface for EC2 F1, that enables high performance hardware acceleration to ethernet based applications on AWS like firewalls, routers and advanced security virtual appliances. With Virtual Ethernet, developers are able to create F1 accelerators that process ethernet packets directly from user-space on the FPGA with high throughput and low-latency. -* [Developer AMI v1.5](https://aws.amazon.com/marketplace/pp/B06VVYBLZZ) with Vivado/SDx 2018.2 tools - New FPGA developer AMI supporting Vivado 2018.2 for faster compile times, higher frequencies and improved timing closure +* [Developer AMI v1.5](https://aws.amazon.com/marketplace/pp/B06VVYBLZZ) with Vivado/SDx 2018.2 tools - New FPGA Developer AMI supporting Vivado 2018.2 for faster compile times, higher frequencies and improved timing closure ## Release 1.4.2 (See [ERRATA](./ERRATA.md) for unsupported features) * Fixed SDAccel XOCL driver compile fails that occur on linux kernels greater than 3.10.0-862.3.3.el7.x86_64 @@ -265,7 +291,7 @@ The following major features are included in this HDK release: * Restrictions on URAM have been updated to enable 100% of the URAM with a CL to be utilized. See documentation on enabling URAM utilization: [URAM_options](./hdk/docs/URAM_Options.md) ### 5. Vivado IP Integrator (IPI) and GUI Workflow -* Vivado graphical design canvas and project-based flow is now supported. This flow allows developers to create CL logic as either RTL or complex subsystems based on an IP centric block diagram. Prior experience in RTL or system block designs is recommended. The [IP Integrator and GUI Vivado workflow](hdk/docs/IPI_GUI_Vivado_Setup.md) enables a unified graphical environment to guide the developer through the common steps to design, implement, and verify FGPAs. To get started, start with the [README that will take you through getting started steps and documents on IPI](hdk/docs/IPI_GUI_Vivado_Setup.md) +* Vivado graphical design canvas and project-based flow is now supported. This flow allows developers to create CL logic as either RTL or complex subsystems based on an IP centric block diagram. Prior experience in RTL or system block designs is recommended. The [IP Integrator and GUI Vivado workflow](hdk/docs/IPI_GUI_Vivado_Setup.md) enables a unified graphical environment to guide the developer through the common steps to design, implement, and verify FPGAs. To get started, start with the [README that will take you through getting started steps and documents on IPI](hdk/docs/IPI_GUI_Vivado_Setup.md) ### 6. Build Flow improvments * See [Build_Scripts](./hdk/common/shell_v04261818/build/scripts) diff --git a/SDAccel/FAQ.md b/SDAccel/FAQ.md index 9786c55dd..6e3ff8714 100644 --- a/SDAccel/FAQ.md +++ b/SDAccel/FAQ.md @@ -1,51 +1,59 @@ # Frequently Asked Questions (FAQ) -## Q: When I run my application on F1, I see these errors: ERROR: Failed to load xclbin ERROR: No program executable for device ERROR: buffer (2) is not resident in device (0)", how to debug these errors? -A: First double check that your AFI has been generated successfully by reviewing the SDAccel README. Second, check that you are running your application on F1 using sudo. Lastly, check that your AWS CLI (configure) was configured using output format as json. +## Q: When I run my application on F1, I see these errors: ERROR: Failed to load xclbin ERROR: No program executable for device ERROR: buffer (2) is not resident in device (0)", how to debug these errors? +A: +* Check that your AFI has been generated successfully by reviewing the SDAccel README. +* Check that you are running your application on F1 as super user(sudo). +* Lastly, check that your AWS CLI (configure) was configured using output format as json. ## Q: During AFI generation (create_sdaccel_afi.sh), how do I resolve this error: "An error occurred (AuthFailure) when calling the CreateFpgaImage operation: AWS was not able to validate the provided access credentials"? -A: For an AFI generation to complete all errors must be resolved. This error ("An error occurred (AuthFailure) when calling the CreateFpgaImage operation: AWS was not able to validate the provided access credentials") message means your AWS credentials were not setup properly or your IAM does not have access to the API (CreateFpgaImage). Here is some additional info on how to setup IAM privileges. -http://docs.aws.amazon.com/AWSEC2/latest/APIReference/ec2-api-permissions.html +A: + +This error message means your AWS credentials or IAM role were not setup correctly to have access to the API (CreateFpgaImage). +AWS Accounts require IAM permissions to access API functions. To test your IAM permissions use [DescribeFpgaImage API](https://github.com/aws/aws-fpga/blob/master/hdk/docs/describe_fpga_images.md) + +To setup IAM privileges please check the [EC2 API Permissions documentation](http://docs.aws.amazon.com/AWSEC2/latest/APIReference/ec2-api-permissions.html) -AWS Accounts require IAM permisions to access API functions. To test your IAM permissions use DescribeFpgaImage API: -https://github.com/aws/aws-fpga/blob/master/hdk/docs/describe_fpga_images.md ## Q: During AFI generation (create_sdaccel_afi.sh), my AFI failed to generate and I see this error message in the log: "Provided clocks configuration is illegal. See AWS FPGA HDK documentation for supported clocks configuration. Frequency 0 is lower than minimal supported frequency of 80", how do I debug this message? -A: Please confirm that you successfully compiled your kernel for HW. For the quick start examples, you will need to have completed the quick start and successfully passed this command: make TARGETS=hw DEVICES=$AWS_PLATFORM all +A: +* Please confirm that you successfully compiled your kernel for HW. +* For the quick start examples, you will need to have completed the quick start and successfully passed this command: `make TARGETS=hw DEVICES=$AWS_PLATFORM all` -## Q: What is a xclbin or binary container on SDAccel? +## Q: What is a xclbin or binary container on SDAccel? What is an awsxclbin? A: The [xclbin](https://www.xilinx.com/html_docs/xilinx2017_2/sdaccel_doc/topics/design-flows/concept-create-compute-unit-binary.html) file or the "Binary Container" is a binary library of kernel compute units that will be loaded together into an OpenCL context for a specific device. -AWS uses a modified version of the xclbin called awsxclbin. The awsxclbin contains the xclbin metadata and AFI ID. +AWS uses a modified version of the xclbin called awsxclbin. The awsxclbin contains the xclbin metadata and AFI ID. ## Q: What can we investigate when xocc fails with a path not meeting timing? A: An example is WARNING: [XOCC 60-732] Link warning: One or more timing paths failed timing targeting MHz for . The frequency is being automatically changed to MHz to enable proper functionality. 1. Generally speaking, lowering the clock will make the design functionally operational in terms of operations (since there will not be timing failures) but the design might not operate at the performance needed due this clock frequency change. We can review what can be done. -1. If CLOCK_NAME is `kernel clock 'DATA_CLK'` then this is the clock that drives the kernels. Try reducing the kernel clock frequency see --kernel_frequency option to xocc in [latest SDAccel Environment User Guide] +1. If CLOCK_NAME is `kernel clock 'DATA_CLK'` then this is the clock that drives the kernels. Try reducing the kernel clock frequency see --kernel_frequency option to xocc in the [latest SDAccel Environment User Guide](https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug1023-sdaccel-user-guide.pdf). 1. If CLOCK_NAME is `system clock 'clk_main_a0'` then this is the clock clk_main_a0 which drives the AXI interconnect between the AWS Shell and the rest of the platform (SDAccel peripherals and user kernels). Using --kernel_frequency as above does not have any direct effect but might have side effect in changing the topology/placement of the design and improve this issue. 1. If OCL/C/C++ kernels were also used, investigate VHLS reports / correlate with kernel source code to see if there are functions with large number of statements in basic block, examples: might have unrolled loops with large loop-count, might have a 100++ latency; the VHLS runs and log files are located in the directory named `_xocc*compile*` 1. Try `xocc -O3` to run bitstream creation process with higher efforts. -1. Open a Vivado implementation project using ```vivado `find -name ipiimpl.xpr` ``` to analyze the design; needs Vivado knowledge; see [UltraFast Design Methodology Guide for the Vivado][latest UG949] +1. Open a Vivado implementation project using ```vivado `find -name ipiimpl.xpr` ``` to analyze the design; needs Vivado knowledge; see [UltraFast Design Methodology Guide for the Vivado](https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug949-vivado-design-methodology.pdf) ## Q: xocc issues message WARNING: [XOCC 204-69] Unable to schedule ...due to limited memory ports. A: This may lower the performance of the implementation. -Details on this are provided in [Debug HLS Performance: Limited memory ports] +Details on this are provided in [the SDAccel HLS Debug document](docs/SDAccel_HLS_Debug.md) ## Q: xocc fails due to routing/resource overflow -A: Examine utilization reports. If OCL/C/C++ kernels were also used, look into the source code for excessive unroll happening. +A: Examine utilization reports. If OCL/C/C++ kernels were also used, look into the source code for excessive unroll happening. ## Q: How do I open the design as a Vivado project (.xpr)? A: There are 2 Vivado project files: 1. CL Design - from command line: ```vivado `find -name ipiprj.xpr\` ``` to see the connectivity of the created design -1. Implementation project - from command line: ```vivado `find -name ipiimpl.xpr\` ``` to analyze the design in the place and routing design phases. For an additional Vivado Design reference, see [UltraFast Design Methodology Guide for the Vivado][latest UG949] +1. Implementation project - from command line: ```vivado `find -name ipiimpl.xpr\` ``` to analyze the design in the place and routing design phases. + 1. For an additional Vivado Design reference, see the [UltraFast Design Methodology Guide for the Vivado](https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug949-vivado-design-methodology.pdf) ## Q: What should I do if FPGA instance execution gets the wrong results or gets stuck? A: 1. Verify hw_emu works as expected -1. See "Chapter 4 - Debugging Applications in the SDAccel Environment" in [latest SDAccel Environment User Guide] +1. See the "Debugging Applications in the SDAccel Environment" chapter in the [latest SDAccel Environment User Guide](https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug1023-sdaccel-user-guide.pdf). ## Q: Bitstream creation fails to create design less that 60 MHz? A: SDAccel flow does not allow clocks running less than 60 MHz kernel clock, therefore, you will need to debug further using [HLS Debug suggestions](./docs/SDAccel_HLS_Debug.md) @@ -66,19 +74,14 @@ A: You may have run the previous [HDK IPI examples](../hdk/docs/IPI_GUI_Vivado_S ## Q: I am getting an error: `symbol lookup error: /opt/xilinx/xrt/lib/libxrt_aws.so: undefined symbol: uuid_parse` What should I do? A: This error occured because the XRT RPM was built without linking in a library needed for the uuid symbols. To fix it, use the latest XRT RPM's documented in the [XRT installation document](docs/XRT_installation_instructions.md) -# Additional Resources -The [AWS SDAccel README]. - -Xilinx web portal for [Xilinx SDAccel documentation] and for [Xilinx SDAccel GitHub repository] +# Additional Resources -Links pointing to **latest** version of the user guides - * [UG1023: SDAccel Environment User Guide][latest SDAccel Environment User Guide] - * [UG1021: SDAccel Environment Tutorial: Getting Started Guide (including emulation/build/running on H/W flow)][latest UG1021] - * [UG1207: SDAccel Environment Optimization Guide][latest SDAccel Environment Optimization Guide] - * [UG949: UltraFast Design Methodology Guide for the Vivado Design Suite][latest UG949] +* The [AWS SDAccel README](README.md). +* Xilinx web portal for [Xilinx SDAccel documentation](https://www.xilinx.com/products/design-tools/software-zone/sdaccel.html?resultsTablePreSelect=xlnxdocumenttypes:SeeAll#documentation) +* [Xilinx SDAccel GitHub repository](https://github.com/Xilinx/SDAccel_Examples) -Links pointing to **2017.4** version of the user guides +* Links pointing to **2017.4** version of the user guides * [UG1023: SDAccel Environment User Guide][UG1023 2017.4] * [UG1021: SDAccel Environment Tutorial: Getting Started Guide (including emulation/build/running on H/W flow)][UG1021 2017.4] * [UG1207: SDAccel Environment Optimization Guide][UG1207 2017.4] diff --git a/SDAccel/README.md b/SDAccel/README.md index 2bfdfa233..e89c4fb4f 100644 --- a/SDAccel/README.md +++ b/SDAccel/README.md @@ -63,9 +63,7 @@ It is highly recommended you read the documentation and utilize software and har $ cd $AWS_FPGA_REPO_DIR $ source sdaccel_setup.sh ``` - * This section describes the valid platforms for shell_v04261818 - * Xilinx Tool 2017.4 Platform: - * AWS_PLATFORM_DYNAMIC_5_0 - (Default) AWS F1 platform dynamically optimized for multi DDR use cases. + * Valid platforms for shell_v04261818: `AWS_PLATFORM_DYNAMIC_5_0` (Default) AWS F1 platform dynamically optimized for multi DDR use cases. * Changing to a different platform can be accomplished by setting AWS_PLATFORM environment variable. Only one platform is supported for this example:   ``` @@ -139,7 +137,7 @@ This assumes you have: The [create_sdaccel_afi.sh](./tools/create_sdaccel_afi.sh) script is provided to facilitate AFI creation from a Xilinx FPGA Binary, it: * Takes in your Xilinx FPGA Binary \*.xclbin file -* Calls *aws ec2 create_fgpa_image* to generate an AFI under the hood +* Calls *aws ec2 create_fpga_image* to generate an AFI under the hood * Generates a \_afi_id.txt which contains the identifiers for your AFI * Creates an AWS FPGA Binary file with an \*.awsxclbin extension that is composed of: Metadata and AGFI-ID. * **This \*.awsxclbin is the AWS FPGA Binary file that will need to be loaded by your host application to the FPGA** @@ -193,12 +191,11 @@ For help with AFI creation issues, see [create-fpga-image error codes](../hdk/do # 3. Run the FPGA accelerated application on Amazon FPGA instances -Here are the steps: -* Start an FPGA instance using [FPGA Developer AMI on AWS Marketplace](https://aws.amazon.com/marketplace/pp/B06VVYBLZZ) and check the AMI [compatiability table](../README.md#devAmi) and [runtime compatilibility table](docs/Create_Runtime_AMI.md#runtime-ami-compatability-table). Alternatively, you can [create your own Runtime AMI](docs/Create_Runtime_AMI.md) for running your SDAccel applications on Amazon FPGA instances. +* Start an FPGA instance using [FPGA Developer AMI on AWS Marketplace](https://aws.amazon.com/marketplace/pp/B06VVYBLZZ) and check the AMI [compatibility table](../README.md#devAmi) and [runtime compatibility table](docs/Create_Runtime_AMI.md#runtime-ami-compatibility-table). Alternatively, you can [create your own Runtime AMI](docs/Create_Runtime_AMI.md) for running your SDAccel applications on Amazon FPGA instances. * *Assuming the developer flow (compilation) was done on a separate instance you will need to:* * Copy the compiled host executable (exe) to the new instance * Copy the \*.awsxclbin AWS FPGA binary file to the new instance - * Depending on the host code, the \*.awsxclbin may need to named .hw..awsxclbin . Ex: ```vector_addition.hw.xilinx_aws-vu9p-f1-04261818_dynamic_5_0.awsxclbin``` + * Depending on the host code, the \*.awsxclbin may need to named \.hw.\.awsxclbin .For Example: ```vector_addition.hw.xilinx_aws-vu9p-f1-04261818_dynamic_5_0.awsxclbin``` * Copy any data files required for execution to the new instance * [Clone the github repository to the new F1 instance and install runtime drivers](#gitsetenv) * Clone the github repository to the new F1 instance and install runtime drivers @@ -212,7 +209,7 @@ Here are the steps: * Source the Runtime Environment & Execute your Host Application: ``` - $ sudo sh + $ sudo -E /bin/bash # source $AWS_FPGA_REPO_DIR/sdaccel_runtime_setup.sh # Other runtime env settings needed by the host app should be setup after this step # ./helloworld ``` diff --git a/SDAccel/docs/Create_Runtime_AMI.md b/SDAccel/docs/Create_Runtime_AMI.md index 1bd05c220..eadaf4ece 100644 --- a/SDAccel/docs/Create_Runtime_AMI.md +++ b/SDAccel/docs/Create_Runtime_AMI.md @@ -1,19 +1,20 @@ # Create a Runtime AMI Starting with an Amazon Linux AMI or Ubuntu -## Runtime AMI Compatability Table +## Runtime AMI Compatibility Table | SDx Version used for AFI Development | Compatible SDAccel Runtime | |--------------------------------------|-----------------------------| | 2017.4 | Runtime installed by sourcing "sdaccel_setup.sh" while using HDK Ver 1.4.X when environment variable RELEASE_VER=2017.4 | - | 2018.2 | AWS FPGA Developer AMI 1.5.0 ( XRT is pre-installed) or [Runtime installed with XRT Version 2.1.0](https://www.xilinx.com/html_docs/xilinx2018_2_xdf/sdaccel_doc/ejy1538090924727.html) | - | 2018.3 | AWS FPGA Developer AMI 1.6.0 ( XRT is pre-installed) or [Runtime installed with XRT Version 2.1.0](https://xilinx.github.io/XRT/2018.3/html/build.html) | + | 2018.2 | AWS FPGA Developer AMI 1.5.0 (XRT is pre-installed) or [Runtime installed with XRT Version 2.1.0](https://www.xilinx.com/html_docs/xilinx2018_2_xdf/sdaccel_doc/ejy1538090924727.html) | + | 2018.3 | AWS FPGA Developer AMI 1.6.0 (XRT is pre-installed) or [Runtime installed with XRT Version 2.1.0](https://xilinx.github.io/XRT/2018.3/html/build.html) | + | 2019.1 | AWS FPGA Developer AMI 1.7.0 (XRT is pre-installed) or [Runtime installed with XRT Version 2.1.0](https://xilinx.github.io/XRT/2019.1/html/build.html) | ## 1. Launch a Runtime Instance & Install Required Packages * Please note Amazon Linux 2 or Amazon Linux are not supported by Xilinx XRT at this time. Please use Centos/RHEL or Ubuntu when using Xilinx XRT Runtimes for the AFIs generated using Xilinx SDx 2018.2 and 2018.3 toolsets. -* Launch an F1 instance using an [Amazon Linux AMI](https://aws.amazon.com/marketplace/pp/B00635Y2IW) or [Centos 7](https://aws.amazon.com/marketplace/pp/B00O7WM7QW) -* Install the required updates +* Launch an F1 instance using [Centos 7](https://aws.amazon.com/marketplace/pp/B00O7WM7QW) or Amazon Linux AMI's +* Update to get the latest packages. ```` $ sudo yum update @@ -54,11 +55,11 @@ * Using an instance running [FPGA Developer AMI](https://aws.amazon.com/marketplace/pp/B06VVYBLZZ) or an on-premises machine with access to a Xilinx SDAccel Tools Installation, first source $AWS_FPGA_REPO_DIR/sdaccel_setup.sh and then run following commands: -* if using Ubuntu or debian distribution set GLIBPATH env variable to Ubuntu. If using any other OS distribution set GLIBPATH to default. +* If using Ubuntu or Debian distributions set GLIBPATH env variable to Ubuntu. If using any other OS distribution set GLIBPATH to default. -* set env variable 'XLNXRTE' to intended runtime install directory path. +* Set env variable 'XLNXRTE' to intended runtime install directory path. -### **For Vivado SDX 2017.4** +### **Xilinx SDX 2017.4: ** ```` $ export GLIBPATH= @@ -79,14 +80,12 @@ * You may need to update path in $XLNXRTE/setup.sh and $XLNXRTE/setup.csh script to match your runtime instance. * Copy $XLNXRTE directory created to $HOME on your Runtime Instance. -### **For Vivado SDX 2018.2** - - Please refer [installing Xilinx SDx 2018.2 XRT](https://www.xilinx.com/html_docs/xilinx2018_2_xdf/sdaccel_doc/ejy1538090924727.html) for instructions on how to install XRT on your AMI. +### **Xilinx SDx 2018.2:** [Install 2018.2 XRT](https://www.xilinx.com/html_docs/xilinx2018_2_xdf/sdaccel_doc/ejy1538090924727.html). -### **For Vivado SDX 2018.3** - - Please refer [installing Xilinx SDx 2018.3 XRT](https://xilinx.github.io/XRT/2018.3/html/build.html) for instructions on how to install runtime on your AMI. +### **Xilinx SDx 2018.3:** [Install 2018.3 XRT](https://xilinx.github.io/XRT/2018.3/html/build.html). +### **Xilinx SDx 2019.1:** [Install 2019.1 XRT](https://xilinx.github.io/XRT/2019.1/html/build.html). + ## 3. Install Runtime Drivers and run your FPGA accelerated application on your Runtime Instance. * Log back on to the Runtime Instance: diff --git a/SDAccel/docs/README_GUI.md b/SDAccel/docs/README_GUI.md index 0818eaac1..4ca59dcd4 100644 --- a/SDAccel/docs/README_GUI.md +++ b/SDAccel/docs/README_GUI.md @@ -7,7 +7,7 @@ The guide explains how to: 1. Verify the application 1. Build the application to execute on FPGA hardware -**Note**: It is highly recommended to review the [SDAccel Guide][SDAccel_Guide] to fully understand the SDAccel flow before using the GUI. +**Note**: It is highly recommended to review the [AWS F1 SDAccel Guide](SDAccel_Guide_AWS_F1.md) to fully understand the SDAccel flow before using the GUI. ## Cloning the aws-fpga Git repository The AWS Github repository contains the example used in this tutorial. diff --git a/SDAccel/docs/SDAccel_Guide_AWS_F1.md b/SDAccel/docs/SDAccel_Guide_AWS_F1.md index 98cffd633..66bf0a739 100644 --- a/SDAccel/docs/SDAccel_Guide_AWS_F1.md +++ b/SDAccel/docs/SDAccel_Guide_AWS_F1.md @@ -164,42 +164,19 @@ Conversely, code which is simply a few lines of basic operations, and has no tas # Additional Resources -The [AWS SDAccel README]. - -Xilinx web portal for [Xilinx SDAccel documentation] and for [Xilinx SDAccel GitHub repository] - - -Links pointing to **2017.4** version of the user guides -1. [UG1023: SDAccel Environment User Guide][UG1023 2017.4] -1. [UG1021: SDAccel Environment Tutorial: Getting Started Guide (including emulation/build/running on H/W flow)][UG1021 2017.4] -1. [UG1207: SDAccel Environment Optimization Guide][UG1207 2017.4] -1. [UG949: UltraFast Design Methodology Guide for the Vivado Design Suite][UG949 2017.4] -1. [UG1238: SDx Development Environment Release Notes, Installation, and Licensing Guide][UG1238 2017.4] - - - -[SDAccel_landing_page]: https://www.xilinx.com/products/design-tools/software-zone/sdaccel.html -[VHLS_landing_page]: https://www.xilinx.com/products/design-tools/vivado/integration/esl-design.html -[Vivado_landing_page]: https://www.xilinx.com/products/design-tools/vivado.html - -[SDAccel Environment User Guide]: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug1023-sdaccel-user-guide.pdf -[UG1021]: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug1021-sdaccel-intro-tutorial.pdf -[SDAccel Environment Optimization Guide]: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug1207-sdaccel-optimization-guide.pdf -[UG949]: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug949-vivado-design-methodology.pdf -[UG902]: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug902-vivado-high-level-synthesis.pdf - -[UG1023 2017.4]: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug1023-sdaccel-user-guide.pdf -[UG1021 2017.4]: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug1021-sdaccel-intro-tutorial.pdf -[UG1207 2017.4]: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug1207-sdaccel-optimization-guide.pdf -[UG1238 2017.4]:http://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug1238-sdx-rnil.pdf -[Xilinx SDAccel documentation]: https://www.xilinx.com/products/design-tools/software-zone/sdaccel.html#documentation -[Xilinx SDAccel GitHub repository]: https://github.com/Xilinx/SDAccel_Examples -[UG949 2017.4]: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug949-vivado-design-methodology.pdf - -[AWS SDAccel Readme]: ../README.md -[OnPremiseDev]: ./On_Premises_Development_Steps.md -[Power_Analysis]: ./SDAccel_Power_Analysis.md -[GUI_README]: ./README_GUI.md -[FAQ]:../FAQ.md +* The [AWS SDAccel README](../README.md). +* Xilinx web portal for [Xilinx SDAccel documentation](https://www.xilinx.com/products/design-tools/software-zone/sdaccel.html?resultsTablePreSelect=xlnxdocumenttypes:SeeAll#documentation) +* [Xilinx SDAccel GitHub repository](https://github.com/Xilinx/SDAccel_Examples) +* [Xilinx SDAccel landing page](https://www.xilinx.com/products/design-tools/software-zone/sdaccel.html) +* [Vivado HLS landing page](https://www.xilinx.com/products/design-tools/vivado/integration/esl-design.html) +* [Vivado landing page](https://www.xilinx.com/products/design-tools/vivado.html) +* [SDAccel Environment User Guide](https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug1023-sdaccel-user-guide.pdf) +* [SDAccel Intro Tutorial](https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug1021-sdaccel-intro-tutorial.pdf) +* [SDAccel Environment Optimization Guide](https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug1207-sdaccel-optimization-guide.pdf) +* [UltraFast Design Methodology Guide](https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug949-vivado-design-methodology.pdf) +* [Vivado High Level Synthesis User Guide](https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug902-vivado-high-level-synthesis.pdf) +* [On Premise Development steps](On_Premises_Development_Steps.md) +* [SDAccel Power Analysis](SDAccel_Power_Analysis.md) +* [FAQ](../FAQ.md) diff --git a/SDAccel/docs/SDAccel_HLS_Debug.md b/SDAccel/docs/SDAccel_HLS_Debug.md index dffbba149..6b0d49010 100755 --- a/SDAccel/docs/SDAccel_HLS_Debug.md +++ b/SDAccel/docs/SDAccel_HLS_Debug.md @@ -1,4 +1,4 @@ -# Debug HLS Performance: Limited memory ports. +# Debug HLS Performance: Limited memory ports In an ideal FPGA implementation, the kernel will process 1 data sample per clock cycle. In the High-Level Synthesis (HLS) technology used in SDAccel, this is referred to an II=1 implementation, where II is the Initiation Interval of design, or the number of clock cycles before the design can read new data inputs. diff --git a/SDAccel/docs/SDAccel_Migrate_dynamic_DSA.md b/SDAccel/docs/SDAccel_Migrate_dynamic_DSA.md index 7dac1ee44..b48b9afe8 100644 --- a/SDAccel/docs/SDAccel_Migrate_dynamic_DSA.md +++ b/SDAccel/docs/SDAccel_Migrate_dynamic_DSA.md @@ -47,7 +47,7 @@ set_property sdx_kernel_type rtl [ipx::current_core] * Profiling hardware no longer pre-built in the platform. Instead, it is added compile time to the design. * This requires an update to the xocc command options. * (2017.4) Add the -profile_kernel option the xocc command to enable profile instrumentation when compiling the kernel; set profile=true in the sdaccel.ini file to collect profile data when running the application. - + * (2019.1) Add the -profile_kernel option the xocc command to enable profile instrumentation when compiling the kernel; set profile=true in the xrt.ini file to collect profile data when running the application. ## Additional resources * [SDAccel Development Enviroment - Changes for 2017.4](https://www.xilinx.com/html_docs/xilinx2017_4/sdaccel_doc/jdl1512623841682.html) * [SDAccel Development Enviroment - Whats new for 2017.4](https://www.xilinx.com/html_docs/xilinx2017_4/sdaccel_doc/rke1512623904797.html) diff --git a/SDAccel/docs/Setup_AWS_CLI_and_S3_Bucket.md b/SDAccel/docs/Setup_AWS_CLI_and_S3_Bucket.md index 2b1bdeb4e..288e6527e 100644 --- a/SDAccel/docs/Setup_AWS_CLI_and_S3_Bucket.md +++ b/SDAccel/docs/Setup_AWS_CLI_and_S3_Bucket.md @@ -1,7 +1,7 @@ ## Setup CLI and Create S3 Bucket -The developer is required to create a S3 bucket for the AFI generation. The bucket will contain a tar file and logs which are generated from the AFI creation service. +The developer is required to create an S3 bucket for the AFI generation. The bucket will contain a tar file and logs which are generated from the AFI creation service. -To install the AWS CLI, please follow the instructions here: (http://docs.aws.amazon.com/cli/latest/userguide/installing.html). +To install the AWS CLI, please follow the [instructions here](http://docs.aws.amazon.com/cli/latest/userguide/installing.html). The AWS SDAccel scripts require JSON output format and the scripts will not work properly if you use any other output format types (ex: text, table). JSON is the default output format of the AWS CLI. diff --git a/SDAccel/docs/XRT_installation_instructions.md b/SDAccel/docs/XRT_installation_instructions.md index 00f1a5ab1..16bec5d51 100644 --- a/SDAccel/docs/XRT_installation_instructions.md +++ b/SDAccel/docs/XRT_installation_instructions.md @@ -1,123 +1,61 @@ -# XRT Installation Instructions - -# Installing Xilinx Runtime (XRT) 2018.3 RC3 Patch 2 - - * Applicable SDx Tool Version: 2018.3 - - * XRT Release Tag: 2018.3.3.2 (SHA: f96913247f94f4bc3b5134c92a0decc138351038) - - * [Xilinx Runtime (XRT) 2018.3 RC3 Patch 2 release](https://github.com/Xilinx/XRT/releases/tag/2018.3.3.2) - - ### Instructions to build & install XRT - - Pre-requisite commands used to build XRT for AWS F1 platform for this release - - ``` - git clone http://www.github.com/aws/aws-fpga.git - cd aws-fpga - source sdaccel_setup.sh - mkdir $SDACCEL_DIR/Runtime - cd $SDACCEL_DIR/Runtime - export XRT_PATH="${SDACCEL_DIR}/Runtime/XRT_2018.3.3.2" - git clone http://www.github.com/Xilinx/XRT.git -b 2018.3.3.2 ${XRT_PATH} - cd ${XRT_PATH} - sudo ./src/runtime_src/tools/scripts/xrtdeps.sh - cd build - - ``` - - Follow [Xilinx's instructions to build & install XRT on Centos/Redhat & Ubuntu/Debian](https://xilinx.github.io/XRT/master/html/build.html#xrt-for-pcie-platforms) to build XRT for a supported OS. - - ### Install on Centos/RHEL using prebuilt RPM - - ``` - - curl -s https://s3.amazonaws.com/aws-fpga-developer-ami/1.6.0/Patches/XRT_2018_3_RC3_Patch2/xrt_201830.2.1.0_7.6.1810-xrt.rpm -o xrt_201830.2.1.0_7.6.1810-xrt.rpm - curl -s https://s3.amazonaws.com/aws-fpga-developer-ami/1.6.0/Patches/XRT_2018_3_RC3_Patch2/xrt_201830.2.1.0_7.6.1810-aws.rpm -o xrt_201830.2.1.0_7.6.1810-aws.rpm - sudo yum remove -y xrt-aws - sudo yum remove -y xrt - sudo yum install -y xrt_201830.2.1.0_7.6.1810-xrt.rpm - sudo yum install -y xrt_201830.2.1.0_7.6.1810-aws.rpm - - ``` - -# Installing Xilinx Runtime (XRT) 2018.2_XDF.RC4 - - * Applicable SDx Tool Version: 2018.2 - - * XRT Release Tag: 2018.2_XDF.RC4 (SHA: 343186f76f59edd01bc48d84cf67fe22a0a3f338) - - * [Xilinx Runtime (XRT) 2018.2_XDF.RC4 release](https://github.com/Xilinx/XRT/tree/2018.2_XDF.RC4) - - ### Instructions to build & install XRT - - Pre-requisite commands used to build XRT for AWS F1 platform for this release - - ``` - git clone http://www.github.com/aws/aws-fpga.git - cd aws-fpga - source sdaccel_setup.sh - mkdir $SDACCEL_DIR/Runtime - cd $SDACCEL_DIR/Runtime - export XRT_PATH="${SDACCEL_DIR}/Runtime/XRT_20182rc4" - git clone http://www.github.com/Xilinx/XRT.git -b 2018.2_XDF.RC4 ${XRT_PATH} - cd ${XRT_PATH} - sudo ./src/runtime_src/tools/scripts/xrtdeps.sh - cd build - - ``` - Follow [ Xilinx's instructions to build & install XRT on Centos/RedHat & Ubuntu/Debian](https://www.xilinx.com/html_docs/xilinx2018_2_xdf/sdaccel_doc/ejy1538090924727.html) to build XRT for supported OS. - - ### Install on Centos/RedHat Linux using prebuilt RPMs - - Run following commands to download and install XRT 2018.2_XDF.RC4 for 'Centos/RHEL' - - ``` - curl -s https://s3.amazonaws.com/aws-fpga-developer-ami/1.5.0/Patches/xrt_201802.2.1.0_7.5.1804-xrt.rpm -o xrt_201802.2.1.0_7.5.1804-xrt.rpm - curl -s https://s3.amazonaws.com/aws-fpga-developer-ami/1.5.0/Patches/xrt_201802.2.1.0_7.5.1804-aws.rpm -o xrt_201802.2.1.0_7.5.1804-aws.rpm - sudo yum remove -y xrt - sudo yum install -y xrt_201802.2.1.0_7.5.1804-xrt.rpm - sudo yum install -y xrt_201802.2.1.0_7.5.1804-aws.rpm - - ``` - -# Installing Xilinx Runtime (XRT) 2018.2_XDF.RC5 - - * Applicable SDx Tool Version: 2018.2 - - * XRT Release Tag: 2018.2_XDF.RC5 (SHA: 65ffad62f427c0bd1bc65b6ea555a810295468b7) - - * [Xilinx Runtime (XRT) 2018.2_XDF.RC5 release](https://github.com/Xilinx/XRT/releases/tag/2018.2_XDF.RC5) - - ### Instructions to build & install XRT - - Pre-requisite commands used to build XRT for AWS F1 platform for this release - - ``` - git clone http://www.github.com/aws/aws-fpga.git - cd aws-fpga - source sdaccel_setup.sh - mkdir $SDACCEL_DIR/Runtime - cd $SDACCEL_DIR/Runtime - export XRT_PATH="${SDACCEL_DIR}/Runtime/XRT_20182rc5 " - git clone http://www.github.com/Xilinx/XRT.git -b 2018.2_XDF.RC5 ${XRT_PATH} - cd ${XRT_PATH} - sudo ./src/runtime_src/tools/scripts/xrtdeps.sh - cd build - - ``` - Follow [ Xilinx's instructions to build & install XRT on Centos/RedHat & Ubuntu/Debian](https://www.xilinx.com/html_docs/xilinx2018_2_xdf/sdaccel_doc/ejy1538090924727.html) to build XRT for supported OS. - - ### Install on Centos/RedHat Linux using prebuilt RPMs - - Run following commands to download and install XRT 2018.2_XDF.RC5 for 'Centos/RHEL' - - ``` - curl -s https://s3.amazonaws.com/aws-fpga-developer-ami/1.5.0/Patches/XRT_2018_2_XDF_RC5/xrt_201802.2.1.0_7.5.1804-xrt.rpm -o xrt_201802.2.1.0_7.5.1804-xrt.rpm - curl -s https://s3.amazonaws.com/aws-fpga-developer-ami/1.5.0/Patches/XRT_2018_2_XDF_RC5/xrt_201802.2.1.0_7.5.1804-aws.rpm -o xrt_201802.2.1.0_7.5.1804-aws.rpm - sudo yum remove -y xrt-aws - sudo yum remove -y xrt - sudo yum install -y xrt_201802.2.1.0_7.5.1804-xrt.rpm - sudo yum install -y xrt_201802.2.1.0_7.5.1804-aws.rpm - - ``` +# Xilinx Runtime (XRT) and SDx Tool versions + +* Xilinx Runtime versions match with the tool that you created your SDAccel AFI with. +* We provide pre-built RPM's for Centos/RHEL and instructions for building XRT +* Use the below table as reference to install and use the correct XRT version for your applications. + +| Xilinx SDx Tool Version | XRT Release Tag | SHA | `xrt` and `xrt-aws` pre-built RPM's (Centos/RHEL) | +|---|---|---|---| +|2019.1| [2019.1_RC2](https://github.com/Xilinx/XRT/releases/tag/2019.1_RC2) | dd210161e204e882027d22132725d8ffdf285149 | [xrt_201910.2.2.0_7.6.1810-xrt.rpm](https://aws-fpga-developer-ami.s3.amazonaws.com/1.7.0/Patches/XRT_2019_1_RC2/xrt_201910.2.2.0_7.6.1810-xrt.rpm) [xrt_201910.2.2.0_7.6.1810-aws.rpm](https://aws-fpga-developer-ami.s3.amazonaws.com/1.7.0/Patches/XRT_2019_1_RC2/xrt_201910.2.2.0_7.6.1810-aws.rpm) | +|2018.3| [2018.3_RC5](https://github.com/Xilinx/XRT/releases/tag/2018.3_RC5) | 8654da1f0d2bd196c9887bdcfe1479103a93e90a | [xrt_201830.2.1.0_7.6.1810-xrt.rpm](https://aws-fpga-developer-ami.s3.amazonaws.com/1.6.0/Patches/XRT_2018_3_RC5/xrt_201830.2.1.0_7.6.1810-xrt.rpm) [xrt_201830.2.1.0_7.6.1810-aws.rpm](https://aws-fpga-developer-ami.s3.amazonaws.com/1.6.0/Patches/XRT_2018_3_RC5/xrt_201830.2.1.0_7.6.1810-aws.rpm) | +|2018.2| [2018.2_XDF.RC5](https://github.com/Xilinx/XRT/releases/tag/2018.2_XDF.RC5) | 65ffad62f427c0bd1bc65b6ea555a810295468b7 | [xrt_201802.2.1.0_7.5.1804-xrt.rpm](https://aws-fpga-developer-ami.s3.amazonaws.com/1.5.0/Patches/XRT_2018_2_XDF_RC5/xrt_201802.2.1.0_7.5.1804-xrt.rpm) [xrt_201802.2.1.0_7.5.1804-aws.rpm](https://aws-fpga-developer-ami.s3.amazonaws.com/1.5.0/Patches/XRT_2018_2_XDF_RC5/xrt_201802.2.1.0_7.5.1804-aws.rpm) | +|2017.4| N/A** | N/A** | N/A** | +** Use XOCL for 2017.4 + +# Centos/RHEL build and install steps + +```bash +XRT_RELEASE_TAG=2019.1_RC2 # Substitute XRT_RELEASE_TAG= + +git clone https://github.com/aws/aws-fpga.git + +cd aws-fpga +source sdaccel_setup.sh +cd $SDACCEL_DIR/Runtime +export XRT_PATH="${SDACCEL_DIR}/Runtime/${XRT_RELEASE_TAG}" +git clone http://www.github.com/Xilinx/XRT.git -b ${XRT_RELEASE_TAG} ${XRT_PATH} + +cd ${XRT_PATH} +sudo ./src/runtime_src/tools/scripts/xrtdeps.sh + +cd build +scl enable devtoolset-6 bash +./build.sh + +cd Release +sudo yum reinstall xrt_*.rpm -y +``` + +# Centos/RHEL pre-built RPM install steps + +### 2019.1 + +```bash +curl -s https://aws-fpga-developer-ami.s3.amazonaws.com/1.7.0/Patches/XRT_2019_1_RC2/xrt_201910.2.2.0_7.6.1810-xrt.rpm -o xrt.rpm +curl -s https://aws-fpga-developer-ami.s3.amazonaws.com/1.7.0/Patches/XRT_2019_1_RC2/xrt_201910.2.2.0_7.6.1810-aws.rpm-o xrt-aws.rpm +sudo yum reinstall xrt*.rpm -y +``` +### 2018.3 + +```bash +curl -s https://aws-fpga-developer-ami.s3.amazonaws.com/1.6.0/Patches/XRT_2018_3_RC5/xrt_201830.2.1.0_7.6.1810-xrt.rpm -o xrt.rpm +curl -s https://aws-fpga-developer-ami.s3.amazonaws.com/1.6.0/Patches/XRT_2018_3_RC5/xrt_201830.2.1.0_7.6.1810-aws.rpm -o xrt-aws.rpm +sudo yum reinstall xrt*.rpm -y +``` +### 2018.2 + +```bash +curl -s https://aws-fpga-developer-ami.s3.amazonaws.com/1.5.0/Patches/XRT_2018_2_XDF_RC5/xrt_201802.2.1.0_7.5.1804-xrt.rpm -o xrt.rpm +curl -s https://aws-fpga-developer-ami.s3.amazonaws.com/1.5.0/Patches/XRT_2018_2_XDF_RC5/xrt_201802.2.1.0_7.5.1804-aws.rpm -o xrt-aws.rpm +sudo yum reinstall xrt*.rpm -y +``` \ No newline at end of file diff --git a/SDAccel/examples/3rd_party/vector_addition/vector_addition_main.cpp.diff b/SDAccel/examples/3rd_party/vector_addition/vector_addition_main.cpp.diff index 9d850916a..94075d891 100644 --- a/SDAccel/examples/3rd_party/vector_addition/vector_addition_main.cpp.diff +++ b/SDAccel/examples/3rd_party/vector_addition/vector_addition_main.cpp.diff @@ -1,22 +1,45 @@ ---- third_party/vector_add/host/src/main.cpp 2017-05-09 22:47:50.000000000 +0000 -+++ sdaccel/vector_add/host/src/main.cpp 2017-09-12 18:55:22.172000000 +0000 -@@ -70,0 +71,2 @@ +--- third_party/vector_add/host/src/main.cpp 2018-02-12 17:55:18.000000000 +0000 ++++ aws/vector_add/host/src/main.cpp 2019-09-15 22:53:15.593553611 +0000 +@@ -67,6 +67,7 @@ + #endif /* USE_SVM_API == 0 */ + scoped_array > ref_output; // num_devices elements + scoped_array n_per_device; // num_devices elements +std::string hwtype = "hw"; -+ -@@ -85,0 +88,3 @@ + + // Function prototypes + float rand_float(); +@@ -84,6 +85,9 @@ + N = options.get("n"); + } + + if(options.has("hw")) { + hwtype = options.get("hw"); + } -@@ -123 +128 @@ -- platform = findPlatform("Intel"); -+ platform = findPlatform("Xilinx"); -@@ -125 +130 @@ -- printf("ERROR: Unable to find Intel FPGA OpenCL platform.\n"); + // Initialize OpenCL. + if(!init_opencl()) { + return -1; +@@ -120,9 +124,9 @@ + } + + // Get the OpenCL platform. +- platform = findPlatform("Intel(R) FPGA SDK for OpenCL(TM)"); ++ platform = findPlatform("Xilinx); + if(platform == NULL) { +- printf("ERROR: Unable to find Intel(R) FPGA OpenCL platform.\n"); + printf("ERROR: Unable to find Xilinx FPGA OpenCL platform.\n"); -@@ -143,2 +148,4 @@ + return false; + } + +@@ -140,8 +144,10 @@ + + // Create the program for all device. Use the first device as the + // representative device (assuming all device are of the same type). - std::string binary_file = getBoardBinaryFile("vector_add", device[0]); - printf("Using AOCX: %s\n", binary_file.c_str()); + std::string fname = "xclbin/vector_add."+ hwtype + "." + VERSION_STR; + printf("Looking for %s.\n",fname.c_str()); + std::string binary_file = getBoardBinaryFile(fname.c_str(), device[0]); + printf("Using XCLBIN: %s\n", binary_file.c_str()); + program = createProgramFromBinary(context, binary_file.c_str(), device, num_devices); + + // Build the program that was just created. diff --git a/SDAccel/examples/aws/helloworld_ocl_runtime/2018.3/helloworld b/SDAccel/examples/aws/helloworld_ocl_runtime/2018.3_2019.1/helloworld similarity index 100% rename from SDAccel/examples/aws/helloworld_ocl_runtime/2018.3/helloworld rename to SDAccel/examples/aws/helloworld_ocl_runtime/2018.3_2019.1/helloworld diff --git a/SDAccel/examples/aws/helloworld_ocl_runtime/2018.3/helloworld_ocl_afi-ids.txt b/SDAccel/examples/aws/helloworld_ocl_runtime/2018.3_2019.1/helloworld_ocl_afi-ids.txt similarity index 100% rename from SDAccel/examples/aws/helloworld_ocl_runtime/2018.3/helloworld_ocl_afi-ids.txt rename to SDAccel/examples/aws/helloworld_ocl_runtime/2018.3_2019.1/helloworld_ocl_afi-ids.txt diff --git a/SDAccel/examples/aws/helloworld_ocl_runtime/2018.3/helloworld_ocl_agfi-ids.txt b/SDAccel/examples/aws/helloworld_ocl_runtime/2018.3_2019.1/helloworld_ocl_agfi-ids.txt similarity index 100% rename from SDAccel/examples/aws/helloworld_ocl_runtime/2018.3/helloworld_ocl_agfi-ids.txt rename to SDAccel/examples/aws/helloworld_ocl_runtime/2018.3_2019.1/helloworld_ocl_agfi-ids.txt diff --git a/SDAccel/examples/aws/helloworld_ocl_runtime/2018.3/sdaccel.ini b/SDAccel/examples/aws/helloworld_ocl_runtime/2018.3_2019.1/sdaccel.ini similarity index 100% rename from SDAccel/examples/aws/helloworld_ocl_runtime/2018.3/sdaccel.ini rename to SDAccel/examples/aws/helloworld_ocl_runtime/2018.3_2019.1/sdaccel.ini diff --git a/SDAccel/examples/aws/helloworld_ocl_runtime/2018.3/vector_addition.hw.xilinx_aws-vu9p-f1-04261818_dynamic_5_0.awsxclbin b/SDAccel/examples/aws/helloworld_ocl_runtime/2018.3_2019.1/vector_addition.hw.xilinx_aws-vu9p-f1-04261818_dynamic_5_0.awsxclbin similarity index 100% rename from SDAccel/examples/aws/helloworld_ocl_runtime/2018.3/vector_addition.hw.xilinx_aws-vu9p-f1-04261818_dynamic_5_0.awsxclbin rename to SDAccel/examples/aws/helloworld_ocl_runtime/2018.3_2019.1/vector_addition.hw.xilinx_aws-vu9p-f1-04261818_dynamic_5_0.awsxclbin diff --git a/SDAccel/examples/aws/helloworld_ocl_runtime/README.md b/SDAccel/examples/aws/helloworld_ocl_runtime/README.md index 1782662b2..a8c9ad2a8 100644 --- a/SDAccel/examples/aws/helloworld_ocl_runtime/README.md +++ b/SDAccel/examples/aws/helloworld_ocl_runtime/README.md @@ -31,23 +31,19 @@ vector_addition.hw.xilinx_aws-vu9p-f1-04261818_dynamic_5_0.awsxclbin --awsxclbin ## Execution - -#### :exclamation: PLEASE NOTE: xclbin & awsxclbin file formats have changed for SDx 2018.3. xclbin & awsxclbin files generated using earlier SDx versions are not compatible with 2018.3 based XRTs. If you are using a 2018.3 based XRT, please copy over awsxclbin & helloworld executable files provided in the 2018.3 subdirectory to this folder. - -Command sequence +#### :exclamation: PLEASE NOTE: xclbin & awsxclbin file formats have changed from SDx 2018.3 onwards. xclbin & awsxclbin files generated using earlier SDx versions are not compatible with 2018.3/2019.1 based XRTs. If you are using a 2018.3/2019.1 based XRT, please copy over awsxclbin & helloworld executable files provided in the 2018.3_2019.1 subdirectory to this folder. ``` sudo fpga-clear-local-image -S 0 - >>$sudo sh -sh-4.2# source $AWS_FPGA_REPO_DIR/sdaccel_runtime_setup.sh -sh-4.2# ./helloworld - +sudo -E /bin/bash +source $AWS_FPGA_REPO_DIR/sdaccel_runtime_setup.sh +./helloworld ``` ## Hello World Example Metadata -| Key | Region | Value for 2017.4 or 2018.2 | Value for 2018.3 | +| Key | Region | SDx 2017.4 or 2018.2 | SDx 2018.3 or 2019.1 | |--------|---------|-----------------------------|------------------| |afi id | us-east-1(N. Virginia) | afi-0532379b26ea13f26 | afi-0c8210915ce9bab5c | |afi id | us-west-2(oregon) | afi-0ab098d3fbfc43c7e | afi-01e237aa978aa74de | diff --git a/SDAccel/examples/xilinx_2019.1 b/SDAccel/examples/xilinx_2019.1 new file mode 160000 index 000000000..0ec1aef54 --- /dev/null +++ b/SDAccel/examples/xilinx_2019.1 @@ -0,0 +1 @@ +Subproject commit 0ec1aef54f3bf17c78581630d687b13fadae9616 diff --git a/SDAccel/kernel_version.txt b/SDAccel/kernel_version.txt index 2ecfd9222..79db7d8b9 100644 --- a/SDAccel/kernel_version.txt +++ b/SDAccel/kernel_version.txt @@ -2,3 +2,4 @@ 3.10.0-693.21.1.el7.x86_64 3.10.0-957.1.3.el7.x86_64 3.10.0-957.5.1.el7.x86_64 +3.10.0-957.27.2.el7.x86_64 \ No newline at end of file diff --git a/SDAccel/sdaccel_xrt_version.txt b/SDAccel/sdaccel_xrt_version.txt index cff9b8f59..89feedc24 100644 --- a/SDAccel/sdaccel_xrt_version.txt +++ b/SDAccel/sdaccel_xrt_version.txt @@ -1,5 +1,5 @@ 2018.2:343186f76f59edd01bc48d84cf67fe22a0a3f338 2018.2:65ffad62f427c0bd1bc65b6ea555a810295468b7 -2018.3:f96913247f94f4bc3b5134c92a0decc138351038 -2018.3:3636217b633930ed4815abd598324691ca25c2f3 -2018.3:48cafdc100b29843fd013d371ffba0141db06b7a \ No newline at end of file +2018.3:8654da1f0d2bd196c9887bdcfe1479103a93e90a +2019.1:e21b8a5b208618834760593bbb15063f7e399642 +2019.1:dd210161e204e882027d22132725d8ffdf285149 \ No newline at end of file diff --git a/SDAccel/tests/test_find_sdaccel_examples.py b/SDAccel/tests/test_find_sdaccel_examples.py index ce443cc95..4d9f1c94b 100644 --- a/SDAccel/tests/test_find_sdaccel_examples.py +++ b/SDAccel/tests/test_find_sdaccel_examples.py @@ -63,11 +63,34 @@ def test_find_example_makefiles(self, xilinxVersion): xilinx_sdaccel_example_map = {} for root, dirs, files in os.walk(self.xilinx_sdaccel_examples_dir): + ignore = False + if os.path.exists(root + "/description.json") and os.path.exists(root + "/Makefile"): + with open(root + "/description.json", "r") as description_file: + description = json.load(description_file) + + if "containers" in description: + if len(description["containers"]) > 1: + ignore = True + logger.info("Ignoring {} as >1 containers found in description.json.".format(root)) + + else: + ignore = True + logger.info("Ignoring {} as no containers found in description.json.".format(root)) + continue + + if "nboard" in description: + if "xilinx_aws-vu9p-f1-04261818" in description["nboard"]: + ignore = True + logger.info("Ignoring {} as F1 device found in nboard.".format(root)) + continue + else: + ignore = True + logger.warn("Ignoring: {} as no Makefile/description.json exist".format(root)) + + if not ignore: xilinx_examples_makefiles.append(root) logger.info("Adding: " + root) - else: - logger.info("Ignoring: " + root) assert len(xilinx_examples_makefiles) != 0, "Could not find any Xilinx SDAccel example in %s" % self.xilinx_sdaccel_examples_dir diff --git a/SDAccel/tests/test_run_sdaccel_example.py b/SDAccel/tests/test_run_sdaccel_example.py index 4bf1ecafe..201fb5c18 100644 --- a/SDAccel/tests/test_run_sdaccel_example.py +++ b/SDAccel/tests/test_run_sdaccel_example.py @@ -68,13 +68,14 @@ def setup_class(cls): return + @pytest.mark.flaky(reruns=2, reruns_delay=2) def test_run_sdaccel_example(self, examplePath, rteName, xilinxVersion): os.chdir(self.get_sdaccel_example_fullpath(examplePath)) (rc, stdout_lines, stderr_lines) = self.run_cmd("make exe") assert rc == 0 - em_run_cmd = self.get_sdaccel_example_run_cmd(examplePath) + em_run_cmd = self.get_sdaccel_example_run_cmd(examplePath, xilinxVersion) check_runtime_script = os.path.join(AwsFpgaTestBase.WORKSPACE,'sdaccel_runtime_setup.sh') self.get_sdaccel_aws_xclbin_file(examplePath, rteName, xilinxVersion) diff --git a/developer_resources/DCV.md b/developer_resources/DCV.md new file mode 100644 index 000000000..fe7498234 --- /dev/null +++ b/developer_resources/DCV.md @@ -0,0 +1,126 @@ +# GUI FPGA Development Environment with NICE DCV +This guide shows steps to setup a GUI FPGA Development Environment using the FPGA Developer AMI using NICE DCV + +## Overview + +[NICE DCV](https://docs.aws.amazon.com/dcv/latest/adminguide/what-is-dcv.html) can be used create a virtual desktop on your FPGA Developer AMI instance. + +[NICE DCV](https://docs.aws.amazon.com/dcv/latest/adminguide/what-is-dcv.html) is a high-performance remote +display protocol that provides customers with a secure way to deliver remote desktops and application streaming +from any cloud or data center to any device, over varying network conditions. + +With NICE DCV and Amazon EC2, customers can run graphics-intensive applications remotely on EC2 instances +and stream the results to simpler client machines, eliminating the need for expensive dedicated workstations. +Customers across a broad range of HPC workloads use NICE DCV for their remote visualization requirements. +The NICE DCV streaming protocol is also utilized by popular services like Amazon AppStream 2.0 and AWS RoboMaker. + +The [DCV Administrator guide](https://docs.aws.amazon.com/dcv/latest/adminguide/what-is-dcv.html) +and the [User guide](https://docs.aws.amazon.com/dcv/latest/userguide/getting-started.html) +are the official resources on how to configure and use DCV. + +The installation process is summarized below for your convenience. + +**NOTE**: +These steps may change when new versions of the DCV Server and Clients are released. +If you experience issues please refer to the [Official DCV documentation](https://docs.aws.amazon.com/dcv/latest/adminguide/what-is-dcv.html). + +## Installation Process + +1. [Setup your FPGA Developer AMI Instance with an IAM Role](https://docs.aws.amazon.com/dcv/latest/adminguide/setting-up-license.html#setting-up-license-ec2) that grants your instance access to NICE DCV endpoints. + + NICE DCV is available for free to use on EC2. + + The NICE DCV server automatically detects that it is running on an Amazon EC2 instance and periodically connects to an Amazon S3 bucket to determine whether a valid license is available. The IAM role enables this functionality. + + Please follow the steps mentioned in the above guide to attach an IAM role to your instance with the following policy: + ``` + { + "Version": "2012-10-17", + "Statement": [ + { + "Effect": "Allow", + "Action": "s3:GetObject", + "Resource": "arn:aws:s3:::dcv-license.region/*" + } + ] + } + ``` + **NOTE:** Without access to the DCV bucket mentioned in the [NICE DCV licensing setup guide](https://docs.aws.amazon.com/dcv/latest/adminguide/setting-up-license.html#setting-up-license-ec2), your server license is only valid of 15 days. + +1. On your FPGA Developer AMI Instance [update the Instance Security Group](https://docs.aws.amazon.com/AWSEC2/latest/UserGuide/using-network-security.html#adding-security-group-rule) to allow TCP Port **8443** Ingress + +1. [Install NICE DCV pre-requisites](https://docs.aws.amazon.com/dcv/latest/adminguide/setting-up-installing-linux-prereq.html) + + ``` + sudo yum -y groupinstall "GNOME Desktop" + sudo yum -y install glx-utils + ``` + +1. [Install NICE DCV Server](https://docs.aws.amazon.com/dcv/latest/adminguide/setting-up-installing-linux-server.html) + + ``` + sudo rpm --import https://s3-eu-west-1.amazonaws.com/nice-dcv-publish/NICE-GPG-KEY + wget https://d1uj6qtbmh3dt5.cloudfront.net/2019.0/Servers/nice-dcv-2019.0-7318-el7.tgz + tar xvf nice-dcv-2019.0-7318-el7.tgz + cd nice-dcv-2019.0-7318-el7 + sudo yum -y install nice-dcv-server-2019.0.7318-1.el7.x86_64.rpm + sudo yum -y install nice-xdcv-2019.0.224-1.el7.x86_64.rpm + + sudo systemctl enable dcvserver + sudo systemctl start dcvserver + ``` + +1. Setup Password + + ``` + sudo passwd centos + ``` + +1. Change firewall settings + + Options: + + * Disable firewalld to allow all connections + ``` + sudo systemctl stop firewalld + ``` + + * Open up the firewall only for tcp port 8443 + + ``` + sudo systemctl start firewalld + sudo firewall-cmd --zone=public --add-port=8443/tcp --permanent + sudo firewall-cmd --reload + ``` + +1. Create a virtual session to connect to + + **NOTE: that you will have to create a new session if you restart your instance.** + + ``` + dcv create-session --type virtual --user centos centos + ``` + +1. Connect to the DCV Remote Desktop session + + 1. **Using a web browser** + + * Make sure that you are using a [supported web browser](https://docs.aws.amazon.com/dcv/latest/adminguide/what-is-dcv.html#what-is-dcv-requirements). + + * Use the secure URL, Public IP address, and correct port (8443) to connect. For example: `https://111.222.333.444:8443` + + **NOTE:** When you connect make sure you use the `https` protocol to ensure a secure connection. + + 1. **Using the NICE DCV Client** + + * Download and install the [DCV Client](https://download.nice-dcv.com/) + + * Use the Public IP address, and correct port (8443) to connect + + An example login screen (for the DCV Client you will need to connect first using the IP:Port, for example `111.222.333.444:8443`): + + ![DCV Login](images/dcv_login.png) + +1. Logging in should show you your new GUI Desktop: + + ![DCV Desktop](images/dcv_desktop.png) \ No newline at end of file diff --git a/developer_resources/DCV_with_ParallelCluster.md b/developer_resources/DCV_with_ParallelCluster.md new file mode 100644 index 000000000..e51327198 --- /dev/null +++ b/developer_resources/DCV_with_ParallelCluster.md @@ -0,0 +1,457 @@ + + +# GUI FPGA Development Environment with NICE DCV and ParallelCluster + +Deploy a CloudFormation template to Launch an EC2 instance with the FPGA Developer AMI that has DCV Remote Desktop and ParallelCluster. + +## Table of Contents + + * [Overview](#overview) + * [Requirements](#requirements) + * [Architecture](#architecture) + * [Cost](#cost) + * [Duration](#duration) + * [Step-by-step Guide](#step-by-step-guide) + * [Subscribe to AWS FPGA Developer AMI](#subscribe-to-aws-fpga-developer-ami) + * [Launch with CloudFormation](#launch-with-cloudformation) + * [Connect to the DCV Remote Desktop session](#connect-to-the-dcv-remote-desktop-session) + * [Launch Vivado](#launch-vivado) + * [ParallelCluster Configuration](#pcluster-config) + * [Building a DCP On ParallelCluster Using SGE](#building-a-dcp-on-parallelcluster-using-sge) + * [Building a DCP On ParallelCluster Using Slurm](#building-a-dcp-on-parallelcluster-using-slurm) + * [Building a DCP On ParallelCluster Using Torque](#building-a-dcp-on-parallelcluster-using-torque) + * [FAQ](#faq) + * [References](#references) + + +## Overview + +This tutorial shows how to launch an EC2 instance using the FPGA Developer AMI that has +[NICE DCV](https://docs.aws.amazon.com/dcv/latest/adminguide/what-is-dcv.html) and +[AWS ParallelCluster](https://docs.aws.amazon.com/parallelcluster/latest/ug/what-is-aws-parallelcluster.html) +installed and configured to enable FPGA development in a GUI environment that is high performance +and cost effective. + +[NICE DCV](https://docs.aws.amazon.com/dcv/latest/adminguide/what-is-dcv.html) is a high-performance remote +display protocol that provides customers with a secure way to deliver remote desktops and application streaming +from any cloud or data center to any device, over varying network conditions. + +With NICE DCV and Amazon EC2, customers can run graphics-intensive applications remotely on EC2 instances +and stream the results to simpler client machines, eliminating the need for expensive dedicated workstations. +Customers across a broad range of HPC workloads use NICE DCV for their remote visualization requirements. +The NICE DCV streaming protocol is also utilized by popular services like Amazon AppStream 2.0 and AWS RoboMaker. + +[AWS ParallelCluster](https://docs.aws.amazon.com/parallelcluster/latest/ug/what-is-aws-parallelcluster.html) +provides a scalable compute environment for running compute or resource intensive jobs such as DCP generation or +F1 runtime applications. +ParallelCluster can help manage costs by automatically starting and terminating instances as needed by jobs. + + + +## Requirements +- You will need to subscribe to the [AWS FPGA Developer AMI on the AWS Marketplace](https://aws.amazon.com/marketplace/pp/B06VVYBLZZ) +- You will need a VPC that has access to the internet, either using a public subnet or NAT gateway. + - This is required to download all of the packages (for both DCV and OS packages) and to be able to connect to the instances. + - ParallelCluster instances can run in either private or public subnets that have access to the internet. + + +## Architecture + +![Architecture](images/vivado_dcv_diagram.png) + + +## Cost + +There is no additional charge to use NICE DCV or ParallelCluster on Amazon EC2. + +You only pay for the EC2 resources you use to run and store your workloads. + + +## Duration + +The following table shows the estimated time for the different steps in this tutorial. +The time it takes to complete each step will vary based on the instance types the instance types that use. + +| **Step** | **t3-2xlarge Duration** | **c5.4xlarge Duration** | **z1d.xlarge Duration** | **m5.2xlarge Duration** | **r5.xlarge Duration** | +|-------------------------------------------------------------|-------------------------|-------------------------|-------------------------|-------------------------|------------------------| +| [Subscribe to AWS FPGA Developer AMI](#subscribe) | 1 min | 1 min | 1 min | 1 min | 1 min | +| [Launch with CloudFormation](#launch) | 23 min | 18 min | 17 min | 18 min | 20 min | +| [Connect to the DCV Remote Desktop session](#connect) | 1 min | 1 min | 1 min | 1 min | 1 min | +| cl_hello_world DCP on Desktop | 91m40s | 75m44s | 77m9s | 83m42s | 83m20s | + +It will take ~20 minutes for CloudFormation to automatically create your GUI Desktop environment. + + +## Step-by-step Guide + + +### Subscribe to AWS FPGA Developer AMI + +Before you can launch the CloudFormation stack, you will need to subscribe to the AWS FPGA Developer AMI. +There is no charge to subscribe to the AWS FPGA Developer AMI; you will only be charged for the underlying resources. + +* Sign into your AWS account +* Go to the [AWS FPGA Developer AMI on the AWS Marketplace](https://aws.amazon.com/marketplace/pp/B06VVYBLZZ) +* Click on **Continue to Subscribe** button on upper right + +![Continue to Subscribe](images/Continue_to_Subscribe.png) + + +### Launch with CloudFormation + +The resources used in this workshop will be launched with AWS CloudFormation. For additional information about CloudFormation please visit +[AWS CloudFormation](https://aws.amazon.com/cloudformation/). + +IMPORTANT: Read through all steps below before *_clicking_* the *Launch on AWS* button. + +1. Click on the *Launch on AWS* button and follow the CloudFormation prompts to begin. + + Currently available in these regions. + + TIP *_Context-click (right-click)_* the *Launch on AWS* button and open the link in a new tab or +window to make it easy to navigate between this guide and the AWS Console. + + | *Region* | *Launch template* | + |----------|-------------------| + | *N. Virginia* (us-east-1) | | + | *Ohio* (us-east-21) | | + | *N. California* (us-west-1) | | + | *Oregon* (us-west-2) | | + | *Ireland* (eu-west-1) | | + | *Sydney* (ap-southeast-2) | | + | *Hong Kong\** (ap-east-1) | | + + \**May require additional request for access* +1. Accept the defaults on the *Prerequisite - Prepare template* page and *_click_* *Next*. +1. You should see the *Stack Details* page: + ![Stack Details](images/stack_details.png) +1. *_Enter_* values for parameters. + + | *Parameter* | *Variable Name* | *Description* + |-------------|-----------------|--------------| + | *VPC ID* | VPCId | VPC ID for where the remote desktop instance should be launched. + | *VPC CIDR Block* | VPCCidrBlock | We use this to create a security group that allows NFS access to and from the remote desktop instance. Pick the CIDR from the VPC ID Parameter above(For eg: `vpc-123abc(10.0.0.0/16)`). + | *FPGA Developer AMI Version* | FpgaDevAmiVersion | Select the FPGA Developer AMI Version you want to launch your instances with. Picks the latest version by default. + | *User name for DCV login* | UserName | User name for DCV remote desktop login, default is *_simuser_* + | *Password for DCV login* | UserPass | Password for DCV remote desktop login. + | *Subnet ID* | Subnet | Select a Subnet ID in the Availability Zone where you want the instance launched. Pick a subnet from the VPC selected above. + | *EC2 Key Name* | EC2KeyName | Name of an existing EC2 KeyPair to enable SSH access to the instance. + | *Remote Desktop Instance Type* | remoteDesktopInstanceType | Select an instance type for your remote desktop. + | *CIDR block for remote access (ports 22 and 8443)* | AccessCidr | Put the IP ranges from where you allow remote access to your remote desktop. This opens up ports 22 and 8443 for the CIDR range. We recommend setting it to the output of [Check My IP](http://checkip.amazonaws.com/). For eg: `12.34.56.78/32` so that only you can access the instance. + | *Project Data Size* | ProjectDataSize | Enter the size in GB for your project_data EBS volume. You can always [increase your volume size later](https://docs.aws.amazon.com/AWSEC2/latest/UserGuide/requesting-ebs-volume-modifications.html). Default is 5GB. + | _OPTIONAL_: *Existing Security Group (e.g. sg-abcd1234efgh)* | ExistingSecurityGroup | *OPTIONAL:* Needs to be a SG ID, for example sg-abcd1234efgh. This is an [already existing Security Group ID that is in the same VPC](https://console.aws.amazon.com/vpc/home?#SecurityGroups), this is an addition to the security groups that are automatically created to enable access to the remote desktop, leave as NO_VALUE if you choose not use this. + | _OPTIONAL_: *Static Private IP Address* | StaticPrivateIpAddress | *OPTIONAL:* If you already have a private VPC address range, you can specify the private IP address to use, leave as *NO_VALUE* if you choose not use this + | *Assign a Public IP address* | UsePublicIp | Should a public IP address be given to the instance, this is overridden by `*CreateElasticIP = True*` + | *Create an Elastic IP address* | CreateElasticIP | Should an Elastic IP address be created and assigned, this allows for persistent IP address assignment + | _OPTIONAL_: *S3 bucket for read access* | S3BucketName | *OPTIONAL:* S3 bucket to allow this instance read access (List and Get), leave as *NO_VALUE* if you choose not use this + | _OPTIONAL_: *ParallelCluster Scheduler* | Scheduler | *OPTIONAL:* Select a scheduler to setup with ParallelCluster. Only necessary if you want to deploy a compute cluster. + | _OPTIONAL_: *ParallelCluster Subnet ID* | PclusterSubnet | *OPTIONAL:* Select a Subnet ID in the Availability Zone where you want the cluster instances launched. Pick a subnet from the VPC selected above. + | _OPTIONAL_: *Scheduler instance type* | MasterInstanceType | *OPTIONAL:* Select an instance type you want the scheduler master to run on. This can be a small/free tier instance. + | _OPTIONAL_: *DCP Build instance type* | DcpInstanceType | *OPTIONAL:* Select an instance type for building DCP's. z1d.xlarge, c5.4xlarge, m5.2xlarge, r5.xlarge, t3.2xlarge, t2.2xlarge are recommended. + | _OPTIONAL_: *F1 instance type* | F1InstanceType | *OPTIONAL:* Select a runtime instance type for your Runtime queue. + +1. After you have entered values for the parameters, *_click_* *Next*. + +1. *_Accept_* the default values of the *Configure stack options* and *Advanced options* sections and *_click_* *Next*. + +1. *_Review_* the CloudFormation stack settings. + +1. *_Click_* all checkboxes in the blue *Capabilities* box at the bottom of the page. + ![Capabilities](images/capabilities_checkbox.png) + +1. *_Click_* *Create stack*. + + This will start the deployment process. + AWS CloudFormation will create all of the resources specified in the template and set them up. + +1. Verify stack was created successfully + + In the *Events* tab, you should see `*CREATE_COMPLETE*` for the `AWS::CloudFormation::Stack` event Type. + In the *Stack Info* tab, you should see `*CREATE_COMPLETE*` in the Status field. + It will take ~20 minutes for the stack creation to complete. This is due to the large number of packages that need to be installed. Upon completion you should see the connection information (IP address) in the *Outputs* section of the stack. + + +### Connect to the DCV Remote Desktop session + +You can either use your web browser to connect to the DCV Remote Desktop session or you can use the DCV Client. + +1. **Using a web browser** + i. Make sure that you are using a [supported web browser](https://docs.aws.amazon.com/dcv/latest/adminguide/what-is-dcv.html#what-is-dcv-requirements). + i. Use the secure URL, Public IP address, and correct port (8443) to connect + + When you connect make sure you use the https protocol, to ensure you are using a connecting connection. + + For example: `https://111.222.333.444:8443` + +1. **Use the NICE DCV Client** + + * Download and install the [DCV Client](https://download.nice-dcv.com/) + + * Use the Public IP address, and correct port (8443) to connect + + For example: `111.222.333.444:8443` + + An example login screen (for the DCV Client you will need to connect first using the IP:Port, for example 111.222.333.444:8443): + + ![DCV Login](images/dcv_login.png) + + * After you login with the credentials you specified when creating the stack, you will see the Desktop: + + ![DCV Desktop](images/dcv_desktop.png) + + + +### Launch Vivado + +Now that your remote desktop is setup, you can launch the Vivado Design Suite (included in the AWS FPGA Developer AMI). + + i. Start a terminal session, go to *_Applications -> Favorites -> Terminal_*. + + i. Type `vivado` at the command prompt and hit enter: + + ![Vivado Launch](images/vivado_launch.png) + + Vivado will launch in a GUI session: + + ![Vivado Startup](images/vivado_startup.png) + + + +### ParallelCluster Configuration + +The template creates a ParallelCluster configuration and an AMI for the cluster instances. +If you selected a scheduler, then it will also create two ParallelCluster clusters. +If you didn't select a scheduler in the template you can still manually start a cluster. + +The configuration file for ParallelCluster is found in `~/.parallelcluster/config` and the +configuration parameters are documented [here](https://docs.aws.amazon.com/parallelcluster/latest/ug/configuration.html). +It supports the following schedulers: +* sge +* slurm +* torque + +The template creates a custom ParallelCluster AMI based on the FPGA Developer AMI so that they have +the Xilinx tools installed. +They also mount `~/src/project_data` from your DCV instance so that your project data is accessible +on the ParallelCluster compute nodes. + +If you selected a scheduler then the template will create two ParallelCluster clusters, where +${Scheduler} is the scheduler you selected when you launched the template. + +* The fpgadev-${Scheduler} cluster is for running compute intense jobs such as DCP generation. +* The fpgarun-${Scheduler} cluster is for testing your AFI on F1 instances. + +If you didn't select a scheduler then you can start the clusters manually using the following commands +replacing ${Scheduler} with the scheduler you want to use. + +``` +pcluster create -t fpgadev-${Scheduler} fpgadev-${Scheduler} +pcluster create -t fpgarun-${Scheduler} fpgarun-${Scheduler} +``` + +All the clusters are configured to terminate the compute nodes if they are idle for more than one minute. +When jobs are queued the cluster will automatically launch enough compute nodes to run the jobs. +The configuration file limits the max number of compute nodes in the cluster to two nodes. +You can modify the `max_queue_size` parameter in the configuration file if you need to increase that limit. + +You can check the status of the clusters using the `pcluster list` command. + +``` +$ pcluster list +fpgadev-sge CREATE_IN_PROGRESS 2.4.1 +fpgarun-sge CREATE_IN_PROGRESS 2.4.1 +``` + +If no clusters are listed then it is possible that the custom AMI isn't complete. +You can check the status of the custom AMI generation by looking in the log file +at `~/.parallelcluster/create-ami.log`. + +Wait until the cluster status is *CREATE_COMPLETE*. + +``` +$ pcluster list +fpgadev-sge CREATE_COMPLETE 2.4.1 +fpgarun-sge CREATE_COMPLETE 2.4.1 +``` + +You can get information about the cluster by running the `pcluster status` command. + +``` +$ pcluster status fpgadev-sge +Status: CREATE_COMPLETE +MasterServer: RUNNING +MasterPublicIP: 3.95.42.219 +ClusterUser: centos +MasterPrivateIP: 172.31.15.131 +``` + +**NOTE:** All of the scheduler commands have to be executed on the scheduler's master instance. +You will use ssh to connect to the instance. + +The CloudFormation template created an EC2 KeyPair, saved the private key at `~/pcluster.pem`, and added it to your ssh agent. +ParallelCluster is configured to use this key. +You can connect to the master using the following command. + +``` +pcluster ssh fpgadev-sge +``` + +Any additional arguments are passed to the ssh command. +This allows you to run commands on the master from your desktop. +For example you can check that your project data is mounted +in the cluster. + +``` +$ pcluster ssh fpgadev-sge ls ~/src/project_data +aws-fpga +build_cl_hello_world.sh +``` + +Note that the master in this tutorial is configured as a t3.micro instance so it lacks the +compute resources required for running jobs. +It's role is to manage jobs running in the cluster. + +The following sections show how to run a the cl_hello_world example's DCP generation job +on ParallelCluster using the different schedulers. +The script to do the DCP generation is at `~/src/project_data/build_cl_hello_world.sh`. + + + +### Building a DCP On ParallelCluster Using SGE + +Use the `qsub` command to submit the job on an SGE cluster. + +``` +$ pcluster ssh fpgadev-sge qsub ~/src/project_data/build_cl_hello_world.sh +Unable to run job: warning: ${UserName}'s job is not allowed to run in any queue +Your job 1 ("build_cl_hello_world.sh") has been submitted +Exiting. +``` + +The warning is because a compute node isn't available to run the job. +You can verify that the job was actually submitted using the `qstat` command. + +``` +$ qstat +job-ID prior name user state submit/start at queue slots ja-task-ID +----------------------------------------------------------------------------------------------------------------- + 1 0.55500 build_cl_h ${UserName} qw 09/17/2019 18:06:38 1 +``` + +ParallelCluster will detect that the job is queued and start a new compute node to run it. +You can verify this by going to the EC2 console. + +When the compute node starts, the job will transition to running state. + +``` +$ pcluster ssh fpgadev-sge qstat +job-ID prior name user state submit/start at queue slots ja-task-ID +----------------------------------------------------------------------------------------------------------------- + 1 0.55500 build_cl_h ${UserName} r 09/17/2019 18:38:15 all.q@ip-172-31-12-135.ec2.int 1 +``` + +The output of the job is written to your home directory on the master. + +``` +$ pcluster ssh fpgadev-sge ls +build_cl_hello_world.sh.e1 +build_cl_hello_world.sh.o1 +src +``` + + + +### Building a DCP On ParallelCluster Using Slurm + +The process for using Slurm is similar, except the scheduler commands are different. +Use the `sbatch` command to submit a job. + +``` +$ pcluster ssh fpgadev-slurm sbatch src/project_data/build_cl_hello_world.sh +Submitted batch job 1 +``` + +Use the `squeue` command to check the status. + +``` +$ pcluster ssh fpgadev-slurm squeue + JOBID PARTITION NAME USER ST TIME NODES NODELIST(REASON) + 1 compute build_cl cartalla R 0:06 1 ip-172-31-13-182 +``` + + + +### Building a DCP On ParallelCluster Using Torque + +The process for using Torque is the same as sge except the output is different. +Use the `qsub` command to submit a job. + +``` +$ pcluster ssh fpgadev-torque qsub src/project_data/build_cl_hello_world.sh +1.ip-172-31-5-142.ec2.internal +``` + +Use the `qstat` command to check the status. + +``` +$ pcluster ssh fpgadev-torque qstat +Job ID Name User Time Use S Queue +------------------------- ---------------- --------------- -------- - ----- +1.ip-172-31-5-142.ec2.interna ...ello_world.sh cartalla 0 Q batch +``` + + + +## FAQ + +* How do I find out if my template deployment completed? + + * In the *Events* tab, you should see `*CREATE_COMPLETE*` for the `AWS::CloudFormation::Stack` event Type. + * In the *Stack Info* tab, you should see `*CREATE_COMPLETE*` in the Status field. + +* How do I update to a new template? + + You can update your deployed stack by going to the [CloudFormation console](https://console.aws.amazon.com/cloudformation) -> Stacks -> Your Stack and selecting the `Update` button at the top. + + You have three ways of updating: + + 1. Use current template + + This option lets you update parameters in the currently deployed stack. + Click next after selecting this option to see the parameters, change them and go through the deployment steps as before. + + 1. Replace current template + + This option lets you select an updated template. + + If you want to update your stack with a new template that we have released, select this option and point to our template URL: + `https://aws-fpga-hdk-resources.s3.amazonaws.com/developer_resources/cfn_templates/dcv_with_pcluster.yaml` + + This will let you get any fixes and updates that we publish to the template. + + 1. Modify the template in the CloudFormation Designer + + This option lets you graphically edit the template and add parts depending on your need. + Check the [Official CloudFormation Designer documentation](https://docs.aws.amazon.com/AWSCloudFormation/latest/UserGuide/working-with-templates-cfn-designer.html) for more details on how to get started! + +* How do I terminate my instance? + + To clean up resources created by a CloudFormation stack, we strongly suggest deleting the stack instead of deleting resources individually. + + CloudFormation will handle the instance termination for you. + + To delete a stack, please follow the [CloudFormation User Guide](https://docs.aws.amazon.com/AWSCloudFormation/latest/UserGuide/cfn-console-delete-stack.html) + +* How do I troubleshoot CloudFormation stack deployment issues? + + To start off, please check the [CloudFormation Troubleshooting Guide](https://docs.aws.amazon.com/AWSCloudFormation/latest/UserGuide/troubleshooting.html) + + Next, post a question on the [FPGA Development forum](https://forums.aws.amazon.com/forum.jspa?forumID=243&start=0) **OR** file a support ticket from the [Support Center](https://console.aws.amazon.com/support) and someone should be able to help you out! + + + +## References + +- [NICE DCV](https://docs.aws.amazon.com/dcv/latest/adminguide/what-is-dcv.html) +- [Xilinx Vivado Design Suite](https://www.xilinx.com/products/design-tools/vivado.html) +- [AWS ParallelCluster](https://docs.aws.amazon.com/parallelcluster/latest/ug/what-is-aws-parallelcluster.html) diff --git a/developer_resources/README.md b/developer_resources/README.md new file mode 100644 index 000000000..91f1165ee --- /dev/null +++ b/developer_resources/README.md @@ -0,0 +1,15 @@ +# Developer Resources + +We provide the [FPGA Developer AMI](https://aws.amazon.com/marketplace/pp/B06VVYBLZZ) with Xilinx tools pre-installed and setup for development right away. + +However, setting up an instance for development might require a few extra steps like +* Setting up a GUI Desktop. +* Setting up a Runtime instance. +* Setting up a development environment that includes an elastic compute cluster. + +This document guides developers to setting up their development environment for development, +building/running/debugging designs and managing costs while doing so. + +We have provided the following two ways of setting up your development environment: +* [Guide for creating a GUI Desktop for FPGA Development using NICE DCV and the FPGA Developer AMI](DCV.md) +* [Automated Deployment of a GUI Desktop and HPC cluster for FPGA Development based on NICE DCV and AWS ParallelCluster](DCV_with_ParallelCluster.md) \ No newline at end of file diff --git a/developer_resources/images/Continue_to_Subscribe.png b/developer_resources/images/Continue_to_Subscribe.png new file mode 100644 index 000000000..dd13b1480 Binary files /dev/null and b/developer_resources/images/Continue_to_Subscribe.png differ diff --git a/developer_resources/images/Launch_on_AWS.png b/developer_resources/images/Launch_on_AWS.png new file mode 100644 index 000000000..89fc87e09 Binary files /dev/null and b/developer_resources/images/Launch_on_AWS.png differ diff --git a/developer_resources/images/capabilities_checkbox.png b/developer_resources/images/capabilities_checkbox.png new file mode 100644 index 000000000..bb536a1fb Binary files /dev/null and b/developer_resources/images/capabilities_checkbox.png differ diff --git a/developer_resources/images/dcv_desktop.png b/developer_resources/images/dcv_desktop.png new file mode 100644 index 000000000..3c62f20b1 Binary files /dev/null and b/developer_resources/images/dcv_desktop.png differ diff --git a/developer_resources/images/dcv_login.png b/developer_resources/images/dcv_login.png new file mode 100644 index 000000000..9ca3208fe Binary files /dev/null and b/developer_resources/images/dcv_login.png differ diff --git a/developer_resources/images/stack_details.png b/developer_resources/images/stack_details.png new file mode 100644 index 000000000..cb6f94d8d Binary files /dev/null and b/developer_resources/images/stack_details.png differ diff --git a/developer_resources/images/vivado_dcv_diagram.png b/developer_resources/images/vivado_dcv_diagram.png new file mode 100644 index 000000000..e29b28e2a Binary files /dev/null and b/developer_resources/images/vivado_dcv_diagram.png differ diff --git a/developer_resources/images/vivado_launch.png b/developer_resources/images/vivado_launch.png new file mode 100644 index 000000000..43166db2d Binary files /dev/null and b/developer_resources/images/vivado_launch.png differ diff --git a/developer_resources/images/vivado_startup.png b/developer_resources/images/vivado_startup.png new file mode 100644 index 000000000..848bd6879 Binary files /dev/null and b/developer_resources/images/vivado_startup.png differ diff --git a/hdk/README.md b/hdk/README.md index bd6a96863..48238144b 100644 --- a/hdk/README.md +++ b/hdk/README.md @@ -53,18 +53,19 @@ #### AWS Account, F1/EC2 Instances, On-Premises, AWS IAM Permissions, AWS CLI and S3 Setup (One-time Setup) * [Setup an AWS Account](https://aws.amazon.com/free/) * Launch an instance using the [FPGA Developer AMI](https://aws.amazon.com/marketplace/pp/B06VVYBLZZ) which comes pre-installed with Vivado and required licenses. Given the large size of the FPGA used inside the AWS FPGA instances, the implementation tools require 32GiB Memory (ex: c4.4xlarge, m4.2xlarge, r4.xlarge, t2.2xlarge). c4.4xlarge and c4.8xlarge would provide the fastest execution time with 30 and 60GiB of memory respectively. Developers who want to save on cost, would start coding and run simulations on low-cost instances, like t2.2xlarge, and move to the aforementioned larger instances to run the synthesis of their acceleration code. Follow the [On-Premises Instructions](docs/on_premise_licensing_help.md) to purchase and install a license from Xilinx. - * This release supports Xilinx SDx 2017.4 only. The compatibility table describes the mapping of developer kit version to [FPGA developer AMI](https://aws.amazon.com/marketplace/pp/B06VVYBLZZ) version: +* The compatibility table describes the mapping of developer kit version to [FPGA Developer AMI](https://aws.amazon.com/marketplace/pp/B06VVYBLZZ) version: -| Developer Kit Version | Tool Version Supported | Compatible FPGA developer AMI Version | +| Developer Kit Version | Tool Version Supported | Compatible FPGA Developer AMI Version | |-----------|-----------|------| | 1.3.0-1.3.6 | 2017.1(Deprecated) | v1.3.5(Deprecated) | | 1.3.7-1.3.X | 2017.1(Deprecated) | v1.3.5-v1.3.X(Deprecated) | | 1.3.7-1.3.X | 2017.4 | v1.4.0-v1.4.X (Xilinx SDx 2017.4) | -| 1.4.0-1.4.X | 2017.4 | v1.4.0-v1.4.X (Xilinx SDx 2017.4) | -| 1.4.3-1.4.X | 2018.2 | v1.5.0 (Xilinx SDx 2018.2) | -| 1.4.8-1.4.X | 2018.3 | v1.6.0 (Xilinx SDx 2018.3) | +| 1.4.0-1.4.2 | 2017.4 | v1.4.0-v1.4.X (Xilinx SDx 2017.4) | +| 1.4.3-1.4.7 | 2018.2 | v1.5.0 (Xilinx SDx 2018.2) | +| 1.4.8-1.4.10 | 2018.3 | v1.6.0 (Xilinx SDx 2018.3) | +| 1.4.11-1.4.X | 2019.1 | v1.7.0 (Xilinx SDx 2019.1) | -* FPGA developer kit version is listed in [hdk_version.txt](./hdk_version.txt) +* The FPGA Developer Kit version is listed in [hdk_version.txt](./hdk_version.txt) * FPGA developer kit supported tool versions are listed in [supported\_vivado\_versions](../supported_vivado_versions.txt) diff --git a/hdk/cl/examples/cl_dram_dma/verif/scripts/Makefile.ies b/hdk/cl/examples/cl_dram_dma/verif/scripts/Makefile.ies index 59da02e64..65df9e036 100644 --- a/hdk/cl/examples/cl_dram_dma/verif/scripts/Makefile.ies +++ b/hdk/cl/examples/cl_dram_dma/verif/scripts/Makefile.ies @@ -39,5 +39,5 @@ endif $(COMPLIB_DIR): cd $(SIM_ROOT) && echo "compile_simlib -language all -dir $(COMPLIB_DIR) -simulator $(SIMULATOR) -library all -family all" > create_libs.tcl - cd $(SIM_ROOT) && vivado -mode batch -source create_libs.tcl + -cd $(SIM_ROOT) && vivado -mode batch -source create_libs.tcl cd $(SIM_ROOT) && rm -rf create_libs.tcl diff --git a/hdk/cl/examples/cl_dram_dma/verif/scripts/Makefile.questa b/hdk/cl/examples/cl_dram_dma/verif/scripts/Makefile.questa index f8c9d3915..808b23c27 100644 --- a/hdk/cl/examples/cl_dram_dma/verif/scripts/Makefile.questa +++ b/hdk/cl/examples/cl_dram_dma/verif/scripts/Makefile.questa @@ -41,6 +41,12 @@ ifeq ($(TEST),test_null) else cd $(SIM_DIR) && vsim -c -voptargs="+acc" -64 -t ps -sv_seed random -L $(COMPLIB_DIR)/unisims_ver -L $(COMPLIB_DIR)/unisim -L $(COMPLIB_DIR)/unifast_ver -L $(COMPLIB_DIR)/unifast -L $(COMPLIB_DIR)/unimacro_ver -L $(COMPLIB_DIR)/unimacro -L $(COMPLIB_DIR)/secureip -L $(COMPLIB_DIR)/axi_register_slice_v2_1_18 -L $(COMPLIB_DIR)/axi_infrastructure_v1_1_0 -L $(COMPLIB_DIR)/axi_crossbar_v2_1_19 -L $(COMPLIB_DIR)/xpm -L $(COMPLIB_DIR)/axi_clock_converter_v2_1_17 -L $(COMPLIB_DIR)/fifo_generator_v13_2_3 -L $(COMPLIB_DIR)/fifo_generator_v13_1_4 -L $(COMPLIB_DIR)/axi_data_fifo_v2_1_17 -L $(COMPLIB_DIR)/generic_baseblocks_v2_1_0 $(PLUSARGS) -l $(TEST).log -do "run -all; quit -f" tb glbl $(TEST) endif +else ifeq ($(VIVADO_TOOL_VERSION), v2019.1) +ifeq ($(TEST),test_null) + cd $(SIM_DIR) && vsim -c -voptargs="+acc" -64 -t ps -sv_seed random -L $(COMPLIB_DIR)/unisims_ver -L $(COMPLIB_DIR)/unisim -L $(COMPLIB_DIR)/unifast_ver -L $(COMPLIB_DIR)/unifast -L $(COMPLIB_DIR)/unimacro_ver -L $(COMPLIB_DIR)/unimacro -L $(COMPLIB_DIR)/secureip -L $(COMPLIB_DIR)/axi_register_slice_v2_1_19 -L $(COMPLIB_DIR)/axi_infrastructure_v1_1_0 -L $(COMPLIB_DIR)/axi_crossbar_v2_1_20 -L $(COMPLIB_DIR)/xpm -L $(COMPLIB_DIR)/axi_clock_converter_v2_1_18 -L $(COMPLIB_DIR)/fifo_generator_v13_2_4 -L $(COMPLIB_DIR)/fifo_generator_v13_1_4 -L $(COMPLIB_DIR)/axi_data_fifo_v2_1_18 -L $(COMPLIB_DIR)/generic_baseblocks_v2_1_0 $(PLUSARGS) -l $(C_TEST).log -do "run -all; quit -f" tb glbl $(TEST) +else + cd $(SIM_DIR) && vsim -c -voptargs="+acc" -64 -t ps -sv_seed random -L $(COMPLIB_DIR)/unisims_ver -L $(COMPLIB_DIR)/unisim -L $(COMPLIB_DIR)/unifast_ver -L $(COMPLIB_DIR)/unifast -L $(COMPLIB_DIR)/unimacro_ver -L $(COMPLIB_DIR)/unimacro -L $(COMPLIB_DIR)/secureip -L $(COMPLIB_DIR)/axi_register_slice_v2_1_19 -L $(COMPLIB_DIR)/axi_infrastructure_v1_1_0 -L $(COMPLIB_DIR)/axi_crossbar_v2_1_20 -L $(COMPLIB_DIR)/xpm -L $(COMPLIB_DIR)/axi_clock_converter_v2_1_18 -L $(COMPLIB_DIR)/fifo_generator_v13_2_4 -L $(COMPLIB_DIR)/fifo_generator_v13_1_4 -L $(COMPLIB_DIR)/axi_data_fifo_v2_1_18 -L $(COMPLIB_DIR)/generic_baseblocks_v2_1_0 $(PLUSARGS) -l $(TEST).log -do "run -all; quit -f" tb glbl $(TEST) +endif else ifeq ($(TEST),test_null) cd $(SIM_DIR) && vsim -c -voptargs="+acc" -64 -t ps -sv_seed random -L $(COMPLIB_DIR)/unisims_ver -L $(COMPLIB_DIR)/unisim -L $(COMPLIB_DIR)/unifast_ver -L $(COMPLIB_DIR)/unifast -L $(COMPLIB_DIR)/unimacro_ver -L $(COMPLIB_DIR)/unimacro -L $(COMPLIB_DIR)/secureip -L $(COMPLIB_DIR)/axi_register_slice_v2_1_17 -L $(COMPLIB_DIR)/axi_infrastructure_v1_1_0 -L $(COMPLIB_DIR)/axi_crossbar_v2_1_18 -L $(COMPLIB_DIR)/xpm -L $(COMPLIB_DIR)/axi_clock_converter_v2_1_16 -L $(COMPLIB_DIR)/fifo_generator_v13_2_2 -L $(COMPLIB_DIR)/fifo_generator_v13_1_4 -L $(COMPLIB_DIR)/axi_data_fifo_v2_1_16 -L $(COMPLIB_DIR)/generic_baseblocks_v2_1_0 $(PLUSARGS) -l $(C_TEST).log -do "run -all; quit -f" tb glbl $(TEST) diff --git a/hdk/cl/examples/cl_dram_dma/verif/scripts/Makefile.vcs b/hdk/cl/examples/cl_dram_dma/verif/scripts/Makefile.vcs index 3321775ce..61cb8232f 100644 --- a/hdk/cl/examples/cl_dram_dma/verif/scripts/Makefile.vcs +++ b/hdk/cl/examples/cl_dram_dma/verif/scripts/Makefile.vcs @@ -27,7 +27,7 @@ compile: $(COMPLIB_DIR) mkdir -p $(SIM_DIR) cd ${SIM_DIR} && ln -s -f ../vcs_complib/synopsys_sim.setup cd $(SIM_DIR) && vlogan -g -ntb_opts tb_timescale=1ps/1ps -timescale=1ps/1ps -sverilog +systemverilogext+.sv +libext+.sv +libext+.v -full64 -lca -v2005 +v2k -l compile.vlogan.log -debug_all -f $(SCRIPTS_DIR)/top.$(SIMULATOR).f +define+VCS +define+DMA_TEST $(DEFAULT_DEFINES) +lint=TFIPC-L - cd $(SIM_DIR) && vcs tb $(TEST) $(C_FILES) $(VCS_OPT) -CFLAGS "-I$(C_SDK_USR_INC_DIR)" -CFLAGS "-I$(C_SDK_USR_UTILS_DIR) -std=gnu99" -CFLAGS "-I$(C_COMMON_DIR)/include" -CFLAGS "-I$(C_COMMON_DIR)/src" -CFLAGS "-DSV_TEST" -CFLAGS "-DSCOPE" -CFLAGS "-I$(C_INC_DIR)" "-I$(C_SRC_DIR)" -debug_all -M -I +lint=TFIPC-L -debug_all -debug_pp glbl -ntb_opts tb_timescale=1ps/1ps -timescale=1ps/1ps -sverilog -full64 +memcbk -licqueue -lca -v2005 -l compile.vcs.log + cd $(SIM_DIR) && vcs tb $(TEST) $(C_FILES) $(VCS_OPT) -CFLAGS "-I$(C_SDK_USR_INC_DIR)" -CFLAGS "-I$(C_SDK_USR_UTILS_DIR) -std=gnu99" -CFLAGS "-I$(C_COMMON_DIR)/include" -CFLAGS "-I$(C_COMMON_DIR)/src" -CFLAGS "-DSV_TEST" -CFLAGS "-DSCOPE" -CFLAGS "-I$(C_INC_DIR)" "-I$(C_SRC_DIR)" -debug_all -M +lint=TFIPC-L -debug_all -debug_pp glbl -ntb_opts tb_timescale=1ps/1ps -timescale=1ps/1ps -sverilog -full64 +memcbk -licqueue -lca -v2005 -l compile.vcs.log run: @@ -39,5 +39,5 @@ endif $(COMPLIB_DIR): cd $(SIM_ROOT) && echo "compile_simlib -language all -dir $(COMPLIB_DIR) -simulator $(SIMULATOR) -library all -family all" > create_libs.tcl - cd $(SIM_ROOT) && vivado -mode batch -source create_libs.tcl + -cd $(SIM_ROOT) && vivado -mode batch -source create_libs.tcl cd $(SIM_ROOT) && rm -rf create_libs.tcl diff --git a/hdk/cl/examples/cl_hello_world/software/runtime/test_hello_world.c b/hdk/cl/examples/cl_hello_world/software/runtime/test_hello_world.c index 54b671f9a..6bd8e358c 100644 --- a/hdk/cl/examples/cl_hello_world/software/runtime/test_hello_world.c +++ b/hdk/cl/examples/cl_hello_world/software/runtime/test_hello_world.c @@ -125,7 +125,7 @@ int main(int argc, char **argv) /* initialize the fpga_mgmt library */ rc = fpga_mgmt_init(); - fail_on(rc, out, "Unable to initialize the fpga_pci library"); + fail_on(rc, out, "Unable to initialize the fpga_mgmt library"); #ifndef SV_TEST rc = check_afi_ready(slot_id); diff --git a/hdk/cl/examples/cl_hello_world/verif/scripts/Makefile.ies b/hdk/cl/examples/cl_hello_world/verif/scripts/Makefile.ies index dec3281b0..12842ce3f 100644 --- a/hdk/cl/examples/cl_hello_world/verif/scripts/Makefile.ies +++ b/hdk/cl/examples/cl_hello_world/verif/scripts/Makefile.ies @@ -39,5 +39,5 @@ endif $(COMPLIB_DIR): cd $(SIM_ROOT) && echo "compile_simlib -language all -dir $(COMPLIB_DIR) -simulator $(SIMULATOR) -library all -family all" > create_libs.tcl - cd $(SIM_ROOT) && vivado -mode batch -source create_libs.tcl + -cd $(SIM_ROOT) && vivado -mode batch -source create_libs.tcl cd $(SIM_ROOT) && rm -rf create_libs.tcl diff --git a/hdk/cl/examples/cl_hello_world/verif/scripts/Makefile.questa b/hdk/cl/examples/cl_hello_world/verif/scripts/Makefile.questa index 206aa5f00..3b5b17d11 100644 --- a/hdk/cl/examples/cl_hello_world/verif/scripts/Makefile.questa +++ b/hdk/cl/examples/cl_hello_world/verif/scripts/Makefile.questa @@ -41,6 +41,12 @@ ifeq ($(TEST),test_null) else cd $(SIM_DIR) && vsim -c -voptargs="+acc" -64 -t ps -sv_seed random -L $(COMPLIB_DIR)/unisims_ver -L $(COMPLIB_DIR)/unisim -L $(COMPLIB_DIR)/unifast_ver -L $(COMPLIB_DIR)/unifast -L $(COMPLIB_DIR)/unimacro_ver -L $(COMPLIB_DIR)/unimacro -L $(COMPLIB_DIR)/secureip -L $(COMPLIB_DIR)/axi_register_slice_v2_1_18 -L $(COMPLIB_DIR)/axi_infrastructure_v1_1_0 -L $(COMPLIB_DIR)/axi_crossbar_v2_1_19 -L $(COMPLIB_DIR)/xpm -L $(COMPLIB_DIR)/axi_clock_converter_v2_1_17 -L $(COMPLIB_DIR)/fifo_generator_v13_2_3 -L $(COMPLIB_DIR)/fifo_generator_v13_1_4 -L $(COMPLIB_DIR)/axi_data_fifo_v2_1_17 -L $(COMPLIB_DIR)/generic_baseblocks_v2_1_0 -l $(TEST).log -do "run -all; quit -f" tb glbl $(TEST) endif +else ifeq ($(VIVADO_TOOL_VERSION), v2019.1) +ifeq ($(TEST),test_null) + cd $(SIM_DIR) && vsim -c -voptargs="+acc" -64 -t ps -sv_seed random -L $(COMPLIB_DIR)/unisims_ver -L $(COMPLIB_DIR)/unisim -L $(COMPLIB_DIR)/unifast_ver -L $(COMPLIB_DIR)/unifast -L $(COMPLIB_DIR)/unimacro_ver -L $(COMPLIB_DIR)/unimacro -L $(COMPLIB_DIR)/secureip -L $(COMPLIB_DIR)/axi_register_slice_v2_1_19 -L $(COMPLIB_DIR)/axi_infrastructure_v1_1_0 -L $(COMPLIB_DIR)/axi_crossbar_v2_1_20 -L $(COMPLIB_DIR)/xpm -L $(COMPLIB_DIR)/axi_clock_converter_v2_1_18 -L $(COMPLIB_DIR)/fifo_generator_v13_2_4 -L $(COMPLIB_DIR)/fifo_generator_v13_1_4 -L $(COMPLIB_DIR)/axi_data_fifo_v2_1_18 -L $(COMPLIB_DIR)/generic_baseblocks_v2_1_0 -l $(C_TEST).log -do "run -all; quit -f" tb glbl $(TEST) +else + cd $(SIM_DIR) && vsim -c -voptargs="+acc" -64 -t ps -sv_seed random -L $(COMPLIB_DIR)/unisims_ver -L $(COMPLIB_DIR)/unisim -L $(COMPLIB_DIR)/unifast_ver -L $(COMPLIB_DIR)/unifast -L $(COMPLIB_DIR)/unimacro_ver -L $(COMPLIB_DIR)/unimacro -L $(COMPLIB_DIR)/secureip -L $(COMPLIB_DIR)/axi_register_slice_v2_1_19 -L $(COMPLIB_DIR)/axi_infrastructure_v1_1_0 -L $(COMPLIB_DIR)/axi_crossbar_v2_1_20 -L $(COMPLIB_DIR)/xpm -L $(COMPLIB_DIR)/axi_clock_converter_v2_1_18 -L $(COMPLIB_DIR)/fifo_generator_v13_2_4 -L $(COMPLIB_DIR)/fifo_generator_v13_1_4 -L $(COMPLIB_DIR)/axi_data_fifo_v2_1_18 -L $(COMPLIB_DIR)/generic_baseblocks_v2_1_0 -l $(TEST).log -do "run -all; quit -f" tb glbl $(TEST) +endif else ifeq ($(TEST),test_null) cd $(SIM_DIR) && vsim -c -voptargs="+acc" -64 -t ps -sv_seed random -L $(COMPLIB_DIR)/unisims_ver -L $(COMPLIB_DIR)/unisim -L $(COMPLIB_DIR)/unifast_ver -L $(COMPLIB_DIR)/unifast -L $(COMPLIB_DIR)/unimacro_ver -L $(COMPLIB_DIR)/unimacro -L $(COMPLIB_DIR)/secureip -L $(COMPLIB_DIR)/axi_register_slice_v2_1_17 -L $(COMPLIB_DIR)/axi_infrastructure_v1_1_0 -L $(COMPLIB_DIR)/axi_crossbar_v2_1_18 -L $(COMPLIB_DIR)/xpm -L $(COMPLIB_DIR)/axi_clock_converter_v2_1_16 -L $(COMPLIB_DIR)/fifo_generator_v13_2_2 -L $(COMPLIB_DIR)/fifo_generator_v13_1_4 -L $(COMPLIB_DIR)/axi_data_fifo_v2_1_16 -L $(COMPLIB_DIR)/generic_baseblocks_v2_1_0 -l $(C_TEST).log -do "run -all; quit -f" tb glbl $(TEST) diff --git a/hdk/cl/examples/cl_hello_world/verif/scripts/Makefile.vcs b/hdk/cl/examples/cl_hello_world/verif/scripts/Makefile.vcs index ed3f6487d..9f3fbcd42 100644 --- a/hdk/cl/examples/cl_hello_world/verif/scripts/Makefile.vcs +++ b/hdk/cl/examples/cl_hello_world/verif/scripts/Makefile.vcs @@ -26,7 +26,7 @@ compile: $(COMPLIB_DIR) mkdir -p $(SIM_DIR) cd ${SIM_DIR} && ln -s -f ../vcs_complib/synopsys_sim.setup cd $(SIM_DIR) && vlogan -ntb_opts tb_timescale=1ps/1ps -timescale=1ps/1ps -sverilog +systemverilogext+.sv +libext+.sv +libext+.v -full64 -lca -v2005 +v2k -l compile.vlogan.log -f $(SCRIPTS_DIR)/top.$(SIMULATOR).f +define+VCS $(DEFINES) +lint=TFIPC-L - cd $(SIM_DIR) && vcs tb $(TEST) $(C_FILES) -CFLAGS "-I$(C_SDK_USR_INC_DIR)" -CFLAGS "-I$(C_SDK_USR_UTILS_DIR)" -CFLAGS "-I$(C_COMMON_DIR)/include" -CFLAGS "-I$(C_COMMON_DIR)/src" -CFLAGS "-DSV_TEST" -CFLAGS "-DSCOPE" -CFLAGS "-I$(C_INC_DIR)" -debug_all -M -I +lint=TFIPC-L -debug_pp glbl -ntb_opts tb_timescale=1ps/1ps -timescale=1ps/1ps -sverilog -full64 +memcbk -licqueue -lca -v2005 -l compile.vcs.log + cd $(SIM_DIR) && vcs tb $(TEST) $(C_FILES) -CFLAGS "-I$(C_SDK_USR_INC_DIR)" -CFLAGS "-I$(C_SDK_USR_UTILS_DIR)" -CFLAGS "-I$(C_COMMON_DIR)/include" -CFLAGS "-I$(C_COMMON_DIR)/src" -CFLAGS "-DSV_TEST" -CFLAGS "-DSCOPE" -CFLAGS "-I$(C_INC_DIR)" -debug_all -M +lint=TFIPC-L -debug_pp glbl -ntb_opts tb_timescale=1ps/1ps -timescale=1ps/1ps -sverilog -full64 +memcbk -licqueue -lca -v2005 -l compile.vcs.log run: @@ -38,5 +38,5 @@ endif $(COMPLIB_DIR): cd $(SIM_ROOT) && echo "compile_simlib -language all -dir $(COMPLIB_DIR) -simulator $(SIMULATOR) -library all -family all" > create_libs.tcl - cd $(SIM_ROOT) && vivado -mode batch -source create_libs.tcl + -cd $(SIM_ROOT) && vivado -mode batch -source create_libs.tcl cd $(SIM_ROOT) && rm -rf create_libs.tcl \ No newline at end of file diff --git a/hdk/cl/examples/cl_hello_world_vhdl/verif/scripts/Makefile.questa b/hdk/cl/examples/cl_hello_world_vhdl/verif/scripts/Makefile.questa index 46ff2e701..7e4285e25 100644 --- a/hdk/cl/examples/cl_hello_world_vhdl/verif/scripts/Makefile.questa +++ b/hdk/cl/examples/cl_hello_world_vhdl/verif/scripts/Makefile.questa @@ -34,6 +34,8 @@ ifeq ($(VIVADO_TOOL_VERSION), v2017.4) cd $(SIM_DIR) && vsim -c -voptargs="+acc" -64 -t ps -sv_seed random -L $(COMPLIB_DIR)/unisims_ver -L $(COMPLIB_DIR)/unisim -L $(COMPLIB_DIR)/unifast_ver -L $(COMPLIB_DIR)/unifast -L $(COMPLIB_DIR)/unimacro_ver -L $(COMPLIB_DIR)/unimacro -L $(COMPLIB_DIR)/secureip -L $(COMPLIB_DIR)/axi_register_slice_v2_1_15 -L $(COMPLIB_DIR)/axi_infrastructure_v1_1_0 -L $(COMPLIB_DIR)/axi_crossbar_v2_1_16 -L $(COMPLIB_DIR)/xpm -L $(COMPLIB_DIR)/axi_clock_converter_v2_1_14 -L $(COMPLIB_DIR)/fifo_generator_v13_2_1 -L $(COMPLIB_DIR)/fifo_generator_v13_1_4 -L $(COMPLIB_DIR)/axi_data_fifo_v2_1_14 -L $(COMPLIB_DIR)/generic_baseblocks_v2_1_0 -do "run -all; quit -f" tb glbl $(TEST) else ifeq ($(VIVADO_TOOL_VERSION), v2018.3) cd $(SIM_DIR) && vsim -c -voptargs="+acc" -64 -t ps -sv_seed random -L $(COMPLIB_DIR)/unisims_ver -L $(COMPLIB_DIR)/unisim -L $(COMPLIB_DIR)/unifast_ver -L $(COMPLIB_DIR)/unifast -L $(COMPLIB_DIR)/unimacro_ver -L $(COMPLIB_DIR)/unimacro -L $(COMPLIB_DIR)/secureip -L $(COMPLIB_DIR)/axi_register_slice_v2_1_18 -L $(COMPLIB_DIR)/axi_infrastructure_v1_1_0 -L $(COMPLIB_DIR)/axi_crossbar_v2_1_19 -L $(COMPLIB_DIR)/xpm -L $(COMPLIB_DIR)/axi_clock_converter_v2_1_17 -L $(COMPLIB_DIR)/fifo_generator_v13_2_3 -L $(COMPLIB_DIR)/fifo_generator_v13_1_4 -L $(COMPLIB_DIR)/axi_data_fifo_v2_1_17 -L $(COMPLIB_DIR)/generic_baseblocks_v2_1_0 -do "run -all; quit -f" tb glbl $(TEST) +else ifeq ($(VIVADO_TOOL_VERSION), v2019.1) + cd $(SIM_DIR) && vsim -c -voptargs="+acc" -64 -t ps -sv_seed random -L $(COMPLIB_DIR)/unisims_ver -L $(COMPLIB_DIR)/unisim -L $(COMPLIB_DIR)/unifast_ver -L $(COMPLIB_DIR)/unifast -L $(COMPLIB_DIR)/unimacro_ver -L $(COMPLIB_DIR)/unimacro -L $(COMPLIB_DIR)/secureip -L $(COMPLIB_DIR)/axi_register_slice_v2_1_19 -L $(COMPLIB_DIR)/axi_infrastructure_v1_1_0 -L $(COMPLIB_DIR)/axi_crossbar_v2_1_20 -L $(COMPLIB_DIR)/xpm -L $(COMPLIB_DIR)/axi_clock_converter_v2_1_18 -L $(COMPLIB_DIR)/fifo_generator_v13_2_4 -L $(COMPLIB_DIR)/fifo_generator_v13_1_4 -L $(COMPLIB_DIR)/axi_data_fifo_v2_1_18 -L $(COMPLIB_DIR)/generic_baseblocks_v2_1_0 -do "run -all; quit -f" tb glbl $(TEST) else cd $(SIM_DIR) && vsim -c -voptargs="+acc" -64 -t ps -sv_seed random -L $(COMPLIB_DIR)/unisims_ver -L $(COMPLIB_DIR)/unisim -L $(COMPLIB_DIR)/unifast_ver -L $(COMPLIB_DIR)/unifast -L $(COMPLIB_DIR)/unimacro_ver -L $(COMPLIB_DIR)/unimacro -L $(COMPLIB_DIR)/secureip -L $(COMPLIB_DIR)/axi_register_slice_v2_1_17 -L $(COMPLIB_DIR)/axi_infrastructure_v1_1_0 -L $(COMPLIB_DIR)/axi_crossbar_v2_1_18 -L $(COMPLIB_DIR)/xpm -L $(COMPLIB_DIR)/axi_clock_converter_v2_1_16 -L $(COMPLIB_DIR)/fifo_generator_v13_2_2 -L $(COMPLIB_DIR)/fifo_generator_v13_1_4 -L $(COMPLIB_DIR)/axi_data_fifo_v2_1_16 -L $(COMPLIB_DIR)/generic_baseblocks_v2_1_0 -do "run -all; quit -f" tb glbl $(TEST) endif diff --git a/hdk/cl/examples/cl_hello_world_vhdl/verif/scripts/Makefile.vcs b/hdk/cl/examples/cl_hello_world_vhdl/verif/scripts/Makefile.vcs index 1e0d22000..b3c250dd9 100644 --- a/hdk/cl/examples/cl_hello_world_vhdl/verif/scripts/Makefile.vcs +++ b/hdk/cl/examples/cl_hello_world_vhdl/verif/scripts/Makefile.vcs @@ -27,12 +27,12 @@ compile: $(COMPLIB_DIR) cd ${SIM_DIR} && ln -s -f ../vcs_complib/synopsys_sim.setup cd $(SIM_DIR) && vlogan -ntb_opts tb_timescale=1ps/1ps -timescale=1ps/1ps -sverilog +systemverilogext+.sv +libext+.sv +libext+.v -full64 -lca -v2005 +v2k -l compile.vlogan.log -f $(SCRIPTS_DIR)/top.$(SIMULATOR).f +define+VCS $(DEFINES) +lint=TFIPC-L cd $(SIM_DIR) && vhdlan -full64 -l compile.vhdlan.log -f $(SCRIPTS_DIR)/top_vhdl.$(SIMULATOR).f - cd $(SIM_DIR) && vcs tb $(TEST) $(C_TEST_NAME) -CFLAGS "-I$(C_INC_DIR)" -debug_all -M -I +lint=TFIPC-L -debug_pp glbl -ntb_opts tb_timescale=1ps/1ps -timescale=1ps/1ps -sverilog -full64 +memcbk -licqueue -lca -v2005 -l compile.vcs.log + cd $(SIM_DIR) && vcs tb $(TEST) $(C_TEST_NAME) -CFLAGS "-I$(C_INC_DIR)" -debug_all -M +lint=TFIPC-L -debug_pp glbl -ntb_opts tb_timescale=1ps/1ps -timescale=1ps/1ps -sverilog -full64 +memcbk -licqueue -lca -v2005 -l compile.vcs.log run: cd $(SIM_DIR) && ./simv -l $(TEST).log $(PLUSARGS) +ntb_random_seed_automatic +vpdfile+$(TEST).vpd $(COMPLIB_DIR): cd $(SIM_ROOT) && echo "compile_simlib -language all -dir $(COMPLIB_DIR) -simulator $(SIMULATOR) -library all -family all" > create_libs.tcl - cd $(SIM_ROOT) && vivado -mode batch -source create_libs.tcl + -cd $(SIM_ROOT) && vivado -mode batch -source create_libs.tcl cd $(SIM_ROOT) && rm -rf create_libs.tcl diff --git a/hdk/cl/examples/cl_sde/verif/scripts/Makefile.ies b/hdk/cl/examples/cl_sde/verif/scripts/Makefile.ies index 59da02e64..65df9e036 100644 --- a/hdk/cl/examples/cl_sde/verif/scripts/Makefile.ies +++ b/hdk/cl/examples/cl_sde/verif/scripts/Makefile.ies @@ -39,5 +39,5 @@ endif $(COMPLIB_DIR): cd $(SIM_ROOT) && echo "compile_simlib -language all -dir $(COMPLIB_DIR) -simulator $(SIMULATOR) -library all -family all" > create_libs.tcl - cd $(SIM_ROOT) && vivado -mode batch -source create_libs.tcl + -cd $(SIM_ROOT) && vivado -mode batch -source create_libs.tcl cd $(SIM_ROOT) && rm -rf create_libs.tcl diff --git a/hdk/cl/examples/cl_sde/verif/scripts/Makefile.questa b/hdk/cl/examples/cl_sde/verif/scripts/Makefile.questa index b48581724..decab5be8 100644 --- a/hdk/cl/examples/cl_sde/verif/scripts/Makefile.questa +++ b/hdk/cl/examples/cl_sde/verif/scripts/Makefile.questa @@ -41,6 +41,12 @@ ifeq ($(TEST),test_null) else cd $(SIM_DIR) && vsim -c -voptargs="+acc" -64 -t ps -sv_seed random -L $(COMPLIB_DIR)/unisims_ver -L $(COMPLIB_DIR)/unisim -L $(COMPLIB_DIR)/unifast_ver -L $(COMPLIB_DIR)/unifast -L $(COMPLIB_DIR)/unimacro_ver -L $(COMPLIB_DIR)/unimacro -L $(COMPLIB_DIR)/secureip -L $(COMPLIB_DIR)/axi_register_slice_v2_1_18 -L $(COMPLIB_DIR)/axi_infrastructure_v1_1_0 -L $(COMPLIB_DIR)/axi_crossbar_v2_1_19 -L $(COMPLIB_DIR)/xpm -L $(COMPLIB_DIR)/axi_clock_converter_v2_1_17 -L $(COMPLIB_DIR)/fifo_generator_v13_2_3 -L $(COMPLIB_DIR)/fifo_generator_v13_1_4 -L $(COMPLIB_DIR)/axi_data_fifo_v2_1_17 -L $(COMPLIB_DIR)/generic_baseblocks_v2_1_0 -l $(TEST).log -do "run -all; quit -f" tb glbl $(TEST) endif +else ifeq ($(VIVADO_TOOL_VERSION), v2019.1) +ifeq ($(TEST),test_null) + cd $(SIM_DIR) && vsim -c -voptargs="+acc" -64 -t ps -sv_seed random -L $(COMPLIB_DIR)/unisims_ver -L $(COMPLIB_DIR)/unisim -L $(COMPLIB_DIR)/unifast_ver -L $(COMPLIB_DIR)/unifast -L $(COMPLIB_DIR)/unimacro_ver -L $(COMPLIB_DIR)/unimacro -L $(COMPLIB_DIR)/secureip -L $(COMPLIB_DIR)/axi_register_slice_v2_1_19 -L $(COMPLIB_DIR)/axi_infrastructure_v1_1_0 -L $(COMPLIB_DIR)/axi_crossbar_v2_1_20 -L $(COMPLIB_DIR)/xpm -L $(COMPLIB_DIR)/axi_clock_converter_v2_1_18 -L $(COMPLIB_DIR)/fifo_generator_v13_2_4 -L $(COMPLIB_DIR)/fifo_generator_v13_1_4 -L $(COMPLIB_DIR)/axi_data_fifo_v2_1_18 -L $(COMPLIB_DIR)/generic_baseblocks_v2_1_0 -l $(C_TEST).log -do "run -all; quit -f" tb glbl $(TEST) +else + cd $(SIM_DIR) && vsim -c -voptargs="+acc" -64 -t ps -sv_seed random -L $(COMPLIB_DIR)/unisims_ver -L $(COMPLIB_DIR)/unisim -L $(COMPLIB_DIR)/unifast_ver -L $(COMPLIB_DIR)/unifast -L $(COMPLIB_DIR)/unimacro_ver -L $(COMPLIB_DIR)/unimacro -L $(COMPLIB_DIR)/secureip -L $(COMPLIB_DIR)/axi_register_slice_v2_1_19 -L $(COMPLIB_DIR)/axi_infrastructure_v1_1_0 -L $(COMPLIB_DIR)/axi_crossbar_v2_1_20 -L $(COMPLIB_DIR)/xpm -L $(COMPLIB_DIR)/axi_clock_converter_v2_1_18 -L $(COMPLIB_DIR)/fifo_generator_v13_2_4 -L $(COMPLIB_DIR)/fifo_generator_v13_1_4 -L $(COMPLIB_DIR)/axi_data_fifo_v2_1_18 -L $(COMPLIB_DIR)/generic_baseblocks_v2_1_0 -l $(TEST).log -do "run -all; quit -f" tb glbl $(TEST) +endif else ifeq ($(TEST),test_null) cd $(SIM_DIR) && vsim -c -voptargs="+acc" -64 -t ps -sv_seed random -L $(COMPLIB_DIR)/unisims_ver -L $(COMPLIB_DIR)/unisim -L $(COMPLIB_DIR)/unifast_ver -L $(COMPLIB_DIR)/unifast -L $(COMPLIB_DIR)/unimacro_ver -L $(COMPLIB_DIR)/unimacro -L $(COMPLIB_DIR)/secureip -L $(COMPLIB_DIR)/axi_register_slice_v2_1_17 -L $(COMPLIB_DIR)/axi_infrastructure_v1_1_0 -L $(COMPLIB_DIR)/axi_crossbar_v2_1_18 -L $(COMPLIB_DIR)/xpm -L $(COMPLIB_DIR)/axi_clock_converter_v2_1_16 -L $(COMPLIB_DIR)/fifo_generator_v13_2_2 -L $(COMPLIB_DIR)/fifo_generator_v13_1_4 -L $(COMPLIB_DIR)/axi_data_fifo_v2_1_16 -L $(COMPLIB_DIR)/generic_baseblocks_v2_1_0 -l $(C_TEST).log -do "run -all; quit -f" tb glbl $(TEST) diff --git a/hdk/cl/examples/cl_sde/verif/scripts/Makefile.vcs b/hdk/cl/examples/cl_sde/verif/scripts/Makefile.vcs index 61f241f9e..dc2f5f3ee 100644 --- a/hdk/cl/examples/cl_sde/verif/scripts/Makefile.vcs +++ b/hdk/cl/examples/cl_sde/verif/scripts/Makefile.vcs @@ -26,12 +26,12 @@ compile: $(COMPLIB_DIR) mkdir -p $(SIM_DIR) cd $(SIM_DIR) && ln -s -f ../vcs_complib/synopsys_sim.setup cd $(SIM_DIR) && vlogan -ntb_opts tb_timescale=1ps/1ps -timescale=1ps/1ps -sverilog +systemverilogext+.sv +libext+.sv +libext+.v -full64 -lca -v2005 +v2k -l compile.vlogan.log -f $(SCRIPTS_DIR)/top.$(SIMULATOR).f +define+VCS $(DEFINES) +lint=TFIPC-L - cd $(SIM_DIR) && vcs tb $(TEST) $(C_FILES) -CFLAGS "-I$(C_SDK_USR_INC_DIR)" -CFLAGS "-I$(C_SDK_USR_UTILS_DIR)" -CFLAGS "-I$(C_COMMON_DIR)/include" -CFLAGS "-I$(C_COMMON_DIR)/src" -CFLAGS "-DSV_TEST" -CFLAGS "-DSCOPE" -CFLAGS "-I$(C_INC_DIR)" -debug_all -M -I +lint=TFIPC-L -debug_pp glbl -ntb_opts tb_timescale=1ps/1ps -timescale=1ps/1ps -sverilog -full64 +memcbk -licqueue -lca -v2005 -l compile.vcs.log + cd $(SIM_DIR) && vcs tb $(TEST) $(C_FILES) -CFLAGS "-I$(C_SDK_USR_INC_DIR)" -CFLAGS "-I$(C_SDK_USR_UTILS_DIR)" -CFLAGS "-I$(C_COMMON_DIR)/include" -CFLAGS "-I$(C_COMMON_DIR)/src" -CFLAGS "-DSV_TEST" -CFLAGS "-DSCOPE" -CFLAGS "-I$(C_INC_DIR)" -debug_all -M +lint=TFIPC-L -debug_pp glbl -ntb_opts tb_timescale=1ps/1ps -timescale=1ps/1ps -sverilog -full64 +memcbk -licqueue -lca -v2005 -l compile.vcs.log run: cd $(SIM_DIR) && ./simv -l -l $(TEST).log $(PLUSARGS) +ntb_random_seed_automatic +vpdfile+$(TEST).vpd $(COMPLIB_DIR): cd $(SIM_ROOT) && echo "compile_simlib -language all -dir $(COMPLIB_DIR) -simulator $(SIMULATOR) -library all -family all" > create_libs.tcl - cd $(SIM_ROOT) && vivado -mode batch -source create_libs.tcl + -cd $(SIM_ROOT) && vivado -mode batch -source create_libs.tcl cd $(SIM_ROOT) && rm -rf create_libs.tcl diff --git a/hdk/cl/examples/cl_uram_example/verif/scripts/Makefile.ies b/hdk/cl/examples/cl_uram_example/verif/scripts/Makefile.ies index 4e46036b3..d623c649a 100644 --- a/hdk/cl/examples/cl_uram_example/verif/scripts/Makefile.ies +++ b/hdk/cl/examples/cl_uram_example/verif/scripts/Makefile.ies @@ -40,5 +40,5 @@ endif $(COMPLIB_DIR): cd $(SIM_ROOT) && echo "compile_simlib -language all -dir $(COMPLIB_DIR) -simulator $(SIMULATOR) -library all -family all" > create_libs.tcl - cd $(SIM_ROOT) && vivado -mode batch -source create_libs.tcl + -cd $(SIM_ROOT) && vivado -mode batch -source create_libs.tcl cd $(SIM_ROOT) && rm -rf create_libs.tcl diff --git a/hdk/cl/examples/cl_uram_example/verif/scripts/Makefile.questa b/hdk/cl/examples/cl_uram_example/verif/scripts/Makefile.questa index 0cb6d70e0..3d31459e1 100644 --- a/hdk/cl/examples/cl_uram_example/verif/scripts/Makefile.questa +++ b/hdk/cl/examples/cl_uram_example/verif/scripts/Makefile.questa @@ -42,6 +42,12 @@ ifeq ($(TEST),test_null) else cd $(SIM_DIR) && vsim -c -voptargs="+acc" -64 -t ps -sv_seed random -L $(COMPLIB_DIR)/unisims_ver -L $(COMPLIB_DIR)/unisim -L $(COMPLIB_DIR)/unifast_ver -L $(COMPLIB_DIR)/unifast -L $(COMPLIB_DIR)/unimacro_ver -L $(COMPLIB_DIR)/unimacro -L $(COMPLIB_DIR)/secureip -L $(COMPLIB_DIR)/axi_register_slice_v2_1_18 -L $(COMPLIB_DIR)/axi_infrastructure_v1_1_0 -L $(COMPLIB_DIR)/axi_crossbar_v2_1_19 -L $(COMPLIB_DIR)/xpm -L $(COMPLIB_DIR)/axi_clock_converter_v2_1_17 -L $(COMPLIB_DIR)/fifo_generator_v13_1_4 -L $(COMPLIB_DIR)/axi_data_fifo_v2_1_17 -L $(COMPLIB_DIR)/generic_baseblocks_v2_1_0 -l $(TEST).log -do "run -all; quit -f" tb glbl $(TEST) endif +else ifeq ($(VIVADO_TOOL_VERSION), v2019.1) +ifeq ($(TEST),test_null) + cd $(SIM_DIR) && vsim -c -voptargs="+acc" -64 -t ps -sv_seed random -L $(COMPLIB_DIR)/unisims_ver -L $(COMPLIB_DIR)/unisim -L $(COMPLIB_DIR)/unifast_ver -L $(COMPLIB_DIR)/unifast -L $(COMPLIB_DIR)/unimacro_ver -L $(COMPLIB_DIR)/unimacro -L $(COMPLIB_DIR)/secureip -L $(COMPLIB_DIR)/axi_register_slice_v2_1_19 -L $(COMPLIB_DIR)/axi_infrastructure_v1_1_0 -L $(COMPLIB_DIR)/axi_crossbar_v2_1_20 -L $(COMPLIB_DIR)/xpm -L $(COMPLIB_DIR)/axi_clock_converter_v2_1_18 -L $(COMPLIB_DIR)/fifo_generator_v13_1_4 -L $(COMPLIB_DIR)/axi_data_fifo_v2_1_18 -L $(COMPLIB_DIR)/generic_baseblocks_v2_1_0 -l $(C_TEST).log -do "run -all; quit -f" tb glbl $(TEST) +else + cd $(SIM_DIR) && vsim -c -voptargs="+acc" -64 -t ps -sv_seed random -L $(COMPLIB_DIR)/unisims_ver -L $(COMPLIB_DIR)/unisim -L $(COMPLIB_DIR)/unifast_ver -L $(COMPLIB_DIR)/unifast -L $(COMPLIB_DIR)/unimacro_ver -L $(COMPLIB_DIR)/unimacro -L $(COMPLIB_DIR)/secureip -L $(COMPLIB_DIR)/axi_register_slice_v2_1_19 -L $(COMPLIB_DIR)/axi_infrastructure_v1_1_0 -L $(COMPLIB_DIR)/axi_crossbar_v2_1_20 -L $(COMPLIB_DIR)/xpm -L $(COMPLIB_DIR)/axi_clock_converter_v2_1_18 -L $(COMPLIB_DIR)/fifo_generator_v13_1_4 -L $(COMPLIB_DIR)/axi_data_fifo_v2_1_18 -L $(COMPLIB_DIR)/generic_baseblocks_v2_1_0 -l $(TEST).log -do "run -all; quit -f" tb glbl $(TEST) +endif else ifeq ($(TEST),test_null) cd $(SIM_DIR) && vsim -c -voptargs="+acc" -64 -t ps -sv_seed random -L $(COMPLIB_DIR)/unisims_ver -L $(COMPLIB_DIR)/unisim -L $(COMPLIB_DIR)/unifast_ver -L $(COMPLIB_DIR)/unifast -L $(COMPLIB_DIR)/unimacro_ver -L $(COMPLIB_DIR)/unimacro -L $(COMPLIB_DIR)/secureip -L $(COMPLIB_DIR)/axi_register_slice_v2_1_17 -L $(COMPLIB_DIR)/axi_infrastructure_v1_1_0 -L $(COMPLIB_DIR)/axi_crossbar_v2_1_18 -L $(COMPLIB_DIR)/xpm -L $(COMPLIB_DIR)/axi_clock_converter_v2_1_16 -L $(COMPLIB_DIR)/fifo_generator_v13_1_4 -L $(COMPLIB_DIR)/axi_data_fifo_v2_1_16 -L $(COMPLIB_DIR)/generic_baseblocks_v2_1_0 -l $(C_TEST).log -do "run -all; quit -f" tb glbl $(TEST) diff --git a/hdk/cl/examples/cl_uram_example/verif/scripts/Makefile.vcs b/hdk/cl/examples/cl_uram_example/verif/scripts/Makefile.vcs index efc2fd924..367b53fe2 100644 --- a/hdk/cl/examples/cl_uram_example/verif/scripts/Makefile.vcs +++ b/hdk/cl/examples/cl_uram_example/verif/scripts/Makefile.vcs @@ -27,7 +27,7 @@ compile: $(COMPLIB_DIR) cd ${SIM_DIR} && ln -s -f ../vcs_complib/synopsys_sim.setup cd $(SIM_DIR) && vhdlan -full64 ${CL_ROOT}/design/ctrl_uram.vhd cd $(SIM_DIR) && vlogan -ntb_opts tb_timescale=1ps/1ps -timescale=1ps/1ps -sverilog +systemverilogext+.sv +libext+.sv +libext+.v -full64 -lca -v2005 +v2k -l compile.vlogan.log -f $(SCRIPTS_DIR)/top.$(SIMULATOR).f +define+VCS $(DEFINES) +lint=TFIPC-L - cd $(SIM_DIR) && vcs tb $(TEST) $(C_FILES) -CFLAGS "-I$(C_SDK_USR_INC_DIR)" -CFLAGS "-I$(C_SDK_USR_UTILS_DIR)" -CFLAGS "-I$(C_COMMON_DIR)/include" -CFLAGS "-I$(C_COMMON_DIR)/src" -CFLAGS "-DSV_TEST" -CFLAGS "-DSCOPE" -CFLAGS "-I$(C_INC_DIR)" -debug_all -M -I +lint=TFIPC-L -debug_pp glbl -ntb_opts tb_timescale=1ps/1ps -timescale=1ps/1ps -sverilog -full64 +memcbk -licqueue -lca -v2005 -l compile.vcs.log + cd $(SIM_DIR) && vcs tb $(TEST) $(C_FILES) -CFLAGS "-I$(C_SDK_USR_INC_DIR)" -CFLAGS "-I$(C_SDK_USR_UTILS_DIR)" -CFLAGS "-I$(C_COMMON_DIR)/include" -CFLAGS "-I$(C_COMMON_DIR)/src" -CFLAGS "-DSV_TEST" -CFLAGS "-DSCOPE" -CFLAGS "-I$(C_INC_DIR)" -debug_all -M +lint=TFIPC-L -debug_pp glbl -ntb_opts tb_timescale=1ps/1ps -timescale=1ps/1ps -sverilog -full64 +memcbk -licqueue -lca -v2005 -l compile.vcs.log run: @@ -39,5 +39,5 @@ endif $(COMPLIB_DIR): cd $(SIM_ROOT) && echo "compile_simlib -language all -dir $(COMPLIB_DIR) -simulator $(SIMULATOR) -library all -family all" > create_libs.tcl - cd $(SIM_ROOT) && vivado -mode batch -source create_libs.tcl + -cd $(SIM_ROOT) && vivado -mode batch -source create_libs.tcl cd $(SIM_ROOT) && rm -rf create_libs.tcl \ No newline at end of file diff --git a/hdk/cl/examples/hello_world_hlx/README.md b/hdk/cl/examples/hello_world_hlx/README.md index d6d9371fe..47e35ebf2 100755 --- a/hdk/cl/examples/hello_world_hlx/README.md +++ b/hdk/cl/examples/hello_world_hlx/README.md @@ -101,6 +101,7 @@ The runtime software must be compiled for the AFI to run on F1. Copy the software directory to any directory and compile with the following commands: ``` +$ source $AWS_FPGA_REPO_DIR/sdk_setup.sh $ cp -r $HDK_COMMON_DIR/shell_stable/hlx/hlx_examples/build/IPI/hello_world/software $ cd software $ make all diff --git a/hdk/common/shell_v04261818/hlx/design/ip/aws_v1_0/component.xml b/hdk/common/shell_v04261818/hlx/design/ip/aws_v1_0/component.xml old mode 100755 new mode 100644 index 1a4dff5b1..de54734cf --- a/hdk/common/shell_v04261818/hlx/design/ip/aws_v1_0/component.xml +++ b/hdk/common/shell_v04261818/hlx/design/ip/aws_v1_0/component.xml @@ -4407,7 +4407,7 @@ viewChecksum - 01e58ca0 + ebc2f515 @@ -4429,7 +4429,7 @@ viewChecksum - 7a659885 + ffa0fbf3 @@ -15920,7 +15920,61 @@ aws_v1_0_2 - hdl/aws_v1_0_vl_rfs.sv + hdl/sim/axi4_slave_bfm.sv + systemVerilogSource + USED_IN_ipstatic + aws_v1_0_2 + + + hdl/sim/axi_bfm_defines.svh + systemVerilogSource + USED_IN_ipstatic + aws_v1_0_2 + + + hdl/sim/axi_mem_model.sv + systemVerilogSource + USED_IN_ipstatic + aws_v1_0_2 + + + hdl/lib_pipe.sv + systemVerilogSource + USED_IN_ipstatic + aws_v1_0_2 + + + hdl/sim/ccf_ctl.v + verilogSource + USED_IN_ipstatic + aws_v1_0_2 + + + hdl/sim/sync.v + verilogSource + USED_IN_ipstatic + aws_v1_0_2 + + + hdl/sim/flop_ccf.sv + systemVerilogSource + USED_IN_ipstatic + aws_v1_0_2 + + + hdl/sim/mgt_acc_axl.sv + systemVerilogSource + USED_IN_ipstatic + aws_v1_0_2 + + + hdl/sim/mgt_gen_axl.sv + systemVerilogSource + USED_IN_ipstatic + aws_v1_0_2 + + + hdl/sim/sh_ddr.sv systemVerilogSource USED_IN_ipstatic aws_v1_0_2 @@ -15938,6 +15992,12 @@ true aws_v1_0_2 + + hdl/aws_v1_0_top.sv + systemVerilogSource + USED_IN_ipstatic + aws_v1_0_2 + xilinx_verilogbehavioralsimulation_xilinx_com_ip_ddr4_2_2__ref_view_fileset @@ -15979,7 +16039,37 @@ aws_v1_0_2 - hdl/aws_v1_0_vlsyn_rfs.sv + hdl/lib_pipe.sv + systemVerilogSource + aws_v1_0_2 + + + hdl/synth/ccf_ctl.v + verilogSource + aws_v1_0_2 + + + hdl/synth/sync.v + verilogSource + aws_v1_0_2 + + + hdl/synth/flop_ccf.sv + systemVerilogSource + aws_v1_0_2 + + + hdl/synth/mgt_acc_axl.sv + systemVerilogSource + aws_v1_0_2 + + + hdl/synth/mgt_gen_axl.sv + systemVerilogSource + aws_v1_0_2 + + + hdl/synth/sh_ddr.sv systemVerilogSource aws_v1_0_2 @@ -15995,6 +16085,12 @@ true aws_v1_0_2 + + hdl/aws_v1_0_top.sv + systemVerilogSource + CHECKSUM_c59ef6a9 + aws_v1_0_2 + xilinx_verilogsynthesis_xilinx_com_ip_ddr4_2_2__ref_view_fileset @@ -16429,14 +16525,14 @@ AWS http://www.xilinx.com 2 - 2018-06-05T19:20:33Z + 2019-08-08T23:47:40Z 2017.4 - + diff --git a/hdk/common/shell_v04261818/hlx/design/ip/aws_v1_0/doc/aws_v1_0_changelog.txt b/hdk/common/shell_v04261818/hlx/design/ip/aws_v1_0/doc/aws_v1_0_changelog.txt old mode 100755 new mode 100644 index eaf4576a7..ab0095d6a --- a/hdk/common/shell_v04261818/hlx/design/ip/aws_v1_0/doc/aws_v1_0_changelog.txt +++ b/hdk/common/shell_v04261818/hlx/design/ip/aws_v1_0/doc/aws_v1_0_changelog.txt @@ -4,6 +4,7 @@ * Bug Fix: Changed default Clock Group A recipe from A0 to A1. * New Feature: Support new Amazon shell v1.4 (SHELL_VERSION = 0x04261818). * New Feature: Changed default DEVICE_ID from 0xF000 to 0xF010. + * New Feature: Added AXI slave BFM simulation models. * Revision change in one or more subcores 2017.3: @@ -20,7 +21,7 @@ * New Feature: Native Vivado Release * New Feature: Initial release. -(c) Copyright 2017 - 2018 Xilinx, Inc. All rights reserved. +(c) Copyright 2017 - 2019 Xilinx, Inc. All rights reserved. This file contains confidential and proprietary information of Xilinx, Inc. and is protected under U.S. and diff --git a/hdk/common/shell_v04261818/hlx/design/ip/aws_v1_0/hdl/aws_v1_0_top.sv b/hdk/common/shell_v04261818/hlx/design/ip/aws_v1_0/hdl/aws_v1_0_top.sv new file mode 100644 index 000000000..df3ce581a --- /dev/null +++ b/hdk/common/shell_v04261818/hlx/design/ip/aws_v1_0/hdl/aws_v1_0_top.sv @@ -0,0 +1,1006 @@ +// (c) Copyright 2017 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +(* DowngradeIPIdentifiedWarnings="yes" *) +module aws_v1_0_2_top # + ( + parameter integer C_MODE = 0, + // 0 = AWS HLS (IPI) flow: All interfaces are available. + // 1 = SDx Unified flow Memory-only mode: Only DDR interfaces and related ports are available. + // 2 = SDx Unified flow Non-memory mode: All interfaces except DDR-related are available. + parameter integer C_DDR_A_PRESENT = 0, + parameter integer C_DDR_B_PRESENT = 0, + parameter integer C_DDR_D_PRESENT = 0, + parameter integer C_NUM_A_CLOCKS = 1, + parameter integer C_NUM_B_CLOCKS = 0, + parameter integer C_NUM_C_CLOCKS = 0, + parameter [15:0] C_VENDOR_ID = 16'h1D0F, + parameter [15:0] C_DEVICE_ID = 16'hF010, + parameter [15:0] C_SUBSYSTEM_VENDOR_ID = 16'hFEDD, + parameter [15:0] C_SUBSYSTEM_ID = 16'h1D51, + parameter C_CLOCK_A0_PERIOD = "4.0", + parameter C_CLOCK_A1_PERIOD = "8.0", + parameter C_CLOCK_B0_PERIOD = "4.0", + parameter C_CLOCK_C0_PERIOD = "3.333333", + parameter integer C_CLOCK_A_RECIPE = 1, + parameter integer C_CLOCK_B_RECIPE = 0, + parameter integer C_CLOCK_C_RECIPE = 0, + parameter integer C_NUM_STAGES_STATS = 1, + parameter integer C_PCIM_PRESENT = 0 + ) + ( + //-------------------------------- + // S_SH bus-interface ports + //-------------------------------- + `include "aws_v1_0_2_ports.vh" // Subset of Amazon-provided port definitions (without Debug Bridge) + , + + //-------------------------------- + // Globals + //-------------------------------- + output wire clk_main_a0_out, //Main clock. This is the clock for all of the interfaces of AWS + output wire clk_extra_a1_out, //Extra clock A1 (phase aligned to "A" clock group) + output wire clk_extra_a2_out, //Extra clock A2 (phase aligned to "A" clock group) + output wire clk_extra_a3_out, //Extra clock A3 (phase aligned to "A" clock group) + output wire clk_extra_b0_out, //Extra clock B0 (phase aligned to "B" clock group) + output wire clk_extra_b1_out, //Extra clock B1 (phase aligned to "B" clock group) + output wire clk_extra_c0_out, //Extra clock C0 (phase aligned to "C" clock group) + output wire clk_extra_c1_out, //Extra clock C1 (phase aligned to "C" clock group) + + output wire rst_main_n_out, //Reset sync to main clock. + output wire kernel_rst_n_out, //Kernel_reset. + + output wire flr_assert, //Function level reset assertion. + input wire flr_done, //Function level reset done acknowledge + + output wire [15:0] status_vdip, //Virtual DIP switches. + input wire [15:0] status_vled, //Virtual LEDs + + input wire [15:0] irq_req, // User-defined interrupt request + output wire [15:0] irq_ack, // User-defined interrupt acknowledge + + output wire [63:0] glcount0, //Global counter 0 + output wire [63:0] glcount1, //Global counter 1 + + //-------------------------------- + // S_AXI_DDRA bus-interface ports + //-------------------------------- + input wire [15:0] s_axi_ddra_awid, + input wire [63:0] s_axi_ddra_awaddr, + input wire [7:0] s_axi_ddra_awlen, + input wire [2:0] s_axi_ddra_awsize, + input wire s_axi_ddra_awvalid, + output wire s_axi_ddra_awready, + input wire [511:0] s_axi_ddra_wdata, + input wire [63:0] s_axi_ddra_wstrb, + input wire s_axi_ddra_wlast, + input wire s_axi_ddra_wvalid, + output wire s_axi_ddra_wready, + output wire [15:0] s_axi_ddra_bid, + output wire [1:0] s_axi_ddra_bresp, + output wire s_axi_ddra_bvalid, + input wire s_axi_ddra_bready, + input wire [15:0] s_axi_ddra_arid, + input wire [63:0] s_axi_ddra_araddr, + input wire [7:0] s_axi_ddra_arlen, + input wire [2:0] s_axi_ddra_arsize, + input wire s_axi_ddra_arvalid, + output wire s_axi_ddra_arready, + output wire [15:0] s_axi_ddra_rid, + output wire [511:0] s_axi_ddra_rdata, + output wire [1:0] s_axi_ddra_rresp, + output wire s_axi_ddra_rlast, + output wire s_axi_ddra_rvalid, + input wire s_axi_ddra_rready, + + output wire ddra_is_ready, + + //-------------------------------- + // S_AXI_DDRB bus-interface ports + //-------------------------------- + input wire [15:0] s_axi_ddrb_awid, + input wire [63:0] s_axi_ddrb_awaddr, + input wire [7:0] s_axi_ddrb_awlen, + input wire [2:0] s_axi_ddrb_awsize, + input wire s_axi_ddrb_awvalid, + output wire s_axi_ddrb_awready, + input wire [511:0] s_axi_ddrb_wdata, + input wire [63:0] s_axi_ddrb_wstrb, + input wire s_axi_ddrb_wlast, + input wire s_axi_ddrb_wvalid, + output wire s_axi_ddrb_wready, + output wire [15:0] s_axi_ddrb_bid, + output wire [1:0] s_axi_ddrb_bresp, + output wire s_axi_ddrb_bvalid, + input wire s_axi_ddrb_bready, + input wire [15:0] s_axi_ddrb_arid, + input wire [63:0] s_axi_ddrb_araddr, + input wire [7:0] s_axi_ddrb_arlen, + input wire [2:0] s_axi_ddrb_arsize, + input wire s_axi_ddrb_arvalid, + output wire s_axi_ddrb_arready, + output wire [15:0] s_axi_ddrb_rid, + output wire [511:0] s_axi_ddrb_rdata, + output wire [1:0] s_axi_ddrb_rresp, + output wire s_axi_ddrb_rlast, + output wire s_axi_ddrb_rvalid, + input wire s_axi_ddrb_rready, + + output wire ddrb_is_ready, + + //-------------------------------- + // S_AXI_DDRC bus-interface ports + //-------------------------------- + input wire [15:0] s_axi_ddrc_awid, + input wire [63:0] s_axi_ddrc_awaddr, + input wire [7:0] s_axi_ddrc_awlen, + input wire [2:0] s_axi_ddrc_awsize, + input wire s_axi_ddrc_awvalid, + output wire s_axi_ddrc_awready, + input wire [511:0] s_axi_ddrc_wdata, + input wire [63:0] s_axi_ddrc_wstrb, + input wire s_axi_ddrc_wlast, + input wire s_axi_ddrc_wvalid, + output wire s_axi_ddrc_wready, + output wire [15:0] s_axi_ddrc_bid, + output wire [1:0] s_axi_ddrc_bresp, + output wire s_axi_ddrc_bvalid, + input wire s_axi_ddrc_bready, + input wire [15:0] s_axi_ddrc_arid, + input wire [63:0] s_axi_ddrc_araddr, + input wire [7:0] s_axi_ddrc_arlen, + input wire [2:0] s_axi_ddrc_arsize, + input wire s_axi_ddrc_arvalid, + output wire s_axi_ddrc_arready, + output wire [15:0] s_axi_ddrc_rid, + output wire [511:0] s_axi_ddrc_rdata, + output wire [1:0] s_axi_ddrc_rresp, + output wire s_axi_ddrc_rlast, + output wire s_axi_ddrc_rvalid, + input wire s_axi_ddrc_rready, + + output wire ddrc_is_ready, + + //-------------------------------- + // S_AXI_DDRD bus-interface ports + //-------------------------------- + input wire [15:0] s_axi_ddrd_awid, + input wire [63:0] s_axi_ddrd_awaddr, + input wire [7:0] s_axi_ddrd_awlen, + input wire [2:0] s_axi_ddrd_awsize, + input wire s_axi_ddrd_awvalid, + output wire s_axi_ddrd_awready, + input wire [511:0] s_axi_ddrd_wdata, + input wire [63:0] s_axi_ddrd_wstrb, + input wire s_axi_ddrd_wlast, + input wire s_axi_ddrd_wvalid, + output wire s_axi_ddrd_wready, + output wire [15:0] s_axi_ddrd_bid, + output wire [1:0] s_axi_ddrd_bresp, + output wire s_axi_ddrd_bvalid, + input wire s_axi_ddrd_bready, + input wire [15:0] s_axi_ddrd_arid, + input wire [63:0] s_axi_ddrd_araddr, + input wire [7:0] s_axi_ddrd_arlen, + input wire [2:0] s_axi_ddrd_arsize, + input wire s_axi_ddrd_arvalid, + output wire s_axi_ddrd_arready, + output wire [15:0] s_axi_ddrd_rid, + output wire [511:0] s_axi_ddrd_rdata, + output wire [1:0] s_axi_ddrd_rresp, + output wire s_axi_ddrd_rlast, + output wire s_axi_ddrd_rvalid, + input wire s_axi_ddrd_rready, + + output wire ddrd_is_ready, + + //-------------------------------- + // M_AXI_SDA bus-interface ports + //-------------------------------- + output wire [31:0] m_axi_sda_awaddr, + output wire m_axi_sda_awvalid, + input wire m_axi_sda_awready, + output wire [31:0] m_axi_sda_wdata, + output wire [3:0] m_axi_sda_wstrb, + output wire m_axi_sda_wvalid, + input wire m_axi_sda_wready, + input wire [1:0] m_axi_sda_bresp, + input wire m_axi_sda_bvalid, + output wire m_axi_sda_bready, + output wire [31:0] m_axi_sda_araddr, + output wire m_axi_sda_arvalid, + input wire m_axi_sda_arready, + input wire [31:0] m_axi_sda_rdata, + input wire [1:0] m_axi_sda_rresp, + input wire m_axi_sda_rvalid, + output wire m_axi_sda_rready, + + //-------------------------------- + // M_AXI_OCL bus-interface ports + //-------------------------------- + output wire [31:0] m_axi_ocl_awaddr, + output wire m_axi_ocl_awvalid, + input wire m_axi_ocl_awready, + output wire [31:0] m_axi_ocl_wdata, + output wire [3:0] m_axi_ocl_wstrb, + output wire m_axi_ocl_wvalid, + input wire m_axi_ocl_wready, + input wire [1:0] m_axi_ocl_bresp, + input wire m_axi_ocl_bvalid, + output wire m_axi_ocl_bready, + output wire [31:0] m_axi_ocl_araddr, + output wire m_axi_ocl_arvalid, + input wire m_axi_ocl_arready, + input wire [31:0] m_axi_ocl_rdata, + input wire [1:0] m_axi_ocl_rresp, + input wire m_axi_ocl_rvalid, + output wire m_axi_ocl_rready, + + //-------------------------------- + // M_AXI_BAR1 bus-interface ports + //-------------------------------- + output wire [31:0] m_axi_bar1_awaddr, + output wire m_axi_bar1_awvalid, + input wire m_axi_bar1_awready, + output wire [31:0] m_axi_bar1_wdata, + output wire [3:0] m_axi_bar1_wstrb, + output wire m_axi_bar1_wvalid, + input wire m_axi_bar1_wready, + input wire [1:0] m_axi_bar1_bresp, + input wire m_axi_bar1_bvalid, + output wire m_axi_bar1_bready, + output wire [31:0] m_axi_bar1_araddr, + output wire m_axi_bar1_arvalid, + input wire m_axi_bar1_arready, + input wire [31:0] m_axi_bar1_rdata, + input wire [1:0] m_axi_bar1_rresp, + input wire m_axi_bar1_rvalid, + output wire m_axi_bar1_rready, + + //-------------------------------- + // M_AXI_PCIS bus-interface ports (SH transactions to CL) + //-------------------------------- + output wire [5:0] m_axi_pcis_awid, + output wire [63:0] m_axi_pcis_awaddr, + output wire [7:0] m_axi_pcis_awlen, + output wire [2:0] m_axi_pcis_awsize, + output wire m_axi_pcis_awvalid, + input wire m_axi_pcis_awready, + output wire [511:0] m_axi_pcis_wdata, + output wire [63:0] m_axi_pcis_wstrb, + output wire m_axi_pcis_wlast, + output wire m_axi_pcis_wvalid, + input wire m_axi_pcis_wready, + input wire [5:0] m_axi_pcis_bid, + input wire [1:0] m_axi_pcis_bresp, + input wire m_axi_pcis_bvalid, + output wire m_axi_pcis_bready, + output wire [5:0] m_axi_pcis_arid, + output wire [63:0] m_axi_pcis_araddr, + output wire [7:0] m_axi_pcis_arlen, + output wire [2:0] m_axi_pcis_arsize, + output wire m_axi_pcis_arvalid, + input wire m_axi_pcis_arready, + input wire [5:0] m_axi_pcis_rid, + input wire [511:0] m_axi_pcis_rdata, + input wire [1:0] m_axi_pcis_rresp, + input wire m_axi_pcis_rlast, + input wire m_axi_pcis_rvalid, + output wire m_axi_pcis_rready, + output wire [1:0] m_axi_pcis_awburst, + output wire [1:0] m_axi_pcis_arburst, + + //-------------------------------- + // S_AXI_PCIM bus-interface ports (CL transactions to SH) + //-------------------------------- + input wire [15:0] s_axi_pcim_awid, + input wire [63:0] s_axi_pcim_awaddr, + input wire [7:0] s_axi_pcim_awlen, + input wire [2:0] s_axi_pcim_awsize, + input wire [18:0] s_axi_pcim_awuser, + input wire s_axi_pcim_awvalid, + output wire s_axi_pcim_awready, + input wire [511:0] s_axi_pcim_wdata, + input wire [63:0] s_axi_pcim_wstrb, + input wire s_axi_pcim_wlast, + input wire s_axi_pcim_wvalid, + output wire s_axi_pcim_wready, + output wire [15:0] s_axi_pcim_bid, + output wire [1:0] s_axi_pcim_bresp, + output wire s_axi_pcim_bvalid, + input wire s_axi_pcim_bready, + input wire [15:0] s_axi_pcim_arid, + input wire [63:0] s_axi_pcim_araddr, + input wire [7:0] s_axi_pcim_arlen, + input wire [2:0] s_axi_pcim_arsize, + input wire [18:0] s_axi_pcim_aruser, + input wire s_axi_pcim_arvalid, + output wire s_axi_pcim_arready, + output wire [15:0] s_axi_pcim_rid, + output wire [511:0] s_axi_pcim_rdata, + output wire [1:0] s_axi_pcim_rresp, + output wire s_axi_pcim_rlast, + output wire s_axi_pcim_rvalid, + input wire s_axi_pcim_rready, + + output wire [1:0] cfg_max_payload_out, //Max payload size - 00:128B, 01:256B, 10:512B + output wire [2:0] cfg_max_read_req_out //Max read requst size - 000b:128B, 001b:256B, 010b:512B, 011b:1024B + ); + + generate + + assign clk_main_a0_out = clk_main_a0 ; + assign clk_extra_a1_out = C_NUM_A_CLOCKS>1 ? clk_extra_a1 : 1'b0 ; + assign clk_extra_a2_out = C_NUM_A_CLOCKS>2 ? clk_extra_a2 : 1'b0 ; + assign clk_extra_a3_out = C_NUM_A_CLOCKS>3 ? clk_extra_a3 : 1'b0 ; + assign clk_extra_b0_out = C_NUM_B_CLOCKS>0 ? clk_extra_b0 : 1'b0 ; + assign clk_extra_b1_out = C_NUM_B_CLOCKS>1 ? clk_extra_b1 : 1'b0 ; + assign clk_extra_c0_out = C_NUM_C_CLOCKS>0 ? clk_extra_c0 : 1'b0 ; + assign clk_extra_c1_out = C_NUM_C_CLOCKS>1 ? clk_extra_c1 : 1'b0 ; + assign rst_main_n_out = rst_main_n ; + assign kernel_rst_n_out = kernel_rst_n ; + assign flr_assert = sh_cl_flr_assert ; + assign status_vdip = sh_cl_status_vdip ; + assign irq_ack = sh_cl_apppf_irq_ack ; + assign glcount0 = sh_cl_glcount0 ; + assign glcount1 = sh_cl_glcount1 ; + + assign cl_sh_flr_done = flr_done ; + assign cl_sh_status_vled = status_vled ; + assign cl_sh_apppf_irq_req = irq_req ; + + assign cl_sh_status0 = 0 ; + assign cl_sh_status1 = 0 ; + assign cl_sh_id0 = {C_DEVICE_ID, C_VENDOR_ID} ; + assign cl_sh_id1 = {C_SUBSYSTEM_ID, C_SUBSYSTEM_VENDOR_ID} ; + + assign cl_sh_dma_wr_full = 1'b0; + assign cl_sh_dma_rd_full = 1'b0; + + assign cl_sh_ddr_awid = s_axi_ddrc_awid ; + assign cl_sh_ddr_awaddr = s_axi_ddrc_awaddr ; + assign cl_sh_ddr_awlen = s_axi_ddrc_awlen ; + assign cl_sh_ddr_awsize = s_axi_ddrc_awsize ; + assign cl_sh_ddr_awburst = 2'b01 ; + assign cl_sh_ddr_awvalid = s_axi_ddrc_awvalid ; + assign cl_sh_ddr_wdata = s_axi_ddrc_wdata ; + assign cl_sh_ddr_wstrb = s_axi_ddrc_wstrb ; + assign cl_sh_ddr_wlast = s_axi_ddrc_wlast ; + assign cl_sh_ddr_wvalid = s_axi_ddrc_wvalid ; + assign cl_sh_ddr_bready = s_axi_ddrc_bready ; + assign cl_sh_ddr_arid = s_axi_ddrc_arid ; + assign cl_sh_ddr_araddr = s_axi_ddrc_araddr ; + assign cl_sh_ddr_arlen = s_axi_ddrc_arlen ; + assign cl_sh_ddr_arsize = s_axi_ddrc_arsize ; + assign cl_sh_ddr_arburst = 2'b01 ; + assign cl_sh_ddr_arvalid = s_axi_ddrc_arvalid ; + assign cl_sh_ddr_rready = s_axi_ddrc_rready ; + + assign s_axi_ddrc_awready = sh_cl_ddr_awready ; + assign s_axi_ddrc_wready = sh_cl_ddr_wready ; + assign s_axi_ddrc_bid = sh_cl_ddr_bid ; + assign s_axi_ddrc_bresp = sh_cl_ddr_bresp ; + assign s_axi_ddrc_bvalid = sh_cl_ddr_bvalid ; + assign s_axi_ddrc_arready = sh_cl_ddr_arready ; + assign s_axi_ddrc_rid = sh_cl_ddr_rid ; + assign s_axi_ddrc_rdata = sh_cl_ddr_rdata ; + assign s_axi_ddrc_rresp = sh_cl_ddr_rresp ; + assign s_axi_ddrc_rlast = sh_cl_ddr_rlast ; + assign s_axi_ddrc_rvalid = sh_cl_ddr_rvalid ; + assign ddrc_is_ready = sh_cl_ddr_is_ready ; + + assign cl_sh_ddr_wid = 0 ; + + assign cl_sda_awready = m_axi_sda_awready ; + assign cl_sda_wready = m_axi_sda_wready ; + assign cl_sda_bresp = m_axi_sda_bresp ; + assign cl_sda_bvalid = m_axi_sda_bvalid ; + assign cl_sda_arready = m_axi_sda_arready ; + assign cl_sda_rdata = m_axi_sda_rdata ; + assign cl_sda_rresp = m_axi_sda_rresp ; + assign cl_sda_rvalid = m_axi_sda_rvalid ; + + assign m_axi_sda_awaddr = sda_cl_awaddr ; + assign m_axi_sda_awvalid = sda_cl_awvalid ; + assign m_axi_sda_wdata = sda_cl_wdata ; + assign m_axi_sda_wstrb = sda_cl_wstrb ; + assign m_axi_sda_wvalid = sda_cl_wvalid ; + assign m_axi_sda_bready = sda_cl_bready ; + assign m_axi_sda_araddr = sda_cl_araddr ; + assign m_axi_sda_arvalid = sda_cl_arvalid ; + assign m_axi_sda_rready = sda_cl_rready ; + + assign ocl_sh_awready = m_axi_ocl_awready ; + assign ocl_sh_wready = m_axi_ocl_wready ; + assign ocl_sh_bresp = m_axi_ocl_bresp ; + assign ocl_sh_bvalid = m_axi_ocl_bvalid ; + assign ocl_sh_arready = m_axi_ocl_arready ; + assign ocl_sh_rdata = m_axi_ocl_rdata ; + assign ocl_sh_rresp = m_axi_ocl_rresp ; + assign ocl_sh_rvalid = m_axi_ocl_rvalid ; + + assign m_axi_ocl_awaddr = sh_ocl_awaddr ; + assign m_axi_ocl_awvalid = sh_ocl_awvalid ; + assign m_axi_ocl_wdata = sh_ocl_wdata ; + assign m_axi_ocl_wstrb = sh_ocl_wstrb ; + assign m_axi_ocl_wvalid = sh_ocl_wvalid ; + assign m_axi_ocl_bready = sh_ocl_bready ; + assign m_axi_ocl_araddr = sh_ocl_araddr ; + assign m_axi_ocl_arvalid = sh_ocl_arvalid ; + assign m_axi_ocl_rready = sh_ocl_rready ; + + assign bar1_sh_awready = m_axi_bar1_awready ; + assign bar1_sh_wready = m_axi_bar1_wready ; + assign bar1_sh_bresp = m_axi_bar1_bresp ; + assign bar1_sh_bvalid = m_axi_bar1_bvalid ; + assign bar1_sh_arready = m_axi_bar1_arready ; + assign bar1_sh_rdata = m_axi_bar1_rdata ; + assign bar1_sh_rresp = m_axi_bar1_rresp ; + assign bar1_sh_rvalid = m_axi_bar1_rvalid ; + + assign m_axi_bar1_awaddr = sh_bar1_awaddr ; + assign m_axi_bar1_awvalid = sh_bar1_awvalid ; + assign m_axi_bar1_wdata = sh_bar1_wdata ; + assign m_axi_bar1_wstrb = sh_bar1_wstrb ; + assign m_axi_bar1_wvalid = sh_bar1_wvalid ; + assign m_axi_bar1_bready = sh_bar1_bready ; + assign m_axi_bar1_araddr = sh_bar1_araddr ; + assign m_axi_bar1_arvalid = sh_bar1_arvalid ; + assign m_axi_bar1_rready = sh_bar1_rready ; + + assign cl_sh_dma_pcis_awready = m_axi_pcis_awready ; + assign cl_sh_dma_pcis_wready = m_axi_pcis_wready ; + assign cl_sh_dma_pcis_bid = m_axi_pcis_bid ; + assign cl_sh_dma_pcis_bresp = m_axi_pcis_bresp ; + assign cl_sh_dma_pcis_bvalid = m_axi_pcis_bvalid ; + assign cl_sh_dma_pcis_arready = m_axi_pcis_arready ; + assign cl_sh_dma_pcis_rid = m_axi_pcis_rid ; + assign cl_sh_dma_pcis_rdata = m_axi_pcis_rdata ; + assign cl_sh_dma_pcis_rresp = m_axi_pcis_rresp ; + assign cl_sh_dma_pcis_rlast = m_axi_pcis_rlast ; + assign cl_sh_dma_pcis_rvalid = m_axi_pcis_rvalid ; + + assign m_axi_pcis_awid = sh_cl_dma_pcis_awid ; + assign m_axi_pcis_awaddr = sh_cl_dma_pcis_awaddr ; + assign m_axi_pcis_awlen = sh_cl_dma_pcis_awlen ; + assign m_axi_pcis_awsize = sh_cl_dma_pcis_awsize ; + assign m_axi_pcis_awvalid = sh_cl_dma_pcis_awvalid ; + assign m_axi_pcis_wdata = sh_cl_dma_pcis_wdata ; + assign m_axi_pcis_wstrb = sh_cl_dma_pcis_wstrb ; + assign m_axi_pcis_wlast = sh_cl_dma_pcis_wlast ; + assign m_axi_pcis_wvalid = sh_cl_dma_pcis_wvalid ; + assign m_axi_pcis_bready = sh_cl_dma_pcis_bready ; + assign m_axi_pcis_arid = sh_cl_dma_pcis_arid ; + assign m_axi_pcis_araddr = sh_cl_dma_pcis_araddr ; + assign m_axi_pcis_arlen = sh_cl_dma_pcis_arlen ; + assign m_axi_pcis_arsize = sh_cl_dma_pcis_arsize ; + assign m_axi_pcis_arvalid = sh_cl_dma_pcis_arvalid ; + assign m_axi_pcis_rready = sh_cl_dma_pcis_rready ; + assign m_axi_pcis_awburst = 2'b01 ; + assign m_axi_pcis_arburst = 2'b01 ; + + assign cl_sh_pcim_awid = s_axi_pcim_awid ; + assign cl_sh_pcim_awaddr = s_axi_pcim_awaddr ; + assign cl_sh_pcim_awlen = s_axi_pcim_awlen ; + assign cl_sh_pcim_awsize = s_axi_pcim_awsize ; + assign cl_sh_pcim_awuser = s_axi_pcim_awuser ; + assign cl_sh_pcim_awvalid = s_axi_pcim_awvalid ; + assign cl_sh_pcim_wdata = s_axi_pcim_wdata ; + assign cl_sh_pcim_wstrb = s_axi_pcim_wstrb ; + assign cl_sh_pcim_wlast = s_axi_pcim_wlast ; + assign cl_sh_pcim_wvalid = s_axi_pcim_wvalid ; + assign cl_sh_pcim_bready = s_axi_pcim_bready ; + assign cl_sh_pcim_arid = s_axi_pcim_arid ; + assign cl_sh_pcim_araddr = s_axi_pcim_araddr ; + assign cl_sh_pcim_arlen = s_axi_pcim_arlen ; + assign cl_sh_pcim_arsize = s_axi_pcim_arsize ; + assign cl_sh_pcim_aruser = s_axi_pcim_aruser ; + assign cl_sh_pcim_arvalid = s_axi_pcim_arvalid ; + assign cl_sh_pcim_rready = s_axi_pcim_rready ; + + assign s_axi_pcim_awready = sh_cl_pcim_awready ; + assign s_axi_pcim_wready = sh_cl_pcim_wready ; + assign s_axi_pcim_bid = sh_cl_pcim_bid ; + assign s_axi_pcim_bresp = sh_cl_pcim_bresp ; + assign s_axi_pcim_bvalid = sh_cl_pcim_bvalid ; + assign s_axi_pcim_arready = sh_cl_pcim_arready ; + assign s_axi_pcim_rid = sh_cl_pcim_rid ; + assign s_axi_pcim_rdata = sh_cl_pcim_rdata ; + assign s_axi_pcim_rresp = sh_cl_pcim_rresp ; + assign s_axi_pcim_rlast = sh_cl_pcim_rlast ; + assign s_axi_pcim_rvalid = sh_cl_pcim_rvalid ; + assign cfg_max_payload_out = cfg_max_payload ; + assign cfg_max_read_req_out = cfg_max_read_req ; + + if ((C_MODE == 0) || (C_MODE == 1)) begin : gen_mem + + logic [15:0] cl_sh_ddr_awid_2d[2:0]; + logic [63:0] cl_sh_ddr_awaddr_2d[2:0]; + logic [7:0] cl_sh_ddr_awlen_2d[2:0]; + logic [2:0] cl_sh_ddr_awsize_2d[2:0]; + logic [1:0] cl_sh_ddr_awburst_2d[2:0]; + logic cl_sh_ddr_awvalid_2d[2:0]; + logic [2:0] sh_cl_ddr_awready_2d; + logic [15:0] cl_sh_ddr_wid_2d[2:0]; + logic [511:0] cl_sh_ddr_wdata_2d[2:0]; + logic [63:0] cl_sh_ddr_wstrb_2d[2:0]; + logic [2:0] cl_sh_ddr_wlast_2d; + logic [2:0] cl_sh_ddr_wvalid_2d; + logic [2:0] sh_cl_ddr_wready_2d; + logic [15:0] sh_cl_ddr_bid_2d[2:0]; + logic [1:0] sh_cl_ddr_bresp_2d[2:0]; + logic [2:0] sh_cl_ddr_bvalid_2d; + logic [2:0] cl_sh_ddr_bready_2d; + logic [15:0] cl_sh_ddr_arid_2d[2:0]; + logic [63:0] cl_sh_ddr_araddr_2d[2:0]; + logic [7:0] cl_sh_ddr_arlen_2d[2:0]; + logic [2:0] cl_sh_ddr_arsize_2d[2:0]; + logic [1:0] cl_sh_ddr_arburst_2d[2:0]; + logic [2:0] cl_sh_ddr_arvalid_2d; + logic [2:0] sh_cl_ddr_arready_2d; + logic [15:0] sh_cl_ddr_rid_2d[2:0]; + logic [511:0] sh_cl_ddr_rdata_2d[2:0]; + logic [1:0] sh_cl_ddr_rresp_2d[2:0]; + logic [2:0] sh_cl_ddr_rlast_2d; + logic [2:0] sh_cl_ddr_rvalid_2d; + logic [2:0] cl_sh_ddr_rready_2d; + logic [2:0] sh_cl_ddr_is_ready_2d; + + assign cl_sh_ddr_awid_2d[0] = s_axi_ddra_awid ; + assign cl_sh_ddr_awaddr_2d[0] = s_axi_ddra_awaddr ; + assign cl_sh_ddr_awlen_2d[0] = s_axi_ddra_awlen ; + assign cl_sh_ddr_awsize_2d[0] = s_axi_ddra_awsize ; + assign cl_sh_ddr_awburst_2d[0] = 2'b01 ; + assign cl_sh_ddr_awvalid_2d[0] = s_axi_ddra_awvalid ; + assign cl_sh_ddr_wid_2d[0] = 0 ; + assign cl_sh_ddr_wdata_2d[0] = s_axi_ddra_wdata ; + assign cl_sh_ddr_wstrb_2d[0] = s_axi_ddra_wstrb ; + assign cl_sh_ddr_wlast_2d[0] = s_axi_ddra_wlast ; + assign cl_sh_ddr_wvalid_2d[0] = s_axi_ddra_wvalid ; + assign cl_sh_ddr_bready_2d[0] = s_axi_ddra_bready ; + assign cl_sh_ddr_arid_2d[0] = s_axi_ddra_arid ; + assign cl_sh_ddr_araddr_2d[0] = s_axi_ddra_araddr ; + assign cl_sh_ddr_arlen_2d[0] = s_axi_ddra_arlen ; + assign cl_sh_ddr_arsize_2d[0] = s_axi_ddra_arsize ; + assign cl_sh_ddr_arburst_2d[0] = 2'b01 ; + assign cl_sh_ddr_arvalid_2d[0] = s_axi_ddra_arvalid ; + assign cl_sh_ddr_rready_2d[0] = s_axi_ddra_rready ; + + assign s_axi_ddra_awready = sh_cl_ddr_awready_2d[0] ; + assign s_axi_ddra_wready = sh_cl_ddr_wready_2d[0] ; + assign s_axi_ddra_bid = sh_cl_ddr_bid_2d[0] ; + assign s_axi_ddra_bresp = sh_cl_ddr_bresp_2d[0] ; + assign s_axi_ddra_bvalid = sh_cl_ddr_bvalid_2d[0] ; + assign s_axi_ddra_arready = sh_cl_ddr_arready_2d[0] ; + assign s_axi_ddra_rid = sh_cl_ddr_rid_2d[0] ; + assign s_axi_ddra_rdata = sh_cl_ddr_rdata_2d[0] ; + assign s_axi_ddra_rresp = sh_cl_ddr_rresp_2d[0] ; + assign s_axi_ddra_rlast = sh_cl_ddr_rlast_2d[0] ; + assign s_axi_ddra_rvalid = sh_cl_ddr_rvalid_2d[0] ; + assign ddra_is_ready = sh_cl_ddr_is_ready_2d[0]; + + assign cl_sh_ddr_awid_2d[1] = s_axi_ddrb_awid ; + assign cl_sh_ddr_awaddr_2d[1] = s_axi_ddrb_awaddr ; + assign cl_sh_ddr_awlen_2d[1] = s_axi_ddrb_awlen ; + assign cl_sh_ddr_awsize_2d[1] = s_axi_ddrb_awsize ; + assign cl_sh_ddr_awburst_2d[1] = 2'b01 ; + assign cl_sh_ddr_awvalid_2d[1] = s_axi_ddrb_awvalid ; + assign cl_sh_ddr_wid_2d[1] = 0 ; + assign cl_sh_ddr_wdata_2d[1] = s_axi_ddrb_wdata ; + assign cl_sh_ddr_wstrb_2d[1] = s_axi_ddrb_wstrb ; + assign cl_sh_ddr_wlast_2d[1] = s_axi_ddrb_wlast ; + assign cl_sh_ddr_wvalid_2d[1] = s_axi_ddrb_wvalid ; + assign cl_sh_ddr_bready_2d[1] = s_axi_ddrb_bready ; + assign cl_sh_ddr_arid_2d[1] = s_axi_ddrb_arid ; + assign cl_sh_ddr_araddr_2d[1] = s_axi_ddrb_araddr ; + assign cl_sh_ddr_arlen_2d[1] = s_axi_ddrb_arlen ; + assign cl_sh_ddr_arsize_2d[1] = s_axi_ddrb_arsize ; + assign cl_sh_ddr_arburst_2d[1] = 2'b01 ; + assign cl_sh_ddr_arvalid_2d[1] = s_axi_ddrb_arvalid ; + assign cl_sh_ddr_rready_2d[1] = s_axi_ddrb_rready ; + + assign s_axi_ddrb_awready = sh_cl_ddr_awready_2d[1] ; + assign s_axi_ddrb_wready = sh_cl_ddr_wready_2d[1] ; + assign s_axi_ddrb_bid = sh_cl_ddr_bid_2d[1] ; + assign s_axi_ddrb_bresp = sh_cl_ddr_bresp_2d[1] ; + assign s_axi_ddrb_bvalid = sh_cl_ddr_bvalid_2d[1] ; + assign s_axi_ddrb_arready = sh_cl_ddr_arready_2d[1] ; + assign s_axi_ddrb_rid = sh_cl_ddr_rid_2d[1] ; + assign s_axi_ddrb_rdata = sh_cl_ddr_rdata_2d[1] ; + assign s_axi_ddrb_rresp = sh_cl_ddr_rresp_2d[1] ; + assign s_axi_ddrb_rlast = sh_cl_ddr_rlast_2d[1] ; + assign s_axi_ddrb_rvalid = sh_cl_ddr_rvalid_2d[1] ; + assign ddrb_is_ready = sh_cl_ddr_is_ready_2d[1]; + + assign cl_sh_ddr_awid_2d[2] = s_axi_ddrd_awid ; + assign cl_sh_ddr_awaddr_2d[2] = s_axi_ddrd_awaddr ; + assign cl_sh_ddr_awlen_2d[2] = s_axi_ddrd_awlen ; + assign cl_sh_ddr_awsize_2d[2] = s_axi_ddrd_awsize ; + assign cl_sh_ddr_awburst_2d[2] = 2'b01 ; + assign cl_sh_ddr_awvalid_2d[2] = s_axi_ddrd_awvalid ; + assign cl_sh_ddr_wid_2d[2] = 0 ; + assign cl_sh_ddr_wdata_2d[2] = s_axi_ddrd_wdata ; + assign cl_sh_ddr_wstrb_2d[2] = s_axi_ddrd_wstrb ; + assign cl_sh_ddr_wlast_2d[2] = s_axi_ddrd_wlast ; + assign cl_sh_ddr_wvalid_2d[2] = s_axi_ddrd_wvalid ; + assign cl_sh_ddr_bready_2d[2] = s_axi_ddrd_bready ; + assign cl_sh_ddr_arid_2d[2] = s_axi_ddrd_arid ; + assign cl_sh_ddr_araddr_2d[2] = s_axi_ddrd_araddr ; + assign cl_sh_ddr_arlen_2d[2] = s_axi_ddrd_arlen ; + assign cl_sh_ddr_arsize_2d[2] = s_axi_ddrd_arsize ; + assign cl_sh_ddr_arburst_2d[2] = 2'b01 ; + assign cl_sh_ddr_arvalid_2d[2] = s_axi_ddrd_arvalid ; + assign cl_sh_ddr_rready_2d[2] = s_axi_ddrd_rready ; + + assign s_axi_ddrd_awready = sh_cl_ddr_awready_2d[2] ; + assign s_axi_ddrd_wready = sh_cl_ddr_wready_2d[2] ; + assign s_axi_ddrd_bid = sh_cl_ddr_bid_2d[2] ; + assign s_axi_ddrd_bresp = sh_cl_ddr_bresp_2d[2] ; + assign s_axi_ddrd_bvalid = sh_cl_ddr_bvalid_2d[2] ; + assign s_axi_ddrd_arready = sh_cl_ddr_arready_2d[2] ; + assign s_axi_ddrd_rid = sh_cl_ddr_rid_2d[2] ; + assign s_axi_ddrd_rdata = sh_cl_ddr_rdata_2d[2] ; + assign s_axi_ddrd_rresp = sh_cl_ddr_rresp_2d[2] ; + assign s_axi_ddrd_rlast = sh_cl_ddr_rlast_2d[2] ; + assign s_axi_ddrd_rvalid = sh_cl_ddr_rvalid_2d[2] ; + assign ddrd_is_ready = sh_cl_ddr_is_ready_2d[2]; + + logic ddr_aws_stat_ack0; + logic [31:0] ddr_aws_stat_rdata0; + logic [7:0] ddr_aws_stat_int0; + logic ddr_aws_stat_ack1; + logic [31:0] ddr_aws_stat_rdata1; + logic [7:0] ddr_aws_stat_int1; + logic ddr_aws_stat_ack2; + logic [31:0] ddr_aws_stat_rdata2; + logic [7:0] ddr_aws_stat_int2; + + logic [7:0] pipe_ddr_stat_addr0; + logic pipe_ddr_stat_wr0; + logic pipe_ddr_stat_rd0; + logic [31:0] pipe_ddr_stat_wdata0; + logic ddr_pipe_stat_ack0; + logic [31:0] ddr_pipe_stat_rdata0; + logic [7:0] ddr_pipe_stat_int0; + + logic [7:0] pipe_ddr_stat_addr1; + logic pipe_ddr_stat_wr1; + logic pipe_ddr_stat_rd1; + logic [31:0] pipe_ddr_stat_wdata1; + logic ddr_pipe_stat_ack1; + logic [31:0] ddr_pipe_stat_rdata1; + logic [7:0] ddr_pipe_stat_int1; + + logic [7:0] pipe_ddr_stat_addr2; + logic pipe_ddr_stat_wr2; + logic pipe_ddr_stat_rd2; + logic [31:0] pipe_ddr_stat_wdata2; + logic ddr_pipe_stat_ack2; + logic [31:0] ddr_pipe_stat_rdata2; + logic [7:0] ddr_pipe_stat_int2; + +//------------------------------------------------- +// Tie-offs when DDRs are disabled +//------------------------------------------------- + assign ddr_sh_stat_ack0 = (C_DDR_A_PRESENT!=0) ? ddr_aws_stat_ack0 : 1'b1; + assign ddr_sh_stat_rdata0 = (C_DDR_A_PRESENT!=0) ? ddr_aws_stat_rdata0 : 0; + assign ddr_sh_stat_int0 = (C_DDR_A_PRESENT!=0) ? ddr_aws_stat_int0 : 8'b0; + assign ddr_sh_stat_ack1 = (C_DDR_B_PRESENT!=0) ? ddr_aws_stat_ack1 : 1'b1; + assign ddr_sh_stat_rdata1 = (C_DDR_B_PRESENT!=0) ? ddr_aws_stat_rdata1 : 0; + assign ddr_sh_stat_int1 = (C_DDR_B_PRESENT!=0) ? ddr_aws_stat_int1 : 8'b0; + assign ddr_sh_stat_ack2 = (C_DDR_D_PRESENT!=0) ? ddr_aws_stat_ack2 : 1'b1; + assign ddr_sh_stat_rdata2 = (C_DDR_D_PRESENT!=0) ? ddr_aws_stat_rdata2 : 0; + assign ddr_sh_stat_int2 = (C_DDR_D_PRESENT!=0) ? ddr_aws_stat_int2 : 8'b0; + +//------------------------------------------------- +// Reset Synchronization +//------------------------------------------------- + logic pre_sync_rst_n; + logic sync_rst_n; + + always @(negedge rst_main_n or posedge clk_main_a0) begin + if (!rst_main_n) begin + pre_sync_rst_n <= 1'b0; + sync_rst_n <= 1'b0; + end else begin + pre_sync_rst_n <= 1'b1; + sync_rst_n <= pre_sync_rst_n; + end + end + + `ifdef FPGA_LESS_RST + `undef FPGA_LESS_RST + `endif + + lib_pipe #(.WIDTH(32), .STAGES(C_NUM_STAGES_STATS)) pipe_stat_wdata0 (.clk(clk_main_a0), .rst_n(1'b1), .in_bus(sh_ddr_stat_wdata0), .out_bus(pipe_ddr_stat_wdata0)); + lib_pipe #(.WIDTH(8), .STAGES(C_NUM_STAGES_STATS)) pipe_stat_addr0 (.clk(clk_main_a0), .rst_n(1'b1), .in_bus(sh_ddr_stat_addr0), .out_bus(pipe_ddr_stat_addr0)); + lib_pipe #(.WIDTH(1), .STAGES(C_NUM_STAGES_STATS)) pipe_stat_wr0 (.clk(clk_main_a0), .rst_n(sync_rst_n), .in_bus(sh_ddr_stat_wr0), .out_bus(pipe_ddr_stat_wr0)); + lib_pipe #(.WIDTH(1), .STAGES(C_NUM_STAGES_STATS)) pipe_stat_rd0 (.clk(clk_main_a0), .rst_n(sync_rst_n), .in_bus(sh_ddr_stat_rd0), .out_bus(pipe_ddr_stat_rd0)); + lib_pipe #(.WIDTH(32), .STAGES(C_NUM_STAGES_STATS)) pipe_stat_rdata0 (.clk(clk_main_a0), .rst_n(1'b1), .out_bus(ddr_aws_stat_rdata0), .in_bus(ddr_pipe_stat_rdata0)); + lib_pipe #(.WIDTH(1), .STAGES(C_NUM_STAGES_STATS)) pipe_stat_ack0 (.clk(clk_main_a0), .rst_n(sync_rst_n), .out_bus(ddr_aws_stat_ack0), .in_bus(ddr_pipe_stat_ack0)); + lib_pipe #(.WIDTH(8), .STAGES(C_NUM_STAGES_STATS)) pipe_stat_int0 (.clk(clk_main_a0), .rst_n(sync_rst_n), .out_bus(ddr_aws_stat_int0), .in_bus(ddr_pipe_stat_int0)); + + lib_pipe #(.WIDTH(32), .STAGES(C_NUM_STAGES_STATS)) pipe_stat_wdata1 (.clk(clk_main_a0), .rst_n(1'b1), .in_bus(sh_ddr_stat_wdata1), .out_bus(pipe_ddr_stat_wdata1)); + lib_pipe #(.WIDTH(8), .STAGES(C_NUM_STAGES_STATS)) pipe_stat_addr1 (.clk(clk_main_a0), .rst_n(1'b1), .in_bus(sh_ddr_stat_addr1), .out_bus(pipe_ddr_stat_addr1)); + lib_pipe #(.WIDTH(1), .STAGES(C_NUM_STAGES_STATS)) pipe_stat_wr1 (.clk(clk_main_a0), .rst_n(sync_rst_n), .in_bus(sh_ddr_stat_wr1), .out_bus(pipe_ddr_stat_wr1)); + lib_pipe #(.WIDTH(1), .STAGES(C_NUM_STAGES_STATS)) pipe_stat_rd1 (.clk(clk_main_a0), .rst_n(sync_rst_n), .in_bus(sh_ddr_stat_rd1), .out_bus(pipe_ddr_stat_rd1)); + lib_pipe #(.WIDTH(32), .STAGES(C_NUM_STAGES_STATS)) pipe_stat_rdata1 (.clk(clk_main_a0), .rst_n(1'b1), .out_bus(ddr_aws_stat_rdata1), .in_bus(ddr_pipe_stat_rdata1)); + lib_pipe #(.WIDTH(1), .STAGES(C_NUM_STAGES_STATS)) pipe_stat_ack1 (.clk(clk_main_a0), .rst_n(sync_rst_n), .out_bus(ddr_aws_stat_ack1), .in_bus(ddr_pipe_stat_ack1)); + lib_pipe #(.WIDTH(8), .STAGES(C_NUM_STAGES_STATS)) pipe_stat_int1 (.clk(clk_main_a0), .rst_n(sync_rst_n), .out_bus(ddr_aws_stat_int1), .in_bus(ddr_pipe_stat_int1)); + + lib_pipe #(.WIDTH(32), .STAGES(C_NUM_STAGES_STATS)) pipe_stat_wdata2 (.clk(clk_main_a0), .rst_n(1'b1), .in_bus(sh_ddr_stat_wdata2), .out_bus(pipe_ddr_stat_wdata2)); + lib_pipe #(.WIDTH(8), .STAGES(C_NUM_STAGES_STATS)) pipe_stat_addr2 (.clk(clk_main_a0), .rst_n(1'b1), .in_bus(sh_ddr_stat_addr2), .out_bus(pipe_ddr_stat_addr2)); + lib_pipe #(.WIDTH(1), .STAGES(C_NUM_STAGES_STATS)) pipe_stat_wr2 (.clk(clk_main_a0), .rst_n(sync_rst_n), .in_bus(sh_ddr_stat_wr2), .out_bus(pipe_ddr_stat_wr2)); + lib_pipe #(.WIDTH(1), .STAGES(C_NUM_STAGES_STATS)) pipe_stat_rd2 (.clk(clk_main_a0), .rst_n(sync_rst_n), .in_bus(sh_ddr_stat_rd2), .out_bus(pipe_ddr_stat_rd2)); + lib_pipe #(.WIDTH(32), .STAGES(C_NUM_STAGES_STATS)) pipe_stat_rdata2 (.clk(clk_main_a0), .rst_n(1'b1), .out_bus(ddr_aws_stat_rdata2), .in_bus(ddr_pipe_stat_rdata2)); + lib_pipe #(.WIDTH(1), .STAGES(C_NUM_STAGES_STATS)) pipe_stat_ack2 (.clk(clk_main_a0), .rst_n(sync_rst_n), .out_bus(ddr_aws_stat_ack2), .in_bus(ddr_pipe_stat_ack2)); + lib_pipe #(.WIDTH(8), .STAGES(C_NUM_STAGES_STATS)) pipe_stat_int2 (.clk(clk_main_a0), .rst_n(sync_rst_n), .out_bus(ddr_aws_stat_int2), .in_bus(ddr_pipe_stat_int2)); + + sh_ddr #( + .DDR_A_PRESENT(C_DDR_A_PRESENT), + .DDR_B_PRESENT(C_DDR_B_PRESENT), + .DDR_D_PRESENT(C_DDR_D_PRESENT) + ) sh_ddr_0 + ( + .clk(clk_main_a0), + .rst_n(sync_rst_n), + + .stat_clk(clk_main_a0), + .stat_rst_n(sync_rst_n), + + .CLK_300M_DIMM0_DP(CLK_300M_DIMM0_DP), + .CLK_300M_DIMM0_DN(CLK_300M_DIMM0_DN), + .M_A_ACT_N(M_A_ACT_N), + .M_A_MA(M_A_MA), + .M_A_BA(M_A_BA), + .M_A_BG(M_A_BG), + .M_A_CKE(M_A_CKE), + .M_A_ODT(M_A_ODT), + .M_A_CS_N(M_A_CS_N), + .M_A_CLK_DN(M_A_CLK_DN), + .M_A_CLK_DP(M_A_CLK_DP), + .M_A_PAR(M_A_PAR), + .M_A_DQ(M_A_DQ), + .M_A_ECC(M_A_ECC), + .M_A_DQS_DP(M_A_DQS_DP), + .M_A_DQS_DN(M_A_DQS_DN), + .cl_RST_DIMM_A_N(cl_RST_DIMM_A_N), + + .CLK_300M_DIMM1_DP(CLK_300M_DIMM1_DP), + .CLK_300M_DIMM1_DN(CLK_300M_DIMM1_DN), + .M_B_ACT_N(M_B_ACT_N), + .M_B_MA(M_B_MA), + .M_B_BA(M_B_BA), + .M_B_BG(M_B_BG), + .M_B_CKE(M_B_CKE), + .M_B_ODT(M_B_ODT), + .M_B_CS_N(M_B_CS_N), + .M_B_CLK_DN(M_B_CLK_DN), + .M_B_CLK_DP(M_B_CLK_DP), + .M_B_PAR(M_B_PAR), + .M_B_DQ(M_B_DQ), + .M_B_ECC(M_B_ECC), + .M_B_DQS_DP(M_B_DQS_DP), + .M_B_DQS_DN(M_B_DQS_DN), + .cl_RST_DIMM_B_N(cl_RST_DIMM_B_N), + + .CLK_300M_DIMM3_DP(CLK_300M_DIMM3_DP), + .CLK_300M_DIMM3_DN(CLK_300M_DIMM3_DN), + .M_D_ACT_N(M_D_ACT_N), + .M_D_MA(M_D_MA), + .M_D_BA(M_D_BA), + .M_D_BG(M_D_BG), + .M_D_CKE(M_D_CKE), + .M_D_ODT(M_D_ODT), + .M_D_CS_N(M_D_CS_N), + .M_D_CLK_DN(M_D_CLK_DN), + .M_D_CLK_DP(M_D_CLK_DP), + .M_D_PAR(M_D_PAR), + .M_D_DQ(M_D_DQ), + .M_D_ECC(M_D_ECC), + .M_D_DQS_DP(M_D_DQS_DP), + .M_D_DQS_DN(M_D_DQS_DN), + .cl_RST_DIMM_D_N(cl_RST_DIMM_D_N), + + //------------------------------------------------------ + // AXI Slave Interfaces + //------------------------------------------------------ + .cl_sh_ddr_awid(cl_sh_ddr_awid_2d), + .cl_sh_ddr_awaddr(cl_sh_ddr_awaddr_2d), + .cl_sh_ddr_awlen(cl_sh_ddr_awlen_2d), + .cl_sh_ddr_awsize(cl_sh_ddr_awsize_2d), + .cl_sh_ddr_awburst(cl_sh_ddr_awburst_2d), + .cl_sh_ddr_awvalid(cl_sh_ddr_awvalid_2d), + .sh_cl_ddr_awready(sh_cl_ddr_awready_2d), + + .cl_sh_ddr_wid(cl_sh_ddr_wid_2d), + .cl_sh_ddr_wdata(cl_sh_ddr_wdata_2d), + .cl_sh_ddr_wstrb(cl_sh_ddr_wstrb_2d), + .cl_sh_ddr_wlast(cl_sh_ddr_wlast_2d), + .cl_sh_ddr_wvalid(cl_sh_ddr_wvalid_2d), + .sh_cl_ddr_wready(sh_cl_ddr_wready_2d), + + .sh_cl_ddr_bid(sh_cl_ddr_bid_2d), + .sh_cl_ddr_bresp(sh_cl_ddr_bresp_2d), + .sh_cl_ddr_bvalid(sh_cl_ddr_bvalid_2d), + .cl_sh_ddr_bready(cl_sh_ddr_bready_2d), + + .cl_sh_ddr_arid(cl_sh_ddr_arid_2d), + .cl_sh_ddr_araddr(cl_sh_ddr_araddr_2d), + .cl_sh_ddr_arlen(cl_sh_ddr_arlen_2d), + .cl_sh_ddr_arsize(cl_sh_ddr_arsize_2d), + .cl_sh_ddr_arburst(cl_sh_ddr_arburst_2d), + .cl_sh_ddr_arvalid(cl_sh_ddr_arvalid_2d), + .sh_cl_ddr_arready(sh_cl_ddr_arready_2d), + + .sh_cl_ddr_rid(sh_cl_ddr_rid_2d), + .sh_cl_ddr_rdata(sh_cl_ddr_rdata_2d), + .sh_cl_ddr_rresp(sh_cl_ddr_rresp_2d), + .sh_cl_ddr_rlast(sh_cl_ddr_rlast_2d), + .sh_cl_ddr_rvalid(sh_cl_ddr_rvalid_2d), + .cl_sh_ddr_rready(cl_sh_ddr_rready_2d), + + .sh_cl_ddr_is_ready(sh_cl_ddr_is_ready_2d), + + .sh_ddr_stat_addr0 (pipe_ddr_stat_addr0 ), + .sh_ddr_stat_wr0 (pipe_ddr_stat_wr0 ), + .sh_ddr_stat_rd0 (pipe_ddr_stat_rd0 ), + .sh_ddr_stat_wdata0 (pipe_ddr_stat_wdata0), + .ddr_sh_stat_ack0 (ddr_pipe_stat_ack0 ), + .ddr_sh_stat_rdata0 (ddr_pipe_stat_rdata0), + .ddr_sh_stat_int0 (ddr_pipe_stat_int0 ), + + .sh_ddr_stat_addr1 (pipe_ddr_stat_addr1 ), + .sh_ddr_stat_wr1 (pipe_ddr_stat_wr1 ), + .sh_ddr_stat_rd1 (pipe_ddr_stat_rd1 ), + .sh_ddr_stat_wdata1 (pipe_ddr_stat_wdata1), + .ddr_sh_stat_ack1 (ddr_pipe_stat_ack1 ), + .ddr_sh_stat_rdata1 (ddr_pipe_stat_rdata1), + .ddr_sh_stat_int1 (ddr_pipe_stat_int1 ), + + .sh_ddr_stat_addr2 (pipe_ddr_stat_addr2 ), + .sh_ddr_stat_wr2 (pipe_ddr_stat_wr2 ), + .sh_ddr_stat_rd2 (pipe_ddr_stat_rd2 ), + .sh_ddr_stat_wdata2 (pipe_ddr_stat_wdata2), + .ddr_sh_stat_ack2 (ddr_pipe_stat_ack2 ), + .ddr_sh_stat_rdata2 (ddr_pipe_stat_rdata2), + .ddr_sh_stat_int2 (ddr_pipe_stat_int2 ) + + ); + + end else begin : gen_non_mem + + assign s_axi_ddra_awready = 0; + assign s_axi_ddra_wready = 0; + assign s_axi_ddra_bid = 0; + assign s_axi_ddra_bresp = 0; + assign s_axi_ddra_bvalid = 0; + assign s_axi_ddra_arready = 0; + assign s_axi_ddra_rid = 0; + assign s_axi_ddra_rdata = 0; + assign s_axi_ddra_rresp = 0; + assign s_axi_ddra_rlast = 1'b1; + assign s_axi_ddra_rvalid = 0; + assign ddra_is_ready = 0; + + assign s_axi_ddrb_awready = 0; + assign s_axi_ddrb_wready = 0; + assign s_axi_ddrb_bid = 0; + assign s_axi_ddrb_bresp = 0; + assign s_axi_ddrb_bvalid = 0; + assign s_axi_ddrb_arready = 0; + assign s_axi_ddrb_rid = 0; + assign s_axi_ddrb_rdata = 0; + assign s_axi_ddrb_rresp = 0; + assign s_axi_ddrb_rlast = 1'b1; + assign s_axi_ddrb_rvalid = 0; + assign ddrb_is_ready = 0; + + assign s_axi_ddrd_awready = 0; + assign s_axi_ddrd_wready = 0; + assign s_axi_ddrd_bid = 0; + assign s_axi_ddrd_bresp = 0; + assign s_axi_ddrd_bvalid = 0; + assign s_axi_ddrd_arready = 0; + assign s_axi_ddrd_rid = 0; + assign s_axi_ddrd_rdata = 0; + assign s_axi_ddrd_rresp = 0; + assign s_axi_ddrd_rlast = 1'b1; + assign s_axi_ddrd_rvalid = 0; + assign ddrd_is_ready = 0; + + assign ddr_sh_stat_ack0 = 1'b1; + assign ddr_sh_stat_rdata0 = 0; + assign ddr_sh_stat_int0 = 8'b0; + assign ddr_sh_stat_ack1 = 1'b1; + assign ddr_sh_stat_rdata1 = 0; + assign ddr_sh_stat_int1 = 8'b0; + assign ddr_sh_stat_ack2 = 1'b1; + assign ddr_sh_stat_rdata2 = 0; + assign ddr_sh_stat_int2 = 8'b0; + + assign M_A_ACT_N = 0; + assign M_A_MA = 0; + assign M_A_BA = 0; + assign M_A_BG = 0; + assign M_A_CKE = 0; + assign M_A_ODT = 0; + assign M_A_CS_N = 0; + assign M_A_CLK_DN = 0; + assign M_A_CLK_DP = 0; + assign M_A_PAR = 0; + assign cl_RST_DIMM_A_N = 0; + + assign M_B_ACT_N = 0; + assign M_B_MA = 0; + assign M_B_BA = 0; + assign M_B_BG = 0; + assign M_B_CKE = 0; + assign M_B_ODT = 0; + assign M_B_CS_N = 0; + assign M_B_CLK_DN = 0; + assign M_B_CLK_DP = 0; + assign M_B_PAR = 0; + assign cl_RST_DIMM_B_N = 0; + + assign M_D_ACT_N = 0; + assign M_D_MA = 0; + assign M_D_BA = 0; + assign M_D_BG = 0; + assign M_D_CKE = 0; + assign M_D_ODT = 0; + assign M_D_CS_N = 0; + assign M_D_CLK_DN = 0; + assign M_D_CLK_DP = 0; + assign M_D_PAR = 0; + assign cl_RST_DIMM_D_N = 0; + + end // gen_mem + endgenerate + +endmodule diff --git a/hdk/common/shell_v04261818/hlx/design/ip/aws_v1_0/hdl/aws_v1_0_vl_rfs.sv b/hdk/common/shell_v04261818/hlx/design/ip/aws_v1_0/hdl/aws_v1_0_vl_rfs.sv deleted file mode 100755 index edf00b8c6..000000000 --- a/hdk/common/shell_v04261818/hlx/design/ip/aws_v1_0/hdl/aws_v1_0_vl_rfs.sv +++ /dev/null @@ -1,3076 +0,0 @@ -//---------------------------------------------------------------------------------- -//Copyright (c) 2014 -// -//Permission is hereby granted, free of charge, to any person obtaining a copy -//of this software and associated documentation files (the "Software"), to deal -//in the Software without restriction, including without limitation the rights -//to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -//copies of the Software, and to permit persons to whom the Software is -//furnished to do so, subject to the following conditions: -// -//The above copyright notice and this permission notice shall be included in -//all copies or substantial portions of the Software. -// -//THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -//IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -//FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -//AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -//LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -//OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -//THE SOFTWARE. -//---------------------------------------------------------------------------------- - -//simple pipeline - -//WIDTH is the width of the DATA -//STAGES is the number of stages (flops in the pipeline) -module lib_pipe #(parameter WIDTH=8, parameter STAGES=1) ( - input clk, - input rst_n, - - input[WIDTH-1:0] in_bus, - - output [WIDTH-1:0] out_bus - ); - -//Note the shreg_extract=no directs Xilinx to not infer shift registers which -// defeats using this as a pipeline - - -`ifdef FPGA_LESS_RST - (*shreg_extract="no"*) logic [WIDTH-1:0] pipe[STAGES-1:0] = '{default:'0}; -`else - (*shreg_extract="no"*) logic [WIDTH-1:0] pipe[STAGES-1:0]; -`endif - -//(*srl_style="register"*) logic [WIDTH-1:0] pipe [STAGES-1:0]; -// logic [WIDTH-1:0] pipe [STAGES-1:0]; - - integer i; - -`ifdef FPGA_LESS_RST - always @(posedge clk) -`else - always @(negedge rst_n or posedge clk) - if (!rst_n) - begin - for (i=0; i1) - begin - for (i=1; i1 ? clk_extra_a1 : 1'b0 ; - assign clk_extra_a2_out = C_NUM_A_CLOCKS>2 ? clk_extra_a2 : 1'b0 ; - assign clk_extra_a3_out = C_NUM_A_CLOCKS>3 ? clk_extra_a3 : 1'b0 ; - assign clk_extra_b0_out = C_NUM_B_CLOCKS>0 ? clk_extra_b0 : 1'b0 ; - assign clk_extra_b1_out = C_NUM_B_CLOCKS>1 ? clk_extra_b1 : 1'b0 ; - assign clk_extra_c0_out = C_NUM_C_CLOCKS>0 ? clk_extra_c0 : 1'b0 ; - assign clk_extra_c1_out = C_NUM_C_CLOCKS>1 ? clk_extra_c1 : 1'b0 ; - assign rst_main_n_out = rst_main_n ; - assign kernel_rst_n_out = kernel_rst_n ; - assign flr_assert = sh_cl_flr_assert ; - assign status_vdip = sh_cl_status_vdip ; - assign irq_ack = sh_cl_apppf_irq_ack ; - assign glcount0 = sh_cl_glcount0 ; - assign glcount1 = sh_cl_glcount1 ; - - assign cl_sh_flr_done = flr_done ; - assign cl_sh_status_vled = status_vled ; - assign cl_sh_apppf_irq_req = irq_req ; - - assign cl_sh_status0 = 0 ; - assign cl_sh_status1 = 0 ; - assign cl_sh_id0 = {C_DEVICE_ID, C_VENDOR_ID} ; - assign cl_sh_id1 = {C_SUBSYSTEM_ID, C_SUBSYSTEM_VENDOR_ID} ; - - assign cl_sh_dma_wr_full = 1'b0; - assign cl_sh_dma_rd_full = 1'b0; - - assign cl_sh_ddr_awid = s_axi_ddrc_awid ; - assign cl_sh_ddr_awaddr = s_axi_ddrc_awaddr ; - assign cl_sh_ddr_awlen = s_axi_ddrc_awlen ; - assign cl_sh_ddr_awsize = s_axi_ddrc_awsize ; - assign cl_sh_ddr_awburst = 2'b01 ; - assign cl_sh_ddr_awvalid = s_axi_ddrc_awvalid ; - assign cl_sh_ddr_wdata = s_axi_ddrc_wdata ; - assign cl_sh_ddr_wstrb = s_axi_ddrc_wstrb ; - assign cl_sh_ddr_wlast = s_axi_ddrc_wlast ; - assign cl_sh_ddr_wvalid = s_axi_ddrc_wvalid ; - assign cl_sh_ddr_bready = s_axi_ddrc_bready ; - assign cl_sh_ddr_arid = s_axi_ddrc_arid ; - assign cl_sh_ddr_araddr = s_axi_ddrc_araddr ; - assign cl_sh_ddr_arlen = s_axi_ddrc_arlen ; - assign cl_sh_ddr_arsize = s_axi_ddrc_arsize ; - assign cl_sh_ddr_arburst = 2'b01 ; - assign cl_sh_ddr_arvalid = s_axi_ddrc_arvalid ; - assign cl_sh_ddr_rready = s_axi_ddrc_rready ; - - assign s_axi_ddrc_awready = sh_cl_ddr_awready ; - assign s_axi_ddrc_wready = sh_cl_ddr_wready ; - assign s_axi_ddrc_bid = sh_cl_ddr_bid ; - assign s_axi_ddrc_bresp = sh_cl_ddr_bresp ; - assign s_axi_ddrc_bvalid = sh_cl_ddr_bvalid ; - assign s_axi_ddrc_arready = sh_cl_ddr_arready ; - assign s_axi_ddrc_rid = sh_cl_ddr_rid ; - assign s_axi_ddrc_rdata = sh_cl_ddr_rdata ; - assign s_axi_ddrc_rresp = sh_cl_ddr_rresp ; - assign s_axi_ddrc_rlast = sh_cl_ddr_rlast ; - assign s_axi_ddrc_rvalid = sh_cl_ddr_rvalid ; - assign ddrc_is_ready = sh_cl_ddr_is_ready ; - - assign cl_sh_ddr_wid = 0 ; - - assign cl_sda_awready = m_axi_sda_awready ; - assign cl_sda_wready = m_axi_sda_wready ; - assign cl_sda_bresp = m_axi_sda_bresp ; - assign cl_sda_bvalid = m_axi_sda_bvalid ; - assign cl_sda_arready = m_axi_sda_arready ; - assign cl_sda_rdata = m_axi_sda_rdata ; - assign cl_sda_rresp = m_axi_sda_rresp ; - assign cl_sda_rvalid = m_axi_sda_rvalid ; - - assign m_axi_sda_awaddr = sda_cl_awaddr ; - assign m_axi_sda_awvalid = sda_cl_awvalid ; - assign m_axi_sda_wdata = sda_cl_wdata ; - assign m_axi_sda_wstrb = sda_cl_wstrb ; - assign m_axi_sda_wvalid = sda_cl_wvalid ; - assign m_axi_sda_bready = sda_cl_bready ; - assign m_axi_sda_araddr = sda_cl_araddr ; - assign m_axi_sda_arvalid = sda_cl_arvalid ; - assign m_axi_sda_rready = sda_cl_rready ; - - assign ocl_sh_awready = m_axi_ocl_awready ; - assign ocl_sh_wready = m_axi_ocl_wready ; - assign ocl_sh_bresp = m_axi_ocl_bresp ; - assign ocl_sh_bvalid = m_axi_ocl_bvalid ; - assign ocl_sh_arready = m_axi_ocl_arready ; - assign ocl_sh_rdata = m_axi_ocl_rdata ; - assign ocl_sh_rresp = m_axi_ocl_rresp ; - assign ocl_sh_rvalid = m_axi_ocl_rvalid ; - - assign m_axi_ocl_awaddr = sh_ocl_awaddr ; - assign m_axi_ocl_awvalid = sh_ocl_awvalid ; - assign m_axi_ocl_wdata = sh_ocl_wdata ; - assign m_axi_ocl_wstrb = sh_ocl_wstrb ; - assign m_axi_ocl_wvalid = sh_ocl_wvalid ; - assign m_axi_ocl_bready = sh_ocl_bready ; - assign m_axi_ocl_araddr = sh_ocl_araddr ; - assign m_axi_ocl_arvalid = sh_ocl_arvalid ; - assign m_axi_ocl_rready = sh_ocl_rready ; - - assign bar1_sh_awready = m_axi_bar1_awready ; - assign bar1_sh_wready = m_axi_bar1_wready ; - assign bar1_sh_bresp = m_axi_bar1_bresp ; - assign bar1_sh_bvalid = m_axi_bar1_bvalid ; - assign bar1_sh_arready = m_axi_bar1_arready ; - assign bar1_sh_rdata = m_axi_bar1_rdata ; - assign bar1_sh_rresp = m_axi_bar1_rresp ; - assign bar1_sh_rvalid = m_axi_bar1_rvalid ; - - assign m_axi_bar1_awaddr = sh_bar1_awaddr ; - assign m_axi_bar1_awvalid = sh_bar1_awvalid ; - assign m_axi_bar1_wdata = sh_bar1_wdata ; - assign m_axi_bar1_wstrb = sh_bar1_wstrb ; - assign m_axi_bar1_wvalid = sh_bar1_wvalid ; - assign m_axi_bar1_bready = sh_bar1_bready ; - assign m_axi_bar1_araddr = sh_bar1_araddr ; - assign m_axi_bar1_arvalid = sh_bar1_arvalid ; - assign m_axi_bar1_rready = sh_bar1_rready ; - - assign cl_sh_dma_pcis_awready = m_axi_pcis_awready ; - assign cl_sh_dma_pcis_wready = m_axi_pcis_wready ; - assign cl_sh_dma_pcis_bid = m_axi_pcis_bid ; - assign cl_sh_dma_pcis_bresp = m_axi_pcis_bresp ; - assign cl_sh_dma_pcis_bvalid = m_axi_pcis_bvalid ; - assign cl_sh_dma_pcis_arready = m_axi_pcis_arready ; - assign cl_sh_dma_pcis_rid = m_axi_pcis_rid ; - assign cl_sh_dma_pcis_rdata = m_axi_pcis_rdata ; - assign cl_sh_dma_pcis_rresp = m_axi_pcis_rresp ; - assign cl_sh_dma_pcis_rlast = m_axi_pcis_rlast ; - assign cl_sh_dma_pcis_rvalid = m_axi_pcis_rvalid ; - - assign m_axi_pcis_awid = sh_cl_dma_pcis_awid ; - assign m_axi_pcis_awaddr = sh_cl_dma_pcis_awaddr ; - assign m_axi_pcis_awlen = sh_cl_dma_pcis_awlen ; - assign m_axi_pcis_awsize = sh_cl_dma_pcis_awsize ; - assign m_axi_pcis_awvalid = sh_cl_dma_pcis_awvalid ; - assign m_axi_pcis_wdata = sh_cl_dma_pcis_wdata ; - assign m_axi_pcis_wstrb = sh_cl_dma_pcis_wstrb ; - assign m_axi_pcis_wlast = sh_cl_dma_pcis_wlast ; - assign m_axi_pcis_wvalid = sh_cl_dma_pcis_wvalid ; - assign m_axi_pcis_bready = sh_cl_dma_pcis_bready ; - assign m_axi_pcis_arid = sh_cl_dma_pcis_arid ; - assign m_axi_pcis_araddr = sh_cl_dma_pcis_araddr ; - assign m_axi_pcis_arlen = sh_cl_dma_pcis_arlen ; - assign m_axi_pcis_arsize = sh_cl_dma_pcis_arsize ; - assign m_axi_pcis_arvalid = sh_cl_dma_pcis_arvalid ; - assign m_axi_pcis_rready = sh_cl_dma_pcis_rready ; - assign m_axi_pcis_awburst = 2'b01 ; - assign m_axi_pcis_arburst = 2'b01 ; - - assign cl_sh_pcim_awid = s_axi_pcim_awid ; - assign cl_sh_pcim_awaddr = s_axi_pcim_awaddr ; - assign cl_sh_pcim_awlen = s_axi_pcim_awlen ; - assign cl_sh_pcim_awsize = s_axi_pcim_awsize ; - assign cl_sh_pcim_awuser = s_axi_pcim_awuser ; - assign cl_sh_pcim_awvalid = s_axi_pcim_awvalid ; - assign cl_sh_pcim_wdata = s_axi_pcim_wdata ; - assign cl_sh_pcim_wstrb = s_axi_pcim_wstrb ; - assign cl_sh_pcim_wlast = s_axi_pcim_wlast ; - assign cl_sh_pcim_wvalid = s_axi_pcim_wvalid ; - assign cl_sh_pcim_bready = s_axi_pcim_bready ; - assign cl_sh_pcim_arid = s_axi_pcim_arid ; - assign cl_sh_pcim_araddr = s_axi_pcim_araddr ; - assign cl_sh_pcim_arlen = s_axi_pcim_arlen ; - assign cl_sh_pcim_arsize = s_axi_pcim_arsize ; - assign cl_sh_pcim_aruser = s_axi_pcim_aruser ; - assign cl_sh_pcim_arvalid = s_axi_pcim_arvalid ; - assign cl_sh_pcim_rready = s_axi_pcim_rready ; - - assign s_axi_pcim_awready = sh_cl_pcim_awready ; - assign s_axi_pcim_wready = sh_cl_pcim_wready ; - assign s_axi_pcim_bid = sh_cl_pcim_bid ; - assign s_axi_pcim_bresp = sh_cl_pcim_bresp ; - assign s_axi_pcim_bvalid = sh_cl_pcim_bvalid ; - assign s_axi_pcim_arready = sh_cl_pcim_arready ; - assign s_axi_pcim_rid = sh_cl_pcim_rid ; - assign s_axi_pcim_rdata = sh_cl_pcim_rdata ; - assign s_axi_pcim_rresp = sh_cl_pcim_rresp ; - assign s_axi_pcim_rlast = sh_cl_pcim_rlast ; - assign s_axi_pcim_rvalid = sh_cl_pcim_rvalid ; - assign cfg_max_payload_out = cfg_max_payload ; - assign cfg_max_read_req_out = cfg_max_read_req ; - - if ((C_MODE == 0) || (C_MODE == 1)) begin : gen_mem - - logic [15:0] cl_sh_ddr_awid_2d[2:0]; - logic [63:0] cl_sh_ddr_awaddr_2d[2:0]; - logic [7:0] cl_sh_ddr_awlen_2d[2:0]; - logic [2:0] cl_sh_ddr_awsize_2d[2:0]; - logic [1:0] cl_sh_ddr_awburst_2d[2:0]; - logic cl_sh_ddr_awvalid_2d[2:0]; - logic [2:0] sh_cl_ddr_awready_2d; - logic [15:0] cl_sh_ddr_wid_2d[2:0]; - logic [511:0] cl_sh_ddr_wdata_2d[2:0]; - logic [63:0] cl_sh_ddr_wstrb_2d[2:0]; - logic [2:0] cl_sh_ddr_wlast_2d; - logic [2:0] cl_sh_ddr_wvalid_2d; - logic [2:0] sh_cl_ddr_wready_2d; - logic [15:0] sh_cl_ddr_bid_2d[2:0]; - logic [1:0] sh_cl_ddr_bresp_2d[2:0]; - logic [2:0] sh_cl_ddr_bvalid_2d; - logic [2:0] cl_sh_ddr_bready_2d; - logic [15:0] cl_sh_ddr_arid_2d[2:0]; - logic [63:0] cl_sh_ddr_araddr_2d[2:0]; - logic [7:0] cl_sh_ddr_arlen_2d[2:0]; - logic [2:0] cl_sh_ddr_arsize_2d[2:0]; - logic [1:0] cl_sh_ddr_arburst_2d[2:0]; - logic [2:0] cl_sh_ddr_arvalid_2d; - logic [2:0] sh_cl_ddr_arready_2d; - logic [15:0] sh_cl_ddr_rid_2d[2:0]; - logic [511:0] sh_cl_ddr_rdata_2d[2:0]; - logic [1:0] sh_cl_ddr_rresp_2d[2:0]; - logic [2:0] sh_cl_ddr_rlast_2d; - logic [2:0] sh_cl_ddr_rvalid_2d; - logic [2:0] cl_sh_ddr_rready_2d; - logic [2:0] sh_cl_ddr_is_ready_2d; - - assign cl_sh_ddr_awid_2d[0] = s_axi_ddra_awid ; - assign cl_sh_ddr_awaddr_2d[0] = s_axi_ddra_awaddr ; - assign cl_sh_ddr_awlen_2d[0] = s_axi_ddra_awlen ; - assign cl_sh_ddr_awsize_2d[0] = s_axi_ddra_awsize ; - assign cl_sh_ddr_awburst_2d[0] = 2'b01 ; - assign cl_sh_ddr_awvalid_2d[0] = s_axi_ddra_awvalid ; - assign cl_sh_ddr_wid_2d[0] = 0 ; - assign cl_sh_ddr_wdata_2d[0] = s_axi_ddra_wdata ; - assign cl_sh_ddr_wstrb_2d[0] = s_axi_ddra_wstrb ; - assign cl_sh_ddr_wlast_2d[0] = s_axi_ddra_wlast ; - assign cl_sh_ddr_wvalid_2d[0] = s_axi_ddra_wvalid ; - assign cl_sh_ddr_bready_2d[0] = s_axi_ddra_bready ; - assign cl_sh_ddr_arid_2d[0] = s_axi_ddra_arid ; - assign cl_sh_ddr_araddr_2d[0] = s_axi_ddra_araddr ; - assign cl_sh_ddr_arlen_2d[0] = s_axi_ddra_arlen ; - assign cl_sh_ddr_arsize_2d[0] = s_axi_ddra_arsize ; - assign cl_sh_ddr_arburst_2d[0] = 2'b01 ; - assign cl_sh_ddr_arvalid_2d[0] = s_axi_ddra_arvalid ; - assign cl_sh_ddr_rready_2d[0] = s_axi_ddra_rready ; - - assign s_axi_ddra_awready = sh_cl_ddr_awready_2d[0] ; - assign s_axi_ddra_wready = sh_cl_ddr_wready_2d[0] ; - assign s_axi_ddra_bid = sh_cl_ddr_bid_2d[0] ; - assign s_axi_ddra_bresp = sh_cl_ddr_bresp_2d[0] ; - assign s_axi_ddra_bvalid = sh_cl_ddr_bvalid_2d[0] ; - assign s_axi_ddra_arready = sh_cl_ddr_arready_2d[0] ; - assign s_axi_ddra_rid = sh_cl_ddr_rid_2d[0] ; - assign s_axi_ddra_rdata = sh_cl_ddr_rdata_2d[0] ; - assign s_axi_ddra_rresp = sh_cl_ddr_rresp_2d[0] ; - assign s_axi_ddra_rlast = sh_cl_ddr_rlast_2d[0] ; - assign s_axi_ddra_rvalid = sh_cl_ddr_rvalid_2d[0] ; - assign ddra_is_ready = sh_cl_ddr_is_ready_2d[0]; - - assign cl_sh_ddr_awid_2d[1] = s_axi_ddrb_awid ; - assign cl_sh_ddr_awaddr_2d[1] = s_axi_ddrb_awaddr ; - assign cl_sh_ddr_awlen_2d[1] = s_axi_ddrb_awlen ; - assign cl_sh_ddr_awsize_2d[1] = s_axi_ddrb_awsize ; - assign cl_sh_ddr_awburst_2d[1] = 2'b01 ; - assign cl_sh_ddr_awvalid_2d[1] = s_axi_ddrb_awvalid ; - assign cl_sh_ddr_wid_2d[1] = 0 ; - assign cl_sh_ddr_wdata_2d[1] = s_axi_ddrb_wdata ; - assign cl_sh_ddr_wstrb_2d[1] = s_axi_ddrb_wstrb ; - assign cl_sh_ddr_wlast_2d[1] = s_axi_ddrb_wlast ; - assign cl_sh_ddr_wvalid_2d[1] = s_axi_ddrb_wvalid ; - assign cl_sh_ddr_bready_2d[1] = s_axi_ddrb_bready ; - assign cl_sh_ddr_arid_2d[1] = s_axi_ddrb_arid ; - assign cl_sh_ddr_araddr_2d[1] = s_axi_ddrb_araddr ; - assign cl_sh_ddr_arlen_2d[1] = s_axi_ddrb_arlen ; - assign cl_sh_ddr_arsize_2d[1] = s_axi_ddrb_arsize ; - assign cl_sh_ddr_arburst_2d[1] = 2'b01 ; - assign cl_sh_ddr_arvalid_2d[1] = s_axi_ddrb_arvalid ; - assign cl_sh_ddr_rready_2d[1] = s_axi_ddrb_rready ; - - assign s_axi_ddrb_awready = sh_cl_ddr_awready_2d[1] ; - assign s_axi_ddrb_wready = sh_cl_ddr_wready_2d[1] ; - assign s_axi_ddrb_bid = sh_cl_ddr_bid_2d[1] ; - assign s_axi_ddrb_bresp = sh_cl_ddr_bresp_2d[1] ; - assign s_axi_ddrb_bvalid = sh_cl_ddr_bvalid_2d[1] ; - assign s_axi_ddrb_arready = sh_cl_ddr_arready_2d[1] ; - assign s_axi_ddrb_rid = sh_cl_ddr_rid_2d[1] ; - assign s_axi_ddrb_rdata = sh_cl_ddr_rdata_2d[1] ; - assign s_axi_ddrb_rresp = sh_cl_ddr_rresp_2d[1] ; - assign s_axi_ddrb_rlast = sh_cl_ddr_rlast_2d[1] ; - assign s_axi_ddrb_rvalid = sh_cl_ddr_rvalid_2d[1] ; - assign ddrb_is_ready = sh_cl_ddr_is_ready_2d[1]; - - assign cl_sh_ddr_awid_2d[2] = s_axi_ddrd_awid ; - assign cl_sh_ddr_awaddr_2d[2] = s_axi_ddrd_awaddr ; - assign cl_sh_ddr_awlen_2d[2] = s_axi_ddrd_awlen ; - assign cl_sh_ddr_awsize_2d[2] = s_axi_ddrd_awsize ; - assign cl_sh_ddr_awburst_2d[2] = 2'b01 ; - assign cl_sh_ddr_awvalid_2d[2] = s_axi_ddrd_awvalid ; - assign cl_sh_ddr_wid_2d[2] = 0 ; - assign cl_sh_ddr_wdata_2d[2] = s_axi_ddrd_wdata ; - assign cl_sh_ddr_wstrb_2d[2] = s_axi_ddrd_wstrb ; - assign cl_sh_ddr_wlast_2d[2] = s_axi_ddrd_wlast ; - assign cl_sh_ddr_wvalid_2d[2] = s_axi_ddrd_wvalid ; - assign cl_sh_ddr_bready_2d[2] = s_axi_ddrd_bready ; - assign cl_sh_ddr_arid_2d[2] = s_axi_ddrd_arid ; - assign cl_sh_ddr_araddr_2d[2] = s_axi_ddrd_araddr ; - assign cl_sh_ddr_arlen_2d[2] = s_axi_ddrd_arlen ; - assign cl_sh_ddr_arsize_2d[2] = s_axi_ddrd_arsize ; - assign cl_sh_ddr_arburst_2d[2] = 2'b01 ; - assign cl_sh_ddr_arvalid_2d[2] = s_axi_ddrd_arvalid ; - assign cl_sh_ddr_rready_2d[2] = s_axi_ddrd_rready ; - - assign s_axi_ddrd_awready = sh_cl_ddr_awready_2d[2] ; - assign s_axi_ddrd_wready = sh_cl_ddr_wready_2d[2] ; - assign s_axi_ddrd_bid = sh_cl_ddr_bid_2d[2] ; - assign s_axi_ddrd_bresp = sh_cl_ddr_bresp_2d[2] ; - assign s_axi_ddrd_bvalid = sh_cl_ddr_bvalid_2d[2] ; - assign s_axi_ddrd_arready = sh_cl_ddr_arready_2d[2] ; - assign s_axi_ddrd_rid = sh_cl_ddr_rid_2d[2] ; - assign s_axi_ddrd_rdata = sh_cl_ddr_rdata_2d[2] ; - assign s_axi_ddrd_rresp = sh_cl_ddr_rresp_2d[2] ; - assign s_axi_ddrd_rlast = sh_cl_ddr_rlast_2d[2] ; - assign s_axi_ddrd_rvalid = sh_cl_ddr_rvalid_2d[2] ; - assign ddrd_is_ready = sh_cl_ddr_is_ready_2d[2]; - - logic ddr_aws_stat_ack0; - logic [31:0] ddr_aws_stat_rdata0; - logic [7:0] ddr_aws_stat_int0; - logic ddr_aws_stat_ack1; - logic [31:0] ddr_aws_stat_rdata1; - logic [7:0] ddr_aws_stat_int1; - logic ddr_aws_stat_ack2; - logic [31:0] ddr_aws_stat_rdata2; - logic [7:0] ddr_aws_stat_int2; - - logic [7:0] pipe_ddr_stat_addr0; - logic pipe_ddr_stat_wr0; - logic pipe_ddr_stat_rd0; - logic [31:0] pipe_ddr_stat_wdata0; - logic ddr_pipe_stat_ack0; - logic [31:0] ddr_pipe_stat_rdata0; - logic [7:0] ddr_pipe_stat_int0; - - logic [7:0] pipe_ddr_stat_addr1; - logic pipe_ddr_stat_wr1; - logic pipe_ddr_stat_rd1; - logic [31:0] pipe_ddr_stat_wdata1; - logic ddr_pipe_stat_ack1; - logic [31:0] ddr_pipe_stat_rdata1; - logic [7:0] ddr_pipe_stat_int1; - - logic [7:0] pipe_ddr_stat_addr2; - logic pipe_ddr_stat_wr2; - logic pipe_ddr_stat_rd2; - logic [31:0] pipe_ddr_stat_wdata2; - logic ddr_pipe_stat_ack2; - logic [31:0] ddr_pipe_stat_rdata2; - logic [7:0] ddr_pipe_stat_int2; - -//------------------------------------------------- -// Tie-offs when DDRs are disabled -//------------------------------------------------- - assign ddr_sh_stat_ack0 = (C_DDR_A_PRESENT!=0) ? ddr_aws_stat_ack0 : 1'b1; - assign ddr_sh_stat_rdata0 = (C_DDR_A_PRESENT!=0) ? ddr_aws_stat_rdata0 : 0; - assign ddr_sh_stat_int0 = (C_DDR_A_PRESENT!=0) ? ddr_aws_stat_int0 : 8'b0; - assign ddr_sh_stat_ack1 = (C_DDR_B_PRESENT!=0) ? ddr_aws_stat_ack1 : 1'b1; - assign ddr_sh_stat_rdata1 = (C_DDR_B_PRESENT!=0) ? ddr_aws_stat_rdata1 : 0; - assign ddr_sh_stat_int1 = (C_DDR_B_PRESENT!=0) ? ddr_aws_stat_int1 : 8'b0; - assign ddr_sh_stat_ack2 = (C_DDR_D_PRESENT!=0) ? ddr_aws_stat_ack2 : 1'b1; - assign ddr_sh_stat_rdata2 = (C_DDR_D_PRESENT!=0) ? ddr_aws_stat_rdata2 : 0; - assign ddr_sh_stat_int2 = (C_DDR_D_PRESENT!=0) ? ddr_aws_stat_int2 : 8'b0; - -//------------------------------------------------- -// Reset Synchronization -//------------------------------------------------- - logic pre_sync_rst_n; - logic sync_rst_n; - - always @(negedge rst_main_n or posedge clk_main_a0) begin - if (!rst_main_n) begin - pre_sync_rst_n <= 1'b0; - sync_rst_n <= 1'b0; - end else begin - pre_sync_rst_n <= 1'b1; - sync_rst_n <= pre_sync_rst_n; - end - end - - `ifdef FPGA_LESS_RST - `undef FPGA_LESS_RST - `endif - - lib_pipe #(.WIDTH(32), .STAGES(C_NUM_STAGES_STATS)) pipe_stat_wdata0 (.clk(clk_main_a0), .rst_n(1'b1), .in_bus(sh_ddr_stat_wdata0), .out_bus(pipe_ddr_stat_wdata0)); - lib_pipe #(.WIDTH(8), .STAGES(C_NUM_STAGES_STATS)) pipe_stat_addr0 (.clk(clk_main_a0), .rst_n(1'b1), .in_bus(sh_ddr_stat_addr0), .out_bus(pipe_ddr_stat_addr0)); - lib_pipe #(.WIDTH(1), .STAGES(C_NUM_STAGES_STATS)) pipe_stat_wr0 (.clk(clk_main_a0), .rst_n(sync_rst_n), .in_bus(sh_ddr_stat_wr0), .out_bus(pipe_ddr_stat_wr0)); - lib_pipe #(.WIDTH(1), .STAGES(C_NUM_STAGES_STATS)) pipe_stat_rd0 (.clk(clk_main_a0), .rst_n(sync_rst_n), .in_bus(sh_ddr_stat_rd0), .out_bus(pipe_ddr_stat_rd0)); - lib_pipe #(.WIDTH(32), .STAGES(C_NUM_STAGES_STATS)) pipe_stat_rdata0 (.clk(clk_main_a0), .rst_n(1'b1), .out_bus(ddr_aws_stat_rdata0), .in_bus(ddr_pipe_stat_rdata0)); - lib_pipe #(.WIDTH(1), .STAGES(C_NUM_STAGES_STATS)) pipe_stat_ack0 (.clk(clk_main_a0), .rst_n(sync_rst_n), .out_bus(ddr_aws_stat_ack0), .in_bus(ddr_pipe_stat_ack0)); - lib_pipe #(.WIDTH(8), .STAGES(C_NUM_STAGES_STATS)) pipe_stat_int0 (.clk(clk_main_a0), .rst_n(sync_rst_n), .out_bus(ddr_aws_stat_int0), .in_bus(ddr_pipe_stat_int0)); - - lib_pipe #(.WIDTH(32), .STAGES(C_NUM_STAGES_STATS)) pipe_stat_wdata1 (.clk(clk_main_a0), .rst_n(1'b1), .in_bus(sh_ddr_stat_wdata1), .out_bus(pipe_ddr_stat_wdata1)); - lib_pipe #(.WIDTH(8), .STAGES(C_NUM_STAGES_STATS)) pipe_stat_addr1 (.clk(clk_main_a0), .rst_n(1'b1), .in_bus(sh_ddr_stat_addr1), .out_bus(pipe_ddr_stat_addr1)); - lib_pipe #(.WIDTH(1), .STAGES(C_NUM_STAGES_STATS)) pipe_stat_wr1 (.clk(clk_main_a0), .rst_n(sync_rst_n), .in_bus(sh_ddr_stat_wr1), .out_bus(pipe_ddr_stat_wr1)); - lib_pipe #(.WIDTH(1), .STAGES(C_NUM_STAGES_STATS)) pipe_stat_rd1 (.clk(clk_main_a0), .rst_n(sync_rst_n), .in_bus(sh_ddr_stat_rd1), .out_bus(pipe_ddr_stat_rd1)); - lib_pipe #(.WIDTH(32), .STAGES(C_NUM_STAGES_STATS)) pipe_stat_rdata1 (.clk(clk_main_a0), .rst_n(1'b1), .out_bus(ddr_aws_stat_rdata1), .in_bus(ddr_pipe_stat_rdata1)); - lib_pipe #(.WIDTH(1), .STAGES(C_NUM_STAGES_STATS)) pipe_stat_ack1 (.clk(clk_main_a0), .rst_n(sync_rst_n), .out_bus(ddr_aws_stat_ack1), .in_bus(ddr_pipe_stat_ack1)); - lib_pipe #(.WIDTH(8), .STAGES(C_NUM_STAGES_STATS)) pipe_stat_int1 (.clk(clk_main_a0), .rst_n(sync_rst_n), .out_bus(ddr_aws_stat_int1), .in_bus(ddr_pipe_stat_int1)); - - lib_pipe #(.WIDTH(32), .STAGES(C_NUM_STAGES_STATS)) pipe_stat_wdata2 (.clk(clk_main_a0), .rst_n(1'b1), .in_bus(sh_ddr_stat_wdata2), .out_bus(pipe_ddr_stat_wdata2)); - lib_pipe #(.WIDTH(8), .STAGES(C_NUM_STAGES_STATS)) pipe_stat_addr2 (.clk(clk_main_a0), .rst_n(1'b1), .in_bus(sh_ddr_stat_addr2), .out_bus(pipe_ddr_stat_addr2)); - lib_pipe #(.WIDTH(1), .STAGES(C_NUM_STAGES_STATS)) pipe_stat_wr2 (.clk(clk_main_a0), .rst_n(sync_rst_n), .in_bus(sh_ddr_stat_wr2), .out_bus(pipe_ddr_stat_wr2)); - lib_pipe #(.WIDTH(1), .STAGES(C_NUM_STAGES_STATS)) pipe_stat_rd2 (.clk(clk_main_a0), .rst_n(sync_rst_n), .in_bus(sh_ddr_stat_rd2), .out_bus(pipe_ddr_stat_rd2)); - lib_pipe #(.WIDTH(32), .STAGES(C_NUM_STAGES_STATS)) pipe_stat_rdata2 (.clk(clk_main_a0), .rst_n(1'b1), .out_bus(ddr_aws_stat_rdata2), .in_bus(ddr_pipe_stat_rdata2)); - lib_pipe #(.WIDTH(1), .STAGES(C_NUM_STAGES_STATS)) pipe_stat_ack2 (.clk(clk_main_a0), .rst_n(sync_rst_n), .out_bus(ddr_aws_stat_ack2), .in_bus(ddr_pipe_stat_ack2)); - lib_pipe #(.WIDTH(8), .STAGES(C_NUM_STAGES_STATS)) pipe_stat_int2 (.clk(clk_main_a0), .rst_n(sync_rst_n), .out_bus(ddr_aws_stat_int2), .in_bus(ddr_pipe_stat_int2)); - - sh_ddr #( - .DDR_A_PRESENT(C_DDR_A_PRESENT), - .DDR_B_PRESENT(C_DDR_B_PRESENT), - .DDR_D_PRESENT(C_DDR_D_PRESENT) - ) sh_ddr_0 - ( - .clk(clk_main_a0), - .rst_n(sync_rst_n), - - .stat_clk(clk_main_a0), - .stat_rst_n(sync_rst_n), - - .CLK_300M_DIMM0_DP(CLK_300M_DIMM0_DP), - .CLK_300M_DIMM0_DN(CLK_300M_DIMM0_DN), - .M_A_ACT_N(M_A_ACT_N), - .M_A_MA(M_A_MA), - .M_A_BA(M_A_BA), - .M_A_BG(M_A_BG), - .M_A_CKE(M_A_CKE), - .M_A_ODT(M_A_ODT), - .M_A_CS_N(M_A_CS_N), - .M_A_CLK_DN(M_A_CLK_DN), - .M_A_CLK_DP(M_A_CLK_DP), - .M_A_PAR(M_A_PAR), - .M_A_DQ(M_A_DQ), - .M_A_ECC(M_A_ECC), - .M_A_DQS_DP(M_A_DQS_DP), - .M_A_DQS_DN(M_A_DQS_DN), - .cl_RST_DIMM_A_N(cl_RST_DIMM_A_N), - - .CLK_300M_DIMM1_DP(CLK_300M_DIMM1_DP), - .CLK_300M_DIMM1_DN(CLK_300M_DIMM1_DN), - .M_B_ACT_N(M_B_ACT_N), - .M_B_MA(M_B_MA), - .M_B_BA(M_B_BA), - .M_B_BG(M_B_BG), - .M_B_CKE(M_B_CKE), - .M_B_ODT(M_B_ODT), - .M_B_CS_N(M_B_CS_N), - .M_B_CLK_DN(M_B_CLK_DN), - .M_B_CLK_DP(M_B_CLK_DP), - .M_B_PAR(M_B_PAR), - .M_B_DQ(M_B_DQ), - .M_B_ECC(M_B_ECC), - .M_B_DQS_DP(M_B_DQS_DP), - .M_B_DQS_DN(M_B_DQS_DN), - .cl_RST_DIMM_B_N(cl_RST_DIMM_B_N), - - .CLK_300M_DIMM3_DP(CLK_300M_DIMM3_DP), - .CLK_300M_DIMM3_DN(CLK_300M_DIMM3_DN), - .M_D_ACT_N(M_D_ACT_N), - .M_D_MA(M_D_MA), - .M_D_BA(M_D_BA), - .M_D_BG(M_D_BG), - .M_D_CKE(M_D_CKE), - .M_D_ODT(M_D_ODT), - .M_D_CS_N(M_D_CS_N), - .M_D_CLK_DN(M_D_CLK_DN), - .M_D_CLK_DP(M_D_CLK_DP), - .M_D_PAR(M_D_PAR), - .M_D_DQ(M_D_DQ), - .M_D_ECC(M_D_ECC), - .M_D_DQS_DP(M_D_DQS_DP), - .M_D_DQS_DN(M_D_DQS_DN), - .cl_RST_DIMM_D_N(cl_RST_DIMM_D_N), - - //------------------------------------------------------ - // AXI Slave Interfaces - //------------------------------------------------------ - .cl_sh_ddr_awid(cl_sh_ddr_awid_2d), - .cl_sh_ddr_awaddr(cl_sh_ddr_awaddr_2d), - .cl_sh_ddr_awlen(cl_sh_ddr_awlen_2d), - .cl_sh_ddr_awsize(cl_sh_ddr_awsize_2d), - .cl_sh_ddr_awburst(cl_sh_ddr_awburst_2d), - .cl_sh_ddr_awvalid(cl_sh_ddr_awvalid_2d), - .sh_cl_ddr_awready(sh_cl_ddr_awready_2d), - - .cl_sh_ddr_wid(cl_sh_ddr_wid_2d), - .cl_sh_ddr_wdata(cl_sh_ddr_wdata_2d), - .cl_sh_ddr_wstrb(cl_sh_ddr_wstrb_2d), - .cl_sh_ddr_wlast(cl_sh_ddr_wlast_2d), - .cl_sh_ddr_wvalid(cl_sh_ddr_wvalid_2d), - .sh_cl_ddr_wready(sh_cl_ddr_wready_2d), - - .sh_cl_ddr_bid(sh_cl_ddr_bid_2d), - .sh_cl_ddr_bresp(sh_cl_ddr_bresp_2d), - .sh_cl_ddr_bvalid(sh_cl_ddr_bvalid_2d), - .cl_sh_ddr_bready(cl_sh_ddr_bready_2d), - - .cl_sh_ddr_arid(cl_sh_ddr_arid_2d), - .cl_sh_ddr_araddr(cl_sh_ddr_araddr_2d), - .cl_sh_ddr_arlen(cl_sh_ddr_arlen_2d), - .cl_sh_ddr_arsize(cl_sh_ddr_arsize_2d), - .cl_sh_ddr_arburst(cl_sh_ddr_arburst_2d), - .cl_sh_ddr_arvalid(cl_sh_ddr_arvalid_2d), - .sh_cl_ddr_arready(sh_cl_ddr_arready_2d), - - .sh_cl_ddr_rid(sh_cl_ddr_rid_2d), - .sh_cl_ddr_rdata(sh_cl_ddr_rdata_2d), - .sh_cl_ddr_rresp(sh_cl_ddr_rresp_2d), - .sh_cl_ddr_rlast(sh_cl_ddr_rlast_2d), - .sh_cl_ddr_rvalid(sh_cl_ddr_rvalid_2d), - .cl_sh_ddr_rready(cl_sh_ddr_rready_2d), - - .sh_cl_ddr_is_ready(sh_cl_ddr_is_ready_2d), - - .sh_ddr_stat_addr0 (pipe_ddr_stat_addr0 ), - .sh_ddr_stat_wr0 (pipe_ddr_stat_wr0 ), - .sh_ddr_stat_rd0 (pipe_ddr_stat_rd0 ), - .sh_ddr_stat_wdata0 (pipe_ddr_stat_wdata0), - .ddr_sh_stat_ack0 (ddr_pipe_stat_ack0 ), - .ddr_sh_stat_rdata0 (ddr_pipe_stat_rdata0), - .ddr_sh_stat_int0 (ddr_pipe_stat_int0 ), - - .sh_ddr_stat_addr1 (pipe_ddr_stat_addr1 ), - .sh_ddr_stat_wr1 (pipe_ddr_stat_wr1 ), - .sh_ddr_stat_rd1 (pipe_ddr_stat_rd1 ), - .sh_ddr_stat_wdata1 (pipe_ddr_stat_wdata1), - .ddr_sh_stat_ack1 (ddr_pipe_stat_ack1 ), - .ddr_sh_stat_rdata1 (ddr_pipe_stat_rdata1), - .ddr_sh_stat_int1 (ddr_pipe_stat_int1 ), - - .sh_ddr_stat_addr2 (pipe_ddr_stat_addr2 ), - .sh_ddr_stat_wr2 (pipe_ddr_stat_wr2 ), - .sh_ddr_stat_rd2 (pipe_ddr_stat_rd2 ), - .sh_ddr_stat_wdata2 (pipe_ddr_stat_wdata2), - .ddr_sh_stat_ack2 (ddr_pipe_stat_ack2 ), - .ddr_sh_stat_rdata2 (ddr_pipe_stat_rdata2), - .ddr_sh_stat_int2 (ddr_pipe_stat_int2 ) - - ); - - end else begin : gen_non_mem - - assign s_axi_ddra_awready = 0; - assign s_axi_ddra_wready = 0; - assign s_axi_ddra_bid = 0; - assign s_axi_ddra_bresp = 0; - assign s_axi_ddra_bvalid = 0; - assign s_axi_ddra_arready = 0; - assign s_axi_ddra_rid = 0; - assign s_axi_ddra_rdata = 0; - assign s_axi_ddra_rresp = 0; - assign s_axi_ddra_rlast = 1'b1; - assign s_axi_ddra_rvalid = 0; - assign ddra_is_ready = 0; - - assign s_axi_ddrb_awready = 0; - assign s_axi_ddrb_wready = 0; - assign s_axi_ddrb_bid = 0; - assign s_axi_ddrb_bresp = 0; - assign s_axi_ddrb_bvalid = 0; - assign s_axi_ddrb_arready = 0; - assign s_axi_ddrb_rid = 0; - assign s_axi_ddrb_rdata = 0; - assign s_axi_ddrb_rresp = 0; - assign s_axi_ddrb_rlast = 1'b1; - assign s_axi_ddrb_rvalid = 0; - assign ddrb_is_ready = 0; - - assign s_axi_ddrd_awready = 0; - assign s_axi_ddrd_wready = 0; - assign s_axi_ddrd_bid = 0; - assign s_axi_ddrd_bresp = 0; - assign s_axi_ddrd_bvalid = 0; - assign s_axi_ddrd_arready = 0; - assign s_axi_ddrd_rid = 0; - assign s_axi_ddrd_rdata = 0; - assign s_axi_ddrd_rresp = 0; - assign s_axi_ddrd_rlast = 1'b1; - assign s_axi_ddrd_rvalid = 0; - assign ddrd_is_ready = 0; - - assign ddr_sh_stat_ack0 = 1'b1; - assign ddr_sh_stat_rdata0 = 0; - assign ddr_sh_stat_int0 = 8'b0; - assign ddr_sh_stat_ack1 = 1'b1; - assign ddr_sh_stat_rdata1 = 0; - assign ddr_sh_stat_int1 = 8'b0; - assign ddr_sh_stat_ack2 = 1'b1; - assign ddr_sh_stat_rdata2 = 0; - assign ddr_sh_stat_int2 = 8'b0; - - assign M_A_ACT_N = 0; - assign M_A_MA = 0; - assign M_A_BA = 0; - assign M_A_BG = 0; - assign M_A_CKE = 0; - assign M_A_ODT = 0; - assign M_A_CS_N = 0; - assign M_A_CLK_DN = 0; - assign M_A_CLK_DP = 0; - assign M_A_PAR = 0; - assign cl_RST_DIMM_A_N = 0; - - assign M_B_ACT_N = 0; - assign M_B_MA = 0; - assign M_B_BA = 0; - assign M_B_BG = 0; - assign M_B_CKE = 0; - assign M_B_ODT = 0; - assign M_B_CS_N = 0; - assign M_B_CLK_DN = 0; - assign M_B_CLK_DP = 0; - assign M_B_PAR = 0; - assign cl_RST_DIMM_B_N = 0; - - assign M_D_ACT_N = 0; - assign M_D_MA = 0; - assign M_D_BA = 0; - assign M_D_BG = 0; - assign M_D_CKE = 0; - assign M_D_ODT = 0; - assign M_D_CS_N = 0; - assign M_D_CLK_DN = 0; - assign M_D_CLK_DP = 0; - assign M_D_PAR = 0; - assign cl_RST_DIMM_D_N = 0; - - end // gen_mem - endgenerate - -endmodule - - diff --git a/hdk/common/shell_v04261818/hlx/design/ip/aws_v1_0/hdl/aws_v1_0_vlsyn_rfs.sv b/hdk/common/shell_v04261818/hlx/design/ip/aws_v1_0/hdl/aws_v1_0_vlsyn_rfs.sv deleted file mode 100755 index f2122cceb..000000000 --- a/hdk/common/shell_v04261818/hlx/design/ip/aws_v1_0/hdl/aws_v1_0_vlsyn_rfs.sv +++ /dev/null @@ -1,3099 +0,0 @@ -//---------------------------------------------------------------------------------- -//Copyright (c) 2014 -// -//Permission is hereby granted, free of charge, to any person obtaining a copy -//of this software and associated documentation files (the "Software"), to deal -//in the Software without restriction, including without limitation the rights -//to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -//copies of the Software, and to permit persons to whom the Software is -//furnished to do so, subject to the following conditions: -// -//The above copyright notice and this permission notice shall be included in -//all copies or substantial portions of the Software. -// -//THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -//IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -//FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -//AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -//LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -//OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -//THE SOFTWARE. -//---------------------------------------------------------------------------------- - -//simple pipeline - -//WIDTH is the width of the DATA -//STAGES is the number of stages (flops in the pipeline) -module lib_pipe #(parameter WIDTH=8, parameter STAGES=1) ( - input clk, - input rst_n, - - input[WIDTH-1:0] in_bus, - - output [WIDTH-1:0] out_bus - ); - -//Note the shreg_extract=no directs Xilinx to not infer shift registers which -// defeats using this as a pipeline - - -`ifdef FPGA_LESS_RST - (*shreg_extract="no"*) logic [WIDTH-1:0] pipe[STAGES-1:0] = '{default:'0}; -`else - (*shreg_extract="no"*) logic [WIDTH-1:0] pipe[STAGES-1:0]; -`endif - -//(*srl_style="register"*) logic [WIDTH-1:0] pipe [STAGES-1:0]; -// logic [WIDTH-1:0] pipe [STAGES-1:0]; - - integer i; - -`ifdef FPGA_LESS_RST - always @(posedge clk) -`else - always @(negedge rst_n or posedge clk) - if (!rst_n) - begin - for (i=0; i1) - begin - for (i=1; i1 ? clk_extra_a1 : 1'b0 ; - assign clk_extra_a2_out = C_NUM_A_CLOCKS>2 ? clk_extra_a2 : 1'b0 ; - assign clk_extra_a3_out = C_NUM_A_CLOCKS>3 ? clk_extra_a3 : 1'b0 ; - assign clk_extra_b0_out = C_NUM_B_CLOCKS>0 ? clk_extra_b0 : 1'b0 ; - assign clk_extra_b1_out = C_NUM_B_CLOCKS>1 ? clk_extra_b1 : 1'b0 ; - assign clk_extra_c0_out = C_NUM_C_CLOCKS>0 ? clk_extra_c0 : 1'b0 ; - assign clk_extra_c1_out = C_NUM_C_CLOCKS>1 ? clk_extra_c1 : 1'b0 ; - assign rst_main_n_out = rst_main_n ; - assign kernel_rst_n_out = kernel_rst_n ; - assign flr_assert = sh_cl_flr_assert ; - assign status_vdip = sh_cl_status_vdip ; - assign irq_ack = sh_cl_apppf_irq_ack ; - assign glcount0 = sh_cl_glcount0 ; - assign glcount1 = sh_cl_glcount1 ; - - assign cl_sh_flr_done = flr_done ; - assign cl_sh_status_vled = status_vled ; - assign cl_sh_apppf_irq_req = irq_req ; - - assign cl_sh_status0 = 0 ; - assign cl_sh_status1 = 0 ; - assign cl_sh_id0 = {C_DEVICE_ID, C_VENDOR_ID} ; - assign cl_sh_id1 = {C_SUBSYSTEM_ID, C_SUBSYSTEM_VENDOR_ID} ; - - assign cl_sh_dma_wr_full = 1'b0; - assign cl_sh_dma_rd_full = 1'b0; - - assign cl_sh_ddr_awid = s_axi_ddrc_awid ; - assign cl_sh_ddr_awaddr = s_axi_ddrc_awaddr ; - assign cl_sh_ddr_awlen = s_axi_ddrc_awlen ; - assign cl_sh_ddr_awsize = s_axi_ddrc_awsize ; - assign cl_sh_ddr_awburst = 2'b01 ; - assign cl_sh_ddr_awvalid = s_axi_ddrc_awvalid ; - assign cl_sh_ddr_wdata = s_axi_ddrc_wdata ; - assign cl_sh_ddr_wstrb = s_axi_ddrc_wstrb ; - assign cl_sh_ddr_wlast = s_axi_ddrc_wlast ; - assign cl_sh_ddr_wvalid = s_axi_ddrc_wvalid ; - assign cl_sh_ddr_bready = s_axi_ddrc_bready ; - assign cl_sh_ddr_arid = s_axi_ddrc_arid ; - assign cl_sh_ddr_araddr = s_axi_ddrc_araddr ; - assign cl_sh_ddr_arlen = s_axi_ddrc_arlen ; - assign cl_sh_ddr_arsize = s_axi_ddrc_arsize ; - assign cl_sh_ddr_arburst = 2'b01 ; - assign cl_sh_ddr_arvalid = s_axi_ddrc_arvalid ; - assign cl_sh_ddr_rready = s_axi_ddrc_rready ; - - assign s_axi_ddrc_awready = sh_cl_ddr_awready ; - assign s_axi_ddrc_wready = sh_cl_ddr_wready ; - assign s_axi_ddrc_bid = sh_cl_ddr_bid ; - assign s_axi_ddrc_bresp = sh_cl_ddr_bresp ; - assign s_axi_ddrc_bvalid = sh_cl_ddr_bvalid ; - assign s_axi_ddrc_arready = sh_cl_ddr_arready ; - assign s_axi_ddrc_rid = sh_cl_ddr_rid ; - assign s_axi_ddrc_rdata = sh_cl_ddr_rdata ; - assign s_axi_ddrc_rresp = sh_cl_ddr_rresp ; - assign s_axi_ddrc_rlast = sh_cl_ddr_rlast ; - assign s_axi_ddrc_rvalid = sh_cl_ddr_rvalid ; - assign ddrc_is_ready = sh_cl_ddr_is_ready ; - - assign cl_sh_ddr_wid = 0 ; - - assign cl_sda_awready = m_axi_sda_awready ; - assign cl_sda_wready = m_axi_sda_wready ; - assign cl_sda_bresp = m_axi_sda_bresp ; - assign cl_sda_bvalid = m_axi_sda_bvalid ; - assign cl_sda_arready = m_axi_sda_arready ; - assign cl_sda_rdata = m_axi_sda_rdata ; - assign cl_sda_rresp = m_axi_sda_rresp ; - assign cl_sda_rvalid = m_axi_sda_rvalid ; - - assign m_axi_sda_awaddr = sda_cl_awaddr ; - assign m_axi_sda_awvalid = sda_cl_awvalid ; - assign m_axi_sda_wdata = sda_cl_wdata ; - assign m_axi_sda_wstrb = sda_cl_wstrb ; - assign m_axi_sda_wvalid = sda_cl_wvalid ; - assign m_axi_sda_bready = sda_cl_bready ; - assign m_axi_sda_araddr = sda_cl_araddr ; - assign m_axi_sda_arvalid = sda_cl_arvalid ; - assign m_axi_sda_rready = sda_cl_rready ; - - assign ocl_sh_awready = m_axi_ocl_awready ; - assign ocl_sh_wready = m_axi_ocl_wready ; - assign ocl_sh_bresp = m_axi_ocl_bresp ; - assign ocl_sh_bvalid = m_axi_ocl_bvalid ; - assign ocl_sh_arready = m_axi_ocl_arready ; - assign ocl_sh_rdata = m_axi_ocl_rdata ; - assign ocl_sh_rresp = m_axi_ocl_rresp ; - assign ocl_sh_rvalid = m_axi_ocl_rvalid ; - - assign m_axi_ocl_awaddr = sh_ocl_awaddr ; - assign m_axi_ocl_awvalid = sh_ocl_awvalid ; - assign m_axi_ocl_wdata = sh_ocl_wdata ; - assign m_axi_ocl_wstrb = sh_ocl_wstrb ; - assign m_axi_ocl_wvalid = sh_ocl_wvalid ; - assign m_axi_ocl_bready = sh_ocl_bready ; - assign m_axi_ocl_araddr = sh_ocl_araddr ; - assign m_axi_ocl_arvalid = sh_ocl_arvalid ; - assign m_axi_ocl_rready = sh_ocl_rready ; - - assign bar1_sh_awready = m_axi_bar1_awready ; - assign bar1_sh_wready = m_axi_bar1_wready ; - assign bar1_sh_bresp = m_axi_bar1_bresp ; - assign bar1_sh_bvalid = m_axi_bar1_bvalid ; - assign bar1_sh_arready = m_axi_bar1_arready ; - assign bar1_sh_rdata = m_axi_bar1_rdata ; - assign bar1_sh_rresp = m_axi_bar1_rresp ; - assign bar1_sh_rvalid = m_axi_bar1_rvalid ; - - assign m_axi_bar1_awaddr = sh_bar1_awaddr ; - assign m_axi_bar1_awvalid = sh_bar1_awvalid ; - assign m_axi_bar1_wdata = sh_bar1_wdata ; - assign m_axi_bar1_wstrb = sh_bar1_wstrb ; - assign m_axi_bar1_wvalid = sh_bar1_wvalid ; - assign m_axi_bar1_bready = sh_bar1_bready ; - assign m_axi_bar1_araddr = sh_bar1_araddr ; - assign m_axi_bar1_arvalid = sh_bar1_arvalid ; - assign m_axi_bar1_rready = sh_bar1_rready ; - - assign cl_sh_dma_pcis_awready = m_axi_pcis_awready ; - assign cl_sh_dma_pcis_wready = m_axi_pcis_wready ; - assign cl_sh_dma_pcis_bid = m_axi_pcis_bid ; - assign cl_sh_dma_pcis_bresp = m_axi_pcis_bresp ; - assign cl_sh_dma_pcis_bvalid = m_axi_pcis_bvalid ; - assign cl_sh_dma_pcis_arready = m_axi_pcis_arready ; - assign cl_sh_dma_pcis_rid = m_axi_pcis_rid ; - assign cl_sh_dma_pcis_rdata = m_axi_pcis_rdata ; - assign cl_sh_dma_pcis_rresp = m_axi_pcis_rresp ; - assign cl_sh_dma_pcis_rlast = m_axi_pcis_rlast ; - assign cl_sh_dma_pcis_rvalid = m_axi_pcis_rvalid ; - - assign m_axi_pcis_awid = sh_cl_dma_pcis_awid ; - assign m_axi_pcis_awaddr = sh_cl_dma_pcis_awaddr ; - assign m_axi_pcis_awlen = sh_cl_dma_pcis_awlen ; - assign m_axi_pcis_awsize = sh_cl_dma_pcis_awsize ; - assign m_axi_pcis_awvalid = sh_cl_dma_pcis_awvalid ; - assign m_axi_pcis_wdata = sh_cl_dma_pcis_wdata ; - assign m_axi_pcis_wstrb = sh_cl_dma_pcis_wstrb ; - assign m_axi_pcis_wlast = sh_cl_dma_pcis_wlast ; - assign m_axi_pcis_wvalid = sh_cl_dma_pcis_wvalid ; - assign m_axi_pcis_bready = sh_cl_dma_pcis_bready ; - assign m_axi_pcis_arid = sh_cl_dma_pcis_arid ; - assign m_axi_pcis_araddr = sh_cl_dma_pcis_araddr ; - assign m_axi_pcis_arlen = sh_cl_dma_pcis_arlen ; - assign m_axi_pcis_arsize = sh_cl_dma_pcis_arsize ; - assign m_axi_pcis_arvalid = sh_cl_dma_pcis_arvalid ; - assign m_axi_pcis_rready = sh_cl_dma_pcis_rready ; - assign m_axi_pcis_awburst = 2'b01 ; - assign m_axi_pcis_arburst = 2'b01 ; - - assign cl_sh_pcim_awid = s_axi_pcim_awid ; - assign cl_sh_pcim_awaddr = s_axi_pcim_awaddr ; - assign cl_sh_pcim_awlen = s_axi_pcim_awlen ; - assign cl_sh_pcim_awsize = s_axi_pcim_awsize ; - assign cl_sh_pcim_awuser = s_axi_pcim_awuser ; - assign cl_sh_pcim_awvalid = s_axi_pcim_awvalid ; - assign cl_sh_pcim_wdata = s_axi_pcim_wdata ; - assign cl_sh_pcim_wstrb = s_axi_pcim_wstrb ; - assign cl_sh_pcim_wlast = s_axi_pcim_wlast ; - assign cl_sh_pcim_wvalid = s_axi_pcim_wvalid ; - assign cl_sh_pcim_bready = s_axi_pcim_bready ; - assign cl_sh_pcim_arid = s_axi_pcim_arid ; - assign cl_sh_pcim_araddr = s_axi_pcim_araddr ; - assign cl_sh_pcim_arlen = s_axi_pcim_arlen ; - assign cl_sh_pcim_arsize = s_axi_pcim_arsize ; - assign cl_sh_pcim_aruser = s_axi_pcim_aruser ; - assign cl_sh_pcim_arvalid = s_axi_pcim_arvalid ; - assign cl_sh_pcim_rready = s_axi_pcim_rready ; - - assign s_axi_pcim_awready = sh_cl_pcim_awready ; - assign s_axi_pcim_wready = sh_cl_pcim_wready ; - assign s_axi_pcim_bid = sh_cl_pcim_bid ; - assign s_axi_pcim_bresp = sh_cl_pcim_bresp ; - assign s_axi_pcim_bvalid = sh_cl_pcim_bvalid ; - assign s_axi_pcim_arready = sh_cl_pcim_arready ; - assign s_axi_pcim_rid = sh_cl_pcim_rid ; - assign s_axi_pcim_rdata = sh_cl_pcim_rdata ; - assign s_axi_pcim_rresp = sh_cl_pcim_rresp ; - assign s_axi_pcim_rlast = sh_cl_pcim_rlast ; - assign s_axi_pcim_rvalid = sh_cl_pcim_rvalid ; - assign cfg_max_payload_out = cfg_max_payload ; - assign cfg_max_read_req_out = cfg_max_read_req ; - - if ((C_MODE == 0) || (C_MODE == 1)) begin : gen_mem - - logic [15:0] cl_sh_ddr_awid_2d[2:0]; - logic [63:0] cl_sh_ddr_awaddr_2d[2:0]; - logic [7:0] cl_sh_ddr_awlen_2d[2:0]; - logic [2:0] cl_sh_ddr_awsize_2d[2:0]; - logic [1:0] cl_sh_ddr_awburst_2d[2:0]; - logic cl_sh_ddr_awvalid_2d[2:0]; - logic [2:0] sh_cl_ddr_awready_2d; - logic [15:0] cl_sh_ddr_wid_2d[2:0]; - logic [511:0] cl_sh_ddr_wdata_2d[2:0]; - logic [63:0] cl_sh_ddr_wstrb_2d[2:0]; - logic [2:0] cl_sh_ddr_wlast_2d; - logic [2:0] cl_sh_ddr_wvalid_2d; - logic [2:0] sh_cl_ddr_wready_2d; - logic [15:0] sh_cl_ddr_bid_2d[2:0]; - logic [1:0] sh_cl_ddr_bresp_2d[2:0]; - logic [2:0] sh_cl_ddr_bvalid_2d; - logic [2:0] cl_sh_ddr_bready_2d; - logic [15:0] cl_sh_ddr_arid_2d[2:0]; - logic [63:0] cl_sh_ddr_araddr_2d[2:0]; - logic [7:0] cl_sh_ddr_arlen_2d[2:0]; - logic [2:0] cl_sh_ddr_arsize_2d[2:0]; - logic [1:0] cl_sh_ddr_arburst_2d[2:0]; - logic [2:0] cl_sh_ddr_arvalid_2d; - logic [2:0] sh_cl_ddr_arready_2d; - logic [15:0] sh_cl_ddr_rid_2d[2:0]; - logic [511:0] sh_cl_ddr_rdata_2d[2:0]; - logic [1:0] sh_cl_ddr_rresp_2d[2:0]; - logic [2:0] sh_cl_ddr_rlast_2d; - logic [2:0] sh_cl_ddr_rvalid_2d; - logic [2:0] cl_sh_ddr_rready_2d; - logic [2:0] sh_cl_ddr_is_ready_2d; - - assign cl_sh_ddr_awid_2d[0] = s_axi_ddra_awid ; - assign cl_sh_ddr_awaddr_2d[0] = s_axi_ddra_awaddr ; - assign cl_sh_ddr_awlen_2d[0] = s_axi_ddra_awlen ; - assign cl_sh_ddr_awsize_2d[0] = s_axi_ddra_awsize ; - assign cl_sh_ddr_awburst_2d[0] = 2'b01 ; - assign cl_sh_ddr_awvalid_2d[0] = s_axi_ddra_awvalid ; - assign cl_sh_ddr_wid_2d[0] = 0 ; - assign cl_sh_ddr_wdata_2d[0] = s_axi_ddra_wdata ; - assign cl_sh_ddr_wstrb_2d[0] = s_axi_ddra_wstrb ; - assign cl_sh_ddr_wlast_2d[0] = s_axi_ddra_wlast ; - assign cl_sh_ddr_wvalid_2d[0] = s_axi_ddra_wvalid ; - assign cl_sh_ddr_bready_2d[0] = s_axi_ddra_bready ; - assign cl_sh_ddr_arid_2d[0] = s_axi_ddra_arid ; - assign cl_sh_ddr_araddr_2d[0] = s_axi_ddra_araddr ; - assign cl_sh_ddr_arlen_2d[0] = s_axi_ddra_arlen ; - assign cl_sh_ddr_arsize_2d[0] = s_axi_ddra_arsize ; - assign cl_sh_ddr_arburst_2d[0] = 2'b01 ; - assign cl_sh_ddr_arvalid_2d[0] = s_axi_ddra_arvalid ; - assign cl_sh_ddr_rready_2d[0] = s_axi_ddra_rready ; - - assign s_axi_ddra_awready = sh_cl_ddr_awready_2d[0] ; - assign s_axi_ddra_wready = sh_cl_ddr_wready_2d[0] ; - assign s_axi_ddra_bid = sh_cl_ddr_bid_2d[0] ; - assign s_axi_ddra_bresp = sh_cl_ddr_bresp_2d[0] ; - assign s_axi_ddra_bvalid = sh_cl_ddr_bvalid_2d[0] ; - assign s_axi_ddra_arready = sh_cl_ddr_arready_2d[0] ; - assign s_axi_ddra_rid = sh_cl_ddr_rid_2d[0] ; - assign s_axi_ddra_rdata = sh_cl_ddr_rdata_2d[0] ; - assign s_axi_ddra_rresp = sh_cl_ddr_rresp_2d[0] ; - assign s_axi_ddra_rlast = sh_cl_ddr_rlast_2d[0] ; - assign s_axi_ddra_rvalid = sh_cl_ddr_rvalid_2d[0] ; - assign ddra_is_ready = sh_cl_ddr_is_ready_2d[0]; - - assign cl_sh_ddr_awid_2d[1] = s_axi_ddrb_awid ; - assign cl_sh_ddr_awaddr_2d[1] = s_axi_ddrb_awaddr ; - assign cl_sh_ddr_awlen_2d[1] = s_axi_ddrb_awlen ; - assign cl_sh_ddr_awsize_2d[1] = s_axi_ddrb_awsize ; - assign cl_sh_ddr_awburst_2d[1] = 2'b01 ; - assign cl_sh_ddr_awvalid_2d[1] = s_axi_ddrb_awvalid ; - assign cl_sh_ddr_wid_2d[1] = 0 ; - assign cl_sh_ddr_wdata_2d[1] = s_axi_ddrb_wdata ; - assign cl_sh_ddr_wstrb_2d[1] = s_axi_ddrb_wstrb ; - assign cl_sh_ddr_wlast_2d[1] = s_axi_ddrb_wlast ; - assign cl_sh_ddr_wvalid_2d[1] = s_axi_ddrb_wvalid ; - assign cl_sh_ddr_bready_2d[1] = s_axi_ddrb_bready ; - assign cl_sh_ddr_arid_2d[1] = s_axi_ddrb_arid ; - assign cl_sh_ddr_araddr_2d[1] = s_axi_ddrb_araddr ; - assign cl_sh_ddr_arlen_2d[1] = s_axi_ddrb_arlen ; - assign cl_sh_ddr_arsize_2d[1] = s_axi_ddrb_arsize ; - assign cl_sh_ddr_arburst_2d[1] = 2'b01 ; - assign cl_sh_ddr_arvalid_2d[1] = s_axi_ddrb_arvalid ; - assign cl_sh_ddr_rready_2d[1] = s_axi_ddrb_rready ; - - assign s_axi_ddrb_awready = sh_cl_ddr_awready_2d[1] ; - assign s_axi_ddrb_wready = sh_cl_ddr_wready_2d[1] ; - assign s_axi_ddrb_bid = sh_cl_ddr_bid_2d[1] ; - assign s_axi_ddrb_bresp = sh_cl_ddr_bresp_2d[1] ; - assign s_axi_ddrb_bvalid = sh_cl_ddr_bvalid_2d[1] ; - assign s_axi_ddrb_arready = sh_cl_ddr_arready_2d[1] ; - assign s_axi_ddrb_rid = sh_cl_ddr_rid_2d[1] ; - assign s_axi_ddrb_rdata = sh_cl_ddr_rdata_2d[1] ; - assign s_axi_ddrb_rresp = sh_cl_ddr_rresp_2d[1] ; - assign s_axi_ddrb_rlast = sh_cl_ddr_rlast_2d[1] ; - assign s_axi_ddrb_rvalid = sh_cl_ddr_rvalid_2d[1] ; - assign ddrb_is_ready = sh_cl_ddr_is_ready_2d[1]; - - assign cl_sh_ddr_awid_2d[2] = s_axi_ddrd_awid ; - assign cl_sh_ddr_awaddr_2d[2] = s_axi_ddrd_awaddr ; - assign cl_sh_ddr_awlen_2d[2] = s_axi_ddrd_awlen ; - assign cl_sh_ddr_awsize_2d[2] = s_axi_ddrd_awsize ; - assign cl_sh_ddr_awburst_2d[2] = 2'b01 ; - assign cl_sh_ddr_awvalid_2d[2] = s_axi_ddrd_awvalid ; - assign cl_sh_ddr_wid_2d[2] = 0 ; - assign cl_sh_ddr_wdata_2d[2] = s_axi_ddrd_wdata ; - assign cl_sh_ddr_wstrb_2d[2] = s_axi_ddrd_wstrb ; - assign cl_sh_ddr_wlast_2d[2] = s_axi_ddrd_wlast ; - assign cl_sh_ddr_wvalid_2d[2] = s_axi_ddrd_wvalid ; - assign cl_sh_ddr_bready_2d[2] = s_axi_ddrd_bready ; - assign cl_sh_ddr_arid_2d[2] = s_axi_ddrd_arid ; - assign cl_sh_ddr_araddr_2d[2] = s_axi_ddrd_araddr ; - assign cl_sh_ddr_arlen_2d[2] = s_axi_ddrd_arlen ; - assign cl_sh_ddr_arsize_2d[2] = s_axi_ddrd_arsize ; - assign cl_sh_ddr_arburst_2d[2] = 2'b01 ; - assign cl_sh_ddr_arvalid_2d[2] = s_axi_ddrd_arvalid ; - assign cl_sh_ddr_rready_2d[2] = s_axi_ddrd_rready ; - - assign s_axi_ddrd_awready = sh_cl_ddr_awready_2d[2] ; - assign s_axi_ddrd_wready = sh_cl_ddr_wready_2d[2] ; - assign s_axi_ddrd_bid = sh_cl_ddr_bid_2d[2] ; - assign s_axi_ddrd_bresp = sh_cl_ddr_bresp_2d[2] ; - assign s_axi_ddrd_bvalid = sh_cl_ddr_bvalid_2d[2] ; - assign s_axi_ddrd_arready = sh_cl_ddr_arready_2d[2] ; - assign s_axi_ddrd_rid = sh_cl_ddr_rid_2d[2] ; - assign s_axi_ddrd_rdata = sh_cl_ddr_rdata_2d[2] ; - assign s_axi_ddrd_rresp = sh_cl_ddr_rresp_2d[2] ; - assign s_axi_ddrd_rlast = sh_cl_ddr_rlast_2d[2] ; - assign s_axi_ddrd_rvalid = sh_cl_ddr_rvalid_2d[2] ; - assign ddrd_is_ready = sh_cl_ddr_is_ready_2d[2]; - - logic ddr_aws_stat_ack0; - logic [31:0] ddr_aws_stat_rdata0; - logic [7:0] ddr_aws_stat_int0; - logic ddr_aws_stat_ack1; - logic [31:0] ddr_aws_stat_rdata1; - logic [7:0] ddr_aws_stat_int1; - logic ddr_aws_stat_ack2; - logic [31:0] ddr_aws_stat_rdata2; - logic [7:0] ddr_aws_stat_int2; - - logic [7:0] pipe_ddr_stat_addr0; - logic pipe_ddr_stat_wr0; - logic pipe_ddr_stat_rd0; - logic [31:0] pipe_ddr_stat_wdata0; - logic ddr_pipe_stat_ack0; - logic [31:0] ddr_pipe_stat_rdata0; - logic [7:0] ddr_pipe_stat_int0; - - logic [7:0] pipe_ddr_stat_addr1; - logic pipe_ddr_stat_wr1; - logic pipe_ddr_stat_rd1; - logic [31:0] pipe_ddr_stat_wdata1; - logic ddr_pipe_stat_ack1; - logic [31:0] ddr_pipe_stat_rdata1; - logic [7:0] ddr_pipe_stat_int1; - - logic [7:0] pipe_ddr_stat_addr2; - logic pipe_ddr_stat_wr2; - logic pipe_ddr_stat_rd2; - logic [31:0] pipe_ddr_stat_wdata2; - logic ddr_pipe_stat_ack2; - logic [31:0] ddr_pipe_stat_rdata2; - logic [7:0] ddr_pipe_stat_int2; - -//------------------------------------------------- -// Tie-offs when DDRs are disabled -//------------------------------------------------- - assign ddr_sh_stat_ack0 = (C_DDR_A_PRESENT!=0) ? ddr_aws_stat_ack0 : 1'b1; - assign ddr_sh_stat_rdata0 = (C_DDR_A_PRESENT!=0) ? ddr_aws_stat_rdata0 : 0; - assign ddr_sh_stat_int0 = (C_DDR_A_PRESENT!=0) ? ddr_aws_stat_int0 : 8'b0; - assign ddr_sh_stat_ack1 = (C_DDR_B_PRESENT!=0) ? ddr_aws_stat_ack1 : 1'b1; - assign ddr_sh_stat_rdata1 = (C_DDR_B_PRESENT!=0) ? ddr_aws_stat_rdata1 : 0; - assign ddr_sh_stat_int1 = (C_DDR_B_PRESENT!=0) ? ddr_aws_stat_int1 : 8'b0; - assign ddr_sh_stat_ack2 = (C_DDR_D_PRESENT!=0) ? ddr_aws_stat_ack2 : 1'b1; - assign ddr_sh_stat_rdata2 = (C_DDR_D_PRESENT!=0) ? ddr_aws_stat_rdata2 : 0; - assign ddr_sh_stat_int2 = (C_DDR_D_PRESENT!=0) ? ddr_aws_stat_int2 : 8'b0; - -//------------------------------------------------- -// Reset Synchronization -//------------------------------------------------- - logic pre_sync_rst_n; - logic sync_rst_n; - - always @(negedge rst_main_n or posedge clk_main_a0) begin - if (!rst_main_n) begin - pre_sync_rst_n <= 1'b0; - sync_rst_n <= 1'b0; - end else begin - pre_sync_rst_n <= 1'b1; - sync_rst_n <= pre_sync_rst_n; - end - end - - `ifdef FPGA_LESS_RST - `undef FPGA_LESS_RST - `endif - - lib_pipe #(.WIDTH(32), .STAGES(C_NUM_STAGES_STATS)) pipe_stat_wdata0 (.clk(clk_main_a0), .rst_n(1'b1), .in_bus(sh_ddr_stat_wdata0), .out_bus(pipe_ddr_stat_wdata0)); - lib_pipe #(.WIDTH(8), .STAGES(C_NUM_STAGES_STATS)) pipe_stat_addr0 (.clk(clk_main_a0), .rst_n(1'b1), .in_bus(sh_ddr_stat_addr0), .out_bus(pipe_ddr_stat_addr0)); - lib_pipe #(.WIDTH(1), .STAGES(C_NUM_STAGES_STATS)) pipe_stat_wr0 (.clk(clk_main_a0), .rst_n(sync_rst_n), .in_bus(sh_ddr_stat_wr0), .out_bus(pipe_ddr_stat_wr0)); - lib_pipe #(.WIDTH(1), .STAGES(C_NUM_STAGES_STATS)) pipe_stat_rd0 (.clk(clk_main_a0), .rst_n(sync_rst_n), .in_bus(sh_ddr_stat_rd0), .out_bus(pipe_ddr_stat_rd0)); - lib_pipe #(.WIDTH(32), .STAGES(C_NUM_STAGES_STATS)) pipe_stat_rdata0 (.clk(clk_main_a0), .rst_n(1'b1), .out_bus(ddr_aws_stat_rdata0), .in_bus(ddr_pipe_stat_rdata0)); - lib_pipe #(.WIDTH(1), .STAGES(C_NUM_STAGES_STATS)) pipe_stat_ack0 (.clk(clk_main_a0), .rst_n(sync_rst_n), .out_bus(ddr_aws_stat_ack0), .in_bus(ddr_pipe_stat_ack0)); - lib_pipe #(.WIDTH(8), .STAGES(C_NUM_STAGES_STATS)) pipe_stat_int0 (.clk(clk_main_a0), .rst_n(sync_rst_n), .out_bus(ddr_aws_stat_int0), .in_bus(ddr_pipe_stat_int0)); - - lib_pipe #(.WIDTH(32), .STAGES(C_NUM_STAGES_STATS)) pipe_stat_wdata1 (.clk(clk_main_a0), .rst_n(1'b1), .in_bus(sh_ddr_stat_wdata1), .out_bus(pipe_ddr_stat_wdata1)); - lib_pipe #(.WIDTH(8), .STAGES(C_NUM_STAGES_STATS)) pipe_stat_addr1 (.clk(clk_main_a0), .rst_n(1'b1), .in_bus(sh_ddr_stat_addr1), .out_bus(pipe_ddr_stat_addr1)); - lib_pipe #(.WIDTH(1), .STAGES(C_NUM_STAGES_STATS)) pipe_stat_wr1 (.clk(clk_main_a0), .rst_n(sync_rst_n), .in_bus(sh_ddr_stat_wr1), .out_bus(pipe_ddr_stat_wr1)); - lib_pipe #(.WIDTH(1), .STAGES(C_NUM_STAGES_STATS)) pipe_stat_rd1 (.clk(clk_main_a0), .rst_n(sync_rst_n), .in_bus(sh_ddr_stat_rd1), .out_bus(pipe_ddr_stat_rd1)); - lib_pipe #(.WIDTH(32), .STAGES(C_NUM_STAGES_STATS)) pipe_stat_rdata1 (.clk(clk_main_a0), .rst_n(1'b1), .out_bus(ddr_aws_stat_rdata1), .in_bus(ddr_pipe_stat_rdata1)); - lib_pipe #(.WIDTH(1), .STAGES(C_NUM_STAGES_STATS)) pipe_stat_ack1 (.clk(clk_main_a0), .rst_n(sync_rst_n), .out_bus(ddr_aws_stat_ack1), .in_bus(ddr_pipe_stat_ack1)); - lib_pipe #(.WIDTH(8), .STAGES(C_NUM_STAGES_STATS)) pipe_stat_int1 (.clk(clk_main_a0), .rst_n(sync_rst_n), .out_bus(ddr_aws_stat_int1), .in_bus(ddr_pipe_stat_int1)); - - lib_pipe #(.WIDTH(32), .STAGES(C_NUM_STAGES_STATS)) pipe_stat_wdata2 (.clk(clk_main_a0), .rst_n(1'b1), .in_bus(sh_ddr_stat_wdata2), .out_bus(pipe_ddr_stat_wdata2)); - lib_pipe #(.WIDTH(8), .STAGES(C_NUM_STAGES_STATS)) pipe_stat_addr2 (.clk(clk_main_a0), .rst_n(1'b1), .in_bus(sh_ddr_stat_addr2), .out_bus(pipe_ddr_stat_addr2)); - lib_pipe #(.WIDTH(1), .STAGES(C_NUM_STAGES_STATS)) pipe_stat_wr2 (.clk(clk_main_a0), .rst_n(sync_rst_n), .in_bus(sh_ddr_stat_wr2), .out_bus(pipe_ddr_stat_wr2)); - lib_pipe #(.WIDTH(1), .STAGES(C_NUM_STAGES_STATS)) pipe_stat_rd2 (.clk(clk_main_a0), .rst_n(sync_rst_n), .in_bus(sh_ddr_stat_rd2), .out_bus(pipe_ddr_stat_rd2)); - lib_pipe #(.WIDTH(32), .STAGES(C_NUM_STAGES_STATS)) pipe_stat_rdata2 (.clk(clk_main_a0), .rst_n(1'b1), .out_bus(ddr_aws_stat_rdata2), .in_bus(ddr_pipe_stat_rdata2)); - lib_pipe #(.WIDTH(1), .STAGES(C_NUM_STAGES_STATS)) pipe_stat_ack2 (.clk(clk_main_a0), .rst_n(sync_rst_n), .out_bus(ddr_aws_stat_ack2), .in_bus(ddr_pipe_stat_ack2)); - lib_pipe #(.WIDTH(8), .STAGES(C_NUM_STAGES_STATS)) pipe_stat_int2 (.clk(clk_main_a0), .rst_n(sync_rst_n), .out_bus(ddr_aws_stat_int2), .in_bus(ddr_pipe_stat_int2)); - - sh_ddr #( - .DDR_A_PRESENT(C_DDR_A_PRESENT), - .DDR_B_PRESENT(C_DDR_B_PRESENT), - .DDR_D_PRESENT(C_DDR_D_PRESENT) - ) sh_ddr_0 - ( - .clk(clk_main_a0), - .rst_n(sync_rst_n), - - .stat_clk(clk_main_a0), - .stat_rst_n(sync_rst_n), - - .CLK_300M_DIMM0_DP(CLK_300M_DIMM0_DP), - .CLK_300M_DIMM0_DN(CLK_300M_DIMM0_DN), - .M_A_ACT_N(M_A_ACT_N), - .M_A_MA(M_A_MA), - .M_A_BA(M_A_BA), - .M_A_BG(M_A_BG), - .M_A_CKE(M_A_CKE), - .M_A_ODT(M_A_ODT), - .M_A_CS_N(M_A_CS_N), - .M_A_CLK_DN(M_A_CLK_DN), - .M_A_CLK_DP(M_A_CLK_DP), - .M_A_PAR(M_A_PAR), - .M_A_DQ(M_A_DQ), - .M_A_ECC(M_A_ECC), - .M_A_DQS_DP(M_A_DQS_DP), - .M_A_DQS_DN(M_A_DQS_DN), - .cl_RST_DIMM_A_N(cl_RST_DIMM_A_N), - - .CLK_300M_DIMM1_DP(CLK_300M_DIMM1_DP), - .CLK_300M_DIMM1_DN(CLK_300M_DIMM1_DN), - .M_B_ACT_N(M_B_ACT_N), - .M_B_MA(M_B_MA), - .M_B_BA(M_B_BA), - .M_B_BG(M_B_BG), - .M_B_CKE(M_B_CKE), - .M_B_ODT(M_B_ODT), - .M_B_CS_N(M_B_CS_N), - .M_B_CLK_DN(M_B_CLK_DN), - .M_B_CLK_DP(M_B_CLK_DP), - .M_B_PAR(M_B_PAR), - .M_B_DQ(M_B_DQ), - .M_B_ECC(M_B_ECC), - .M_B_DQS_DP(M_B_DQS_DP), - .M_B_DQS_DN(M_B_DQS_DN), - .cl_RST_DIMM_B_N(cl_RST_DIMM_B_N), - - .CLK_300M_DIMM3_DP(CLK_300M_DIMM3_DP), - .CLK_300M_DIMM3_DN(CLK_300M_DIMM3_DN), - .M_D_ACT_N(M_D_ACT_N), - .M_D_MA(M_D_MA), - .M_D_BA(M_D_BA), - .M_D_BG(M_D_BG), - .M_D_CKE(M_D_CKE), - .M_D_ODT(M_D_ODT), - .M_D_CS_N(M_D_CS_N), - .M_D_CLK_DN(M_D_CLK_DN), - .M_D_CLK_DP(M_D_CLK_DP), - .M_D_PAR(M_D_PAR), - .M_D_DQ(M_D_DQ), - .M_D_ECC(M_D_ECC), - .M_D_DQS_DP(M_D_DQS_DP), - .M_D_DQS_DN(M_D_DQS_DN), - .cl_RST_DIMM_D_N(cl_RST_DIMM_D_N), - - //------------------------------------------------------ - // AXI Slave Interfaces - //------------------------------------------------------ - .cl_sh_ddr_awid(cl_sh_ddr_awid_2d), - .cl_sh_ddr_awaddr(cl_sh_ddr_awaddr_2d), - .cl_sh_ddr_awlen(cl_sh_ddr_awlen_2d), - .cl_sh_ddr_awsize(cl_sh_ddr_awsize_2d), - .cl_sh_ddr_awburst(cl_sh_ddr_awburst_2d), - .cl_sh_ddr_awvalid(cl_sh_ddr_awvalid_2d), - .sh_cl_ddr_awready(sh_cl_ddr_awready_2d), - - .cl_sh_ddr_wid(cl_sh_ddr_wid_2d), - .cl_sh_ddr_wdata(cl_sh_ddr_wdata_2d), - .cl_sh_ddr_wstrb(cl_sh_ddr_wstrb_2d), - .cl_sh_ddr_wlast(cl_sh_ddr_wlast_2d), - .cl_sh_ddr_wvalid(cl_sh_ddr_wvalid_2d), - .sh_cl_ddr_wready(sh_cl_ddr_wready_2d), - - .sh_cl_ddr_bid(sh_cl_ddr_bid_2d), - .sh_cl_ddr_bresp(sh_cl_ddr_bresp_2d), - .sh_cl_ddr_bvalid(sh_cl_ddr_bvalid_2d), - .cl_sh_ddr_bready(cl_sh_ddr_bready_2d), - - .cl_sh_ddr_arid(cl_sh_ddr_arid_2d), - .cl_sh_ddr_araddr(cl_sh_ddr_araddr_2d), - .cl_sh_ddr_arlen(cl_sh_ddr_arlen_2d), - .cl_sh_ddr_arsize(cl_sh_ddr_arsize_2d), - .cl_sh_ddr_arburst(cl_sh_ddr_arburst_2d), - .cl_sh_ddr_arvalid(cl_sh_ddr_arvalid_2d), - .sh_cl_ddr_arready(sh_cl_ddr_arready_2d), - - .sh_cl_ddr_rid(sh_cl_ddr_rid_2d), - .sh_cl_ddr_rdata(sh_cl_ddr_rdata_2d), - .sh_cl_ddr_rresp(sh_cl_ddr_rresp_2d), - .sh_cl_ddr_rlast(sh_cl_ddr_rlast_2d), - .sh_cl_ddr_rvalid(sh_cl_ddr_rvalid_2d), - .cl_sh_ddr_rready(cl_sh_ddr_rready_2d), - - .sh_cl_ddr_is_ready(sh_cl_ddr_is_ready_2d), - - .sh_ddr_stat_addr0 (pipe_ddr_stat_addr0 ), - .sh_ddr_stat_wr0 (pipe_ddr_stat_wr0 ), - .sh_ddr_stat_rd0 (pipe_ddr_stat_rd0 ), - .sh_ddr_stat_wdata0 (pipe_ddr_stat_wdata0), - .ddr_sh_stat_ack0 (ddr_pipe_stat_ack0 ), - .ddr_sh_stat_rdata0 (ddr_pipe_stat_rdata0), - .ddr_sh_stat_int0 (ddr_pipe_stat_int0 ), - - .sh_ddr_stat_addr1 (pipe_ddr_stat_addr1 ), - .sh_ddr_stat_wr1 (pipe_ddr_stat_wr1 ), - .sh_ddr_stat_rd1 (pipe_ddr_stat_rd1 ), - .sh_ddr_stat_wdata1 (pipe_ddr_stat_wdata1), - .ddr_sh_stat_ack1 (ddr_pipe_stat_ack1 ), - .ddr_sh_stat_rdata1 (ddr_pipe_stat_rdata1), - .ddr_sh_stat_int1 (ddr_pipe_stat_int1 ), - - .sh_ddr_stat_addr2 (pipe_ddr_stat_addr2 ), - .sh_ddr_stat_wr2 (pipe_ddr_stat_wr2 ), - .sh_ddr_stat_rd2 (pipe_ddr_stat_rd2 ), - .sh_ddr_stat_wdata2 (pipe_ddr_stat_wdata2), - .ddr_sh_stat_ack2 (ddr_pipe_stat_ack2 ), - .ddr_sh_stat_rdata2 (ddr_pipe_stat_rdata2), - .ddr_sh_stat_int2 (ddr_pipe_stat_int2 ) - - ); - - end else begin : gen_non_mem - - assign s_axi_ddra_awready = 0; - assign s_axi_ddra_wready = 0; - assign s_axi_ddra_bid = 0; - assign s_axi_ddra_bresp = 0; - assign s_axi_ddra_bvalid = 0; - assign s_axi_ddra_arready = 0; - assign s_axi_ddra_rid = 0; - assign s_axi_ddra_rdata = 0; - assign s_axi_ddra_rresp = 0; - assign s_axi_ddra_rlast = 1'b1; - assign s_axi_ddra_rvalid = 0; - assign ddra_is_ready = 0; - - assign s_axi_ddrb_awready = 0; - assign s_axi_ddrb_wready = 0; - assign s_axi_ddrb_bid = 0; - assign s_axi_ddrb_bresp = 0; - assign s_axi_ddrb_bvalid = 0; - assign s_axi_ddrb_arready = 0; - assign s_axi_ddrb_rid = 0; - assign s_axi_ddrb_rdata = 0; - assign s_axi_ddrb_rresp = 0; - assign s_axi_ddrb_rlast = 1'b1; - assign s_axi_ddrb_rvalid = 0; - assign ddrb_is_ready = 0; - - assign s_axi_ddrd_awready = 0; - assign s_axi_ddrd_wready = 0; - assign s_axi_ddrd_bid = 0; - assign s_axi_ddrd_bresp = 0; - assign s_axi_ddrd_bvalid = 0; - assign s_axi_ddrd_arready = 0; - assign s_axi_ddrd_rid = 0; - assign s_axi_ddrd_rdata = 0; - assign s_axi_ddrd_rresp = 0; - assign s_axi_ddrd_rlast = 1'b1; - assign s_axi_ddrd_rvalid = 0; - assign ddrd_is_ready = 0; - - assign ddr_sh_stat_ack0 = 1'b1; - assign ddr_sh_stat_rdata0 = 0; - assign ddr_sh_stat_int0 = 8'b0; - assign ddr_sh_stat_ack1 = 1'b1; - assign ddr_sh_stat_rdata1 = 0; - assign ddr_sh_stat_int1 = 8'b0; - assign ddr_sh_stat_ack2 = 1'b1; - assign ddr_sh_stat_rdata2 = 0; - assign ddr_sh_stat_int2 = 8'b0; - - assign M_A_ACT_N = 0; - assign M_A_MA = 0; - assign M_A_BA = 0; - assign M_A_BG = 0; - assign M_A_CKE = 0; - assign M_A_ODT = 0; - assign M_A_CS_N = 0; - assign M_A_CLK_DN = 0; - assign M_A_CLK_DP = 0; - assign M_A_PAR = 0; - assign cl_RST_DIMM_A_N = 0; - - assign M_B_ACT_N = 0; - assign M_B_MA = 0; - assign M_B_BA = 0; - assign M_B_BG = 0; - assign M_B_CKE = 0; - assign M_B_ODT = 0; - assign M_B_CS_N = 0; - assign M_B_CLK_DN = 0; - assign M_B_CLK_DP = 0; - assign M_B_PAR = 0; - assign cl_RST_DIMM_B_N = 0; - - assign M_D_ACT_N = 0; - assign M_D_MA = 0; - assign M_D_BA = 0; - assign M_D_BG = 0; - assign M_D_CKE = 0; - assign M_D_ODT = 0; - assign M_D_CS_N = 0; - assign M_D_CLK_DN = 0; - assign M_D_CLK_DP = 0; - assign M_D_PAR = 0; - assign cl_RST_DIMM_D_N = 0; - - end // gen_mem - endgenerate - -endmodule - - diff --git a/hdk/common/shell_v04261818/hlx/design/ip/aws_v1_0/hdl/lib_pipe.sv b/hdk/common/shell_v04261818/hlx/design/ip/aws_v1_0/hdl/lib_pipe.sv new file mode 120000 index 000000000..c55fd5431 --- /dev/null +++ b/hdk/common/shell_v04261818/hlx/design/ip/aws_v1_0/hdl/lib_pipe.sv @@ -0,0 +1 @@ +../../../../../design/lib/lib_pipe.sv \ No newline at end of file diff --git a/hdk/common/shell_v04261818/hlx/design/ip/aws_v1_0/hdl/sim b/hdk/common/shell_v04261818/hlx/design/ip/aws_v1_0/hdl/sim new file mode 120000 index 000000000..4eb7f5aee --- /dev/null +++ b/hdk/common/shell_v04261818/hlx/design/ip/aws_v1_0/hdl/sim @@ -0,0 +1 @@ +../../../../../design/sh_ddr/sim \ No newline at end of file diff --git a/hdk/common/shell_v04261818/hlx/design/ip/aws_v1_0/hdl/sim/gray.inc b/hdk/common/shell_v04261818/hlx/design/ip/aws_v1_0/hdl/sim/gray.inc deleted file mode 100755 index 35e3b5ac3..000000000 --- a/hdk/common/shell_v04261818/hlx/design/ip/aws_v1_0/hdl/sim/gray.inc +++ /dev/null @@ -1,54 +0,0 @@ -// SHA: bddf8457046b3a64e63d28d7e334020b6f1d09ee -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "XILINX" -`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2015" -`pragma protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2017_05", key_method = "rsa" -`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) -`pragma protect key_block -iWZCE953hJCDyIc+ne+gwzh8qXsoHncv0uZD9mD+v5fx+PEpRYsrUwVcqY8NGks/8KrnC1SNztDZ -curQivQImMnSoAGPeG2bNV8bmkBS1rhgCF+dM7tLc6A2UDWpvGzLUBwtZEoYGo9qI/brjagfJ4AB -rEXslIMBpU4DM78ZslW+HuM6LGQaxRCRc5YmcX9lULqKp4gcYejmK7bNBZVoMQPaxbOJKJ6Shm8B -OwZERFn7ecS2YTdmKNHaXgTG11pozaLBWmvQ9dAoBbjBP2u9av9r72qQ/x/sB/rBhukAV1tbxMRT -N5VdaW8njTW1/BmqfN0EYNrisu9/VrhCD8CpOw== - -`pragma protect data_method = "AES128-CBC" -`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 2048) -`pragma protect data_block -kJG/xGGs9D/8k2u3JRVp+XhN8w/W2vao3+RyPdGKa2ielHnUCL6Wf5zeKZvunCPxvE+hY4IzwA3A -wigLpWB1GOP6DyilyJ2bV2zhnBCaKdy+sFGQK2AzyHbMPzKs/Ubz1cWrjh6Jcdp+x7Wl6gnlaHmm -C6KgAmVndCZq6vvWz4TzJpiMaoUt8ge+9MvH1ILAiY5mdQk8SA9G9EnSNdGDfC8Qe+hAMW0ttojk -f04YI1slnd2P1kOSfMve5S1SG6p2NyrTQR/dOSRVfWgY4tzGGMBPPsf4SE2IDpA+/2vOC+FLNBhd -xa57bmlMKsW3u0KXGvtjziIxPzWYRt5wl3/6MpPPTR3jKfxlfT+y5iP19sf4otY1AYhFc7+Jz4+q -Wm7eM7ZCz75nYMrfbJsiPnEskhdbpqSKb4gbKLLSwYu8I6zrl8/KMBIsKSdDK2YQiFrUtH2pWpp3 -7GYqqwBtYcFQB66ouMrQVA4q+ihCg0WtFf+5LpFri1Cy5khHYCDA2T0Cj06nwDTK9P7PS0axtUli -1PFd+O9zh72LvJ8Ayr+H/vZLeFdvf15XP1DGfzcDf83nWk3lINWwdxQ6BDGyKCp1x5rz9BSLpKKF -U2GzDlX8RcGGYQoli/JUZA8qX8be1ele/nXV/Ml/60KLS+L+Lrr0TzzFuCjU5xek/jO6w3+/e5D9 -ftBYgkZyeXr7nYiIM7X0zkkdMGrsDu2uhKKrvCe4x5IakCs9osJhpqCj4mRdENY1GEMxLv1q/4NS -tMo6k3LWn6pAfTPvHZlSvjdkP3JRNKrLFObdtaqGs4/TgTh6HtlG3PTskPeRmU6XF+jQoW249M3x -jJoW5N32GZlP8PlSRUnr9pUUHZ+ysjkUNjBrmmSV0F091Fyy8gqV688MkjrN2mQVcPO2G/EiJ4Kn -z2RnciR5HBjJVzkUA2rZR8pjz2n5htUIY8/+O14sYbEPFakdH0JKGpNPimxPcOkczl6xtGsbhiD1 -MftzBA2MxWF9lwRtNp1op3ugvZerTcQ7ftERBTzrV3AU7btg17E6iWiFUty3r+ToY6rzD5n8ZSOY -N1ji41hc1VpTMxrYty33ejc2GruqxpW7O6iZyQ4q7nXYZpt3K84119Au2avjVTunErpwN30qgOxR -Cw1HLyxIqmft7QUz74FiYnPS9s2A13hRVQ29TYLf+X46vBfHdO5kTFIKu+eNH0PQ9I9CcXBnUrHj -Mo26d3+JtSZGPO6Hm356Ur45Waq0+l5mm3YbfgqMESCPUQfzTfSVF4PN4DAU5Hv8HPB6H7y5le5q -QGBbza/nPgLnY546FMEbAczzR2A6eefQ2chEKdoTH3OT5rlMZZqBiK4ZHToaQYXWKTih0DoJMV0U -5pCpeoLoErMEqP0S+wcvA3zQkA0YqXc2KDkrovZgTyyaPgdC8YzghEmlxMq8DQs8ikdVy3hdfYob -8QWNYdrgVk781vc8DXNU3mHZ0jEZQYaaTZV5ZlBGtJzWngGmWwMoL0F29f3LdlZAhERnFbejR/eZ -UBXXBzgj5nrM2Fr+RlAowrjFcs/nr32fkCSfpnl9r77NtqxX4CnTBhLe7c4WSm+4Etah0DGdI7Gh -JVKmqaeEhXaB2f/QlCabxSheicrWkLWBUD3TG/j33ZwcHjs3r56T/YsYLfPmXxz5MZpZus6kp7oz -7TOqe9WlXjsAw4SEDPEZhbcPu8kxzbqdq+O8E0FJjBXNhqgkNmhOmJdxgpGODASsM8WGOLsDILOb -TmcS7J94JWDDI5E8v2XGhrGSvRPpQI4s7SS7Q1i457UZzrHM8wTTCq6ONvI3jGeEKlaCcbGTAWYD -3/Rc7CpZO3vho08wcgRVlAeozKLfiqrnyk/fyx1M6pESrKQUYHzPf2uXUaEH2qHZpBOABoyVhT7M -tXxZL6KImwr/UKLb4WQpsCV8txdAHSojgCjEahgloM/yQQyNFDBmYfG2yQGxeGgXGgCneDNvdmXq -zo8SmZGuEU6583y2Af6rwXWuvfMcByzcBDUkVXO3WBXfBoG94KJBhHo40FXVrfVwpVjeEBXakwKy -B0NarE4jj5uofWkKhaUEYIhVvPV6fmR0DUlyt6DW6zJXNDe1dsgfs2jw6I6N2ffgzX4IXyMpOh48 -Xz/DaHENQArcIhlJL8za5WIoZROdtYf2sfL0Jlnl6rwzcwXEFIBZfSeheWkoP+wTUM5tKsbiB1xV -2eUJshGm2lnAIWhRLn4baHxeDSMtIjYTGwkVmgF/N8uAPr5UkrofL5GiVA3iWXtTdpA3gSVbe+U2 -Fsw4SarJJp+PbTjgPh6dP+KdrOjVGXM7KV0KAr6qV+woPXK7GAxsj9CTepwf+5pOq0N7fGsc1GH0 -8GdvwfmbELp3tXvI0emNI9dy7Zl40gDneqnqZPbWRMqPi911iT/1BxGo0LzeGDquUXbRPj9xm7sH -qPdkoIIENexwsxeLugkSs9+/K+S4rkwkVsG/1zx7GzZ+SOWpU0sXkHIq7+wPJ04/OVjyzrubRCxt -6VgTKH6NZwIkFBEcxLP7UzhV5x5RgPGi3qmissvhCBWtyKJomwqVhX0ozi0QLYOIUMFx9ftAAHQF -fXrlhhz9DKLH8khVKAUcqCreXnSyHY/FxanjBnzovfxUl3XzDYxv5oPPbu6LT37jDNOqw6cRAuMP -fedDSu42Dymfn7IPAwV0tBVMFbxNSO8Q87Nl9Oz19SSqCJS3meV0MZd+KYQyM3LEb545tts= -`pragma protect end_protected diff --git a/hdk/common/shell_v04261818/hlx/design/ip/aws_v1_0/hdl/synth b/hdk/common/shell_v04261818/hlx/design/ip/aws_v1_0/hdl/synth new file mode 120000 index 000000000..85198b6a3 --- /dev/null +++ b/hdk/common/shell_v04261818/hlx/design/ip/aws_v1_0/hdl/synth @@ -0,0 +1 @@ +../../../../../design/sh_ddr/synth \ No newline at end of file diff --git a/hdk/common/shell_v04261818/hlx/design/ip/aws_v1_0/hdl/synth/gray.inc b/hdk/common/shell_v04261818/hlx/design/ip/aws_v1_0/hdl/synth/gray.inc deleted file mode 100755 index d15760163..000000000 --- a/hdk/common/shell_v04261818/hlx/design/ip/aws_v1_0/hdl/synth/gray.inc +++ /dev/null @@ -1,61 +0,0 @@ -// SHA: bddf8457046b3a64e63d28d7e334020b6f1d09ee -`pragma protect begin_protected -`pragma protect version = 2 -`pragma protect encrypt_agent = "XILINX" -`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2015" -`pragma protect begin_commonblock -`pragma protect control error_handling="delegated" -`pragma protect end_commonblock -`pragma protect begin_toolblock -`pragma protect rights_digest_method="sha256" -`pragma protect key_keyowner = "Xilinx", key_keyname= "xilinxt_2017_05", key_method = "rsa", key_block -GQ3cf/VGHY0xKfRLLTPQZDazEA3OyQ5p2SCdrSlmdPjCM7yE2VcditpKLLWOfn5+0jtL5Uy85K3Z -RJNHMY3ze7jXvEClcJ2Vzp4fwkFCOlM/vh4YGp9wET1CUY56wndycOW/RlHrhiqDq2bXfR7NoD8w -aUaWced9KaFJ122f3nIBhocYiGlY/mHq0LOkoyK9v0rxbrTOm4QTm9WMLhpFX5+pN2RWspU3lhH4 -4c0N26aRVupP7gBcHGRqsMPfRxZ8cjR5JDjSAuOQjPsOBwlBb2C6oraqRKgBy/u0d80adeVoucHF -MEe7jM34roCrBZ0ebqJX8uHjLcNKZfzAt+w65g== - -`pragma protect control xilinx_configuration_visible = "false" -`pragma protect control xilinx_enable_modification = "false" -`pragma protect control xilinx_enable_probing = "false" -`pragma protect end_toolblock="+F6HPoNYthaGX52y+5DOhQmlp8k/oolHCsFRV36MRR8=" -`pragma protect data_method = "AES128-CBC" -`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 2048) -`pragma protect data_block -53kgbiIAqixoiMbgLm6sQR7urx0digpOBUiU5C4zCLVOgvP6jILtzGHp1o8/cRAaUwztJPdFqMku -qUzzLLOCANzAAXRvJS4UEx3mHiUJ3Bt/jh6mx8J/NBWMds9dF5xtS4nN6sHEtPhm1xgUSGRDH1vO -LUwOLDgTOIzTAIiVylONAVKeZ6VgTdDlBnsFlPApvJxx4NNDDLc5v5gwJek7RBaDOCtDWaf8vx/R -B2Z8k0NnpdYFcgTrjoNUTCZErPhqzsWdrrUNr28ANK541xMJ2NK5ON4CIAiQMhPcmzojS08ydU3c -DLdcPTSKaXL5U3HS2d/hlYEpi7atjmq6jrFyMrP5JHaPXDq4JE4g8ZM694zfqTEDCqrKmPQQCQW1 -7DaiFOwFB1dkzUDSdXbao7ccRsWb1hzl+9ylXaVQC8lRlfx4kIEWNOae4sNbD7Zdz0xFp3FN5Y8b -Cpb1uEV/J6dKw/DV8pBHMW5reix2s+uk9gA++A3gQciMm0qPc2ZBQ4dgyLb/RAiJN1OFggXDn6wH -pO4YYvg5gy5WLvOW4saFHN5/bFSIPCCSfBC83hP5/j93J5LuS/Tg9g6DAv+QShQLo/IY3znLxYwu -1EUhZOY4hc7TS9CZQqdLoZzvpUK2xpEq8v9Cg+t/aHqJQbeHw8He3hiaBiVjGfA8j/GePf644T20 -oGeQ9v9VTUW77rIJzpl8pejhftSnwWLEsrBqcAj0STiGRMF0u5088G84Bzf95qgq4q2/qKwXpEqa -bBISKPumQoaUsdVIOqoxuO6IpZDWKFOpu4WJcm/Yw5Giypi9uZRkAOPehQ8NkBi9+vNC/OwuWjKp -2tA4vUFUIKXMMUuNSErf2wJ064ajf34K54QfrKXp1bNB7fvwlekUwWirIRButrxEJSWS3tcgRGNn -zdYAv+hZEihs3jfi4HuXpbLEVAxQqZZUPfS4LZTQRUWDXj6zLw5VdrlmfTHe6XYaQ4JMhhD0ChYI -4kkD+jq37vfYfN6NNRWJLhk8cYa14Jdn/b6VrCaUSkMKUfN3ao0vhWrxqPSHmB7g5Yk6hihdxfAn -s2mQ/QIDFy56Kx21K9eypEWvtyU08yMllG58ZLH3mxAR2COg+eI9ku+Bzkzj2DDIAHHB/RQevjIZ -sDpluevaqALD7Eolcy3ikXos8+UnTOQQ8VBcAAFwcPdiF9/K0qKd4EPNCyOsvFe+4YY4bKro9fjr -Bfc7UNF1MPEIUCVBmjW8U9NxLSPmAnSxXYM6z1TBrwLN8DREPYS7owTqdheLEpC0a2a2EN3RjOUg -aOBfyhIcupxSbhzgmMuiSjhOQb/Hrw0SGpljEAJRXqtZ2xWdXulKgUjTLUYI98mzyTviBozRJx55 -vpjIgJSB+1ewvrY3EA72ZaVE3HsuF3STL8zuCnp0x/lP6f+hQbQTSuFA6XxZVrnp110if2lOzEMr -2urkDBqDW5f3FDAndhakpPB4GEYEzsli41PfnO4YHK4hXvGhmw1W25nsbaAaILjmYJY6v8ATRHvh -0hy7+MiItqTg4pXjuKip4WY9n5FjUhGvFW7KP9XsgKMz1MwEc+XSpdlDprY0JPiENyFxPqZf9qDl -tGr2eQ1GF7zGWz5/kl84JVNbpvqArofI2aJaszFsRC86cYtyocHugHUNCia+3xVG7Ch5fqf57LtM -YeFmiWTtIkocbCGsOC5PIusc5olkVd3TIKkGimkV04fvMdOuSqrvIi3Chndu0xDVApCuC+wchLiN -iPCXc0wfTKuqiKbvZiaUUPDyaGAGpqeZL/kRbowWbZ5ZVAnX+MANoozeZT5A5INyw9JwdzOx71Im -qcL+2C0XMHj0sijLuIG9Yx6WDBSOcO4P5xXO0Gir7rV0jG47x6Dj1+p64UGdAPolUYUwXUeQcM34 -1ohA9lTfT4egDO9GOgkovwi2Jhqt3HLvTu/ERAMUc/03DgLykeAaW2C1ya+g7HwHvIZbrptX6Bb1 -YZOmkBUN5rF0OkhIRaJ9kSuteLPUbgSPImbyAPmyHt9TPuaMHD/v2fIjq2ojC+O8BVG3p78FsloG -I+hILpbDCsC7PGFzmAhuMPTN4gJTig0YDJfHOTAq1OYeWt6y60ldRwKfIorbPrQ4EzS1CdorSIXM -nf5yFA8VwSkiGn6+JBmR+4nKK+RfDJCLYdHa3E9we2aO6SbhRRUr3gfaPmqRjGYCARnAcwt2GmL0 -Qh/l3zfL8yCqeFYN0lcfUG2HaGzvdwQ5bilQwfw3iU/6A2uRl0h9WhEaOZ0zTfh1SC0RJwgaB9b6 -amGnp9AoqrrWCmWpHQlJXWtd2m0Z/8X/GzLaWKjziBr1TJzVBmzT7F0kG92bdCugH/LHFdBVRxq1 -OdkKq+CDmYMiXP8Pn6SmP/JIykeAnW8zfNPyFV0DZ/DtCSNPSqqsxM/XzBBYq2DCYBymx8fJTpTs -uotFv42OYAtoxsuwThd5cIUJBT8HvG+m9agbzH1xi96xWZlpOviytMTwBJwqJqU2dk+p2VlyJN2F -46Zt6rq/dYtEhGbwgiRoEa4dO8JVS3XylGy9meaFqofkMPAvt0AI5ql0dzgqxMqvBfLCcYtbiNvq -av1/jdaLcOCHVpWSxwQYLOys37ItLASqrgbRQpug4aoJHNdU5/7jDDVs2v5o3HGNlrZ0PJTxVfQr -C0spm0fWtBxMCEmbkj98XyqI0PDupjLGcbrX5kRdp9E0DCJadbthVTs0zcw09dlckjhzGwA= -`pragma protect end_protected diff --git a/hdk/common/shell_v04261818/hlx/hlx_examples/build/IPI/cl_hls_dds/software/test_cl.c b/hdk/common/shell_v04261818/hlx/hlx_examples/build/IPI/cl_hls_dds/software/test_cl.c index 86a704103..605d30944 100755 --- a/hdk/common/shell_v04261818/hlx/hlx_examples/build/IPI/cl_hls_dds/software/test_cl.c +++ b/hdk/common/shell_v04261818/hlx/hlx_examples/build/IPI/cl_hls_dds/software/test_cl.c @@ -67,8 +67,8 @@ int main(int argc, char **argv) { int slot_id; /* initialize the fpga_pci library so we could have access to FPGA PCIe from this applications */ - rc = fpga_pci_init(); - fail_on(rc, out, "Unable to initialize the fpga_pci library"); + rc = fpga_mgmt_init(); + fail_on(rc, out, "Unable to initialize the fpga_mgmt library"); /* This demo works with single FPGA slot, we pick slot #0 as it works for both f1.2xl and f1.16xl */ diff --git a/hdk/common/shell_v04261818/hlx/hlx_examples/build/IPI/cl_ipi_cdma_test/software/test_cl.c b/hdk/common/shell_v04261818/hlx/hlx_examples/build/IPI/cl_ipi_cdma_test/software/test_cl.c index d8ca274c1..afe30616c 100644 --- a/hdk/common/shell_v04261818/hlx/hlx_examples/build/IPI/cl_ipi_cdma_test/software/test_cl.c +++ b/hdk/common/shell_v04261818/hlx/hlx_examples/build/IPI/cl_ipi_cdma_test/software/test_cl.c @@ -69,9 +69,9 @@ int main(int argc, char **argv) { int rc; int slot_id; - /* initialize the fpga_pci library so we could have access to FPGA PCIe from this applications */ - rc = fpga_pci_init(); - fail_on(rc, out, "Unable to initialize the fpga_pci library"); + /* initialize the fpga_mgmt library so we could have access to FPGA PCIe from this applications */ + rc = fpga_mgmt_init(); + fail_on(rc, out, "Unable to initialize the fpga_mgmt library"); /* This demo works with single FPGA slot, we pick slot #0 as it works for both f1.2xl and f1.16xl */ diff --git a/hdk/common/shell_v04261818/hlx/hlx_examples/build/IPI/hello_world/software/test_cl.c b/hdk/common/shell_v04261818/hlx/hlx_examples/build/IPI/hello_world/software/test_cl.c index a6f57084f..41454624b 100755 --- a/hdk/common/shell_v04261818/hlx/hlx_examples/build/IPI/hello_world/software/test_cl.c +++ b/hdk/common/shell_v04261818/hlx/hlx_examples/build/IPI/hello_world/software/test_cl.c @@ -55,8 +55,8 @@ int main(int argc, char **argv) { int rc; int slot_id; - /* initialize the fpga_pci library so we could have access to FPGA PCIe from this applications */ - rc = fpga_pci_init(); + /* initialize the fpga_mgmt library */ + rc = fpga_mgmt_init(); fail_on(rc, out, "Unable to initialize the fpga_pci library"); /* This demo works with single FPGA slot, we pick slot #0 as it works for both f1.2xl and f1.16xl */ @@ -66,19 +66,14 @@ int main(int argc, char **argv) { rc = check_afi_ready(slot_id); fail_on(rc, out, "AFI not ready"); - printf("\n"); printf("===== Hello World Example =====\n"); rc = peek_poke_example(slot_id, FPGA_APP_PF, APP_PF_BAR1); fail_on(rc, out, "peek-poke example failed"); - - - return rc; - out: return 1; } diff --git a/hdk/docs/AFI_Manifest.md b/hdk/docs/AFI_Manifest.md index 1e030854a..40588cb3e 100644 --- a/hdk/docs/AFI_Manifest.md +++ b/hdk/docs/AFI_Manifest.md @@ -40,6 +40,7 @@ The manifest file is a text file formatted with key=value pairs. Some keys are m | vivado tool version | field value | |------------------- | -----------| +| 2019.1 | tool_version=v2019.1 | | 2018.3 | tool_version=v2018.3 | | 2018.2 | tool_version=v2018.2 | | 2017.4 | tool_version=v2017.4 | diff --git a/hdk/docs/AWS_Shell_Interface_Specification.md b/hdk/docs/AWS_Shell_Interface_Specification.md index 827e99643..99be458a5 100644 --- a/hdk/docs/AWS_Shell_Interface_Specification.md +++ b/hdk/docs/AWS_Shell_Interface_Specification.md @@ -316,7 +316,8 @@ Each DRAM interface is accessed via an AXI-4 interface: There is a single status signal that the DRAM interface is trained and ready for access. DDR access should be gated when the DRAM interface is not ready. The addressing uses ROW/COLUMN/BANK (Interleaved) mapping of AXI address to DRAM Row/Col/BankGroup. The Read and Write channels are serviced with round-robin arbitration (i.e. equal priority). -The DRAM interface uses the Xilinx DDR-4 Interface controller. The AXI-4 interface adheres to the Xilinx specification. Uncorrectable ECC errors are signaled with RRESP. ECC error status can be read using AWS Management Software APIs. +The DRAM interface uses the Xilinx DDR-4 Interface controller. The AXI-4 interface adheres to the Xilinx specification. Uncorrectable ECC errors are signaled with RRESP. A CL can be designed to handle ECC errors by monitoring RRESP on the DDR AXI interfaces. The CL will receive a SLVERR RRESP on an uncorrectable ECC error. +**NOTE:** Writing to a DDR location is required before reading the DDR location to initialize the ECC. False ECC errors may occur when un-initialized DDR locations are read. Additionally, there are three statistics interfaces between the Shell and CL (one for each CL DDR controller). If the DDR controllers are being used by the CL, then the interfaces must be connected between the Shell and the DRAM interface controller modules. diff --git a/hdk/docs/IPI_GUI_Vivado_Setup.md b/hdk/docs/IPI_GUI_Vivado_Setup.md index 0d1d628df..5888256c4 100644 --- a/hdk/docs/IPI_GUI_Vivado_Setup.md +++ b/hdk/docs/IPI_GUI_Vivado_Setup.md @@ -46,7 +46,7 @@ In init.tcl or Vivado\_init.tcl, add the following line based upon the $HDK\_SHE # Windows Install -Download, install, and configure the license for Vivado SDx 2017.4 or Vivado 2018.2 or Vivado 2018.3 for Windows. More information is provided at: +Download, install, and configure the license for Vivado SDx 2017.4, 2018.2, 2018.3 or 2019.1 for Windows. More information is provided at: [On-Premises Licensing Help](./on_premise_licensing_help.md) diff --git a/hdk/docs/RTL_Simulating_CL_Designs.md b/hdk/docs/RTL_Simulating_CL_Designs.md index 39540f1f0..957d79a68 100644 --- a/hdk/docs/RTL_Simulating_CL_Designs.md +++ b/hdk/docs/RTL_Simulating_CL_Designs.md @@ -4,12 +4,12 @@ Developers tend to simulate their designs to validate the RTL design and functionality, before hitting the build stage and registering it with AWS EC2 as Amazon FPGA Image (AFI). AWS FPGA HDK comes with a shell simulation model that supports RTL-level simulation using Xilinx' Vivado XSIM, MentorGraphics' Questa, Cadence Incisive and Synopsys' VCS RTL simulators. See table below for supported simulator versions. -| 3rd party simulator Tool | 2017.4 Vivado tool | 2018.2 Vivado tool | 2018.3 Vivado tool | -|--------------------------|--------------------|--------------------|--------------------| -| Xilinx Vivado XSIM | Vivado v2017.4.op (64-bit) | Vivado v2018.2_AR71275_op (64-bit) | Vivado v2018.3.op (64-bit) | -| Synopsys VCS | vcs-mx/M-2017.03-SP2-11 | vcs-mx/N-2017.12-SP1-1 | vcs-mx/N-2017.12-SP2 | -| Mentor Graphics Questa | 10.6b | 10.6c_1 | 10.6c_1 | -| Cadence Incisive Enterprise Simulator(IES) | 15.20.063 | 15.20.063 | 15.20.063 | +| Simulator | Vivado 2017.4 | Vivado 2018.2 | Vivado 2018.3 | Vivado 2019.1 | +|--------------------------|--------------------|--------------------|--------------------|---| +| Xilinx Vivado XSIM | Vivado v2017.4 | Vivado v2018.2 | Vivado v2018.3 |Vivado v2019.1 | +| Synopsys VCS | M-2017.03-SP2-11 | N-2017.12-SP1-1 | N-2017.12-SP2 | O-2018.09 | +| Mentor Graphics Questa | 10.6b | 10.6c_1 | 10.6c_1 | 10.7c | +| Cadence Incisive Enterprise Simulator(IES) | 15.20.063 | 15.20.063 | 15.20.063 | 15.20.065 | Developers can write their tests in SystemVerilog and/or C languages. If a developer chooses to use the supplied C framework, he/she can use the same C code for simulation and for runtime on your FPGA-enabled instance like F1. diff --git a/hdk/docs/on_premise_licensing_help.md b/hdk/docs/on_premise_licensing_help.md index 06059c9b5..cab84d183 100644 --- a/hdk/docs/on_premise_licensing_help.md +++ b/hdk/docs/on_premise_licensing_help.md @@ -5,6 +5,14 @@ This document helps developers who choose to develop on-premises with specifying and licensing AWS-compatible Xilinx tools for use with the AWS FPGA HDK. +## Requirements for AWS HDK 1.4.11+ (2019.1) + * Xilinx Vivado v2019.1 or v2019.1.op (64-bit) + * License: EF-VIVADO-SDX-VU9P-OP + * SW Build 2552052 on Fri May 24 14:47:09 MDT 2019 + * IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 + * URL: https://www.xilinx.com/member/forms/download/xef.html?filename=Xilinx_SDAccel_2019.1_0524_1430_Lin64.bin + * MD5 SUM Value: aa20eba36ebe480ec7ae59a4a8c85896 + ## Requirements for AWS HDK 1.4.8+ (2018.3) * Xilinx Vivado v2018.3 or v2018.3.op (64-bit) * License: EF-VIVADO-SDX-VU9P-OP diff --git a/hdk/hdk_version.txt b/hdk/hdk_version.txt index ed64e9969..e05658b5b 100644 --- a/hdk/hdk_version.txt +++ b/hdk/hdk_version.txt @@ -1 +1 @@ -HDK_VERSION=1.4.10 \ No newline at end of file +HDK_VERSION=1.4.11 diff --git a/hdk/tests/test_gen_dcp.py b/hdk/tests/test_gen_dcp.py index d2ccd22db..0a9956236 100644 --- a/hdk/tests/test_gen_dcp.py +++ b/hdk/tests/test_gen_dcp.py @@ -93,12 +93,15 @@ def set_allowed_warnings(cls): (('.*',), r'WARNING: \[Place 30-640\] Place Check.*'), (('.*',), r'WARNING: \[BD 41-2180\] Resetting the memory initialization file.*'), (('.*',), r'WARNING: \[Synth 8-689\] .*'), + (('.*',), r'WARNING: \[Synth 8-6896\] .*'), + (('.*',), r'WARNING: \[Synth 8-7023\] .*'), (('cl_sde_*',), r'WARNING: \[Vivado 12-180\] No cells matched .*'), (('cl_sde_*',), r'WARNING: \[Vivado 12-1008\] No clocks found for command.*'), (('cl_sde_*',), r'CRITICAL WARNING: \[Designutils 20-1280\] .*'), (('cl_sde_*',), r'^CRITICAL WARNING: \[Constraints 18-952\] .*'), (('cl_sde_*',), r'^CRITICAL WARNING: \[Vivado 12-1039\] .*'), (('cl_sde_*',), r'^CRITICAL WARNING: \[Vivado 12-1433\] .*'), + (('cl_sde.*',), r'WARNING: \[Synth 8-6057\] Memory.*'), (('cl_dram_dma_A1_B2_C0_2_(CONGESTION|BASIC)',), r'^CRITICAL WARNING: \[Route 35-39\] The design did not meet timing requirements'), (('cl_dram_dma_A1_B2_C0_2_(CONGESTION|TIMING)',), r'WARNING: \[Vivado 12-180\] No cells matched \'CL/CL_DMA_PCIS_SLV/CL_TST_DDR_B/CL_TST/sync_rst_n_reg\''), (('cl_dram_dma_*',), r'CRITICAL WARNING: \[Designutils 20-1280\] Could not find module \'bd_bf3f_microblaze_I_0\''), diff --git a/hdk/tests/test_hdk_scripts.py b/hdk/tests/test_hdk_scripts.py index d6b49de27..cfa2c8a2a 100644 --- a/hdk/tests/test_hdk_scripts.py +++ b/hdk/tests/test_hdk_scripts.py @@ -58,12 +58,6 @@ def test_create_fpga_image(self): def test_wait_for_afi(self): self.run_cmd("{}/shared/bin/scripts/wait_for_afi.py --afi {}".format(self.WORKSPACE, self.afi)) - def test_wait_for_afi_python27(self): - self.run_cmd("python2.7 {}/shared/bin/scripts/wait_for_afi.py --afi {}".format(self.WORKSPACE, self.afi)) - - def test_wait_for_afi_python34(self): - self.run_cmd("python3.4 {}/shared/bin/scripts/wait_for_afi.py --afi {}".format(self.WORKSPACE, self.afi)) - @pytest.mark.skip(reason="Not implemented") def test_notify_via_sns(self): assert False diff --git a/sdaccel_runtime_setup.sh b/sdaccel_runtime_setup.sh index 4f3b43464..bc735cd11 100644 --- a/sdaccel_runtime_setup.sh +++ b/sdaccel_runtime_setup.sh @@ -117,8 +117,8 @@ function check_kernel_ver { cat $AWS_FPGA_REPO_DIR/SDAccel/kernel_version.txt warn_msg "Xilinx Runtime not validated against your installed kernel version." fi - } + # Process command line args args=( "$@" ) for (( i = 0; i < ${#args[@]}; i++ )); do @@ -144,11 +144,13 @@ done if ! exists vivado; then if [[ -z "${VIVADO_TOOL_VERSION}" ]]; then - err_msg " You are not using FPGA Developer AMI and VIVADO_TOOL_VERSION ENV variable is Empty. " - err_msg " ENV Variable VIVADO_TOOL_VERSION is required to be set for runtime " + err_msg " VIVADO_TOOL_VERSION ENV variable is not set." + err_msg " ENV Variable VIVADO_TOOL_VERSION needs to be set for runtime usage. " + err_msg " If AFI was generated using V2019.1 tools use the command : export VIVADO_TOOL_VERSION=2019.1 " + err_msg " If AFI was generated using V2018.3 tools use the command : export VIVADO_TOOL_VERSION=2018.3 " err_msg " If AFI was generated using V2018.2 tools use the command : export VIVADO_TOOL_VERSION=2018.2 " err_msg " If AFI was generated using V2017.4 tools use the command : export VIVADO_TOOL_VERSION=2017.4 " - err_msg " If you are using the FPGA Developer AMI then please request support on AWS FPGA Developers Forum." + err_msg " Please set VIVADO_TOOL_VERSION to the correct value and re-run script." return 1 else info_msg " VIVADO tools not found. Reading VIVADO_TOOL_VERSION ENV variable to determine runtime version... " @@ -167,7 +169,7 @@ check_kernel_ver check_xdma_driver check_edma_driver -if [[ "$VIVADO_TOOL_VERSION" =~ .*2018\.2.* || "$VIVADO_TOOL_VERSION" =~ .*2018\.3.* ]]; then +if [[ "$VIVADO_TOOL_VERSION" =~ .*2018\.2.* || "$VIVADO_TOOL_VERSION" =~ .*2018\.3.* || "$VIVADO_TOOL_VERSION" =~ .*2019\.1.* ]]; then info_msg "Xilinx Vivado version is $VIVADO_TOOL_VERSION" if [ $override == 1 ]; then @@ -190,12 +192,12 @@ if [[ "$VIVADO_TOOL_VERSION" =~ .*2018\.2.* || "$VIVADO_TOOL_VERSION" =~ .*2018\ if [ -f "/opt/xilinx/xrt/setup.sh" ]; then source /opt/xilinx/xrt/setup.sh else - err_msg " Cannot find /opt/xilinx/xrt/setup.sh " - err_msg " Please check XRT is installed correctly " - err_msg "Please Refer $AWS_FPGA_REPO/SDAccel/doc/XRT_installation_instructions.md for XRT installation instructions" + err_msg " Cannot find /opt/xilinx/xrt/setup.sh" + err_msg " Please check XRT is installed correctly" + err_msg " Please Refer to $AWS_FPGA_REPO/SDAccel/doc/XRT_installation_instructions.md for XRT installation instructions" return 1 fi - info_msg " XRT Runtime setup Done " + info_msg " XRT Runtime setup Done" else err_msg "$xrt_build_ver does not match recommended versions" cat $AWS_FPGA_REPO_DIR/SDAccel/sdaccel_xrt_version.txt @@ -209,7 +211,6 @@ if [[ "$VIVADO_TOOL_VERSION" =~ .*2018\.2.* || "$VIVADO_TOOL_VERSION" =~ .*2018\ fi else info_msg "Xilinx Vivado version is $VIVADO_TOOL_VERSION " - #info_msg " checking for file: /opt/Xilinx/SDx/${VIVADO_TOOL_VERSION}.rte.dyn/setup.sh" info_msg " Now checking XOCL driver..." check_xocl_driver if [ -f "/opt/Xilinx/SDx/${VIVADO_TOOL_VERSION}.rte.dyn/setup.sh" ]; then diff --git a/sdaccel_setup.sh b/sdaccel_setup.sh index a5d004459..2d17953e7 100644 --- a/sdaccel_setup.sh +++ b/sdaccel_setup.sh @@ -171,7 +171,7 @@ setup_patches # Update Xilinx SDAccel Examples from GitHub info_msg "Using SDx $RELEASE_VER" -if [[ $RELEASE_VER =~ .*2017\.4.* || $RELEASE_VER =~ .*2018\.2.* || $RELEASE_VER =~ .*2018\.3.* ]]; then +if [[ $RELEASE_VER =~ .*2017\.4.* || $RELEASE_VER =~ .*2018\.2.* || $RELEASE_VER =~ .*2018\.3.* || $RELEASE_VER =~ .*2019\.1.* ]]; then info_msg "Updating Xilinx SDAccel Examples $RELEASE_VER" git submodule update --init -- SDAccel/examples/xilinx_$RELEASE_VER export VIVADO_TOOL_VER=$RELEASE_VER @@ -183,8 +183,8 @@ if [[ $RELEASE_VER =~ .*2017\.4.* || $RELEASE_VER =~ .*2018\.2.* || $RELEASE_VER fi ln -sf $SDACCEL_DIR/examples/xilinx_$RELEASE_VER $SDACCEL_DIR/examples/xilinx else - echo " $RELEASE_VER is not supported (2017.4, 2018.2 & 2018.3 are supported).\n" - exit 2 + echo " $RELEASE_VER is not supported (2017.4, 2018.2, 2018.3 and 2019.1 are supported).\n" + return 2 fi # settings64 removal - once we put this in the AMI, we will add a check diff --git a/sdk/linux_kernel_drivers/xdma/xdma_install.md b/sdk/linux_kernel_drivers/xdma/xdma_install.md index db2aaef12..b0803b3f1 100644 --- a/sdk/linux_kernel_drivers/xdma/xdma_install.md +++ b/sdk/linux_kernel_drivers/xdma/xdma_install.md @@ -66,7 +66,7 @@ __*For Suse*__ __**Step 2**__: Clone the git repo locally under my_fpga_dir for example: ``` - $ mkdir -p + $ mkdir -p $ cd $ git clone https://github.com/aws/aws-fpga ``` diff --git a/sdk/tests/test_fpga_tools.py b/sdk/tests/test_fpga_tools.py index 53a5805db..ff2629a4f 100644 --- a/sdk/tests/test_fpga_tools.py +++ b/sdk/tests/test_fpga_tools.py @@ -48,6 +48,7 @@ class TestFpgaTools(BaseSdkTools): Test FPGA AFI Management tools described in ../userspace/fpga_mgmt_tools/README.md ''' + @pytest.mark.flaky(reruns=2, reruns_delay=5) def test_describe_local_image_slots(self): for slot in range(self.num_slots): self.fpga_clear_local_image(slot) @@ -88,6 +89,7 @@ def test_describe_local_image_slots(self): assert stdout[slot * 3 + 1] == 'AFIDEVICE {} 0x1d0f 0x1042 {}'.format(slot, self.slot2device[slot]), "slot={}\n{}".format(slot, "\n".join(stdout)) assert stdout[slot * 3 + 2] == 'AFIDEVICE {} 0x1d0f 0x1041 {}'.format(slot, self.slot2mbox_device[slot]), "slot={}\n{}".format(slot, "\n".join(stdout)) + @pytest.mark.flaky(reruns=2, reruns_delay=5) def test_describe_local_image(self): for slot in range(self.num_slots): self.fpga_clear_local_image(slot) @@ -127,6 +129,7 @@ def test_describe_local_image(self): assert stdout[50] == 'Clock Group C Frequency (Mhz)' assert stdout[51] == '0 0 ' + @pytest.mark.flaky(reruns=2, reruns_delay=5) def test_load_local_image(self): for slot in range(self.num_slots): (rc, stdout, stderr) = self.run_cmd("sudo fpga-load-local-image --request-timeout {} -S {} -I {}".format(self.DEFAULT_REQUEST_TIMEOUT, slot, self.cl_hello_world_agfi), echo=True) @@ -173,6 +176,7 @@ def test_load_local_image(self): assert stdout[1] == 'AFIDEVICE {} 0x1d0f 0xf000 {}'.format(slot, self.slot2device[slot]) self.fpga_clear_local_image(slot) + @pytest.mark.flaky(reruns=2, reruns_delay=5) def test_clear_local_image(self): for slot in range(self.num_slots): # Test clearing already cleared @@ -230,6 +234,7 @@ def test_start_virtual_jtag(self): assert stdout[0] == 'AFI {} none cleared 1 ok 0 {}'.format(slot, self.shell_version) assert stdout[1] == 'AFIDEVICE {} 0x1d0f 0x1042 {}'.format(self.slot2device[slot]) + @pytest.mark.flaky(reruns=2, reruns_delay=5) def test_get_virtual_led(self): # This is tested in the cl_hello_world example for slot in range(self.num_slots): @@ -241,6 +246,7 @@ def test_get_virtual_led(self): assert stdout[0] == 'FPGA slot id {} have the following Virtual LED:'.format(slot) assert re.match('[01]{4}-[01]{4}-[01]{4}-[01]{4}', stdout[1]) + @pytest.mark.flaky(reruns=2, reruns_delay=5) def test_virtual_dip_switch(self): for slot in range(self.num_slots): # Start it on an empty slot @@ -260,6 +266,8 @@ def test_virtual_dip_switch(self): assert stdout[0] == 'FPGA slot id {} has the following Virtual DIP Switches:'.format(slot) assert stdout[1] == '1111-1111-1111-1111' + # Add extra delay in case we have a lot of slot loads + @pytest.mark.flaky(reruns=2, reruns_delay=10) def test_parallel_slot_loads(self): def run_slot(slot): for afi in [self.cl_dram_dma_agfi, self.cl_hello_world_agfi, self.cl_dram_dma_agfi]: diff --git a/sdk/tests/test_non_root_access.py b/sdk/tests/test_non_root_access.py index 09482b0be..df3303f7a 100755 --- a/sdk/tests/test_non_root_access.py +++ b/sdk/tests/test_non_root_access.py @@ -78,6 +78,6 @@ def test_hello_world_as_non_root_user(self): for slot in range(AwsFpgaTestBase.num_slots): (rc, out, err) = self.run_cmd("bash -x {}/sdk/tests/non_root_log_into_group.sh {}".format(os.environ['WORKSPACE'], slot)) logger.info("{}\n{}".format(out, err)) - assert rc == 0 + assert rc == 0 AwsFpgaTestBase.fpga_set_virtual_dip_switch("1111111111111111", slot, as_root=False) - assert AwsFpgaTestBase.fpga_get_virtual_led(slot, as_root=False) == "1010-1101-1101-1110" + assert AwsFpgaTestBase.fpga_get_virtual_led(slot, as_root=False) == "1010-1101-1101-1110" diff --git a/sdk/tests/test_sdk_scripts.py b/sdk/tests/test_sdk_scripts.py index c6964d879..2d5738cf1 100644 --- a/sdk/tests/test_sdk_scripts.py +++ b/sdk/tests/test_sdk_scripts.py @@ -54,8 +54,5 @@ def test_sdk_setup(self): logger.info(self) assert False - def test_fio_tools_setup_python27(self): - self.setup_fio_tools(python_version=2.7) - - def test_fio_tools_setup_python34(self): - self.setup_fio_tools(python_version=3.4) + def test_fio_tools_setup(self): + self.setup_fio_tools() diff --git a/sdk/userspace/fpga_mgmt_tools/README.md b/sdk/userspace/fpga_mgmt_tools/README.md index f59bc9f6f..6f21b3932 100644 --- a/sdk/userspace/fpga_mgmt_tools/README.md +++ b/sdk/userspace/fpga_mgmt_tools/README.md @@ -144,7 +144,7 @@ The following command displays the current state for the given FPGA slot number. ### Looking at Metrics -The `fpga-describe-local-image` **`metrics`** option may be used to display FPGA image hardware metrics including FPGA PCI and DDR ECC metrics. +The `fpga-describe-local-image` **`metrics`** option may be used to display FPGA image hardware metrics including FPGA PCI and DDR metrics. Additionally, the `fpga-describe-local-image` **`clear-metrics`** option may be used to display and clear FPGA image hardware metrics (clear on read). diff --git a/sdk/userspace/install_fpga_mgmt_tools.sh b/sdk/userspace/install_fpga_mgmt_tools.sh index e929bc44c..740665cad 100755 --- a/sdk/userspace/install_fpga_mgmt_tools.sh +++ b/sdk/userspace/install_fpga_mgmt_tools.sh @@ -68,6 +68,7 @@ echo "AWS FPGA: Copying Amazon FPGA Image (AFI) Management Tools to $AFI_MGMT_TO cp -f $AFI_MGMT_TOOLS_SRC_DIR/fpga-* $AFI_MGMT_TOOLS_DST_DIR cp -f $AFI_MGMT_TOOLS_LIB_DIR/libfpga_mgmt.so.1.0.0 $AFI_MGMT_LIBS_DST_DIR ln -sf libfpga_mgmt.so.1 $AFI_MGMT_LIBS_DST_DIR/libfpga_mgmt.so +ln -sf libfpga_mgmt.so.1.0.0 $AFI_MGMT_LIBS_DST_DIR/libfpga_mgmt.so.1 source /tmp/sdk_root_env.exp if allow_non_root ; then diff --git a/shared/lib/aws_fpga_test_utils/AwsFpgaTestBase.py b/shared/lib/aws_fpga_test_utils/AwsFpgaTestBase.py index c2183725c..be82b060a 100644 --- a/shared/lib/aws_fpga_test_utils/AwsFpgaTestBase.py +++ b/shared/lib/aws_fpga_test_utils/AwsFpgaTestBase.py @@ -301,9 +301,10 @@ def get_sdaccel_example_s3_afi_tag(examplePath, target, rteName, xilinxVersion): return "{}/create-afi/afi-ids.txt".format(root_tag) @staticmethod - def get_sdaccel_example_run_cmd(examplePath): + def get_sdaccel_example_run_cmd(examplePath, xilinxVersion): ''' @param examplePath: Path of the Xilinx SDAccel example + @param xilinxVersion: The Xilinx tool version ''' description = AwsFpgaTestBase.get_sdaccel_example_description(examplePath) if description.get("em_cmd", None): @@ -313,9 +314,15 @@ def get_sdaccel_example_run_cmd(examplePath): run_cmd = "./{}".format(description.get("host_exe", None)) if description.get("cmd_args", None): if "PROJECT" not in description.get("cmd_args", None) and "BUILD" not in description.get("cmd_args", None): - run_cmd += " {}".format(description.get("cmd_args", None)) + if "2019.1" not in xilinxVersion: + run_cmd += " {}".format(description.get("cmd_args", None)) + else: + run_cmd += " {}".format(description.get("cmd_args", None).replace(".xclbin",".hw.xilinx_aws-vu9p-f1-04261818_dynamic_5_0.xclbin")) else: - run_cmd += " {}".format((description.get("cmd_args", None).replace("PROJECT",".")).replace("BUILD","./xclbin")) + if "2019.1" not in xilinxVersion: + run_cmd += " {}".format((description.get("cmd_args", None).replace("PROJECT",".")).replace("BUILD","./xclbin")) + else: + run_cmd += " {}".format(((description.get("cmd_args", None).replace(".xclbin",".hw.xilinx_aws-vu9p-f1-04261818_dynamic_5_0.awsxclbin")).replace("PROJECT",".")).replace("BUILD","./xclbin")) assert run_cmd is not None, "Could not find run_cmd(em_cmd) or (host_exe) in the example description here {}".format(examplePath) @@ -518,7 +525,7 @@ def get_fio_write_benchmark_script(driver='xdma'): return os.path.join(AwsFpgaTestBase.get_fio_tool_root(), "scripts/{}_4-ch_4-1M_write.fio".format(driver)) @staticmethod - def setup_fio_tools(python_version=2.7): + def setup_fio_tools(): '''Install and setup fio tools''' # If downloaded repo already, exists, delete it so we can fetch again if os.path.exists(AwsFpgaTestBase.get_fio_tool_install_path()): @@ -526,7 +533,7 @@ def setup_fio_tools(python_version=2.7): logger.info("Installing fio_dma_tools") - (rc, stdout_lines, stderr_lines) = AwsFpgaTestBase.run_cmd("python{} {} {}".format(python_version, AwsFpgaTestBase.get_fio_tool_install_script(), AwsFpgaTestBase.get_fio_tool_install_path()), echo=True) + (rc, stdout_lines, stderr_lines) = AwsFpgaTestBase.run_cmd("python {} {}".format(AwsFpgaTestBase.get_fio_tool_install_script(), AwsFpgaTestBase.get_fio_tool_install_path()), echo=True) assert rc == 0 assert os.path.exists("{}".format(AwsFpgaTestBase.get_fio_tool_run_script())) diff --git a/shared/lib/check_src_headers.py b/shared/lib/check_src_headers.py index d3c229edd..7249bb367 100755 --- a/shared/lib/check_src_headers.py +++ b/shared/lib/check_src_headers.py @@ -560,9 +560,9 @@ def check_headers(dir): "SDAccel/examples/aws/helloworld_ocl_runtime/helloworld", "SDAccel/examples/aws/helloworld_ocl_runtime/sdaccel.ini", "SDAccel/examples/aws/helloworld_ocl_runtime/vector_addition.hw.xilinx_aws-vu9p-f1-04261818_dynamic_5_0.awsxclbin", - "SDAccel/examples/aws/helloworld_ocl_runtime/2018.3/helloworld", - "SDAccel/examples/aws/helloworld_ocl_runtime/2018.3/sdaccel.ini", - "SDAccel/examples/aws/helloworld_ocl_runtime/2018.3/vector_addition.hw.xilinx_aws-vu9p-f1-04261818_dynamic_5_0.awsxclbin" + "SDAccel/examples/aws/helloworld_ocl_runtime/2018.3_2019.1/helloworld", + "SDAccel/examples/aws/helloworld_ocl_runtime/2018.3_2019.1/sdaccel.ini", + "SDAccel/examples/aws/helloworld_ocl_runtime/2018.3_2019.1/vector_addition.hw.xilinx_aws-vu9p-f1-04261818_dynamic_5_0.awsxclbin" ]) file_provider.set_exclude_paths([ diff --git a/shared/tests/bin/install_python_venv.sh b/shared/tests/bin/install_python_venv.sh new file mode 100755 index 000000000..98f834734 --- /dev/null +++ b/shared/tests/bin/install_python_venv.sh @@ -0,0 +1,89 @@ +# Amazon FPGA Hardware Development Kit +# +# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. +# +# Licensed under the Amazon Software License (the "License"). You may not use +# this file except in compliance with the License. A copy of the License is +# located at +# +# http://aws.amazon.com/asl/ +# +# or in the "license" file accompanying this file. This file is distributed on +# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or +# implied. See the License for the specific language governing permissions and +# limitations under the License. + +# Script must be sourced from a bash shell or it will not work +# When being sourced $0 will be the interactive shell and $BASH_SOURCE_ will contain the script being sourced +# When being run $0 and $_ will be the same. + +os_uname=`uname -r` + +script=${BASH_SOURCE[0]} +full_script=$(readlink -f $script) +script_name=$(basename $full_script) +script_dir=$(dirname $full_script) + +python_versions=(3.6 2.7) + +# First install python if it is not installed. +for python_version in ${python_versions[@]}; do + if [[ $os_uname =~ (amzn2) ]]; then + python_version = ${python_version:0:1} + fi + + python=python$python_version + pip=pip$python_version + yum_python_package=${python/./} + if [ ! -e /usr/bin/$python ]; then + if ! sudo yum -y install $yum_python_package; then + echo "Error: Install of $yum_python_package failed" + exit 1 + fi + fi +done + +# Python2 pip is common between OS's. We can use that to install other +if [ ! -e /usr/bin/pip2 ]; then + if ! sudo yum -y install python2-pip; then + echo "Error: Install of $yum_python_package failed" + exit 1 + fi +fi + +# Install virtualenv +if [ ! -e /usr/bin/virtualenv ]; then + if ! sudo pip install virtualenv; then + echo "Error: Install of virtualenv failed" + exit 1 + fi +fi + +# Install virtualenvwrapper +if [ ! -e /usr/bin/virtualenvwrapper.sh ]; then + if ! sudo pip install virtualenvwrapper; then + echo "Error: Install of virtualenvwrapper failed" + exit 1 + fi +fi + +source virtualenvwrapper.sh + +# Create virtualenv environments +for python_version in ${python_versions[@]}; do + + if [[ $os_uname =~ (amzn2) ]] + then + site_packages=/usr/lib64/python$python_version/site-packages/ + + python=python${python_version:0:1} + + mkvirtualenv -r $script_dir/requirements.txt -p $(which $python) --system-site-packages python${python_version:0:1} + + # Adding the python bindings site packages to path + add2virtualenv $site_packages + else + python=python$python_version + mkvirtualenv -r $script_dir/requirements.txt -p $(which $python) python${python_version:0:1} + fi +done \ No newline at end of file diff --git a/shared/tests/bin/requirements.txt b/shared/tests/bin/requirements.txt new file mode 100644 index 000000000..354f359a2 --- /dev/null +++ b/shared/tests/bin/requirements.txt @@ -0,0 +1,6 @@ +pytest +pytest-timeout +pytest-rerunfailures +boto3 +markdown +GitPython \ No newline at end of file diff --git a/shared/tests/bin/setup_test_env.sh b/shared/tests/bin/setup_test_env.sh index 2668c68f2..bca0a7935 100644 --- a/shared/tests/bin/setup_test_env.sh +++ b/shared/tests/bin/setup_test_env.sh @@ -27,48 +27,20 @@ full_script=$(readlink -f $script) script_name=$(basename $full_script) script_dir=$(dirname $full_script) -python_versions=(2.7 3.6) +instance_id=`curl http://169.254.169.254/latest/meta-data/instance-id` +instance_type=`curl http://169.254.169.254/latest/meta-data/instance-type` -python_packages=(\ -pytest \ -pytest-timeout \ -GitPython \ -boto3 \ -markdown \ -) - -for python_version in ${python_versions[@]}; do - python=python$python_version - pip=pip$python_version - yum_python_package=${python/./} - yum_pip_package=$yum_python_package-pip - if [ ! -e /usr/bin/$python ]; then - if ! sudo yum -y install $yum_python_package; then - echo "error: Install of $yum_python_package failed" - return 1 - fi - fi - if [ ! -e /usr/bin/$pip ]; then - if ! sudo yum -y install $yum_pip_package; then - echo "error: Install of $yum_pip_package failed" - return 1 - fi - fi - - for p in ${python_packages[@]}; do - if ! $pip show $p > /dev/null; then - echo "Installing $p" - if ! $pip install --user $p; then - echo "error: Install of $python $p failed" - return 1 - fi - fi - done -done +echo "Test Running on INSTANCE ID: $instance_id INSTANCE TYPE: $instance_type" if [ ":$WORKSPACE" == ":" ]; then export WORKSPACE=$(git rev-parse --show-toplevel) fi +export WORKON_HOME=$WORKSPACE/.virtualenvs + +$script_dir/install_python_venv.sh + +# Setup default environment to work on +source $WORKSPACE/.virtualenvs/python2/bin/activate export PYTHONPATH=$WORKSPACE/shared/lib:$PYTHONPATH diff --git a/shared/tests/bin/setup_test_env_al2.sh b/shared/tests/bin/setup_test_env_al2.sh deleted file mode 100644 index 1004e6672..000000000 --- a/shared/tests/bin/setup_test_env_al2.sh +++ /dev/null @@ -1,77 +0,0 @@ -# Amazon FPGA Hardware Development Kit -# -# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. -# -# Licensed under the Amazon Software License (the "License"). You may not use -# this file except in compliance with the License. A copy of the License is -# located at -# -# http://aws.amazon.com/asl/ -# -# or in the "license" file accompanying this file. This file is distributed on -# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or -# implied. See the License for the specific language governing permissions and -# limitations under the License. - -# Script must be sourced from a bash shell or it will not work -# When being sourced $0 will be the interactive shell and $BASH_SOURCE_ will contain the script being sourced -# When being run $0 and $_ will be the same. - -script=${BASH_SOURCE[0]} -if [ $script == $0 ]; then - echo "ERROR: You must source this script" - exit 2 -fi - -full_script=$(readlink -f $script) -script_name=$(basename $full_script) -script_dir=$(dirname $full_script) - -python_versions=(2 3) - -python_packages=(\ -pytest \ -pytest-timeout \ -GitPython \ -boto3 \ -awscli \ -markdown \ -) - -for python_version in ${python_versions[@]}; do - python=python$python_version - pip=pip$python_version - yum_python_package=${python/./} - yum_pip_package=$yum_python_package-pip - if [ ! -e /usr/bin/$python ]; then - if ! sudo yum -y install $yum_python_package; then - echo "error: Install of $yum_python_package failed" - set +x - return 1 - fi - fi - if [ ! -e /usr/bin/$pip ]; then - if ! sudo yum -y install $yum_pip_package; then - echo "error: Install of $yum_pip_package failed" - return 1 - fi - fi - - for p in ${python_packages[@]}; do - if ! $pip show $p > /dev/null; then - echo "Installing $p" - if ! $pip install --user $p; then - echo "error: Install of $python $p failed" - return 1 - fi - fi - done -done - -if [ ":$WORKSPACE" == ":" ]; then - export WORKSPACE=$(git rev-parse --show-toplevel) -fi - -export PYTHONPATH=$WORKSPACE/shared/lib:$PYTHONPATH - -export AWS_DEFAULT_REGION=us-east-1 diff --git a/shared/tests/bin/setup_test_runtime_sdaccel_env.sh b/shared/tests/bin/setup_test_runtime_sdaccel_env.sh index b16239f9d..36774b597 100644 --- a/shared/tests/bin/setup_test_runtime_sdaccel_env.sh +++ b/shared/tests/bin/setup_test_runtime_sdaccel_env.sh @@ -27,6 +27,8 @@ full_script=$(readlink -f $script) script_name=$(basename $full_script) script_dir=$(dirname $full_script) +export LD_LIBRARY_PATH=$XILINX_SDX/lnx64/tools/opencv/:$LD_LIBRARY_PATH + if ! source $script_dir/setup_test_env.sh; then return 1 fi diff --git a/shared/tests/bin/setup_test_sdk_env.sh b/shared/tests/bin/setup_test_sdk_env.sh index 828f8f314..03f6eceda 100644 --- a/shared/tests/bin/setup_test_sdk_env.sh +++ b/shared/tests/bin/setup_test_sdk_env.sh @@ -26,11 +26,21 @@ fi full_script=$(readlink -f $script) script_name=$(basename $full_script) script_dir=$(dirname $full_script) +setup_test_env_script_dir=$script_dir if ! source $script_dir/setup_test_env.sh; then - return 1 + return 1 fi if ! source $WORKSPACE/sdk_setup.sh; then - return 1 + return 1 fi + +if [ x$1 == "xpy_bindings" ] ; then + source $WORKSPACE/.virtualenvs/python3/bin/activate + aws s3 cp s3://aws-fpga-jenkins-testing/python_bindings_dependencies/setup.sh . + chmod 755 ./setup.sh + ./setup.sh + export PYTHONPATH=$PYTHONPATH:$SDK_DIR/apps + source $WORKSPACE/.virtualenvs/python2/bin/activate +fi \ No newline at end of file diff --git a/shared/tests/bin/setup_test_sdk_env_al2.sh b/shared/tests/bin/setup_test_sdk_env_al2.sh deleted file mode 100644 index eb64b4adb..000000000 --- a/shared/tests/bin/setup_test_sdk_env_al2.sh +++ /dev/null @@ -1,43 +0,0 @@ -# Amazon FPGA Hardware Development Kit -# -# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. -# -# Licensed under the Amazon Software License (the "License"). You may not use -# this file except in compliance with the License. A copy of the License is -# located at -# -# http://aws.amazon.com/asl/ -# -# or in the "license" file accompanying this file. This file is distributed on -# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or -# implied. See the License for the specific language governing permissions and -# limitations under the License. - -# Script must be sourced from a bash shell or it will not work -# When being sourced $0 will be the interactive shell and $BASH_SOURCE_ will contain the script being sourced -# When being run $0 and $_ will be the same. - -script=${BASH_SOURCE[0]} -if [ $script == $0 ]; then - echo "ERROR: You must source this script" - exit 2 -fi - -full_script=$(readlink -f $script) -script_name=$(basename $full_script) -script_dir=$(dirname $full_script) - -if ! source $script_dir/setup_test_env_al2.sh; then - return 1 -fi - -if ! source $WORKSPACE/sdk_setup.sh; then - return 1 -fi - -if [ x$1 == "xpy_bindings" ] ; then - aws s3 cp s3://aws-fpga-jenkins-testing/python_bindings_dependencies/setup.sh . - chmod 755 ./setup.sh - ./setup.sh - export PYTHONPATH=$PYTHONPATH:$SDK_DIR/apps -fi diff --git a/shared/tests/bin/setup_test_xrtpatch.sh b/shared/tests/bin/setup_test_xrtpatch.sh index 07fd9e809..63eb1380b 100644 --- a/shared/tests/bin/setup_test_xrtpatch.sh +++ b/shared/tests/bin/setup_test_xrtpatch.sh @@ -75,7 +75,7 @@ elif [[ "$VIVADO_TOOL_VERSION" =~ .*2018\.3.* ]]; then echo "Xilinx Vivado version is 2018.3" s3_ami_version=1.6.0 - xrt_release_version=XRT_2018_3_RC3_Patch2 + xrt_release_version=XRT_2018_3_RC5 xrt_rpm_name=xrt_201830.2.1.0_7.6.1810-xrt.rpm aws_xrt_rpm_name=xrt_201830.2.1.0_7.6.1810-aws.rpm diff --git a/supported_vivado_versions.txt b/supported_vivado_versions.txt index fa85458c8..5b4d35c21 100644 --- a/supported_vivado_versions.txt +++ b/supported_vivado_versions.txt @@ -6,3 +6,5 @@ Vivado v2018.2.op (64-bit) Vivado v2018.2 (64-bit) Vivado v2018.3.op (64-bit) Vivado v2018.3 (64-bit) +Vivado v2019.1.op (64-bit) +Vivado v2019.1 (64-bit)