The SDAccel Environment has a feature to estimate the power used by the FPGA. Power analysis is not enabled by default in the AWS F1 instance, however it may be enabled with a command line option.
Power analysis can only be performed in the hardware build flow: it is not performed during SW Emulation or HW emulation. It may be enabled by the following command line switch to your existing xocc command line.
$ xocc YOUR_EXISTING_COMMAND_LINE --xp vivado_param:project.runs.noReportGeneration=0
This option enables the generation of all implementation reports. Many of these reports contain detailed information about the hardware implementation. In general, these reports are only recommended for users with experience in RTL hardware design, and hence they are not generated by default.
With the option above ambled, the power report can be reviewed at the following location (referenced from inside your SDAccel project directory), where is the name of your kernel.
./System/_xocc_link_/impl/build/system//bitstream/_ipi/ipiimpl/ipiimpl.runs/impl_1/xcl_design_wrapper_power_routed.rpt
The SDAccel environment has an option to enable power optimization.
$ xocc YOUR_EXISTING_COMMAND_LINE --xp vivado_prop:run.impl_1.{STEPS.POST_PLACE_POWER_OPT_DESIGN.IS_ENABLED}=1
After power optimization, the power report shows the new power values for the design.