Add Sipeed Tangnano9k and Tangnano20k boards

FemtoRV/BOARDS/tangnano20k.cst

@@ -0,0 +1,18 @@
+
+IO_LOC "clk" 4;
+CLOCK_LOC "clk" BUFG;
+
+// active high
+IO_LOC "RESET" 88;
+
+IO_LOC "LED[0]" 15;
+IO_LOC "LED[1]" 16;
+IO_LOC "LED[2]" 17;
+IO_LOC "LED[3]" 18;
+IO_LOC "LED[4]" 19;
+IO_LOC "LED[5]" 20;
+
+IO_LOC "TXD" 26;
+IO_PORT "TXD" PULL_MODE=UP;
+IO_LOC "RXD" 48;
+IO_PORT "RXD" PULL_MODE=UP;

FemtoRV/BOARDS/tangnano9k.cst

@@ -0,0 +1,28 @@
+// 27 MHz clock
+IO_LOC "pclk" 52;
+IO_PORT "pclk" IO_TYPE=LVCMOS33 PULL_MODE=NONE;
+
+// active low
+IO_LOC "RESET" 4;
+IO_PORT "RESET" IO_TYPE=LVCMOS33 PULL_MODE=NONE;
+
+IO_LOC "LED[0]" 10;
+IO_LOC "LED[1]" 11;
+IO_LOC "LED[2]" 13;
+IO_LOC "LED[3]" 14;
+IO_LOC "LED[4]" 15;
+IO_LOC "LED[5]" 16;
+
+IO_PORT "LED[0]" IO_TYPE=LVCMOS33 PULL_MODE=NONE;
+IO_PORT "LED[1]" IO_TYPE=LVCMOS33 PULL_MODE=NONE;
+IO_PORT "LED[2]" IO_TYPE=LVCMOS33 PULL_MODE=NONE;
+IO_PORT "LED[3]" IO_TYPE=LVCMOS33 PULL_MODE=NONE;
+IO_PORT "LED[4]" IO_TYPE=LVCMOS33 PULL_MODE=NONE;
+IO_PORT "LED[5]" IO_TYPE=LVCMOS33 PULL_MODE=NONE;
+
+// UART
+IO_LOC "TXD" 32;
+IO_PORT "TXD" IO_TYPE=LVCMOS33 PULL_MODE=UP;
+IO_LOC "RXD" 31;
+IO_PORT "RXD" IO_TYPE=LVCMOS33 PULL_MODE=UP;
+

FemtoRV/BOARDS/tangnano9k.mk

@@ -0,0 +1,20 @@
+DEVICE=GW1NR-LV9QN88PC6/I5
+FAMILY=GW1N-9C
+
+YOSYS_TANGNANO9K_OPT=-q -p "synth_gowin -top $(PROJECTNAME); write_json $(PROJECTNAME)-synth.json"
+NEXTPNR_TANGNANO9K_OPT=--device ${DEVICE} --vopt family=${FAMILY} --vopt cst=BOARDS/tangnano9k.cst
+
+TANGNANO9K: TANGNANO9K.firmware_config TANGNANO9K.synth TANGNANO9K.prog
+
+TANGNANO9K.synth: FIRMWARE/firmware.hex 
+	yosys ${YOSYS_TANGNANO9K_OPT} ${VERILOGS}
+	nextpnr-himbaechel --json ${PROJECTNAME}-synth.json --write ${PROJECTNAME}.json
+	gowin_pack -d ${DEVICE} -o $(PROJECTNAME).bit
+
+TANGNANO9K.prog:
+	openFPGALoader --board tangnano9k femtosoc.bit
+
+TANGNANO9K.firmware_config:
+	BOARD=tangnano9k TOOLS/make_config.sh -DTANGNANO9K
+	(cd FIRMWARE; make libs)
+

FemtoRV/Makefile

@@ -16,6 +16,8 @@ include BOARDS/ecp5_evn.mk
 #include BOARDS/arty35_symbiflow.mk
 include BOARDS/arty35_yosys_nextpnr.mk
 include BOARDS/cmod_a7_yosys_nextpnr.mk
+include BOARDS/tangnano9k.mk
+include BOARDS/tangnano20k.mk
 
 
 .PHONY: all clean terminal testbench 

FemtoRV/RTL/CONFIGS/tangnano20k_config.v

@@ -0,0 +1,42 @@
+// Default femtosoc configuration file for Tangnano20k
+
+/*** Devices ******************************************************************/
+
+`define NRV_IO_LEDS          // Mapped IO, LEDs D1,D2,D3,D4 (D5 = errors)
+`define NRV_IO_UART          // Mapped IO, virtual UART (USB)
+//`define NRV_IO_SSD1351       // Mapped IO, 128x128x64K OLED screen
+//`define NRV_IO_MAX7219       // Mapped IO, 8x8 led matrix
+//`define NRV_MAPPED_SPI_FLASH // SPI flash mapped in address space. 
+
+/*** Processor configuration **************************************************/
+
+`define NRV_FREQ 70          // Frequency in MHz
+
+//         CORE                      RV32 subset    fmax validated-experimental
+//
+//`define NRV_FEMTORV32_QUARK       // RV32I          fmax = 80-110 MHz
+//`define NRV_FEMTORV32_TACHYON     // RV32I          fmax = 100-135 MHz
+//`define NRV_FEMTORV32_ELECTRON    // RV32IM         fmax = 70-80 MHz
+//`define NRV_FEMTORV32_INTERMISSUM // RV32IM,   IRQ  fmax = 60-80 MHz
+//`define NRV_FEMTORV32_GRACILIS    // RV32IMC,  IRQ  fmax = 60-80 MHz
+`define NRV_FEMTORV32_PETITBATEAU   // RV32IMFC, IRQ  fmax = 50-80 MHz
+//`define NRV_FEMTORV32_TESTDRIVE
+
+`define NRV_RESET_ADDR 0       // The address the processor jumps to on reset 
+
+/*** RAM (in bytes, needs to be a multiple of 4)*******************************/
+
+`define NRV_RAM 313107 // XXX
+
+/*** Advanced devices configuration *******************************************/
+
+`define NRV_IO_HARDWARE_CONFIG // Hardware config registers mapped in IO-Space
+                               // (note: firmware libfemtorv32 depends on it)
+
+/******************************************************************************/
+
+`define NRV_NEGATIVE_RESET // reset button active low
+
+`define NRV_CONFIGURED
+
+

FemtoRV/RTL/CONFIGS/tangnano9k_config.v

@@ -0,0 +1,41 @@
+// Default femtosoc configuration file for Tangnano9k
+
+/*** Devices ******************************************************************/
+
+`define NRV_IO_LEDS          // Mapped IO, LEDs D1,D2,D3,D4 (D5 = errors)
+`define NRV_IO_UART          // Mapped IO, virtual UART (USB)
+//`define NRV_IO_SSD1351       // Mapped IO, 128x128x64K OLED screen
+//`define NRV_IO_MAX7219       // Mapped IO, 8x8 led matrix
+//`define NRV_MAPPED_SPI_FLASH // SPI flash mapped in address space. 
+
+/*** Processor configuration **************************************************/
+
+`define NRV_FREQ 70          // Frequency in MHz
+
+//         CORE                      RV32 subset    fmax validated-experimental
+//
+`define NRV_FEMTORV32_QUARK       // RV32I          fmax = 80-110 MHz
+//`define NRV_FEMTORV32_TACHYON     // RV32I          fmax = 100-135 MHz
+//`define NRV_FEMTORV32_ELECTRON    // RV32IM         fmax = 70-80 MHz
+//`define NRV_FEMTORV32_INTERMISSUM // RV32IM,   IRQ  fmax = 60-80 MHz
+//`define NRV_FEMTORV32_GRACILIS    // RV32IMC,  IRQ  fmax = 60-80 MHz
+//`define NRV_FEMTORV32_PETITBATEAU   // RV32IMFC, IRQ  fmax = 50-80 MHz
+//`define NRV_FEMTORV32_TESTDRIVE
+
+`define NRV_RESET_ADDR 0       // The address the processor jumps to on reset 
+
+/*** RAM (in bytes, needs to be a multiple of 4)*******************************/
+
+`define NRV_RAM 32768 // XXX
+
+/*** Advanced devices configuration *******************************************/
+
+`define NRV_IO_HARDWARE_CONFIG // Hardware config registers mapped in IO-Space
+                               // (note: firmware libfemtorv32 depends on it)
+
+/******************************************************************************/
+
+`define NRV_NEGATIVE_RESET // reset button active low
+
+`define NRV_CONFIGURED
+

FemtoRV/RTL/PLL/femtopll.v

@@ -40,6 +40,8 @@ endmodule
   `include "pll_arty.v"
  `elsif CMODA7
   `include "pll_cmod_a7.v"
+ `elsif TANGNANO_9K
+  `include "pll_tangnano9k.v"
  `endif
 `endif
 

FemtoRV/RTL/PLL/gen_pll.sh

@@ -110,6 +110,57 @@ EOF
      endcase
    endgenerate
 endmodule  
+EOF
+      ;;
+   "TANGNANO9K"|"TANGNANO20K")
+      cat << EOF
+
+ module femtoPLL  #(
+    parameter freq = 40
+ ) (
+    input wire pclk,
+    output wire clk
+ );
+   rPLL #(
+EOF
+	if [ $FPGA_KIND = "TANGNANO9K" ]; then
+		echo '      .DEVICE("GW1NR-9C"),'
+	else
+		echo '      .DEVICE("GW2AR-18C"),'
+	fi
+cat << EOF
+      .FCLKIN("27")
+ ) pll (
+      .CLKOUT(clk),
+      .RESET(1'b0),
+      .RESET_P(1'b0),
+      .CLKIN(pclk),
+      .CLKFB(1'b0),
+      .FBDSEL(6'b0),
+      .IDSEL(6'b0),
+      .ODSEL(6'b0),
+      .PSDA(4'b0),
+      .DUTYDA(4'b0),
+      .FDLY(4'b0)
+   );
+   generate
+     case(freq)
+EOF
+      for OUTPUTFREQ in `cat frequencies.txt`
+      do
+        echo "     $OUTPUTFREQ: begin"
+        gowin_pll -d GW1NR-LV9QN88PC6/I5 -i $INPUTFREQ -o $OUTPUTFREQ \
+	    | egrep "IDIV_SEL|FBDIV_SEL|ODIV_SEL" \
+	    | sed -e 's|[:()]| |g' \
+	    | awk '{printf("      defparam pll%s = %s;\n",$1,$2);}'
+        echo "     end"
+      done
+      cat <<EOF
+     default: UNKNOWN_FREQUENCY unknown_frequency();
+     endcase
+  endgenerate   
+
+endmodule  
 EOF
       ;;
    *)

FemtoRV/RTL/PLL/gen_plls.sh

@@ -15,4 +15,10 @@ echo Generating PLL for ULX3S
 ./gen_pll.sh ECP5 25 > pll_ulx3s.v
 
 echo Generating PLL for ECP5 evaluation board
-./gen_pll.sh ECP5 12 > pll_ecp5_evn.v
+./gen_pll.sh ECP5 12 > pll_ecp5_evn.v
+
+echo Generating PLL for SIPEED Tangnano9k board
+./gen_pll.sh TANGNANO9K 27 > pll_tangnano9k.v
+
+echo Generating PLL for SIPEED Tangnano20k board
+./gen_pll.sh TANGNANO20K 27 > pll_tangnano20k.v