From 726d88878f16c15f66f51da7d2df772a5b836dd2 Mon Sep 17 00:00:00 2001
From: Iztok Jeras <iztok.jeras@gmail.com>
Date: Sun, 27 Mar 2022 20:36:14 +0200
Subject: [PATCH] RTL: fixed issue with memory access alignment

---
 FemtoRV/RTL/PROCESSOR/femtorv32_quark.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/FemtoRV/RTL/PROCESSOR/femtorv32_quark.v b/FemtoRV/RTL/PROCESSOR/femtorv32_quark.v
index f82d0113..2790c8a7 100644
--- a/FemtoRV/RTL/PROCESSOR/femtorv32_quark.v
+++ b/FemtoRV/RTL/PROCESSOR/femtorv32_quark.v
@@ -235,7 +235,7 @@ module FemtoRV32 #(
    // 32 bits, so we deactivate width test for mem_addr and writeBackData
 
    assign mem_addr = state[WAIT_INSTR_bit] | state[FETCH_INSTR_bit] ?
-                     PC : loadstore_addr ;
+                     PC : {loadstore_addr[ADDR_WIDTH-1:2], 2'b00} ;
 
    /***************************************************************************/
    // The value written back to the register file.