Merge pull request #207 from Boavizta/fix/change-die-size-unit

Change unit of cpu die size from cm2 to mm2
Boavizta · Aug 30, 2023 · 0092bf1 · 0092bf1
2 parents 743be68 + 36189a6
commit 0092bf1
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diff --git a/boaviztapi/data/archetypes/server.csv b/boaviztapi/data/archetypes/server.csv
@@ -11,5 +11,5 @@ storage_medium,,rack,1;1;2,,8;6;10,,,,,,8;4;32,1;2;6,,32;16;48,500;100;2000,,,,2
 ",
 storage_high,,rack,1;1;2,,10;16;24,,,,,,8;4;32,1;2;6,,"48,32,64",500;100;2000,,,,2;1;2,2.99;1;5,50;0;100,1,35040,"0.33;0.2;0.6
 ",
-dellR740,Dell,rack,2,0.245,24,,,,,,32,12,,1,400,,,,2;1;2,2.99;1;5,50;0;100,1,35040,"0.33;0.2;0.6
+dellR740,Dell,rack,2,24.5,24,,,,,,32,12,,1,400,,,,2;1;2,2.99;1;5,50;0;100,1,35040,"0.33;0.2;0.6
 ",
diff --git a/boaviztapi/data/crowdsourcing/cpu_manufacture.csv b/boaviztapi/data/crowdsourcing/cpu_manufacture.csv
@@ -1,38 +1,38 @@
-manufacturer,family,manufacture_date,process,die_size,core_units,die_size_per_core,Source
-Intel,skylake,2017,14,1.0183,2,0.51,https://en.wikichip.org/wiki/intel/microarchitectures/skylake_(client)#Dual-core
-Intel,skylake,2017,14,1.223,4,0.31,https://en.wikichip.org/wiki/intel/microarchitectures/skylake_(client)#Quad-core
-Intel,skylake,2017,14,3.2544,10,0.33,https://en.wikichip.org/wiki/intel/microarchitectures/skylake_(server)#Low_Core_Count_.28LCC.29
-Intel,skylake,2017,14,4.85,18,0.27,https://en.wikichip.org/wiki/intel/microarchitectures/skylake_(server)#High_Core_Count_.28HCC.29
-Intel,skylake,2017,14,6.94,28,0.25,https://en.wikichip.org/wiki/intel/microarchitectures/skylake_(server)#Extreme_Core_Count_.28XCC.29
-Intel,coffee lake,2017,14,1.26,4,0.32,https://en.wikichip.org/wiki/intel/microarchitectures/coffee_lake#Quad-Core
-Intel,coffee lake,2017,14,1.496,6,0.25,https://en.wikichip.org/wiki/intel/microarchitectures/coffee_lake#Hexa-Core
-Intel,coffee lake,2017,14,1.74,8,0.22,https://en.wikichip.org/wiki/intel/microarchitectures/coffee_lake#Octa-Core
-Intel,broadwell,2014,14,0.82,2,0.41,https://en.wikichip.org/wiki/intel/microarchitectures/broadwell_(client)#Dual-core
-Intel,broadwell,2014,14,1.82,4,0.46,https://en.wikichip.org/wiki/intel/microarchitectures/broadwell_(client)#Quad-core_Broadwell_with_Iris_Pro_die
-Intel,broadwell,2014,14,2.46,10,0.25,https://en.wikichip.org/wiki/intel/microarchitectures/broadwell_(client)#Deca-core_Broadwell
-Intel,broadwell,2014,14,3.0518,14,0.22,https://en.wikichip.org/wiki/intel/microarchitectures/broadwell_(client)#Die_Stats
-Intel,broadwell,2014,14,4.5612,24,0.19,https://en.wikichip.org/wiki/intel/microarchitectures/broadwell_(client)#Die_Stats
-Intel,haswell,2013,22,1.81,2,0.91,https://en.wikichip.org/wiki/intel/microarchitectures/haswell_(client)#Dual-core_GT3
-Intel,haswell,2013,22,2.6,4,0.65,https://en.wikichip.org/wiki/intel/microarchitectures/haswell_(client)#Quad-core_GT3
-Intel,haswell,2013,22,3.5552,8,0.44,https://en.wikichip.org/wiki/intel/microarchitectures/haswell_(client)#Octa-core
-Intel,haswell,2013,22,6.22,18,0.35,https://en.wikichip.org/wiki/intel/microarchitectures/haswell_(client)#Octadeca-core
-Intel,ivy bridge,2011,22,1.6,4,0.40,https://en.wikichip.org/wiki/intel/microarchitectures/ivy_bridge_(client)#Quad-core_Ivy_Bridge_die
-Intel,ivy bridge,2011,22,5.41,15,0.36,https://en.wikichip.org/wiki/intel/microarchitectures/ivy_bridge_(client)#Pentadeca-Core_Ivy_Bridge_die
-Intel,ivy bridge,2011,22,3.41,10,0.34,https://en.wikichip.org/wiki/intel/microarchitectures/ivy_bridge_(client)#Deca-core_Ivy_Bridge_Die
-Intel,ivy bridge,2011,22,2.565,6,0.43,https://en.wikichip.org/wiki/intel/microarchitectures/ivy_bridge_(client)#Hexa-core_Ivy_Bridge_Die
-Intel,sandy bridge,2010,32,1.49,2,0.75,https://en.wikichip.org/wiki/intel/microarchitectures/sandy_bridge_(client)#Dual-Core_.28GT2.29
-Intel,sandy bridge,2010,32,2.16,4,0.54,https://en.wikichip.org/wiki/intel/microarchitectures/sandy_bridge_(client)#Quad-Core
-Intel,kaby lake,2017,14,1.26,4,0.32,https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake
-Intel,ice lake,2019,10,6.28,40,0.16,https://fuse.wikichip.org/news/4734/intel-launches-3rd-gen-ice-lake-xeon-scalable/
-Intel,ice lake,2019,10,1.3,4,0.33,https://medium.com/@ewoutterhoeven/calculating-the-intel-ice-lake-quad-core-die-size-130mm2-ce18a44c5f05
-Intel,ice lake,2019,10,3.7,16,0.23,https://twitter.com/dylan522p/status/1326817993792266241?lang=en
-Intel,ice lake,2019,10,5.05,28,0.18,https://twitter.com/dylan522p/status/1326817993792266241?lang=en
-Intel,ice lake,2019,10,6.3,42,0.15,https://twitter.com/dylan522p/status/1326817993792266241?lang=en
-Amd,Rome,2019,7,13.09,16,0.82,https://www.techarp.com/computer/amd-zen-3-tech-report/ (74mm2*core_units+125mm2)
-Amd,Rome,2019,7,10.13,12,0.84,https://www.techarp.com/computer/amd-zen-3-tech-report/ (74mm2*core_units+125mm2)
-Amd,Rome,2019,7,7.17,8,0.90,https://www.techarp.com/computer/amd-zen-3-tech-report/ (74mm2*core_units+125mm2)
-Amd,Rome,2019,7,5.69,6,0.95,https://www.techarp.com/computer/amd-zen-3-tech-report/ (74mm2*core_units+125mm2)
-Amd,Milan,2020,7,14.162,16,0.89,https://www.techarp.com/computer/amd-zen-3-tech-report/ (80.7mm2*core_units+125mm2)
-Amd,Milan,2020,7,10.934,12,0.91,https://www.techarp.com/computer/amd-zen-3-tech-report/ (80.7mm2*core_units+125mm2)
-Amd,Milan,2020,7,7.706,8,0.96,https://www.techarp.com/computer/amd-zen-3-tech-report/ (80.7mm2*core_units+125mm2)
-Amd,Milan,2020,7,6.092,6,1.02,https://www.techarp.com/computer/amd-zen-3-tech-report/ (80.7mm2*core_units+125mm2)
+,manufacturer,family,manufacture_date,process,die_size,core_units,die_size_per_core,Source
+0,Intel,skylake,2017,14,101.83,2,51.0,https://en.wikichip.org/wiki/intel/microarchitectures/skylake_(client)#Dual-core
+1,Intel,skylake,2017,14,122.3,4,31.0,https://en.wikichip.org/wiki/intel/microarchitectures/skylake_(client)#Quad-core
+2,Intel,skylake,2017,14,325.44,10,33.0,https://en.wikichip.org/wiki/intel/microarchitectures/skylake_(server)#Low_Core_Count_.28LCC.29
+3,Intel,skylake,2017,14,485,18,27.0,https://en.wikichip.org/wiki/intel/microarchitectures/skylake_(server)#High_Core_Count_.28HCC.29
+4,Intel,skylake,2017,14,694.0,28,25.0,https://en.wikichip.org/wiki/intel/microarchitectures/skylake_(server)#Extreme_Core_Count_.28XCC.29
+5,Intel,coffee lake,2017,14,126.0,4,32.0,https://en.wikichip.org/wiki/intel/microarchitectures/coffee_lake#Quad-Core
+6,Intel,coffee lake,2017,14,149.6,6,25.0,https://en.wikichip.org/wiki/intel/microarchitectures/coffee_lake#Hexa-Core
+7,Intel,coffee lake,2017,14,174.0,8,22.0,https://en.wikichip.org/wiki/intel/microarchitectures/coffee_lake#Octa-Core
+8,Intel,broadwell,2014,14,82.0,2,41.0,https://en.wikichip.org/wiki/intel/microarchitectures/broadwell_(client)#Dual-core
+9,Intel,broadwell,2014,14,182.0,4,46.0,https://en.wikichip.org/wiki/intel/microarchitectures/broadwell_(client)#Quad-core_Broadwell_with_Iris_Pro_die
+10,Intel,broadwell,2014,14,246.0,10,25.0,https://en.wikichip.org/wiki/intel/microarchitectures/broadwell_(client)#Deca-core_Broadwell
+11,Intel,broadwell,2014,14,305.18,14,22.0,https://en.wikichip.org/wiki/intel/microarchitectures/broadwell_(client)#Die_Stats
+12,Intel,broadwell,2014,14,456.12,24,19.0,https://en.wikichip.org/wiki/intel/microarchitectures/broadwell_(client)#Die_Stats
+13,Intel,haswell,2013,22,181.0,2,91.0,https://en.wikichip.org/wiki/intel/microarchitectures/haswell_(client)#Dual-core_GT3
+14,Intel,haswell,2013,22,260.0,4,65.0,https://en.wikichip.org/wiki/intel/microarchitectures/haswell_(client)#Quad-core_GT3
+15,Intel,haswell,2013,22,355.52,8,44.0,https://en.wikichip.org/wiki/intel/microarchitectures/haswell_(client)#Octa-core
+16,Intel,haswell,2013,22,622.0,18,35.0,https://en.wikichip.org/wiki/intel/microarchitectures/haswell_(client)#Octadeca-core
+17,Intel,ivy bridge,2011,22,160.0,4,40.0,https://en.wikichip.org/wiki/intel/microarchitectures/ivy_bridge_(client)#Quad-core_Ivy_Bridge_die
+18,Intel,ivy bridge,2011,22,541.0,15,36.0,https://en.wikichip.org/wiki/intel/microarchitectures/ivy_bridge_(client)#Pentadeca-Core_Ivy_Bridge_die
+19,Intel,ivy bridge,2011,22,341.0,10,34.0,https://en.wikichip.org/wiki/intel/microarchitectures/ivy_bridge_(client)#Deca-core_Ivy_Bridge_Die
+20,Intel,ivy bridge,2011,22,256.5,6,43.0,https://en.wikichip.org/wiki/intel/microarchitectures/ivy_bridge_(client)#Hexa-core_Ivy_Bridge_Die
+21,Intel,sandy bridge,2010,32,149.0,2,75.0,https://en.wikichip.org/wiki/intel/microarchitectures/sandy_bridge_(client)#Dual-Core_.28GT2.29
+22,Intel,sandy bridge,2010,32,216.0,4,54.0,https://en.wikichip.org/wiki/intel/microarchitectures/sandy_bridge_(client)#Quad-Core
+23,Intel,kaby lake,2017,14,126.0,4,32.0,https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake
+24,Intel,ice lake,2019,10,628.0,40,16.0,https://fuse.wikichip.org/news/4734/intel-launches-3rd-gen-ice-lake-xeon-scalable/
+25,Intel,ice lake,2019,10,130.0,4,33.0,https://medium.com/@ewoutterhoeven/calculating-the-intel-ice-lake-quad-core-die-size-130mm2-ce18a44c5f05
+26,Intel,ice lake,2019,10,370.0,16,23.0,https://twitter.com/dylan522p/status/1326817993792266241?lang=en
+27,Intel,ice lake,2019,10,505.0,28,18.0,https://twitter.com/dylan522p/status/1326817993792266241?lang=en
+28,Intel,ice lake,2019,10,630.0,42,15.0,https://twitter.com/dylan522p/status/1326817993792266241?lang=en
+29,Amd,Rome,2019,7,1309.0,16,82.0,https://www.techarp.com/computer/amd-zen-3-tech-report/ (74mm2*core_units+125mm2)
+30,Amd,Rome,2019,7,1013,12,84.0,https://www.techarp.com/computer/amd-zen-3-tech-report/ (74mm2*core_units+125mm2)
+31,Amd,Rome,2019,7,717.0,8,90.0,https://www.techarp.com/computer/amd-zen-3-tech-report/ (74mm2*core_units+125mm2)
+32,Amd,Rome,2019,7,569.0,6,95.0,https://www.techarp.com/computer/amd-zen-3-tech-report/ (74mm2*core_units+125mm2)
+33,Amd,Milan,2020,7,1416.2,16,89.0,https://www.techarp.com/computer/amd-zen-3-tech-report/ (80.7mm2*core_units+125mm2)
+34,Amd,Milan,2020,7,1093.40,12,91.0,https://www.techarp.com/computer/amd-zen-3-tech-report/ (80.7mm2*core_units+125mm2)
+35,Amd,Milan,2020,7,770.6,8,96.0,https://www.techarp.com/computer/amd-zen-3-tech-report/ (80.7mm2*core_units+125mm2)
+36,Amd,Milan,2020,7,609.20,6,102.0,https://www.techarp.com/computer/amd-zen-3-tech-report/ (80.7mm2*core_units+125mm2)
diff --git a/boaviztapi/data/factors.yml b/boaviztapi/data/factors.yml
@@ -30,19 +30,19 @@
 
 "cpu": {
   "gwp": {
-    "die_impact": 1.97,
+    "die_impact": 0.0197,
     "impact": 9.14,
-    "constant_core_impact": 0.491
+    "constant_core_impact": 49.1
   },
   "pe": {
-    "die_impact": 26.50,
+    "die_impact": 0.2650,
     "impact": 156.00,
-    "constant_core_impact": 0.491
+    "constant_core_impact": 49.1
   },
   "adp": {
-    "die_impact": 5.80e-07,
+    "die_impact": 5.80e-09,
     "impact": 2.04e-02,
-    "constant_core_impact": 0.491
+    "constant_core_impact": 49.1
   }
 }
 

diff --git a/boaviztapi/model/component/cpu.py b/boaviztapi/model/component/cpu.py
@@ -36,14 +36,14 @@ def __init__(self, archetype=get_component_archetype(config["default_cpu"], "cpu
         )
         self.die_size_per_core = Boattribute(
             complete_function=self._complete_die_size_per_core,
-            unit="cm2",
+            unit="mm2",
             default=get_arch_value(archetype, 'die_size_per_core', 'default'),
             min=get_arch_value(archetype, 'die_size_per_core', 'min'),
             max=get_arch_value(archetype, 'die_size_per_core', 'max')
         )
         self.die_size = Boattribute(
             complete_function=self._complete_from_name,
-            unit="cm2",
+            unit="mm2",
             default=get_arch_value(archetype, 'die_size', 'default'),
             min=get_arch_value(archetype, 'die_size', 'min'),
             max=get_arch_value(archetype, 'die_size', 'max')
@@ -249,6 +249,5 @@ def _complete_from_name(self):
             if cores is not None:
                 self.core_units.set_completed(cores, min=cores_min, max=cores_max, source=f"Completed from name name based on {source}.")
             if die_size is not None:
-                # divide by 100 to convert mm2 into cm2
-                self.die_size.set_completed(die_size/100, min=die_size_min/100, max=die_size_max/100, source=f"{die_size_source} : Completed from name name based on {source}.")
+                self.die_size.set_completed(die_size, min=die_size_min, max=die_size_max, source=f"{die_size_source} : Completed from name name based on {source}.")
             self.name_completion = True
diff --git a/docs/docs/Explanations/components/cpu.md b/docs/docs/Explanations/components/cpu.md
@@ -7,9 +7,9 @@
 | units             | None | 1;1;1                           | CPU quantity                                  | 2                  |
 | usage             | None | See Usage                       | See usage                                     | ..                 |
 | core_units        | None | 24;1;64                         | Number of physical core on one CPU            | 12                 |
-| die_size          | cm2  | None                            | Size of the die                               | 1.1                |
+| die_size          | mm2  | None                            | Size of the die                               | 1.1                |
 | embeddedr         | None | None                            | Name of the CPU embeddedr                     | AMD                |
-| die_size_per_core | cm2  | (avg;min;max) in our dataset    | Size of the die divided by the number of core | 0.245              |
+| die_size_per_core | mm2  | (avg;min;max) in our dataset    | Size of the die divided by the number of core | 0.245              |
 | model_range       | None | None                            | Name of the cpu range or brand                | i7                 |
 | family            | None | None                            | Name of the architectural family (Generation) | Skylake            |
 | name              | None | None                            | Complete commercial name of the CPU           | Intel Core i7-1065 |

diff --git a/docs/docs/Reference/format/component_route.md b/docs/docs/Reference/format/component_route.md
@@ -1,3 +1,4 @@
+
 # Component routes
 
 Available components :
@@ -33,7 +34,7 @@ You can set a units. If so, all the impacts will be multiplied by the number of
 ``` json
 {
    "core_units": 24,
-   "die_size_per_core": 0.245
+   "die_size_per_core": 245
 }
 ```
 

diff --git a/docs/docs/Reference/format/server_route.md b/docs/docs/Reference/format/server_route.md
@@ -51,7 +51,7 @@ Specific needed data are sent to apply the bottom-up methodology.
         {
             "units": 2,
             "core_units": 24,
-            "die_size_per_core": 0.245
+            "die_size_per_core": 245
         },
         "ram":
         [

diff --git a/docs/docs/getting_started/cpu_component.md b/docs/docs/getting_started/cpu_component.md
@@ -173,12 +173,12 @@ Result :
       "max": 64
     },
     "die_size_per_core": {
-      "value": 0.25,
+      "value": 25,
       "status": "COMPLETED",
-      "unit": "cm2",
+      "unit": "mm2",
       "source": "https://en.wikichip.org/wiki/intel/microarchitectures/skylake_(server)#Extreme_Core_Count_.28XCC.29",
-      "min": 0.25,
-      "max": 0.27
+      "min": 25,
+      "max": 27
     },
     "model_range": {
       "value": "Xeon Gold",
@@ -378,12 +378,12 @@ Result :
       "status": "INPUT"
     },
     "die_size_per_core": {
-      "value": 0.25,
+      "value": 25,
       "status": "COMPLETED",
-      "unit": "cm2",
+      "unit": "mm2",
       "source": "https://en.wikichip.org/wiki/intel/microarchitectures/skylake_(server)#Extreme_Core_Count_.28XCC.29",
-      "min": 0.25,
-      "max": 0.27
+      "min": 25,
+      "max": 27
     },
     "family": {
       "value": "skylake",

diff --git a/docs/docs/getting_started/single_server.md b/docs/docs/getting_started/single_server.md
@@ -200,12 +200,12 @@ It will return:
         "max": 32
       },
       "die_size_per_core": {
-        "value": 0.48162162162162164,
+        "value": 48.162162162162164,
         "status": "COMPLETED",
-        "unit": "cm2",
+        "unit": "mm2",
         "source": "Average for all families",
-        "min": 0.15,
-        "max": 1.02
+        "min": 15,
+        "max": 102
       },
       "duration": {
         "value": 35040,
@@ -579,7 +579,7 @@ curl -X 'POST' \
     "cpu": {
       "units": 2,
       "core_units": 12,
-      "die_size_per_core": 0.245
+      "die_size_per_core": 245
     },
     "ram": [
       {