(autogenerated by mkmbox.py)
| Offset | Name | Size | Direction | Desc | Note |
|---|---|---|---|---|---|
| 0 | MB0_MAGIC_NUMBER | 2 | MCC=>FPGA | Mailbox magic number | Access by byte as: MB0_MAGIC_NUMBER_x (x=0,1) |
| 2 | MB0_VERSION_MAJOR | 1 | MCC=>FPGA | Mailbox major version | |
| 3 | MB0_VERSION_MINOR | 1 | MCC=>FPGA | Mailbox minor version |
| Offset | Name | Size | Direction | Desc | Note |
|---|---|---|---|---|---|
| 0 | MB2_FMC_MGT_CTL | 1 | FPGA=>MMC | Input is bitfield. See scripts/README.md mgtmux_mbox.sh. |
| Offset | Name | Size | Direction | Desc | Note |
|---|---|---|---|---|---|
| 0 | MB3_COUNT | 2 | MCC=>FPGA | Mailbox update counter | Access by byte as: MB3_COUNT_x (x=0,1) |
| 2 | MB3_WD_STATE | 1 | MCC=>FPGA | Watchdog bitfile state. 0=STATE_BOOT, 1=STATE_GOLDEN, 2=STATE_USER | |
| 4 | MB3_LM75_0 | 2 | MCC=>FPGA | Returns LM75_0 temperature in units of 0.5degC | Access by byte as: MB3_LM75_0_x (x=0,1) |
| 6 | MB3_LM75_1 | 2 | MCC=>FPGA | Returns LM75_1 temperature in units of 0.5degC | Access by byte as: MB3_LM75_1_x (x=0,1) |
| 8 | MB3_FMC_ST | 1 | MCC=>FPGA | Returns bitfield. 0=FMC1_PWR, 1=FMC1_FUSE, 2=FMC2_PWR, 3=FMC1_FUSE | |
| 9 | MB3_PWR_ST | 1 | MCC=>FPGA | Returns bitfield. 0=PSU_EN, 1=~POE_PRESENT, 2=OTEMP | |
| 10 | MB3_MGTMUX_ST | 1 | MCC=>FPGA | Returns bitfield of mux pin states. 0=MUX0_MMC, 1=MUX1_MMC, 2=MUX2_MMC | |
| 12 | MB3_GIT32 | 4 | MCC=>FPGA | 32-bit git commit ID | Access by byte as: MB3_GIT32_x (x=0,1,2,3) |
| Offset | Name | Size | Direction | Desc | Note |
|---|---|---|---|---|---|
| 0 | MB4_MAX_T1_HI | 1 | MCC=>FPGA | Returns raw value of MAX6639 register TEMP_CH1 | |
| 1 | MB4_MAX_T1_LO | 1 | MCC=>FPGA | Returns raw value of MAX6639 register TEMP_EXT_CH1 | |
| 2 | MB4_MAX_T2_HI | 1 | MCC=>FPGA | Returns raw value of MAX6639 register TEMP_CH2 | |
| 3 | MB4_MAX_T2_LO | 1 | MCC=>FPGA | Returns raw value of MAX6639 register TEMP_EXT_CH2 | |
| 4 | MB4_MAX_F1_TACH | 1 | MCC=>FPGA | Returns raw value of MAX6639 register FAN1_TACH_CNT | |
| 5 | MB4_MAX_F2_TACH | 1 | MCC=>FPGA | Returns raw value of MAX6639 register FAN2_TACH_CNT | |
| 6 | MB4_MAX_F1_DUTY | 1 | MCC=>FPGA | Returns MAX6639 ch1 fan duty cycle as duty_percent*1.2. | |
| 7 | MB4_MAX_F2_DUTY | 1 | MCC=>FPGA | Returns MAX6639 ch2 fan duty cycle as duty_percent*1.2. | |
| 8 | MB4_PCB_REV | 1 | MCC=>FPGA | Returns bitfield. [4:7]=Board type (0=sim, 1=marble, 2=mini), [0:3]=PCB rev | |
| 10 | MB4_COUNT | 2 | MCC=>FPGA | Mailbox update counter | Access by byte as: MB4_COUNT_x (x=0,1) |
| 12 | MB4_HASH | 4 | MCC=>FPGA | Hash of mailbox functionality. | Access by byte as: MB4_HASH_x (x=0,1,2,3) |
| Offset | Name | Size | Direction | Desc | Note |
|---|---|---|---|---|---|
| 0 | MB5_I2C_BUS_STATUS | 1 | MMC<=>FPGA | Returns logical OR of all I2C function return values. Write nonzero value to clear status. |
| Offset | Name | Size | Direction | Desc | Note |
|---|---|---|---|---|---|
| 0 | MB6_FSYNTH_I2C_ADDR | 1 | MCC=>FPGA | I2C address of frequency synthesizer (si570) in 8-bit (shifted) format. | |
| 1 | MB6_FSYNTH_CONFIG | 1 | MCC=>FPGA | Config byte of frequency synthesizer (si570). Bit 0: Enable pin polarity (0 = polarity low, 1 = polarity high). Bit 1: Temperature stability (0 = 20 ppm or 50 ppm, 1 = 7 ppm) Bits 2-5: reserved. Bits [7:6]: 0b01 = Valid config (avoid acting on invalid 0xff or 0x00). | |
| 2 | MB6_FSYNTH_FREQ | 4 | MCC=>FPGA | Startup frequency of frequency synthesizer (si570) in Hz. | Access by byte as: MB6_FSYNTH_FREQ_x (x=0,1,2,3) |
| Offset | Name | Size | Direction | Desc | Note |
|---|---|---|---|---|---|
| 0 | MB7_WD_NONCE | 8 | MCC=>FPGA | A 64-bit nonce to be used by the remote host to produce a watchdog MAC. | Access by byte as: MB7_WD_NONCE_x (x=0,1,2,3,4,5,6,7) |
| Offset | Name | Size | Direction | Desc | Note |
|---|---|---|---|---|---|
| 0 | MB8_WD_HASH | 8 | FPGA=>MMC | 64-bit MAC supplied by the remote host to reset watchdog timer. | Access by byte as: MB8_WD_HASH_x (x=0,1,2,3,4,5,6,7) |
| Offset | Name | Size | Direction | Desc | Note |
|---|---|---|---|---|---|
| 0 | MB9_VOUT_1V0 | 2 | MCC=>FPGA | Voltage of the 1V0 rail measured internally by the power supply. | Access by byte as: MB9_VOUT_1V0_x (x=0,1) |
| 2 | MB9_IOUT_1V0 | 2 | MCC=>FPGA | Output current from the 1V0 rail measured internally by the power supply. | Access by byte as: MB9_IOUT_1V0_x (x=0,1) |
| 4 | MB9_VOUT_1V8 | 2 | MCC=>FPGA | Voltage of the 1V8 rail measured internally by the power supply. | Access by byte as: MB9_VOUT_1V8_x (x=0,1) |
| 6 | MB9_IOUT_1V8 | 2 | MCC=>FPGA | Output current from the 1V8 rail measured internally by the power supply. | Access by byte as: MB9_IOUT_1V8_x (x=0,1) |
| 8 | MB9_VOUT_2V5 | 2 | MCC=>FPGA | Voltage of the 2V5 rail measured internally by the power supply. | Access by byte as: MB9_VOUT_2V5_x (x=0,1) |
| 10 | MB9_IOUT_2V5 | 2 | MCC=>FPGA | Output current from the 2V5 rail measured internally by the power supply. | Access by byte as: MB9_IOUT_2V5_x (x=0,1) |
| 12 | MB9_VOUT_3V3 | 2 | MCC=>FPGA | Voltage of the 3V3 rail measured internally by the power supply. | Access by byte as: MB9_VOUT_3V3_x (x=0,1) |
| 14 | MB9_IOUT_3V3 | 2 | MCC=>FPGA | Output current from the 3V3 rail measured internally by the power supply. | Access by byte as: MB9_IOUT_3V3_x (x=0,1) |