From 2f4dd681c682c3aa79b2d3f21d9a3d1743630a31 Mon Sep 17 00:00:00 2001 From: Andrew Nolte Date: Sun, 2 Jun 2024 23:45:40 -0400 Subject: [PATCH] tweak readme --- README.md | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/README.md b/README.md index b7698f8..22f5728 100644 --- a/README.md +++ b/README.md @@ -35,6 +35,7 @@ Verible supports both SystemVerilog and Verilog, while the others are only veril - Zero config required if module names match file - Code completion suggests relevant symbols- package refs, params, ports, macros, builtins, etc. - Hover and Completion for builtin functions like $bits() +### See a detailed feature list and roadmap in [FEATURES.md](FEATURES.md) #### Third party options: [`verible-verilog-ls`](https://github.com/chipsalliance/verible/tree/master/verilog/tools/ls) || [`veridian`](https://github.com/vivekmalneedi/veridian) || [`svls`](https://github.com/dalance/svls) @@ -90,7 +91,3 @@ This is the recommended linter because it's the [fastest and most compliant](htt ### See all config options in [CONFIG.md](CONFIG.md) For debugging your config, you can see the logs in Output tab > select 'verilog' in the dropdown - - -## Features -See a detailed feature list and roadmap in [FEATURES.md](FEATURES.md)