From 802587fc933fd80678352b991852983d8c4a5cb1 Mon Sep 17 00:00:00 2001 From: Dr Maxim Orlovsky Date: Fri, 15 Nov 2024 01:31:17 +0100 Subject: [PATCH] chore: release v0.12.0-beta.2 --- Cargo.lock | 2 +- Cargo.toml | 2 +- src/core/core.rs | 13 +++++++++---- src/core/mod.rs | 1 + src/core/util.rs | 3 +++ src/isa/arch.rs | 2 +- src/isa/ctrl/exec.rs | 6 +++--- src/isa/instr.rs | 2 +- src/library/lib.rs | 2 +- src/library/marshaller.rs | 2 +- src/vm.rs | 2 +- 11 files changed, 23 insertions(+), 14 deletions(-) diff --git a/Cargo.lock b/Cargo.lock index feea9c8..375c1d4 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -4,7 +4,7 @@ version = 3 [[package]] name = "aluvm" -version = "0.12.0-beta.1" +version = "0.12.0-beta.2" dependencies = [ "amplify", "ascii-armor", diff --git a/Cargo.toml b/Cargo.toml index 9df4190..5575c8d 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -1,7 +1,7 @@ [package] name = "aluvm" description = "Functional registry-based RISC virtual machine" -version = "0.12.0-beta.1" +version = "0.12.0-beta.2" authors = ["Dr Maxim Orlovsky "] repository = "https://github.com/aluvm/rust-aluvm" homepage = "https://aluvm.org" diff --git a/src/core/core.rs b/src/core/core.rs index 95e34bb..ddd30c4 100644 --- a/src/core/core.rs +++ b/src/core/core.rs @@ -126,9 +126,9 @@ pub struct Core< #[strict_type(lib = LIB_NAME_ALUVM)] #[cfg_attr(feature = "serde", derive(Serialize, Deserialize))] pub struct CoreConfig { - /// Initial value for the [`Core::ch`] flag. + /// Initial value for the `CH` register. pub halt: bool, - /// Initial value for the [`Core::cl`] flag. + /// Initial value for the `CL` register. pub complexity_lim: Option, } @@ -141,15 +141,20 @@ impl Default for CoreConfig { /// /// - [`CoreConfig::halt`] /// - [`CoreConfig::complexity_lim`] - /// - [`CoreConfig::field_order`] fn default() -> Self { CoreConfig { halt: true, complexity_lim: None } } } +impl Default + for Core +{ + fn default() -> Self { Core::new() } +} + impl Core { /// Initializes registers. Sets `st0` to `true`, counters to zero, call stack to empty and the /// rest of registers to `None` value. /// - /// An alias for [`AluCore::with`]`(`[`CoreConfig::default()`]`)`. + /// An alias for [`Core::with`]`(`[`CoreConfig::default()`]`)`. #[inline] pub fn new() -> Self { assert!(CALL_STACK_SIZE <= CALL_STACK_SIZE_MAX as usize, "Call stack size is too large"); diff --git a/src/core/mod.rs b/src/core/mod.rs index 69a7613..0d6eb47 100644 --- a/src/core/mod.rs +++ b/src/core/mod.rs @@ -24,6 +24,7 @@ //! AluVM registers system +#[allow(clippy::module_inception)] mod core; mod microcode; mod util; diff --git a/src/core/util.rs b/src/core/util.rs index 149828d..d6fb95d 100644 --- a/src/core/util.rs +++ b/src/core/util.rs @@ -35,10 +35,12 @@ pub trait Register: Copy + Ord + Debug + Display { #[derive(Debug)] pub enum NoRegs {} +#[allow(clippy::non_canonical_clone_impl)] impl Clone for NoRegs { fn clone(&self) -> Self { unreachable!() } } impl Copy for NoRegs {} +#[allow(clippy::non_canonical_clone_impl)] impl PartialEq for NoRegs { fn eq(&self, _: &Self) -> bool { unreachable!() } } @@ -46,6 +48,7 @@ impl Eq for NoRegs {} impl Ord for NoRegs { fn cmp(&self, _: &Self) -> Ordering { unreachable!() } } +#[allow(clippy::non_canonical_partial_ord_impl)] impl PartialOrd for NoRegs { fn partial_cmp(&self, _: &Self) -> Option { unreachable!() } } diff --git a/src/isa/arch.rs b/src/isa/arch.rs index 0a8bbbd..c0be7a8 100644 --- a/src/isa/arch.rs +++ b/src/isa/arch.rs @@ -58,7 +58,7 @@ impl From<&'static str> for IsaId { fn from(id: &'static str) -> Self { Self(RString::from(id)) } } -/// Reserved instruction, which equal to [`ControlFlowOp::Fail`]. +/// Reserved instruction, which equal to [`crate::ExecStep::FailHalt`]. #[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Hash, Debug, Display, Default)] #[display("halt {0:#02X}#h")] pub struct ReservedInstr(/** Reserved instruction op code value */ pub(super) u8); diff --git a/src/isa/ctrl/exec.rs b/src/isa/ctrl/exec.rs index cec21db..1a2a1f6 100644 --- a/src/isa/ctrl/exec.rs +++ b/src/isa/ctrl/exec.rs @@ -69,8 +69,8 @@ impl Instruction for Instr { _: &Self::Context<'_>, ) -> ExecStep> { match self { - Instr::Ctrl(instr) => instr.exec(site, core, &mut ()), - Instr::Reserved(instr) => instr.exec(site, core, &mut ()), + Instr::Ctrl(instr) => instr.exec(site, core, &()), + Instr::Reserved(instr) => instr.exec(site, core, &()), } } } @@ -153,7 +153,7 @@ impl Instruction for CtrlInstr { let Some(pos) = current.offset.checked_add_signed(shift as i16) else { return ExecStep::FailHalt; }; - return ExecStep::Jump(pos); + ExecStep::Jump(pos) }; match *self { diff --git a/src/isa/instr.rs b/src/isa/instr.rs index e5ce2c1..d828dfa 100644 --- a/src/isa/instr.rs +++ b/src/isa/instr.rs @@ -62,7 +62,7 @@ pub trait Instruction: Display + Debug + Bytecode { type Context<'ctx>; fn isa_ext() -> TinyOrdSet { - let iter = Self::ISA_EXT.into_iter().copied().map(IsaId::from); + let iter = Self::ISA_EXT.iter().copied().map(IsaId::from); TinyOrdSet::from_iter_checked(iter) } diff --git a/src/library/lib.rs b/src/library/lib.rs index 885fe5c..cf5dffc 100644 --- a/src/library/lib.rs +++ b/src/library/lib.rs @@ -35,7 +35,7 @@ use strict_encoding::{StrictDeserialize, StrictSerialize}; use crate::core::SiteId; use crate::{IsaId, Site, LIB_NAME_ALUVM}; -pub const LIB_ID_TAG: &'static str = "urn:ubideco:aluvm:lib:v01#241020"; +pub const LIB_ID_TAG: &str = "urn:ubideco:aluvm:lib:v01#241020"; /// Unique identifier for an AluVM library. #[derive(Wrapper, Copy, Clone, Ord, PartialOrd, Eq, PartialEq, Hash, Default, Debug, From)] diff --git a/src/library/marshaller.rs b/src/library/marshaller.rs index f2ec9b9..de0f193 100644 --- a/src/library/marshaller.rs +++ b/src/library/marshaller.rs @@ -423,7 +423,7 @@ where if len >= u16::MAX as usize { return Err(MarshallError::DataExceedsLimit(len)); } - let offset = self.write_unique(&data)?; + let offset = self.write_unique(data)?; self.write_word(offset)?; self.write_word(len as u16) } diff --git a/src/vm.rs b/src/vm.rs index 88d85f0..6fb9d45 100644 --- a/src/vm.rs +++ b/src/vm.rs @@ -31,7 +31,7 @@ use crate::isa::{Instr, Instruction}; use crate::library::{Lib, LibId, LibSite}; /// Alu virtual machine providing single-core execution environment -#[derive(Clone, Debug)] +#[derive(Clone, Debug, Default)] pub struct Vm> where Isa: Instruction {