diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 1658ae0f2a4..cdddb129395 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -228,6 +228,23 @@ csr_test:
     - source verif/regress/dv-riscv-csr-access-test.sh
     - python3 .gitlab-ci/scripts/report_simu.py verif/sim/logfile.log
 
+mmu_sv32_test:
+  extends:
+    - .verif_test
+    - .template_job_short_ci
+  parallel:
+    matrix:
+      - DV_TARGET: [cv32a60x]
+  variables:
+    DV_SIMULATORS: "veri-testharness,spike"
+    DASHBOARD_JOB_TITLE: "mmu_sv32_test $DV_TARGET"
+    DASHBOARD_JOB_DESCRIPTION: "MMU SV32 regression suite"
+    DASHBOARD_SORT_INDEX: 0
+    DASHBOARD_JOB_CATEGORY: "Test suites"
+  script:
+    - source verif/regress/dv-riscv-mmu-sv32-test.sh
+    - python3 .gitlab-ci/scripts/report_simu.py verif/sim/logfile.log
+
 pub_hwconfig:
   extends:
     - .verif_test
diff --git a/verif/regress/dv-riscv-mmu-sv32-test.sh b/verif/regress/dv-riscv-mmu-sv32-test.sh
new file mode 100644
index 00000000000..ca03934d105
--- /dev/null
+++ b/verif/regress/dv-riscv-mmu-sv32-test.sh
@@ -0,0 +1,31 @@
+# Copyright 2021 Thales DIS design services SAS
+#
+# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
+# You may obtain a copy of the License at https://solderpad.org/licenses/
+#
+# Original Author: Jean-Roch COULON - Thales
+
+# where are the tools
+if ! [ -n "$RISCV" ]; then
+  echo "Error: RISCV variable undefined"
+  return
+fi
+
+# install the required tools
+source verif/regress/install-cva6.sh
+source verif/regress/install-riscv-dv.sh
+source verif/regress/install-riscv-arch-test.sh
+
+if ! [ -n "$DV_TARGET" ]; then
+  DV_TARGET=cv64a6_imafdc_sv39
+fi
+
+if ! [ -n "$DV_SIMULATORS" ]; then
+  DV_SIMULATORS=veri-testharness,spike
+fi
+
+cd verif/sim
+python3 cva6.py --testlist=../tests/testlist_riscv-mmu-sv32-test-$DV_TARGET.yaml --target $DV_TARGET --iss_yaml=cva6.yaml --iss=$DV_SIMULATORS $DV_OPTS --linker=../tests/riscv-arch-test/riscv-target/spike/link.ld
+cd -