From 40ff47bebe9d5fc23afeee4b6c23b7cf7c230fb2 Mon Sep 17 00:00:00 2001 From: mazharali09 <2019ee186@student.uet.edu.pk> Date: Fri, 8 Sep 2023 21:15:19 +0500 Subject: [PATCH] changes for test cli --- core/cache_subsystem/wt_dcache_wbuffer.sv | 21 +-------------------- core/frontend/instr_queue.sv | 2 +- core/issue_read_operands.sv | 2 +- 3 files changed, 3 insertions(+), 22 deletions(-) diff --git a/core/cache_subsystem/wt_dcache_wbuffer.sv b/core/cache_subsystem/wt_dcache_wbuffer.sv index c68de4e5f2..9da533584d 100644 --- a/core/cache_subsystem/wt_dcache_wbuffer.sv +++ b/core/cache_subsystem/wt_dcache_wbuffer.sv @@ -190,36 +190,17 @@ module wt_dcache_wbuffer import ariane_pkg::*; import wt_cache_pkg::*; #( assign miss_size_o = riscv::IS_XLEN64 ? toSize64(bdirty[dirty_ptr]): toSize32(bdirty[dirty_ptr]); - // replicate transfers shorter than a dword - /* - always_comb begin - if (riscv::IS_XLEN64) - miss_wdata_o = repData64(wbuffer_dirty_mux.data, bdirty_off, miss_size_o[1:0]); - else - miss_wdata_o = repData32(wbuffer_dirty_mux.data, bdirty_off, miss_size_o[1:0]); - end*/ + // replicate transfers shorter than a dword assign miss_wdata_o = riscv::IS_XLEN64 ? repData64(wbuffer_dirty_mux.data, bdirty_off, miss_size_o[1:0]): repData32(wbuffer_dirty_mux.data, bdirty_off, miss_size_o[1:0]); if (ariane_pkg::DATA_USER_EN) begin - /* - if (riscv::IS_XLEN64) - assign miss_wuser_o = repData64(wbuffer_dirty_mux.user, bdirty_off, miss_size_o[1:0]); - else - assign miss_wuser_o = repData32(wbuffer_dirty_mux.user, bdirty_off, miss_size_o[1:0]); - */ assign miss_wuser_o = riscv::IS_XLEN64 ? repData64(wbuffer_dirty_mux.user, bdirty_off, miss_size_o[1:0]): repData32(wbuffer_dirty_mux.user, bdirty_off, miss_size_o[1:0]); end else begin assign miss_wuser_o = '0; end - /* - if (riscv::IS_XLEN64) - assign tx_be = to_byte_enable8(bdirty_off, miss_size_o[1:0]); - else - assign tx_be = to_byte_enable4(bdirty_off, miss_size_o[1:0]); - */ assign tx_be = riscv::IS_XLEN64 ? to_byte_enable8(bdirty_off, miss_size_o[1:0]): to_byte_enable4(bdirty_off, miss_size_o[1:0]); diff --git a/core/frontend/instr_queue.sv b/core/frontend/instr_queue.sv index cc5dca5310..a101f1f762 100644 --- a/core/frontend/instr_queue.sv +++ b/core/frontend/instr_queue.sv @@ -279,7 +279,7 @@ module instr_queue import ariane_pkg::*; #( end fetch_entry_o.instruction = instr_data_out[i].instr; fetch_entry_o.ex.valid = instr_data_out[i].ex != ariane_pkg::FE_NONE; - fetch_entry_o.ex.tval = {/*{64-riscv::VLEN{1'b0}},*/ instr_data_out[i].ex_vaddr}; + fetch_entry_o.ex.tval = {instr_data_out[i].ex_vaddr}; fetch_entry_o.branch_predict.cf = instr_data_out[i].cf; pop_instr[i] = fetch_entry_valid_o & fetch_entry_ready_i; end diff --git a/core/issue_read_operands.sv b/core/issue_read_operands.sv index ca53ad55fe..8d9a0ac9aa 100644 --- a/core/issue_read_operands.sv +++ b/core/issue_read_operands.sv @@ -222,7 +222,7 @@ module issue_read_operands import ariane_pkg::*; #( imm_n = is_imm_fpr_cfg(issue_instr_i.op, CVA6Cfg.FpPresent) ? {{riscv::XLEN-CVA6Cfg.FLen{1'b0}}, operand_c_regfile} : issue_instr_i.op == OFFLOAD ? operand_c_regfile : issue_instr_i.result; end else begin - imm_n = is_imm_fpr_cfg(issue_instr_i.op, CVA6Cfg.FpPresent) ? {/*{riscv::XLEN-CVA6Cfg.FLen{1'b0}},*/ operand_c_regfile} : issue_instr_i.result; + imm_n = is_imm_fpr_cfg(issue_instr_i.op, CVA6Cfg.FpPresent) ? {operand_c_regfile} : issue_instr_i.result; end trans_id_n = issue_instr_i.trans_id; fu_n = issue_instr_i.fu;