diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index eb3bacd64f..1658ae0f2a 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -1,4 +1,4 @@ -# Copyright 2022 Thales DIS design services SAS +# Copyright 2022 Thales Silicon Security # # Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -7,36 +7,24 @@ # # Original Author: Yannick Casamatta (yannick.casamatta@thalesgroup.com) -# Project maintainers must define following variables to adapt this CI to their runtime environment (Settings > CI/CD > Variables) -# - RUN_CORE_CI: 'true'/'false' -# - SETUP_CI_CORE_BRANCH: master -# - RUN_CORE_V_VERIF_CI: 'true'/'false' -# - SETUP_CI_CVV_BRANCH: master -# - RUN_EXTERNAL_CI: 'true'/'false' -# - SETUP_CI_BRANCH: master - +# Please refer to .gitlab-ci/README.md to add jobs -# A git repository named "setup-ci" must be created in the same namespace as cva6 and must contain the following files: -# - 'cva6/cva6.yml' (if RUN_CORE_CI == 'true') -# - 'cva6/core-v-verif-cva6.yml' (if RUN_CVV_CI == 'true') -# - 'common/cva6.yml' (if $RUN_EXTERNAL_CI == 'true') -# Each of these files must at least contain the variables necessary for the execution of the associated downstream pipeline. -# Other elements such as new jobs can be added to overload the associated downstream pipeline included in this repository. -# Example for core-v-verif can be found in repository core-v-verif, path ".gitlab-ci/setup-ci-example/" - -# Guidelines: -# - Prefer using parent-child pipelines instead of including yml for ease of maintenance. -# - Specific elements should be defined in the triggered yml to avoid conflicts between pipelines. -# - In this file, only generic job/variables should be declared. +# Project maintainers must define following variables to adapt this CI to their runtime environment (Settings > CI/CD > Variables) +# - SETUP_CI_CVV_BRANCH: master (the main branch of CVA6 repository) +# A git repository named "setup-ci" must be created in the same namespace as cva6 and must contain the following file: +# - 'cva6/core-v-verif-cva6.yml' +# +# This file must at least contain the variables necessary for the execution of +# this pipeline. +# Other elements such as new jobs can be added to overload the associated +# downstream pipeline included in this repository. +# Example can be found in ".gitlab-ci/setup-ci-example/" -include: +include: - project: '$CI_PROJECT_NAMESPACE/setup-ci' ref: '$SETUP_CI_CVV_BRANCH' - file: 'cva6/cva6-core-v-verif.yml' - rules: - - if: '$RUN_CORE_V_VERIF_CI == "true"' - + file: 'cva6/core-v-verif-cva6.yml' workflow: rules: @@ -60,124 +48,576 @@ workflow: CORE_V_VERIF_BRANCH: $CI_COMMIT_REF_NAME - when: never +variables: + GIT_SUBMODULE_STRATEGY: recursive + TAGS_RUNNER: $TAGS_RUNNER + DASHBOARD: "cva6" + WORKFLOW_EVENT: $CI_PIPELINE_SOURCE + +# macro: job that does not require cloning anythings +.template_job_low_footprint: + variables: + GIT_STRATEGY: none + +# macro: job always launched (if pipeline is created) +.template_job_full_ci: + tags: [$TAGS_RUNNER] + rules: + - when: on_success + +# macro: job launched only on main branches, other case set to manual (if pipeline is created) +.template_job_short_ci: + tags: [$TAGS_RUNNER] + rules: + - if: '$CI_WEIGHT == "forced"' + when: on_success + - if: '$CI_WEIGHT == "full"' + when: on_success + - when: manual + allow_failure: true + +# macro: job set to manual (if pipeline is created) +.template_job_always_manual: + tags: [$TAGS_RUNNER] + rules: + - if: '$CI_WEIGHT == "forced"' + when: on_success + - when: manual + allow_failure: true stages: - - build - - test + - build tools + - smoke tests + - verif tests + - backend tests + - find failures + - report +.verif_test: + stage: verif tests + before_script: + - mkdir -p tools + - mv artifacts/tools/spike tools + - rm -rf artifacts/ + - mkdir -p artifacts/{reports,logs} + - python3 .gitlab-ci/scripts/report_fail.py + - echo $SYN_VCS_BASHRC; source $SYN_VCS_BASHRC + artifacts: &artifacts + when: always + paths: + - artifacts/ + +.backend_test: + stage: backend tests + before_script: + - mkdir -p artifacts/{reports,logs} + - python3 .gitlab-ci/scripts/report_fail.py + artifacts: *artifacts -check_env: +pub_check_env: + stage: build tools + extends: + - .template_job_low_footprint + - .template_job_full_ci + script: + - env + +pub_build_tools: + stage: build tools + extends: + - .template_job_full_ci + script: + # ROOT_PROJECT is used by Spike installer and designates the toplevel of core-v-verif tree. + - 'export ROOT_PROJECT=$(pwd)' + # If a local build of Spike is requested, clean up build and installation directories. + - '[ -n "$SPIKE_INSTALL_DIR" -a "$SPIKE_INSTALL_DIR" = "__local__" ] && rm -rf vendor/riscv/riscv-isa-sim/build' + - '[ -n "$SPIKE_INSTALL_DIR" -a "$SPIKE_INSTALL_DIR" = "__local__" ] && rm -rf tools/spike' + # Create default directory corresponding to the artifact path. + - mkdir -p tools/spike + # Set up Spike, whether locally built or pre-installed. + # If initially set to "__local__", SPIKE_INSTALL_DIR will be resolved + # to an absolute path by the installation script. + - source verif/regress/install-spike.sh + # Strip locally built binaries and libraries to reduce artifact size. + - '[ -f $(pwd)/tools/spike/bin/spike ] && strip $(pwd)/tools/spike/bin/spike* $(pwd)/tools/spike/lib/lib*.*' + - mkdir -p artifacts/tools/ + - mv tools/spike artifacts/tools/ + artifacts: + paths: + - artifacts/tools/spike/* + +pub_smoke: + stage: smoke tests + extends: + - .template_job_full_ci + parallel: + matrix: + - DV_SIMULATORS: ["veri-testharness,spike","vcs-testharness,spike","vcs-uvm,spike" ] variables: - GIT_STRATEGY: none - tags: [$TAGS_RUNNER] + DASHBOARD_JOB_TITLE: "Smoke test $DV_SIMULATORS" + DASHBOARD_JOB_DESCRIPTION: "Short tests to challenge most architectures with most testbenchs configurations" + DASHBOARD_SORT_INDEX: 0 + DASHBOARD_JOB_CATEGORY: "Basic" before_script: - after_script: - stage: build - script: - - echo $TAGS_RUNNER - - echo $RUN_CORE_CI - - echo $SETUP_CI_CORE_BRANCH - - echo $RUN_CORE_V_VERIF_CI - - echo $SETUP_CI_CVV_BRANCH - - echo $RUN_EXTERNAL_CI - - echo $SETUP_CI_EXTERNAL_BRANCH - - echo $CORE_V_VERIF_REPO - - echo $CORE_V_VERIF_BRANCH - - echo $CI_COMMIT_REF_NAME - - echo $CI_COMMIT_BRANCH - - -# core testbench downstream pipeline describes in '.gitlab-ci/cva6.yml' + 'cva6/cva6.yml' of 'setup-ci' repository -# If enabled by RUN_CORE_CI -cva6: - stage: test - trigger: - include: - - local: .gitlab-ci/cva6.yml - - project: '$CI_PROJECT_NAMESPACE/setup-ci' - ref: '$SETUP_CI_CORE_BRANCH' - file: 'cva6/cva6.yml' - strategy: depend - variables: - TAGS_RUNNER: $TAGS_RUNNER - SETUP_CI_BRANCH: $SETUP_CI_CORE_BRANCH - CI_PROJECT_NAMESPACE: $CI_PROJECT_NAMESPACE - DASHBOARD: "cva6" - WORKFLOW_EVENT: $CI_PIPELINE_SOURCE + - !reference [.verif_test, before_script] + script: + # In order to capture logs in case of test failure, the test script cannot fail. + - source verif/regress/smoke-tests.sh || true + # The list of files must NOT fail on various DV_SIMULATORS values, so use 'v*_sim' to match + # 'veri-testharness_sim', 'vcs-testharness_sim' and 'vcs-uvm_sim' (one of them always applies, + # at least until new RTL simulator configurations are added.) + - for i in verif/sim/*/v*_sim/*.log.iss ; do head -10000 $i > artifacts/logs/$(basename $i).head ; done + - python3 .gitlab-ci/scripts/report_simu.py verif/sim/logfile.log + artifacts: *artifacts + +pub_gen_smoke: + stage: smoke tests + extends: + - .template_job_full_ci + parallel: + matrix: + - DV_SIMULATORS: ["vcs-uvm,spike"] + variables: + DASHBOARD_JOB_TITLE: "Smoke Generated test $DV_SIMULATORS" + DASHBOARD_JOB_DESCRIPTION: "Short generated tests to challenge the CVA6-DV on STEP1 configuration" + DASHBOARD_SORT_INDEX: 0 + DASHBOARD_JOB_CATEGORY: "Basic" + before_script: + - !reference [.verif_test, before_script] + script: + # In order to capture logs in case of test failure, the test script cannot fail. + - source verif/regress/smoke-gen_tests.sh || true + # The list of files must NOT fail on various DV_SIMULATORS values, so use 'v*_sim' to match + # 'veri-testharness_sim', 'vcs-testharness_sim' and 'vcs-uvm_sim' (one of them always applies, + # at least until new RTL simulator configurations are added.) + - for i in verif/sim/*/v*_sim/*.log.iss ; do head -10000 $i > artifacts/logs/$(basename $i).head ; done + - python3 .gitlab-ci/scripts/report_simu.py verif/sim/logfile.log + artifacts: *artifacts + +pub_riscv_arch_test: + extends: + - .verif_test + - .template_job_short_ci + parallel: + matrix: + - DV_TARGET: [cv64a6_imafdc_sv39, cv32a60x] + variables: + DV_SIMULATORS: "veri-testharness,spike" + DASHBOARD_JOB_TITLE: "arch_test $DV_TARGET" + DASHBOARD_JOB_DESCRIPTION: "Compliance regression suite" + DASHBOARD_SORT_INDEX: 0 + DASHBOARD_JOB_CATEGORY: "Test suites" + script: + - source verif/regress/dv-riscv-arch-test.sh + - python3 .gitlab-ci/scripts/report_simu.py verif/sim/logfile.log + +csr_test: + extends: + - .verif_test + - .template_job_short_ci + parallel: + matrix: + - DV_TARGET: [cv32a60x] + variables: + DV_SIMULATORS: "veri-testharness,spike" + DASHBOARD_JOB_TITLE: "csr_test $DV_TARGET" + DASHBOARD_JOB_DESCRIPTION: "CSR regression suite" + DASHBOARD_SORT_INDEX: 0 + DASHBOARD_JOB_CATEGORY: "Test suites" + script: + - source verif/regress/dv-riscv-csr-access-test.sh + - python3 .gitlab-ci/scripts/report_simu.py verif/sim/logfile.log + +pub_hwconfig: + extends: + - .verif_test + - .template_job_short_ci + parallel: + matrix: + - DV_SIMULATORS: ["veri-testharness,spike"] + DV_HWCONFIG_OPTS: + - "--default_config=cv32a60x --isa=rv32imac --RenameEn=1" + variables: + DASHBOARD_JOB_TITLE: "HW config $DV_SIMULATORS $DV_HWCONFIG_OPTS" + DASHBOARD_JOB_DESCRIPTION: "Short tests to challenge target configurations" + DASHBOARD_SORT_INDEX: 1 + DASHBOARD_JOB_CATEGORY: "Basic" + script: + - source verif/regress/hwconfig_tests.sh + - python3 .gitlab-ci/scripts/report_pass.py + +pub_compliance: + extends: + - .verif_test + - .template_job_short_ci + parallel: + matrix: + - DV_TARGET: [cv64a6_imafdc_sv39, cv32a60x] + variables: + DV_SIMULATORS: "veri-testharness,spike" + DASHBOARD_JOB_TITLE: "Compliance $DV_TARGET" + DASHBOARD_JOB_DESCRIPTION: "Compliance regression suite" + DASHBOARD_SORT_INDEX: 2 + DASHBOARD_JOB_CATEGORY: "Test suites" + script: + - source verif/regress/dv-riscv-compliance.sh + - python3 .gitlab-ci/scripts/report_simu.py verif/sim/logfile.log + +pub_tests-v: + extends: + - .verif_test + - .template_job_short_ci + parallel: + matrix: + - DV_TARGET: [cv64a6_imafdc_sv39] + variables: + DV_SIMULATORS: "veri-testharness,spike" + DV_TESTLISTS: "../tests/testlist_riscv-tests-$DV_TARGET-v.yaml" + DASHBOARD_JOB_TITLE: "Riscv-test $DV_TARGET (virtual)" + DASHBOARD_JOB_DESCRIPTION: "Riscv-test regression suite (virtual)" + DASHBOARD_SORT_INDEX: 3 + DASHBOARD_JOB_CATEGORY: "Test suites" + script: + - source verif/regress/dv-riscv-tests.sh + - python3 .gitlab-ci/scripts/report_simu.py verif/sim/logfile.log + +pub_tests-p: + extends: + - .verif_test + - .template_job_short_ci + parallel: + matrix: + - DV_TARGET: [cv64a6_imafdc_sv39, cv32a60x] + variables: + DV_SIMULATORS: "veri-testharness,spike" + DV_TESTLISTS: "../tests/testlist_riscv-tests-$DV_TARGET-p.yaml" + DASHBOARD_JOB_TITLE: "Riscv-test $DV_TARGET (physical)" + DASHBOARD_JOB_DESCRIPTION: "Riscv-test regression suite (physical)" + DASHBOARD_SORT_INDEX: 4 + DASHBOARD_JOB_CATEGORY: "Test suites" + script: + - source verif/regress/dv-riscv-tests.sh + - python3 .gitlab-ci/scripts/report_simu.py verif/sim/logfile.log + +pub_synthesis_others: + timeout: 2 hours + extends: + - .verif_test + - .template_job_always_manual + parallel: + matrix: + - TARGET: [cv64a6_imafdc_sv39] + PERIOD: ["1.1"] + - TARGET: [cv32a60x] + PERIOD: ["0.95"] + variables: &synth_vars + INPUT_DELAY: "0.46" + OUTPUT_DELAY: "0.11" + DASHBOARD_JOB_TITLE: "ASIC Synthesis $TARGET" + DASHBOARD_JOB_DESCRIPTION: "Synthesis indicator with specific Techno" + DASHBOARD_SORT_INDEX: 5 + DASHBOARD_JOB_CATEGORY: "Synthesis" + script: &synth_script + #ack trick to manage float gitlab-ci variables that seems to support only string or integer + - echo $SYNTH_PERIOD + - echo $INPUT_DELAY + - echo $OUTPUT_DELAY + - echo $NAND2_AREA + - echo $FOUNDRY_PATH + - echo $PERIOD + - echo $TECH_NAME + - echo $TARGET + - source verif/regress/install-cva6.sh + - echo $SYN_DCSHELL_BASHRC; source $SYN_DCSHELL_BASHRC + - make -C pd/synth cva6_synth + - mv pd/synth/cva6_${TARGET}_synth_modified.v artifacts/cva6_${TARGET}_synth_modified.v + - python3 .gitlab-ci/scripts/report_synth.py pd/synth/cva6_${TARGET}/reports/$PERIOD/cva6_$(echo $TECH_NAME)_synth_area.rpt pd/synth/synthesis_batch.log rules: - - if: $RUN_CORE_CI == "true" - when: always - - when: never + - when: manual + allow_failure: true +pub_synthesis: + timeout: 2 hours + extends: + - .verif_test + - .template_job_always_manual + variables: + <<: *synth_vars + TARGET: cv32a6_embedded + PERIOD: "0.85" + script: *synth_script -# Please read .gitlab-ci/cva6.yml in core-v-verif repository -# core testbench downstream pipeline describes in '.gitlab-ci/core-v-verif-cva6.yml' + 'cva6/core-v-verif-cva6.yml' of 'setup-ci' repository -# If enabled by RUN_CORE_V_VERIF_CI -# core-v-verif trigger job (see previous core-v-verif-build job) -core-v-verif-build: - stage: build +pub_smoke-gate: + extends: + - .backend_test + - .template_job_always_manual + needs: + - pub_build_tools + - pub_synthesis variables: - GIT_STRATEGY: none + DASHBOARD_JOB_TITLE: "Smoke Gate $TARGET" + DASHBOARD_JOB_DESCRIPTION: "Simple test to check netlist from ASIC synthesis" + DASHBOARD_SORT_INDEX: 6 + DASHBOARD_JOB_CATEGORY: "Post Synthesis" + TARGET: cv32a6_embedded + script: + - mkdir -p tools + - mv artifacts/tools/spike tools + - echo $SYN_VCS_BASHRC; source $SYN_VCS_BASHRC + - echo $LIB_VERILOG + - echo $FOUNDRY_PATH + - echo $PERIOD + - echo $TECH_NAME + - source verif/regress/install-cva6.sh + - source verif/regress/install-riscv-dv.sh + - source verif/regress/install-riscv-tests.sh + - mv artifacts/cva6_${TARGET}_synth_modified.v pd/synth/cva6_${TARGET}_synth_modified.v + - cd verif/sim + - make vcs_clean_all + - python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv32a60x-p.yaml --test rv32ui-p-lw --iss_yaml cva6.yaml --target $TARGET --iss=spike,vcs-gate $DV_OPTS + - cd - + - python3 .gitlab-ci/scripts/report_simu.py verif/sim/logfile.log + +pub_coremark: + extends: + - .verif_test + - .template_job_full_ci + variables: + DASHBOARD_JOB_TITLE: "CoreMark" + DASHBOARD_JOB_DESCRIPTION: "Performance indicator" + DASHBOARD_SORT_INDEX: 5 + DASHBOARD_JOB_CATEGORY: "Performance" + script: + - bash verif/regress/coremark.sh --no-print + - python3 .gitlab-ci/scripts/report_benchmark.py --coremark verif/sim/out_*/veri-testharness_sim/core_main.log + +pub_dhrystone: + extends: + - .verif_test + - .template_job_full_ci + variables: + DASHBOARD_JOB_TITLE: "Dhrystone" + DASHBOARD_JOB_DESCRIPTION: "Performance indicator" + DASHBOARD_SORT_INDEX: 5 + DASHBOARD_JOB_CATEGORY: "Performance" + script: + - bash verif/regress/dhrystone.sh + - python3 .gitlab-ci/scripts/report_benchmark.py --dhrystone verif/sim/out_*/veri-testharness_sim/dhrystone_main.log + +pub_fpga-build: + timeout: 90 minutes + extends: + - .verif_test + - .template_job_short_ci + variables: + DASHBOARD_JOB_TITLE: "FPGA Build $TARGET" + DASHBOARD_JOB_DESCRIPTION: "Test of FPGA build flow" + DASHBOARD_SORT_INDEX: 9 + DASHBOARD_JOB_CATEGORY: "Synthesis" + TARGET: cv32a60x + script: + - source $VIVADO_SETUP + - source verif/regress/install-cva6.sh + - make fpga target=$TARGET + - mkdir -p artifacts/reports + - mv corev_apu/fpga/work-fpga/ariane_xilinx.bit artifacts/ariane_xilinx_$TARGET.bit + - python3 .gitlab-ci/scripts/report_fpga.py corev_apu/fpga/reports/ariane.utilization.rpt + +pub_generated_tests: tags: [$TAGS_RUNNER] + extends: + - .verif_test + variables: + DASHBOARD_SORT_INDEX: 11 + DASHBOARD_JOB_CATEGORY: "Code Coverage" + parallel: + matrix: + - list_num: 1 + DASHBOARD_JOB_TITLE: "Generated Random Arithmetic tests" + DASHBOARD_JOB_DESCRIPTION: "Generate Random Arithmetic tests using CVA6-DV" + - list_num: 2 + DASHBOARD_JOB_TITLE: "Generated Hazard Arithmetic tests" + DASHBOARD_JOB_DESCRIPTION: "Generate Hazard register (RAW) Arithmetic tests using CVA6-DV" + - list_num: 3 + DASHBOARD_JOB_TITLE: "Generated CSR tests" + DASHBOARD_JOB_DESCRIPTION: "Generate Random CSR tests using CVA6-DV" + - list_num: 4 + DASHBOARD_JOB_TITLE: "Generated MMU tests" + DASHBOARD_JOB_DESCRIPTION: "Generate Random MMU tests using CVA6-DV" + - list_num: 5 + DASHBOARD_JOB_TITLE: "Generated Random Load_store tests" + DASHBOARD_JOB_DESCRIPTION: "Generate Random Load_store tests using CVA6-DV" + - list_num: 6 + DASHBOARD_JOB_TITLE: "Generated Jump tests" + DASHBOARD_JOB_DESCRIPTION: "Generate Random Arithmetic Jump tests using CVA6-DV" script: - - echo $CORE_V_VERIF_REPO - - echo $CORE_V_VERIF_BRANCH - - '[[ -e ./core-v-verif ]] && rm -rf core-v-verif' - - git clone $CORE_V_VERIF_REPO -b $CORE_V_VERIF_BRANCH --depth=1 core-v-verif - - cd core-v-verif - - echo CORE_V_VERIF_HASH=$(git rev-parse origin/$CORE_V_VERIF_BRANCH) - - echo CORE_V_VERIF_HASH=$(git rev-parse origin/$CORE_V_VERIF_BRANCH) > ../.env - - cd .. - - mkdir -p artifacts/.gitlab-ci/core_v_verif - - mv core-v-verif/.gitlab-ci/cva6.yml artifacts/.gitlab-ci/core_v_verif/cva6.yml + - mkdir -p artifacts/coverage + - source verif/regress/dv-generated-tests.sh + - mv verif/sim/vcs_results/default/vcs.d/simv.vdb artifacts/coverage + - mv verif/sim/seedlist.yaml artifacts/coverage + - python3 .gitlab-ci/scripts/report_pass.py rules: - - if: '$RUN_CORE_V_VERIF_CI == "true"' - when: always - - when: never + - when: manual + allow_failure: true + timeout: 4h artifacts: - paths: - - artifacts/.gitlab-ci/core_v_verif/cva6.yml - reports: - dotenv: .env - - -# core-v-verif trigger job (see previous core-v-verif-build job) -core-v-verif: - stage: test - trigger: - include: - - artifact: artifacts/.gitlab-ci/core_v_verif/cva6.yml - job: core-v-verif-build - - project: '$CI_PROJECT_NAMESPACE/setup-ci' - ref: '$SETUP_CI_CVV_BRANCH' - file: 'cva6/core-v-verif-cva6.yml' - - local: .gitlab-ci/core-v-verif-cva6.yml - strategy: depend - variables: - TAGS_RUNNER: $TAGS_RUNNER - SCOPE_CVV: "false" - CORE_V_VERIF_HASH: $CORE_V_VERIF_HASH - DASHBOARD: "cva6" - WORKFLOW_EVENT: $CI_PIPELINE_SOURCE + expire_in: 3 week + +pub_generated_xif_tests: + tags: [$TAGS_RUNNER] + extends: + - .verif_test + variables: + DASHBOARD_SORT_INDEX: 12 + DASHBOARD_JOB_CATEGORY: "Code Coverage" + parallel: + matrix: + - list_num: 1 + DASHBOARD_JOB_TITLE: "Generated Random xif tests" + DASHBOARD_JOB_DESCRIPTION: "Generate Random tests for cvxif using CVA6-DV" + script: + - mkdir -p artifacts/coverage + - source verif/regress/dv-generated-xif-tests.sh + - mv verif/sim/vcs_results/default/vcs.d/simv.vdb artifacts/coverage + - mv verif/sim/seedlist.yaml artifacts/coverage + - python3 .gitlab-ci/scripts/report_pass.py rules: - - if: '$RUN_CORE_V_VERIF_CI == "true"' - when: always - - when: never + - when: manual + allow_failure: true + timeout: 4h + artifacts: + expire_in: 3 week +pub_directed_isacov-tests: + tags: [$TAGS_RUNNER] + extends: + - .verif_test + variables: + DASHBOARD_SORT_INDEX: 13 + DASHBOARD_JOB_CATEGORY: "Functional Coverage" + parallel: + matrix: + - list_num: 0 + DASHBOARD_JOB_TITLE: "Directed tests" + DASHBOARD_JOB_DESCRIPTION: "Execute directed tests to improve functional coverage of ISA" + script: + - mkdir -p artifacts/coverage + - source verif/regress/dv-generated-tests.sh + - mv verif/sim/vcs_results/default/vcs.d/simv.vdb artifacts/coverage + - python3 .gitlab-ci/scripts/report_pass.py + rules: + - when: manual + allow_failure: true + timeout: 4h + artifacts: + expire_in: 3 week -# Use this entry point to run a pipeline from another repository (hosted on the same gitlab server) -# If enabled by RUN_SETUP_CI, additionnal variables may be necessary and should be declared by project maintainers. -external: - trigger: - include: - - project: '$CI_PROJECT_NAMESPACE/setup-ci' - ref: '$SETUP_CI_EXTERNAL_BRANCH' - file: 'common/cva6.yml' - strategy: depend +pub_directed_xif-tests: + tags: [$TAGS_RUNNER] + extends: + - .verif_test variables: - TAGS_RUNNER: $TAGS_RUNNER + DASHBOARD_SORT_INDEX: 15 + DASHBOARD_JOB_CATEGORY: "Functional Coverage" + parallel: + matrix: + - list_num: 0 + DASHBOARD_JOB_TITLE: "Directed tests" + DASHBOARD_JOB_DESCRIPTION: "Execute directed tests to improve functional coverage of cvxif" + script: + - mkdir -p artifacts/coverage + - source verif/regress/dv-generated-xif-tests.sh + - mv verif/sim/vcs_results/default/vcs.d/simv.vdb artifacts/coverage + - python3 .gitlab-ci/scripts/report_pass.py rules: - - if: '$RUN_EXTERNAL_CI == "true"' - when: always + - when: manual + allow_failure: true + timeout: 4h + artifacts: + expire_in: 3 week + +pub_fpga-boot: + tags: [fpga,shell] + extends: + - .backend_test + needs: + - pub_build_tools + - pub_fpga-build + variables: + VERILATOR_INSTALL_DIR: "NO" # Skip install and checks of verilator + SPIKE_ROOT: "NO" # Skip install and checks of spike + DASHBOARD_JOB_TITLE: "FPGA Linux32 Boot " + DASHBOARD_JOB_DESCRIPTION: "Test of Linux 32 bits boot on FPGA Genesys2" + DASHBOARD_SORT_INDEX: 10 + DASHBOARD_JOB_CATEGORY: "Synthesis" + script: + - source verif/regress/install-cva6.sh + - source $VIVADO2022_SETUP + - mkdir -p corev_apu/fpga/work-fpga + - mv artifacts/ariane_xilinx_cv32a60x.bit corev_apu/fpga/work-fpga/ariane_xilinx.bit + - cd corev_apu/fpga/scripts + - source check_fpga_boot.sh + - cd - + - python3 .gitlab-ci/scripts/report_fpga_boot.py corev_apu/fpga/scripts/fpga_boot.rpt + +code_coverage-report: + tags: [$TAGS_RUNNER] + extends: + - .backend_test + needs: + - pub_generated_tests + - pub_directed_isacov-tests + - pub_generated_xif_tests + - pub_directed_xif-tests + variables: + DASHBOARD_JOB_TITLE: "Report merge coverage" + DASHBOARD_JOB_DESCRIPTION: "Report merge coverage of generated tests" + DASHBOARD_SORT_INDEX: 14 + DASHBOARD_JOB_CATEGORY: "Code Coverage" + script: + - echo $SYN_VCS_BASHRC; source $SYN_VCS_BASHRC + - mkdir -p artifacts/cov_reports/ + - mkdir -p verif/sim/vcs_results/default/vcs.d + - mv artifacts/coverage/simv.vdb verif/sim/vcs_results/default/vcs.d/ + - mv artifacts/coverage/seedlist.yaml verif/sim/seedlist.yaml + - make -C verif/sim generate_cov_dash + - mv verif/sim/urgReport artifacts/cov_reports/ + - python3 .gitlab-ci/scripts/report_pass.py + rules: + - when: on_success + artifacts: + expire_in: 3 week + +check gitlab jobs status: + stage: find failures + tags: [$TAGS_RUNNER] + rules: + - if: '$DASHBOARD_URL' + when: on_failure - when: never + variables: + DASHBOARD_JOB_TITLE: "Environment check" + DASHBOARD_JOB_DESCRIPTION: "Detect environment issues" + DASHBOARD_SORT_INDEX: 0 + DASHBOARD_JOB_CATEGORY: "Environment" + script: + - rm -rf artifacts/ + - mkdir -p artifacts/reports + - python3 .gitlab-ci/scripts/report_envfail.py + artifacts: *artifacts +merge reports: + stage: report + tags: [$TAGS_RUNNER] + rules: + - if: '$DASHBOARD_URL' + when: always + - when: never + script: + - mkdir -p artifacts/reports + - ls -al artifacts/reports + - python3 .gitlab-ci/scripts/merge_job_reports.py artifacts/reports pipeline_report_$CI_PIPELINE_ID.yml + artifacts: + when: always + paths: + - "artifacts/reports/pipeline_report_$CI_PIPELINE_ID.yml" diff --git a/.gitlab-ci/README.md b/.gitlab-ci/README.md new file mode 100644 index 0000000000..8f531175e2 --- /dev/null +++ b/.gitlab-ci/README.md @@ -0,0 +1,252 @@ + + +# GitLab CI for core-v-verif + CVA6 + +This document describes the different steps performed automatically when a branch is pushed to a repository. +It is not meant to be a complete description. +It is an entry point to help to understand the structure of the pipelines; to find the information your are looking for / the part of the CI you want to edit. +Please refer to the mentioned files for more details. + +Only the GitLab-related tasks are described here. + + +## Before the branch reaches GitLab + +CVA6 and core-v-verif repositories are mirrored into GitLab repositories owned by Thales, to perform regression tests on pull requests. + +> Note: in CVA6 regression tests are also run on the `master` branch, and in core-v-verif on the `cva6/dev` branch. + + +## Pipeline boot + +When a branch is pushed, the entry point of the CI is the `.gitlab-ci.yml` file at the repository root. + +> See [`core-v-verif/.gitlab-ci.yml`] and [`cva6/.gitlab-ci.yml`] + +[`core-v-verif/.gitlab-ci.yml`]: https://github.com/openhwgroup/core-v-verif/blob/cva6/dev/.gitlab-ci.yml +[`cva6/.gitlab-ci.yml`]: https://github.com/openhwgroup/cva6/blob/master/.gitlab-ci.yml + +Both source files from a `setup-ci` project (to locate tools etc.), define workflow rules and perform a small environment check. + +All pipelines need both CVA6 and core-v-verif to run tests. +By default the branches used are: + +- The one from the PR +- The main branch from the other repository. + The main branch is defined in `setup-ci` (`master` for CVA6 and `cva6/dev` for core-v-verif). + +However, the entry points also detect the `cvvdev/*` pattern in the branch name to run CVA6 and core-v-verif pipelines on branches with the same name. +It is useful to consistently test PRs impacting both repositories. + +In the CVA6 pipeline: + +1. The `core-v-verif-build` job gets the current commit hash of core-v-verif to set it as an environment variable. + It gets the list of tests to run [`core-v-verif/.gitlab-ci/cva6.yml`] (see next steps). +2. The `core-v-verif` job triggers a child pipeline using: + - [`core-v-verif/.gitlab-ci/cva6.yml`] fetched by `core-v-verif-build` + - [`cva6/.gitlab-ci/core-v-verif-cva6.yml`] which defines a `before_script` and an `after_script` to `cd` the core-v-verif repository with the hash defined by `core-v-verif-build` + +[`core-v-verif/.gitlab-ci/cva6.yml`]: https://github.com/openhwgroup/core-v-verif/blob/cva6/dev/.gitlab-ci/cva6.yml +[`cva6/.gitlab-ci/core-v-verif-cva6.yml`]: https://github.com/openhwgroup/cva6/blob/master/.gitlab-ci/core-v-verif-cva6.yml + +In core-v-verif pipelines, the `cva6` job triggers a child pipeline using: + +- [`core-v-verif/.gitlab-ci/cva6.yml`] (the list of tests) +- [`core-v-verif/.gitlab-ci/core-v-verif-cva6.yml`] (global `before_script` and `after_script`). + +[`core-v-verif/.gitlab-ci/core-v-verif-cva6.yml`]: https://github.com/openhwgroup/core-v-verif/blob/cva6/dev/.gitlab-ci/core-v-verif-cva6.yml + + +## Running the tests + +Thanks to the previous step, in pipelines from both CVA6 and core-v-verif, the current working directory is core-v-verif, with CVA6 checked out in `core-v-cores/cva6`. + +The tests are described in [`core-v-verif/.gitlab-ci/cva6.yml`]. + +Stages are defined as below (order matters): + +- `init env`: only contains `pub_initjob`, which sets a hash for CVA6 as an environment variable, so that it is the same one for all jobs of this pipeline. + It is only run in core-v-verif pipelines as CVA6 pipelines already have the CVA6 commit hash of the pipeline! +- `build tools`: `pub_build_tools` build Spike and `pub_check_env` prints some environment variable for debugging. +- `smoke tests`: `pub_smoke` runs smoke tests. +- `verif tests`: many jobs runs different verif tests. + The template for them is described later in this document. +- `backend tests`: jobs which use results of `verif tests`, often synthesis results. +- `report`: `merge reports` merges all reports into a single yaml. + + +### Adding a verif test + +A simple test looks like this: + +```yml +pub_: + extends: + - .verif_test + - .template_job_short_ci + variables: + DASHBOARD_JOB_TITLE: "" + DASHBOARD_JOB_DESCRIPTION: "<description for dashboard>" + DASHBOARD_SORT_INDEX: <index to sort jobs in dashboard> + DASHBOARD_JOB_CATEGORY: "<job category for dashboard>" + script: + - source cva6/regress/<my-script>.sh + - python3 .gitlab-ci/scripts/report_<kind>.py <args...> +``` + +- `.verif_test` tells that: + - The job goes in `verif tests` stage + - Before running the script part, additionally to the global `before_script`: + - Spike is got from `pub_build_tools` + - Artifacts are cleaned, `artifacts/reports` and `artifacts/logs` are created + - A "failure" report is created by default (in case the script exists early) + - `$SYN_VCS_BASHRC` is sourced + - All the contents of the `artifacts/` folder will be considered as artifacts (even if the job fails) +- `.template_job_short_ci` tells in which pipeline mode the job should run +- `variables` defines environment variables. + The 4 above are needed to generate the report for the dashboard. +- `script` defines the script to run: + 1. Run the test, for instance sourcing a script in `cva6/regress/` + 2. Generate a report running a script from `.gitlab-ci/scripts/reports_*.py` + +> Notes: +> +> You can add more environment variables such as: +> +> ```yml +> variables: +> DV_SIMULATORS: "veri-testharness,spike" +> DV_TESTLISTS: "../tests/testlist_riscv-tests-$DV_TARGET-p.yaml" +> ``` +> +> You can also have several jobs running in parallel with variables taking different values: +> +> ```yml +> parallel: +> matrix: +> - DV_TARGET: [cv64a6_imafdc_sv39, cv32a60x] +> ``` + + +### Adding a backend test + +```yml +pub_<name>: + needs: + - *initjob + - pub_<other_job> + - <...> + extends: + - .backend_test + - .template_job_always_manual + variables: + <same as for verif tests> + script: + - <mv spike from artifacts if you need it> + - <your script> + - python3 .gitlab-ci/scripts/report_<kind>.py <args...> +``` + +Backend tests are like verif tests, differences are: + +- `needs` list is needed to specify in which conditions the test is run (with `.template_job_*`). + It contains: + - `*initjob` to be sure the correct CVA6 commit is used. + Without a `needs` list, all jobs from all previous stages are considered as needed. + However, when a `needs` list is declared, all useful dependencies must be specified by hand, which is more complex. + - `pub_build_tools` if you need spike (don't forget to `mv` it from the artifacts!) + - The jobs you need artifacts from +- `.backend_test` indicates that: + - The job goes in `backend tests` stage + - It performs the same steps than `.backend_test`, except that: + - it does not source VCS (so you have to do it if you need it) + - it does not move spike (so you have to do it if you need it) + + +## Generating a report + +You might want to use `.gitlab-ci/scripts/report_simu.py`. + +If it does not suit your needs, below are snippets to help you write a report generator using our python library. + +```python +import report_builder as rb + +# Create metrics +metric = rb.TableMetric('Metric name') +metric.add_value('colomn 1', 'colomn 2', 'etc') + +# Gather them into a report +report = rb.Report('report label') +report.add_metric(metric) + +# Create the report file in the artifacts +report.dump() +``` + +There are 3 kinds of metric: + +```python +# A simple table +metric = rb.TableMetric('Metric name, actually not displayed yet') +metric.add_value('colomn 1', 'colomn 2', 'etc') + +# A table with a pass/fail label on each line +metric = rb.TableStatusMetric('Metric name, actually not displayed yet') +metric.add_pass('colomn 1', 'colomn 2', 'etc') +metric.add_fail('colomn 1', 'colomn 2', 'etc') + +# A log +metric = rb.LogMetric('Metric name, actually not displayed yet') +metric.add_value("one line (no need to add a backslash n)") +metric.values += ["one line (no need to add a backslash n)"] # same as above +metric.values = ["line1", "line2", "etc"] # also works + +# You can fail a metric of any kind at any moment +metric.fail() +``` + +Failures are propagated: + +- one fail in a `TableStatusMetric` fails the whole metric +- one failed metric fails the whole report +- one failed report fails the whole pipeline report + + +## Dashboard + +The `merge reports` job merges the report from all jobs of the pipeline into a single file. +It pushes this file to a repository. +This repository has a CI which produces HTML dashboard pages from the latest files. +These HTML pages are published on <https://riscv-ci.pages.thales-invia.fr/dashboard/> + +- Main pages [`dashboard_cva6_0.html`] and [`dashboard_core-v-verif_0.html`] gather results from all processed pipelines. +- Each page `dashboard_<project>_<PR id>.html` gathers results from all pipelines of one PR. + +[`dashboard_cva6_0.html`]: https://riscv-ci.pages.thales-invia.fr/dashboard/dashboard_cva6_0.html +[`dashboard_core-v-verif_0.html`]: https://riscv-ci.pages.thales-invia.fr/dashboard/dashboard_core-v-verif_0.html + + +## PR comment + +The `merge reports` job gets the list of open PRs. +It compares the name of the current branch with the name of each PR branch to find the PR. +If a PR matches, it triggers the GitHub workflow `dashboard-done.yml` in this repository, providing the PR number and the success/fail status. + +> See [`core-v-verif/.github/workflows/dashboard-done.yml`] and [`cva6/.github/workflows/dashboard-done.yml`] + +[`core-v-verif/.github/workflows/dashboard-done.yml`]: https://github.com/openhwgroup/core-v-verif/blob/cva6/dev/.github/workflows/dashboard-done.yml +[`cva6/.github/workflows/dashboard-done.yml`]: https://github.com/openhwgroup/cva6/blob/master/.github/workflows/dashboard-done.yml + +This GitHub workflow creates a comment in the PR with the success/fail status and a link to the dashboard page. + +However, the dashboard page may not be available right at this moment, as page generation, performed later, takes time. diff --git a/.gitlab-ci/core-v-verif-cva6.yml b/.gitlab-ci/core-v-verif-cva6.yml deleted file mode 100644 index 4df7110f7d..0000000000 --- a/.gitlab-ci/core-v-verif-cva6.yml +++ /dev/null @@ -1,19 +0,0 @@ -before_script: - - '[[ -e ./core-v-verif ]] && rm -rf core-v-verif' - - mkdir core-v-verif - - cd core-v-verif - - echo $CORE_V_VERIF_REPO - - echo $CORE_V_VERIF_HASH - - git init - - git remote add origin $CORE_V_VERIF_REPO - - git fetch --depth=1 origin $CORE_V_VERIF_HASH - - git reset --hard $CORE_V_VERIF_HASH - - git submodule update --init --recursive --depth=1 - - cd .. - - ln -rs ./ core-v-verif/core-v-cores/cva6 - - '[[ -e ./artifacts ]] && mv ./artifacts ./core-v-verif/artifacts' - - cd core-v-verif - -after_script: - - '[[ -e ./core-v-verif/artifacts ]] && mv ./core-v-verif/artifacts ./artifacts' - - cd .. diff --git a/.gitlab-ci/cva6.yml b/.gitlab-ci/cva6.yml deleted file mode 100644 index dbe021d095..0000000000 --- a/.gitlab-ci/cva6.yml +++ /dev/null @@ -1,152 +0,0 @@ - -before_script: - # paths to local or network installations (the riscv toolchain and - # verilator are not built in the ci job as in travis) - - export QUESTASIM_HOME=/usr/pack/modelsim-10.6b-kgf/questasim/ - - export QUESTASIM_VERSION=-10.6b - - export QUESTASIM_FLAGS=-noautoldlibpath - - export CXX=g++-7.2.0 CC=gcc-7.2.0 - - export RISCV=/scratch2/gitlabci/riscv_install - - export VERILATOR_ROOT=/scratch2/gitlabci/verilator-4.014 - # setup dependent paths - - export PATH=${RISCV}/bin:$VERILATOR_ROOT/bin:${PATH} - - export LIBRARY_PATH=$RISCV/lib - - export LD_LIBRARY_PATH=$RISCV/lib:/usr/pack/gcc-7.2.0-af/linux-x64/lib64/ - - export C_INCLUDE_PATH=$RISCV/include:$VERILATOR_ROOT/include:/usr/pack/gcc-7.2.0-af/linux-x64/include - - export CPLUS_INCLUDE_PATH=$RISCV/include:$VERILATOR_ROOT/include:/usr/pack/gcc-7.2.0-af/linux-x64/include - # number of parallel jobs to use for make commands and simulation - - export NUM_JOBS=4 - - which java - - java -version - - which git - - git --version - - ci/make-tmp.sh - - git submodule init - - git submodule update --recursive - -variables: - GIT_SUBMODULE_STRATEGY: recursive - -stages: - - build - - write-back - - write-through - -################################### -# prepare -build: - stage: build - script: - - ci/build-riscv-tests.sh - - ci/get-torture.sh - - make clean - # this currently does not work with the current runner version... - #- make torture-gen - artifacts: - paths: - - tmp - -################################### -# tests with write-back cache system - -# rv64ui-p-* and rv64ui-v-* tests -asm-quest: - stage: write-back - script: - - make -j${NUM_JOBS} run-asm-tests batch-mode=1 - dependencies: - - build - -amo-quest: - stage: write-back - script: - - make -j${NUM_JOBS} run-amo-tests batch-mode=1 - dependencies: - - build - -# floating point -fp-quest: - stage: write-back - script: - - make -j${NUM_JOBS} run-fp-tests batch-mode=1 - dependencies: - - build - -bench-quest: - stage: write-back - script: - - make -j${NUM_JOBS} run-benchmarks batch-mode=1 - dependencies: - - build - -# rv64ui-p-* tests -asm1-ver: - stage: write-back - script: - - make -j${NUM_JOBS} run-asm-tests1-verilator - dependencies: - - build - -# rv64ui-v-* tests -asm2-ver: - stage: write-back - script: - - make -j${NUM_JOBS} run-asm-tests2-verilator - dependencies: - - build - -# rv64um-*-* tests -mul-ver: - stage: write-back - script: - - make -j${NUM_JOBS} run-mul-verilator - dependencies: - - build - -# atomics -amo-ver: - stage: write-back - script: - - make -j${NUM_JOBS} run-amo-verilator - dependencies: - - build - -# floating point -fp-ver: - stage: write-back - script: - - make -j${NUM_JOBS} run-fp-verilator - dependencies: - - build - -bench-ver: - stage: write-back - script: - - make -j${NUM_JOBS} run-benchmarks-verilator - dependencies: - - build - -bench-ver: - stage: write-back - script: - - make -j${NUM_JOBS} run-benchmarks-verilator - dependencies: - - build - -# torture: -# stage: write-back -# script: -# - make torture-rtest batch-mode=1 -# - make torture-rtest-verilator -# dependencies: -# - build - -serdiv-quest: - stage: write-back - script: - - cd tb/tb_serdiv/ - - make simc - - "grep 'CI: PASSED' summary.rep" - dependencies: - - build - diff --git a/.gitlab-ci/scripts/github_integration.py b/.gitlab-ci/scripts/github_integration.py new file mode 100644 index 0000000000..c49c5b7983 --- /dev/null +++ b/.gitlab-ci/scripts/github_integration.py @@ -0,0 +1,63 @@ +""" +This module makes it possible to trigger GitHub workflows. +""" + +from os import environ as env +import requests + +def api_url(owner, repo): + "Build API url for a given repository" + return f"https://api.github.com/repos/{owner}/{repo}" + +def pulls(owner, repo): + "Get (public) pull requests from a given repository" + url = api_url(owner, repo) + '/pulls' + headers = {} + if 'GH_TOKEN' in env: + headers["Authorization"] = f"Token {env['GH_TOKEN']}" + response = requests.get(url, headers=headers) + assert response.status_code == 200 + return response.json() + +class Workflow: + "GitHub Workflow that can be triggered on a dispatch event" + def __init__(self, owner, repo, workflow_id, ref): + dispatches = f"/actions/workflows/{workflow_id}/dispatches" + self.url = api_url(owner, repo) + dispatches + self.ref = ref + + def _trigger(self, inputs): + "Trigger the workflow" + data = { + 'ref': self.ref, + 'inputs': inputs, + } + token = env['GH_TOKEN'] + headers = { + 'Accept': 'application/vnd.github+json', + 'Authorization': f"Bearer {token}", + 'X-GitHub-Api-Version': '2022-11-28', + } + return requests.post(url=self.url, json=data, headers=headers) + +class DashboardDone(Workflow): + "`dashboard-done.yml` GitHub workflow" + def __init__(self, owner, repo, ref): + workflow_id = 'dashboard-done.yml' + Workflow.__init__(self, owner, repo, workflow_id, ref) + + def send(self, pr, success): + "Send success or failure message" + inputs = { + 'pr_number': str(pr), + 'success': success, + } + return self._trigger(inputs) + + def send_success(self, pr): + "Send message stating that job is successful" + return self.send(pr, True) + + def send_failure(self, pr): + "Send message stating that job is failed" + return self.send(pr, False) diff --git a/.gitlab-ci/scripts/merge_job_reports.py b/.gitlab-ci/scripts/merge_job_reports.py new file mode 100644 index 0000000000..e6afdf686b --- /dev/null +++ b/.gitlab-ci/scripts/merge_job_reports.py @@ -0,0 +1,154 @@ +# Copyright 2022 Thales Silicon Security +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Original Author: Yannick Casamatta (yannick.casamatta@thalesgroup.com) +from yaml import safe_load +import os +import re +import pprint +import yaml +import datetime +import sys +import subprocess +import github_integration as gh + +# arguments: inputdir outputfile + +cwd = os.getcwd() + +dashboard_url = os.environ['DASHBOARD_URL'] +git_email = os.environ['DASHBOARD_USER_EMAIL'] +git_name = os.environ['DASHBOARD_USER_NAME'] + +pipeline_creation_timestamp = int(datetime.datetime.strptime(os.environ['CI_PIPELINE_CREATED_AT'], '%Y-%m-%dT%H:%M:%S%z').timestamp()) +pipeline_end_timestamp = int(datetime.datetime.now().timestamp()) +pipeline_duration = pipeline_end_timestamp - pipeline_creation_timestamp + +try: + workflow_type = os.environ['WORKFLOW_TYPE'].strip('\'\"') +except KeyError: + workflow_type = "gitlab" + +workflow_action = os.environ['WORKFLOW_EVENT'].strip('\'\"') + +if workflow_type == 'github': # (from wrapper) + + workflow_uid = os.environ['WORKFLOW_RUN_ID'].strip('\'\"') + workflow_repo_owner = os.environ['WORKFLOW_REPO_OWNER'].strip('\'\"') + workflow_repo = os.environ['WORKFLOW_REPO'].strip('\'\"') # cvv or cva6 + workflow_commit_subject = os.environ['WORKFLOW_COMMIT_MESSAGE'].strip('\'\"') + workflow_commit_author = os.environ['WORKFLOW_COMMIT_AUTHOR'].strip('\'\"') + cvv_branch = os.environ['CORE_V_VERIF_BRANCH'].strip('\'\"') + cvv_sha = os.environ['CORE_V_VERIF_HASH'].strip('\'\"') + cva6_branch = os.environ['CVA6_BRANCH'].strip('\'\"') + cva6_sha = os.environ['CVA6_HASH'].strip('\'\"') +else: # gitlab + workflow_uid = os.environ['CI_PIPELINE_ID'].strip('\'\"') + workflow_repo = 'cva6' + cvv_branch = 'none' + cvv_sha = '0000000' + cva6_branch = os.environ['CI_COMMIT_REF_NAME'].strip('\'\"') + cva6_sha = os.environ['CI_COMMIT_SHA'].strip('\'\"') + workflow_commit_subject = os.environ['CI_COMMIT_MESSAGE'].strip('\'\"') + workflow_commit_author = os.environ['CI_COMMIT_AUTHOR'].strip('\'\"') + +if len(workflow_commit_subject) > 60: + title = workflow_commit_subject[0:60] + '...' +else : + title = workflow_commit_subject +# limit injection through commit message, could be improved! +title = re.sub('[<>\n]*', '', title) + +if workflow_repo == "cva6": + workflow_commit_ref_name = cva6_branch + workflow_commit_sha = cva6_sha +else: # workflow_repo == "cvv": + workflow_commit_ref_name = cvv_branch + workflow_commit_sha = cvv_sha + + +pipeline = { + 'token': 'YC' + str(pipeline_creation_timestamp).replace('.', ''), + 'pipeline_url': os.environ["CI_PIPELINE_URL"], + 'timestamp': pipeline_creation_timestamp, + 'runtime': pipeline_duration, + 'workflow_action': workflow_action, + 'workflow_uid': workflow_uid, + 'workflow_repo': workflow_repo, + 'title': title, + 'description': "", + 'ref_name': workflow_commit_ref_name, + 'author': workflow_commit_author, + 'sha': workflow_commit_sha, + 'env': { + 'cva6': { + 'sha': cva6_sha, + 'branch': cva6_branch + }, + 'core-v-verif': { + 'sha': cvv_sha, + 'branch': cvv_branch + } + }, + 'status': "pass", # overridden when jobs are loaded + 'label': "PASS", # overridden when jobs are loaded + 'jobs': [] +} + +success = True +dir_list = os.listdir(sys.argv[1]) +for f in dir_list: + with open(sys.argv[1] + "/" + f, 'r') as job_report: + report = safe_load(job_report) + pipeline["jobs"].append(report) + if report['status'] != 'pass': + success = False + pipeline["status"] = 'fail' + pipeline["label"] = 'FAIL' + +pprint.pprint(pipeline) + +filename = re.sub('[^\w\.]', '', sys.argv[2]) +print(filename) + +with open(f'{sys.argv[1]}/{filename}', 'w+') as f: + yaml.dump(pipeline, f) + +try: + print(subprocess.check_output(f''' +rm -r .gitlab-ci/dashboard_tmp || echo "nothing to do" +git clone {dashboard_url} .gitlab-ci/dashboard_tmp +mkdir -p .gitlab-ci/dashboard_tmp/pipelines_{workflow_repo} +ls -al {sys.argv[1]} +cp {sys.argv[1]}/{filename} .gitlab-ci/dashboard_tmp/pipelines_{workflow_repo}/ +cd .gitlab-ci/dashboard_tmp +git config user.email {git_email} +git config user.name {git_name} +git add pipelines_{workflow_repo}/{filename} +git commit -m "{workflow_repo}: {title.replace('"',"'")}" || echo "commit fail" +git push +cd - +''', shell=True)) +except subprocess.CalledProcessError as e: + print(f"Error: {e.output}") + +def find_pr(branch, prs): + match = re.search(r'(.*)_PR_([a-zA-Z0-9](?:[a-zA-Z0-9]|[-_](?=[a-zA-Z0-9])){0,38})', branch) + if match: + label = f'{match.group(2)}:{match.group(1)}' + for pr in prs: + if label == pr['head']['label']: + return pr + return None + +pulls = gh.pulls('openhwgroup', workflow_repo) +pr = find_pr(workflow_commit_ref_name, pulls) +if pr is not None: + ref_branch = pr['base']['ref'] + wf = gh.DashboardDone('openhwgroup', workflow_repo, ref_branch) + response = wf.send(pr['number'], success) + print(response.text) diff --git a/.gitlab-ci/scripts/report_benchmark.py b/.gitlab-ci/scripts/report_benchmark.py new file mode 100644 index 0000000000..f84f469421 --- /dev/null +++ b/.gitlab-ci/scripts/report_benchmark.py @@ -0,0 +1,65 @@ +# Copyright 2022 Thales Silicon Security +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Original Author: Côme Allart + +import sys +import report_builder as rb + +path = None +mode = None +iterations = None + +# Keep it up-to-date with compiler version and core performance improvements +# Will fail if the number of cycles is different from this one +valid_cycles = { + 'dhrystone': 217900, + 'coremark': 670777, +} + +for arg in sys.argv[1:]: + if arg == '--dhrystone': + mode = 'dhrystone' + iterations = 500 + elif arg == '--coremark': + mode = 'coremark' + # Too few iterations to consider a score + else: + path = arg + +# We do not want to have a report without a check +assert mode is not None + +with open(path, 'r') as f: + log = [l.strip() for l in f.readlines()] + +stopwatch = [] +for index, line in enumerate(log): + if line.split()[-1] == 'mcycle': + stopwatch.append(int(log[index + 1].split()[-1], 16)) +# There might be > 2 matches, we use the two at the center +N = len(stopwatch) +assert N % 2 == 0 +cycles = stopwatch[N//2] - stopwatch[N//2-1] + +score_metric = rb.TableMetric('Performance results') +score_metric.add_value('cycles', cycles) + +if iterations is not None: + ipmhz = iterations * 1000000 / cycles + if mode == 'dhrystone': + score_metric.add_value('Dhrystone/MHz', ipmhz) + score_metric.add_value('DMIPS/MHz', ipmhz / 1757) + +diff = cycles - valid_cycles[mode] +if diff != 0: + score_metric.fail() + score_metric.add_value('Cycles diff', diff) + +report = rb.Report(f'{cycles//1000} kCycles') +report.add_metric(score_metric) +report.dump() diff --git a/.gitlab-ci/scripts/report_builder.py b/.gitlab-ci/scripts/report_builder.py new file mode 100644 index 0000000000..a34c8b265c --- /dev/null +++ b/.gitlab-ci/scripts/report_builder.py @@ -0,0 +1,161 @@ +# Copyright 2022 Thales Silicon Security +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Original Author: Côme Allart + +""" +Helpers to build CI reports +""" + +import os +import re +from datetime import datetime as dt +import yaml + +class Metric: + "A metric is a part of the body of the report" + + def __init__(self, name): + self.name = name + self.sort_index = None + self.failed = False + self.values = [] + + def to_doc(self): + "Transform to a dictionary" + return { + 'display_name': self.name, + 'sort_index': self.sort_index, + 'type': self._t(), + 'status': "fail" if self.failed else "pass", + 'value': self._values_to_doc(), + } + + def fail(self): + "Mark metric as failed" + self.failed = True + + def _values_to_doc(self): + raise NotImplementedError() + + def _t(self): + raise NotImplementedError() + +class LogMetric(Metric): + "Log lines" + + def add_value(self, line): + "Insert a line in the log" + self.values.append(line) + + def _values_to_doc(self): + return self.values + + def _t(self): + return 'log' + +class TableMetric(Metric): + "Table" + + def add_value(self, *col): + "Insert a line in the table" + self.values.append(list(col)) + + def _values_to_doc(self): + return [{'col': v} for v in self.values] + + def _t(self): + return 'table' + +class TableStatusMetric(Metric): + "Table with status label for each line" + + def add_pass_label(self, label, *col): + "Insert a 'pass' line with given label in the table" + self._add_value('pass', label, *col) + + def add_fail_label(self, label, *col): + "Insert a 'fail' line with given label in the table" + self._add_value('fail', label, *col) + self.fail() + + def add_pass(self, *col): + "Insert a 'pass' line in the table" + self.add_pass_label("PASS", *col) + + def add_fail(self, *col): + "Insert a 'fail' line in the table" + self.add_fail_label("FAIL", *col) + + def _add_value(self, status, label, *col): + self.values.append((status, label, list(col))) + + def _values_to_doc(self): + return [{'status': s, 'label': l, 'col': c} for (s,l,c) in self.values] + + def _t(self): + return 'table_status' + +class Report: + "A report is the top level entity of the document" + + def __init__(self, label=None): + self.label = label + self.failed = False + self.metrics = [] + + def add_metric(self, *metric): + "Add one or more metric(s) to the report body" + for m in metric: + if m.sort_index is None: + if len(self.metrics) > 0: + m.sort_index = self.metrics[-1].sort_index + 1 + else: + m.sort_index = 1 + self.metrics.append(m) + if m.failed: + self.fail() + + def fail(self): + "Mark report as failed" + self.failed = True + + def to_doc(self): + "Transform to a dictionary" + assert len(self.metrics) > 0, "A report must have at least one metric" + start = os.environ['CI_JOB_STARTED_AT'] + start_fmt = '%Y-%m-%dT%H:%M:%S%z' + start = dt.strptime(start, start_fmt).timestamp() + pass_label = "FAIL" if self.failed else "PASS" + label = pass_label if self.label is None else self.label + return { + 'title': os.environ["DASHBOARD_JOB_TITLE"], + 'description': os.environ["DASHBOARD_JOB_DESCRIPTION"], + 'category': os.environ["DASHBOARD_JOB_CATEGORY"], + 'sort_index': os.environ["DASHBOARD_SORT_INDEX"], + 'job_id': os.environ["CI_JOB_ID"], + 'job_url': os.environ["CI_JOB_URL"], + 'job_stage_name': os.environ["CI_JOB_STAGE"], + 'job_started_at': int(start), + 'job_end_at': int(dt.now().timestamp()), + 'token': 'YC' + str(dt.now().timestamp()).replace('.', ''), + 'status': "fail" if self.failed else "pass", + 'metrics': [m.to_doc() for m in self.metrics], + 'label': label, + } + + def dump(self, path=None): + """ + Create report file + + By default the output path is build from $CI_JOB_NAME + """ + if path is None: + filename = re.sub(r'[^\w\.\\\/]', '_', os.environ["CI_JOB_NAME"]) + path = 'artifacts/reports/'+filename+'.yml' + with open(path, 'w') as f: + yaml.dump(self.to_doc(), f) diff --git a/.gitlab-ci/scripts/report_envfail.py b/.gitlab-ci/scripts/report_envfail.py new file mode 100644 index 0000000000..7049bcddc4 --- /dev/null +++ b/.gitlab-ci/scripts/report_envfail.py @@ -0,0 +1,17 @@ +# Copyright 2023 Thales Silicon Security +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Original Author: Côme ALLART - Thales + +import report_builder as rb + +metric = rb.TableStatusMetric('') +metric.add_fail('Environment failure detected. Some reports might be missing') + +report = rb.Report() +report.add_metric(metric) +report.dump() diff --git a/.gitlab-ci/scripts/report_fail.py b/.gitlab-ci/scripts/report_fail.py new file mode 100644 index 0000000000..a59a14c80c --- /dev/null +++ b/.gitlab-ci/scripts/report_fail.py @@ -0,0 +1,17 @@ +# Copyright 2022 Thales Silicon Security +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Original Author: Yannick Casamatta (yannick.casamatta@thalesgroup.com) + +import report_builder as rb + +metric = rb.TableStatusMetric('') +metric.add_fail('Job has failed before end of script') + +report = rb.Report() +report.add_metric(metric) +report.dump() diff --git a/.gitlab-ci/scripts/report_fpga.py b/.gitlab-ci/scripts/report_fpga.py new file mode 100644 index 0000000000..a1f48c7fa6 --- /dev/null +++ b/.gitlab-ci/scripts/report_fpga.py @@ -0,0 +1,51 @@ +# Copyright 2022 Thales Silicon Security +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Original Author: Guillaume Chauvon(guillaume.chauvon@thalesgroup.com) + +import re +import sys + +import report_builder as rb + +with open(str(sys.argv[1]), "r") as f: + log = f.read() + +pattern = re.compile( + "\|(?P<ind> +)(?P<Instance>[\w()\[\].]+) +\| +(?P<Module>[\w()\[\].]+) \| +(?P<TotalLUTs>\d+) \| +(?P<LogicLUTs>\d+) \| +(?P<LUTRAMs>\d+) \| +(?P<SRLs>\d+) \| +(?P<FFs>\d+) \| +(?P<RAMB36>\d+) \| +(?P<RAMB18>\d+) \| +(?P<DSP48Blocks>\d+) \|" +) + +data = [] +for line in pattern.finditer(log): + l = line.groupdict() + if l["Instance"] == "i_ariane_peripherals": + break + data.append(l) + +report = rb.Report() +metric = rb.TableMetric('Utilization Results') + +for i in data: + if (i["ind"]).count(" ") < 10: + if i["Instance"] == "ariane_xilinx": + total = int(i["TotalLUTs"]) // 1000 + report.label = f"{total} kLUTs" + metric.add_value( + i["Instance"], + i["Module"], + i["TotalLUTs"] + " TotalLUTs", + i["LogicLUTs"] + " LogicLUTs", + i["LUTRAMs"] + " LUTRAMs", + i["SRLs"] + " SRLs", + i["FFs"] + " FFs", + i["RAMB36"] + " RAMB36", + i["RAMB18"] + " RAMB18", + i["DSP48Blocks"] + " DSP48Blocks", + ) + +report.add_metric(metric) +report.dump() diff --git a/.gitlab-ci/scripts/report_fpga_boot.py b/.gitlab-ci/scripts/report_fpga_boot.py new file mode 100644 index 0000000000..aca42327a5 --- /dev/null +++ b/.gitlab-ci/scripts/report_fpga_boot.py @@ -0,0 +1,27 @@ +# Copyright 2022 Thales Silicon Security +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Original Author: Guillaume Chauvon(guillaume.chauvon@thalesgroup.com) + +import sys +import report_builder as rb + +with open(str(sys.argv[1]), "r") as f: + lastline = f.readlines()[-1] + +with open(str(sys.argv[1]), "r") as f: + log = f.read() + +metric = rb.TableStatusMetric('Linux boot log') +if not ("Linux buildroot" in lastline and "riscv" in lastline): + metric.add_fail(lastline) +else: + metric.add_pass(lastline) + +report = rb.Report() +report.add_metric(metric) +report.dump() diff --git a/.gitlab-ci/scripts/report_pass.py b/.gitlab-ci/scripts/report_pass.py new file mode 100644 index 0000000000..a458d0608a --- /dev/null +++ b/.gitlab-ci/scripts/report_pass.py @@ -0,0 +1,17 @@ +# Copyright 2022 Thales Silicon Security +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Original Author: Yannick Casamatta (yannick.casamatta@thalesgroup.com) + +import report_builder as rb + +metric = rb.TableStatusMetric('') +metric.add_pass('Job completed without error. No metric extraction is configured') + +report = rb.Report() +report.add_metric(metric) +report.dump() diff --git a/.gitlab-ci/scripts/report_simu.py b/.gitlab-ci/scripts/report_simu.py new file mode 100644 index 0000000000..620356a756 --- /dev/null +++ b/.gitlab-ci/scripts/report_simu.py @@ -0,0 +1,40 @@ +# Copyright 2022 Thales Silicon Security +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Original Author: Yannick Casamatta (yannick.casamatta@thalesgroup.com) + +import sys +import re +import report_builder as rb + +with open(str(sys.argv[1]), 'r') as f: + log = f.read() + +pattern = re.compile( + "^(?:\w{3}, \d{2} \w{3} \d{4} \d{2}:\d{2}:\d{2} INFO )?Compiling (.*) : .*(tests\S*)$[\s\S]*?^(?:\w{3}, \d{2} \w{3} \d{4} \d{2}:\d{2}:\d{2} INFO )?Found matching ISS: (\S*)$[\s\S]*?^(?:\w{3}, \d{2} \w{3} \d{4} \d{2}:\d{2}:\d{2} INFO )?ISA (\S*)$[\s\S]*?^(?:\w{3}, \d{2} \w{3} \d{4} \d{2}:\d{2}:\d{2} INFO )?\[(\w*)\]: (\d*) matched(?:, (\d*) mismatch)?$", + re.MULTILINE) +list_of_tests = pattern.findall(log) + +metric = rb.TableStatusMetric('') + +job_test_pass = 0 +job_test_total = 0 +for i in list_of_tests: + job_test_total += 1 + col = [i[3], i[2], i[0], i[1]] # isa testbench testsuite test + if i[4] == "PASSED": + metric.add_pass(*col) + job_test_pass += 1 + else: + metric.add_fail(*col) + +if job_test_total == 0: + metric.fail() + +report = rb.Report(f'{job_test_pass}/{job_test_total}') +report.add_metric(metric) +report.dump() diff --git a/.gitlab-ci/scripts/report_synth.py b/.gitlab-ci/scripts/report_synth.py new file mode 100644 index 0000000000..5f31bce46b --- /dev/null +++ b/.gitlab-ci/scripts/report_synth.py @@ -0,0 +1,90 @@ +# Copyright 2022 Thales Silicon Security +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Original Author: Yannick Casamatta (yannick.casamatta@thalesgroup.com) + +import re +import sys +import os +import yaml +import report_builder as rb + +log_path = str(sys.argv[1]) +with open(log_path, 'r') as f: + log = f.read() + +with open(str(sys.argv[2]), 'r') as f: + synthesis_log = f.read() + +kgate_ratio = int(os.environ["NAND2_AREA"]) +path_re = r'^pd/synth/cva6_([^/]+)' +with open(".gitlab-ci/expected_synth.yml", "r") as f: + expected = yaml.safe_load(f) + +#Compile & elaborate log: +log_metric = rb.LogMetric('Synthesis full log') +error_log = [] +warning_log = [] +for line in synthesis_log.splitlines(): + if os.environ['FOUNDRY_PATH'] in line: + continue + if os.environ['TECH_NAME'] in line: + continue + if 'Error: ' in line: + error_log.append(line) + if 'Warning: ' in line: + warning_log.append(line) +log_metric.values = error_log + warning_log + +# Area repport: +pattern = re.compile( + "^(Combinational area|Buf/Inv area|Noncombinational area|Macro/Black Box area):\ *(\d*\.\d*)$", + re.MULTILINE) +global_val = pattern.findall(log) + +pattern = re.compile( + "^(\w*(?:\/\w*){0,2})\ *(\d*\.\d*)\ *(\d*\.\d*)\ *(\d*\.\d*)\ *(\d*\.\d*)\ *(\d*\.\d*)\ *(\w*)$", + re.MULTILINE) +hier = pattern.findall(log) + +total_area = float(hier[0][1]) + +result_metric = rb.TableMetric('Global results') +kgates = total_area / kgate_ratio +gates = int(kgates * 1000) +result_metric.add_value("Total area", f'{gates} Gates') +for i in global_val: + rel_area = 0 if total_area == 0 else int(float(i[1]) / total_area * 100) + result_metric.add_value(i[0], f'{rel_area} %') +match = re.match(path_re, log_path) +if match: + target = match.group(1) + if target in expected: + diff = gates - expected[target]['gates'] + if abs(diff) >= 300: + result_metric.fail() + else: + raise Exception(f"unexpected target: {target}") +else: + raise Exception(f"unexpected file name: {log_path}") + + +hier_metric = rb.TableMetric('Hierarchies details') +for i in hier: + hier_metric.add_value( + i[0], # hier + f"{int(float(i[1])/kgate_ratio)} kGates", # area + f"{int(float(i[2]))} %", # % + #int(float(i[3]))/int(float(i[1])*100), # % combi + #int(float(i[4]))/int(float(i[1])*100), # % reg + #int(float(i[5]))/int(float(i[1])*100), # % black box + ) + +report = rb.Report(f'{int(kgates)} kGates') +report.add_metric(result_metric, hier_metric, log_metric) + +report.dump() diff --git a/.gitlab-ci/setup-ci-example/core-v-verif-cva6.yml b/.gitlab-ci/setup-ci-example/core-v-verif-cva6.yml new file mode 100644 index 0000000000..a0553c582a --- /dev/null +++ b/.gitlab-ci/setup-ci-example/core-v-verif-cva6.yml @@ -0,0 +1,34 @@ +variables: + RISCV: /opt/common/tools/gcc-10.2.0 + RISCV_PREFIX: /shares/common/tools/gcc-10.2.0/bin/riscv-none-elf- + VERILATOR_ROOT: /opt/common/tools/verilator-4.110 + SPIKE_ROOT: /opt/common/tools/spike + BBL_ROOT: /opt/common/tools/Linux-ariane-sdk + SYN_VCS_BASHRC: /opt/synopsys/vcs/XXXX/setup/bashrc.example + SYN_VERDI_BASHRC: /opt/synopsys/verdi/XXXX/setup/bashrc.ini + SYN_DCSHELL_BASHRC: /opt/synopsys/syn/XXXX/setup/bashrc + QUESTA_BASHRC: /opt/questa/XXXX/setup/bashrc + VIVADO_SETUP: /opt/xilinx/Vivado/XXXX/settings64.sh + CVA6_REPO: https://github.com/openhwgroup/cva6 + CVA6_BRANCH: master + COMPLIANCE_REPO: https://github.com/riscv-non-isa/riscv-arch-test.git + COMPLIANCE_BRANCH: main + COMPLIANCE_HASH: 220e78542da4510e40eac31e31fdd4e77cdae437 + COMPLIANCE_PATCH: ../../../cva6/riscv-compliance.patch + TESTS_REPO: https://github.com/riscv/riscv-tests.git + TESTS_BRANCH: master + TESTS_HASH: f92842f91644092960ac7946a61ec2895e543cec + DV_REPO: https://github.com/google/riscv-dv.git + DV_BRANCH: master + NUM_JOBS: 24 + FOUNDRY_PATH: /techno/lib/stdcellXXXX + TECH_NAME: core_XXXX05v25c + SYNTH_PERIOD : 30 + LIB_VERILOG: /techno/lib/verilog_XXXX/XXXX.v + DASHBOARD_USER_EMAIL: user@example.com + DASHBOARD_USER_NAME: "user" + DASHBOARD_URL: "git@example.com:namespace/repo_name.git" + UART_SERIAL: "/dev/ttyUSBXXXX" + HW_SERVER_URL: "TCP:URLXXX:PORTXXX" + VIVADO_CMD: "vivado_lab" + VIVADO2022_SETUP: /opt/common/tools/XXXX/Vivado_Lab/2022.1/settings64.sh diff --git a/.gitmodules b/.gitmodules index 649e699afa..2fc1e58620 100644 --- a/.gitmodules +++ b/.gitmodules @@ -34,3 +34,6 @@ [submodule "corev_apu/tb/common_verification"] path = corev_apu/tb/common_verification url = https://github.com/pulp-platform/common_verification.git +[submodule "verif/core-v-verif"] + path = verif/core-v-verif + url = https://github.com/openhwgroup/core-v-verif diff --git a/README.md b/README.md index de5990a277..818d4b750b 100644 --- a/README.md +++ b/README.md @@ -30,14 +30,7 @@ The top-level directories of this repo: * **pd**: Example and CI scripts to synthesis CVA6. * **util**: General utility scriptware. * **vendor**: Third-party IP maintained outside the repository. - -## Verification -The verification environment for the CVA6 is _not_ in this Repository. - -The verification environment for this core as well as other cores in the OpenHW Group CORE-V family is at the -[core-v-verif](https://github.com/openhwgroup/core-v-verif) repository on GitHub. - -The Makefiles supported in the **core-v-verif** project automatically clone the appropriate version of the **CVA6** RTL sources. +* **verif**: Verification environment for the CVA6. The verification files shared with other cores are in the [core-v-verif](https://github.com/openhwgroup/core-v-verif) repository on GitHub. core-v-verif is defined as a cva6 submodule. ## Contributing We highly appreciate community contributions. @@ -85,8 +78,11 @@ CVA6 User Documentation - [CVA6 User Documentation](#cva6-user-documentation) - [Getting Started](#getting-started) - [Checkout Repo](#checkout-repo) - - [Install Verilator Simulation Flow](#install-verilator-simulation-flow) - - [Build Model and Run Simulations](#build-model-and-run-simulations) + - [Build Model and Run Simulations with verif directory](#build-model-and-run-simulations-with-verif-directory) + - [Directories](#directories) + - [Prerequisites](#prerequisites) + - [Environent setup](#environent-setup) + - [Test execution](#test-execution) - [Running User-Space Applications](#running-user-space-applications) - [Physical Implementation](#physical-implementation) - [ASIC Synthesis](#asic-synthesis) @@ -114,71 +110,93 @@ The following instructions will allow you to compile and run a Verilator model o ### Checkout Repo Checkout the repository and initialize all submodules -``` +```sh git clone https://github.com/openhwgroup/cva6.git +cd cva6 git submodule update --init --recursive ``` -### Install Verilator Simulation Flow +### Build Model and Run Simulations with verif directory -1. Setup install directory `RISCV` environment variable i.e. `export RISCV=/YOUR/TOOLCHAIN/INSTALLATION/DIRECTORY` -2. Run `./ci/setup.sh` to install all required tools (i.e. verilator, device-tree-compiler, riscv64-unknown-elf-*, ..) +#### verif Directories +- **bsp**: board support package for test-programs compiled/assembled/linked for the CVA6. +This BSP is used by both `core` testbench and `uvmt_cva6` UVM verification environment. +- **regress**: scripts to install tools, test suites, CVA6 code and to execute tests +- **sim**: simulation environment (e.g. riscv-dv) +- **tb**: testbench module instancing the core +- **tests**: source of test cases and test lists -You can install verilator from source using `./ci/install-verilator.sh` or by manually installing `verilator >= 4.002` -Note: There is currently a known issue with version 4.106 and 4.108. 4.106 does not compile and 4.108 hangs after a -couple of cycles simulation time.) +There are README files in each directory with additional information. +#### Prerequisites +To execute tests on CVA6 core, you need a RISC-V toolchain. -### Build Model and Run Simulations +Be aware that only gcc 11.1.0 or newer are supported in core-v-verif repository. +To build and install riscv gcc compiler in local, you can use the following commands : -#### Build default model -Build the Verilator model of CVA6 by using the Makefile: -``` -make verilate +```sh +git clone https://github.com/riscv-collab/riscv-gnu-toolchain +cd riscv-gnu-toolchain +git clone https://github.com/gcc-mirror/gcc -b releases/gcc-13 gcc-13 +./configure –prefix:/path/to/installation/directory --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" --with-gcc-src=`pwd`/gcc-13 +make –j32 ``` -#### Build model with VCD support -To build the verilator model with support for vcd files: -- Install Verilator from source (tested on v4.110): - - https://verilator.org/guide/latest/install.html#run-in-place-from-verilator-root - - You can use the [run-in-place feature](https://verilator.org/guide/latest/install.html#run-in-place-from-verilator-root). No need to install the software. Please note that Makefile needs a C++ file from Verilator sources. - - Set `VERILATOR_ROOT` to the repository root (for instance `export VERILATOR_ROOT=/opt/<verilator_repo>`). +These commands will install the riscv gcc 13.1.0 compiler which is the latest version. +Once running the previous commands, your environment must be updated with : -You can finally generate the model: -``` -make verilate DEBUG=1 TRACE_FAST=1 +```sh +export RISCV=/path/to/installation/directory +export RISCV_PREFIX=$RISCV/bin/riscv-none- +export RISCV_GCC=$RISCV_PREFIXgcc +export CV_SW_PREFIX=riscv-none-elf- ``` -#### Run simulations -This will create a C++ model of the core including a SystemVerilog wrapper and link it against a C++ testbench (in the `tb` subfolder). The binary can be found in the `work-ver` and accepts a RISC-V ELF binary as an argument, e.g.: +This 4 variables will ensure you use correctly the new gcc compiler you have just installed. +You will now be able to run the test scripts. -``` -work-ver/Variane_testharness rv64um-v-divuw -``` +#### Environent setup + +To run simulation, several tools and repositories are needed: +- Gcc as compiler, +- Spike as instruction set simulator, +- Verilator as simulator (if used as simulator to simulate), +- [riscv-dv](https://github.com/google/riscv-dv) as simulation environment. -**Note:** If you want to generate the VCD for the same software (`-v` to specify the VCD filename): -```bash -work-ver/Variane_testharness -v output.vcd rv64um-v-divuw +If you would like to use a precompiled Verilator, please setup the path to the installation directory +```sh +export VERILATOR_INSTALL_DIR=/path/to/installation/directory ``` -The Verilator testbench makes use of the `riscv-fesvr`. This means that you can use the `riscv-tests` repository as well as `riscv-pk` out-of-the-box. As a general rule of thumb the Verilator model will behave like Spike (exception for being orders of magnitudes slower). +The smoke_tests execution will end up the installation by installing Verilator, Spike, tests from regression suites as arch-test, riscv-dv. Then it runs the smoke_tests test. -Both, the Verilator model as well as the Questa simulation will produce trace logs. The Verilator trace is more basic but you can feed the log to `spike-dasm` to resolve instructions to mnemonics. Unfortunately value inspection is currently not possible for the Verilator trace file. +Three simulation types are supported: +- **veri-testharness**: verilator with corev_apu/testharness testbench, +- **vcs-testharness**: vcs with corev_apu/testharness testbench, +- **vcs-uvm**: vcs with UVM testbench. +To check the RTL cva6 behaviour, the RTL simulation trace is compared to spike trace. `DV_SIMULATORS` need to be setup to define which simulators are used. -``` -spike-dasm < trace_hart_00.dasm > logfile.txt +```sh +export DV_SIMULATORS=veri-testharness,spike +sh verif/regress/smoke-tests.sh ``` -To build, compile and run the CVA6 core-only in its example testbench using Verilator (known to work with V4.108): -``` -$ cd core/example_tb -$ make veri_run +#### Test execution + +Run one of the shell scripts: + +```sh +# riscv-compliance (https://github.com/riscv/riscv-compliance) test suite: +sh verif/regress/dv-riscv-compliance.sh +# riscv-tests (https://github.com/riscv/riscv-tests) test suite: +sh verif/regress/dv-riscv-tests.sh ``` -`make help` will print all supported targets. ### Running User-Space Applications +> :warning: **Warning**: this chapter needs to be updated. See Github issue https://github.com/openhwgroup/cva6/issues/1358. + It is possible to run user-space binaries on CVA6 with ([RISC-V Proxy Kernel and Boot Loader](https://github.com/riscv/riscv-pk)). RISC-V PK can be installed by running: `./ci/install-riscvpk.sh` @@ -228,11 +246,13 @@ Reports are under: pd/synth/ariane/reports ### ASIC Gate Simulation with `core-v-verif` repository -``` +> :warning: **Warning**: this chapter needs to be updated. See Github issue https://github.com/openhwgroup/cva6/issues/1358. + +```sh export DV_SIMULATORS=veri-testharness,spike cva6/regress/smoke-tests.sh -make -C core-v-cores/cva6/pd/synth cva6_synth FOUNDRY_PATH=/your/techno/basepath/ TECH_NAME=yourTechnoName TARGET_LIBRARY_FILES="yourLib1.db\ yourLib2.db" PERIOD=10 NAND2_AREA=650 TARGET=cv64a6_imafdc_sv39 ADDITIONAL_SEARCH_PATH="others/libs/paths/one\ others/libs/paths/two" -sed 's/module SyncSpRamBeNx64_1/module SyncSpRamBeNx64_2/' core-v-cores/cva6/pd/synth/ariane_synth.v > core-v-cores/cva6/pd/synth/ariane_synth_modified.v +make -C pd/synth cva6_synth FOUNDRY_PATH=/your/techno/basepath/ TECH_NAME=yourTechnoName TARGET_LIBRARY_FILES="yourLib1.db\ yourLib2.db" PERIOD=10 NAND2_AREA=650 TARGET=cv64a6_imafdc_sv39 ADDITIONAL_SEARCH_PATH="others/libs/paths/one\ others/libs/paths/two" +sed 's/module SyncSpRamBeNx64_1/module SyncSpRamBeNx64_2/' pd/synth/ariane_synth.v > pd/synth/ariane_synth_modified.v cd cva6/sim make vcs_clean python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv64a6_imafdc_sv39-p.yaml --test rv64ui-p-ld --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=spike,vcs-core-gate $DV_OPTS diff --git a/vendor/patches/riscv/riscv-isa-sim/0001-generate-shared-fesvr-lib.patch b/vendor/patches/riscv/riscv-isa-sim/0001-generate-shared-fesvr-lib.patch new file mode 100644 index 0000000000..78c71e567f --- /dev/null +++ b/vendor/patches/riscv/riscv-isa-sim/0001-generate-shared-fesvr-lib.patch @@ -0,0 +1,12 @@ +diff --git a/fesvr/fesvr.mk.in b/fesvr/fesvr.mk.in +index 695de5278..43aed6786 100644 +--- a/fesvr/fesvr.mk.in ++++ b/fesvr/fesvr.mk.in +@@ -20,6 +20,7 @@ fesvr_install_hdrs = $(fesvr_hdrs) + fesvr_install_config_hdr = yes + + fesvr_install_lib = yes ++fesvr_install_shared_lib = yes + + fesvr_srcs = \ + elfloader.cc \ diff --git a/vendor/patches/riscv/riscv-isa-sim/0002-improve-extension-loading-diagnostics.patch b/vendor/patches/riscv/riscv-isa-sim/0002-improve-extension-loading-diagnostics.patch new file mode 100644 index 0000000000..490a8ee50d --- /dev/null +++ b/vendor/patches/riscv/riscv-isa-sim/0002-improve-extension-loading-diagnostics.patch @@ -0,0 +1,15 @@ +diff --git a/riscv/extensions.cc b/riscv/extensions.cc +index 347dc5e91..b488aad15 100644 +--- a/riscv/extensions.cc ++++ b/riscv/extensions.cc +@@ -27,8 +27,8 @@ std::function<extension_t*()> find_extension(const char* name) + if (!dlh) { + dlh = dlopen(libdefault.c_str(), RTLD_LAZY); + if (!dlh) { +- fprintf(stderr, "couldn't find shared library either '%s' or '%s')\n", +- libname.c_str(), libdefault.c_str()); ++ fprintf(stderr, "couldn't load shared library (either '%s' or '%s'), reason: %s\n", ++ libname.c_str(), libdefault.c_str(), dlerror()); + exit(-1); + } + diff --git a/vendor/patches/riscv/riscv-isa-sim/0003-add-cvxif-extension.patch b/vendor/patches/riscv/riscv-isa-sim/0003-add-cvxif-extension.patch new file mode 100644 index 0000000000..3445cda993 --- /dev/null +++ b/vendor/patches/riscv/riscv-isa-sim/0003-add-cvxif-extension.patch @@ -0,0 +1,533 @@ +diff --git a/customext/customext.mk.in b/customext/customext.mk.in +index a14e771c2..888634b46 100644 +--- a/customext/customext.mk.in ++++ b/customext/customext.mk.in +@@ -7,5 +7,6 @@ customext_subproject_deps = \ + customext_srcs = \ + dummy_rocc.cc \ + cflush.cc \ ++ cvxif.cc \ + + customext_install_shared_lib = yes +diff --git a/customext/cvxif.cc b/customext/cvxif.cc +new file mode 100644 +index 000000000..dd1a7329a +--- /dev/null ++++ b/customext/cvxif.cc +@@ -0,0 +1,226 @@ ++// Copyright (C) 2022 Thales DIS Design Services SAS ++// ++// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0. ++// ++// Original Author: Zbigniew CHAMSKI <zbigniew.chamski@thalesgroup.com> ++ ++#include "cvxif.h" ++#include "mmu.h" ++#include <cstring> ++ ++// Define custom insns templates. ++// The insn-level wrapper is 'c##n' (default implementation, ++// writeback disabled), the default implementation ++// is 'custom##n': illegal instruction, return 0. ++// The writeback controller 'cvxif_extn_t::do_writeback_p' ++// is in charge of determining if writeback is required or not. ++// Expected instruction encoding is 4 bytes. ++#define customX(n) \ ++static reg_t c##n(processor_t* p, insn_t insn, reg_t pc) \ ++ { \ ++ cvxif_t* cvxif = static_cast<cvxif_t*>(p->get_extension()); \ ++ cvxif_insn_t custom_insn; \ ++ custom_insn.i = insn; \ ++ reg_t xd = cvxif->default_custom##n(custom_insn); \ ++ if (cvxif->do_writeback_p(custom_insn)) \ ++ WRITE_RD(xd); \ ++ return pc+4; \ ++ } \ ++ \ ++ reg_t default_custom##n(cvxif_insn_t insn) \ ++ { \ ++ return custom##n(insn); \ ++ } ++ ++// This class instantiates the CV-X-IF interface. ++class cvxif_t : public cvxif_extn_t ++{ ++ public: ++ const char* name() { return "cvxif_spike"; } ++ ++ bool do_writeback_p(cvxif_insn_t copro_insn) ++ { ++ // INSN_R personality serves to simplify access to standard encoding fields. ++ cvxif_r_insn_t insn_r = copro_insn.r_type; ++ ++ if (insn_r.opcode != MATCH_CUSTOM3) ++ return false; ++ else switch (insn_r.funct3) ++ { ++ case 0b000: ++ // CUSTOM_NOP and CUSTOM_EXC have rd == x0. ++ // Return TRUE if destination is NOT x0. ++ return (insn_r.rd != 0x0); ++ ++ case 0b010: ++ // Return false for CUS_SD. ++ return false; ++ ++ default: ++ // All other cases: writeback is assumed REQUIRED. ++ return true; ++ } ++ } ++ ++ // Custom0 instructions: default behaviour. ++ reg_t custom0(cvxif_insn_t incoming_insn) ++ { ++ illegal_instruction(); ++ return -1; ++ } ++ ++ // Custom1 instructions: default behaviour. ++ reg_t custom1(cvxif_insn_t incoming_insn) ++ { ++ illegal_instruction(); ++ return -1; ++ } ++ ++ // Custom2 instructions: default behaviour. ++ reg_t custom2(cvxif_insn_t incoming_insn) ++ { ++ illegal_instruction(); ++ return -1; ++ } ++ ++ // Custom3 instructions: provide an explicit implementation of decode+exec. ++ reg_t custom3(cvxif_insn_t incoming_insn) ++ { ++ // Assume R-type insn: it shares opcode and funct3 fields with other CVXIF insn formats. ++ cvxif_r_insn_t r_insn = incoming_insn.r_type; ++ // INSN_T simplifies access to register values. ++ insn_t insn = incoming_insn.i; ++ ++ switch (r_insn.funct3) ++ { ++ case 0: ++ ++ // funct7[1:0] == 0b01: three-input RV add. ++ // If rd is x0: illegal instruction. ++ if ((r_insn.funct7 & 0x3) == 0b01) ++ { ++ if (insn.rd() == 0x0) ++ illegal_instruction(); ++ ++ // Destination is not x0: R4-type insn performing a 3-operand RV add ++ return (reg_t) ((reg_t) RS1 + (reg_t) RS2 + (reg_t) RS3); ++ } ++ ++ // Non-memory operations (including NOP and EXC) ++ switch (r_insn.funct7 & 0b1111001) ++ { ++ case 0: ++ { ++ // Single-cycle RV addition with privilege: all non-privilege bits are zero. ++ // funct7[2:1] == 0x0 (PRV_U): CUS_ADD (single-cycle RV ADD, any mode) ++ // funct7[2:1] == 0x1 (PRV_S): CUS_S_ADD (single-cycle S-/M-mode RV ADD) ++ // funct7[2:1] == 0x2 (PRV_HS): ILLEGAL ++ // funct7[2:1] == 0x3 (PRV_M): CUS_M_ADD (single-cycle M-mode RV ADD) ++ reg_t required_priv = (r_insn.funct7 & 0x6) >> 1; ++ if (required_priv != PRV_HS && (p->get_state()->prv & required_priv) == required_priv) ++ return (reg_t) ((reg_t) RS1 + (reg_t) RS2); ++ else ++ illegal_instruction(); ++ } ++ ++ case 0x8: ++ // Multi-cycle RV add. ++ // TODO FIXME: Represent delay. ++ return (reg_t) ((reg_t) RS1 + (reg_t) RS2); ++ ++ case 0x40: ++ // Exception. MCAUSE[4:0] encoded in RS1, MCAUSE[5] assumed to be 0. ++ if (insn.rd() == 0x0 && insn.rs2() == 0x0) ++ { ++ // Raise an exception only if registers rd and rs2 are both x0 (no 'bit 5' extension yet). ++ raise_exception(insn, insn.rs1()); ++ // Writeback will be disabled by 'do_writeback_p'. ++ return (reg_t) -1; ++ } ++ else ++ // Illegal instruction. ++ illegal_instruction(); ++ ++ default: ++ illegal_instruction(); ++ } ++ ++ case 1: ++ // Perform RV load. If runtime XLEN is not 64, assume 32. ++ if (p->get_xlen() == 64) ++ return MMU.load_int64(RS1 + insn.i_imm()); ++ else ++ return MMU.load_int32(RS1 + insn.i_imm()); ++ ++ case 2: ++ // Perform RV store. If runtime XLEN is not 64, assume 32. ++ if (p->get_xlen() == 64) ++ MMU.store_uint64(RS1 + insn.s_imm(), RS2); ++ else ++ MMU.store_uint32(RS1 + insn.s_imm(), RS2); ++ ++ // Writeback will be disabled by 'do_writeback_p'. ++ break; ++ ++ default: ++ illegal_instruction(); ++ } ++ ++ // FORNOW: Return 0xf......f to simplify debugging. ++ return (reg_t) -1; ++ } ++ ++ cvxif_t() ++ { ++ } ++ ++ void raise_exception(insn_t insn, reg_t exc_index) ++ { ++ switch (exc_index) { ++ case CAUSE_MISALIGNED_LOAD: ++ // Use 0x1 as perfectly unaligned address;-) ++ throw trap_load_address_misaligned((p ? p->get_state()->v : false), 1, 0, 0); ++ case CAUSE_LOAD_ACCESS: ++ // Use 0x1 as invalid address. ++ throw trap_load_access_fault((p ? p->get_state()->v : false), 1, 0, 0); ++ case CAUSE_MISALIGNED_STORE: ++ // Use 0x1 as perfectly unaligned address;-) ++ throw trap_store_address_misaligned((p ? p->get_state()->v : false), 1, 0, 0); ++ case CAUSE_STORE_ACCESS: ++ // Use 0x1 as invalid address. ++ throw trap_store_access_fault((p ? p->get_state()->v : false), 1, 0, 0); ++ case CAUSE_LOAD_PAGE_FAULT: ++ // Use 0x1 as always-faulting address. ++ throw trap_load_page_fault((p ? p->get_state()->v : false), 1, 0, 0); ++ case CAUSE_STORE_PAGE_FAULT: ++ // Use 0x1 as always-faulting address. ++ throw trap_store_page_fault((p ? p->get_state()->v : false), 1, 0, 0); ++ default: ++ illegal_instruction(); ++ } ++ } ++ ++ // Define templates of new instructions. ++ customX(0) ++ customX(1) ++ customX(2) ++ customX(3) ++ ++ // Set instruction handlers for customN opcode patterns. ++ // NOTE: This method may need revisiting if multiple custom extensions are to be loaded ++ // simultaneously in the future. ++ std::vector<insn_desc_t> get_instructions() ++ { ++ std::vector<insn_desc_t> insns; ++ insns.push_back((insn_desc_t){0x0b, 0x7f, &::illegal_instruction, c0}); ++ insns.push_back((insn_desc_t){0x2b, 0x7f, &::illegal_instruction, c1}); ++ insns.push_back((insn_desc_t){0x5b, 0x7f, &::illegal_instruction, c2}); ++ insns.push_back((insn_desc_t){0x7b, 0x7f, &c3, c3}); ++ return insns; ++ } ++ ++private: ++ // State variables go here. ++}; ++ ++REGISTER_EXTENSION(cvxif, []() { return new cvxif_t; }) +diff --git a/customext/cvxif_test.c b/customext/cvxif_test.c +new file mode 100644 +index 000000000..d39ca2229 +--- /dev/null ++++ b/customext/cvxif_test.c +@@ -0,0 +1,111 @@ ++// Copyright (C) 2022 Thales DIS Design Services SAS ++// ++// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0. ++// ++// Original Author: Zbigniew CHAMSKI <zbigniew.chamski@thalesgroup.com> ++// ++// The following is a RISC-V program to test the functionality of the ++// basic CVXIF accelerator interface on the Core-V side. ++// Compile using "riscv-none-elf-gcc -O2 cvxif_test.elf cvxif_test.c" ++// with -march=/-mabi= settings appropriate for your project. ++// Run using "spike -l --extension=cvxif cvxif_test.elf", adding ++// an --isa= setting appropriate for your project. ++// ++// Upon simulating the compiled program, the trace should contain five ++// instances of custom3 instructions (the third one being decoded as ++// 'unknown'). ++// The last occurrence of 'custom3' instruction in the trace, encoded as ++// 0x8002007b, should be immediately followed by exception ++// 'trap_load_address_misaligned' with a tval equal to 0x1 and the ++// execution should terminate correctly with exit code 0. ++// ++// In 64-bit mode, the trace of the last occurrence of custom3 ++// instruction should be equivalent to ++// ++// core 0: 0x0000000080002686 (0x8002007b) custom3 (args unknown) ++// core 0: exception trap_load_address_misaligned, epc 0x0000000080002686 ++// core 0: tval 0x0000000000000001 ++// ++// The corresponding trace in 32-bit mode should be equivalent to ++// ++// core 0: 0x8000205a (0x8002007b) custom3 (args unknown) ++// core 0: exception trap_load_address_misaligned, epc 0x8000205a ++// core 0: tval 0x00000001 ++ ++#include <assert.h> ++#include <stdio.h> ++#include <stdint.h> ++#include <stdlib.h> ++ ++// Values of MCAUSE corresponding to exceptions coming from the coprocessor I/F ++#define CAUSE_MISALIGNED_LOAD 0x4 ++#define CAUSE_LOAD_ACCESS 0x5 ++#define CAUSE_MISALIGNED_STORE 0x6 ++#define CAUSE_STORE_ACCESS 0x7 ++#define CAUSE_LOAD_PAGE_FAULT 0xd ++#define CAUSE_STORE_PAGE_FAULT 0xf ++#define CAUSE_COPROCESSOR_EXCEPTION 0x20 ++ ++// Value of TVAL to pass around. ++#define COPRO_TVAL_TEST 0x1a ++ ++// Macro to read a CSR (from spike's "encoding.h") ++#define read_csr(reg) ({ unsigned long __tmp; \ ++ asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ ++ __tmp; }) ++ ++int main() { ++ // "unsigned long int" is always XLEN bits wide. ++ unsigned long int x = 123, y = 456, z = 0, t = 0; ++ static unsigned long int amem = 111, bmem = 0; ++ unsigned long a; ++ ++ // Add x + y into z. Funct7 == 0, funct3 == 0x0. ++ asm volatile (".insn r CUSTOM_3, 0, 0, %0, %1, %2" : "=r"(z) : "r"(x), "r"(y)); ++ if (z != 123 + 456) ++ { ++ // printf("FAILURE!!!\n"); ++ return 1; ++ } ++ ++ // Add three operands in a single R4-type add. ++ // Leverage current values of x, y and z (z == x + y). ++ asm volatile (".insn r CUSTOM_3, 0, 0x1, %0, %1, %2, %3" : "=r"(t) : "r"(x), "r"(y), "r"(z)); ++ if (t != x + y + z) ++ { ++ // printf("FAILURE"); ++ return 2; ++ } ++ // Load 'a' from 'amem'. CUSTOM_LD: opcode == CUSTOM_3, insn_type == I, funct3 == 0x1. ++ asm volatile (".insn i CUSTOM_3, 0x1, %0, %1" : "=r"(a) : "m"(amem), "I"(0)); ++ if (a != 111) ++ { ++ // printf("FAILURE!!!\n"); ++ return 3; ++ } ++ ++ // Store 'a' in 'bmem'. CUSTOM_SD: opcode == CUSTOM_3, insn_type == S, funct3 == 0x2. ++ asm volatile (".insn s CUSTOM_3, 0x2, %0, %1" : : "r"(a), "m"(bmem)); ++ if (bmem != 111) ++ { ++ // printf("FAILURE!!!\n"); ++ return 4; ++ } ++ ++ // Generate a misaligned load exception (mcause == 0x4). ++ asm volatile (".insn r CUSTOM_3, 0x0, 0x40, x0, x4, x0" : : ); ++ ++ // If we get here, then the exception test failed ==> exit with general failure code. ++ exit(1337); ++} ++ ++// Override default trap handler. ++uintptr_t handle_trap(uintptr_t cause, uintptr_t epc, uintptr_t regs[32]) ++{ ++ if (cause == CAUSE_MISALIGNED_LOAD) ++ // Successfully terminate. ++ exit(0); ++ else ++ // Fail with explicit retcode. ++ exit(5); ++} +diff --git a/riscv/cvxif.h b/riscv/cvxif.h +new file mode 100644 +index 000000000..e3a6fba1d +--- /dev/null ++++ b/riscv/cvxif.h +@@ -0,0 +1,77 @@ ++// Copyright (C) 2022 Thales DIS Design Services SAS ++// ++// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0. ++// ++// Original Author: Zbigniew CHAMSKI <zbigniew.chamski@thalesgroup.com> ++ ++#ifndef _RISCV_CVXIF_H ++#define _RISCV_CVXIF_H ++ ++#include "extension.h" ++ ++// R-type instruction format ++struct cvxif_r_insn_t ++{ ++ unsigned opcode : 7; ++ unsigned rd : 5; ++ unsigned funct3 : 3; ++ unsigned rs1 : 5; ++ unsigned rs2 : 5; ++ unsigned funct7 : 7; ++}; ++ ++// R4-type instruction format ++struct cvxif_r4_insn_t ++{ ++ unsigned opcode : 7; ++ unsigned rd : 5; ++ unsigned funct3 : 3; ++ unsigned rs1 : 5; ++ unsigned rs2 : 5; ++ unsigned funct2 : 2; ++ unsigned rs3 : 5; ++}; ++ ++// I-type instruction format ++struct cvxif_i_insn_t ++{ ++ unsigned opcode : 7; ++ unsigned rd : 5; ++ unsigned funct3 : 3; ++ unsigned rs1 : 5; ++ unsigned imm : 12; ++}; ++ ++// S-type instruction format ++struct cvxif_s_insn_t ++{ ++ unsigned opcode : 7; ++ unsigned imm_low : 5; ++ unsigned funct3 : 3; ++ unsigned rs1 : 5; ++ unsigned rs2 : 5; ++ unsigned imm_high : 7; ++}; ++ ++union cvxif_insn_t ++{ ++ cvxif_r_insn_t r_type; ++ cvxif_r4_insn_t r4_type; ++ cvxif_i_insn_t i_type; ++ cvxif_s_insn_t s_type; ++ insn_t i; ++}; ++ ++class cvxif_extn_t : public extension_t ++{ ++ public: ++ virtual bool do_writeback_p(cvxif_insn_t insn); ++ virtual reg_t custom0(cvxif_insn_t insn); ++ virtual reg_t custom1(cvxif_insn_t insn); ++ virtual reg_t custom2(cvxif_insn_t insn); ++ virtual reg_t custom3(cvxif_insn_t insn); ++ std::vector<insn_desc_t> get_instructions(); ++ std::vector<disasm_insn_t*> get_disasms(); ++}; ++ ++#endif +diff --git a/riscv/cvxif_base.cc b/riscv/cvxif_base.cc +new file mode 100644 +index 000000000..5097344c5 +--- /dev/null ++++ b/riscv/cvxif_base.cc +@@ -0,0 +1,64 @@ ++// Copyright (C) 2022 Thales DIS Design Services SAS ++// ++// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0. ++// ++// Original Author: Zbigniew CHAMSKI <zbigniew.chamski@thalesgroup.com> ++ ++#include "cvxif.h" ++#include "trap.h" ++#include <cstdlib> ++ ++// Virtual base class of CVXIF. ++ ++// Return true if writeback is required. ++// Be on the safe side, disable writeback. ++bool cvxif_extn_t::do_writeback_p(cvxif_insn_t insn) ++{ ++ return false; ++} ++ ++// Define custom insns templates. ++// The insn-level wrapper is 'c##n' (default implementation, ++// writeback disabled), the default implementation ++// is 'custom##n': illegal instruction, return 0. ++// The writeback controller 'cvxif_extn_t::do_writeback_p' ++// is in charge of determining if writeback is required or not. ++// Expected instruction encoding is 4 bytes. ++#define customX(n) \ ++static reg_t c##n(processor_t* p, insn_t insn, reg_t pc) \ ++ { \ ++ cvxif_extn_t* cvxif = static_cast<cvxif_extn_t*>(p->get_extension()); \ ++ cvxif_insn_t custom_insn; \ ++ custom_insn.i = insn; \ ++ reg_t xd = cvxif->custom##n(custom_insn); \ ++ if (cvxif->do_writeback_p(custom_insn)) \ ++ WRITE_RD(xd); \ ++ return pc+4; \ ++ } \ ++ \ ++ reg_t cvxif_extn_t::custom##n(cvxif_insn_t insn) \ ++ { \ ++ illegal_instruction(); \ ++ return -1; \ ++ } ++ ++customX(0) ++customX(1) ++customX(2) ++customX(3) ++ ++std::vector<insn_desc_t> cvxif_extn_t::get_instructions() ++{ ++ std::vector<insn_desc_t> insns; ++ insns.push_back((insn_desc_t){0x0b, 0x7f, &::illegal_instruction, c0}); ++ insns.push_back((insn_desc_t){0x2b, 0x7f, &::illegal_instruction, c1}); ++ insns.push_back((insn_desc_t){0x5b, 0x7f, &::illegal_instruction, c2}); ++ insns.push_back((insn_desc_t){0x7b, 0x7f, &::illegal_instruction, c3}); ++ return insns; ++} ++ ++std::vector<disasm_insn_t*> cvxif_extn_t::get_disasms() ++{ ++ std::vector<disasm_insn_t*> insns; ++ return insns; ++} +diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in +index 56014662c..3da5f6d8b 100644 +--- a/riscv/riscv.mk.in ++++ b/riscv/riscv.mk.in +@@ -26,6 +26,7 @@ riscv_hdrs = \ + cfg.h \ + common.h \ + csrs.h \ ++ cvxif.h \ + debug_defines.h \ + debug_module.h \ + debug_rom_defines.h \ +@@ -58,6 +59,7 @@ + extension.cc \ + extensions.cc \ + rocc.cc \ ++ cvxif_base.cc \ + devices.cc \ + rom.cc \ + clint.cc \ diff --git a/vendor/patches/riscv/riscv-isa-sim/0004-enforce-max-steps-limit.patch b/vendor/patches/riscv/riscv-isa-sim/0004-enforce-max-steps-limit.patch new file mode 100644 index 0000000000..0028d39e1e --- /dev/null +++ b/vendor/patches/riscv/riscv-isa-sim/0004-enforce-max-steps-limit.patch @@ -0,0 +1,110 @@ +diff --git a/vendor/riscv/riscv-isa-sim/riscv/sim.cc b/vendor/riscv/riscv-isa-sim/riscv/sim.cc +index dcbd469d3..8863a5f78 100644 +--- a/vendor/riscv/riscv-isa-sim/riscv/sim.cc ++++ b/vendor/riscv/riscv-isa-sim/riscv/sim.cc +@@ -40,7 +40,8 @@ sim_t::sim_t(const cfg_t *cfg, bool halted, + const char *log_path, + bool dtb_enabled, const char *dtb_file, + bool socket_enabled, +- FILE *cmd_file) // needed for command line option --cmd ++ FILE *cmd_file, // needed for command line option --cmd ++ size_t max_steps) + : htif_t(args), + isa(cfg->isa(), cfg->priv()), + cfg(cfg), +@@ -52,6 +53,8 @@ sim_t::sim_t(const cfg_t *cfg, bool halted, + cmd_file(cmd_file), + sout_(nullptr), + current_step(0), ++ total_steps(0), ++ max_steps(max_steps), + current_proc(0), + debug(false), + histogram_enabled(false), +@@ -236,6 +239,21 @@ void sim_t::step(size_t n) + procs[current_proc]->step(steps); + + current_step += steps; ++ total_steps += steps; ++ ++ // max_steps must be non-zero to act as an execution limit. ++ if (max_steps && total_steps >= max_steps) ++ { ++ // "Stepout": max step count reached/exceeded. ++ std::cerr << "*** Maximum step count reached (total_steps = " ++ << std::dec << total_steps << ", max_steps = " ++ << max_steps << "), exiting!" << std::endl; ++ // TODO FIXME: Determine the best method of terminating. ++ // FORNOW: Exit successfully and let the caller of Spike ++ // decide how to proceed in view of simulation results. ++ exit(0); ++ } ++ + if (current_step == INTERLEAVE) + { + current_step = 0; +diff --git a/vendor/riscv/riscv-isa-sim/riscv/sim.h b/vendor/riscv/riscv-isa-sim/riscv/sim.h +index 3109173f1..377e96514 100644 +--- a/vendor/riscv/riscv-isa-sim/riscv/sim.h ++++ b/vendor/riscv/riscv-isa-sim/riscv/sim.h +@@ -32,7 +32,8 @@ public: + const debug_module_config_t &dm_config, const char *log_path, + bool dtb_enabled, const char *dtb_file, + bool socket_enabled, +- FILE *cmd_file); // needed for command line option --cmd ++ FILE *cmd_file, // needed for command line option --cmd ++ size_t max_steps); + ~sim_t(); + + // run the simulation to completion +@@ -88,6 +89,8 @@ private: + static const size_t INSNS_PER_RTC_TICK = 100; // 10 MHz clock for 1 BIPS core + static const size_t CPU_HZ = 1000000000; // 1GHz CPU + size_t current_step; ++ size_t total_steps; ++ size_t max_steps; + size_t current_proc; + bool debug; + bool histogram_enabled; // provide a histogram of PCs +diff --git a/vendor/riscv/riscv-isa-sim/spike_main/spike.cc b/vendor/riscv/riscv-isa-sim/spike_main/spike.cc +index 7290f38bb..657533cb1 100644 +--- a/vendor/riscv/riscv-isa-sim/spike_main/spike.cc ++++ b/vendor/riscv/riscv-isa-sim/spike_main/spike.cc +@@ -86,6 +86,8 @@ static void help(int exit_code = 1) + fprintf(stderr, " --dm-no-halt-groups Debug module won't support halt groups\n"); + fprintf(stderr, " --dm-no-impebreak Debug module won't support implicit ebreak in program buffer\n"); + fprintf(stderr, " --blocksz=<size> Cache block size (B) for CMO operations(powers of 2) [default 64]\n"); ++ fprintf(stderr, " --steps=<n> Stop simulation after reaching specified number of steps " ++ "(default: unlimited)\n"); + + exit(exit_code); + } +@@ -361,6 +363,7 @@ int main(int argc, char** argv) + .support_haltgroups = true, + .support_impebreak = true + }; ++ size_t max_steps = 0; + cfg_arg_t<size_t> nprocs(1); + + cfg_t cfg(/*default_initrd_bounds=*/std::make_pair((reg_t)0, (reg_t)0), +@@ -465,6 +468,7 @@ int main(int argc, char** argv) + exit(-1); + } + }); ++ parser.option(0, "steps", 1, [&](const char* s){max_steps = strtoull(s, 0, 0);}); + parser.option(0, "dm-progsize", 1, + [&](const char* s){dm_config.progbufsize = atoul_safe(s);}); + parser.option(0, "dm-no-impebreak", 0, +@@ -564,9 +568,9 @@ int main(int argc, char** argv) + } + + sim_t s(&cfg, halted, +- mems, plugin_devices, htif_args, dm_config, log_path, dtb_enabled, dtb_file, +- socket, +- cmd_file); ++ mems, plugin_devices, htif_args, dm_config, log_path, dtb_enabled, dtb_file, ++ socket, ++ cmd_file, max_steps); + std::unique_ptr<remote_bitbang_t> remote_bitbang((remote_bitbang_t *) NULL); + std::unique_ptr<jtag_dtm_t> jtag_dtm( + new jtag_dtm_t(&s.debug_module, dmi_rti)); diff --git a/vendor/patches/riscv/riscv-isa-sim/0005-yield-load-reservation.patch b/vendor/patches/riscv/riscv-isa-sim/0005-yield-load-reservation.patch new file mode 100644 index 0000000000..cc3a98d895 --- /dev/null +++ b/vendor/patches/riscv/riscv-isa-sim/0005-yield-load-reservation.patch @@ -0,0 +1,14 @@ +diff --git a/vendor/riscv/riscv-isa-sim/riscv/sim.cc b/vendor/riscv/riscv-isa-sim/riscv/sim.cc +index 8863a5f7..9179ee4e 100644 +--- a/vendor/riscv/riscv-isa-sim/riscv/sim.cc ++++ b/vendor/riscv/riscv-isa-sim/riscv/sim.cc +@@ -257,7 +257,8 @@ void sim_t::step(size_t n) + if (current_step == INTERLEAVE) + { + current_step = 0; +- procs[current_proc]->get_mmu()->yield_load_reservation(); ++ if (procs.size() > 1) ++ procs[current_proc]->get_mmu()->yield_load_reservation(); + if (++current_proc == procs.size()) { + current_proc = 0; + if (clint) clint->increment(INTERLEAVE / INSNS_PER_RTC_TICK); diff --git a/vendor/patches/riscv/riscv-isa-sim/0006-implement-unknown-cvxif-exception.patch b/vendor/patches/riscv/riscv-isa-sim/0006-implement-unknown-cvxif-exception.patch new file mode 100644 index 0000000000..a35a8e5b70 --- /dev/null +++ b/vendor/patches/riscv/riscv-isa-sim/0006-implement-unknown-cvxif-exception.patch @@ -0,0 +1,85 @@ +diff --git a/vendor/riscv/riscv-isa-sim/customext/cvxif.cc b/vendor/riscv/riscv-isa-sim/customext/cvxif.cc +index ae92b1cc..b1bef8e6 100644 +--- a/vendor/riscv/riscv-isa-sim/customext/cvxif.cc ++++ b/vendor/riscv/riscv-isa-sim/customext/cvxif.cc +@@ -134,17 +134,26 @@ class cvxif_t : public cvxif_extn_t + } + break; + case FUNC3_1: +- //Actually only CUS_ADD using func3 equal to one, we don't need to add another switch case +- return (reg_t) ((reg_t) RS1 + (reg_t) RS2); ++ switch(r_insn.funct7) { ++ case 0: ++ return (reg_t) ((reg_t) RS1 + (reg_t) RS2); ++ break; ++ default: ++ illegal_instruction(); ++ } + + case FUNC3_2: +- //Actually only CUS_EXC using func3 equal to one, we don't need to add another switch case +- if (r_insn.rs2 != 0 || r_insn.rd != 0){ +- illegal_instruction(); +- } else { +- raise_exception(insn, (reg_t) (r_insn.rs1)); +- } +- break; ++ switch (r_insn.funct7) { ++ case (0x60): ++ if (r_insn.rs2 != 0 || r_insn.rd != 0){ ++ illegal_instruction(); ++ } else { ++ raise_exception(insn, (reg_t) (r_insn.rs1)); ++ } ++ break; ++ default: ++ illegal_instruction(); ++ } + default: + illegal_instruction(); + } +@@ -195,15 +204,15 @@ class cvxif_t : public cvxif_extn_t + // Use 0x1 as always-faulting address. + throw trap_store_page_fault((p ? p->get_state()->v : false), 1, 0, 0); + case CAUSE_FETCH_GUEST_PAGE_FAULT: +- throw trap_instruction_guest_page_fault(1, 0, 0); ++ throw trap_instruction_guest_page_fault(0, 0, 0); + case CAUSE_LOAD_GUEST_PAGE_FAULT: +- throw trap_load_guest_page_fault( 1, 0, 0); ++ throw trap_load_guest_page_fault(0, 0, 0); + case CAUSE_VIRTUAL_INSTRUCTION: +- throw trap_virtual_instruction(1); ++ throw trap_virtual_instruction(0); + case CAUSE_STORE_GUEST_PAGE_FAULT: +- throw trap_store_guest_page_fault(1, 0, 0); ++ throw trap_store_guest_page_fault(0, 0, 0); + default: +- illegal_instruction(); ++ throw trap_unknown_instruction(exc_index, (reg_t)0); + } + } + +diff --git a/vendor/riscv/riscv-isa-sim/riscv/trap.h b/vendor/riscv/riscv-isa-sim/riscv/trap.h +index 54948fdd..78b549cf 100644 +--- a/vendor/riscv/riscv-isa-sim/riscv/trap.h ++++ b/vendor/riscv/riscv-isa-sim/riscv/trap.h +@@ -82,6 +82,12 @@ class mem_trap_t : public trap_t + std::string name() { return "trap_"#x; } \ + }; + ++#define DECLARE_CUSTOM_TRAP(x) class trap_##x : public insn_trap_t { \ ++ public: \ ++ trap_##x(reg_t n, reg_t tval) : insn_trap_t(n, false, tval) {} \ ++ std::string name() { return "trap_"#x; } \ ++}; ++ + #define DECLARE_INST_WITH_GVA_TRAP(n, x) class trap_##x : public insn_trap_t { \ + public: \ + trap_##x(bool gva, reg_t tval) : insn_trap_t(n, gva, tval) {} \ +@@ -119,5 +125,6 @@ DECLARE_MEM_GVA_TRAP(CAUSE_FETCH_GUEST_PAGE_FAULT, instruction_guest_page_fault) + DECLARE_MEM_GVA_TRAP(CAUSE_LOAD_GUEST_PAGE_FAULT, load_guest_page_fault) + DECLARE_INST_TRAP(CAUSE_VIRTUAL_INSTRUCTION, virtual_instruction) + DECLARE_MEM_GVA_TRAP(CAUSE_STORE_GUEST_PAGE_FAULT, store_guest_page_fault) ++DECLARE_CUSTOM_TRAP(unknown_instruction) + + #endif diff --git a/vendor/riscv/riscv-isa-sim/.gitignore b/vendor/riscv/riscv-isa-sim/.gitignore new file mode 100644 index 0000000000..6bae0e15f3 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/.gitignore @@ -0,0 +1,9 @@ +build/ +*.gch +autom4te.cache/ +.*.swp +*.o +*.d +.gdb_history +.#* +*~ diff --git a/vendor/riscv/riscv-isa-sim/ChangeLog.md b/vendor/riscv/riscv-isa-sim/ChangeLog.md new file mode 100644 index 0000000000..144cb135d1 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/ChangeLog.md @@ -0,0 +1,36 @@ +Version 1.1.0 +------------- +- Zbkb, Zbkc, Zbkx, Zknd, Zkne, Zknh, Zksed, Zksh scalar cryptography extensions (Zk, Zkn, and Zks groups), v1.0 +- Zkr virtual entropy source emulation, v1.0 +- V extension, v1.0 +- P extension, v0.9.2 +- Zba extension, v1.0 +- Zbb extension, v1.0 +- Zbc extension, v1.0 +- Zbs extension, v1.0 +- Hypervisor extension, v1.0 +- Svnapot extension, v1.0 +- Svpbmt extension, v1.0 +- Svinval extension, v1.0 + +Version 1.0.1-dev +----------------- +- Preliminary support for a subset of the Vector Extension, v0.7.1. +- Support S-mode vectored interrupts (i.e. `stvec[0]` is now writable). +- Added support for dynamic linking of libraries containing MMIO devices. +- Added `--priv` flag to control which privilege modes are available. +- When the commit log is enabled at configure time (`--enable-commitlog`), + it must also be enabled at runtime with the `--log-commits` option. +- Several debug-related additions and changes: + - Added `hasel` debug feature. + - Added `--dm-no-abstract-csr` command-line option. + - Added `--dm-no-halt-groups` command line option. + - Renamed `--progsize` to `--dm-progsize`. + - Renamed `--debug-sba` to `--dm-sba`. + - Renamed `--debug-auth` to `--dm-auth`. + - Renamed `--abstract-rti` to `--dm-abstract-rti`. + - Renamed `--without-hasel` to `--dm-no-hasel`. + +Version 1.0.0 (2019-03-30) +-------------------------- +- First versioned release. diff --git a/vendor/riscv/riscv-isa-sim/LICENSE b/vendor/riscv/riscv-isa-sim/LICENSE new file mode 100644 index 0000000000..34f576ba81 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/LICENSE @@ -0,0 +1,24 @@ +Copyright (c) 2010-2017, The Regents of the University of California +(Regents). All Rights Reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. Neither the name of the Regents nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + +IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, +SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING +OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS +BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED +HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE +MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. diff --git a/vendor/riscv/riscv-isa-sim/Makefile.in b/vendor/riscv/riscv-isa-sim/Makefile.in new file mode 100644 index 0000000000..c3e1822d3b --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/Makefile.in @@ -0,0 +1,521 @@ +#========================================================================= +# Toplevel Makefile for the Modular C++ Build System +#========================================================================= +# Please read the documenation in 'mcppbs-doc.txt' for more details on +# how the Modular C++ Build System works. For most projects, a developer +# will not need to make any changes to this makefile. The key targets +# are as follows: +# +# - default : build all libraries and programs +# - check : build and run all unit tests +# - install : install headers, project library, and some programs +# - clean : remove all generated content (except autoconf files) +# - dist : make a source tarball +# - distcheck : make a source tarball, untar it, check it, clean it +# - distclean : remove everything +# + +#------------------------------------------------------------------------- +# Basic setup +#------------------------------------------------------------------------- + +# Remove all default implicit rules since they can cause subtle bugs +# and they just make things run slower +.SUFFIXES: +% : %,v +% : RCS/%,v +% : RCS/% +% : s.% +% : SCCS/s.% + +# Default is to build the prereqs of the all target (defined at bottom) +default : all +.PHONY : default + +project_name := @PACKAGE_TARNAME@ +src_dir := @srcdir@ +scripts_dir := $(src_dir)/scripts + +HAVE_INT128 := @HAVE_INT128@ +HAVE_DLOPEN := @HAVE_DLOPEN@ +HAVE_CLANG_PCH := @HAVE_CLANG_PCH@ + +# If the version information is not in the configure script, then we +# assume that we are in a working directory. We use the vcs-version.sh +# script in the scripts directory to generate an appropriate version +# string. Currently the way things are setup we have to run this script +# everytime we run make so the script needs to be as fast as possible. + +ifeq (@PACKAGE_VERSION@,?) + project_ver:=$(shell $(scripts_dir)/vcs-version.sh $(src_dir)) +else + project_ver:=@PACKAGE_VERSION@ +endif + +# Installation directories + +prefix ?= @prefix@ + +INSTALLDIR ?= $(DESTDIR)$(prefix) + +install_hdrs_dir := $(INSTALLDIR)/include +install_libs_dir := $(INSTALLDIR)/lib +install_exes_dir := $(INSTALLDIR)/bin + +#------------------------------------------------------------------------- +# List of subprojects +#------------------------------------------------------------------------- + +sprojs := @subprojects@ +sprojs_enabled := @subprojects_enabled@ + +sprojs_include := -I. -I$(src_dir) $(addprefix -I$(src_dir)/, $(sprojs_enabled)) +VPATH := $(addprefix $(src_dir)/, $(sprojs_enabled)) + +#------------------------------------------------------------------------- +# Programs and flags +#------------------------------------------------------------------------- + +# C++ compiler +# - CPPFLAGS : flags for the preprocessor (eg. -I,-D) +# - CXXFLAGS : flags for C++ compiler (eg. -Wall,-g,-O3) +# +# To allow a user to specify CFLAGS or similar as part of the Make +# command, we also have mcpps-CFLAGS etc. with stuff that shouldn't be +# lost in such a case. +# +# The order of precedence (highest to lowest) is then: +# +# - Specified as part of Make command line +# - Specified as part of running configure +# - Specified here (default-CFLAGS) +# +# These all appear on the command line, from lowest precedence to +# highest. + +default-CFLAGS := -DPREFIX=\"$(prefix)\" -Wall -Wno-unused -Wno-nonportable-include-path -g -O2 -fPIC +default-CXXFLAGS := $(default-CFLAGS) -std=c++17 + +mcppbs-CPPFLAGS := @CPPFLAGS@ +mcppbs-CFLAGS := $(default-CFLAGS) @CFLAGS@ +mcppbs-CXXFLAGS := $(mcppbs-CFLAGS) $(default-CXXFLAGS) @CXXFLAGS@ + +CC := @CC@ +CXX := @CXX@ + +# These are the flags actually used for a C++ compile or a C compile. +# The language-specific flags come after the preprocessor flags, but +# user-supplied flags always take precedence. +all-cxx-flags := \ + $(mcppbs-CPPFLAGS) $(mcppbs-CXXFLAGS) $(CPPFLAGS) $(CXXFLAGS) +all-c-flags := \ + $(mcppbs-CPPFLAGS) $(mcppbs-CFLAGS) $(CPPFLAGS) $(CFLAGS) + +COMPILE := $(CXX) -MMD -MP $(all-cxx-flags) $(sprojs_include) @BOOST_CPPFLAGS@ +COMPILE_C := $(CC) -MMD -MP $(all-c-flags) $(sprojs_include) + +# Linker +# - LDFLAGS : Flags for the linker (eg. -L) +# - LIBS : Library flags (eg. -l) + +mcppbs-LDFLAGS := @LDFLAGS@ @BOOST_LDFLAGS@ +all-link-flags := $(mcppbs-LDFLAGS) $(LDFLAGS) + +comma := , +LD := $(CXX) +LIBS := @LIBS@ @BOOST_ASIO_LIB@ @BOOST_REGEX_LIB@ +LINK := $(LD) -L. $(all-link-flags) -Wl,-rpath,$(install_libs_dir) $(patsubst -L%,-Wl$(comma)-rpath$(comma)%,$(filter -L%,$(LDFLAGS))) + +# Library creation + +AR := @AR@ +RANLIB := @RANLIB@ + +# Host simulator + +RUN := @RUN@ +RUNFLAGS := @RUNFLAGS@ + +# Installation + +MKINSTALLDIRS := $(scripts_dir)/mk-install-dirs.sh +INSTALL := @INSTALL@ +INSTALL_HDR := $(INSTALL) -m 644 +INSTALL_LIB := $(INSTALL) -m 644 +INSTALL_EXE := $(INSTALL) -m 755 +STOW := @stow@ + +# Tests +bintests = $(src_dir)/tests/ebreak.py + +#------------------------------------------------------------------------- +# Include subproject makefile fragments +#------------------------------------------------------------------------- + +sprojs_mk = $(addsuffix .mk, $(sprojs_enabled)) + +-include $(sprojs_mk) + +dist_junk += $(sprojs_mk) + +#------------------------------------------------------------------------- +# Reverse list helper function +#------------------------------------------------------------------------- +# This function is used by the subproject template to reverse the list +# of dependencies. It uses recursion to perform the reversal. +# +# Arguments: +# $(1) : space separated input list +# retval : input list in reverse order +# + +reverse_list = $(call reverse_list_h,$(1),) +define reverse_list_h + $(if $(strip $(1)), \ + $(call reverse_list_h, \ + $(wordlist 2,$(words $(1)),$(1)), \ + $(firstword $(1)) $(2)), \ + $(2)) +endef + +#------------------------------------------------------------------------- +# Template for per subproject rules +#------------------------------------------------------------------------- +# The template is instantiated for each of the subprojects. It relies on +# subprojects defining a certain set of make variables which are all +# prefixed with the subproject name. Since subproject names can have +# dashes in them (and the make variables are assumed to only use +# underscores) the template takes two arguments - one with the regular +# subproject name and one with dashes replaced with underscores. +# +# Arguments: +# $(1) : real subproject name (ie with dashes) +# $(2) : normalized subproject name (ie dashes replaced with underscores) +# + +define subproject_template + +# In some (rare) cases, a subproject might not have any actual object +# files. It might only include header files or program sources. To keep +# things consistent we still want a library for this subproject, so in +# this spectial case we create a dummy source file and thus the build +# system will create a library for this subproject with just the +# corresponding dummy object file. + +ifeq ($$(strip $$($(2)_srcs) $$($(2)_c_srcs)),) +$(2)_srcs += _$(1).cc +$(2)_junk += _$(1).cc +endif + +_$(1).cc : + echo "int _$(2)( int arg ) { return arg; }" > $$@ + +# Build the object files for this subproject + +$(2)_pch := $$(patsubst %.h, %.h.gch, $$($(2)_precompiled_hdrs)) +$(2)_objs := $$(patsubst %.cc, %.o, $$($(2)_srcs)) +$(2)_c_objs := $$(patsubst %.c, %.o, $$($(2)_c_srcs)) +$(2)_deps := $$(patsubst %.o, %.d, $$($(2)_objs)) +$(2)_deps += $$(patsubst %.o, %.d, $$($(2)_c_objs)) +$(2)_deps += $$(patsubst %.h, %.h.d, $$($(2)_precompiled_hdrs)) +$$($(2)_pch) : %.h.gch : %.h + $(COMPILE) -x c++-header $$< -c -o $$@ +$$($(2)_objs) : %.o : %.cc $$($(2)_gen_hdrs) $$($(2)_pch) + $(COMPILE) $(if $(HAVE_CLANG_PCH), $$(if $$($(2)_pch), -include-pch $$($(2)_pch))) $$($(2)_CFLAGS) -c $$< +$$($(2)_c_objs) : %.o : %.c $$($(2)_gen_hdrs) + $(COMPILE_C) $$($(2)_CFLAGS) -c $$< + +$(2)_junk += $$($(2)_pch) $$($(2)_objs) $$($(2)_c_objs) $$($(2)_deps) \ + $$($(2)_gen_hdrs) + +# Reverse the dependency list so that a given subproject only depends on +# subprojects listed to its right. This is the correct order for linking +# the list of subproject libraries. + +$(2)_reverse_deps := $$(call reverse_list,$$($(2)_subproject_deps)) + +# Build a library for this subproject + +$(2)_lib_libs := $$($(2)_reverse_deps) +$(2)_lib_libnames := $$(patsubst %, lib%.a, $$($(2)_lib_libs)) +$(2)_lib_libarg := $$(patsubst %, -l%, $$($(2)_lib_libs)) +$(2)_lib_libnames_shared := $$(if $$($(2)_install_shared_lib),lib$(1).so,) + +lib$(1).a : $$($(2)_objs) $$($(2)_c_objs) + rm -f $$@ + $(AR) rcs $$@ $$^ +lib$(1).so : $$($(2)_objs) $$($(2)_c_objs) $$($(2)_lib_libnames_shared) $$($(2)_lib_libnames) + $(LINK) -shared -o $$@ $(if $(filter Darwin,$(shell uname -s)),-install_name $(install_libs_dir)/$$@) $$^ $$($(2)_lib_libnames) $(LIBS) + +$(2)_junk += lib$(1).a +$(2)_junk += $$(if $$($(2)_install_shared_lib),lib$(1).so,) + +# Build unit tests + +$(2)_test_objs := $$(patsubst %.cc, %.o, $$($(2)_test_srcs)) +$(2)_test_deps := $$(patsubst %.o, %.d, $$($(2)_test_objs)) +$(2)_test_exes := $$(patsubst %.t.cc, %-utst, $$($(2)_test_srcs)) +$(2)_test_outs := $$(patsubst %, %.out, $$($(2)_test_exes)) +$(2)_test_libs := $(1) $$($(2)_reverse_deps) utst +$(2)_test_libnames := $$(patsubst %, lib%.a, $$($(2)_test_libs)) +$(2)_test_libarg := $$(patsubst %, -l%, $$($(2)_test_libs)) + +$$($(2)_test_objs) : %.o : %.cc + $(COMPILE) -c $$< + +$$($(2)_test_exes) : %-utst : %.t.o $$($(2)_test_libnames) + $(LINK) -o $$@ $$< $$($(2)_test_libnames) $(LIBS) + +$(2)_deps += $$($(2)_test_deps) +$(2)_junk += \ + $$($(2)_test_objs) $$($(2)_test_deps) \ + $$($(2)_test_exes) *.junk-dat + +# Run unit tests + +$$($(2)_test_outs) : %.out : % + $(RUN) $(RUNFLAGS) ./$$< default | tee $$@ + +$(2)_junk += $$($(2)_test_outs) + +# Build programs + +$(2)_prog_objs := $$(patsubst %.cc, %.o, $$($(2)_prog_srcs)) +$(2)_prog_deps := $$(patsubst %.o, %.d, $$($(2)_prog_objs)) +$(2)_prog_exes := $$(patsubst %.cc, %, $$($(2)_prog_srcs)) +$(2)_prog_libs := $(1) $$($(2)_reverse_deps) +$(2)_prog_libnames := $$(patsubst %, lib%.a, $$($(2)_prog_libs)) +$(2)_prog_libarg := $$(patsubst %, -l%, $$($(2)_prog_libs)) + +$$($(2)_prog_objs) : %.o : %.cc + $(COMPILE) -c $$< + +$$($(2)_prog_exes) : % : %.o $$($(2)_prog_libnames) + $(LINK) -o $$@ $$< $$($(2)_prog_libnames) $(LIBS) + +$(2)_deps += $$($(2)_prog_deps) +$(2)_junk += $$($(2)_prog_objs) $$($(2)_prog_deps) $$($(2)_prog_exes) + +# Build programs which will be installed + +$(2)_install_prog_objs := $$(patsubst %.cc, %.o, $$($(2)_install_prog_srcs)) +$(2)_install_prog_deps := $$(patsubst %.o, %.d, $$($(2)_install_prog_objs)) +$(2)_install_prog_exes := $$(patsubst %.cc, %, $$($(2)_install_prog_srcs)) + +$$($(2)_install_prog_objs) : %.o : %.cc $$($(2)_gen_hdrs) + $(COMPILE) -c $$< + +$$($(2)_install_prog_exes) : % : %.o $$($(2)_prog_libnames) + $(LINK) -o $$@ $$< $$($(2)_prog_libnames) $(LIBS) + +$(2)_deps += $$($(2)_install_prog_deps) +$(2)_junk += \ + $$($(2)_install_prog_objs) $$($(2)_install_prog_deps) \ + $$($(2)_install_prog_exes) + +# Subproject specific targets + +all-$(1) : lib$(1).a $$($(2)_install_prog_exes) + +check-$(1) : $$($(2)_test_outs) + echo; grep -h -e'Unit Tests' -e'FAILED' -e'Segementation' $$^; echo + +clean-$(1) : + rm -rf $$($(2)_junk) + +.PHONY : all-$(1) check-$(1) clean-$(1) + +# Update running variables + +junk += $$($(2)_junk) +deps += $$($(2)_deps) + +test_outs += $$($(2)_test_outs) + +install_config_hdrs += $$(if $$($(2)_install_config_hdr),$(1),) +install_hdrs += $$(addprefix $(src_dir)/$(1)/, $$($(2)_install_hdrs)) +install_libs += $$(if $$($(2)_install_lib),lib$(1).a,) +install_libs += $$(if $$($(2)_install_shared_lib),lib$(1).so,) +install_exes += $$($(2)_install_prog_exes) +install_pcs += $$(if $$($(2)_install_lib),riscv-$(1).pc,) + +endef + +# Iterate over the subprojects and call the template for each one + +$(foreach sproj,$(sprojs_enabled), \ + $(eval $(call subproject_template,$(sproj),$(subst -,_,$(sproj))))) + +#------------------------------------------------------------------------- +# Autodependency files +#------------------------------------------------------------------------- + +-include $(deps) + +deps : $(deps) +.PHONY : deps + +#------------------------------------------------------------------------- +# Check +#------------------------------------------------------------------------- + +bintest_outs = $(bintests:=.out) +junk += $(bintest_outs) +%.out: % all + ./$* < /dev/null 2>&1 | tee $@ + +check-cpp : $(test_outs) + @echo + ! grep -h -e'Unit Tests' -e'FAILED' -e'Segmentation' $^ < /dev/null + @echo + +check-bin : $(bintest_outs) + ! tail -n 1 $^ < /dev/null 2>&1 | grep FAILED + +check : check-cpp check-bin + +.PHONY : check + +#------------------------------------------------------------------------- +# Installation +#------------------------------------------------------------------------- + +install-config-hdrs : config.h + $(MKINSTALLDIRS) $(install_hdrs_dir) + for dir in $(install_config_hdrs); \ + do \ + $(MKINSTALLDIRS) $(install_hdrs_dir)/$$dir; \ + $(INSTALL_HDR) $< $(install_hdrs_dir)/$$dir; \ + done + +install-hdrs : $(install_hdrs) + $(MKINSTALLDIRS) $(install_hdrs_dir) + for file in $(subst $(src_dir)/,,$^); \ + do \ + $(MKINSTALLDIRS) $(install_hdrs_dir)/`dirname $$file`; \ + $(INSTALL_HDR) $(src_dir)/$$file $(install_hdrs_dir)/`dirname $$file`; \ + done + +install-libs : $(install_libs) + $(MKINSTALLDIRS) $(install_libs_dir) + for file in $^; \ + do \ + $(INSTALL_LIB) $$file $(install_libs_dir); \ + done + +install-exes : $(install_exes) + $(MKINSTALLDIRS) $(install_exes_dir) + for file in $^; \ + do \ + $(INSTALL_EXE) $$file $(install_exes_dir); \ + done + +install-pc : $(install_pcs) + $(MKINSTALLDIRS) $(install_libs_dir)/pkgconfig/ + for file in $^; \ + do \ + $(INSTALL_HDR) $$file $(install_libs_dir)/pkgconfig/; \ + done + +install : install-hdrs install-config-hdrs install-libs install-exes install-pc + +.PHONY : install install-hdrs install-config-hdrs install-libs install-exes + +#------------------------------------------------------------------------- +# Regenerate configure information +#------------------------------------------------------------------------- + +config.status : $(src_dir)/configure + ./config.status --recheck + +sprojs_mk_in = \ + $(join $(addprefix $(src_dir)/, $(sprojs_enabled)), \ + $(patsubst %, /%.mk.in, $(sprojs_enabled))) + +Makefile : $(src_dir)/Makefile.in $(sprojs_mk_in) config.status + ./config.status + +dist_junk += config.status config.h Makefile config.log + +#------------------------------------------------------------------------- +# Distribution +#------------------------------------------------------------------------- +# The distribution tarball is named project-ver.tar.gz and it includes +# both enabled and disabled subprojects. + +dist_files = \ + $(sprojs) \ + README \ + style-guide.txt \ + mcppbs-uguide.txt \ + scripts \ + configure.ac \ + aclocal.m4 \ + configure \ + config.h.in \ + Makefile.in \ + +dist_dir := $(project_name)-$(project_ver) +dist_tgz := $(project_name)-$(project_ver).tar.gz + +# Notice that when we make the distribution we rewrite the configure.ac +# script with the current version and we rerun autoconf in the new +# source directory so that the distribution will have the proper version +# information. We also rewrite the "Version : " line in the README. + +dist : + rm -rf $(dist_dir) + mkdir $(dist_dir) + tar -C $(src_dir) -cf - $(dist_files) | tar -C $(dist_dir) -xpf - + sed -i.bak 's/^\(# Version :\).*/\1 $(project_ver)/' $(dist_dir)/README + sed -i.bak 's/\( proj_version,\).*/\1 [$(project_ver)])/' $(dist_dir)/configure.ac + cd $(dist_dir) && \ + autoconf && autoheader && \ + rm -rf autom4te.cache configure.ac.bak README.bak + tar -czvf $(dist_tgz) $(dist_dir) + rm -rf $(dist_dir) + +# You can use the distcheck target to try untarring the distribution and +# then running configure, make, make check, and make distclean. A +# "directory is not empty" error means distclean is not removing +# everything. + +distcheck : dist + rm -rf $(dist_dir) + tar -xzvf $(dist_tgz) + mkdir -p $(dist_dir)/build + cd $(dist_dir)/build; ../configure; make; make check; make distclean + rm -rf $(dist_dir) + +junk += $(project_name)-*.tar.gz + +.PHONY : dist distcheck + +#------------------------------------------------------------------------- +# Default +#------------------------------------------------------------------------- + +all : $(install_hdrs) $(install_libs) $(install_exes) +.PHONY : all + +#------------------------------------------------------------------------- +# Makefile debugging +#------------------------------------------------------------------------- +# This handy rule will display the contents of any make variable by +# using the target debug-<varname>. So for example, make debug-junk will +# display the contents of the junk variable. + +debug-% : + @echo $* = $($*) + +#------------------------------------------------------------------------- +# Clean up junk +#------------------------------------------------------------------------- + +clean : + rm -rf *~ \#* $(junk) + +distclean : + rm -rf *~ \#* $(junk) $(dist_junk) + +.PHONY : clean distclean diff --git a/vendor/riscv/riscv-isa-sim/README.md b/vendor/riscv/riscv-isa-sim/README.md new file mode 100644 index 0000000000..9455bfae6e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/README.md @@ -0,0 +1,314 @@ +Spike RISC-V ISA Simulator +============================ + +About +------------- + +Spike, the RISC-V ISA Simulator, implements a functional model of one or more +RISC-V harts. It is named after the golden spike used to celebrate the +completion of the US transcontinental railway. + +Spike supports the following RISC-V ISA features: + - RV32I and RV64I base ISAs, v2.1 + - RV32E and RV64E base ISAs, v1.9 + - Zifencei extension, v2.0 + - Zicsr extension, v2.0 + - M extension, v2.0 + - A extension, v2.1 + - F extension, v2.2 + - D extension, v2.2 + - Q extension, v2.2 + - C extension, v2.0 + - Zbkb, Zbkc, Zbkx, Zknd, Zkne, Zknh, Zksed, Zksh scalar cryptography extensions (Zk, Zkn, and Zks groups), v1.0 + - Zkr virtual entropy source emulation, v1.0 + - V extension, v1.0 (_requires a 64-bit host_) + - P extension, v0.9.2 + - Zba extension, v1.0 + - Zbb extension, v1.0 + - Zbc extension, v1.0 + - Zbs extension, v1.0 + - Zfh and Zfhmin half-precision floating-point extensions, v1.0 + - Zfinx extension, v1.0 + - Zmmul integer multiplication extension, v1.0 + - Zicbom, Zicbop, Zicboz cache-block maintenance extensions, v1.0 + - Conformance to both RVWMO and RVTSO (Spike is sequentially consistent) + - Machine, Supervisor, and User modes, v1.11 + - Hypervisor extension, v1.0 + - Svnapot extension, v1.0 + - Svpbmt extension, v1.0 + - Svinval extension, v1.0 + - Sdext extension, v1.0-STABLE + - Sdtrig extension, v1.0-STABLE + - 4 triggers support type={2, 3, 4, 5, 6, 15} (mcontrol, icount, itrigger, etrigger, mcontrol6, disabled) + - Smepmp extension v1.0 + - Smstateen extension, v1.0 + - Sscofpmf v0.5.2 + - Zca extension, v1.0 + - Zcb extension, v1.0 + - Zcf extension, v1.0 + - Zcd extension, v1.0 + - Zcmp extension, v1.0 + - Zcmt extension, v1.0 + +As a Spike extension, the remainder of the proposed +[Bit-Manipulation Extensions](https://github.com/riscv/riscv-bitmanip) +is provided under the Spike-custom extension name _Xbitmanip_. +These instructions (and, of course, the extension name) are not RISC-V +standards. + +These proposed bit-manipulation extensions can be split into further +groups: Zbp, Zbs, Zbe, Zbf, Zbc, Zbm, Zbr, Zbt. Note that Zbc is +ratified, but the original proposal contained some extra instructions +(64-bit carryless multiplies) which are captured here. + +To enable these extensions individually, use the Spike-custom +extension names _XZbp_, _XZbs_, _XZbc_, and so on. + +Versioning and APIs +------------------- + +Projects are versioned primarily to indicate when the API has been extended or +rendered incompatible. In that spirit, Spike aims to follow the +[SemVer](https://semver.org/spec/v2.0.0.html) versioning scheme, in which +major version numbers are incremented when backwards-incompatible API changes +are made; minor version numbers are incremented when new APIs are added; and +patch version numbers are incremented when bugs are fixed in +a backwards-compatible manner. + +Spike's principal public API is the RISC-V ISA. _The C++ interface to Spike's +internals is **not** considered a public API at this time_, and +backwards-incompatible changes to this interface _will_ be made without +incrementing the major version number. + +Build Steps +--------------- + +We assume that the RISCV environment variable is set to the RISC-V tools +install path. + + $ apt-get install device-tree-compiler + $ mkdir build + $ cd build + $ ../configure --prefix=$RISCV + $ make + $ [sudo] make install + +If your system uses the `yum` package manager, you can substitute +`yum install dtc` for the first step. + +Build Steps on OpenBSD +---------------------- + +Install bash, gmake, dtc, and use clang. + + $ pkg_add bash gmake dtc + $ exec bash + $ export CC=cc; export CXX=c++ + $ mkdir build + $ cd build + $ ../configure --prefix=$RISCV + $ gmake + $ [doas] make install + +Compiling and Running a Simple C Program +------------------------------------------- + +Install spike (see Build Steps), riscv-gnu-toolchain, and riscv-pk. + +Write a short C program and name it hello.c. Then, compile it into a RISC-V +ELF binary named hello: + + $ riscv64-unknown-elf-gcc -o hello hello.c + +Now you can simulate the program atop the proxy kernel: + + $ spike pk hello + +Simulating a New Instruction +------------------------------------ + +Adding an instruction to the simulator requires two steps: + + 1. Describe the instruction's functional behavior in the file + riscv/insns/<new_instruction_name>.h. Examine other instructions + in that directory as a starting point. + + 2. Add the opcode and opcode mask to riscv/opcodes.h. Alternatively, + add it to the riscv-opcodes package, and it will do so for you: + ``` + $ cd ../riscv-opcodes + $ vi opcodes // add a line for the new instruction + $ make install + ``` + + 3. Rebuild the simulator. + +Interactive Debug Mode +--------------------------- + +To invoke interactive debug mode, launch spike with -d: + + $ spike -d pk hello + +To see the contents of an integer register (0 is for core 0): + + : reg 0 a0 + +To see the contents of a floating point register: + + : fregs 0 ft0 + +or: + + : fregd 0 ft0 + +depending upon whether you wish to print the register as single- or double-precision. + +To see the contents of a memory location (physical address in hex): + + : mem 2020 + +To see the contents of memory with a virtual address (0 for core 0): + + : mem 0 2020 + +You can advance by one instruction by pressing the enter key. You can also +execute until a desired equality is reached: + + : until pc 0 2020 (stop when pc=2020) + : until reg 0 mie a (stop when register mie=0xa) + : until mem 2020 50a9907311096993 (stop when mem[2020]=50a9907311096993) + +Alternatively, you can execute as long as an equality is true: + + : while mem 2020 50a9907311096993 + +You can continue execution indefinitely by: + + : r + +At any point during execution (even without -d), you can enter the +interactive debug mode with `<control>-<c>`. + +To end the simulation from the debug prompt, press `<control>-<c>` or: + + : q + +Debugging With Gdb +------------------ + +An alternative to interactive debug mode is to attach using gdb. Because spike +tries to be like real hardware, you also need OpenOCD to do that. OpenOCD +doesn't currently know about address translation, so it's not possible to +easily debug programs that are run under `pk`. We'll use the following test +program: +``` +$ cat rot13.c +char text[] = "Vafgehpgvba frgf jnag gb or serr!"; + +// Don't use the stack, because sp isn't set up. +volatile int wait = 1; + +int main() +{ + while (wait) + ; + + // Doesn't actually go on the stack, because there are lots of GPRs. + int i = 0; + while (text[i]) { + char lower = text[i] | 32; + if (lower >= 'a' && lower <= 'm') + text[i] += 13; + else if (lower > 'm' && lower <= 'z') + text[i] -= 13; + i++; + } + +done: + while (!wait) + ; +} +$ cat spike.lds +OUTPUT_ARCH( "riscv" ) + +SECTIONS +{ + . = 0x10110000; + .text : { *(.text) } + .data : { *(.data) } +} +$ riscv64-unknown-elf-gcc -g -Og -o rot13-64.o -c rot13.c +$ riscv64-unknown-elf-gcc -g -Og -T spike.lds -nostartfiles -o rot13-64 rot13-64.o +``` + +To debug this program, first run spike telling it to listen for OpenOCD: +``` +$ spike --rbb-port=9824 -m0x10100000:0x20000 rot13-64 +Listening for remote bitbang connection on port 9824. +``` + +In a separate shell run OpenOCD with the appropriate configuration file: +``` +$ cat spike.cfg +adapter driver remote_bitbang +remote_bitbang host localhost +remote_bitbang port 9824 + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0xdeadbeef + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME riscv -chain-position $_TARGETNAME + +gdb_report_data_abort enable + +init +halt +$ openocd -f spike.cfg +Open On-Chip Debugger 0.10.0-dev-00002-gc3b344d (2017-06-08-12:14) +... +riscv.cpu: target state: halted +``` + +In yet another shell, start your gdb debug session: +``` +tnewsome@compy-vm:~/SiFive/spike-test$ riscv64-unknown-elf-gdb rot13-64 +GNU gdb (GDB) 8.0.50.20170724-git +Copyright (C) 2017 Free Software Foundation, Inc. +License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html> +This is free software: you are free to change and redistribute it. +There is NO WARRANTY, to the extent permitted by law. Type "show copying" +and "show warranty" for details. +This GDB was configured as "--host=x86_64-pc-linux-gnu --target=riscv64-unknown-elf". +Type "show configuration" for configuration details. +For bug reporting instructions, please see: +<http://www.gnu.org/software/gdb/bugs/>. +Find the GDB manual and other documentation resources online at: +<http://www.gnu.org/software/gdb/documentation/>. +For help, type "help". +Type "apropos word" to search for commands related to "word"... +Reading symbols from rot13-64...done. +(gdb) target remote localhost:3333 +Remote debugging using localhost:3333 +0x0000000010010004 in main () at rot13.c:8 +8 while (wait) +(gdb) print wait +$1 = 1 +(gdb) print wait=0 +$2 = 0 +(gdb) print text +$3 = "Vafgehpgvba frgf jnag gb or serr!" +(gdb) b done +Breakpoint 1 at 0x10110064: file rot13.c, line 22. +(gdb) c +Continuing. +Disabling abstract command writes to CSRs. + +Breakpoint 1, main () at rot13.c:23 +23 while (!wait) +(gdb) print wait +$4 = 0 +(gdb) print text +... +``` diff --git a/vendor/riscv/riscv-isa-sim/VERSION b/vendor/riscv/riscv-isa-sim/VERSION new file mode 100644 index 0000000000..6ce2a75593 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/VERSION @@ -0,0 +1 @@ +#define SPIKE_VERSION "1.1.1-dev" diff --git a/vendor/riscv/riscv-isa-sim/aclocal.m4 b/vendor/riscv/riscv-isa-sim/aclocal.m4 new file mode 100644 index 0000000000..def74dbadf --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/aclocal.m4 @@ -0,0 +1,302 @@ +#========================================================================= +# Local Autoconf Macros +#========================================================================= +# This file contains the macros for the Modular C++ Build System and +# additional autoconf macros which developers can use in their +# configure.ac scripts. Please read the documentation in +# 'mcppbs-doc.txt' for more details on how the Modular C++ Build System +# works. The documenation for each macro should include information +# about the author, date, and copyright. + +#------------------------------------------------------------------------- +# MCPPBS_PROG_INSTALL +#------------------------------------------------------------------------- +# This macro will add an --enable-stow command line option to the +# configure script. When enabled, this macro will first check to see if +# the stow program is available and if so it will set the $stow shell +# variable to the binary name and the $enable_stow shell variable to +# "yes". These variables can be used in a makefile to conditionally use +# stow for installation. +# +# This macro uses two environment variables to help setup default stow +# locations. The $STOW_PREFIX is used for stowing native built packages. +# The packages are staged in $STOW_PREFIX/pkgs and then symlinks are +# created from within $STOW_PREFIX into the pkgs subdirectory. If you +# only do native builds then this is all you need to set. If you don't +# set $STOW_PREFIX then the default is just the normal default prefix +# which is almost always /usr/local. +# +# For non-native builds we probably want to install the packages in a +# different location which includes the host architecture name as part +# of the prefix. For these kind of builds, we can specify the $STOW_ROOT +# environment variable and the effective prefix will be +# $STOW_ROOT/${host_alias} where ${host_alias} is specified on the +# configure command line with "--host". +# +# Here is an example setup: +# +# STOW_ROOT="$HOME/install" +# STOW_ARCH="i386-macosx10.4" +# STOW_PREFIX="${STOW_ROOT}/${STOW_ARCH}" +# + +AC_DEFUN([MCPPBS_PROG_INSTALL], +[ + + # Configure command line option + + AC_ARG_ENABLE(stow, + AS_HELP_STRING(--enable-stow,[Enable stow-based install]), + [enable_stow="yes"],[enable_stow="no"]) + + AC_SUBST([enable_stow]) + + # Environment variables + + AC_ARG_VAR([STOW_ROOT], [Root for non-native stow-based installs]) + AC_ARG_VAR([STOW_PREFIX], [Prefix for stow-based installs]) + + # Check for install script + + AC_PROG_INSTALL +]) + +#------------------------------------------------------------------------- +# MCPPBS_PROG_RUN +# ------------------------------------------------------------------------- +# If we are doing a non-native build then we look for an isa simulator +# to use for running tests. We set the RUN substitution variable to be +# empty for native builds or to the name of the isa simulator for +# non-native builds. Thus a makefile can run compiled programs +# regardless if we are doing a native or non-native build like this: +# +# $(RUN) $(RUNFLAGS) ./test-program +# + +AC_DEFUN([MCPPBS_PROG_RUN], +[ + AS_IF([ test "${build}" != "${host}" ], + [ + AC_CHECK_TOOLS([RUN],[isa-run run],[no]) + AS_IF([ test ${RUN} = "no" ], + [ + AC_MSG_ERROR([Cannot find simulator for target ${target_alias}]) + ]) + ],[ + RUN="" + ]) + AC_SUBST([RUN]) + AC_SUBST([RUNFLAGS]) +]) + +#------------------------------------------------------------------------- +# MCPPBS_SUBPROJECTS([ sproj1, sproj2, ... ]) +#------------------------------------------------------------------------- +# The developer should call this macro with a list of the subprojects +# which make up this project. One should order the list such that any +# given subproject only depends on subprojects listed before it. The +# subproject names can also include an * suffix which indicates that +# this is an optional subproject. Optional subprojects are only included +# as part of the project build if enabled on the configure command line +# with a --enable-<subproject> flag. The user can also specify that all +# optional subprojects should be included in the build with the +# --enable-optional-subprojects flag. +# +# Subproject names can also include a ** suffix which indicates that it +# is an optional subproject, but there is a group with the same name. +# Thus the --enable-<sproj> command line option will enable not just the +# subproject sproj but all of the subprojects which are in the group. +# There is no error checking to make sure that if you use the ** suffix +# you actually define a group so be careful. +# +# Both required and optional subprojects should have a 'subproject.ac' +# file. The script's filename should be the abbreivated subproject name +# (assuming the subproject name is sproj then we would use 'sproj.ac') +# The MCPPBS_SUBPROJECTS macro includes the 'subproject.ac' files for +# enabled subprojects. Whitespace and newlines are allowed within the +# list. +# +# Author : Christopher Batten +# Date : September 10, 2008 + +AC_DEFUN([MCPPBS_SUBPROJECTS], +[ + + # Add command line argument to enable all optional subprojects + + AC_ARG_ENABLE(optional-subprojects, + AS_HELP_STRING([--enable-optional-subprojects], + [Enable all optional subprojects])) + + # Loop through the subprojects given in the macro argument + + m4_foreach([MCPPBS_SPROJ],[$1], + [ + + # Determine if this is a required or an optional subproject + + m4_define([MCPPBS_IS_REQ], + m4_bmatch(MCPPBS_SPROJ,[\*+],[false],[true])) + + # Determine if there is a group with the same name + + m4_define([MCPPBS_IS_GROUP], + m4_bmatch(MCPPBS_SPROJ,[\*\*],[true],[false])) + + # Create variations of the subproject name suitable for use as a CPP + # enabled define, a shell enabled variable, and a shell function + + m4_define([MCPPBS_SPROJ_NORM], + m4_normalize(m4_bpatsubsts(MCPPBS_SPROJ,[*],[]))) + + m4_define([MCPPBS_SPROJ_DEFINE], + m4_toupper(m4_bpatsubst(MCPPBS_SPROJ_NORM[]_ENABLED,[-],[_]))) + + m4_define([MCPPBS_SPROJ_FUNC], + m4_bpatsubst(_mpbp_[]MCPPBS_SPROJ_NORM[]_configure,[-],[_])) + + m4_define([MCPPBS_SPROJ_UNDERSCORES], + m4_bpatsubsts(MCPPBS_SPROJ,[-],[_])) + + m4_define([MCPPBS_SPROJ_SHVAR], + m4_bpatsubst(enable_[]MCPPBS_SPROJ_NORM[]_sproj,[-],[_])) + + # Add subproject to our running list + + subprojects="$subprojects MCPPBS_SPROJ_NORM" + + # Process the subproject appropriately. If enabled add it to the + # $enabled_subprojects running shell variable, set a + # SUBPROJECT_ENABLED C define, and include the appropriate + # 'subproject.ac'. + + m4_if(MCPPBS_IS_REQ,[true], + [ + AC_MSG_NOTICE([configuring default subproject : MCPPBS_SPROJ_NORM]) + AC_CONFIG_FILES(MCPPBS_SPROJ_NORM[].mk:MCPPBS_SPROJ_NORM[]/MCPPBS_SPROJ_NORM[].mk.in) + MCPPBS_SPROJ_SHVAR="yes" + subprojects_enabled="$subprojects_enabled MCPPBS_SPROJ_NORM" + AC_DEFINE(MCPPBS_SPROJ_DEFINE,, + [Define if subproject MCPPBS_SPROJ_NORM is enabled]) + m4_include(MCPPBS_SPROJ_NORM[]/MCPPBS_SPROJ_NORM[].ac) + ],[ + + # For optional subprojects we capture the 'subproject.ac' as a + # shell function so that in the MCPPBS_GROUP macro we can just + # call this shell function instead of reading in 'subproject.ac' + # again. + + MCPPBS_SPROJ_FUNC () + { + AC_MSG_NOTICE([configuring optional subproject : MCPPBS_SPROJ_NORM]) + AC_CONFIG_FILES(MCPPBS_SPROJ_NORM[].mk:MCPPBS_SPROJ_NORM[]/MCPPBS_SPROJ_NORM[].mk.in) + MCPPBS_SPROJ_SHVAR="yes" + subprojects_enabled="$subprojects_enabled MCPPBS_SPROJ_NORM" + AC_DEFINE(MCPPBS_SPROJ_DEFINE,, + [Define if subproject MCPPBS_SPROJ_NORM is enabled]) + m4_include(MCPPBS_SPROJ_NORM[]/MCPPBS_SPROJ_NORM[].ac) + }; + + # Optional subprojects add --enable-subproject command line + # options, _if_ the subproject name is not also a group name. + + m4_if(MCPPBS_IS_GROUP,[false], + [ + AC_ARG_ENABLE(MCPPBS_SPROJ_NORM, + AS_HELP_STRING(--enable-MCPPBS_SPROJ_NORM, + [Subproject MCPPBS_SPROJ_NORM]), + [MCPPBS_SPROJ_SHVAR="yes"],[MCPPBS_SPROJ_SHVAR="no"]) + + AS_IF([test "$MCPPBS_SPROJ_SHVAR" = "yes"], + [ + eval "MCPPBS_SPROJ_FUNC" + ],[ + AC_MSG_NOTICE([processing optional subproject : MCPPBS_SPROJ_NORM]) + ]) + + ],[ + + # If the subproject name is also a group name then we need to + # make sure that we set the shell variable for that subproject to + # no so that the group code knows we haven't run it yet. + + AC_MSG_NOTICE([processing optional subproject : MCPPBS_SPROJ_NORM]) + MCPPBS_SPROJ_SHVAR="no" + + ]) + + # Always execute the subproject configure code if we are enabling + # all subprojects. + + AS_IF([ test "$enable_optional_subprojects" = "yes" \ + && test "$MCPPBS_SPROJ_SHVAR" = "no" ], + [ + eval "MCPPBS_SPROJ_FUNC" + ]) + + ]) + + ]) + + # Output make variables + + AC_SUBST([subprojects]) + AC_SUBST([subprojects_enabled]) + +]) + +#------------------------------------------------------------------------- +# MCPPBS_GROUP( [group-name], [ sproj1, sproj2, ... ] ) +#------------------------------------------------------------------------- +# This macro creates a subproject group with the given group-name. When +# a user specifies --enable-<group-name> the listed subprojects will be +# enabled. Groups can have the same name as a subproject and in that +# case whenever a user specifies --enable-<subproject> the subprojects +# listed in the corresponding group will also be enabled. Groups are +# useful for specifying related subprojects which are usually enabled +# together, as well as for specifying that a specific optional +# subproject has dependencies on other optional subprojects. +# +# Author : Christopher Batten +# Date : September 10, 2008 + +AC_DEFUN([MCPPBS_GROUP], +[ + + m4_define([MCPPBS_GROUP_NORM], + m4_normalize([$1])) + + m4_define([MCPPBS_GROUP_SHVAR], + m4_bpatsubst(enable_[]MCPPBS_GROUP_NORM[]_group,[-],[_])) + + AC_ARG_ENABLE(MCPPBS_GROUP_NORM, + AS_HELP_STRING(--enable-MCPPBS_GROUP_NORM, + [Group MCPPBS_GROUP_NORM: $2]), + [MCPPBS_GROUP_SHVAR="yes"],[MCPPBS_GROUP_SHVAR="no"]) + + AS_IF([test "$MCPPBS_GROUP_SHVAR" = "yes" ], + [ + AC_MSG_NOTICE([configuring optional group : MCPPBS_GROUP_NORM]) + ]) + + m4_foreach([MCPPBS_SPROJ],[$2], + [ + + m4_define([MCPPBS_SPROJ_NORM], + m4_normalize(MCPPBS_SPROJ)) + + m4_define([MCPPBS_SPROJ_SHVAR], + m4_bpatsubst(enable_[]MCPPBS_SPROJ_NORM[]_sproj,[-],[_])) + + m4_define([MCPPBS_SPROJ_FUNC], + m4_bpatsubst(_mpbp_[]MCPPBS_SPROJ_NORM[]_configure,[-],[_])) + + AS_IF([ test "$MCPPBS_GROUP_SHVAR" = "yes" \ + && test "$MCPPBS_SPROJ_SHVAR" = "no" ], + [ + eval "MCPPBS_SPROJ_FUNC" + ]) + + ]) + +]) diff --git a/vendor/riscv/riscv-isa-sim/arch_test_target/spike/Makefile.include b/vendor/riscv/riscv-isa-sim/arch_test_target/spike/Makefile.include new file mode 100644 index 0000000000..13eacdc1f5 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/arch_test_target/spike/Makefile.include @@ -0,0 +1,25 @@ +# set TARGETDIR to point to the directory which contains a sub-folder in the same name as the target +export TARGETDIR ?= /scratch/git-repo/github/neel/riscv-isa-sim/arch_test_target + +# set XLEN to max supported XLEN. Allowed values are 32 and 64 +export XLEN ?= 64 + +# name of the target. Note a folder of the same name must exist in the TARGETDIR directory +export RISCV_TARGET ?= spike + +# set the RISCV_DEVICE environment to a single extension you want to compile, simulate and/or verify. +# Leave this blank if you want to iterate through all the supported extensions available in the target +export RISCV_DEVICE ?= + +# set this to a string which needs to be passed to your target Makefile.include files +export RISCV_TARGET_FLAGS ?= + +# set this if you want to enable assertions on the test-suites. Currently no tests support +# assertions. +export RISCV_ASSERT ?= 0 + +# set the number of parallel jobs (along with any other arguments) you would like to execute. Note that the target needs to ensure +# that no common files across jobs are created/overwritten leading to unknown behavior +JOBS= -j1 + + diff --git a/vendor/riscv/riscv-isa-sim/arch_test_target/spike/README.md b/vendor/riscv/riscv-isa-sim/arch_test_target/spike/README.md new file mode 100644 index 0000000000..56af2492ec --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/arch_test_target/spike/README.md @@ -0,0 +1,58 @@ +# Using the Spike Simulator as an Architectural test model + +This is a reference for running Spike as a target for the RISC-V Architectural Test framework. + +## Getting Spike + +The Spike repository should be cloned from [here](https://github.com/riscv/riscv-isa-sim/), preferably at the same directory level as the riscv-arch-test repository. + +## Building Spike + +The [README.md](../README.md) at the top level of the riscv-isa-sim directory gives details on building an executable spike model. + +## Adding Spike as a target to the Architectural Test framework + +Also at the top level is an ``arch_test_target directory``. This directory contains all the collaterals +required to add Spike as a target to the architectural test framework. + +The file ``arch_test_target/spike/Makefile.include`` contains various parameters which can be set by +the user to modify the instance of spike on which the tests need to be run. +The user can modify the ``XLEN`` variable based on whether 32-bit or 64-bit tests need to be run. +If one would like to run tests of a single extension then set the `RISCV_DEVICE` to that extension +name (eg. M, C, Zifencei, etc). Leaving the ``RISCV_DEVICE`` empty would indicate running all tests +for all extensions available in the ``device/rv{XLEN}i_m`` directory No other variables should be modified. + +Now clone the architectural test framework repo and copy the updated Makefile.include to it: + +``` + $ git clone https://github.com/riscv/riscv-arch-test.git + $ cd riscv-arch-test + $ cp <custom-path>/riscv-isa-sim/arch_test_target/spike/Makefile.include . +``` + +The user will have to modify the ``TARGETDIR`` variable in ``riscv-arch-test/Makefile.include`` to point to the +absolute location of the ``riscv-isa-sim/arch_test_target`` directory. + +You can execute the tests from the root directory of the riscv-arch-test repo: + +``` +make compile simulate verify +``` + +## Updating the target for new tests + +As tests for new extensions are added to the architectural test repo, the spike target (i.e. +arch_test_target directory) will also need to be updated accordingly. Please refer to the [Porting a new target](https://github.com/riscv/riscv-arch-test/blob/master/doc/README.adoc#5-porting-a-new-target) +section for more details on what those changes/updates should be. + + + + + + + + + + + + diff --git a/vendor/riscv/riscv-isa-sim/arch_test_target/spike/device/Makefile_common.inc b/vendor/riscv/riscv-isa-sim/arch_test_target/spike/device/Makefile_common.inc new file mode 100644 index 0000000000..c43222de3f --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/arch_test_target/spike/device/Makefile_common.inc @@ -0,0 +1,34 @@ +TARGET_SIM ?= spike +TARGET_FLAGS ?= $(RISCV_TARGET_FLAGS) +ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),) + $(error Target simulator executable '$(TARGET_SIM)` not found) +endif + +RISCV_PREFIX ?= riscv$(XLEN)-unknown-elf- +RISCV_GCC ?= $(RISCV_PREFIX)gcc +RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump +RISCV_GCC_OPTS ?= -g -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles $(RVTEST_DEFINES) + +COMPILE_CMD = $$(RISCV_GCC) $(1) $$(RISCV_GCC_OPTS) \ + -I$(ROOTDIR)/riscv-test-suite/env/ \ + -I$(TARGETDIR)/$(RISCV_TARGET)/ \ + -T$(TARGETDIR)/$(RISCV_TARGET)/link.ld \ + $$(<) -o $$@ +OBJ_CMD = $$(RISCV_OBJDUMP) $$@ -D > $$@.objdump; \ + $$(RISCV_OBJDUMP) $$@ --source > $$@.debug + + +COMPILE_TARGET=\ + $(COMPILE_CMD); \ + if [ $$$$? -ne 0 ] ; \ + then \ + echo "\e[31m$$(RISCV_GCC) failed for target $$(@) \e[39m" ; \ + exit 1 ; \ + fi ; \ + $(OBJ_CMD); \ + if [ $$$$? -ne 0 ] ; \ + then \ + echo "\e[31m $$(RISCV_OBJDUMP) failed for target $$(@) \e[39m" ; \ + exit 1 ; \ + fi ; + diff --git a/vendor/riscv/riscv-isa-sim/arch_test_target/spike/device/rv32e_unratified/C/Makefile.include b/vendor/riscv/riscv-isa-sim/arch_test_target/spike/device/rv32e_unratified/C/Makefile.include new file mode 100644 index 0000000000..daf0f43496 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/arch_test_target/spike/device/rv32e_unratified/C/Makefile.include @@ -0,0 +1,7 @@ +include $(TARGETDIR)/spike/device/Makefile_common.inc +RUN_CMD = $(TARGET_SIM) $(TARGET_FLAGS) --isa=rv32ec \ + +signature=$(*).signature.output +signature-granularity=4\ + $< + +RUN_TARGET=\ + $(RUN_CMD) diff --git a/vendor/riscv/riscv-isa-sim/arch_test_target/spike/device/rv32e_unratified/E/Makefile.include b/vendor/riscv/riscv-isa-sim/arch_test_target/spike/device/rv32e_unratified/E/Makefile.include new file mode 100644 index 0000000000..548b17d7df --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/arch_test_target/spike/device/rv32e_unratified/E/Makefile.include @@ -0,0 +1,7 @@ +include $(TARGETDIR)/spike/device/Makefile_common.inc +RUN_CMD = $(TARGET_SIM) $(TARGET_FLAGS) --isa=rv32e \ + +signature=$(*).signature.output +signature-granularity=4\ + $< + +RUN_TARGET=\ + $(RUN_CMD) diff --git a/vendor/riscv/riscv-isa-sim/arch_test_target/spike/device/rv32e_unratified/M/Makefile.include b/vendor/riscv/riscv-isa-sim/arch_test_target/spike/device/rv32e_unratified/M/Makefile.include new file mode 100644 index 0000000000..749c7fc2a3 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/arch_test_target/spike/device/rv32e_unratified/M/Makefile.include @@ -0,0 +1,7 @@ +include $(TARGETDIR)/spike/device/Makefile_common.inc +RUN_CMD = $(TARGET_SIM) $(TARGET_FLAGS) --isa=rv32em \ + +signature=$(*).signature.output +signature-granularity=4\ + $< + +RUN_TARGET=\ + $(RUN_CMD) diff --git a/vendor/riscv/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/C/Makefile.include b/vendor/riscv/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/C/Makefile.include new file mode 100644 index 0000000000..346feaae75 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/C/Makefile.include @@ -0,0 +1,7 @@ +include $(TARGETDIR)/spike/device/Makefile_common.inc +RUN_CMD = $(TARGET_SIM) $(TARGET_FLAGS) --isa=rv32ic \ + +signature=$(*).signature.output +signature-granularity=4\ + $< + +RUN_TARGET=\ + $(RUN_CMD) diff --git a/vendor/riscv/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/F/Makefile.include b/vendor/riscv/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/F/Makefile.include new file mode 100644 index 0000000000..4fb87c622c --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/F/Makefile.include @@ -0,0 +1,7 @@ +include $(TARGETDIR)/spike/device/Makefile_common.inc +RUN_CMD = $(TARGET_SIM) $(TARGET_FLAGS) --isa=rv32if \ + +signature=$(*).signature.output +signature-granularity=4\ + $< + +RUN_TARGET=\ + $(RUN_CMD) diff --git a/vendor/riscv/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/I/Makefile.include b/vendor/riscv/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/I/Makefile.include new file mode 100644 index 0000000000..740755c0fa --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/I/Makefile.include @@ -0,0 +1,7 @@ +include $(TARGETDIR)/spike/device/Makefile_common.inc +RUN_CMD = $(TARGET_SIM) $(TARGET_FLAGS) --isa=rv32i \ + +signature=$(*).signature.output +signature-granularity=4\ + $< + +RUN_TARGET=\ + $(RUN_CMD) diff --git a/vendor/riscv/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/M/Makefile.include b/vendor/riscv/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/M/Makefile.include new file mode 100644 index 0000000000..5d8de47ce3 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/M/Makefile.include @@ -0,0 +1,7 @@ +include $(TARGETDIR)/spike/device/Makefile_common.inc +RUN_CMD = $(TARGET_SIM) $(TARGET_FLAGS) --isa=rv32im \ + +signature=$(*).signature.output +signature-granularity=4\ + $< + +RUN_TARGET=\ + $(RUN_CMD) diff --git a/vendor/riscv/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/Zifencei/Makefile.include b/vendor/riscv/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/Zifencei/Makefile.include new file mode 100644 index 0000000000..740755c0fa --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/Zifencei/Makefile.include @@ -0,0 +1,7 @@ +include $(TARGETDIR)/spike/device/Makefile_common.inc +RUN_CMD = $(TARGET_SIM) $(TARGET_FLAGS) --isa=rv32i \ + +signature=$(*).signature.output +signature-granularity=4\ + $< + +RUN_TARGET=\ + $(RUN_CMD) diff --git a/vendor/riscv/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/privilege/Makefile.include b/vendor/riscv/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/privilege/Makefile.include new file mode 100644 index 0000000000..8275495db1 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/privilege/Makefile.include @@ -0,0 +1,7 @@ +include $(TARGETDIR)/spike/device/Makefile_common.inc +RUN_CMD = $(TARGET_SIM) $(TARGET_FLAGS) --isa=rv32ic \ + +signature=$(*).signature.output +signature-granularity=4\ + $< + +RUN_TARGET=\ + $(RUN_CMD) diff --git a/vendor/riscv/riscv-isa-sim/arch_test_target/spike/device/rv64i_m/C/Makefile.include b/vendor/riscv/riscv-isa-sim/arch_test_target/spike/device/rv64i_m/C/Makefile.include new file mode 100644 index 0000000000..e6ca9fb3bf --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/arch_test_target/spike/device/rv64i_m/C/Makefile.include @@ -0,0 +1,7 @@ +include $(TARGETDIR)/spike/device/Makefile_common.inc +RUN_CMD = $(TARGET_SIM) $(TARGET_FLAGS) --isa=rv64ic \ + +signature=$(*).signature.output +signature-granularity=4\ + $< + +RUN_TARGET=\ + $(RUN_CMD) diff --git a/vendor/riscv/riscv-isa-sim/arch_test_target/spike/device/rv64i_m/D/Makefile.include b/vendor/riscv/riscv-isa-sim/arch_test_target/spike/device/rv64i_m/D/Makefile.include new file mode 100644 index 0000000000..26113946a9 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/arch_test_target/spike/device/rv64i_m/D/Makefile.include @@ -0,0 +1,8 @@ +include $(TARGETDIR)/spike/device/Makefile_common.inc +RUN_CMD = $(TARGET_SIM) $(TARGET_FLAGS) --isa=rv64ifd \ + +signature=$(*).signature.output +signature-granularity=4\ + $< + +RUN_TARGET=\ + $(RUN_CMD) + diff --git a/vendor/riscv/riscv-isa-sim/arch_test_target/spike/device/rv64i_m/I/Makefile.include b/vendor/riscv/riscv-isa-sim/arch_test_target/spike/device/rv64i_m/I/Makefile.include new file mode 100644 index 0000000000..2c763bf564 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/arch_test_target/spike/device/rv64i_m/I/Makefile.include @@ -0,0 +1,7 @@ +include $(TARGETDIR)/spike/device/Makefile_common.inc +RUN_CMD = $(TARGET_SIM) $(TARGET_FLAGS) --isa=rv64i \ + +signature=$(*).signature.output +signature-granularity=4\ + $< + +RUN_TARGET=\ + $(RUN_CMD) diff --git a/vendor/riscv/riscv-isa-sim/arch_test_target/spike/device/rv64i_m/M/Makefile.include b/vendor/riscv/riscv-isa-sim/arch_test_target/spike/device/rv64i_m/M/Makefile.include new file mode 100644 index 0000000000..8ce555c647 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/arch_test_target/spike/device/rv64i_m/M/Makefile.include @@ -0,0 +1,8 @@ +include $(TARGETDIR)/spike/device/Makefile_common.inc +RUN_CMD = $(TARGET_SIM) $(TARGET_FLAGS) --isa=rv64im \ + +signature=$(*).signature.output +signature-granularity=4\ + $< + +RUN_TARGET=\ + $(RUN_CMD) + diff --git a/vendor/riscv/riscv-isa-sim/arch_test_target/spike/device/rv64i_m/Zifencei/Makefile.include b/vendor/riscv/riscv-isa-sim/arch_test_target/spike/device/rv64i_m/Zifencei/Makefile.include new file mode 100644 index 0000000000..2c763bf564 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/arch_test_target/spike/device/rv64i_m/Zifencei/Makefile.include @@ -0,0 +1,7 @@ +include $(TARGETDIR)/spike/device/Makefile_common.inc +RUN_CMD = $(TARGET_SIM) $(TARGET_FLAGS) --isa=rv64i \ + +signature=$(*).signature.output +signature-granularity=4\ + $< + +RUN_TARGET=\ + $(RUN_CMD) diff --git a/vendor/riscv/riscv-isa-sim/arch_test_target/spike/device/rv64i_m/privilege/Makefile.include b/vendor/riscv/riscv-isa-sim/arch_test_target/spike/device/rv64i_m/privilege/Makefile.include new file mode 100644 index 0000000000..5ef2802f90 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/arch_test_target/spike/device/rv64i_m/privilege/Makefile.include @@ -0,0 +1,7 @@ +include $(TARGETDIR)/spike/device/Makefile_common.inc +RUN_CMD = $(TARGET_SIM) $(TARGET_FLAGS) --isa=rv64ic \ + +signature=$(*).signature.output +signature-granularity=4\ + $< + +RUN_TARGET=\ + $(RUN_CMD) diff --git a/vendor/riscv/riscv-isa-sim/arch_test_target/spike/link.ld b/vendor/riscv/riscv-isa-sim/arch_test_target/spike/link.ld new file mode 100644 index 0000000000..8ad95e049b --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/arch_test_target/spike/link.ld @@ -0,0 +1,18 @@ +OUTPUT_ARCH( "riscv" ) +ENTRY(rvtest_entry_point) + +SECTIONS +{ + . = 0x80000000; + .text.init : { *(.text.init) } + . = ALIGN(0x1000); + .tohost : { *(.tohost) } + . = ALIGN(0x1000); + .text : { *(.text) } + . = ALIGN(0x1000); + .data : { *(.data) } + .data.string : { *(.data.string)} + .bss : { *(.bss) } + _end = .; +} + diff --git a/vendor/riscv/riscv-isa-sim/arch_test_target/spike/model_test.h b/vendor/riscv/riscv-isa-sim/arch_test_target/spike/model_test.h new file mode 100644 index 0000000000..e968e43aa8 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/arch_test_target/spike/model_test.h @@ -0,0 +1,66 @@ +#ifndef _COMPLIANCE_MODEL_H +#define _COMPLIANCE_MODEL_H + +#if XLEN == 64 + #define ALIGNMENT 3 +#else + #define ALIGNMENT 2 +#endif + +#define RVMODEL_DATA_SECTION \ + .pushsection .tohost,"aw",@progbits; \ + .align 8; .global tohost; tohost: .dword 0; \ + .align 8; .global fromhost; fromhost: .dword 0; \ + .popsection; \ + .align 8; .global begin_regstate; begin_regstate: \ + .word 128; \ + .align 8; .global end_regstate; end_regstate: \ + .word 4; + +//RV_COMPLIANCE_HALT +#define RVMODEL_HALT \ + addi x1, x1, 4; \ + li x1, 1; \ + write_tohost: \ + sw x1, tohost, t1; \ + self_loop: j self_loop; + +#define RVMODEL_BOOT + +//RV_COMPLIANCE_DATA_BEGIN +#define RVMODEL_DATA_BEGIN \ + .align 4; .global begin_signature; begin_signature: + +//RV_COMPLIANCE_DATA_END +#define RVMODEL_DATA_END \ + .align 4; .global end_signature; end_signature: \ + RVMODEL_DATA_SECTION \ + +//RVTEST_IO_INIT +#define RVMODEL_IO_INIT +//RVTEST_IO_WRITE_STR +#define RVMODEL_IO_WRITE_STR(_R, _STR) +//RVTEST_IO_CHECK +#define RVMODEL_IO_CHECK() +//RVTEST_IO_ASSERT_GPR_EQ +#define RVMODEL_IO_ASSERT_GPR_EQ(_S, _R, _I) +//RVTEST_IO_ASSERT_SFPR_EQ +#define RVMODEL_IO_ASSERT_SFPR_EQ(_F, _R, _I) +//RVTEST_IO_ASSERT_DFPR_EQ +#define RVMODEL_IO_ASSERT_DFPR_EQ(_D, _R, _I) + +#define RVMODEL_SET_MSW_INT \ + li t1, 1; \ + li t2, 0x2000000; \ + sw t1, 0(t2); + +#define RVMODEL_CLEAR_MSW_INT \ + li t2, 0x2000000; \ + sw x0, 0(t2); + +#define RVMODEL_CLEAR_MTIMER_INT + +#define RVMODEL_CLEAR_MEXT_INT + +#endif // _COMPLIANCE_MODEL_H + diff --git a/vendor/riscv/riscv-isa-sim/ax_append_flag.m4 b/vendor/riscv/riscv-isa-sim/ax_append_flag.m4 new file mode 100644 index 0000000000..dd6d8b6140 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/ax_append_flag.m4 @@ -0,0 +1,50 @@ +# =========================================================================== +# https://www.gnu.org/software/autoconf-archive/ax_append_flag.html +# =========================================================================== +# +# SYNOPSIS +# +# AX_APPEND_FLAG(FLAG, [FLAGS-VARIABLE]) +# +# DESCRIPTION +# +# FLAG is appended to the FLAGS-VARIABLE shell variable, with a space +# added in between. +# +# If FLAGS-VARIABLE is not specified, the current language's flags (e.g. +# CFLAGS) is used. FLAGS-VARIABLE is not changed if it already contains +# FLAG. If FLAGS-VARIABLE is unset in the shell, it is set to exactly +# FLAG. +# +# NOTE: Implementation based on AX_CFLAGS_GCC_OPTION. +# +# LICENSE +# +# Copyright (c) 2008 Guido U. Draheim <guidod@gmx.de> +# Copyright (c) 2011 Maarten Bosmans <mkbosmans@gmail.com> +# +# Copying and distribution of this file, with or without modification, are +# permitted in any medium without royalty provided the copyright notice +# and this notice are preserved. This file is offered as-is, without any +# warranty. + +#serial 8 + +AC_DEFUN([AX_APPEND_FLAG], +[dnl +AC_PREREQ(2.64)dnl for _AC_LANG_PREFIX and AS_VAR_SET_IF +AS_VAR_PUSHDEF([FLAGS], [m4_default($2,_AC_LANG_PREFIX[FLAGS])]) +AS_VAR_SET_IF(FLAGS,[ + AS_CASE([" AS_VAR_GET(FLAGS) "], + [*" $1 "*], [AC_RUN_LOG([: FLAGS already contains $1])], + [ + AS_VAR_APPEND(FLAGS,[" $1"]) + AC_RUN_LOG([: FLAGS="$FLAGS"]) + ]) + ], + [ + AS_VAR_SET(FLAGS,[$1]) + AC_RUN_LOG([: FLAGS="$FLAGS"]) + ]) +AS_VAR_POPDEF([FLAGS])dnl +])dnl AX_APPEND_FLAG diff --git a/vendor/riscv/riscv-isa-sim/ax_append_link_flags.m4 b/vendor/riscv/riscv-isa-sim/ax_append_link_flags.m4 new file mode 100644 index 0000000000..99b9fa5b4e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/ax_append_link_flags.m4 @@ -0,0 +1,44 @@ +# =========================================================================== +# https://www.gnu.org/software/autoconf-archive/ax_append_link_flags.html +# =========================================================================== +# +# SYNOPSIS +# +# AX_APPEND_LINK_FLAGS([FLAG1 FLAG2 ...], [FLAGS-VARIABLE], [EXTRA-FLAGS], [INPUT]) +# +# DESCRIPTION +# +# For every FLAG1, FLAG2 it is checked whether the linker works with the +# flag. If it does, the flag is added FLAGS-VARIABLE +# +# If FLAGS-VARIABLE is not specified, the linker's flags (LDFLAGS) is +# used. During the check the flag is always added to the linker's flags. +# +# If EXTRA-FLAGS is defined, it is added to the linker's default flags +# when the check is done. The check is thus made with the flags: "LDFLAGS +# EXTRA-FLAGS FLAG". This can for example be used to force the linker to +# issue an error when a bad flag is given. +# +# INPUT gives an alternative input source to AC_COMPILE_IFELSE. +# +# NOTE: This macro depends on the AX_APPEND_FLAG and AX_CHECK_LINK_FLAG. +# Please keep this macro in sync with AX_APPEND_COMPILE_FLAGS. +# +# LICENSE +# +# Copyright (c) 2011 Maarten Bosmans <mkbosmans@gmail.com> +# +# Copying and distribution of this file, with or without modification, are +# permitted in any medium without royalty provided the copyright notice +# and this notice are preserved. This file is offered as-is, without any +# warranty. + +#serial 7 + +AC_DEFUN([AX_APPEND_LINK_FLAGS], +[AX_REQUIRE_DEFINED([AX_CHECK_LINK_FLAG]) +AX_REQUIRE_DEFINED([AX_APPEND_FLAG]) +for flag in $1; do + AX_CHECK_LINK_FLAG([$flag], [AX_APPEND_FLAG([$flag], [m4_default([$2], [LDFLAGS])])], [], [$3], [$4]) +done +])dnl AX_APPEND_LINK_FLAGS diff --git a/vendor/riscv/riscv-isa-sim/ax_boost_asio.m4 b/vendor/riscv/riscv-isa-sim/ax_boost_asio.m4 new file mode 100644 index 0000000000..4247b33cb6 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/ax_boost_asio.m4 @@ -0,0 +1,110 @@ +# =========================================================================== +# https://www.gnu.org/software/autoconf-archive/ax_boost_asio.html +# =========================================================================== +# +# SYNOPSIS +# +# AX_BOOST_ASIO +# +# DESCRIPTION +# +# Test for Asio library from the Boost C++ libraries. The macro requires a +# preceding call to AX_BOOST_BASE. Further documentation is available at +# <http://randspringer.de/boost/index.html>. +# +# This macro calls: +# +# AC_SUBST(BOOST_ASIO_LIB) +# +# And sets: +# +# HAVE_BOOST_ASIO +# +# LICENSE +# +# Copyright (c) 2008 Thomas Porschberg <thomas@randspringer.de> +# Copyright (c) 2008 Pete Greenwell <pete@mu.org> +# +# Copying and distribution of this file, with or without modification, are +# permitted in any medium without royalty provided the copyright notice +# and this notice are preserved. This file is offered as-is, without any +# warranty. + +#serial 18 + +AC_DEFUN([AX_BOOST_ASIO], +[ + AC_ARG_WITH([boost-asio], + AS_HELP_STRING([--with-boost-asio@<:@=special-lib@:>@], + [use the ASIO library from boost - it is possible to specify a certain library for the linker + e.g. --with-boost-asio=boost_system-gcc41-mt-1_34 ]), + [ + if test "$withval" = "no"; then + want_boost="no" + elif test "$withval" = "yes"; then + want_boost="yes" + ax_boost_user_asio_lib="" + else + want_boost="yes" + ax_boost_user_asio_lib="$withval" + fi + ], + [want_boost="yes"] + ) + + if test "x$want_boost" = "xyes"; then + AC_REQUIRE([AC_PROG_CC]) + CPPFLAGS_SAVED="$CPPFLAGS" + CPPFLAGS="$CPPFLAGS $BOOST_CPPFLAGS" + export CPPFLAGS + + LDFLAGS_SAVED="$LDFLAGS" + LDFLAGS="$LDFLAGS $BOOST_LDFLAGS" + export LDFLAGS + + AC_CACHE_CHECK(whether the Boost::ASIO library is available, + ax_cv_boost_asio, + [AC_LANG_PUSH([C++]) + AC_COMPILE_IFELSE([AC_LANG_PROGRAM([[ @%:@include <boost/asio.hpp> + ]], + [[ + + boost::asio::io_service io; + boost::system::error_code timer_result; + boost::asio::deadline_timer t(io); + t.cancel(); + io.run_one(); + return 0; + ]])], + ax_cv_boost_asio=yes, ax_cv_boost_asio=no) + AC_LANG_POP([C++]) + ]) + if test "x$ax_cv_boost_asio" = "xyes"; then + AC_DEFINE(HAVE_BOOST_ASIO,,[define if the Boost::ASIO library is available]) + BN=boost_system + BOOSTLIBDIR=`echo $BOOST_LDFLAGS | sed -e 's/@<:@^\/@:>@*//'` + if test "x$ax_boost_user_asio_lib" = "x"; then + for ax_lib in `ls $BOOSTLIBDIR/libboost_system*.so* $BOOSTLIBDIR/libboost_system*.dylib* $BOOSTLIBDIR/libboost_system*.a* 2>/dev/null | sed 's,.*/,,' | sed -e 's;^lib\(boost_system.*\)\.so.*$;\1;' -e 's;^lib\(boost_system.*\)\.dylib.*$;\1;' -e 's;^lib\(boost_system.*\)\.a.*$;\1;' ` ; do + AC_CHECK_LIB($ax_lib, main, [BOOST_ASIO_LIB="-l$ax_lib" AC_SUBST(BOOST_ASIO_LIB) link_thread="yes" break], + [link_thread="no"]) + done + else + for ax_lib in $ax_boost_user_asio_lib $BN-$ax_boost_user_asio_lib; do + AC_CHECK_LIB($ax_lib, main, + [BOOST_ASIO_LIB="-l$ax_lib" AC_SUBST(BOOST_ASIO_LIB) link_asio="yes" break], + [link_asio="no"]) + done + + fi + if test "x$ax_lib" = "x"; then + AC_MSG_ERROR(Could not find a version of the Boost::Asio library!) + fi + if test "x$link_asio" = "xno"; then + AC_MSG_ERROR(Could not link against $ax_lib !) + fi + fi + + CPPFLAGS="$CPPFLAGS_SAVED" + LDFLAGS="$LDFLAGS_SAVED" + fi +]) diff --git a/vendor/riscv/riscv-isa-sim/ax_boost_base.m4 b/vendor/riscv/riscv-isa-sim/ax_boost_base.m4 new file mode 100644 index 0000000000..519f1c9d27 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/ax_boost_base.m4 @@ -0,0 +1,303 @@ +# =========================================================================== +# https://www.gnu.org/software/autoconf-archive/ax_boost_base.html +# =========================================================================== +# +# SYNOPSIS +# +# AX_BOOST_BASE([MINIMUM-VERSION], [ACTION-IF-FOUND], [ACTION-IF-NOT-FOUND]) +# +# DESCRIPTION +# +# Test for the Boost C++ libraries of a particular version (or newer) +# +# If no path to the installed boost library is given the macro searchs +# under /usr, /usr/local, /opt and /opt/local and evaluates the +# $BOOST_ROOT environment variable. Further documentation is available at +# <http://randspringer.de/boost/index.html>. +# +# This macro calls: +# +# AC_SUBST(BOOST_CPPFLAGS) / AC_SUBST(BOOST_LDFLAGS) +# +# And sets: +# +# HAVE_BOOST +# +# LICENSE +# +# Copyright (c) 2008 Thomas Porschberg <thomas@randspringer.de> +# Copyright (c) 2009 Peter Adolphs +# +# Copying and distribution of this file, with or without modification, are +# permitted in any medium without royalty provided the copyright notice +# and this notice are preserved. This file is offered as-is, without any +# warranty. + +#serial 49 + +# example boost program (need to pass version) +m4_define([_AX_BOOST_BASE_PROGRAM], + [AC_LANG_PROGRAM([[ +#include <boost/version.hpp> +]],[[ +(void) ((void)sizeof(char[1 - 2*!!((BOOST_VERSION) < ($1))])); +]])]) + +AC_DEFUN([AX_BOOST_BASE], +[ +AC_ARG_WITH([boost], + [AS_HELP_STRING([--with-boost@<:@=ARG@:>@], + [use Boost library from a standard location (ARG=yes), + from the specified location (ARG=<path>), + or disable it (ARG=no) + @<:@ARG=yes@:>@ ])], + [ + AS_CASE([$withval], + [no],[want_boost="no";_AX_BOOST_BASE_boost_path=""], + [yes],[want_boost="yes";_AX_BOOST_BASE_boost_path=""], + [want_boost="yes";_AX_BOOST_BASE_boost_path="$withval"]) + ], + [want_boost="yes"]) + + +AC_ARG_WITH([boost-libdir], + [AS_HELP_STRING([--with-boost-libdir=LIB_DIR], + [Force given directory for boost libraries. + Note that this will override library path detection, + so use this parameter only if default library detection fails + and you know exactly where your boost libraries are located.])], + [ + AS_IF([test -d "$withval"], + [_AX_BOOST_BASE_boost_lib_path="$withval"], + [AC_MSG_ERROR([--with-boost-libdir expected directory name])]) + ], + [_AX_BOOST_BASE_boost_lib_path=""]) + +BOOST_LDFLAGS="" +BOOST_CPPFLAGS="" +AS_IF([test "x$want_boost" = "xyes"], + [_AX_BOOST_BASE_RUNDETECT([$1],[$2],[$3])]) +AC_SUBST(BOOST_CPPFLAGS) +AC_SUBST(BOOST_LDFLAGS) +]) + + +# convert a version string in $2 to numeric and affect to polymorphic var $1 +AC_DEFUN([_AX_BOOST_BASE_TONUMERICVERSION],[ + AS_IF([test "x$2" = "x"],[_AX_BOOST_BASE_TONUMERICVERSION_req="1.20.0"],[_AX_BOOST_BASE_TONUMERICVERSION_req="$2"]) + _AX_BOOST_BASE_TONUMERICVERSION_req_shorten=`expr $_AX_BOOST_BASE_TONUMERICVERSION_req : '\([[0-9]]*\.[[0-9]]*\)'` + _AX_BOOST_BASE_TONUMERICVERSION_req_major=`expr $_AX_BOOST_BASE_TONUMERICVERSION_req : '\([[0-9]]*\)'` + AS_IF([test "x$_AX_BOOST_BASE_TONUMERICVERSION_req_major" = "x"], + [AC_MSG_ERROR([You should at least specify libboost major version])]) + _AX_BOOST_BASE_TONUMERICVERSION_req_minor=`expr $_AX_BOOST_BASE_TONUMERICVERSION_req : '[[0-9]]*\.\([[0-9]]*\)'` + AS_IF([test "x$_AX_BOOST_BASE_TONUMERICVERSION_req_minor" = "x"], + [_AX_BOOST_BASE_TONUMERICVERSION_req_minor="0"]) + _AX_BOOST_BASE_TONUMERICVERSION_req_sub_minor=`expr $_AX_BOOST_BASE_TONUMERICVERSION_req : '[[0-9]]*\.[[0-9]]*\.\([[0-9]]*\)'` + AS_IF([test "X$_AX_BOOST_BASE_TONUMERICVERSION_req_sub_minor" = "X"], + [_AX_BOOST_BASE_TONUMERICVERSION_req_sub_minor="0"]) + _AX_BOOST_BASE_TONUMERICVERSION_RET=`expr $_AX_BOOST_BASE_TONUMERICVERSION_req_major \* 100000 \+ $_AX_BOOST_BASE_TONUMERICVERSION_req_minor \* 100 \+ $_AX_BOOST_BASE_TONUMERICVERSION_req_sub_minor` + AS_VAR_SET($1,$_AX_BOOST_BASE_TONUMERICVERSION_RET) +]) + +dnl Run the detection of boost should be run only if $want_boost +AC_DEFUN([_AX_BOOST_BASE_RUNDETECT],[ + _AX_BOOST_BASE_TONUMERICVERSION(WANT_BOOST_VERSION,[$1]) + succeeded=no + + + AC_REQUIRE([AC_CANONICAL_HOST]) + dnl On 64-bit systems check for system libraries in both lib64 and lib. + dnl The former is specified by FHS, but e.g. Debian does not adhere to + dnl this (as it rises problems for generic multi-arch support). + dnl The last entry in the list is chosen by default when no libraries + dnl are found, e.g. when only header-only libraries are installed! + AS_CASE([${host_cpu}], + [x86_64],[libsubdirs="lib64 libx32 lib lib64"], + [mips*64*],[libsubdirs="lib64 lib32 lib lib64"], + [ppc64|powerpc64|s390x|sparc64|aarch64|ppc64le|powerpc64le|riscv64|e2k],[libsubdirs="lib64 lib lib64"], + [libsubdirs="lib"] + ) + + dnl allow for real multi-arch paths e.g. /usr/lib/x86_64-linux-gnu. Give + dnl them priority over the other paths since, if libs are found there, they + dnl are almost assuredly the ones desired. + AS_CASE([${host_cpu}], + [i?86],[multiarch_libsubdir="lib/i386-${host_os}"], + [armv7l],[multiarch_libsubdir="lib/arm-${host_os}"], + [multiarch_libsubdir="lib/${host_cpu}-${host_os}"] + ) + + dnl first we check the system location for boost libraries + dnl this location ist chosen if boost libraries are installed with the --layout=system option + dnl or if you install boost with RPM + AS_IF([test "x$_AX_BOOST_BASE_boost_path" != "x"],[ + AC_MSG_CHECKING([for boostlib >= $1 ($WANT_BOOST_VERSION) includes in "$_AX_BOOST_BASE_boost_path/include"]) + AS_IF([test -d "$_AX_BOOST_BASE_boost_path/include" && test -r "$_AX_BOOST_BASE_boost_path/include"],[ + AC_MSG_RESULT([yes]) + BOOST_CPPFLAGS="-I$_AX_BOOST_BASE_boost_path/include" + for _AX_BOOST_BASE_boost_path_tmp in $multiarch_libsubdir $libsubdirs; do + AC_MSG_CHECKING([for boostlib >= $1 ($WANT_BOOST_VERSION) lib path in "$_AX_BOOST_BASE_boost_path/$_AX_BOOST_BASE_boost_path_tmp"]) + AS_IF([test -d "$_AX_BOOST_BASE_boost_path/$_AX_BOOST_BASE_boost_path_tmp" && test -r "$_AX_BOOST_BASE_boost_path/$_AX_BOOST_BASE_boost_path_tmp" ],[ + AC_MSG_RESULT([yes]) + BOOST_LDFLAGS="-L$_AX_BOOST_BASE_boost_path/$_AX_BOOST_BASE_boost_path_tmp"; + break; + ], + [AC_MSG_RESULT([no])]) + done],[ + AC_MSG_RESULT([no])]) + ],[ + if test X"$cross_compiling" = Xyes; then + search_libsubdirs=$multiarch_libsubdir + else + search_libsubdirs="$multiarch_libsubdir $libsubdirs" + fi + for _AX_BOOST_BASE_boost_path_tmp in /usr /usr/local /opt /opt/local ; do + if test -d "$_AX_BOOST_BASE_boost_path_tmp/include/boost" && test -r "$_AX_BOOST_BASE_boost_path_tmp/include/boost" ; then + for libsubdir in $search_libsubdirs ; do + if ls "$_AX_BOOST_BASE_boost_path_tmp/$libsubdir/libboost_"* >/dev/null 2>&1 ; then break; fi + done + BOOST_LDFLAGS="-L$_AX_BOOST_BASE_boost_path_tmp/$libsubdir" + BOOST_CPPFLAGS="-I$_AX_BOOST_BASE_boost_path_tmp/include" + break; + fi + done + ]) + + dnl overwrite ld flags if we have required special directory with + dnl --with-boost-libdir parameter + AS_IF([test "x$_AX_BOOST_BASE_boost_lib_path" != "x"], + [BOOST_LDFLAGS="-L$_AX_BOOST_BASE_boost_lib_path"]) + + AC_MSG_CHECKING([for boostlib >= $1 ($WANT_BOOST_VERSION)]) + CPPFLAGS_SAVED="$CPPFLAGS" + CPPFLAGS="$CPPFLAGS $BOOST_CPPFLAGS" + export CPPFLAGS + + LDFLAGS_SAVED="$LDFLAGS" + LDFLAGS="$LDFLAGS $BOOST_LDFLAGS" + export LDFLAGS + + AC_REQUIRE([AC_PROG_CXX]) + AC_LANG_PUSH(C++) + AC_COMPILE_IFELSE([_AX_BOOST_BASE_PROGRAM($WANT_BOOST_VERSION)],[ + AC_MSG_RESULT(yes) + succeeded=yes + found_system=yes + ],[ + ]) + AC_LANG_POP([C++]) + + + + dnl if we found no boost with system layout we search for boost libraries + dnl built and installed without the --layout=system option or for a staged(not installed) version + if test "x$succeeded" != "xyes" ; then + CPPFLAGS="$CPPFLAGS_SAVED" + LDFLAGS="$LDFLAGS_SAVED" + BOOST_CPPFLAGS= + if test -z "$_AX_BOOST_BASE_boost_lib_path" ; then + BOOST_LDFLAGS= + fi + _version=0 + if test -n "$_AX_BOOST_BASE_boost_path" ; then + if test -d "$_AX_BOOST_BASE_boost_path" && test -r "$_AX_BOOST_BASE_boost_path"; then + for i in `ls -d $_AX_BOOST_BASE_boost_path/include/boost-* 2>/dev/null`; do + _version_tmp=`echo $i | sed "s#$_AX_BOOST_BASE_boost_path##" | sed 's/\/include\/boost-//' | sed 's/_/./'` + V_CHECK=`expr $_version_tmp \> $_version` + if test "x$V_CHECK" = "x1" ; then + _version=$_version_tmp + fi + VERSION_UNDERSCORE=`echo $_version | sed 's/\./_/'` + BOOST_CPPFLAGS="-I$_AX_BOOST_BASE_boost_path/include/boost-$VERSION_UNDERSCORE" + done + dnl if nothing found search for layout used in Windows distributions + if test -z "$BOOST_CPPFLAGS"; then + if test -d "$_AX_BOOST_BASE_boost_path/boost" && test -r "$_AX_BOOST_BASE_boost_path/boost"; then + BOOST_CPPFLAGS="-I$_AX_BOOST_BASE_boost_path" + fi + fi + dnl if we found something and BOOST_LDFLAGS was unset before + dnl (because "$_AX_BOOST_BASE_boost_lib_path" = ""), set it here. + if test -n "$BOOST_CPPFLAGS" && test -z "$BOOST_LDFLAGS"; then + for libsubdir in $libsubdirs ; do + if ls "$_AX_BOOST_BASE_boost_path/$libsubdir/libboost_"* >/dev/null 2>&1 ; then break; fi + done + BOOST_LDFLAGS="-L$_AX_BOOST_BASE_boost_path/$libsubdir" + fi + fi + else + if test "x$cross_compiling" != "xyes" ; then + for _AX_BOOST_BASE_boost_path in /usr /usr/local /opt /opt/local ; do + if test -d "$_AX_BOOST_BASE_boost_path" && test -r "$_AX_BOOST_BASE_boost_path" ; then + for i in `ls -d $_AX_BOOST_BASE_boost_path/include/boost-* 2>/dev/null`; do + _version_tmp=`echo $i | sed "s#$_AX_BOOST_BASE_boost_path##" | sed 's/\/include\/boost-//' | sed 's/_/./'` + V_CHECK=`expr $_version_tmp \> $_version` + if test "x$V_CHECK" = "x1" ; then + _version=$_version_tmp + best_path=$_AX_BOOST_BASE_boost_path + fi + done + fi + done + + VERSION_UNDERSCORE=`echo $_version | sed 's/\./_/'` + BOOST_CPPFLAGS="-I$best_path/include/boost-$VERSION_UNDERSCORE" + if test -z "$_AX_BOOST_BASE_boost_lib_path" ; then + for libsubdir in $libsubdirs ; do + if ls "$best_path/$libsubdir/libboost_"* >/dev/null 2>&1 ; then break; fi + done + BOOST_LDFLAGS="-L$best_path/$libsubdir" + fi + fi + + if test -n "$BOOST_ROOT" ; then + for libsubdir in $libsubdirs ; do + if ls "$BOOST_ROOT/stage/$libsubdir/libboost_"* >/dev/null 2>&1 ; then break; fi + done + if test -d "$BOOST_ROOT" && test -r "$BOOST_ROOT" && test -d "$BOOST_ROOT/stage/$libsubdir" && test -r "$BOOST_ROOT/stage/$libsubdir"; then + version_dir=`expr //$BOOST_ROOT : '.*/\(.*\)'` + stage_version=`echo $version_dir | sed 's/boost_//' | sed 's/_/./g'` + stage_version_shorten=`expr $stage_version : '\([[0-9]]*\.[[0-9]]*\)'` + V_CHECK=`expr $stage_version_shorten \>\= $_version` + if test "x$V_CHECK" = "x1" && test -z "$_AX_BOOST_BASE_boost_lib_path" ; then + AC_MSG_NOTICE(We will use a staged boost library from $BOOST_ROOT) + BOOST_CPPFLAGS="-I$BOOST_ROOT" + BOOST_LDFLAGS="-L$BOOST_ROOT/stage/$libsubdir" + fi + fi + fi + fi + + CPPFLAGS="$CPPFLAGS $BOOST_CPPFLAGS" + export CPPFLAGS + LDFLAGS="$LDFLAGS $BOOST_LDFLAGS" + export LDFLAGS + + AC_LANG_PUSH(C++) + AC_COMPILE_IFELSE([_AX_BOOST_BASE_PROGRAM($WANT_BOOST_VERSION)],[ + AC_MSG_RESULT(yes) + succeeded=yes + found_system=yes + ],[ + ]) + AC_LANG_POP([C++]) + fi + + if test "x$succeeded" != "xyes" ; then + if test "x$_version" = "x0" ; then + AC_MSG_NOTICE([[We could not detect the boost libraries (version $1 or higher). If you have a staged boost library (still not installed) please specify \$BOOST_ROOT in your environment and do not give a PATH to --with-boost option. If you are sure you have boost installed, then check your version number looking in <boost/version.hpp>. See http://randspringer.de/boost for more documentation.]]) + else + AC_MSG_NOTICE([Your boost libraries seems to old (version $_version).]) + fi + # execute ACTION-IF-NOT-FOUND (if present): + ifelse([$3], , :, [$3]) + else + AC_DEFINE(HAVE_BOOST,,[define if the Boost library is available]) + # execute ACTION-IF-FOUND (if present): + ifelse([$2], , :, [$2]) + fi + + CPPFLAGS="$CPPFLAGS_SAVED" + LDFLAGS="$LDFLAGS_SAVED" + +]) diff --git a/vendor/riscv/riscv-isa-sim/ax_boost_regex.m4 b/vendor/riscv/riscv-isa-sim/ax_boost_regex.m4 new file mode 100644 index 0000000000..e2413c24fe --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/ax_boost_regex.m4 @@ -0,0 +1,111 @@ +# =========================================================================== +# https://www.gnu.org/software/autoconf-archive/ax_boost_regex.html +# =========================================================================== +# +# SYNOPSIS +# +# AX_BOOST_REGEX +# +# DESCRIPTION +# +# Test for Regex library from the Boost C++ libraries. The macro requires +# a preceding call to AX_BOOST_BASE. Further documentation is available at +# <http://randspringer.de/boost/index.html>. +# +# This macro calls: +# +# AC_SUBST(BOOST_REGEX_LIB) +# +# And sets: +# +# HAVE_BOOST_REGEX +# +# LICENSE +# +# Copyright (c) 2008 Thomas Porschberg <thomas@randspringer.de> +# Copyright (c) 2008 Michael Tindal +# +# Copying and distribution of this file, with or without modification, are +# permitted in any medium without royalty provided the copyright notice +# and this notice are preserved. This file is offered as-is, without any +# warranty. + +#serial 23 + +AC_DEFUN([AX_BOOST_REGEX], +[ + AC_ARG_WITH([boost-regex], + AS_HELP_STRING([--with-boost-regex@<:@=special-lib@:>@], + [use the Regex library from boost - it is possible to specify a certain library for the linker + e.g. --with-boost-regex=boost_regex-gcc-mt-d-1_33_1 ]), + [ + if test "$withval" = "no"; then + want_boost="no" + elif test "$withval" = "yes"; then + want_boost="yes" + ax_boost_user_regex_lib="" + else + want_boost="yes" + ax_boost_user_regex_lib="$withval" + fi + ], + [want_boost="yes"] + ) + + if test "x$want_boost" = "xyes"; then + AC_REQUIRE([AC_PROG_CC]) + CPPFLAGS_SAVED="$CPPFLAGS" + CPPFLAGS="$CPPFLAGS $BOOST_CPPFLAGS" + export CPPFLAGS + + LDFLAGS_SAVED="$LDFLAGS" + LDFLAGS="$LDFLAGS $BOOST_LDFLAGS" + export LDFLAGS + + AC_CACHE_CHECK(whether the Boost::Regex library is available, + ax_cv_boost_regex, + [AC_LANG_PUSH([C++]) + AC_COMPILE_IFELSE([AC_LANG_PROGRAM([[@%:@include <boost/regex.hpp> + ]], + [[boost::regex r(); return 0;]])], + ax_cv_boost_regex=yes, ax_cv_boost_regex=no) + AC_LANG_POP([C++]) + ]) + if test "x$ax_cv_boost_regex" = "xyes"; then + AC_DEFINE(HAVE_BOOST_REGEX,,[define if the Boost::Regex library is available]) + BOOSTLIBDIR=`echo $BOOST_LDFLAGS | sed -e 's/@<:@^\/@:>@*//'` + if test "x$ax_boost_user_regex_lib" = "x"; then + for libextension in `ls $BOOSTLIBDIR/libboost_regex*.so* $BOOSTLIBDIR/libboost_regex*.dylib* $BOOSTLIBDIR/libboost_regex*.a* 2>/dev/null | sed 's,.*/,,' | sed -e 's;^lib\(boost_regex.*\)\.so.*$;\1;' -e 's;^lib\(boost_regex.*\)\.dylib.*;\1;' -e 's;^lib\(boost_regex.*\)\.a.*$;\1;'` ; do + ax_lib=${libextension} + AC_CHECK_LIB($ax_lib, exit, + [BOOST_REGEX_LIB="-l$ax_lib"; AC_SUBST(BOOST_REGEX_LIB) link_regex="yes"; break], + [link_regex="no"]) + done + if test "x$link_regex" != "xyes"; then + for libextension in `ls $BOOSTLIBDIR/boost_regex*.dll* $BOOSTLIBDIR/boost_regex*.a* 2>/dev/null | sed 's,.*/,,' | sed -e 's;^\(boost_regex.*\)\.dll.*$;\1;' -e 's;^\(boost_regex.*\)\.a.*$;\1;'` ; do + ax_lib=${libextension} + AC_CHECK_LIB($ax_lib, exit, + [BOOST_REGEX_LIB="-l$ax_lib"; AC_SUBST(BOOST_REGEX_LIB) link_regex="yes"; break], + [link_regex="no"]) + done + fi + + else + for ax_lib in $ax_boost_user_regex_lib boost_regex-$ax_boost_user_regex_lib; do + AC_CHECK_LIB($ax_lib, main, + [BOOST_REGEX_LIB="-l$ax_lib"; AC_SUBST(BOOST_REGEX_LIB) link_regex="yes"; break], + [link_regex="no"]) + done + fi + if test "x$ax_lib" = "x"; then + AC_MSG_ERROR(Could not find a version of the Boost::Regex library!) + fi + if test "x$link_regex" != "xyes"; then + AC_MSG_ERROR(Could not link against $ax_lib !) + fi + fi + + CPPFLAGS="$CPPFLAGS_SAVED" + LDFLAGS="$LDFLAGS_SAVED" + fi +]) diff --git a/vendor/riscv/riscv-isa-sim/ax_check_compile_flag.m4 b/vendor/riscv/riscv-isa-sim/ax_check_compile_flag.m4 new file mode 100644 index 0000000000..bd753b34d7 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/ax_check_compile_flag.m4 @@ -0,0 +1,53 @@ +# =========================================================================== +# https://www.gnu.org/software/autoconf-archive/ax_check_compile_flag.html +# =========================================================================== +# +# SYNOPSIS +# +# AX_CHECK_COMPILE_FLAG(FLAG, [ACTION-SUCCESS], [ACTION-FAILURE], [EXTRA-FLAGS], [INPUT]) +# +# DESCRIPTION +# +# Check whether the given FLAG works with the current language's compiler +# or gives an error. (Warnings, however, are ignored) +# +# ACTION-SUCCESS/ACTION-FAILURE are shell commands to execute on +# success/failure. +# +# If EXTRA-FLAGS is defined, it is added to the current language's default +# flags (e.g. CFLAGS) when the check is done. The check is thus made with +# the flags: "CFLAGS EXTRA-FLAGS FLAG". This can for example be used to +# force the compiler to issue an error when a bad flag is given. +# +# INPUT gives an alternative input source to AC_COMPILE_IFELSE. +# +# NOTE: Implementation based on AX_CFLAGS_GCC_OPTION. Please keep this +# macro in sync with AX_CHECK_{PREPROC,LINK}_FLAG. +# +# LICENSE +# +# Copyright (c) 2008 Guido U. Draheim <guidod@gmx.de> +# Copyright (c) 2011 Maarten Bosmans <mkbosmans@gmail.com> +# +# Copying and distribution of this file, with or without modification, are +# permitted in any medium without royalty provided the copyright notice +# and this notice are preserved. This file is offered as-is, without any +# warranty. + +#serial 6 + +AC_DEFUN([AX_CHECK_COMPILE_FLAG], +[AC_PREREQ(2.64)dnl for _AC_LANG_PREFIX and AS_VAR_IF +AS_VAR_PUSHDEF([CACHEVAR],[ax_cv_check_[]_AC_LANG_ABBREV[]flags_$4_$1])dnl +AC_CACHE_CHECK([whether _AC_LANG compiler accepts $1], CACHEVAR, [ + ax_check_save_flags=$[]_AC_LANG_PREFIX[]FLAGS + _AC_LANG_PREFIX[]FLAGS="$[]_AC_LANG_PREFIX[]FLAGS $4 $1" + AC_COMPILE_IFELSE([m4_default([$5],[AC_LANG_PROGRAM()])], + [AS_VAR_SET(CACHEVAR,[yes])], + [AS_VAR_SET(CACHEVAR,[no])]) + _AC_LANG_PREFIX[]FLAGS=$ax_check_save_flags]) +AS_VAR_IF(CACHEVAR,yes, + [m4_default([$2], :)], + [m4_default([$3], :)]) +AS_VAR_POPDEF([CACHEVAR])dnl +])dnl AX_CHECK_COMPILE_FLAGS diff --git a/vendor/riscv/riscv-isa-sim/ax_check_link_flag.m4 b/vendor/riscv/riscv-isa-sim/ax_check_link_flag.m4 new file mode 100644 index 0000000000..03a30ce4c7 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/ax_check_link_flag.m4 @@ -0,0 +1,53 @@ +# =========================================================================== +# https://www.gnu.org/software/autoconf-archive/ax_check_link_flag.html +# =========================================================================== +# +# SYNOPSIS +# +# AX_CHECK_LINK_FLAG(FLAG, [ACTION-SUCCESS], [ACTION-FAILURE], [EXTRA-FLAGS], [INPUT]) +# +# DESCRIPTION +# +# Check whether the given FLAG works with the linker or gives an error. +# (Warnings, however, are ignored) +# +# ACTION-SUCCESS/ACTION-FAILURE are shell commands to execute on +# success/failure. +# +# If EXTRA-FLAGS is defined, it is added to the linker's default flags +# when the check is done. The check is thus made with the flags: "LDFLAGS +# EXTRA-FLAGS FLAG". This can for example be used to force the linker to +# issue an error when a bad flag is given. +# +# INPUT gives an alternative input source to AC_LINK_IFELSE. +# +# NOTE: Implementation based on AX_CFLAGS_GCC_OPTION. Please keep this +# macro in sync with AX_CHECK_{PREPROC,COMPILE}_FLAG. +# +# LICENSE +# +# Copyright (c) 2008 Guido U. Draheim <guidod@gmx.de> +# Copyright (c) 2011 Maarten Bosmans <mkbosmans@gmail.com> +# +# Copying and distribution of this file, with or without modification, are +# permitted in any medium without royalty provided the copyright notice +# and this notice are preserved. This file is offered as-is, without any +# warranty. + +#serial 6 + +AC_DEFUN([AX_CHECK_LINK_FLAG], +[AC_PREREQ(2.64)dnl for _AC_LANG_PREFIX and AS_VAR_IF +AS_VAR_PUSHDEF([CACHEVAR],[ax_cv_check_ldflags_$4_$1])dnl +AC_CACHE_CHECK([whether the linker accepts $1], CACHEVAR, [ + ax_check_save_flags=$LDFLAGS + LDFLAGS="$LDFLAGS $4 $1" + AC_LINK_IFELSE([m4_default([$5],[AC_LANG_PROGRAM()])], + [AS_VAR_SET(CACHEVAR,[yes])], + [AS_VAR_SET(CACHEVAR,[no])]) + LDFLAGS=$ax_check_save_flags]) +AS_VAR_IF(CACHEVAR,yes, + [m4_default([$2], :)], + [m4_default([$3], :)]) +AS_VAR_POPDEF([CACHEVAR])dnl +])dnl AX_CHECK_LINK_FLAGS diff --git a/vendor/riscv/riscv-isa-sim/ax_require_defined.m4 b/vendor/riscv/riscv-isa-sim/ax_require_defined.m4 new file mode 100644 index 0000000000..17c3eab7da --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/ax_require_defined.m4 @@ -0,0 +1,37 @@ +# =========================================================================== +# https://www.gnu.org/software/autoconf-archive/ax_require_defined.html +# =========================================================================== +# +# SYNOPSIS +# +# AX_REQUIRE_DEFINED(MACRO) +# +# DESCRIPTION +# +# AX_REQUIRE_DEFINED is a simple helper for making sure other macros have +# been defined and thus are available for use. This avoids random issues +# where a macro isn't expanded. Instead the configure script emits a +# non-fatal: +# +# ./configure: line 1673: AX_CFLAGS_WARN_ALL: command not found +# +# It's like AC_REQUIRE except it doesn't expand the required macro. +# +# Here's an example: +# +# AX_REQUIRE_DEFINED([AX_CHECK_LINK_FLAG]) +# +# LICENSE +# +# Copyright (c) 2014 Mike Frysinger <vapier@gentoo.org> +# +# Copying and distribution of this file, with or without modification, are +# permitted in any medium without royalty provided the copyright notice +# and this notice are preserved. This file is offered as-is, without any +# warranty. + +#serial 2 + +AC_DEFUN([AX_REQUIRE_DEFINED], [dnl + m4_ifndef([$1], [m4_fatal([macro ]$1[ is not defined; is a m4 file missing?])]) +])dnl AX_REQUIRE_DEFINED diff --git a/vendor/riscv/riscv-isa-sim/config.h.in b/vendor/riscv/riscv-isa-sim/config.h.in new file mode 100644 index 0000000000..f6755a1dd8 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/config.h.in @@ -0,0 +1,133 @@ +/* config.h.in. Generated from configure.ac by autoheader. */ + +/* Define if building universal (internal helper macro) */ +#undef AC_APPLE_UNIVERSAL_BUILD + +/* Define if subproject MCPPBS_SPROJ_NORM is enabled */ +#undef CUSTOMEXT_ENABLED + +/* Default value for --isa switch */ +#undef DEFAULT_ISA + +/* Default value for --priv switch */ +#undef DEFAULT_PRIV + +/* Default value for --varch switch */ +#undef DEFAULT_VARCH + +/* Define if subproject MCPPBS_SPROJ_NORM is enabled */ +#undef DISASM_ENABLED + +/* Executable name of device-tree-compiler */ +#undef DTC + +/* Define if subproject MCPPBS_SPROJ_NORM is enabled */ +#undef FDT_ENABLED + +/* Define if subproject MCPPBS_SPROJ_NORM is enabled */ +#undef FESVR_ENABLED + +/* define if the Boost library is available */ +#undef HAVE_BOOST + +/* define if the Boost::ASIO library is available */ +#undef HAVE_BOOST_ASIO + +/* define if the Boost::Regex library is available */ +#undef HAVE_BOOST_REGEX + +/* Dynamic library loading is supported */ +#undef HAVE_DLOPEN + +/* Define to 1 if you have the <inttypes.h> header file. */ +#undef HAVE_INTTYPES_H + +/* Define to 1 if you have the `boost_regex' library (-lboost_regex). */ +#undef HAVE_LIBBOOST_REGEX + +/* Define to 1 if you have the `boost_system' library (-lboost_system). */ +#undef HAVE_LIBBOOST_SYSTEM + +/* Define to 1 if you have the `pthread' library (-lpthread). */ +#undef HAVE_LIBPTHREAD + +/* Define to 1 if you have the <memory.h> header file. */ +#undef HAVE_MEMORY_H + +/* Define to 1 if struct statx exists. */ +#undef HAVE_STATX + +/* Define to 1 if struct statx has stx_mnt_id. */ +#undef HAVE_STATX_MNT_ID + +/* Define to 1 if you have the <stdint.h> header file. */ +#undef HAVE_STDINT_H + +/* Define to 1 if you have the <stdlib.h> header file. */ +#undef HAVE_STDLIB_H + +/* Define to 1 if you have the <strings.h> header file. */ +#undef HAVE_STRINGS_H + +/* Define to 1 if you have the <string.h> header file. */ +#undef HAVE_STRING_H + +/* Define to 1 if you have the <sys/stat.h> header file. */ +#undef HAVE_SYS_STAT_H + +/* Define to 1 if you have the <sys/types.h> header file. */ +#undef HAVE_SYS_TYPES_H + +/* Define to 1 if you have the <unistd.h> header file. */ +#undef HAVE_UNISTD_H + +/* Define to the address where bug reports for this package should be sent. */ +#undef PACKAGE_BUGREPORT + +/* Define to the full name of this package. */ +#undef PACKAGE_NAME + +/* Define to the full name and version of this package. */ +#undef PACKAGE_STRING + +/* Define to the one symbol short name of this package. */ +#undef PACKAGE_TARNAME + +/* Define to the home page for this package. */ +#undef PACKAGE_URL + +/* Define to the version of this package. */ +#undef PACKAGE_VERSION + +/* Define if subproject MCPPBS_SPROJ_NORM is enabled */ +#undef RISCV_ENABLED + +/* Enable support for running target in either endianness */ +#undef RISCV_ENABLE_DUAL_ENDIAN + +/* Define if subproject MCPPBS_SPROJ_NORM is enabled */ +#undef SOFTFLOAT_ENABLED + +/* Define if subproject MCPPBS_SPROJ_NORM is enabled */ +#undef SPIKE_DASM_ENABLED + +/* Define if subproject MCPPBS_SPROJ_NORM is enabled */ +#undef SPIKE_MAIN_ENABLED + +/* Define to 1 if you have the ANSI C header files. */ +#undef STDC_HEADERS + +/* Default value for --target switch */ +#undef TARGET_ARCH + +/* Define WORDS_BIGENDIAN to 1 if your processor stores words with the most + significant byte first (like Motorola and SPARC, unlike Intel). */ +#if defined AC_APPLE_UNIVERSAL_BUILD +# if defined __BIG_ENDIAN__ +# define WORDS_BIGENDIAN 1 +# endif +#else +# ifndef WORDS_BIGENDIAN +# undef WORDS_BIGENDIAN +# endif +#endif diff --git a/vendor/riscv/riscv-isa-sim/configure b/vendor/riscv/riscv-isa-sim/configure new file mode 100755 index 0000000000..419132f75a --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/configure @@ -0,0 +1,7653 @@ +#! /bin/sh +# Guess values for system-dependent variables and create Makefiles. +# Generated by GNU Autoconf 2.69 for RISC-V ISA Simulator ?. +# +# Report bugs to <Andrew Waterman>. +# +# +# Copyright (C) 1992-1996, 1998-2012 Free Software Foundation, Inc. +# +# +# This configure script is free software; the Free Software Foundation +# gives unlimited permission to copy, distribute and modify it. +## -------------------- ## +## M4sh Initialization. ## +## -------------------- ## + +# Be more Bourne compatible +DUALCASE=1; export DUALCASE # for MKS sh +if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then : + emulate sh + NULLCMD=: + # Pre-4.2 versions of Zsh do word splitting on ${1+"$@"}, which + # is contrary to our usage. Disable this feature. + alias -g '${1+"$@"}'='"$@"' + setopt NO_GLOB_SUBST +else + case `(set -o) 2>/dev/null` in #( + *posix*) : + set -o posix ;; #( + *) : + ;; +esac +fi + + +as_nl=' +' +export as_nl +# Printing a long string crashes Solaris 7 /usr/bin/printf. +as_echo='\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\' +as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo +as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo$as_echo +# Prefer a ksh shell builtin over an external printf program on Solaris, +# but without wasting forks for bash or zsh. +if test -z "$BASH_VERSION$ZSH_VERSION" \ + && (test "X`print -r -- $as_echo`" = "X$as_echo") 2>/dev/null; then + as_echo='print -r --' + as_echo_n='print -rn --' +elif (test "X`printf %s $as_echo`" = "X$as_echo") 2>/dev/null; then + as_echo='printf %s\n' + as_echo_n='printf %s' +else + if test "X`(/usr/ucb/echo -n -n $as_echo) 2>/dev/null`" = "X-n $as_echo"; then + as_echo_body='eval /usr/ucb/echo -n "$1$as_nl"' + as_echo_n='/usr/ucb/echo -n' + else + as_echo_body='eval expr "X$1" : "X\\(.*\\)"' + as_echo_n_body='eval + arg=$1; + case $arg in #( + *"$as_nl"*) + expr "X$arg" : "X\\(.*\\)$as_nl"; + arg=`expr "X$arg" : ".*$as_nl\\(.*\\)"`;; + esac; + expr "X$arg" : "X\\(.*\\)" | tr -d "$as_nl" + ' + export as_echo_n_body + as_echo_n='sh -c $as_echo_n_body as_echo' + fi + export as_echo_body + as_echo='sh -c $as_echo_body as_echo' +fi + +# The user is always right. +if test "${PATH_SEPARATOR+set}" != set; then + PATH_SEPARATOR=: + (PATH='/bin;/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 && { + (PATH='/bin:/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 || + PATH_SEPARATOR=';' + } +fi + + +# IFS +# We need space, tab and new line, in precisely that order. Quoting is +# there to prevent editors from complaining about space-tab. +# (If _AS_PATH_WALK were called with IFS unset, it would disable word +# splitting by setting IFS to empty value.) +IFS=" "" $as_nl" + +# Find who we are. Look in the path if we contain no directory separator. +as_myself= +case $0 in #(( + *[\\/]* ) as_myself=$0 ;; + *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + test -r "$as_dir/$0" && as_myself=$as_dir/$0 && break + done +IFS=$as_save_IFS + + ;; +esac +# We did not find ourselves, most probably we were run as `sh COMMAND' +# in which case we are not to be found in the path. +if test "x$as_myself" = x; then + as_myself=$0 +fi +if test ! -f "$as_myself"; then + $as_echo "$as_myself: error: cannot find myself; rerun with an absolute file name" >&2 + exit 1 +fi + +# Unset variables that we do not need and which cause bugs (e.g. in +# pre-3.0 UWIN ksh). But do not cause bugs in bash 2.01; the "|| exit 1" +# suppresses any "Segmentation fault" message there. '((' could +# trigger a bug in pdksh 5.2.14. +for as_var in BASH_ENV ENV MAIL MAILPATH +do eval test x\${$as_var+set} = xset \ + && ( (unset $as_var) || exit 1) >/dev/null 2>&1 && unset $as_var || : +done +PS1='$ ' +PS2='> ' +PS4='+ ' + +# NLS nuisances. +LC_ALL=C +export LC_ALL +LANGUAGE=C +export LANGUAGE + +# CDPATH. +(unset CDPATH) >/dev/null 2>&1 && unset CDPATH + +# Use a proper internal environment variable to ensure we don't fall + # into an infinite loop, continuously re-executing ourselves. + if test x"${_as_can_reexec}" != xno && test "x$CONFIG_SHELL" != x; then + _as_can_reexec=no; export _as_can_reexec; + # We cannot yet assume a decent shell, so we have to provide a +# neutralization value for shells without unset; and this also +# works around shells that cannot unset nonexistent variables. +# Preserve -v and -x to the replacement shell. +BASH_ENV=/dev/null +ENV=/dev/null +(unset BASH_ENV) >/dev/null 2>&1 && unset BASH_ENV ENV +case $- in # (((( + *v*x* | *x*v* ) as_opts=-vx ;; + *v* ) as_opts=-v ;; + *x* ) as_opts=-x ;; + * ) as_opts= ;; +esac +exec $CONFIG_SHELL $as_opts "$as_myself" ${1+"$@"} +# Admittedly, this is quite paranoid, since all the known shells bail +# out after a failed `exec'. +$as_echo "$0: could not re-execute with $CONFIG_SHELL" >&2 +as_fn_exit 255 + fi + # We don't want this to propagate to other subprocesses. + { _as_can_reexec=; unset _as_can_reexec;} +if test "x$CONFIG_SHELL" = x; then + as_bourne_compatible="if test -n \"\${ZSH_VERSION+set}\" && (emulate sh) >/dev/null 2>&1; then : + emulate sh + NULLCMD=: + # Pre-4.2 versions of Zsh do word splitting on \${1+\"\$@\"}, which + # is contrary to our usage. Disable this feature. + alias -g '\${1+\"\$@\"}'='\"\$@\"' + setopt NO_GLOB_SUBST +else + case \`(set -o) 2>/dev/null\` in #( + *posix*) : + set -o posix ;; #( + *) : + ;; +esac +fi +" + as_required="as_fn_return () { (exit \$1); } +as_fn_success () { as_fn_return 0; } +as_fn_failure () { as_fn_return 1; } +as_fn_ret_success () { return 0; } +as_fn_ret_failure () { return 1; } + +exitcode=0 +as_fn_success || { exitcode=1; echo as_fn_success failed.; } +as_fn_failure && { exitcode=1; echo as_fn_failure succeeded.; } +as_fn_ret_success || { exitcode=1; echo as_fn_ret_success failed.; } +as_fn_ret_failure && { exitcode=1; echo as_fn_ret_failure succeeded.; } +if ( set x; as_fn_ret_success y && test x = \"\$1\" ); then : + +else + exitcode=1; echo positional parameters were not saved. +fi +test x\$exitcode = x0 || exit 1 +test -x / || exit 1" + as_suggested=" as_lineno_1=";as_suggested=$as_suggested$LINENO;as_suggested=$as_suggested" as_lineno_1a=\$LINENO + as_lineno_2=";as_suggested=$as_suggested$LINENO;as_suggested=$as_suggested" as_lineno_2a=\$LINENO + eval 'test \"x\$as_lineno_1'\$as_run'\" != \"x\$as_lineno_2'\$as_run'\" && + test \"x\`expr \$as_lineno_1'\$as_run' + 1\`\" = \"x\$as_lineno_2'\$as_run'\"' || exit 1 +test \$(( 1 + 1 )) = 2 || exit 1" + if (eval "$as_required") 2>/dev/null; then : + as_have_required=yes +else + as_have_required=no +fi + if test x$as_have_required = xyes && (eval "$as_suggested") 2>/dev/null; then : + +else + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +as_found=false +for as_dir in /bin$PATH_SEPARATOR/usr/bin$PATH_SEPARATOR$PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + as_found=: + case $as_dir in #( + /*) + for as_base in sh bash ksh sh5; do + # Try only shells that exist, to save several forks. + as_shell=$as_dir/$as_base + if { test -f "$as_shell" || test -f "$as_shell.exe"; } && + { $as_echo "$as_bourne_compatible""$as_required" | as_run=a "$as_shell"; } 2>/dev/null; then : + CONFIG_SHELL=$as_shell as_have_required=yes + if { $as_echo "$as_bourne_compatible""$as_suggested" | as_run=a "$as_shell"; } 2>/dev/null; then : + break 2 +fi +fi + done;; + esac + as_found=false +done +$as_found || { if { test -f "$SHELL" || test -f "$SHELL.exe"; } && + { $as_echo "$as_bourne_compatible""$as_required" | as_run=a "$SHELL"; } 2>/dev/null; then : + CONFIG_SHELL=$SHELL as_have_required=yes +fi; } +IFS=$as_save_IFS + + + if test "x$CONFIG_SHELL" != x; then : + export CONFIG_SHELL + # We cannot yet assume a decent shell, so we have to provide a +# neutralization value for shells without unset; and this also +# works around shells that cannot unset nonexistent variables. +# Preserve -v and -x to the replacement shell. +BASH_ENV=/dev/null +ENV=/dev/null +(unset BASH_ENV) >/dev/null 2>&1 && unset BASH_ENV ENV +case $- in # (((( + *v*x* | *x*v* ) as_opts=-vx ;; + *v* ) as_opts=-v ;; + *x* ) as_opts=-x ;; + * ) as_opts= ;; +esac +exec $CONFIG_SHELL $as_opts "$as_myself" ${1+"$@"} +# Admittedly, this is quite paranoid, since all the known shells bail +# out after a failed `exec'. +$as_echo "$0: could not re-execute with $CONFIG_SHELL" >&2 +exit 255 +fi + + if test x$as_have_required = xno; then : + $as_echo "$0: This script requires a shell more modern than all" + $as_echo "$0: the shells that I found on your system." + if test x${ZSH_VERSION+set} = xset ; then + $as_echo "$0: In particular, zsh $ZSH_VERSION has bugs and should" + $as_echo "$0: be upgraded to zsh 4.3.4 or later." + else + $as_echo "$0: Please tell bug-autoconf@gnu.org and Andrew Waterman +$0: about your system, including any error possibly output +$0: before this message. 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"cannot create directory $as_dir" + + +} # as_fn_mkdir_p + +# as_fn_executable_p FILE +# ----------------------- +# Test if FILE is an executable regular file. +as_fn_executable_p () +{ + test -f "$1" && test -x "$1" +} # as_fn_executable_p +# as_fn_append VAR VALUE +# ---------------------- +# Append the text in VALUE to the end of the definition contained in VAR. Take +# advantage of any shell optimizations that allow amortized linear growth over +# repeated appends, instead of the typical quadratic growth present in naive +# implementations. +if (eval "as_var=1; as_var+=2; test x\$as_var = x12") 2>/dev/null; then : + eval 'as_fn_append () + { + eval $1+=\$2 + }' +else + as_fn_append () + { + eval $1=\$$1\$2 + } +fi # as_fn_append + +# as_fn_arith ARG... +# ------------------ +# Perform arithmetic evaluation on the ARGs, and store the result in the +# global $as_val. Take advantage of shells that can avoid forks. The arguments +# must be portable across $(()) and expr. +if (eval "test \$(( 1 + 1 )) = 2") 2>/dev/null; then : + eval 'as_fn_arith () + { + as_val=$(( $* )) + }' +else + as_fn_arith () + { + as_val=`expr "$@" || test $? -eq 1` + } +fi # as_fn_arith + + +# as_fn_error STATUS ERROR [LINENO LOG_FD] +# ---------------------------------------- +# Output "`basename $0`: error: ERROR" to stderr. If LINENO and LOG_FD are +# provided, also output the error to LOG_FD, referencing LINENO. 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McMahon (1931-1989) for sed's syntax. :-) + sed -n ' + p + /[$]LINENO/= + ' <$as_myself | + sed ' + s/[$]LINENO.*/&-/ + t lineno + b + :lineno + N + :loop + s/[$]LINENO\([^'$as_cr_alnum'_].*\n\)\(.*\)/\2\1\2/ + t loop + s/-\n.*// + ' >$as_me.lineno && + chmod +x "$as_me.lineno" || + { $as_echo "$as_me: error: cannot create $as_me.lineno; rerun with a POSIX shell" >&2; as_fn_exit 1; } + + # If we had to re-execute with $CONFIG_SHELL, we're ensured to have + # already done that, so ensure we don't try to do so again and fall + # in an infinite loop. This has already happened in practice. + _as_can_reexec=no; export _as_can_reexec + # Don't try to exec as it changes $[0], causing all sort of problems + # (the dirname of $[0] is not the place where we might find the + # original and so on. Autoconf is especially sensitive to this). + . "./$as_me.lineno" + # Exit status is that of the last command. + exit +} + +ECHO_C= ECHO_N= ECHO_T= +case `echo -n x` in #((((( +-n*) + case `echo 'xy\c'` in + *c*) ECHO_T=' ';; # ECHO_T is single tab character. + xy) ECHO_C='\c';; + *) echo `echo ksh88 bug on AIX 6.1` > /dev/null + ECHO_T=' ';; + esac;; +*) + ECHO_N='-n';; +esac + +rm -f conf$$ conf$$.exe conf$$.file +if test -d conf$$.dir; then + rm -f conf$$.dir/conf$$.file +else + rm -f conf$$.dir + mkdir conf$$.dir 2>/dev/null +fi +if (echo >conf$$.file) 2>/dev/null; then + if ln -s conf$$.file conf$$ 2>/dev/null; then + as_ln_s='ln -s' + # ... but there are two gotchas: + # 1) On MSYS, both `ln -s file dir' and `ln file dir' fail. + # 2) DJGPP < 2.04 has no symlinks; `ln -s' creates a wrapper executable. + # In both cases, we have to default to `cp -pR'. + ln -s conf$$.file conf$$.dir 2>/dev/null && test ! -f conf$$.exe || + as_ln_s='cp -pR' + elif ln conf$$.file conf$$ 2>/dev/null; then + as_ln_s=ln + else + as_ln_s='cp -pR' + fi +else + as_ln_s='cp -pR' +fi +rm -f conf$$ conf$$.exe conf$$.dir/conf$$.file conf$$.file +rmdir conf$$.dir 2>/dev/null + +if mkdir -p . 2>/dev/null; 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[VAR=VALUE]... + +To assign environment variables (e.g., CC, CFLAGS...), specify them as +VAR=VALUE. See below for descriptions of some of the useful variables. + +Defaults for the options are specified in brackets. + +Configuration: + -h, --help display this help and exit + --help=short display options specific to this package + --help=recursive display the short help of all the included packages + -V, --version display version information and exit + -q, --quiet, --silent do not print \`checking ...' messages + --cache-file=FILE cache test results in FILE [disabled] + -C, --config-cache alias for \`--cache-file=config.cache' + -n, --no-create do not create output files + --srcdir=DIR find the sources in DIR [configure dir or \`..'] + +Installation directories: + --prefix=PREFIX install architecture-independent files in PREFIX + [$ac_default_prefix] + --exec-prefix=EPREFIX install architecture-dependent files in EPREFIX + [PREFIX] + +By default, \`make install' will install all the files in +\`$ac_default_prefix/bin', \`$ac_default_prefix/lib' etc. You can specify +an installation prefix other than \`$ac_default_prefix' using \`--prefix', +for instance \`--prefix=\$HOME'. + +For better control, use the options below. + +Fine tuning of the installation directories: + --bindir=DIR user executables [EPREFIX/bin] + --sbindir=DIR system admin executables [EPREFIX/sbin] + --libexecdir=DIR program executables [EPREFIX/libexec] + --sysconfdir=DIR read-only single-machine data [PREFIX/etc] + --sharedstatedir=DIR modifiable architecture-independent data [PREFIX/com] + --localstatedir=DIR modifiable single-machine data [PREFIX/var] + --runstatedir=DIR modifiable per-process data [LOCALSTATEDIR/run] + --libdir=DIR object code libraries [EPREFIX/lib] + --includedir=DIR C header files [PREFIX/include] + --oldincludedir=DIR C header files for non-gcc [/usr/include] + --datarootdir=DIR read-only arch.-independent data root [PREFIX/share] + --datadir=DIR read-only architecture-independent data [DATAROOTDIR] + --infodir=DIR info documentation [DATAROOTDIR/info] + --localedir=DIR locale-dependent data [DATAROOTDIR/locale] + --mandir=DIR man documentation [DATAROOTDIR/man] + --docdir=DIR documentation root [DATAROOTDIR/doc/spike] + --htmldir=DIR html documentation [DOCDIR] + --dvidir=DIR dvi documentation [DOCDIR] + --pdfdir=DIR pdf documentation [DOCDIR] + --psdir=DIR ps documentation [DOCDIR] +_ACEOF + + cat <<\_ACEOF + +System types: + --build=BUILD configure for building on BUILD [guessed] + --host=HOST cross-compile to build programs to run on HOST [BUILD] +_ACEOF +fi + +if test -n "$ac_init_help"; then + case $ac_init_help in + short | recursive ) echo "Configuration of RISC-V ISA Simulator ?:";; + esac + cat <<\_ACEOF + +Optional Features: + --disable-option-checking ignore unrecognized --enable/--with options + --disable-FEATURE do not include FEATURE (same as --enable-FEATURE=no) + --enable-FEATURE[=ARG] include FEATURE [ARG=yes] + --enable-stow Enable stow-based install + --enable-optional-subprojects + Enable all optional subprojects + --enable-dual-endian Enable support for running target in either + endianness + +Optional Packages: + --with-PACKAGE[=ARG] use PACKAGE [ARG=yes] + --without-PACKAGE do not use PACKAGE (same as --with-PACKAGE=no) + --with-boost[=ARG] use Boost library from a standard location + (ARG=yes), from the specified location (ARG=<path>), + or disable it (ARG=no) [ARG=yes] + --with-boost-libdir=LIB_DIR + Force given directory for boost libraries. Note that + this will override library path detection, so use + this parameter only if default library detection + fails and you know exactly where your boost + libraries are located. + --with-boost-asio[=special-lib] + use the ASIO library from boost - it is possible to + specify a certain library for the linker e.g. + --with-boost-asio=boost_system-gcc41-mt-1_34 + --with-boost-regex[=special-lib] + use the Regex library from boost - it is possible to + specify a certain library for the linker e.g. + --with-boost-regex=boost_regex-gcc-mt-d-1_33_1 + --with-isa=RV64IMAFDC_zicntr_zihpm + Sets the default RISC-V ISA + --with-priv=MSU Sets the default RISC-V privilege modes supported + --with-varch=vlen:128,elen:64 + Sets the default vector config + --with-target=riscv64-unknown-elf + Sets the default target config + +Some influential environment variables: + CC C compiler command + CFLAGS C compiler flags + LDFLAGS linker flags, e.g. -L<lib dir> if you have libraries in a + nonstandard directory <lib dir> + LIBS libraries to pass to the linker, e.g. -l<library> + CPPFLAGS (Objective) C/C++ preprocessor flags, e.g. -I<include dir> if + you have headers in a nonstandard directory <include dir> + CXX C++ compiler command + CXXFLAGS C++ compiler flags + CXXCPP C++ preprocessor + STOW_ROOT Root for non-native stow-based installs + STOW_PREFIX Prefix for stow-based installs + +Use these variables to override the choices made by `configure' or to help +it to find libraries and programs with nonstandard names/locations. + +Report bugs to <Andrew Waterman>. +_ACEOF +ac_status=$? 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Instead the configure script emits a +# non-fatal: +# +# ./configure: line 1673: AX_CFLAGS_WARN_ALL: command not found +# +# It's like AC_REQUIRE except it doesn't expand the required macro. +# +# Here's an example: +# +# AX_REQUIRE_DEFINED([AX_CHECK_LINK_FLAG]) +# +# LICENSE +# +# Copyright (c) 2014 Mike Frysinger <vapier@gentoo.org> +# +# Copying and distribution of this file, with or without modification, are +# permitted in any medium without royalty provided the copyright notice +# and this notice are preserved. This file is offered as-is, without any +# warranty. + +#serial 2 + + +# =========================================================================== +# https://www.gnu.org/software/autoconf-archive/ax_append_flag.html +# =========================================================================== +# +# SYNOPSIS +# +# AX_APPEND_FLAG(FLAG, [FLAGS-VARIABLE]) +# +# DESCRIPTION +# +# FLAG is appended to the FLAGS-VARIABLE shell variable, with a space +# added in between. +# +# If FLAGS-VARIABLE is not specified, the current language's flags (e.g. +# CFLAGS) is used. FLAGS-VARIABLE is not changed if it already contains +# FLAG. If FLAGS-VARIABLE is unset in the shell, it is set to exactly +# FLAG. +# +# NOTE: Implementation based on AX_CFLAGS_GCC_OPTION. +# +# LICENSE +# +# Copyright (c) 2008 Guido U. Draheim <guidod@gmx.de> +# Copyright (c) 2011 Maarten Bosmans <mkbosmans@gmail.com> +# +# Copying and distribution of this file, with or without modification, are +# permitted in any medium without royalty provided the copyright notice +# and this notice are preserved. This file is offered as-is, without any +# warranty. + +#serial 8 + + +# =========================================================================== +# https://www.gnu.org/software/autoconf-archive/ax_check_compile_flag.html +# =========================================================================== +# +# SYNOPSIS +# +# AX_CHECK_COMPILE_FLAG(FLAG, [ACTION-SUCCESS], [ACTION-FAILURE], [EXTRA-FLAGS], [INPUT]) +# +# DESCRIPTION +# +# Check whether the given FLAG works with the current language's compiler +# or gives an error. (Warnings, however, are ignored) +# +# ACTION-SUCCESS/ACTION-FAILURE are shell commands to execute on +# success/failure. +# +# If EXTRA-FLAGS is defined, it is added to the current language's default +# flags (e.g. CFLAGS) when the check is done. The check is thus made with +# the flags: "CFLAGS EXTRA-FLAGS FLAG". This can for example be used to +# force the compiler to issue an error when a bad flag is given. +# +# INPUT gives an alternative input source to AC_COMPILE_IFELSE. +# +# NOTE: Implementation based on AX_CFLAGS_GCC_OPTION. Please keep this +# macro in sync with AX_CHECK_{PREPROC,LINK}_FLAG. +# +# LICENSE +# +# Copyright (c) 2008 Guido U. Draheim <guidod@gmx.de> +# Copyright (c) 2011 Maarten Bosmans <mkbosmans@gmail.com> +# +# Copying and distribution of this file, with or without modification, are +# permitted in any medium without royalty provided the copyright notice +# and this notice are preserved. This file is offered as-is, without any +# warranty. + +#serial 6 + + +# =========================================================================== +# https://www.gnu.org/software/autoconf-archive/ax_check_link_flag.html +# =========================================================================== +# +# SYNOPSIS +# +# AX_CHECK_LINK_FLAG(FLAG, [ACTION-SUCCESS], [ACTION-FAILURE], [EXTRA-FLAGS], [INPUT]) +# +# DESCRIPTION +# +# Check whether the given FLAG works with the linker or gives an error. +# (Warnings, however, are ignored) +# +# ACTION-SUCCESS/ACTION-FAILURE are shell commands to execute on +# success/failure. +# +# If EXTRA-FLAGS is defined, it is added to the linker's default flags +# when the check is done. The check is thus made with the flags: "LDFLAGS +# EXTRA-FLAGS FLAG". This can for example be used to force the linker to +# issue an error when a bad flag is given. +# +# INPUT gives an alternative input source to AC_LINK_IFELSE. +# +# NOTE: Implementation based on AX_CFLAGS_GCC_OPTION. Please keep this +# macro in sync with AX_CHECK_{PREPROC,COMPILE}_FLAG. +# +# LICENSE +# +# Copyright (c) 2008 Guido U. Draheim <guidod@gmx.de> +# Copyright (c) 2011 Maarten Bosmans <mkbosmans@gmail.com> +# +# Copying and distribution of this file, with or without modification, are +# permitted in any medium without royalty provided the copyright notice +# and this notice are preserved. This file is offered as-is, without any +# warranty. + +#serial 6 + + +# =========================================================================== +# https://www.gnu.org/software/autoconf-archive/ax_append_link_flags.html +# =========================================================================== +# +# SYNOPSIS +# +# AX_APPEND_LINK_FLAGS([FLAG1 FLAG2 ...], [FLAGS-VARIABLE], [EXTRA-FLAGS], [INPUT]) +# +# DESCRIPTION +# +# For every FLAG1, FLAG2 it is checked whether the linker works with the +# flag. If it does, the flag is added FLAGS-VARIABLE +# +# If FLAGS-VARIABLE is not specified, the linker's flags (LDFLAGS) is +# used. During the check the flag is always added to the linker's flags. +# +# If EXTRA-FLAGS is defined, it is added to the linker's default flags +# when the check is done. The check is thus made with the flags: "LDFLAGS +# EXTRA-FLAGS FLAG". This can for example be used to force the linker to +# issue an error when a bad flag is given. +# +# INPUT gives an alternative input source to AC_COMPILE_IFELSE. +# +# NOTE: This macro depends on the AX_APPEND_FLAG and AX_CHECK_LINK_FLAG. +# Please keep this macro in sync with AX_APPEND_COMPILE_FLAGS. +# +# LICENSE +# +# Copyright (c) 2011 Maarten Bosmans <mkbosmans@gmail.com> +# +# Copying and distribution of this file, with or without modification, are +# permitted in any medium without royalty provided the copyright notice +# and this notice are preserved. This file is offered as-is, without any +# warranty. + +#serial 7 + + +# =========================================================================== +# https://www.gnu.org/software/autoconf-archive/ax_boost_base.html +# =========================================================================== +# +# SYNOPSIS +# +# AX_BOOST_BASE([MINIMUM-VERSION], [ACTION-IF-FOUND], [ACTION-IF-NOT-FOUND]) +# +# DESCRIPTION +# +# Test for the Boost C++ libraries of a particular version (or newer) +# +# If no path to the installed boost library is given the macro searchs +# under /usr, /usr/local, /opt and /opt/local and evaluates the +# $BOOST_ROOT environment variable. Further documentation is available at +# <http://randspringer.de/boost/index.html>. +# +# This macro calls: +# +# AC_SUBST(BOOST_CPPFLAGS) / AC_SUBST(BOOST_LDFLAGS) +# +# And sets: +# +# HAVE_BOOST +# +# LICENSE +# +# Copyright (c) 2008 Thomas Porschberg <thomas@randspringer.de> +# Copyright (c) 2009 Peter Adolphs +# +# Copying and distribution of this file, with or without modification, are +# permitted in any medium without royalty provided the copyright notice +# and this notice are preserved. This file is offered as-is, without any +# warranty. + +#serial 49 + +# example boost program (need to pass version) + + + + + +# convert a version string in $2 to numeric and affect to polymorphic var $1 + + + + +# =========================================================================== +# https://www.gnu.org/software/autoconf-archive/ax_boost_asio.html +# =========================================================================== +# +# SYNOPSIS +# +# AX_BOOST_ASIO +# +# DESCRIPTION +# +# Test for Asio library from the Boost C++ libraries. The macro requires a +# preceding call to AX_BOOST_BASE. Further documentation is available at +# <http://randspringer.de/boost/index.html>. +# +# This macro calls: +# +# AC_SUBST(BOOST_ASIO_LIB) +# +# And sets: +# +# HAVE_BOOST_ASIO +# +# LICENSE +# +# Copyright (c) 2008 Thomas Porschberg <thomas@randspringer.de> +# Copyright (c) 2008 Pete Greenwell <pete@mu.org> +# +# Copying and distribution of this file, with or without modification, are +# permitted in any medium without royalty provided the copyright notice +# and this notice are preserved. This file is offered as-is, without any +# warranty. + +#serial 18 + + + +# =========================================================================== +# https://www.gnu.org/software/autoconf-archive/ax_boost_regex.html +# =========================================================================== +# +# SYNOPSIS +# +# AX_BOOST_REGEX +# +# DESCRIPTION +# +# Test for Regex library from the Boost C++ libraries. The macro requires +# a preceding call to AX_BOOST_BASE. Further documentation is available at +# <http://randspringer.de/boost/index.html>. +# +# This macro calls: +# +# AC_SUBST(BOOST_REGEX_LIB) +# +# And sets: +# +# HAVE_BOOST_REGEX +# +# LICENSE +# +# Copyright (c) 2008 Thomas Porschberg <thomas@randspringer.de> +# Copyright (c) 2008 Michael Tindal +# +# Copying and distribution of this file, with or without modification, are +# permitted in any medium without royalty provided the copyright notice +# and this notice are preserved. This file is offered as-is, without any +# warranty. + +#serial 23 + + + + +#------------------------------------------------------------------------- +# Checks for programs +#------------------------------------------------------------------------- + +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu +if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}gcc", so it can be a program name with args. +set dummy ${ac_tool_prefix}gcc; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_CC+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_CC="${ac_tool_prefix}gcc" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$ac_cv_prog_CC"; then + ac_ct_CC=$CC + # Extract the first word of "gcc", so it can be a program name with args. +set dummy gcc; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_ac_ct_CC+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_CC"; then + ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_ac_ct_CC="gcc" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_CC=$ac_cv_prog_ac_ct_CC +if test -n "$ac_ct_CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_CC" >&5 +$as_echo "$ac_ct_CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + if test "x$ac_ct_CC" = x; then + CC="" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + CC=$ac_ct_CC + fi +else + CC="$ac_cv_prog_CC" +fi + +if test -z "$CC"; then + if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}cc", so it can be a program name with args. +set dummy ${ac_tool_prefix}cc; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_CC+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_CC="${ac_tool_prefix}cc" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + fi +fi +if test -z "$CC"; then + # Extract the first word of "cc", so it can be a program name with args. +set dummy cc; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_CC+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else + ac_prog_rejected=no +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + if test "$as_dir/$ac_word$ac_exec_ext" = "/usr/ucb/cc"; then + ac_prog_rejected=yes + continue + fi + ac_cv_prog_CC="cc" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +if test $ac_prog_rejected = yes; then + # We found a bogon in the path, so make sure we never use it. + set dummy $ac_cv_prog_CC + shift + if test $# != 0; then + # We chose a different compiler from the bogus one. + # However, it has the same basename, so the bogon will be chosen + # first if we set CC to just the basename; use the full file name. + shift + ac_cv_prog_CC="$as_dir/$ac_word${1+' '}$@" + fi +fi +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$CC"; then + if test -n "$ac_tool_prefix"; then + for ac_prog in cl.exe + do + # Extract the first word of "$ac_tool_prefix$ac_prog", so it can be a program name with args. +set dummy $ac_tool_prefix$ac_prog; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_CC+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_CC="$ac_tool_prefix$ac_prog" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + test -n "$CC" && break + done +fi +if test -z "$CC"; then + ac_ct_CC=$CC + for ac_prog in cl.exe +do + # Extract the first word of "$ac_prog", so it can be a program name with args. +set dummy $ac_prog; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_ac_ct_CC+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_CC"; then + ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_ac_ct_CC="$ac_prog" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_CC=$ac_cv_prog_ac_ct_CC +if test -n "$ac_ct_CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_CC" >&5 +$as_echo "$ac_ct_CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + test -n "$ac_ct_CC" && break +done + + if test "x$ac_ct_CC" = x; then + CC="" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + CC=$ac_ct_CC + fi +fi + +fi + + +test -z "$CC" && { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error $? "no acceptable C compiler found in \$PATH +See \`config.log' for more details" "$LINENO" 5; } + +# Provide some information about the compiler. +$as_echo "$as_me:${as_lineno-$LINENO}: checking for C compiler version" >&5 +set X $ac_compile +ac_compiler=$2 +for ac_option in --version -v -V -qversion; do + { { ac_try="$ac_compiler $ac_option >&5" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_compiler $ac_option >&5") 2>conftest.err + ac_status=$? + if test -s conftest.err; then + sed '10a\ +... rest of stderr output deleted ... + 10q' conftest.err >conftest.er1 + cat conftest.er1 >&5 + fi + rm -f conftest.er1 conftest.err + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } +done + +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +ac_clean_files_save=$ac_clean_files +ac_clean_files="$ac_clean_files a.out a.out.dSYM a.exe b.out" +# Try to create an executable without -o first, disregard a.out. +# It will help us diagnose broken compilers, and finding out an intuition +# of exeext. +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether the C compiler works" >&5 +$as_echo_n "checking whether the C compiler works... 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We should not override ac_cv_exeext if it was cached, +# so that the user can short-circuit this test for compilers unknown to +# Autoconf. +for ac_file in $ac_files '' +do + test -f "$ac_file" || continue + case $ac_file in + *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM | *.o | *.obj ) + ;; + [ab].out ) + # We found the default executable, but exeext='' is most + # certainly right. + break;; + *.* ) + if test "${ac_cv_exeext+set}" = set && test "$ac_cv_exeext" != no; + then :; else + ac_cv_exeext=`expr "$ac_file" : '[^.]*\(\..*\)'` + fi + # We set ac_cv_exeext here because the later test for it is not + # safe: cross compilers may not add the suffix if given an `-o' + # argument, so we may need to know it at that point already. + # Even if this section looks crufty: it has the advantage of + # actually working. + break;; + * ) + break;; + esac +done +test "$ac_cv_exeext" = no && ac_cv_exeext= + +else + ac_file='' +fi +if test -z "$ac_file"; then : + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +$as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + +{ { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error 77 "C compiler cannot create executables +See \`config.log' for more details" "$LINENO" 5; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 +$as_echo "yes" >&6; } +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for C compiler default output file name" >&5 +$as_echo_n "checking for C compiler default output file name... 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For instance with Cygwin, `ls conftest' will +# work properly (i.e., refer to `conftest.exe'), while it won't with +# `rm'. +for ac_file in conftest.exe conftest conftest.*; do + test -f "$ac_file" || continue + case $ac_file in + *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM | *.o | *.obj ) ;; + *.* ) ac_cv_exeext=`expr "$ac_file" : '[^.]*\(\..*\)'` + break;; + * ) break;; + esac +done +else + { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error $? 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"cannot run C compiled programs. +If you meant to cross compile, use \`--host'. +See \`config.log' for more details" "$LINENO" 5; } + fi + fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $cross_compiling" >&5 +$as_echo "$cross_compiling" >&6; } + +rm -f conftest.$ac_ext conftest$ac_cv_exeext conftest.out +ac_clean_files=$ac_clean_files_save +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for suffix of object files" >&5 +$as_echo_n "checking for suffix of object files... " >&6; } +if ${ac_cv_objext+:} false; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +rm -f conftest.o conftest.obj +if { { ac_try="$ac_compile" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_compile") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; then : + for ac_file in conftest.o conftest.obj conftest.*; do + test -f "$ac_file" || continue; + case $ac_file in + *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM ) ;; + *) ac_cv_objext=`expr "$ac_file" : '.*\.\(.*\)'` + break;; + esac +done +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + +{ { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error $? "cannot compute suffix of object files: cannot compile +See \`config.log' for more details" "$LINENO" 5; } +fi +rm -f conftest.$ac_cv_objext conftest.$ac_ext +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_objext" >&5 +$as_echo "$ac_cv_objext" >&6; } +OBJEXT=$ac_cv_objext +ac_objext=$OBJEXT +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether we are using the GNU C compiler" >&5 +$as_echo_n "checking whether we are using the GNU C compiler... " >&6; } +if ${ac_cv_c_compiler_gnu+:} false; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ +#ifndef __GNUC__ + choke me +#endif + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_compiler_gnu=yes +else + ac_compiler_gnu=no +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +ac_cv_c_compiler_gnu=$ac_compiler_gnu + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_c_compiler_gnu" >&5 +$as_echo "$ac_cv_c_compiler_gnu" >&6; } +if test $ac_compiler_gnu = yes; then + GCC=yes +else + GCC= +fi +ac_test_CFLAGS=${CFLAGS+set} +ac_save_CFLAGS=$CFLAGS +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether $CC accepts -g" >&5 +$as_echo_n "checking whether $CC accepts -g... " >&6; } +if ${ac_cv_prog_cc_g+:} false; then : + $as_echo_n "(cached) " >&6 +else + ac_save_c_werror_flag=$ac_c_werror_flag + ac_c_werror_flag=yes + ac_cv_prog_cc_g=no + CFLAGS="-g" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_prog_cc_g=yes +else + CFLAGS="" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + +else + ac_c_werror_flag=$ac_save_c_werror_flag + CFLAGS="-g" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_prog_cc_g=yes +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + ac_c_werror_flag=$ac_save_c_werror_flag +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_prog_cc_g" >&5 +$as_echo "$ac_cv_prog_cc_g" >&6; } +if test "$ac_test_CFLAGS" = set; then + CFLAGS=$ac_save_CFLAGS +elif test $ac_cv_prog_cc_g = yes; then + if test "$GCC" = yes; then + CFLAGS="-g -O2" + else + CFLAGS="-g" + fi +else + if test "$GCC" = yes; then + CFLAGS="-O2" + else + CFLAGS= + fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $CC option to accept ISO C89" >&5 +$as_echo_n "checking for $CC option to accept ISO C89... " >&6; } +if ${ac_cv_prog_cc_c89+:} false; then : + $as_echo_n "(cached) " >&6 +else + ac_cv_prog_cc_c89=no +ac_save_CC=$CC +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include <stdarg.h> +#include <stdio.h> +struct stat; +/* Most of the following tests are stolen from RCS 5.7's src/conf.sh. */ +struct buf { int x; }; +FILE * (*rcsopen) (struct buf *, struct stat *, int); +static char *e (p, i) + char **p; + int i; +{ + return p[i]; +} +static char *f (char * (*g) (char **, int), char **p, ...) +{ + char *s; + va_list v; + va_start (v,p); + s = g (p, va_arg (v,int)); + va_end (v); + return s; +} + +/* OSF 4.0 Compaq cc is some sort of almost-ANSI by default. It has + function prototypes and stuff, but not '\xHH' hex character constants. + These don't provoke an error unfortunately, instead are silently treated + as 'x'. The following induces an error, until -std is added to get + proper ANSI mode. Curiously '\x00'!='x' always comes out true, for an + array size at least. It's necessary to write '\x00'==0 to get something + that's true only with -std. */ +int osf4_cc_array ['\x00' == 0 ? 1 : -1]; + +/* IBM C 6 for AIX is almost-ANSI by default, but it replaces macro parameters + inside strings and character constants. */ +#define FOO(x) 'x' +int xlc6_cc_array[FOO(a) == 'x' ? 1 : -1]; + +int test (int i, double x); +struct s1 {int (*f) (int a);}; +struct s2 {int (*f) (double a);}; +int pairnames (int, char **, FILE *(*)(struct buf *, struct stat *, int), int, int); +int argc; +char **argv; +int +main () +{ +return f (e, argv, 0) != argv[0] || f (e, argv, 1) != argv[1]; + ; + return 0; +} +_ACEOF +for ac_arg in '' -qlanglvl=extc89 -qlanglvl=ansi -std \ + -Ae "-Aa -D_HPUX_SOURCE" "-Xc -D__EXTENSIONS__" +do + CC="$ac_save_CC $ac_arg" + if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_prog_cc_c89=$ac_arg +fi +rm -f core conftest.err conftest.$ac_objext + test "x$ac_cv_prog_cc_c89" != "xno" && break +done +rm -f conftest.$ac_ext +CC=$ac_save_CC + +fi +# AC_CACHE_VAL +case "x$ac_cv_prog_cc_c89" in + x) + { $as_echo "$as_me:${as_lineno-$LINENO}: result: none needed" >&5 +$as_echo "none needed" >&6; } ;; + xno) + { $as_echo "$as_me:${as_lineno-$LINENO}: result: unsupported" >&5 +$as_echo "unsupported" >&6; } ;; + *) + CC="$CC $ac_cv_prog_cc_c89" + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_prog_cc_c89" >&5 +$as_echo "$ac_cv_prog_cc_c89" >&6; } ;; +esac +if test "x$ac_cv_prog_cc_c89" != xno; then : + +fi + +ac_ext=cpp +ac_cpp='$CXXCPP $CPPFLAGS' +ac_compile='$CXX -c $CXXFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CXX -o conftest$ac_exeext $CXXFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_cxx_compiler_gnu + +ac_ext=cpp +ac_cpp='$CXXCPP $CPPFLAGS' +ac_compile='$CXX -c $CXXFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CXX -o conftest$ac_exeext $CXXFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_cxx_compiler_gnu +if test -z "$CXX"; then + if test -n "$CCC"; then + CXX=$CCC + else + if test -n "$ac_tool_prefix"; then + for ac_prog in g++ c++ gpp aCC CC cxx cc++ cl.exe FCC KCC RCC xlC_r xlC + do + # Extract the first word of "$ac_tool_prefix$ac_prog", so it can be a program name with args. +set dummy $ac_tool_prefix$ac_prog; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_CXX+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$CXX"; then + ac_cv_prog_CXX="$CXX" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_CXX="$ac_tool_prefix$ac_prog" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +CXX=$ac_cv_prog_CXX +if test -n "$CXX"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CXX" >&5 +$as_echo "$CXX" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + test -n "$CXX" && break + done +fi +if test -z "$CXX"; then + ac_ct_CXX=$CXX + for ac_prog in g++ c++ gpp aCC CC cxx cc++ cl.exe FCC KCC RCC xlC_r xlC +do + # Extract the first word of "$ac_prog", so it can be a program name with args. +set dummy $ac_prog; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_ac_ct_CXX+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_CXX"; then + ac_cv_prog_ac_ct_CXX="$ac_ct_CXX" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_ac_ct_CXX="$ac_prog" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_CXX=$ac_cv_prog_ac_ct_CXX +if test -n "$ac_ct_CXX"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_CXX" >&5 +$as_echo "$ac_ct_CXX" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + test -n "$ac_ct_CXX" && break +done + + if test "x$ac_ct_CXX" = x; then + CXX="g++" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + CXX=$ac_ct_CXX + fi +fi + + fi +fi +# Provide some information about the compiler. +$as_echo "$as_me:${as_lineno-$LINENO}: checking for C++ compiler version" >&5 +set X $ac_compile +ac_compiler=$2 +for ac_option in --version -v -V -qversion; do + { { ac_try="$ac_compiler $ac_option >&5" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_compiler $ac_option >&5") 2>conftest.err + ac_status=$? + if test -s conftest.err; then + sed '10a\ +... rest of stderr output deleted ... + 10q' conftest.err >conftest.er1 + cat conftest.er1 >&5 + fi + rm -f conftest.er1 conftest.err + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } +done + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether we are using the GNU C++ compiler" >&5 +$as_echo_n "checking whether we are using the GNU C++ compiler... " >&6; } +if ${ac_cv_cxx_compiler_gnu+:} false; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ +#ifndef __GNUC__ + choke me +#endif + + ; + return 0; +} +_ACEOF +if ac_fn_cxx_try_compile "$LINENO"; then : + ac_compiler_gnu=yes +else + ac_compiler_gnu=no +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +ac_cv_cxx_compiler_gnu=$ac_compiler_gnu + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_cxx_compiler_gnu" >&5 +$as_echo "$ac_cv_cxx_compiler_gnu" >&6; } +if test $ac_compiler_gnu = yes; then + GXX=yes +else + GXX= +fi +ac_test_CXXFLAGS=${CXXFLAGS+set} +ac_save_CXXFLAGS=$CXXFLAGS +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether $CXX accepts -g" >&5 +$as_echo_n "checking whether $CXX accepts -g... " >&6; } +if ${ac_cv_prog_cxx_g+:} false; then : + $as_echo_n "(cached) " >&6 +else + ac_save_cxx_werror_flag=$ac_cxx_werror_flag + ac_cxx_werror_flag=yes + ac_cv_prog_cxx_g=no + CXXFLAGS="-g" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_cxx_try_compile "$LINENO"; then : + ac_cv_prog_cxx_g=yes +else + CXXFLAGS="" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_cxx_try_compile "$LINENO"; then : + +else + ac_cxx_werror_flag=$ac_save_cxx_werror_flag + CXXFLAGS="-g" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_cxx_try_compile "$LINENO"; then : + ac_cv_prog_cxx_g=yes +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + ac_cxx_werror_flag=$ac_save_cxx_werror_flag +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_prog_cxx_g" >&5 +$as_echo "$ac_cv_prog_cxx_g" >&6; } +if test "$ac_test_CXXFLAGS" = set; then + CXXFLAGS=$ac_save_CXXFLAGS +elif test $ac_cv_prog_cxx_g = yes; then + if test "$GXX" = yes; then + CXXFLAGS="-g -O2" + else + CXXFLAGS="-g" + fi +else + if test "$GXX" = yes; then + CXXFLAGS="-O2" + else + CXXFLAGS= + fi +fi +ac_ext=cpp +ac_cpp='$CXXCPP $CPPFLAGS' +ac_compile='$CXX -c $CXXFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CXX -o conftest$ac_exeext $CXXFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_cxx_compiler_gnu + +if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}ar", so it can be a program name with args. +set dummy ${ac_tool_prefix}ar; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_AR+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$AR"; then + ac_cv_prog_AR="$AR" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_AR="${ac_tool_prefix}ar" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +AR=$ac_cv_prog_AR +if test -n "$AR"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $AR" >&5 +$as_echo "$AR" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$ac_cv_prog_AR"; then + ac_ct_AR=$AR + # Extract the first word of "ar", so it can be a program name with args. +set dummy ar; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_ac_ct_AR+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_AR"; then + ac_cv_prog_ac_ct_AR="$ac_ct_AR" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_ac_ct_AR="ar" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_AR=$ac_cv_prog_ac_ct_AR +if test -n "$ac_ct_AR"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_AR" >&5 +$as_echo "$ac_ct_AR" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + if test "x$ac_ct_AR" = x; then + AR="" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + AR=$ac_ct_AR + fi +else + AR="$ac_cv_prog_AR" +fi + +if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}ranlib", so it can be a program name with args. +set dummy ${ac_tool_prefix}ranlib; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_RANLIB+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$RANLIB"; then + ac_cv_prog_RANLIB="$RANLIB" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_RANLIB="${ac_tool_prefix}ranlib" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +RANLIB=$ac_cv_prog_RANLIB +if test -n "$RANLIB"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $RANLIB" >&5 +$as_echo "$RANLIB" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$ac_cv_prog_RANLIB"; then + ac_ct_RANLIB=$RANLIB + # Extract the first word of "ranlib", so it can be a program name with args. +set dummy ranlib; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_ac_ct_RANLIB+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_RANLIB"; then + ac_cv_prog_ac_ct_RANLIB="$ac_ct_RANLIB" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_ac_ct_RANLIB="ranlib" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_RANLIB=$ac_cv_prog_ac_ct_RANLIB +if test -n "$ac_ct_RANLIB"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_RANLIB" >&5 +$as_echo "$ac_ct_RANLIB" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + if test "x$ac_ct_RANLIB" = x; then + RANLIB="" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + RANLIB=$ac_ct_RANLIB + fi +else + RANLIB="$ac_cv_prog_RANLIB" +fi + +# Extract the first word of "dtc", so it can be a program name with args. +set dummy dtc; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_path_DTC+:} false; then : + $as_echo_n "(cached) " >&6 +else + case $DTC in + [\\/]* | ?:[\\/]*) + ac_cv_path_DTC="$DTC" # Let the user override the test with a path. + ;; + *) + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_path_DTC="$as_dir/$ac_word$ac_exec_ext" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + + test -z "$ac_cv_path_DTC" && ac_cv_path_DTC="no" + ;; +esac +fi +DTC=$ac_cv_path_DTC +if test -n "$DTC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $DTC" >&5 +$as_echo "$DTC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +if test x"$DTC" == xno; then : + as_fn_error $? "device-tree-compiler not found" "$LINENO" 5 +fi + +cat >>confdefs.h <<_ACEOF +#define DTC "dtc" +_ACEOF + + + +ac_ext=cpp +ac_cpp='$CXXCPP $CPPFLAGS' +ac_compile='$CXX -c $CXXFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CXX -o conftest$ac_exeext $CXXFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_cxx_compiler_gnu +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking how to run the C++ preprocessor" >&5 +$as_echo_n "checking how to run the C++ preprocessor... " >&6; } +if test -z "$CXXCPP"; then + if ${ac_cv_prog_CXXCPP+:} false; then : + $as_echo_n "(cached) " >&6 +else + # Double quotes because CXXCPP needs to be expanded + for CXXCPP in "$CXX -E" "/lib/cpp" + do + ac_preproc_ok=false +for ac_cxx_preproc_warn_flag in '' yes +do + # Use a header file that comes with gcc, so configuring glibc + # with a fresh cross-compiler works. + # Prefer <limits.h> to <assert.h> if __STDC__ is defined, since + # <limits.h> exists even on freestanding compilers. + # On the NeXT, cc -E runs the code through the compiler's parser, + # not just through cpp. "Syntax error" is here to catch this case. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#ifdef __STDC__ +# include <limits.h> +#else +# include <assert.h> +#endif + Syntax error +_ACEOF +if ac_fn_cxx_try_cpp "$LINENO"; then : + +else + # Broken: fails on valid input. +continue +fi +rm -f conftest.err conftest.i conftest.$ac_ext + + # OK, works on sane cases. Now check whether nonexistent headers + # can be detected and how. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include <ac_nonexistent.h> +_ACEOF +if ac_fn_cxx_try_cpp "$LINENO"; then : + # Broken: success on invalid input. +continue +else + # Passes both tests. +ac_preproc_ok=: +break +fi +rm -f conftest.err conftest.i conftest.$ac_ext + +done +# Because of `break', _AC_PREPROC_IFELSE's cleaning code was skipped. +rm -f conftest.i conftest.err conftest.$ac_ext +if $ac_preproc_ok; then : + break +fi + + done + ac_cv_prog_CXXCPP=$CXXCPP + +fi + CXXCPP=$ac_cv_prog_CXXCPP +else + ac_cv_prog_CXXCPP=$CXXCPP +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $CXXCPP" >&5 +$as_echo "$CXXCPP" >&6; } +ac_preproc_ok=false +for ac_cxx_preproc_warn_flag in '' yes +do + # Use a header file that comes with gcc, so configuring glibc + # with a fresh cross-compiler works. + # Prefer <limits.h> to <assert.h> if __STDC__ is defined, since + # <limits.h> exists even on freestanding compilers. + # On the NeXT, cc -E runs the code through the compiler's parser, + # not just through cpp. "Syntax error" is here to catch this case. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#ifdef __STDC__ +# include <limits.h> +#else +# include <assert.h> +#endif + Syntax error +_ACEOF +if ac_fn_cxx_try_cpp "$LINENO"; then : + +else + # Broken: fails on valid input. +continue +fi +rm -f conftest.err conftest.i conftest.$ac_ext + + # OK, works on sane cases. Now check whether nonexistent headers + # can be detected and how. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include <ac_nonexistent.h> +_ACEOF +if ac_fn_cxx_try_cpp "$LINENO"; then : + # Broken: success on invalid input. +continue +else + # Passes both tests. +ac_preproc_ok=: +break +fi +rm -f conftest.err conftest.i conftest.$ac_ext + +done +# Because of `break', _AC_PREPROC_IFELSE's cleaning code was skipped. +rm -f conftest.i conftest.err conftest.$ac_ext +if $ac_preproc_ok; then : + +else + { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error $? "C++ preprocessor \"$CXXCPP\" fails sanity check +See \`config.log' for more details" "$LINENO" 5; } +fi + +ac_ext=cpp +ac_cpp='$CXXCPP $CPPFLAGS' +ac_compile='$CXX -c $CXXFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CXX -o conftest$ac_exeext $CXXFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_cxx_compiler_gnu + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for grep that handles long lines and -e" >&5 +$as_echo_n "checking for grep that handles long lines and -e... " >&6; } +if ${ac_cv_path_GREP+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -z "$GREP"; then + ac_path_GREP_found=false + # Loop through the user's path and test for each of PROGNAME-LIST + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH$PATH_SEPARATOR/usr/xpg4/bin +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_prog in grep ggrep; do + for ac_exec_ext in '' $ac_executable_extensions; do + ac_path_GREP="$as_dir/$ac_prog$ac_exec_ext" + as_fn_executable_p "$ac_path_GREP" || continue +# Check for GNU ac_path_GREP and select it if it is found. + # Check for GNU $ac_path_GREP +case `"$ac_path_GREP" --version 2>&1` in +*GNU*) + ac_cv_path_GREP="$ac_path_GREP" ac_path_GREP_found=:;; +*) + ac_count=0 + $as_echo_n 0123456789 >"conftest.in" + while : + do + cat "conftest.in" "conftest.in" >"conftest.tmp" + mv "conftest.tmp" "conftest.in" + cp "conftest.in" "conftest.nl" + $as_echo 'GREP' >> "conftest.nl" + "$ac_path_GREP" -e 'GREP$' -e '-(cannot match)-' < "conftest.nl" >"conftest.out" 2>/dev/null || break + diff "conftest.out" "conftest.nl" >/dev/null 2>&1 || break + as_fn_arith $ac_count + 1 && ac_count=$as_val + if test $ac_count -gt ${ac_path_GREP_max-0}; then + # Best one so far, save it but keep looking for a better one + ac_cv_path_GREP="$ac_path_GREP" + ac_path_GREP_max=$ac_count + fi + # 10*(2^10) chars as input seems more than enough + test $ac_count -gt 10 && break + done + rm -f conftest.in conftest.tmp conftest.nl conftest.out;; +esac + + $ac_path_GREP_found && break 3 + done + done + done +IFS=$as_save_IFS + if test -z "$ac_cv_path_GREP"; then + as_fn_error $? "no acceptable grep could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" "$LINENO" 5 + fi +else + ac_cv_path_GREP=$GREP +fi + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_path_GREP" >&5 +$as_echo "$ac_cv_path_GREP" >&6; } + GREP="$ac_cv_path_GREP" + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for egrep" >&5 +$as_echo_n "checking for egrep... " >&6; } +if ${ac_cv_path_EGREP+:} false; then : + $as_echo_n "(cached) " >&6 +else + if echo a | $GREP -E '(a|b)' >/dev/null 2>&1 + then ac_cv_path_EGREP="$GREP -E" + else + if test -z "$EGREP"; then + ac_path_EGREP_found=false + # Loop through the user's path and test for each of PROGNAME-LIST + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH$PATH_SEPARATOR/usr/xpg4/bin +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_prog in egrep; do + for ac_exec_ext in '' $ac_executable_extensions; do + ac_path_EGREP="$as_dir/$ac_prog$ac_exec_ext" + as_fn_executable_p "$ac_path_EGREP" || continue +# Check for GNU ac_path_EGREP and select it if it is found. + # Check for GNU $ac_path_EGREP +case `"$ac_path_EGREP" --version 2>&1` in +*GNU*) + ac_cv_path_EGREP="$ac_path_EGREP" ac_path_EGREP_found=:;; +*) + ac_count=0 + $as_echo_n 0123456789 >"conftest.in" + while : + do + cat "conftest.in" "conftest.in" >"conftest.tmp" + mv "conftest.tmp" "conftest.in" + cp "conftest.in" "conftest.nl" + $as_echo 'EGREP' >> "conftest.nl" + "$ac_path_EGREP" 'EGREP$' < "conftest.nl" >"conftest.out" 2>/dev/null || break + diff "conftest.out" "conftest.nl" >/dev/null 2>&1 || break + as_fn_arith $ac_count + 1 && ac_count=$as_val + if test $ac_count -gt ${ac_path_EGREP_max-0}; then + # Best one so far, save it but keep looking for a better one + ac_cv_path_EGREP="$ac_path_EGREP" + ac_path_EGREP_max=$ac_count + fi + # 10*(2^10) chars as input seems more than enough + test $ac_count -gt 10 && break + done + rm -f conftest.in conftest.tmp conftest.nl conftest.out;; +esac + + $ac_path_EGREP_found && break 3 + done + done + done +IFS=$as_save_IFS + if test -z "$ac_cv_path_EGREP"; then + as_fn_error $? "no acceptable egrep could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" "$LINENO" 5 + fi +else + ac_cv_path_EGREP=$EGREP +fi + + fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_path_EGREP" >&5 +$as_echo "$ac_cv_path_EGREP" >&6; } + EGREP="$ac_cv_path_EGREP" + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for ANSI C header files" >&5 +$as_echo_n "checking for ANSI C header files... " >&6; } +if ${ac_cv_header_stdc+:} false; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include <stdlib.h> +#include <stdarg.h> +#include <string.h> +#include <float.h> + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_cxx_try_compile "$LINENO"; then : + ac_cv_header_stdc=yes +else + ac_cv_header_stdc=no +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + +if test $ac_cv_header_stdc = yes; then + # SunOS 4.x string.h does not declare mem*, contrary to ANSI. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include <string.h> + +_ACEOF +if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | + $EGREP "memchr" >/dev/null 2>&1; then : + +else + ac_cv_header_stdc=no +fi +rm -f conftest* + +fi + +if test $ac_cv_header_stdc = yes; then + # ISC 2.0.2 stdlib.h does not declare free, contrary to ANSI. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include <stdlib.h> + +_ACEOF +if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | + $EGREP "free" >/dev/null 2>&1; then : + +else + ac_cv_header_stdc=no +fi +rm -f conftest* + +fi + +if test $ac_cv_header_stdc = yes; then + # /bin/cc in Irix-4.0.5 gets non-ANSI ctype macros unless using -ansi. + if test "$cross_compiling" = yes; then : + : +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include <ctype.h> +#include <stdlib.h> +#if ((' ' & 0x0FF) == 0x020) +# define ISLOWER(c) ('a' <= (c) && (c) <= 'z') +# define TOUPPER(c) (ISLOWER(c) ? 'A' + ((c) - 'a') : (c)) +#else +# define ISLOWER(c) \ + (('a' <= (c) && (c) <= 'i') \ + || ('j' <= (c) && (c) <= 'r') \ + || ('s' <= (c) && (c) <= 'z')) +# define TOUPPER(c) (ISLOWER(c) ? ((c) | 0x40) : (c)) +#endif + +#define XOR(e, f) (((e) && !(f)) || (!(e) && (f))) +int +main () +{ + int i; + for (i = 0; i < 256; i++) + if (XOR (islower (i), ISLOWER (i)) + || toupper (i) != TOUPPER (i)) + return 2; + return 0; +} +_ACEOF +if ac_fn_cxx_try_run "$LINENO"; then : + +else + ac_cv_header_stdc=no +fi +rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext \ + conftest.$ac_objext conftest.beam conftest.$ac_ext +fi + +fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_header_stdc" >&5 +$as_echo "$ac_cv_header_stdc" >&6; } +if test $ac_cv_header_stdc = yes; then + +$as_echo "#define STDC_HEADERS 1" >>confdefs.h + +fi + +# On IRIX 5.3, sys/types and inttypes.h are conflicting. +for ac_header in sys/types.h sys/stat.h stdlib.h string.h memory.h strings.h \ + inttypes.h stdint.h unistd.h +do : + as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh` +ac_fn_cxx_check_header_compile "$LINENO" "$ac_header" "$as_ac_Header" "$ac_includes_default +" +if eval test \"x\$"$as_ac_Header"\" = x"yes"; then : + cat >>confdefs.h <<_ACEOF +#define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1 +_ACEOF + +fi + +done + + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether byte ordering is bigendian" >&5 +$as_echo_n "checking whether byte ordering is bigendian... " >&6; } +if ${ac_cv_c_bigendian+:} false; then : + $as_echo_n "(cached) " >&6 +else + ac_cv_c_bigendian=unknown + # See if we're dealing with a universal compiler. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#ifndef __APPLE_CC__ + not a universal capable compiler + #endif + typedef int dummy; + +_ACEOF +if ac_fn_cxx_try_compile "$LINENO"; then : + + # Check for potential -arch flags. It is not universal unless + # there are at least two -arch flags with different values. + ac_arch= + ac_prev= + for ac_word in $CC $CFLAGS $CPPFLAGS $LDFLAGS; do + if test -n "$ac_prev"; then + case $ac_word in + i?86 | x86_64 | ppc | ppc64) + if test -z "$ac_arch" || test "$ac_arch" = "$ac_word"; then + ac_arch=$ac_word + else + ac_cv_c_bigendian=universal + break + fi + ;; + esac + ac_prev= + elif test "x$ac_word" = "x-arch"; then + ac_prev=arch + fi + done +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test $ac_cv_c_bigendian = unknown; then + # See if sys/param.h defines the BYTE_ORDER macro. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include <sys/types.h> + #include <sys/param.h> + +int +main () +{ +#if ! (defined BYTE_ORDER && defined BIG_ENDIAN \ + && defined LITTLE_ENDIAN && BYTE_ORDER && BIG_ENDIAN \ + && LITTLE_ENDIAN) + bogus endian macros + #endif + + ; + return 0; +} +_ACEOF +if ac_fn_cxx_try_compile "$LINENO"; then : + # It does; now see whether it defined to BIG_ENDIAN or not. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include <sys/types.h> + #include <sys/param.h> + +int +main () +{ +#if BYTE_ORDER != BIG_ENDIAN + not big endian + #endif + + ; + return 0; +} +_ACEOF +if ac_fn_cxx_try_compile "$LINENO"; then : + ac_cv_c_bigendian=yes +else + ac_cv_c_bigendian=no +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + fi + if test $ac_cv_c_bigendian = unknown; then + # See if <limits.h> defines _LITTLE_ENDIAN or _BIG_ENDIAN (e.g., Solaris). + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include <limits.h> + +int +main () +{ +#if ! (defined _LITTLE_ENDIAN || defined _BIG_ENDIAN) + bogus endian macros + #endif + + ; + return 0; +} +_ACEOF +if ac_fn_cxx_try_compile "$LINENO"; then : + # It does; now see whether it defined to _BIG_ENDIAN or not. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include <limits.h> + +int +main () +{ +#ifndef _BIG_ENDIAN + not big endian + #endif + + ; + return 0; +} +_ACEOF +if ac_fn_cxx_try_compile "$LINENO"; then : + ac_cv_c_bigendian=yes +else + ac_cv_c_bigendian=no +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + fi + if test $ac_cv_c_bigendian = unknown; then + # Compile a test program. + if test "$cross_compiling" = yes; then : + # Try to guess by grepping values from an object file. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +short int ascii_mm[] = + { 0x4249, 0x4765, 0x6E44, 0x6961, 0x6E53, 0x7953, 0 }; + short int ascii_ii[] = + { 0x694C, 0x5454, 0x656C, 0x6E45, 0x6944, 0x6E61, 0 }; + int use_ascii (int i) { + return ascii_mm[i] + ascii_ii[i]; + } + short int ebcdic_ii[] = + { 0x89D3, 0xE3E3, 0x8593, 0x95C5, 0x89C4, 0x9581, 0 }; + short int ebcdic_mm[] = + { 0xC2C9, 0xC785, 0x95C4, 0x8981, 0x95E2, 0xA8E2, 0 }; + int use_ebcdic (int i) { + return ebcdic_mm[i] + ebcdic_ii[i]; + } + extern int foo; + +int +main () +{ +return use_ascii (foo) == use_ebcdic (foo); + ; + return 0; +} +_ACEOF +if ac_fn_cxx_try_compile "$LINENO"; then : + if grep BIGenDianSyS conftest.$ac_objext >/dev/null; then + ac_cv_c_bigendian=yes + fi + if grep LiTTleEnDian conftest.$ac_objext >/dev/null ; then + if test "$ac_cv_c_bigendian" = unknown; then + ac_cv_c_bigendian=no + else + # finding both strings is unlikely to happen, but who knows? + ac_cv_c_bigendian=unknown + fi + fi +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +$ac_includes_default +int +main () +{ + + /* Are we little or big endian? From Harbison&Steele. */ + union + { + long int l; + char c[sizeof (long int)]; + } u; + u.l = 1; + return u.c[sizeof (long int) - 1] == 1; + + ; + return 0; +} +_ACEOF +if ac_fn_cxx_try_run "$LINENO"; then : + ac_cv_c_bigendian=no +else + ac_cv_c_bigendian=yes +fi +rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext \ + conftest.$ac_objext conftest.beam conftest.$ac_ext +fi + + fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_c_bigendian" >&5 +$as_echo "$ac_cv_c_bigendian" >&6; } + case $ac_cv_c_bigendian in #( + yes) + $as_echo "#define WORDS_BIGENDIAN 1" >>confdefs.h +;; #( + no) + ;; #( + universal) + +$as_echo "#define AC_APPLE_UNIVERSAL_BUILD 1" >>confdefs.h + + ;; #( + *) + as_fn_error $? "unknown endianness + presetting ac_cv_c_bigendian=no (or yes) will help" "$LINENO" 5 ;; + esac + + +#------------------------------------------------------------------------- +# MCPPBS specific program checks +#------------------------------------------------------------------------- +# These macros check to see if we can do a stow-based install and also +# check for an isa simulator suitable for running the unit test programs +# via the makefile. + +# Find a good install program. We prefer a C program (faster), +# so one script is as good as another. But avoid the broken or +# incompatible versions: +# SysV /etc/install, /usr/sbin/install +# SunOS /usr/etc/install +# IRIX /sbin/install +# AIX /bin/install +# AmigaOS /C/install, which installs bootblocks on floppy discs +# AIX 4 /usr/bin/installbsd, which doesn't work without a -g flag +# AFS /usr/afsws/bin/install, which mishandles nonexistent args +# SVR4 /usr/ucb/install, which tries to use the nonexistent group "staff" +# OS/2's system install, which has a completely different semantic +# ./install, which can be erroneously created by make from ./install.sh. +# Reject install programs that cannot install multiple files. +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for a BSD-compatible install" >&5 +$as_echo_n "checking for a BSD-compatible install... " >&6; } +if test -z "$INSTALL"; then +if ${ac_cv_path_install+:} false; then : + $as_echo_n "(cached) " >&6 +else + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + # Account for people who put trailing slashes in PATH elements. +case $as_dir/ in #(( + ./ | .// | /[cC]/* | \ + /etc/* | /usr/sbin/* | /usr/etc/* | /sbin/* | /usr/afsws/bin/* | \ + ?:[\\/]os2[\\/]install[\\/]* | ?:[\\/]OS2[\\/]INSTALL[\\/]* | \ + /usr/ucb/* ) ;; + *) + # OSF1 and SCO ODT 3.0 have their own names for install. + # Don't use installbsd from OSF since it installs stuff as root + # by default. + for ac_prog in ginstall scoinst install; do + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_prog$ac_exec_ext"; then + if test $ac_prog = install && + grep dspmsg "$as_dir/$ac_prog$ac_exec_ext" >/dev/null 2>&1; then + # AIX install. It has an incompatible calling convention. + : + elif test $ac_prog = install && + grep pwplus "$as_dir/$ac_prog$ac_exec_ext" >/dev/null 2>&1; then + # program-specific install script used by HP pwplus--don't use. + : + else + rm -rf conftest.one conftest.two conftest.dir + echo one > conftest.one + echo two > conftest.two + mkdir conftest.dir + if "$as_dir/$ac_prog$ac_exec_ext" -c conftest.one conftest.two "`pwd`/conftest.dir" && + test -s conftest.one && test -s conftest.two && + test -s conftest.dir/conftest.one && + test -s conftest.dir/conftest.two + then + ac_cv_path_install="$as_dir/$ac_prog$ac_exec_ext -c" + break 3 + fi + fi + fi + done + done + ;; +esac + + done +IFS=$as_save_IFS + +rm -rf conftest.one conftest.two conftest.dir + +fi + if test "${ac_cv_path_install+set}" = set; then + INSTALL=$ac_cv_path_install + else + # As a last resort, use the slow shell script. Don't cache a + # value for INSTALL within a source directory, because that will + # break other packages using the cache if that directory is + # removed, or if the value is a relative name. + INSTALL=$ac_install_sh + fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $INSTALL" >&5 +$as_echo "$INSTALL" >&6; } + +# Use test -z because SunOS4 sh mishandles braces in ${var-val}. +# It thinks the first close brace ends the variable substitution. +test -z "$INSTALL_PROGRAM" && INSTALL_PROGRAM='${INSTALL}' + +test -z "$INSTALL_SCRIPT" && INSTALL_SCRIPT='${INSTALL}' + +test -z "$INSTALL_DATA" && INSTALL_DATA='${INSTALL} -m 644' + + + + # Configure command line option + + # Check whether --enable-stow was given. +if test "${enable_stow+set}" = set; then : + enableval=$enable_stow; enable_stow="yes" +else + enable_stow="no" +fi + + + + + # Environment variables + + + + + # Check for install script + + + + +#------------------------------------------------------------------------- +# Checks for header files +#------------------------------------------------------------------------- + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for ANSI C header files" >&5 +$as_echo_n "checking for ANSI C header files... " >&6; } +if ${ac_cv_header_stdc+:} false; then : + $as_echo_n "(cached) " >&6 +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include <stdlib.h> +#include <stdarg.h> +#include <string.h> +#include <float.h> + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_cxx_try_compile "$LINENO"; then : + ac_cv_header_stdc=yes +else + ac_cv_header_stdc=no +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + +if test $ac_cv_header_stdc = yes; then + # SunOS 4.x string.h does not declare mem*, contrary to ANSI. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include <string.h> + +_ACEOF +if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | + $EGREP "memchr" >/dev/null 2>&1; then : + +else + ac_cv_header_stdc=no +fi +rm -f conftest* + +fi + +if test $ac_cv_header_stdc = yes; then + # ISC 2.0.2 stdlib.h does not declare free, contrary to ANSI. + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include <stdlib.h> + +_ACEOF +if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | + $EGREP "free" >/dev/null 2>&1; then : + +else + ac_cv_header_stdc=no +fi +rm -f conftest* + +fi + +if test $ac_cv_header_stdc = yes; then + # /bin/cc in Irix-4.0.5 gets non-ANSI ctype macros unless using -ansi. + if test "$cross_compiling" = yes; then : + : +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include <ctype.h> +#include <stdlib.h> +#if ((' ' & 0x0FF) == 0x020) +# define ISLOWER(c) ('a' <= (c) && (c) <= 'z') +# define TOUPPER(c) (ISLOWER(c) ? 'A' + ((c) - 'a') : (c)) +#else +# define ISLOWER(c) \ + (('a' <= (c) && (c) <= 'i') \ + || ('j' <= (c) && (c) <= 'r') \ + || ('s' <= (c) && (c) <= 'z')) +# define TOUPPER(c) (ISLOWER(c) ? ((c) | 0x40) : (c)) +#endif + +#define XOR(e, f) (((e) && !(f)) || (!(e) && (f))) +int +main () +{ + int i; + for (i = 0; i < 256; i++) + if (XOR (islower (i), ISLOWER (i)) + || toupper (i) != TOUPPER (i)) + return 2; + return 0; +} +_ACEOF +if ac_fn_cxx_try_run "$LINENO"; then : + +else + ac_cv_header_stdc=no +fi +rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext \ + conftest.$ac_objext conftest.beam conftest.$ac_ext +fi + +fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_header_stdc" >&5 +$as_echo "$ac_cv_header_stdc" >&6; } +if test $ac_cv_header_stdc = yes; then + +$as_echo "#define STDC_HEADERS 1" >>confdefs.h + +fi + + +#------------------------------------------------------------------------- +# Checks for type +#------------------------------------------------------------------------- + +ac_fn_cxx_check_type "$LINENO" "__int128_t" "ac_cv_type___int128_t" "$ac_includes_default" +if test "x$ac_cv_type___int128_t" = xyes; then : + HAVE_INT128=yes + +fi + + +#------------------------------------------------------------------------- +# Default compiler flags +#------------------------------------------------------------------------- + + + + + +for flag in -Wl,--export-dynamic; do + as_CACHEVAR=`$as_echo "ax_cv_check_ldflags__$flag" | $as_tr_sh` +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether the linker accepts $flag" >&5 +$as_echo_n "checking whether the linker accepts $flag... " >&6; } +if eval \${$as_CACHEVAR+:} false; then : + $as_echo_n "(cached) " >&6 +else + + ax_check_save_flags=$LDFLAGS + LDFLAGS="$LDFLAGS $flag" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_cxx_try_link "$LINENO"; then : + eval "$as_CACHEVAR=yes" +else + eval "$as_CACHEVAR=no" +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext + LDFLAGS=$ax_check_save_flags +fi +eval ac_res=\$$as_CACHEVAR + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } +if eval test \"x\$"$as_CACHEVAR"\" = x"yes"; then : + +if ${LDFLAGS+:} false; then : + + case " $LDFLAGS " in #( + *" $flag "*) : + { { $as_echo "$as_me:${as_lineno-$LINENO}: : LDFLAGS already contains \$flag"; } >&5 + (: LDFLAGS already contains $flag) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } ;; #( + *) : + + as_fn_append LDFLAGS " $flag" + { { $as_echo "$as_me:${as_lineno-$LINENO}: : LDFLAGS=\"\$LDFLAGS\""; } >&5 + (: LDFLAGS="$LDFLAGS") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + ;; +esac + +else + + LDFLAGS=$flag + { { $as_echo "$as_me:${as_lineno-$LINENO}: : LDFLAGS=\"\$LDFLAGS\""; } >&5 + (: LDFLAGS="$LDFLAGS") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + +fi + +else + : +fi + +done + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether C++ compiler accepts -relocatable-pch" >&5 +$as_echo_n "checking whether C++ compiler accepts -relocatable-pch... " >&6; } +if ${ax_cv_check_cxxflags___relocatable_pch+:} false; then : + $as_echo_n "(cached) " >&6 +else + + ax_check_save_flags=$CXXFLAGS + CXXFLAGS="$CXXFLAGS -relocatable-pch" + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if ac_fn_cxx_try_compile "$LINENO"; then : + ax_cv_check_cxxflags___relocatable_pch=yes +else + ax_cv_check_cxxflags___relocatable_pch=no +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + CXXFLAGS=$ax_check_save_flags +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ax_cv_check_cxxflags___relocatable_pch" >&5 +$as_echo "$ax_cv_check_cxxflags___relocatable_pch" >&6; } +if test "x$ax_cv_check_cxxflags___relocatable_pch" = xyes; then : + HAVE_CLANG_PCH=yes + +else + : +fi + + +#------------------------------------------------------------------------- +# MCPPBS subproject list +#------------------------------------------------------------------------- +# Order list so that subprojects only depend on those listed earlier. +# The '*' suffix indicates an optional subproject. The '**' suffix +# indicates an optional subproject which is also the name of a group. + + + + # Add command line argument to enable all optional subprojects + + # Check whether --enable-optional-subprojects was given. +if test "${enable_optional_subprojects+set}" = set; then : + enableval=$enable_optional_subprojects; +fi + + + # Loop through the subprojects given in the macro argument + + + + # Determine if this is a required or an optional subproject + + + + # Determine if there is a group with the same name + + + + # Create variations of the subproject name suitable for use as a CPP + # enabled define, a shell enabled variable, and a shell function + + + + + + + + + + + + # Add subproject to our running list + + subprojects="$subprojects fesvr" + + # Process the subproject appropriately. If enabled add it to the + # $enabled_subprojects running shell variable, set a + # SUBPROJECT_ENABLED C define, and include the appropriate + # 'subproject.ac'. + + + { $as_echo "$as_me:${as_lineno-$LINENO}: configuring default subproject : fesvr" >&5 +$as_echo "$as_me: configuring default subproject : fesvr" >&6;} + ac_config_files="$ac_config_files fesvr.mk:fesvr/fesvr.mk.in" + + enable_fesvr_sproj="yes" + subprojects_enabled="$subprojects_enabled fesvr" + +$as_echo "#define FESVR_ENABLED /**/" >>confdefs.h + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for pthread_create in -lpthread" >&5 +$as_echo_n "checking for pthread_create in -lpthread... " >&6; } +if ${ac_cv_lib_pthread_pthread_create+:} false; then : + $as_echo_n "(cached) " >&6 +else + ac_check_lib_save_LIBS=$LIBS +LIBS="-lpthread $LIBS" +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +/* Override any GCC internal prototype to avoid an error. + Use char because int might match the return type of a GCC + builtin and then its argument prototype would still apply. */ +#ifdef __cplusplus +extern "C" +#endif +char pthread_create (); +int +main () +{ +return pthread_create (); + ; + return 0; +} +_ACEOF +if ac_fn_cxx_try_link "$LINENO"; then : + ac_cv_lib_pthread_pthread_create=yes +else + ac_cv_lib_pthread_pthread_create=no +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext +LIBS=$ac_check_lib_save_LIBS +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_pthread_pthread_create" >&5 +$as_echo "$ac_cv_lib_pthread_pthread_create" >&6; } +if test "x$ac_cv_lib_pthread_pthread_create" = xyes; then : + cat >>confdefs.h <<_ACEOF +#define HAVE_LIBPTHREAD 1 +_ACEOF + + LIBS="-lpthread $LIBS" + +else + as_fn_error $? "libpthread is required" "$LINENO" 5 +fi + + +ac_fn_cxx_check_member "$LINENO" "struct statx" "stx_ino" "ac_cv_member_struct_statx_stx_ino" "$ac_includes_default" +if test "x$ac_cv_member_struct_statx_stx_ino" = xyes; then : + +cat >>confdefs.h <<_ACEOF +#define HAVE_STATX 1 +_ACEOF + +fi + + +ac_fn_cxx_check_member "$LINENO" "struct statx" "stx_mnt_id" "ac_cv_member_struct_statx_stx_mnt_id" "$ac_includes_default" +if test "x$ac_cv_member_struct_statx_stx_mnt_id" = xyes; then : + +cat >>confdefs.h <<_ACEOF +#define HAVE_STATX_MNT_ID 1 +_ACEOF + +fi + + + + + + + # Determine if this is a required or an optional subproject + + + + # Determine if there is a group with the same name + + + + # Create variations of the subproject name suitable for use as a CPP + # enabled define, a shell enabled variable, and a shell function + + + + + + + + + + + + # Add subproject to our running list + + subprojects="$subprojects riscv" + + # Process the subproject appropriately. If enabled add it to the + # $enabled_subprojects running shell variable, set a + # SUBPROJECT_ENABLED C define, and include the appropriate + # 'subproject.ac'. + + + { $as_echo "$as_me:${as_lineno-$LINENO}: configuring default subproject : riscv" >&5 +$as_echo "$as_me: configuring default subproject : riscv" >&6;} + ac_config_files="$ac_config_files riscv.mk:riscv/riscv.mk.in" + + enable_riscv_sproj="yes" + subprojects_enabled="$subprojects_enabled riscv" + +$as_echo "#define RISCV_ENABLED /**/" >>confdefs.h + + ac_ext=cpp +ac_cpp='$CXXCPP $CPPFLAGS' +ac_compile='$CXX -c $CXXFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CXX -o conftest$ac_exeext $CXXFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_cxx_compiler_gnu + + + + +# Check whether --with-boost was given. +if test "${with_boost+set}" = set; then : + withval=$with_boost; + case $withval in #( + no) : + want_boost="no";_AX_BOOST_BASE_boost_path="" ;; #( + yes) : + want_boost="yes";_AX_BOOST_BASE_boost_path="" ;; #( + *) : + want_boost="yes";_AX_BOOST_BASE_boost_path="$withval" ;; +esac + +else + want_boost="yes" +fi + + + + +# Check whether --with-boost-libdir was given. +if test "${with_boost_libdir+set}" = set; then : + withval=$with_boost_libdir; + if test -d "$withval"; then : + _AX_BOOST_BASE_boost_lib_path="$withval" +else + as_fn_error $? "--with-boost-libdir expected directory name" "$LINENO" 5 +fi + +else + _AX_BOOST_BASE_boost_lib_path="" +fi + + +BOOST_LDFLAGS="" +BOOST_CPPFLAGS="" +if test "x$want_boost" = "xyes"; then : + + + if test "x1.53" = "x"; then : + _AX_BOOST_BASE_TONUMERICVERSION_req="1.20.0" +else + _AX_BOOST_BASE_TONUMERICVERSION_req="1.53" +fi + _AX_BOOST_BASE_TONUMERICVERSION_req_shorten=`expr $_AX_BOOST_BASE_TONUMERICVERSION_req : '\([0-9]*\.[0-9]*\)'` + _AX_BOOST_BASE_TONUMERICVERSION_req_major=`expr $_AX_BOOST_BASE_TONUMERICVERSION_req : '\([0-9]*\)'` + if test "x$_AX_BOOST_BASE_TONUMERICVERSION_req_major" = "x"; then : + as_fn_error $? "You should at least specify libboost major version" "$LINENO" 5 +fi + _AX_BOOST_BASE_TONUMERICVERSION_req_minor=`expr $_AX_BOOST_BASE_TONUMERICVERSION_req : '[0-9]*\.\([0-9]*\)'` + if test "x$_AX_BOOST_BASE_TONUMERICVERSION_req_minor" = "x"; then : + _AX_BOOST_BASE_TONUMERICVERSION_req_minor="0" +fi + _AX_BOOST_BASE_TONUMERICVERSION_req_sub_minor=`expr $_AX_BOOST_BASE_TONUMERICVERSION_req : '[0-9]*\.[0-9]*\.\([0-9]*\)'` + if test "X$_AX_BOOST_BASE_TONUMERICVERSION_req_sub_minor" = "X"; then : + _AX_BOOST_BASE_TONUMERICVERSION_req_sub_minor="0" +fi + _AX_BOOST_BASE_TONUMERICVERSION_RET=`expr $_AX_BOOST_BASE_TONUMERICVERSION_req_major \* 100000 \+ $_AX_BOOST_BASE_TONUMERICVERSION_req_minor \* 100 \+ $_AX_BOOST_BASE_TONUMERICVERSION_req_sub_minor` + WANT_BOOST_VERSION=$_AX_BOOST_BASE_TONUMERICVERSION_RET + + succeeded=no + + + + case ${host_cpu} in #( + x86_64) : + libsubdirs="lib64 libx32 lib lib64" ;; #( + mips*64*) : + libsubdirs="lib64 lib32 lib lib64" ;; #( + ppc64|powerpc64|s390x|sparc64|aarch64|ppc64le|powerpc64le|riscv64|e2k) : + libsubdirs="lib64 lib lib64" ;; #( + *) : + libsubdirs="lib" + ;; +esac + + case ${host_cpu} in #( + i?86) : + multiarch_libsubdir="lib/i386-${host_os}" ;; #( + armv7l) : + multiarch_libsubdir="lib/arm-${host_os}" ;; #( + *) : + multiarch_libsubdir="lib/${host_cpu}-${host_os}" + ;; +esac + + if test "x$_AX_BOOST_BASE_boost_path" != "x"; then : + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for boostlib >= 1.53 ($WANT_BOOST_VERSION) includes in \"$_AX_BOOST_BASE_boost_path/include\"" >&5 +$as_echo_n "checking for boostlib >= 1.53 ($WANT_BOOST_VERSION) includes in \"$_AX_BOOST_BASE_boost_path/include\"... " >&6; } + if test -d "$_AX_BOOST_BASE_boost_path/include" && test -r "$_AX_BOOST_BASE_boost_path/include"; then : + + { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 +$as_echo "yes" >&6; } + BOOST_CPPFLAGS="-I$_AX_BOOST_BASE_boost_path/include" + for _AX_BOOST_BASE_boost_path_tmp in $multiarch_libsubdir $libsubdirs; do + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for boostlib >= 1.53 ($WANT_BOOST_VERSION) lib path in \"$_AX_BOOST_BASE_boost_path/$_AX_BOOST_BASE_boost_path_tmp\"" >&5 +$as_echo_n "checking for boostlib >= 1.53 ($WANT_BOOST_VERSION) lib path in \"$_AX_BOOST_BASE_boost_path/$_AX_BOOST_BASE_boost_path_tmp\"... " >&6; } + if test -d "$_AX_BOOST_BASE_boost_path/$_AX_BOOST_BASE_boost_path_tmp" && test -r "$_AX_BOOST_BASE_boost_path/$_AX_BOOST_BASE_boost_path_tmp" ; then : + + { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 +$as_echo "yes" >&6; } + BOOST_LDFLAGS="-L$_AX_BOOST_BASE_boost_path/$_AX_BOOST_BASE_boost_path_tmp"; + break; + +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + done +else + + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + +else + + if test X"$cross_compiling" = Xyes; then + search_libsubdirs=$multiarch_libsubdir + else + search_libsubdirs="$multiarch_libsubdir $libsubdirs" + fi + for _AX_BOOST_BASE_boost_path_tmp in /usr /usr/local /opt /opt/local ; do + if test -d "$_AX_BOOST_BASE_boost_path_tmp/include/boost" && test -r "$_AX_BOOST_BASE_boost_path_tmp/include/boost" ; then + for libsubdir in $search_libsubdirs ; do + if ls "$_AX_BOOST_BASE_boost_path_tmp/$libsubdir/libboost_"* >/dev/null 2>&1 ; then break; fi + done + BOOST_LDFLAGS="-L$_AX_BOOST_BASE_boost_path_tmp/$libsubdir" + BOOST_CPPFLAGS="-I$_AX_BOOST_BASE_boost_path_tmp/include" + break; + fi + done + +fi + + if test "x$_AX_BOOST_BASE_boost_lib_path" != "x"; then : + BOOST_LDFLAGS="-L$_AX_BOOST_BASE_boost_lib_path" +fi + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for boostlib >= 1.53 ($WANT_BOOST_VERSION)" >&5 +$as_echo_n "checking for boostlib >= 1.53 ($WANT_BOOST_VERSION)... " >&6; } + CPPFLAGS_SAVED="$CPPFLAGS" + CPPFLAGS="$CPPFLAGS $BOOST_CPPFLAGS" + export CPPFLAGS + + LDFLAGS_SAVED="$LDFLAGS" + LDFLAGS="$LDFLAGS $BOOST_LDFLAGS" + export LDFLAGS + + + ac_ext=cpp +ac_cpp='$CXXCPP $CPPFLAGS' +ac_compile='$CXX -c $CXXFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CXX -o conftest$ac_exeext $CXXFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_cxx_compiler_gnu + + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +#include <boost/version.hpp> + +int +main () +{ + +(void) ((void)sizeof(char[1 - 2*!!((BOOST_VERSION) < ($WANT_BOOST_VERSION))])); + + ; + return 0; +} +_ACEOF +if ac_fn_cxx_try_compile "$LINENO"; then : + + { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 +$as_echo "yes" >&6; } + succeeded=yes + found_system=yes + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + ac_ext=cpp +ac_cpp='$CXXCPP $CPPFLAGS' +ac_compile='$CXX -c $CXXFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CXX -o conftest$ac_exeext $CXXFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_cxx_compiler_gnu + + + + + if test "x$succeeded" != "xyes" ; then + CPPFLAGS="$CPPFLAGS_SAVED" + LDFLAGS="$LDFLAGS_SAVED" + BOOST_CPPFLAGS= + if test -z "$_AX_BOOST_BASE_boost_lib_path" ; then + BOOST_LDFLAGS= + fi + _version=0 + if test -n "$_AX_BOOST_BASE_boost_path" ; then + if test -d "$_AX_BOOST_BASE_boost_path" && test -r "$_AX_BOOST_BASE_boost_path"; then + for i in `ls -d $_AX_BOOST_BASE_boost_path/include/boost-* 2>/dev/null`; do + _version_tmp=`echo $i | sed "s#$_AX_BOOST_BASE_boost_path##" | sed 's/\/include\/boost-//' | sed 's/_/./'` + V_CHECK=`expr $_version_tmp \> $_version` + if test "x$V_CHECK" = "x1" ; then + _version=$_version_tmp + fi + VERSION_UNDERSCORE=`echo $_version | sed 's/\./_/'` + BOOST_CPPFLAGS="-I$_AX_BOOST_BASE_boost_path/include/boost-$VERSION_UNDERSCORE" + done + if test -z "$BOOST_CPPFLAGS"; then + if test -d "$_AX_BOOST_BASE_boost_path/boost" && test -r "$_AX_BOOST_BASE_boost_path/boost"; then + BOOST_CPPFLAGS="-I$_AX_BOOST_BASE_boost_path" + fi + fi + if test -n "$BOOST_CPPFLAGS" && test -z "$BOOST_LDFLAGS"; then + for libsubdir in $libsubdirs ; do + if ls "$_AX_BOOST_BASE_boost_path/$libsubdir/libboost_"* >/dev/null 2>&1 ; then break; fi + done + BOOST_LDFLAGS="-L$_AX_BOOST_BASE_boost_path/$libsubdir" + fi + fi + else + if test "x$cross_compiling" != "xyes" ; then + for _AX_BOOST_BASE_boost_path in /usr /usr/local /opt /opt/local ; do + if test -d "$_AX_BOOST_BASE_boost_path" && test -r "$_AX_BOOST_BASE_boost_path" ; then + for i in `ls -d $_AX_BOOST_BASE_boost_path/include/boost-* 2>/dev/null`; do + _version_tmp=`echo $i | sed "s#$_AX_BOOST_BASE_boost_path##" | sed 's/\/include\/boost-//' | sed 's/_/./'` + V_CHECK=`expr $_version_tmp \> $_version` + if test "x$V_CHECK" = "x1" ; then + _version=$_version_tmp + best_path=$_AX_BOOST_BASE_boost_path + fi + done + fi + done + + VERSION_UNDERSCORE=`echo $_version | sed 's/\./_/'` + BOOST_CPPFLAGS="-I$best_path/include/boost-$VERSION_UNDERSCORE" + if test -z "$_AX_BOOST_BASE_boost_lib_path" ; then + for libsubdir in $libsubdirs ; do + if ls "$best_path/$libsubdir/libboost_"* >/dev/null 2>&1 ; then break; fi + done + BOOST_LDFLAGS="-L$best_path/$libsubdir" + fi + fi + + if test -n "$BOOST_ROOT" ; then + for libsubdir in $libsubdirs ; do + if ls "$BOOST_ROOT/stage/$libsubdir/libboost_"* >/dev/null 2>&1 ; then break; fi + done + if test -d "$BOOST_ROOT" && test -r "$BOOST_ROOT" && test -d "$BOOST_ROOT/stage/$libsubdir" && test -r "$BOOST_ROOT/stage/$libsubdir"; then + version_dir=`expr //$BOOST_ROOT : '.*/\(.*\)'` + stage_version=`echo $version_dir | sed 's/boost_//' | sed 's/_/./g'` + stage_version_shorten=`expr $stage_version : '\([0-9]*\.[0-9]*\)'` + V_CHECK=`expr $stage_version_shorten \>\= $_version` + if test "x$V_CHECK" = "x1" && test -z "$_AX_BOOST_BASE_boost_lib_path" ; then + { $as_echo "$as_me:${as_lineno-$LINENO}: We will use a staged boost library from $BOOST_ROOT" >&5 +$as_echo "$as_me: We will use a staged boost library from $BOOST_ROOT" >&6;} + BOOST_CPPFLAGS="-I$BOOST_ROOT" + BOOST_LDFLAGS="-L$BOOST_ROOT/stage/$libsubdir" + fi + fi + fi + fi + + CPPFLAGS="$CPPFLAGS $BOOST_CPPFLAGS" + export CPPFLAGS + LDFLAGS="$LDFLAGS $BOOST_LDFLAGS" + export LDFLAGS + + ac_ext=cpp +ac_cpp='$CXXCPP $CPPFLAGS' +ac_compile='$CXX -c $CXXFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CXX -o conftest$ac_exeext $CXXFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_cxx_compiler_gnu + + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +#include <boost/version.hpp> + +int +main () +{ + +(void) ((void)sizeof(char[1 - 2*!!((BOOST_VERSION) < ($WANT_BOOST_VERSION))])); + + ; + return 0; +} +_ACEOF +if ac_fn_cxx_try_compile "$LINENO"; then : + + { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 +$as_echo "yes" >&6; } + succeeded=yes + found_system=yes + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + ac_ext=cpp +ac_cpp='$CXXCPP $CPPFLAGS' +ac_compile='$CXX -c $CXXFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CXX -o conftest$ac_exeext $CXXFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_cxx_compiler_gnu + + fi + + if test "x$succeeded" != "xyes" ; then + if test "x$_version" = "x0" ; then + { $as_echo "$as_me:${as_lineno-$LINENO}: We could not detect the boost libraries (version 1.53 or higher). If you have a staged boost library (still not installed) please specify \$BOOST_ROOT in your environment and do not give a PATH to --with-boost option. If you are sure you have boost installed, then check your version number looking in <boost/version.hpp>. See http://randspringer.de/boost for more documentation." >&5 +$as_echo "$as_me: We could not detect the boost libraries (version 1.53 or higher). If you have a staged boost library (still not installed) please specify \$BOOST_ROOT in your environment and do not give a PATH to --with-boost option. If you are sure you have boost installed, then check your version number looking in <boost/version.hpp>. See http://randspringer.de/boost for more documentation." >&6;} + else + { $as_echo "$as_me:${as_lineno-$LINENO}: Your boost libraries seems to old (version $_version)." >&5 +$as_echo "$as_me: Your boost libraries seems to old (version $_version)." >&6;} + fi + # execute ACTION-IF-NOT-FOUND (if present): + : + else + +$as_echo "#define HAVE_BOOST /**/" >>confdefs.h + + # execute ACTION-IF-FOUND (if present): + : + fi + + CPPFLAGS="$CPPFLAGS_SAVED" + LDFLAGS="$LDFLAGS_SAVED" + + +fi + + + + + +# Check whether --with-boost-asio was given. +if test "${with_boost_asio+set}" = set; then : + withval=$with_boost_asio; + if test "$withval" = "no"; then + want_boost="no" + elif test "$withval" = "yes"; then + want_boost="yes" + ax_boost_user_asio_lib="" + else + want_boost="yes" + ax_boost_user_asio_lib="$withval" + fi + +else + want_boost="yes" + +fi + + + if test "x$want_boost" = "xyes"; then + + CPPFLAGS_SAVED="$CPPFLAGS" + CPPFLAGS="$CPPFLAGS $BOOST_CPPFLAGS" + export CPPFLAGS + + LDFLAGS_SAVED="$LDFLAGS" + LDFLAGS="$LDFLAGS $BOOST_LDFLAGS" + export LDFLAGS + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether the Boost::ASIO library is available" >&5 +$as_echo_n "checking whether the Boost::ASIO library is available... " >&6; } +if ${ax_cv_boost_asio+:} false; then : + $as_echo_n "(cached) " >&6 +else + ac_ext=cpp +ac_cpp='$CXXCPP $CPPFLAGS' +ac_compile='$CXX -c $CXXFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CXX -o conftest$ac_exeext $CXXFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_cxx_compiler_gnu + + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + #include <boost/asio.hpp> + +int +main () +{ + + + boost::asio::io_service io; + boost::system::error_code timer_result; + boost::asio::deadline_timer t(io); + t.cancel(); + io.run_one(); + return 0; + + ; + return 0; +} +_ACEOF +if ac_fn_cxx_try_compile "$LINENO"; then : + ax_cv_boost_asio=yes +else + ax_cv_boost_asio=no +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + ac_ext=cpp +ac_cpp='$CXXCPP $CPPFLAGS' +ac_compile='$CXX -c $CXXFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CXX -o conftest$ac_exeext $CXXFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_cxx_compiler_gnu + + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ax_cv_boost_asio" >&5 +$as_echo "$ax_cv_boost_asio" >&6; } + if test "x$ax_cv_boost_asio" = "xyes"; then + +$as_echo "#define HAVE_BOOST_ASIO /**/" >>confdefs.h + + BN=boost_system + BOOSTLIBDIR=`echo $BOOST_LDFLAGS | sed -e 's/[^\/]*//'` + if test "x$ax_boost_user_asio_lib" = "x"; then + for ax_lib in `ls $BOOSTLIBDIR/libboost_system*.so* $BOOSTLIBDIR/libboost_system*.dylib* $BOOSTLIBDIR/libboost_system*.a* 2>/dev/null | sed 's,.*/,,' | sed -e 's;^lib\(boost_system.*\)\.so.*$;\1;' -e 's;^lib\(boost_system.*\)\.dylib.*$;\1;' -e 's;^lib\(boost_system.*\)\.a.*$;\1;' ` ; do + as_ac_Lib=`$as_echo "ac_cv_lib_$ax_lib''_main" | $as_tr_sh` +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for main in -l$ax_lib" >&5 +$as_echo_n "checking for main in -l$ax_lib... " >&6; } +if eval \${$as_ac_Lib+:} false; then : + $as_echo_n "(cached) " >&6 +else + ac_check_lib_save_LIBS=$LIBS +LIBS="-l$ax_lib $LIBS" +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + + +int +main () +{ +return main (); + ; + return 0; +} +_ACEOF +if ac_fn_cxx_try_link "$LINENO"; then : + eval "$as_ac_Lib=yes" +else + eval "$as_ac_Lib=no" +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext +LIBS=$ac_check_lib_save_LIBS +fi +eval ac_res=\$$as_ac_Lib + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } +if eval test \"x\$"$as_ac_Lib"\" = x"yes"; then : + BOOST_ASIO_LIB="-l$ax_lib" link_thread="yes" break +else + link_thread="no" +fi + + done + else + for ax_lib in $ax_boost_user_asio_lib $BN-$ax_boost_user_asio_lib; do + as_ac_Lib=`$as_echo "ac_cv_lib_$ax_lib''_main" | $as_tr_sh` +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for main in -l$ax_lib" >&5 +$as_echo_n "checking for main in -l$ax_lib... " >&6; } +if eval \${$as_ac_Lib+:} false; then : + $as_echo_n "(cached) " >&6 +else + ac_check_lib_save_LIBS=$LIBS +LIBS="-l$ax_lib $LIBS" +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + + +int +main () +{ +return main (); + ; + return 0; +} +_ACEOF +if ac_fn_cxx_try_link "$LINENO"; then : + eval "$as_ac_Lib=yes" +else + eval "$as_ac_Lib=no" +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext +LIBS=$ac_check_lib_save_LIBS +fi +eval ac_res=\$$as_ac_Lib + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } +if eval test \"x\$"$as_ac_Lib"\" = x"yes"; then : + BOOST_ASIO_LIB="-l$ax_lib" link_asio="yes" break +else + link_asio="no" +fi + + done + + fi + if test "x$ax_lib" = "x"; then + as_fn_error $? "Could not find a version of the Boost::Asio library!" "$LINENO" 5 + fi + if test "x$link_asio" = "xno"; then + as_fn_error $? "Could not link against $ax_lib !" "$LINENO" 5 + fi + fi + + CPPFLAGS="$CPPFLAGS_SAVED" + LDFLAGS="$LDFLAGS_SAVED" + fi + + + +# Check whether --with-boost-regex was given. +if test "${with_boost_regex+set}" = set; then : + withval=$with_boost_regex; + if test "$withval" = "no"; then + want_boost="no" + elif test "$withval" = "yes"; then + want_boost="yes" + ax_boost_user_regex_lib="" + else + want_boost="yes" + ax_boost_user_regex_lib="$withval" + fi + +else + want_boost="yes" + +fi + + + if test "x$want_boost" = "xyes"; then + + CPPFLAGS_SAVED="$CPPFLAGS" + CPPFLAGS="$CPPFLAGS $BOOST_CPPFLAGS" + export CPPFLAGS + + LDFLAGS_SAVED="$LDFLAGS" + LDFLAGS="$LDFLAGS $BOOST_LDFLAGS" + export LDFLAGS + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether the Boost::Regex library is available" >&5 +$as_echo_n "checking whether the Boost::Regex library is available... " >&6; } +if ${ax_cv_boost_regex+:} false; then : + $as_echo_n "(cached) " >&6 +else + ac_ext=cpp +ac_cpp='$CXXCPP $CPPFLAGS' +ac_compile='$CXX -c $CXXFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CXX -o conftest$ac_exeext $CXXFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_cxx_compiler_gnu + + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include <boost/regex.hpp> + +int +main () +{ +boost::regex r(); return 0; + ; + return 0; +} +_ACEOF +if ac_fn_cxx_try_compile "$LINENO"; then : + ax_cv_boost_regex=yes +else + ax_cv_boost_regex=no +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + ac_ext=cpp +ac_cpp='$CXXCPP $CPPFLAGS' +ac_compile='$CXX -c $CXXFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CXX -o conftest$ac_exeext $CXXFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_cxx_compiler_gnu + + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ax_cv_boost_regex" >&5 +$as_echo "$ax_cv_boost_regex" >&6; } + if test "x$ax_cv_boost_regex" = "xyes"; then + +$as_echo "#define HAVE_BOOST_REGEX /**/" >>confdefs.h + + BOOSTLIBDIR=`echo $BOOST_LDFLAGS | sed -e 's/[^\/]*//'` + if test "x$ax_boost_user_regex_lib" = "x"; then + for libextension in `ls $BOOSTLIBDIR/libboost_regex*.so* $BOOSTLIBDIR/libboost_regex*.dylib* $BOOSTLIBDIR/libboost_regex*.a* 2>/dev/null | sed 's,.*/,,' | sed -e 's;^lib\(boost_regex.*\)\.so.*$;\1;' -e 's;^lib\(boost_regex.*\)\.dylib.*;\1;' -e 's;^lib\(boost_regex.*\)\.a.*$;\1;'` ; do + ax_lib=${libextension} + as_ac_Lib=`$as_echo "ac_cv_lib_$ax_lib''_exit" | $as_tr_sh` +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for exit in -l$ax_lib" >&5 +$as_echo_n "checking for exit in -l$ax_lib... " >&6; } +if eval \${$as_ac_Lib+:} false; then : + $as_echo_n "(cached) " >&6 +else + ac_check_lib_save_LIBS=$LIBS +LIBS="-l$ax_lib $LIBS" +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +/* Override any GCC internal prototype to avoid an error. + Use char because int might match the return type of a GCC + builtin and then its argument prototype would still apply. */ +#ifdef __cplusplus +extern "C" +#endif +char exit (); +int +main () +{ +return exit (); + ; + return 0; +} +_ACEOF +if ac_fn_cxx_try_link "$LINENO"; then : + eval "$as_ac_Lib=yes" +else + eval "$as_ac_Lib=no" +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext +LIBS=$ac_check_lib_save_LIBS +fi +eval ac_res=\$$as_ac_Lib + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } +if eval test \"x\$"$as_ac_Lib"\" = x"yes"; then : + BOOST_REGEX_LIB="-l$ax_lib"; link_regex="yes"; break +else + link_regex="no" +fi + + done + if test "x$link_regex" != "xyes"; then + for libextension in `ls $BOOSTLIBDIR/boost_regex*.dll* $BOOSTLIBDIR/boost_regex*.a* 2>/dev/null | sed 's,.*/,,' | sed -e 's;^\(boost_regex.*\)\.dll.*$;\1;' -e 's;^\(boost_regex.*\)\.a.*$;\1;'` ; do + ax_lib=${libextension} + as_ac_Lib=`$as_echo "ac_cv_lib_$ax_lib''_exit" | $as_tr_sh` +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for exit in -l$ax_lib" >&5 +$as_echo_n "checking for exit in -l$ax_lib... " >&6; } +if eval \${$as_ac_Lib+:} false; then : + $as_echo_n "(cached) " >&6 +else + ac_check_lib_save_LIBS=$LIBS +LIBS="-l$ax_lib $LIBS" +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +/* Override any GCC internal prototype to avoid an error. + Use char because int might match the return type of a GCC + builtin and then its argument prototype would still apply. */ +#ifdef __cplusplus +extern "C" +#endif +char exit (); +int +main () +{ +return exit (); + ; + return 0; +} +_ACEOF +if ac_fn_cxx_try_link "$LINENO"; then : + eval "$as_ac_Lib=yes" +else + eval "$as_ac_Lib=no" +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext +LIBS=$ac_check_lib_save_LIBS +fi +eval ac_res=\$$as_ac_Lib + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } +if eval test \"x\$"$as_ac_Lib"\" = x"yes"; then : + BOOST_REGEX_LIB="-l$ax_lib"; link_regex="yes"; break +else + link_regex="no" +fi + + done + fi + + else + for ax_lib in $ax_boost_user_regex_lib boost_regex-$ax_boost_user_regex_lib; do + as_ac_Lib=`$as_echo "ac_cv_lib_$ax_lib''_main" | $as_tr_sh` +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for main in -l$ax_lib" >&5 +$as_echo_n "checking for main in -l$ax_lib... " >&6; } +if eval \${$as_ac_Lib+:} false; then : + $as_echo_n "(cached) " >&6 +else + ac_check_lib_save_LIBS=$LIBS +LIBS="-l$ax_lib $LIBS" +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + + +int +main () +{ +return main (); + ; + return 0; +} +_ACEOF +if ac_fn_cxx_try_link "$LINENO"; then : + eval "$as_ac_Lib=yes" +else + eval "$as_ac_Lib=no" +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext +LIBS=$ac_check_lib_save_LIBS +fi +eval ac_res=\$$as_ac_Lib + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } +if eval test \"x\$"$as_ac_Lib"\" = x"yes"; then : + BOOST_REGEX_LIB="-l$ax_lib"; link_regex="yes"; break +else + link_regex="no" +fi + + done + fi + if test "x$ax_lib" = "x"; then + as_fn_error $? "Could not find a version of the Boost::Regex library!" "$LINENO" 5 + fi + if test "x$link_regex" != "xyes"; then + as_fn_error $? "Could not link against $ax_lib !" "$LINENO" 5 + fi + fi + + CPPFLAGS="$CPPFLAGS_SAVED" + LDFLAGS="$LDFLAGS_SAVED" + fi + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for main in -lboost_system" >&5 +$as_echo_n "checking for main in -lboost_system... " >&6; } +if ${ac_cv_lib_boost_system_main+:} false; then : + $as_echo_n "(cached) " >&6 +else + ac_check_lib_save_LIBS=$LIBS +LIBS="-lboost_system $LIBS" +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + + +int +main () +{ +return main (); + ; + return 0; +} +_ACEOF +if ac_fn_cxx_try_link "$LINENO"; then : + ac_cv_lib_boost_system_main=yes +else + ac_cv_lib_boost_system_main=no +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext +LIBS=$ac_check_lib_save_LIBS +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_boost_system_main" >&5 +$as_echo "$ac_cv_lib_boost_system_main" >&6; } +if test "x$ac_cv_lib_boost_system_main" = xyes; then : + cat >>confdefs.h <<_ACEOF +#define HAVE_LIBBOOST_SYSTEM 1 +_ACEOF + + LIBS="-lboost_system $LIBS" + +fi + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for main in -lboost_regex" >&5 +$as_echo_n "checking for main in -lboost_regex... " >&6; } +if ${ac_cv_lib_boost_regex_main+:} false; then : + $as_echo_n "(cached) " >&6 +else + ac_check_lib_save_LIBS=$LIBS +LIBS="-lboost_regex $LIBS" +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + + +int +main () +{ +return main (); + ; + return 0; +} +_ACEOF +if ac_fn_cxx_try_link "$LINENO"; then : + ac_cv_lib_boost_regex_main=yes +else + ac_cv_lib_boost_regex_main=no +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext +LIBS=$ac_check_lib_save_LIBS +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_boost_regex_main" >&5 +$as_echo "$ac_cv_lib_boost_regex_main" >&6; } +if test "x$ac_cv_lib_boost_regex_main" = xyes; then : + cat >>confdefs.h <<_ACEOF +#define HAVE_LIBBOOST_REGEX 1 +_ACEOF + + LIBS="-lboost_regex $LIBS" + +fi + + + +# Check whether --with-isa was given. +if test "${with_isa+set}" = set; then : + withval=$with_isa; +cat >>confdefs.h <<_ACEOF +#define DEFAULT_ISA "$withval" +_ACEOF + +else + +cat >>confdefs.h <<_ACEOF +#define DEFAULT_ISA "RV64IMAFDC_zicntr_zihpm" +_ACEOF + +fi + + + +# Check whether --with-priv was given. +if test "${with_priv+set}" = set; then : + withval=$with_priv; +cat >>confdefs.h <<_ACEOF +#define DEFAULT_PRIV "$withval" +_ACEOF + +else + +cat >>confdefs.h <<_ACEOF +#define DEFAULT_PRIV "MSU" +_ACEOF + +fi + + + +# Check whether --with-varch was given. +if test "${with_varch+set}" = set; then : + withval=$with_varch; +cat >>confdefs.h <<_ACEOF +#define DEFAULT_VARCH "$withval" +_ACEOF + +else + +cat >>confdefs.h <<_ACEOF +#define DEFAULT_VARCH "vlen:128,elen:64" +_ACEOF + +fi + + + +# Check whether --with-target was given. +if test "${with_target+set}" = set; then : + withval=$with_target; +cat >>confdefs.h <<_ACEOF +#define TARGET_ARCH "$withval" +_ACEOF + +else + +cat >>confdefs.h <<_ACEOF +#define TARGET_ARCH "riscv64-unknown-elf" +_ACEOF + +fi + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for library containing dlopen" >&5 +$as_echo_n "checking for library containing dlopen... " >&6; } +if ${ac_cv_search_dlopen+:} false; then : + $as_echo_n "(cached) " >&6 +else + ac_func_search_save_LIBS=$LIBS +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +/* Override any GCC internal prototype to avoid an error. + Use char because int might match the return type of a GCC + builtin and then its argument prototype would still apply. */ +#ifdef __cplusplus +extern "C" +#endif +char dlopen (); +int +main () +{ +return dlopen (); + ; + return 0; +} +_ACEOF +for ac_lib in '' dl dld; do + if test -z "$ac_lib"; then + ac_res="none required" + else + ac_res=-l$ac_lib + LIBS="-l$ac_lib $ac_func_search_save_LIBS" + fi + if ac_fn_cxx_try_link "$LINENO"; then : + ac_cv_search_dlopen=$ac_res +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext + if ${ac_cv_search_dlopen+:} false; then : + break +fi +done +if ${ac_cv_search_dlopen+:} false; then : + +else + ac_cv_search_dlopen=no +fi +rm conftest.$ac_ext +LIBS=$ac_func_search_save_LIBS +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_search_dlopen" >&5 +$as_echo "$ac_cv_search_dlopen" >&6; } +ac_res=$ac_cv_search_dlopen +if test "$ac_res" != no; then : + test "$ac_res" = "none required" || LIBS="$ac_res $LIBS" + + +$as_echo "#define HAVE_DLOPEN /**/" >>confdefs.h + + HAVE_DLOPEN=yes + + +fi + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for pthread_create in -lpthread" >&5 +$as_echo_n "checking for pthread_create in -lpthread... " >&6; } +if ${ac_cv_lib_pthread_pthread_create+:} false; then : + $as_echo_n "(cached) " >&6 +else + ac_check_lib_save_LIBS=$LIBS +LIBS="-lpthread $LIBS" +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +/* Override any GCC internal prototype to avoid an error. + Use char because int might match the return type of a GCC + builtin and then its argument prototype would still apply. */ +#ifdef __cplusplus +extern "C" +#endif +char pthread_create (); +int +main () +{ +return pthread_create (); + ; + return 0; +} +_ACEOF +if ac_fn_cxx_try_link "$LINENO"; then : + ac_cv_lib_pthread_pthread_create=yes +else + ac_cv_lib_pthread_pthread_create=no +fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext +LIBS=$ac_check_lib_save_LIBS +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_pthread_pthread_create" >&5 +$as_echo "$ac_cv_lib_pthread_pthread_create" >&6; } +if test "x$ac_cv_lib_pthread_pthread_create" = xyes; then : + cat >>confdefs.h <<_ACEOF +#define HAVE_LIBPTHREAD 1 +_ACEOF + + LIBS="-lpthread $LIBS" + +else + as_fn_error $? "libpthread is required" "$LINENO" 5 +fi + + +# Check whether --enable-dual-endian was given. +if test "${enable_dual_endian+set}" = set; then : + enableval=$enable_dual_endian; +fi + +if test "x$enable_dual_endian" = "xyes"; then : + + +$as_echo "#define RISCV_ENABLE_DUAL_ENDIAN /**/" >>confdefs.h + + +fi + + + + + + # Determine if this is a required or an optional subproject + + + + # Determine if there is a group with the same name + + + + # Create variations of the subproject name suitable for use as a CPP + # enabled define, a shell enabled variable, and a shell function + + + + + + + + + + + + # Add subproject to our running list + + subprojects="$subprojects disasm" + + # Process the subproject appropriately. If enabled add it to the + # $enabled_subprojects running shell variable, set a + # SUBPROJECT_ENABLED C define, and include the appropriate + # 'subproject.ac'. + + + { $as_echo "$as_me:${as_lineno-$LINENO}: configuring default subproject : disasm" >&5 +$as_echo "$as_me: configuring default subproject : disasm" >&6;} + ac_config_files="$ac_config_files disasm.mk:disasm/disasm.mk.in" + + enable_disasm_sproj="yes" + subprojects_enabled="$subprojects_enabled disasm" + +$as_echo "#define DISASM_ENABLED /**/" >>confdefs.h + + + + + + + # Determine if this is a required or an optional subproject + + + + # Determine if there is a group with the same name + + + + # Create variations of the subproject name suitable for use as a CPP + # enabled define, a shell enabled variable, and a shell function + + + + + + + + + + + + # Add subproject to our running list + + subprojects="$subprojects customext" + + # Process the subproject appropriately. If enabled add it to the + # $enabled_subprojects running shell variable, set a + # SUBPROJECT_ENABLED C define, and include the appropriate + # 'subproject.ac'. + + + { $as_echo "$as_me:${as_lineno-$LINENO}: configuring default subproject : customext" >&5 +$as_echo "$as_me: configuring default subproject : customext" >&6;} + ac_config_files="$ac_config_files customext.mk:customext/customext.mk.in" + + enable_customext_sproj="yes" + subprojects_enabled="$subprojects_enabled customext" + +$as_echo "#define CUSTOMEXT_ENABLED /**/" >>confdefs.h + + + + + + + # Determine if this is a required or an optional subproject + + + + # Determine if there is a group with the same name + + + + # Create variations of the subproject name suitable for use as a CPP + # enabled define, a shell enabled variable, and a shell function + + + + + + + + + + + + # Add subproject to our running list + + subprojects="$subprojects fdt" + + # Process the subproject appropriately. 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The list of subprojects in a +# group should be ordered so that subprojets only depend on those listed +# earlier. Here is an example: +# +# MCPPBS_GROUP( [group-name], [sproja,sprojb,...] ) +# + +#------------------------------------------------------------------------- +# Output +#------------------------------------------------------------------------- + +ac_config_headers="$ac_config_headers config.h" + +ac_config_files="$ac_config_files Makefile" + +ac_config_files="$ac_config_files riscv-fesvr.pc" + +ac_config_files="$ac_config_files riscv-disasm.pc" + +cat >confcache <<\_ACEOF +# This file is a shell script that caches the results of configure +# tests run on this system so they can be shared between configure +# scripts and configure runs, see configure's option --config-cache. +# It is not useful on other systems. If it contains results you don't +# want to keep, you may remove or edit it. +# +# config.status only pays attention to the cache file if you give it +# the --recheck option to rerun configure. +# +# `ac_cv_env_foo' variables (set or unset) will be overridden when +# loading this file, other *unset* `ac_cv_foo' will be assigned the +# following values. + +_ACEOF + +# The following way of writing the cache mishandles newlines in values, +# but we know of no workaround that is simple, portable, and efficient. +# So, we kill variables containing newlines. +# Ultrix sh set writes to stderr and can't be redirected directly, +# and sets the high bit in the cache file unless we assign to the vars. +( + for ac_var in `(set) 2>&1 | sed -n 's/^\([a-zA-Z_][a-zA-Z0-9_]*\)=.*/\1/p'`; do + eval ac_val=\$$ac_var + case $ac_val in #( + *${as_nl}*) + case $ac_var in #( + *_cv_*) { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: cache variable $ac_var contains a newline" >&5 +$as_echo "$as_me: WARNING: cache variable $ac_var contains a newline" >&2;} ;; + esac + case $ac_var in #( + _ | IFS | as_nl) ;; #( + BASH_ARGV | BASH_SOURCE) eval $ac_var= ;; #( + *) { eval $ac_var=; unset $ac_var;} ;; + esac ;; + esac + done + + (set) 2>&1 | + case $as_nl`(ac_space=' '; set) 2>&1` in #( + *${as_nl}ac_space=\ *) + # `set' does not quote correctly, so add quotes: double-quote + # substitution turns \\\\ into \\, and sed turns \\ into \. + sed -n \ + "s/'/'\\\\''/g; + s/^\\([_$as_cr_alnum]*_cv_[_$as_cr_alnum]*\\)=\\(.*\\)/\\1='\\2'/p" + ;; #( + *) + # `set' quotes correctly as required by POSIX, so do not add quotes. + sed -n "/^[_$as_cr_alnum]*_cv_[_$as_cr_alnum]*=/p" + ;; + esac | + sort +) | + sed ' + /^ac_cv_env_/b end + t clear + :clear + s/^\([^=]*\)=\(.*[{}].*\)$/test "${\1+set}" = set || &/ + t end + s/^\([^=]*\)=\(.*\)$/\1=${\1=\2}/ + :end' >>confcache +if diff "$cache_file" confcache >/dev/null 2>&1; then :; else + if test -w "$cache_file"; then + if test "x$cache_file" != "x/dev/null"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: updating cache $cache_file" >&5 +$as_echo "$as_me: updating cache $cache_file" >&6;} + if test ! -f "$cache_file" || test -h "$cache_file"; then + cat confcache >"$cache_file" + else + case $cache_file in #( + */* | ?:*) + mv -f confcache "$cache_file"$$ && + mv -f "$cache_file"$$ "$cache_file" ;; #( + *) + mv -f confcache "$cache_file" ;; + esac + fi + fi + else + { $as_echo "$as_me:${as_lineno-$LINENO}: not updating unwritable cache $cache_file" >&5 +$as_echo "$as_me: not updating unwritable cache $cache_file" >&6;} + fi +fi +rm -f confcache + +test "x$prefix" = xNONE && prefix=$ac_default_prefix +# Let make expand exec_prefix. +test "x$exec_prefix" = xNONE && exec_prefix='${prefix}' + +DEFS=-DHAVE_CONFIG_H + +ac_libobjs= +ac_ltlibobjs= +U= +for ac_i in : $LIBOBJS; do test "x$ac_i" = x: && continue + # 1. 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Invocation command line was + + CONFIG_FILES = $CONFIG_FILES + CONFIG_HEADERS = $CONFIG_HEADERS + CONFIG_LINKS = $CONFIG_LINKS + CONFIG_COMMANDS = $CONFIG_COMMANDS + $ $0 $@ + +on `(hostname || uname -n) 2>/dev/null | sed 1q` +" + +_ACEOF + +case $ac_config_files in *" +"*) set x $ac_config_files; shift; ac_config_files=$*;; +esac + +case $ac_config_headers in *" +"*) set x $ac_config_headers; shift; ac_config_headers=$*;; +esac + + +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +# Files that config.status was made for. +config_files="$ac_config_files" +config_headers="$ac_config_headers" + +_ACEOF + +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +ac_cs_usage="\ +\`$as_me' instantiates files and other configuration actions +from templates according to the current configuration. Unless the files +and actions are specified as TAGs, all are instantiated by default. + +Usage: $0 [OPTION]... [TAG]... + + -h, --help print this help, then exit + -V, --version print version number and configuration settings, then exit + --config print configuration, then exit + -q, --quiet, --silent + do not print progress messages + -d, --debug don't remove temporary files + --recheck update $as_me by reconfiguring in the same conditions + --file=FILE[:TEMPLATE] + instantiate the configuration file FILE + --header=FILE[:TEMPLATE] + instantiate the configuration header FILE + +Configuration files: +$config_files + +Configuration headers: +$config_headers + +Report bugs to <Andrew Waterman>." + +_ACEOF +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +ac_cs_config="`$as_echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`" +ac_cs_version="\\ +RISC-V ISA Simulator config.status ? +configured by $0, generated by GNU Autoconf 2.69, + with options \\"\$ac_cs_config\\" + +Copyright (C) 2012 Free Software Foundation, Inc. +This config.status script is free software; the Free Software Foundation +gives unlimited permission to copy, distribute and modify it." + +ac_pwd='$ac_pwd' +srcdir='$srcdir' +INSTALL='$INSTALL' +test -n "\$AWK" || AWK=awk +_ACEOF + +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +# The default lists apply if the user does not specify any file. +ac_need_defaults=: +while test $# != 0 +do + case $1 in + --*=?*) + ac_option=`expr "X$1" : 'X\([^=]*\)='` + ac_optarg=`expr "X$1" : 'X[^=]*=\(.*\)'` + ac_shift=: + ;; + --*=) + ac_option=`expr "X$1" : 'X\([^=]*\)='` + ac_optarg= + ac_shift=: + ;; + *) + ac_option=$1 + ac_optarg=$2 + ac_shift=shift + ;; + esac + + case $ac_option in + # Handling of the options. + -recheck | --recheck | --rechec | --reche | --rech | --rec | --re | --r) + ac_cs_recheck=: ;; + --version | --versio | --versi | --vers | --ver | --ve | --v | -V ) + $as_echo "$ac_cs_version"; exit ;; + --config | --confi | --conf | --con | --co | --c ) + $as_echo "$ac_cs_config"; exit ;; + --debug | --debu | --deb | --de | --d | -d ) + debug=: ;; + --file | --fil | --fi | --f ) + $ac_shift + case $ac_optarg in + *\'*) ac_optarg=`$as_echo "$ac_optarg" | sed "s/'/'\\\\\\\\''/g"` ;; + '') as_fn_error $? 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"invalid argument: \`$ac_config_target'" "$LINENO" 5;; + esac +done + + +# If the user did not use the arguments to specify the items to instantiate, +# then the envvar interface is used. Set only those that are not. +# We use the long form for the default assignment because of an extremely +# bizarre bug on SunOS 4.1.3. +if $ac_need_defaults; then + test "${CONFIG_FILES+set}" = set || CONFIG_FILES=$config_files + test "${CONFIG_HEADERS+set}" = set || CONFIG_HEADERS=$config_headers +fi + +# Have a temporary directory for convenience. Make it in the build tree +# simply because there is no reason against having it here, and in addition, +# creating and moving files from /tmp can sometimes cause problems. +# Hook for its removal unless debugging. +# Note that there is a small window in which the directory will not be cleaned: +# after its creation but before its name has been assigned to `$tmp'. +$debug || +{ + tmp= ac_tmp= + trap 'exit_status=$? + : "${ac_tmp:=$tmp}" + { test ! -d "$ac_tmp" || rm -fr "$ac_tmp"; } && exit $exit_status +' 0 + trap 'as_fn_exit 1' 1 2 13 15 +} +# Create a (secure) tmp directory for tmp files. + +{ + tmp=`(umask 077 && mktemp -d "./confXXXXXX") 2>/dev/null` && + test -d "$tmp" +} || +{ + tmp=./conf$$-$RANDOM + (umask 077 && mkdir "$tmp") +} || as_fn_error $? "cannot create a temporary directory in ." "$LINENO" 5 +ac_tmp=$tmp + +# Set up the scripts for CONFIG_FILES section. +# No need to generate them if there are no CONFIG_FILES. +# This happens for instance with `./config.status config.h'. +if test -n "$CONFIG_FILES"; then + + +ac_cr=`echo X | tr X '\015'` +# On cygwin, bash can eat \r inside `` if the user requested igncr. +# But we know of no other shell where ac_cr would be empty at this +# point, so we can use a bashism as a fallback. +if test "x$ac_cr" = x; then + eval ac_cr=\$\'\\r\' +fi +ac_cs_awk_cr=`$AWK 'BEGIN { print "a\rb" }' </dev/null 2>/dev/null` +if test "$ac_cs_awk_cr" = "a${ac_cr}b"; then + ac_cs_awk_cr='\\r' +else + ac_cs_awk_cr=$ac_cr +fi + +echo 'BEGIN {' >"$ac_tmp/subs1.awk" && +_ACEOF + + +{ + echo "cat >conf$$subs.awk <<_ACEOF" && + echo "$ac_subst_vars" | sed 's/.*/&!$&$ac_delim/' && + echo "_ACEOF" +} >conf$$subs.sh || + as_fn_error $? "could not make $CONFIG_STATUS" "$LINENO" 5 +ac_delim_num=`echo "$ac_subst_vars" | grep -c '^'` +ac_delim='%!_!# ' +for ac_last_try in false false false false false :; do + . ./conf$$subs.sh || + as_fn_error $? "could not make $CONFIG_STATUS" "$LINENO" 5 + + ac_delim_n=`sed -n "s/.*$ac_delim\$/X/p" conf$$subs.awk | grep -c X` + if test $ac_delim_n = $ac_delim_num; then + break + elif $ac_last_try; then + as_fn_error $? "could not make $CONFIG_STATUS" "$LINENO" 5 + else + ac_delim="$ac_delim!$ac_delim _$ac_delim!! " + fi +done +rm -f conf$$subs.sh + +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +cat >>"\$ac_tmp/subs1.awk" <<\\_ACAWK && +_ACEOF +sed -n ' +h +s/^/S["/; s/!.*/"]=/ +p +g +s/^[^!]*!// +:repl +t repl +s/'"$ac_delim"'$// +t delim +:nl +h +s/\(.\{148\}\)..*/\1/ +t more1 +s/["\\]/\\&/g; s/^/"/; s/$/\\n"\\/ +p +n +b repl +:more1 +s/["\\]/\\&/g; s/^/"/; s/$/"\\/ +p +g +s/.\{148\}// +t nl +:delim +h +s/\(.\{148\}\)..*/\1/ +t more2 +s/["\\]/\\&/g; s/^/"/; s/$/"/ +p +b +:more2 +s/["\\]/\\&/g; s/^/"/; s/$/"\\/ +p +g +s/.\{148\}// +t delim +' <conf$$subs.awk | sed ' +/^[^""]/{ + N + s/\n// +} +' >>$CONFIG_STATUS || ac_write_fail=1 +rm -f conf$$subs.awk +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +_ACAWK +cat >>"\$ac_tmp/subs1.awk" <<_ACAWK && + for (key in S) S_is_set[key] = 1 + FS = "" + +} +{ + line = $ 0 + nfields = split(line, field, "@") + substed = 0 + len = length(field[1]) + for (i = 2; i < nfields; i++) { + key = field[i] + keylen = length(key) + if (S_is_set[key]) { + value = S[key] + line = substr(line, 1, len) "" value "" substr(line, len + keylen + 3) + len += length(value) + length(field[++i]) + substed = 1 + } else + len += 1 + keylen + } + + print line +} + +_ACAWK +_ACEOF +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +if sed "s/$ac_cr//" < /dev/null > /dev/null 2>&1; then + sed "s/$ac_cr\$//; s/$ac_cr/$ac_cs_awk_cr/g" +else + cat +fi < "$ac_tmp/subs1.awk" > "$ac_tmp/subs.awk" \ + || as_fn_error $? "could not setup config files machinery" "$LINENO" 5 +_ACEOF + +# VPATH may cause trouble with some makes, so we remove sole $(srcdir), +# ${srcdir} and @srcdir@ entries from VPATH if srcdir is ".", strip leading and +# trailing colons and then remove the whole line if VPATH becomes empty +# (actually we leave an empty line to preserve line numbers). +if test "x$srcdir" = x.; then + ac_vpsub='/^[ ]*VPATH[ ]*=[ ]*/{ +h +s/// +s/^/:/ +s/[ ]*$/:/ +s/:\$(srcdir):/:/g +s/:\${srcdir}:/:/g +s/:@srcdir@:/:/g +s/^:*// +s/:*$// +x +s/\(=[ ]*\).*/\1/ +G +s/\n// +s/^[^=]*=[ ]*$// +}' +fi + +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +fi # test -n "$CONFIG_FILES" + +# Set up the scripts for CONFIG_HEADERS section. +# No need to generate them if there are no CONFIG_HEADERS. +# This happens for instance with `./config.status Makefile'. +if test -n "$CONFIG_HEADERS"; then +cat >"$ac_tmp/defines.awk" <<\_ACAWK || +BEGIN { +_ACEOF + +# Transform confdefs.h into an awk script `defines.awk', embedded as +# here-document in config.status, that substitutes the proper values into +# config.h.in to produce config.h. + +# Create a delimiter string that does not exist in confdefs.h, to ease +# handling of long lines. +ac_delim='%!_!# ' +for ac_last_try in false false :; do + ac_tt=`sed -n "/$ac_delim/p" confdefs.h` + if test -z "$ac_tt"; then + break + elif $ac_last_try; then + as_fn_error $? "could not make $CONFIG_HEADERS" "$LINENO" 5 + else + ac_delim="$ac_delim!$ac_delim _$ac_delim!! " + fi +done + +# For the awk script, D is an array of macro values keyed by name, +# likewise P contains macro parameters if any. Preserve backslash +# newline sequences. + +ac_word_re=[_$as_cr_Letters][_$as_cr_alnum]* +sed -n ' +s/.\{148\}/&'"$ac_delim"'/g +t rset +:rset +s/^[ ]*#[ ]*define[ ][ ]*/ / +t def +d +:def +s/\\$// +t bsnl +s/["\\]/\\&/g +s/^ \('"$ac_word_re"'\)\(([^()]*)\)[ ]*\(.*\)/P["\1"]="\2"\ +D["\1"]=" \3"/p +s/^ \('"$ac_word_re"'\)[ ]*\(.*\)/D["\1"]=" \2"/p +d +:bsnl +s/["\\]/\\&/g +s/^ \('"$ac_word_re"'\)\(([^()]*)\)[ ]*\(.*\)/P["\1"]="\2"\ +D["\1"]=" \3\\\\\\n"\\/p +t cont +s/^ \('"$ac_word_re"'\)[ ]*\(.*\)/D["\1"]=" \2\\\\\\n"\\/p +t cont +d +:cont +n +s/.\{148\}/&'"$ac_delim"'/g +t clear +:clear +s/\\$// +t bsnlc +s/["\\]/\\&/g; s/^/"/; s/$/"/p +d +:bsnlc +s/["\\]/\\&/g; s/^/"/; s/$/\\\\\\n"\\/p +b cont +' <confdefs.h | sed ' +s/'"$ac_delim"'/"\\\ +"/g' >>$CONFIG_STATUS || ac_write_fail=1 + +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 + for (key in D) D_is_set[key] = 1 + FS = "" +} +/^[\t ]*#[\t ]*(define|undef)[\t ]+$ac_word_re([\t (]|\$)/ { + line = \$ 0 + split(line, arg, " ") + if (arg[1] == "#") { + defundef = arg[2] + mac1 = arg[3] + } else { + defundef = substr(arg[1], 2) + mac1 = arg[2] + } + split(mac1, mac2, "(") #) + macro = mac2[1] + prefix = substr(line, 1, index(line, defundef) - 1) + if (D_is_set[macro]) { + # Preserve the white space surrounding the "#". + print prefix "define", macro P[macro] D[macro] + next + } else { + # Replace #undef with comments. This is necessary, for example, + # in the case of _POSIX_SOURCE, which is predefined and required + # on some systems where configure will not decide to define it. + if (defundef == "undef") { + print "/*", prefix defundef, macro, "*/" + next + } + } +} +{ print } +_ACAWK +_ACEOF +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 + as_fn_error $? "could not setup config headers machinery" "$LINENO" 5 +fi # test -n "$CONFIG_HEADERS" + + +eval set X " :F $CONFIG_FILES :H $CONFIG_HEADERS " +shift +for ac_tag +do + case $ac_tag in + :[FHLC]) ac_mode=$ac_tag; continue;; + esac + case $ac_mode$ac_tag in + :[FHL]*:*);; + :L* | :C*:*) as_fn_error $? "invalid tag \`$ac_tag'" "$LINENO" 5;; + :[FH]-) ac_tag=-:-;; + :[FH]*) ac_tag=$ac_tag:$ac_tag.in;; + esac + ac_save_IFS=$IFS + IFS=: + set x $ac_tag + IFS=$ac_save_IFS + shift + ac_file=$1 + shift + + case $ac_mode in + :L) ac_source=$1;; + :[FH]) + ac_file_inputs= + for ac_f + do + case $ac_f in + -) ac_f="$ac_tmp/stdin";; + *) # Look for the file first in the build tree, then in the source tree + # (if the path is not absolute). The absolute path cannot be DOS-style, + # because $ac_f cannot contain `:'. + test -f "$ac_f" || + case $ac_f in + [\\/$]*) false;; + *) test -f "$srcdir/$ac_f" && ac_f="$srcdir/$ac_f";; + esac || + as_fn_error 1 "cannot find input file: \`$ac_f'" "$LINENO" 5;; + esac + case $ac_f in *\'*) ac_f=`$as_echo "$ac_f" | sed "s/'/'\\\\\\\\''/g"`;; esac + as_fn_append ac_file_inputs " '$ac_f'" + done + + # Let's still pretend it is `configure' which instantiates (i.e., don't + # use $as_me), people would be surprised to read: + # /* config.h. Generated by config.status. */ + configure_input='Generated from '` + $as_echo "$*" | sed 's|^[^:]*/||;s|:[^:]*/|, |g' + `' by configure.' + if test x"$ac_file" != x-; then + configure_input="$ac_file. $configure_input" + { $as_echo "$as_me:${as_lineno-$LINENO}: creating $ac_file" >&5 +$as_echo "$as_me: creating $ac_file" >&6;} + fi + # Neutralize special characters interpreted by sed in replacement strings. + case $configure_input in #( + *\&* | *\|* | *\\* ) + ac_sed_conf_input=`$as_echo "$configure_input" | + sed 's/[\\\\&|]/\\\\&/g'`;; #( + *) ac_sed_conf_input=$configure_input;; + esac + + case $ac_tag in + *:-:* | *:-) cat >"$ac_tmp/stdin" \ + || as_fn_error $? "could not create $ac_file" "$LINENO" 5 ;; + esac + ;; + esac + + ac_dir=`$as_dirname -- "$ac_file" || +$as_expr X"$ac_file" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \ + X"$ac_file" : 'X\(//\)[^/]' \| \ + X"$ac_file" : 'X\(//\)$' \| \ + X"$ac_file" : 'X\(/\)' \| . 2>/dev/null || +$as_echo X"$ac_file" | + sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ + s//\1/ + q + } + /^X\(\/\/\)[^/].*/{ + s//\1/ + q + } + /^X\(\/\/\)$/{ + s//\1/ + q + } + /^X\(\/\).*/{ + s//\1/ + q + } + s/.*/./; q'` + as_dir="$ac_dir"; as_fn_mkdir_p + ac_builddir=. + +case "$ac_dir" in +.) ac_dir_suffix= ac_top_builddir_sub=. ac_top_build_prefix= ;; +*) + ac_dir_suffix=/`$as_echo "$ac_dir" | sed 's|^\.[\\/]||'` + # A ".." for each directory in $ac_dir_suffix. + ac_top_builddir_sub=`$as_echo "$ac_dir_suffix" | sed 's|/[^\\/]*|/..|g;s|/||'` + case $ac_top_builddir_sub in + "") ac_top_builddir_sub=. ac_top_build_prefix= ;; + *) ac_top_build_prefix=$ac_top_builddir_sub/ ;; + esac ;; +esac +ac_abs_top_builddir=$ac_pwd +ac_abs_builddir=$ac_pwd$ac_dir_suffix +# for backward compatibility: +ac_top_builddir=$ac_top_build_prefix + +case $srcdir in + .) # We are building in place. + ac_srcdir=. + ac_top_srcdir=$ac_top_builddir_sub + ac_abs_top_srcdir=$ac_pwd ;; + [\\/]* | ?:[\\/]* ) # Absolute name. + ac_srcdir=$srcdir$ac_dir_suffix; + ac_top_srcdir=$srcdir + ac_abs_top_srcdir=$srcdir ;; + *) # Relative name. + ac_srcdir=$ac_top_build_prefix$srcdir$ac_dir_suffix + ac_top_srcdir=$ac_top_build_prefix$srcdir + ac_abs_top_srcdir=$ac_pwd/$srcdir ;; +esac +ac_abs_srcdir=$ac_abs_top_srcdir$ac_dir_suffix + + + case $ac_mode in + :F) + # + # CONFIG_FILE + # + + case $INSTALL in + [\\/$]* | ?:[\\/]* ) ac_INSTALL=$INSTALL ;; + *) ac_INSTALL=$ac_top_build_prefix$INSTALL ;; + esac +_ACEOF + +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +# If the template does not know about datarootdir, expand it. +# FIXME: This hack should be removed a few years after 2.60. +ac_datarootdir_hack=; ac_datarootdir_seen= +ac_sed_dataroot=' +/datarootdir/ { + p + q +} +/@datadir@/p +/@docdir@/p +/@infodir@/p +/@localedir@/p +/@mandir@/p' +case `eval "sed -n \"\$ac_sed_dataroot\" $ac_file_inputs"` in +*datarootdir*) ac_datarootdir_seen=yes;; +*@datadir@*|*@docdir@*|*@infodir@*|*@localedir@*|*@mandir@*) + { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: $ac_file_inputs seems to ignore the --datarootdir setting" >&5 +$as_echo "$as_me: WARNING: $ac_file_inputs seems to ignore the --datarootdir setting" >&2;} +_ACEOF +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 + ac_datarootdir_hack=' + s&@datadir@&$datadir&g + s&@docdir@&$docdir&g + s&@infodir@&$infodir&g + s&@localedir@&$localedir&g + s&@mandir@&$mandir&g + s&\\\${datarootdir}&$datarootdir&g' ;; +esac +_ACEOF + +# Neutralize VPATH when `$srcdir' = `.'. +# Shell code in configure.ac might set extrasub. +# FIXME: do we really want to maintain this feature? +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +ac_sed_extra="$ac_vpsub +$extrasub +_ACEOF +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +:t +/@[a-zA-Z_][a-zA-Z_0-9]*@/!b +s|@configure_input@|$ac_sed_conf_input|;t t +s&@top_builddir@&$ac_top_builddir_sub&;t t +s&@top_build_prefix@&$ac_top_build_prefix&;t t +s&@srcdir@&$ac_srcdir&;t t +s&@abs_srcdir@&$ac_abs_srcdir&;t t +s&@top_srcdir@&$ac_top_srcdir&;t t +s&@abs_top_srcdir@&$ac_abs_top_srcdir&;t t +s&@builddir@&$ac_builddir&;t t +s&@abs_builddir@&$ac_abs_builddir&;t t +s&@abs_top_builddir@&$ac_abs_top_builddir&;t t +s&@INSTALL@&$ac_INSTALL&;t t +$ac_datarootdir_hack +" +eval sed \"\$ac_sed_extra\" "$ac_file_inputs" | $AWK -f "$ac_tmp/subs.awk" \ + >$ac_tmp/out || as_fn_error $? "could not create $ac_file" "$LINENO" 5 + +test -z "$ac_datarootdir_hack$ac_datarootdir_seen" && + { ac_out=`sed -n '/\${datarootdir}/p' "$ac_tmp/out"`; test -n "$ac_out"; } && + { ac_out=`sed -n '/^[ ]*datarootdir[ ]*:*=/p' \ + "$ac_tmp/out"`; test -z "$ac_out"; } && + { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: $ac_file contains a reference to the variable \`datarootdir' +which seems to be undefined. Please make sure it is defined" >&5 +$as_echo "$as_me: WARNING: $ac_file contains a reference to the variable \`datarootdir' +which seems to be undefined. Please make sure it is defined" >&2;} + + rm -f "$ac_tmp/stdin" + case $ac_file in + -) cat "$ac_tmp/out" && rm -f "$ac_tmp/out";; + *) rm -f "$ac_file" && mv "$ac_tmp/out" "$ac_file";; + esac \ + || as_fn_error $? "could not create $ac_file" "$LINENO" 5 + ;; + :H) + # + # CONFIG_HEADER + # + if test x"$ac_file" != x-; then + { + $as_echo "/* $configure_input */" \ + && eval '$AWK -f "$ac_tmp/defines.awk"' "$ac_file_inputs" + } >"$ac_tmp/config.h" \ + || as_fn_error $? "could not create $ac_file" "$LINENO" 5 + if diff "$ac_file" "$ac_tmp/config.h" >/dev/null 2>&1; then + { $as_echo "$as_me:${as_lineno-$LINENO}: $ac_file is unchanged" >&5 +$as_echo "$as_me: $ac_file is unchanged" >&6;} + else + rm -f "$ac_file" + mv "$ac_tmp/config.h" "$ac_file" \ + || as_fn_error $? "could not create $ac_file" "$LINENO" 5 + fi + else + $as_echo "/* $configure_input */" \ + && eval '$AWK -f "$ac_tmp/defines.awk"' "$ac_file_inputs" \ + || as_fn_error $? "could not create -" "$LINENO" 5 + fi + ;; + + + esac + +done # for ac_tag + + +as_fn_exit 0 +_ACEOF +ac_clean_files=$ac_clean_files_save + +test $ac_write_fail = 0 || + as_fn_error $? "write failure creating $CONFIG_STATUS" "$LINENO" 5 + + +# configure is writing to config.log, and then calls config.status. +# config.status does its own redirection, appending to config.log. +# Unfortunately, on DOS this fails, as config.log is still kept open +# by configure, so config.status won't be able to write to it; its +# output is simply discarded. So we exec the FD to /dev/null, +# effectively closing config.log, so it can be properly (re)opened and +# appended to by config.status. When coming back to configure, we +# need to make the FD available again. +if test "$no_create" != yes; then + ac_cs_success=: + ac_config_status_args= + test "$silent" = yes && + ac_config_status_args="$ac_config_status_args --quiet" + exec 5>/dev/null + $SHELL $CONFIG_STATUS $ac_config_status_args || ac_cs_success=false + exec 5>>config.log + # Use ||, not &&, to avoid exiting from the if with $? = 1, which + # would make configure fail if this is the last instruction. + $ac_cs_success || as_fn_exit 1 +fi +if test -n "$ac_unrecognized_opts" && test "$enable_option_checking" != no; then + { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: unrecognized options: $ac_unrecognized_opts" >&5 +$as_echo "$as_me: WARNING: unrecognized options: $ac_unrecognized_opts" >&2;} +fi + diff --git a/vendor/riscv/riscv-isa-sim/configure.ac b/vendor/riscv/riscv-isa-sim/configure.ac new file mode 100644 index 0000000000..13797a0b2e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/configure.ac @@ -0,0 +1,126 @@ +#========================================================================= +# Toplevel configure.ac for the Modular C++ Build System +#========================================================================= +# Please read the documenation in 'mcppbs-doc.txt' for more details on +# how the Modular C++ Build System works. For most new projects, a +# developer will only need to make the following changes: +# +# - change the project metadata listed right below +# - update the list of subprojects via the 'MCPPBS_SUBPROJECTS' macro +# - possibly add subproject groups if needed to ease configuration +# - add more configure checks for platform specific configuration +# + +#------------------------------------------------------------------------- +# Project metadata +#------------------------------------------------------------------------- + +m4_define( proj_name, [RISC-V ISA Simulator]) +m4_define( proj_maintainer, [Andrew Waterman]) +m4_define( proj_abbreviation, [spike]) + +#------------------------------------------------------------------------- +# Project version information +#------------------------------------------------------------------------- +# Version information is meant to be managed through a version control +# system's tags and revision numbers. In a working copy the version will +# not be defined here (you should just use the version control system's +# mechanisms). When we make a distribution then we can set the version +# here as formed by the scripts/vcs-version.sh script so that the +# distribution knows what version it came from. If you are not using +# version control then it is fine to set this directly. + +m4_define( proj_version, [?]) + +#------------------------------------------------------------------------- +# Setup +#------------------------------------------------------------------------- + +AC_INIT(proj_name,proj_version,proj_maintainer,proj_abbreviation) +AC_LANG_CPLUSPLUS +AC_CONFIG_SRCDIR([riscv/common.h]) +AC_CONFIG_AUX_DIR([scripts]) +AC_CANONICAL_BUILD +AC_CANONICAL_HOST + +m4_include(ax_require_defined.m4) +m4_include(ax_append_flag.m4) +m4_include(ax_check_compile_flag.m4) +m4_include(ax_check_link_flag.m4) +m4_include(ax_append_link_flags.m4) +m4_include(ax_boost_base.m4) +m4_include(ax_boost_asio.m4) +m4_include(ax_boost_regex.m4) + +#------------------------------------------------------------------------- +# Checks for programs +#------------------------------------------------------------------------- + +AC_PROG_CC +AC_PROG_CXX +AC_CHECK_TOOL([AR],[ar]) +AC_CHECK_TOOL([RANLIB],[ranlib]) +AC_PATH_PROG([DTC],[dtc],[no]) +AS_IF([test x"$DTC" == xno],AC_MSG_ERROR([device-tree-compiler not found])) +AC_DEFINE_UNQUOTED(DTC, ["dtc"], [Executable name of device-tree-compiler]) + +AC_C_BIGENDIAN + +#------------------------------------------------------------------------- +# MCPPBS specific program checks +#------------------------------------------------------------------------- +# These macros check to see if we can do a stow-based install and also +# check for an isa simulator suitable for running the unit test programs +# via the makefile. + +MCPPBS_PROG_INSTALL + +#------------------------------------------------------------------------- +# Checks for header files +#------------------------------------------------------------------------- + +AC_HEADER_STDC + +#------------------------------------------------------------------------- +# Checks for type +#------------------------------------------------------------------------- + +AC_CHECK_TYPE([__int128_t], AC_SUBST([HAVE_INT128],[yes])) + +#------------------------------------------------------------------------- +# Default compiler flags +#------------------------------------------------------------------------- + +AX_APPEND_LINK_FLAGS([-Wl,--export-dynamic]) + +AX_CHECK_COMPILE_FLAG([-relocatable-pch], AC_SUBST([HAVE_CLANG_PCH],[yes])) + +#------------------------------------------------------------------------- +# MCPPBS subproject list +#------------------------------------------------------------------------- +# Order list so that subprojects only depend on those listed earlier. +# The '*' suffix indicates an optional subproject. The '**' suffix +# indicates an optional subproject which is also the name of a group. + +MCPPBS_SUBPROJECTS([ fesvr, riscv, disasm, customext, fdt, softfloat, spike_main, spike_dasm ]) + +#------------------------------------------------------------------------- +# MCPPBS subproject groups +#------------------------------------------------------------------------- +# If a group has the same name as a subproject then you must add the +# '**' suffix in the subproject list above. The list of subprojects in a +# group should be ordered so that subprojets only depend on those listed +# earlier. Here is an example: +# +# MCPPBS_GROUP( [group-name], [sproja,sprojb,...] ) +# + +#------------------------------------------------------------------------- +# Output +#------------------------------------------------------------------------- + +AC_CONFIG_HEADERS([config.h]) +AC_CONFIG_FILES([Makefile]) +AC_CONFIG_FILES([riscv-fesvr.pc]) +AC_CONFIG_FILES([riscv-disasm.pc]) +AC_OUTPUT diff --git a/vendor/riscv/riscv-isa-sim/customext/cflush.cc b/vendor/riscv/riscv-isa-sim/customext/cflush.cc new file mode 100644 index 0000000000..485716a0a9 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/customext/cflush.cc @@ -0,0 +1,43 @@ +#include "insn_macros.h" +#include "extension.h" +#include "decode_macros.h" +#include <cstring> + +struct : public arg_t { + std::string to_string(insn_t insn) const { + return xpr_name[insn.rs1()]; + } +} xrs1; + +static reg_t custom_cflush(processor_t* p, insn_t insn, reg_t pc) +{ + require_privilege(PRV_M); + + return pc + 4; \ +} + +class cflush_t : public extension_t +{ + public: + const char* name() { return "cflush"; } + + cflush_t() {} + + std::vector<insn_desc_t> get_instructions() { + std::vector<insn_desc_t> insns; + insns.push_back((insn_desc_t){0xFC000073, 0xFFF07FFF, custom_cflush, custom_cflush, custom_cflush, custom_cflush, custom_cflush, custom_cflush, custom_cflush, custom_cflush}); + insns.push_back((insn_desc_t){0xFC200073, 0xFFF07FFF, custom_cflush, custom_cflush, custom_cflush, custom_cflush, custom_cflush, custom_cflush, custom_cflush, custom_cflush}); + insns.push_back((insn_desc_t){0xFC100073, 0xFFF07FFF, custom_cflush, custom_cflush, custom_cflush, custom_cflush, custom_cflush, custom_cflush, custom_cflush, custom_cflush}); + return insns; + } + + std::vector<disasm_insn_t*> get_disasms() { + std::vector<disasm_insn_t*> insns; + insns.push_back(new disasm_insn_t("cflush.d.l1", 0xFC000073, 0xFFF07FFF, {&xrs1})); + insns.push_back(new disasm_insn_t("cdiscard.d.l1", 0xFC200073, 0xFFF07FFF, {&xrs1})); + insns.push_back(new disasm_insn_t("cflush.i.l1", 0xFC100073, 0xFFF07FFF, {&xrs1})); + return insns; + } +}; + +REGISTER_EXTENSION(cflush, []() { return new cflush_t; }) diff --git a/vendor/riscv/riscv-isa-sim/customext/customext.ac b/vendor/riscv/riscv-isa-sim/customext/customext.ac new file mode 100644 index 0000000000..e69de29bb2 diff --git a/vendor/riscv/riscv-isa-sim/customext/customext.mk.in b/vendor/riscv/riscv-isa-sim/customext/customext.mk.in new file mode 100644 index 0000000000..888634b469 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/customext/customext.mk.in @@ -0,0 +1,12 @@ +customext_subproject_deps = \ + spike_main \ + riscv \ + disasm \ + softfloat \ + +customext_srcs = \ + dummy_rocc.cc \ + cflush.cc \ + cvxif.cc \ + +customext_install_shared_lib = yes diff --git a/vendor/riscv/riscv-isa-sim/customext/cvxif.cc b/vendor/riscv/riscv-isa-sim/customext/cvxif.cc new file mode 100644 index 0000000000..b1bef8e646 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/customext/cvxif.cc @@ -0,0 +1,242 @@ +// Copyright (C) 2022 Thales DIS Design Services SAS +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0. +// +// Original Author: Zbigniew CHAMSKI <zbigniew.chamski@thalesgroup.com> + +#define DECODE_MACRO_USAGE_LOGGED 1 +#include "decode_macros.h" +#include "cvxif.h" +#include "mmu.h" +#include <cstring> + +// Define custom insns templates. +// The insn-level wrapper is 'c##n' (default implementation, +// writeback disabled), the default implementation +// is 'custom##n': illegal instruction, return 0. +// The writeback controller 'cvxif_extn_t::do_writeback_p' +// is in charge of determining if writeback is required or not. +// Expected instruction encoding is 4 bytes. +#define customX(n) \ +static reg_t c##n(processor_t* p, insn_t insn, reg_t pc) \ + { \ + cvxif_t* cvxif = static_cast<cvxif_t*>(p->get_extension()); \ + cvxif_insn_t custom_insn; \ + custom_insn.i = insn; \ + reg_t xd = cvxif->default_custom##n(custom_insn); \ + if (cvxif->do_writeback_p(custom_insn)) \ + WRITE_RD(xd); \ + return pc+4; \ + } \ + \ + reg_t default_custom##n(cvxif_insn_t insn) \ + { \ + return custom##n(insn); \ + } + +// This class instantiates the CV-X-IF interface. +class cvxif_t : public cvxif_extn_t +{ + public: + const char* name() { return "cvxif_spike"; } + + bool do_writeback_p(cvxif_insn_t copro_insn) + { + // INSN_R personality serves to simplify access to standard encoding fields. + cvxif_r_insn_t insn_r = copro_insn.r_type; + + if (insn_r.opcode != 0x7b /* MATCH_CUSTOM3 */) + return false; + else switch (insn_r.funct3) + { + case FUNC3_0: + //CUS_NOP have rd equal to zero + return (insn_r.rd != 0x0); + + case FUNC3_1: + //Only CUS_ADD + return true; + + case FUNC3_2: + //Only CUS_EXC + return false; + + default: + // All other cases: writeback is assumed REQUIRED. + return false; + } + } + + // Custom0 instructions: default behaviour. + reg_t custom0(cvxif_insn_t incoming_insn) + { + illegal_instruction(); + return -1; + } + + // Custom1 instructions: default behaviour. + reg_t custom1(cvxif_insn_t incoming_insn) + { + illegal_instruction(); + return -1; + } + + // Custom2 instructions: default behaviour. + reg_t custom2(cvxif_insn_t incoming_insn) + { + illegal_instruction(); + return -1; + } + + // Custom3 instructions: provide an explicit implementation of decode+exec. + reg_t custom3(cvxif_insn_t incoming_insn) + { + // Assume R-type insn: it shares opcode and funct3 fields with other CVXIF insn formats. + cvxif_r_insn_t r_insn = incoming_insn.r_type; + // INSN_T simplifies access to register values. + insn_t insn = incoming_insn.i; + + switch (r_insn.funct3) + { + case FUNC3_0: + switch (r_insn.funct7 & 0x1) { + case NO_RS3: + switch (r_insn.funct7 & 0xe) { + case CUS_NOP: + break; + case CUS_U_ADD: + if (p -> get_state() -> prv != PRV_U) { + illegal_instruction(); + } + return (reg_t) ((reg_t) RS1 + (reg_t) RS2 + (reg_t) RS3); + + case CUS_S_ADD: + if (p -> get_state() -> prv != PRV_S) { + illegal_instruction(); + } + return (reg_t) ((reg_t) RS1 + (reg_t) RS2); + + case CUS_ADD_MULTI: + return (reg_t) ((reg_t) RS1 + (reg_t) RS2); + + default: + illegal_instruction(); + } + break; + case RS3_IN: + //Actually only CUS_ADD_RS3 using rs3, we don't need to add another switch case + if (p -> get_nb_register_source() != 3) { + illegal_instruction(); + } + return (reg_t) ((reg_t) RS1 + (reg_t) RS2 + (reg_t) RS3); + default: + illegal_instruction(); + } + break; + case FUNC3_1: + switch(r_insn.funct7) { + case 0: + return (reg_t) ((reg_t) RS1 + (reg_t) RS2); + break; + default: + illegal_instruction(); + } + + case FUNC3_2: + switch (r_insn.funct7) { + case (0x60): + if (r_insn.rs2 != 0 || r_insn.rd != 0){ + illegal_instruction(); + } else { + raise_exception(insn, (reg_t) (r_insn.rs1)); + } + break; + default: + illegal_instruction(); + } + default: + illegal_instruction(); + } + + // FORNOW: Return 0xf......f to simplify debugging. + return (reg_t) -1; + } + + cvxif_t() + { + } + + void raise_exception(insn_t insn, reg_t exc_index) + { + switch (exc_index) { + case CAUSE_MISALIGNED_FETCH: + throw trap_instruction_address_misaligned((p ? p->get_state()->v : false), 1, 0, 0); + case CAUSE_FETCH_ACCESS: + throw trap_instruction_access_fault((p ? p->get_state()->v : false), 1, 0, 0); + case CAUSE_BREAKPOINT: + throw trap_breakpoint((p ? p->get_state()->v : false), 1); + case CAUSE_MISALIGNED_LOAD: + // Use 0x1 as perfectly unaligned address;-) + throw trap_load_address_misaligned((p ? p->get_state()->v : false), 1, 0, 0); + case CAUSE_LOAD_ACCESS: + // Use 0x1 as invalid address. + throw trap_load_access_fault((p ? p->get_state()->v : false), 1, 0, 0); + case CAUSE_MISALIGNED_STORE: + // Use 0x1 as perfectly unaligned address;-) + throw trap_store_address_misaligned((p ? p->get_state()->v : false), 1, 0, 0); + case CAUSE_STORE_ACCESS: + // Use 0x1 as invalid address. + throw trap_store_access_fault((p ? p->get_state()->v : false), 1, 0, 0); + case CAUSE_USER_ECALL: + throw trap_user_ecall(); + case CAUSE_SUPERVISOR_ECALL: + throw trap_supervisor_ecall(); + case CAUSE_VIRTUAL_SUPERVISOR_ECALL: + throw trap_virtual_supervisor_ecall(); + case CAUSE_MACHINE_ECALL: + throw trap_machine_ecall(); + case CAUSE_FETCH_PAGE_FAULT: + throw trap_instruction_page_fault((p ? p->get_state()->v : false), 1, 0, 0); + case CAUSE_LOAD_PAGE_FAULT: + // Use 0x1 as always-faulting address. + throw trap_load_page_fault((p ? p->get_state()->v : false), 1, 0, 0); + case CAUSE_STORE_PAGE_FAULT: + // Use 0x1 as always-faulting address. + throw trap_store_page_fault((p ? p->get_state()->v : false), 1, 0, 0); + case CAUSE_FETCH_GUEST_PAGE_FAULT: + throw trap_instruction_guest_page_fault(0, 0, 0); + case CAUSE_LOAD_GUEST_PAGE_FAULT: + throw trap_load_guest_page_fault(0, 0, 0); + case CAUSE_VIRTUAL_INSTRUCTION: + throw trap_virtual_instruction(0); + case CAUSE_STORE_GUEST_PAGE_FAULT: + throw trap_store_guest_page_fault(0, 0, 0); + default: + throw trap_unknown_instruction(exc_index, (reg_t)0); + } + } + + // Define templates of new instructions. + customX(0) + customX(1) + customX(2) + customX(3) + + // Set instruction handlers for customN opcode patterns. + // NOTE: This method may need revisiting if multiple custom extensions are to be loaded + // simultaneously in the future. + std::vector<insn_desc_t> get_instructions() + { + std::vector<insn_desc_t> insns; + insns.push_back((insn_desc_t){0x0b, 0x7f, &::illegal_instruction, &::illegal_instruction, &::illegal_instruction, &::illegal_instruction, &::illegal_instruction, &::illegal_instruction, &::illegal_instruction, c0}); + insns.push_back((insn_desc_t){0x2b, 0x7f, &::illegal_instruction, &::illegal_instruction, &::illegal_instruction, &::illegal_instruction, &::illegal_instruction, &::illegal_instruction, &::illegal_instruction, c1}); + insns.push_back((insn_desc_t){0x5b, 0x7f, &::illegal_instruction, &::illegal_instruction, &::illegal_instruction, &::illegal_instruction, &::illegal_instruction, &::illegal_instruction, &::illegal_instruction, c2}); + insns.push_back((insn_desc_t){0x7b, 0x7f, &c3, &c3, &c3, &c3, &c3, &c3, &c3, c3}); + return insns; + } + +private: + // State variables go here. +}; + +REGISTER_EXTENSION(cvxif, []() { return new cvxif_t; }) diff --git a/vendor/riscv/riscv-isa-sim/customext/cvxif_test.c b/vendor/riscv/riscv-isa-sim/customext/cvxif_test.c new file mode 100644 index 0000000000..bcd86151d2 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/customext/cvxif_test.c @@ -0,0 +1,111 @@ +// Copyright (C) 2022 Thales DIS Design Services SAS +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0. +// +// Original Author: Zbigniew CHAMSKI <zbigniew.chamski@thalesgroup.com> +// +// The following is a RISC-V program to test the functionality of the +// basic CVXIF accelerator interface on the Core-V side. +// Compile using "riscv-none-elf-gcc -O2 cvxif_test.elf cvxif_test.c" +// with -march=/-mabi= settings appropriate for your project. +// Run using "spike -l --extension=cvxif cvxif_test.elf", adding +// an --isa= setting appropriate for your project. +// +// Upon simulating the compiled program, the trace should contain five +// instances of custom3 instructions (the third one being decoded as +// 'unknown'). +// The last occurrence of 'custom3' instruction in the trace, encoded as +// 0x8002007b, should be immediately followed by exception +// 'trap_load_address_misaligned' with a tval equal to 0x1 and the +// execution should terminate correctly with exit code 0. +// +// In 64-bit mode, the trace of the last occurrence of custom3 +// instruction should be equivalent to +// +// core 0: 0x0000000080002686 (0x8002007b) custom3 (args unknown) +// core 0: exception trap_load_address_misaligned, epc 0x0000000080002686 +// core 0: tval 0x0000000000000001 +// +// The corresponding trace in 32-bit mode should be equivalent to +// +// core 0: 0x8000205a (0x8002007b) custom3 (args unknown) +// core 0: exception trap_load_address_misaligned, epc 0x8000205a +// core 0: tval 0x00000001 + +#include <assert.h> +#include <stdio.h> +#include <stdint.h> +#include <stdlib.h> + +// Values of MCAUSE corresponding to exceptions coming from the coprocessor I/F +#define CAUSE_MISALIGNED_LOAD 0x4 +#define CAUSE_LOAD_ACCESS 0x5 +#define CAUSE_MISALIGNED_STORE 0x6 +#define CAUSE_STORE_ACCESS 0x7 +#define CAUSE_LOAD_PAGE_FAULT 0xd +#define CAUSE_STORE_PAGE_FAULT 0xf +#define CAUSE_COPROCESSOR_EXCEPTION 0x20 + +// Value of TVAL to pass around. +#define COPRO_TVAL_TEST 0x1a + +// Macro to read a CSR (from spike's "encoding.h") +#define read_csr(reg) ({ unsigned long __tmp; \ + asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ + __tmp; }) + +int main() { + // "unsigned long int" is always XLEN bits wide. + unsigned long int x = 123, y = 456, z = 0, t = 0; + static unsigned long int amem = 111, bmem = 0; + unsigned long a; + + // Add x + y into z. Funct7 == 0, funct3 == 0x0. + asm volatile (".insn r CUSTOM_3, 0, 0, %0, %1, %2" : "=r"(z) : "r"(x), "r"(y)); + if (z != 123 + 456) + { + // printf("FAILURE!!!\n"); + return 1; + } + + // Add three operands in a single R4-type add. + // Leverage current values of x, y and z (z == x + y). + asm volatile (".insn r CUSTOM_3, 0, 0x1, %0, %1, %2, %3" : "=r"(t) : "r"(x), "r"(y), "r"(z)); + if (t != x + y + z) + { + // printf("FAILURE"); + return 2; + } + // Load 'a' from 'amem'. CUSTOM_LD: opcode == CUSTOM_3, insn_type == I, funct3 == 0x1. + asm volatile (".insn i CUSTOM_3, 0x1, %0, %1" : "=r"(a) : "m"(amem), "I"(0)); + if (a != 111) + { + // printf("FAILURE!!!\n"); + return 3; + } + + // Store 'a' in 'bmem'. CUSTOM_SD: opcode == CUSTOM_3, insn_type == S, funct3 == 0x2. + asm volatile (".insn s CUSTOM_3, 0x2, %0, %1" : : "r"(a), "m"(bmem)); + if (bmem != 111) + { + // printf("FAILURE!!!\n"); + return 4; + } + + // Generate a misaligned load exception (mcause == 0x4). + asm volatile (".insn r CUSTOM_3, 0x0, 0x40, x0, x4, x0" : : ); + + // If we get here, then the exception test failed ==> exit with general failure code. + exit(1337); +} + +// Override default trap handler. +uintptr_t handle_trap(uintptr_t cause, uintptr_t epc, uintptr_t regs[32]) +{ + if (cause == CAUSE_MISALIGNED_LOAD) + // Successfully terminate. + exit(0); + else + // Fail with explicit retcode. + exit(5); +} diff --git a/vendor/riscv/riscv-isa-sim/customext/dummy_rocc.cc b/vendor/riscv/riscv-isa-sim/customext/dummy_rocc.cc new file mode 100644 index 0000000000..8c051fad2e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/customext/dummy_rocc.cc @@ -0,0 +1,47 @@ +#include "rocc.h" +#include "mmu.h" +#include <cstring> + +class dummy_rocc_t : public rocc_t +{ + public: + const char* name() { return "dummy_rocc"; } + + reg_t custom0(rocc_insn_t insn, reg_t xs1, reg_t UNUSED xs2) + { + reg_t prev_acc = acc[insn.rs2]; + + if (insn.rs2 >= num_acc) + illegal_instruction(); + + switch (insn.funct) + { + case 0: // acc <- xs1 + acc[insn.rs2] = xs1; + break; + case 1: // xd <- acc (the only real work is the return statement below) + break; + case 2: // acc[rs2] <- Mem[xs1] + acc[insn.rs2] = p->get_mmu()->load<uint64_t>(xs1); + break; + case 3: // acc[rs2] <- accX + xs1 + acc[insn.rs2] += xs1; + break; + default: + illegal_instruction(); + } + + return prev_acc; // in all cases, xd <- previous value of acc[rs2] + } + + dummy_rocc_t() + { + memset(acc, 0, sizeof(acc)); + } + + private: + static const int num_acc = 4; + reg_t acc[num_acc]; +}; + +REGISTER_EXTENSION(dummy_rocc, []() { return new dummy_rocc_t; }) diff --git a/vendor/riscv/riscv-isa-sim/customext/dummy_rocc_test.c b/vendor/riscv/riscv-isa-sim/customext/dummy_rocc_test.c new file mode 100644 index 0000000000..94de8c041e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/customext/dummy_rocc_test.c @@ -0,0 +1,29 @@ +// The following is a RISC-V program to test the functionality of the +// dummy RoCC accelerator. +// Compile with riscv64-unknown-elf-gcc dummy_rocc_test.c +// Run with spike --extension=dummy_rocc pk a.out + +#include <assert.h> +#include <stdio.h> +#include <stdint.h> + +int main() { + uint64_t x = 123, y = 456, z = 0; + // load x into accumulator 2 (funct=0) + asm volatile ("custom0 x0, %0, 2, 0" : : "r"(x)); + // read it back into z (funct=1) to verify it + asm volatile ("custom0 %0, x0, 2, 1" : "=r"(z)); + assert(z == x); + // accumulate 456 into it (funct=3) + asm volatile ("custom0 x0, %0, 2, 3" : : "r"(y)); + // verify it + asm volatile ("custom0 %0, x0, 2, 1" : "=r"(z)); + assert(z == x+y); + // do it all again, but initialize acc2 via memory this time (funct=2) + asm volatile ("custom0 x0, %0, 2, 2" : : "r"(&x)); + asm volatile ("custom0 x0, %0, 2, 3" : : "r"(y)); + asm volatile ("custom0 %0, x0, 2, 1" : "=r"(z)); + assert(z == x+y); + + printf("success!\n"); +} diff --git a/vendor/riscv/riscv-isa-sim/debug_rom/.gitignore b/vendor/riscv/riscv-isa-sim/debug_rom/.gitignore new file mode 100644 index 0000000000..98bd13e4dd --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/debug_rom/.gitignore @@ -0,0 +1,5 @@ +/debug_rom +/debug_rom32 +/debug_rom64 +/debug_rom32.h +/debug_rom64.h diff --git a/vendor/riscv/riscv-isa-sim/debug_rom/Makefile b/vendor/riscv/riscv-isa-sim/debug_rom/Makefile new file mode 100644 index 0000000000..d6546e9a6f --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/debug_rom/Makefile @@ -0,0 +1,24 @@ +# Recursive make is bad, but in this case we're cross compiling which is a +# pretty unusual use case. + +CC = $(RISCV)/bin/riscv64-unknown-elf-gcc +OBJCOPY = $(RISCV)/bin/riscv64-unknown-elf-objcopy + +COMPILE = $(CC) -nostdlib -nostartfiles -I.. -Tlink.ld + +ELFS = debug_rom +DEPS = debug_rom.S link.ld ../riscv/debug_rom_defines.h ../riscv/encoding.h + +all: $(patsubst %,%.h,$(ELFS)) + +%.h: %.raw + xxd -i $^ | sed "s/^unsigned/static const unsigned/" > $@ + +%.raw: % + $(OBJCOPY) -O binary --only-section .text $^ $@ + +debug_rom: $(DEPS) + $(COMPILE) -o $@ $< + +clean: + rm -f $(ELFS) debug_rom*.raw debug_rom.h diff --git a/vendor/riscv/riscv-isa-sim/debug_rom/debug_rom.S b/vendor/riscv/riscv-isa-sim/debug_rom/debug_rom.S new file mode 100755 index 0000000000..2d361397e3 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/debug_rom/debug_rom.S @@ -0,0 +1,79 @@ +// See LICENSE.SiFive for license details. + +#include "riscv/encoding.h" +#include "riscv/debug_rom_defines.h" + + .option norvc + .global entry + .global exception + + // Entry location on ebreak, Halt, or Breakpoint + // It is the same for all harts. They branch when + // their GO or RESUME bit is set. + +entry: + jal zero, _entry +resume: + // Not used. + jal zero, _resume +exception: + jal zero, _exception + +_entry: + // This fence is required because the execution may have written something + // into the Abstract Data or Program Buffer registers. + fence + csrw CSR_DSCRATCH0, s0 // Save s0 to allow signaling MHARTID + + // We continue to let the hart know that we are halted in order that + // a DM which was reset is still made aware that a hart is halted. + // We keep checking both whether there is something the debugger wants + // us to do, or whether we should resume. +entry_loop: + csrr s0, CSR_MHARTID + sw s0, DEBUG_ROM_HALTED(zero) + lbu s0, DEBUG_ROM_FLAGS(s0) // 1 byte flag per hart. Only one hart advances here. + andi s0, s0, (1 << DEBUG_ROM_FLAG_GO) + bnez s0, going + csrr s0, CSR_MHARTID + lbu s0, DEBUG_ROM_FLAGS(s0) // multiple harts can resume here + andi s0, s0, (1 << DEBUG_ROM_FLAG_RESUME) + bnez s0, _resume + wfi + jal zero, entry_loop + +_exception: + // Restore S0, which we always save to dscratch. + // We need this in case the user tried an abstract write to a + // non-existent CSR. + csrr s0, CSR_DSCRATCH0 + sw zero, DEBUG_ROM_EXCEPTION(zero) // Let debug module know you got an exception. + ebreak + +going: + csrr s0, CSR_MHARTID + sw s0, DEBUG_ROM_GOING(zero) // When debug module sees this write, the GO flag is reset. + csrr s0, CSR_DSCRATCH0 // Restore s0 here + fence + fence.i + jalr zero, zero, %lo(whereto) // Debug module will put different instructions and data in the RAM, + // so we use fence and fence.i for safety. (rocket-chip doesn't have this + // because jalr is special there) + +_resume: + csrr s0, CSR_MHARTID + sw s0, DEBUG_ROM_RESUMING(zero) // When Debug Module sees this write, the RESUME flag is reset. + csrr s0, CSR_DSCRATCH0 // Restore s0 + dret + + // END OF ACTUAL "ROM" CONTENTS. BELOW IS JUST FOR LINKER SCRIPT. + +.section .whereto +whereto: + nop + // Variable "ROM" This is : jal x0 abstract, jal x0 program_buffer, + // or jal x0 resume, as desired. + // Debug Module state machine tracks what is 'desired'. + // We don't need/want to use jalr here because all of the + // Variable ROM contents are set by + // Debug Module before setting the OK_GO byte. diff --git a/vendor/riscv/riscv-isa-sim/debug_rom/debug_rom.h b/vendor/riscv/riscv-isa-sim/debug_rom/debug_rom.h new file mode 100644 index 0000000000..7edd5f68f9 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/debug_rom/debug_rom.h @@ -0,0 +1,13 @@ +static const unsigned char debug_rom_raw[] = { + 0x6f, 0x00, 0xc0, 0x00, 0x6f, 0x00, 0x00, 0x06, 0x6f, 0x00, 0x80, 0x03, + 0x0f, 0x00, 0xf0, 0x0f, 0x73, 0x10, 0x24, 0x7b, 0x73, 0x24, 0x40, 0xf1, + 0x23, 0x20, 0x80, 0x10, 0x03, 0x44, 0x04, 0x40, 0x13, 0x74, 0x14, 0x00, + 0x63, 0x14, 0x04, 0x02, 0x73, 0x24, 0x40, 0xf1, 0x03, 0x44, 0x04, 0x40, + 0x13, 0x74, 0x24, 0x00, 0x63, 0x18, 0x04, 0x02, 0x73, 0x00, 0x50, 0x10, + 0x6f, 0xf0, 0x9f, 0xfd, 0x73, 0x24, 0x20, 0x7b, 0x23, 0x26, 0x00, 0x10, + 0x73, 0x00, 0x10, 0x00, 0x73, 0x24, 0x40, 0xf1, 0x23, 0x22, 0x80, 0x10, + 0x73, 0x24, 0x20, 0x7b, 0x0f, 0x00, 0xf0, 0x0f, 0x0f, 0x10, 0x00, 0x00, + 0x67, 0x00, 0x00, 0x30, 0x73, 0x24, 0x40, 0xf1, 0x23, 0x24, 0x80, 0x10, + 0x73, 0x24, 0x20, 0x7b, 0x73, 0x00, 0x20, 0x7b +}; +static const unsigned int debug_rom_raw_len = 116; diff --git a/vendor/riscv/riscv-isa-sim/debug_rom/link.ld b/vendor/riscv/riscv-isa-sim/debug_rom/link.ld new file mode 100644 index 0000000000..897c42da00 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/debug_rom/link.ld @@ -0,0 +1,15 @@ +OUTPUT_ARCH( "riscv" ) +ENTRY( entry ) +SECTIONS +{ + .whereto 0x300 : + { + *(.whereto) + } + . = 0x800; + .text : + { + *(.text) + } + _end = .; +} diff --git a/vendor/riscv/riscv-isa-sim/disasm/disasm.ac b/vendor/riscv/riscv-isa-sim/disasm/disasm.ac new file mode 100644 index 0000000000..e69de29bb2 diff --git a/vendor/riscv/riscv-isa-sim/disasm/disasm.cc b/vendor/riscv/riscv-isa-sim/disasm/disasm.cc new file mode 100644 index 0000000000..fef9facab4 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/disasm/disasm.cc @@ -0,0 +1,2273 @@ +// See LICENSE for license details. + +#include "disasm.h" +#include "decode_macros.h" +#include <cassert> +#include <string> +#include <vector> +#include <cstdarg> +#include <sstream> +#include <stdlib.h> +// For std::reverse: +#include <algorithm> + +#ifdef __GNUC__ +# pragma GCC diagnostic ignored "-Wunused-variable" +#endif + +// Indicates that the next arg (only) is optional. +// If the result of converting the next arg to a string is "" +// then it will not be printed. +static const arg_t* opt = nullptr; + +struct : public arg_t { + std::string to_string(insn_t insn) const { + return std::to_string((int)insn.i_imm()) + '(' + xpr_name[insn.rs1()] + ')'; + } +} load_address; + +struct : public arg_t { + std::string to_string(insn_t insn) const { + return std::to_string((int)insn.rvc_lbimm()) + '(' + xpr_name[insn.rvc_rs1s()] + ')'; + } +} rvb_b_address; + +struct : public arg_t { + std::string to_string(insn_t insn) const { + return std::to_string((int)insn.rvc_lhimm()) + '(' + xpr_name[insn.rvc_rs1s()] + ')'; + } +} rvb_h_address; + +struct : public arg_t { + std::string to_string(insn_t insn) const { + return std::to_string((int)insn.s_imm()) + '(' + xpr_name[insn.rs1()] + ')'; + } +} store_address; + +struct : public arg_t { + std::string to_string(insn_t insn) const { + return std::string("(") + xpr_name[insn.rs1()] + ')'; + } +} base_only_address; + +struct : public arg_t { + std::string to_string(insn_t insn) const { + return xpr_name[insn.rd()]; + } +} xrd; + +struct : public arg_t { + std::string to_string(insn_t insn) const { + return xpr_name[insn.rs1()]; + } +} xrs1; + +struct : public arg_t { + std::string to_string(insn_t insn) const { + return std::to_string((uint32_t)insn.rvc_index()); + } +} rvcm_jt_index; + +struct : public arg_t { + std::string to_string(insn_t insn) const { + int rlist = insn.rvc_rlist(); + if (rlist >= 4) { + switch(rlist) { + case 4: return "{ra}"; + case 5: return "{ra, s0}"; + case 15: return "{ra, s0-s11}"; + default: return "{ra, s0-s" + std::to_string(rlist - 5)+'}'; + } + } else { + return "unsupport rlist"; + } + } +} rvcm_pushpop_rlist; + +struct : public arg_t { + std::string to_string(insn_t insn) const { + return '-' + std::to_string(insn.zcmp_stack_adjustment(32)); + } +} rvcm_push_stack_adj_32; + +struct : public arg_t { + std::string to_string(insn_t insn) const { + return '-' + std::to_string(insn.zcmp_stack_adjustment(64)); + } +} rvcm_push_stack_adj_64; + +struct : public arg_t { + std::string to_string(insn_t insn) const { + return std::to_string(insn.zcmp_stack_adjustment(32)); + } +} rvcm_pop_stack_adj_32; + +struct : public arg_t { + std::string to_string(insn_t insn) const { + return std::to_string(insn.zcmp_stack_adjustment(64)); + } +} rvcm_pop_stack_adj_64; + +struct : public arg_t { + std::string to_string(insn_t insn) const { + return xpr_name[insn.rs2()]; + } +} xrs2; + +struct : public arg_t { + std::string to_string(insn_t insn) const { + return xpr_name[insn.rs3()]; + } +} xrs3; + +struct : public arg_t { + std::string to_string(insn_t insn) const { + return fpr_name[insn.rd()]; + } +} frd; + +struct : public arg_t { + std::string to_string(insn_t insn) const { + return fpr_name[insn.rs1()]; + } +} frs1; + +struct : public arg_t { + std::string to_string(insn_t insn) const { + return fpr_name[insn.rs2()]; + } +} frs2; + +struct : public arg_t { + std::string to_string(insn_t insn) const { + return fpr_name[insn.rs3()]; + } +} frs3; + +struct : public arg_t { + std::string to_string(insn_t insn) const { + switch (insn.csr()) + { + #define DECLARE_CSR(name, num) case num: return #name; + #include "encoding.h" + #undef DECLARE_CSR + default: + { + char buf[16]; + snprintf(buf, sizeof buf, "unknown_%03" PRIx64, insn.csr()); + return std::string(buf); + } + } + } +} csr; + +struct : public arg_t { + std::string to_string(insn_t insn) const { + return std::to_string((int)insn.i_imm()); + } +} imm; + +struct : public arg_t { + std::string to_string(insn_t insn) const { + return std::to_string((int)insn.shamt()); + } +} shamt; + +struct : public arg_t { + std::string to_string(insn_t insn) const { + std::stringstream s; + s << std::hex << "0x" << ((uint32_t)insn.u_imm() >> 12); + return s.str(); + } +} bigimm; + +struct : public arg_t { + std::string to_string(insn_t insn) const { + return std::to_string(insn.rs1()); + } +} zimm5; + +struct : public arg_t { + std::string to_string(insn_t insn) const { + int32_t target = insn.sb_imm(); + std::string s = target >= 0 ? "pc + " : "pc - "; + s += std::to_string(abs(target)); + return s; + } +} branch_target; + +struct : public arg_t { + std::string to_string(insn_t insn) const { + std::stringstream s; + int32_t target = insn.uj_imm(); + char sign = target >= 0 ? '+' : '-'; + s << "pc " << sign << std::hex << " 0x" << abs(target); + return s.str(); + } +} jump_target; + +struct : public arg_t { + std::string to_string(insn_t insn) const { + return xpr_name[insn.rvc_rs1()]; + } +} rvc_rs1; + +struct : public arg_t { + std::string to_string(insn_t insn) const { + return xpr_name[insn.rvc_rs2()]; + } +} rvc_rs2; + +struct : public arg_t { + std::string to_string(insn_t insn) const { + return fpr_name[insn.rvc_rs2()]; + } +} rvc_fp_rs2; + +struct : public arg_t { + std::string to_string(insn_t insn) const { + return xpr_name[insn.rvc_rs1s()]; + } +} rvc_rs1s; + +struct : public arg_t { + std::string to_string(insn_t insn) const { + return xpr_name[insn.rvc_rs2s()]; + } +} rvc_rs2s; + +struct : public arg_t { + std::string to_string(insn_t insn) const { + return fpr_name[insn.rvc_rs2s()]; + } +} rvc_fp_rs2s; + +struct : public arg_t { + std::string to_string(insn_t UNUSED insn) const { + return xpr_name[X_SP]; + } +} rvc_sp; + +struct : public arg_t { + std::string to_string(insn_t insn) const { + return std::to_string((int)insn.rvc_imm()); + } +} rvc_imm; + +struct : public arg_t { + std::string to_string(insn_t insn) const { + return std::to_string((int)insn.rvc_addi4spn_imm()); + } +} rvc_addi4spn_imm; + +struct : public arg_t { + std::string to_string(insn_t insn) const { + return std::to_string((int)insn.rvc_addi16sp_imm()); + } +} rvc_addi16sp_imm; + +struct : public arg_t { + std::string to_string(insn_t insn) const { + return std::to_string((int)insn.rvc_lwsp_imm()); + } +} rvc_lwsp_imm; + +struct : public arg_t { + std::string to_string(insn_t insn) const { + return std::to_string((int)(insn.rvc_imm() & 0x3f)); + } +} rvc_shamt; + +struct : public arg_t { + std::string to_string(insn_t insn) const { + std::stringstream s; + s << std::hex << "0x" << ((uint32_t)insn.rvc_imm() << 12 >> 12); + return s.str(); + } +} rvc_uimm; + +struct : public arg_t { + std::string to_string(insn_t insn) const { + return std::to_string((int)insn.rvc_lwsp_imm()) + '(' + xpr_name[X_SP] + ')'; + } +} rvc_lwsp_address; + +struct : public arg_t { + std::string to_string(insn_t insn) const { + return std::to_string((int)insn.rvc_ldsp_imm()) + '(' + xpr_name[X_SP] + ')'; + } +} rvc_ldsp_address; + +struct : public arg_t { + std::string to_string(insn_t insn) const { + return std::to_string((int)insn.rvc_swsp_imm()) + '(' + xpr_name[X_SP] + ')'; + } +} rvc_swsp_address; + +struct : public arg_t { + std::string to_string(insn_t insn) const { + return std::to_string((int)insn.rvc_sdsp_imm()) + '(' + xpr_name[X_SP] + ')'; + } +} rvc_sdsp_address; + +struct : public arg_t { + std::string to_string(insn_t insn) const { + return std::to_string((int)insn.rvc_lw_imm()) + '(' + xpr_name[insn.rvc_rs1s()] + ')'; + } +} rvc_lw_address; + +struct : public arg_t { + std::string to_string(insn_t insn) const { + return std::to_string((int)insn.rvc_ld_imm()) + '(' + xpr_name[insn.rvc_rs1s()] + ')'; + } +} rvc_ld_address; + +struct : public arg_t { + std::string to_string(insn_t insn) const { + int32_t target = insn.rvc_b_imm(); + std::string s = target >= 0 ? "pc + " : "pc - "; + s += std::to_string(abs(target)); + return s; + } +} rvc_branch_target; + +struct : public arg_t { + std::string to_string(insn_t insn) const { + int32_t target = insn.rvc_j_imm(); + std::string s = target >= 0 ? "pc + " : "pc - "; + s += std::to_string(abs(target)); + return s; + } +} rvc_jump_target; + +struct : public arg_t { + std::string to_string(insn_t insn) const { + return std::string("(") + xpr_name[insn.rs1()] + ')'; + } +} v_address; + +struct : public arg_t { + std::string to_string(insn_t insn) const { + return vr_name[insn.rd()]; + } +} vd; + +struct : public arg_t { + std::string to_string(insn_t insn) const { + return vr_name[insn.rs1()]; + } +} vs1; + +struct : public arg_t { + std::string to_string(insn_t insn) const { + return vr_name[insn.rs2()]; + } +} vs2; + +struct : public arg_t { + std::string to_string(insn_t insn) const { + return vr_name[insn.rd()]; + } +} vs3; + +struct : public arg_t { + std::string to_string(insn_t insn) const { + return insn.v_vm() ? "" : "v0.t"; + } +} vm; + +struct : public arg_t { + std::string to_string(insn_t UNUSED insn) const { + return "v0"; + } +} v0; + +struct : public arg_t { + std::string to_string(insn_t insn) const { + return std::to_string((int)insn.v_simm5()); + } +} v_simm5; + +struct : public arg_t { + std::string to_string(insn_t insn) const { + std::stringstream s; + int sew = insn.v_sew(); + int lmul = insn.v_lmul(); + auto vta = insn.v_vta() == 1 ? "ta" : "tu"; + auto vma = insn.v_vma() == 1 ? "ma" : "mu"; + s << "e" << sew; + if(insn.v_frac_lmul()) { + std::string lmul_str = ""; + switch(lmul){ + case 3: + lmul_str = "f2"; + break; + case 2: + lmul_str = "f4"; + break; + case 1: + lmul_str = "f8"; + break; + default: + assert(true && "unsupport fractional LMUL"); + } + s << ", m" << lmul_str; + } else { + s << ", m" << (1 << lmul); + } + s << ", " << vta << ", " << vma; + return s.str(); + } +} v_vtype; + +struct : public arg_t { + std::string to_string(insn_t UNUSED insn) const { + return "x0"; + } +} x0; + +struct : public arg_t { + std::string to_string(insn_t insn) const { + std::string s; + auto iorw = insn.iorw(); + bool has_pre = false; + static const char type[] = "wroi"; + for (int i = 7; i >= 4; --i) { + if (iorw & (1ul << i)) { + s += type[i - 4]; + has_pre = true; + } + } + + s += (has_pre ? "," : ""); + for (int i = 3; i >= 0; --i) { + if (iorw & (1ul << i)) { + s += type[i]; + } + } + + return s; + } +} iorw; + +struct : public arg_t { + std::string to_string(insn_t insn) const { + return std::to_string((int)insn.p_imm2()); + } +} p_imm2; + +struct : public arg_t { + std::string to_string(insn_t insn) const { + return std::to_string((int)insn.p_imm3()); + } +} p_imm3; + +struct : public arg_t { + std::string to_string(insn_t insn) const { + return std::to_string((int)insn.p_imm4()); + } +} p_imm4; + +struct : public arg_t { + std::string to_string(insn_t insn) const { + return std::to_string((int)insn.p_imm5()); + } +} p_imm5; + +struct : public arg_t { + std::string to_string(insn_t insn) const { + return std::to_string((int)insn.p_imm6()); + } +} p_imm6; + +struct : public arg_t { + std::string to_string(insn_t insn) const { + return std::to_string((int)insn.bs()); + } +} bs; + +struct : public arg_t { + std::string to_string(insn_t insn) const { + return std::to_string((int)insn.rcon()); + } +} rcon; + +typedef struct { + reg_t match; + reg_t mask; + const char *fmt; + std::vector<const arg_t*>& arg; +} custom_fmt_t; + +std::string disassembler_t::disassemble(insn_t insn) const +{ + const disasm_insn_t* disasm_insn = lookup(insn); + return disasm_insn ? disasm_insn->to_string(insn) : "unknown"; +} + +static void NOINLINE add_noarg_insn(disassembler_t* d, const char* name, uint32_t match, uint32_t mask) +{ + d->add_insn(new disasm_insn_t(name, match, mask, {})); +} + +static void NOINLINE add_rtype_insn(disassembler_t* d, const char* name, uint32_t match, uint32_t mask) +{ + d->add_insn(new disasm_insn_t(name, match, mask, {&xrd, &xrs1, &xrs2})); +} + +static void NOINLINE add_r1type_insn(disassembler_t* d, const char* name, uint32_t match, uint32_t mask) +{ + d->add_insn(new disasm_insn_t(name, match, mask, {&xrd, &xrs1})); +} + +static void NOINLINE add_r3type_insn(disassembler_t* d, const char* name, uint32_t match, uint32_t mask) +{ + d->add_insn(new disasm_insn_t(name, match, mask, {&xrd, &xrs1, &xrs2, &xrs3})); +} + +static void NOINLINE add_itype_insn(disassembler_t* d, const char* name, uint32_t match, uint32_t mask) +{ + d->add_insn(new disasm_insn_t(name, match, mask, {&xrd, &xrs1, &imm})); +} + +static void NOINLINE add_itype_shift_insn(disassembler_t* d, const char* name, uint32_t match, uint32_t mask) +{ + d->add_insn(new disasm_insn_t(name, match, mask, {&xrd, &xrs1, &shamt})); +} + +static void NOINLINE add_xload_insn(disassembler_t* d, const char* name, uint32_t match, uint32_t mask) +{ + d->add_insn(new disasm_insn_t(name, match, mask, {&xrd, &load_address})); +} + +static void NOINLINE add_xstore_insn(disassembler_t* d, const char* name, uint32_t match, uint32_t mask) +{ + d->add_insn(new disasm_insn_t(name, match, mask, {&xrs2, &store_address})); +} + +static void NOINLINE add_fload_insn(disassembler_t* d, const char* name, uint32_t match, uint32_t mask) +{ + d->add_insn(new disasm_insn_t(name, match, mask, {&frd, &load_address})); +} + +static void NOINLINE add_fstore_insn(disassembler_t* d, const char* name, uint32_t match, uint32_t mask) +{ + d->add_insn(new disasm_insn_t(name, match, mask, {&frs2, &store_address})); +} + +static void NOINLINE add_xamo_insn(disassembler_t* d, const char* name, uint32_t match, uint32_t mask) +{ + d->add_insn(new disasm_insn_t(name, match, mask, {&xrd, &xrs2, &base_only_address})); +} + +static void NOINLINE add_xlr_insn(disassembler_t* d, const char* name, uint32_t match, uint32_t mask) +{ + d->add_insn(new disasm_insn_t(name, match, mask, {&xrd, &base_only_address})); +} + +static void NOINLINE add_xst_insn(disassembler_t* d, const char* name, uint32_t match, uint32_t mask) +{ + d->add_insn(new disasm_insn_t(name, match, mask, {&xrs2, &base_only_address})); +} + +static void NOINLINE add_btype_insn(disassembler_t* d, const char* name, uint32_t match, uint32_t mask) +{ + d->add_insn(new disasm_insn_t(name, match, mask, {&xrs1, &xrs2, &branch_target})); +} + +static void NOINLINE add_b1type_insn(disassembler_t* d, const char* name, uint32_t match, uint32_t mask) +{ + const uint32_t mask_rs2 = 0x1fUL << 20; + d->add_insn(new disasm_insn_t(name, match, mask | mask_rs2, {&xrs1, &branch_target})); +} + +static void NOINLINE add_frtype_insn(disassembler_t* d, const char* name, uint32_t match, uint32_t mask) +{ + d->add_insn(new disasm_insn_t(name, match, mask, {&frd, &frs1, &frs2})); +} + +static void NOINLINE add_fr1type_insn(disassembler_t* d, const char* name, uint32_t match, uint32_t mask) +{ + d->add_insn(new disasm_insn_t(name, match, mask, {&frd, &frs1})); +} + +static void NOINLINE add_fr3type_insn(disassembler_t* d, const char* name, uint32_t match, uint32_t mask) +{ + d->add_insn(new disasm_insn_t(name, match, mask, {&frd, &frs1, &frs2, &frs3})); +} + +static void NOINLINE add_fxtype_insn(disassembler_t* d, const char* name, uint32_t match, uint32_t mask) +{ + d->add_insn(new disasm_insn_t(name, match, mask, {&xrd, &frs1})); +} + +static void NOINLINE add_xftype_insn(disassembler_t* d, const char* name, uint32_t match, uint32_t mask) +{ + d->add_insn(new disasm_insn_t(name, match, mask, {&frd, &xrs1})); +} + +static void NOINLINE add_fx2type_insn(disassembler_t* d, const char* name, uint32_t match, uint32_t mask) +{ + d->add_insn(new disasm_insn_t(name, match, mask, {&xrd, &frs1, &frs2})); +} + +static void NOINLINE add_sfence_insn(disassembler_t* d, const char* name, uint32_t match, uint32_t mask) +{ + d->add_insn(new disasm_insn_t(name, match, mask, {&xrs1, &xrs2})); +} + +static void NOINLINE add_pitype3_insn(disassembler_t* d, const char* name, uint32_t match, uint32_t mask) +{ + d->add_insn(new disasm_insn_t(name, match, mask, {&xrd, &xrs1, &p_imm3})); +} + +static void NOINLINE add_pitype4_insn(disassembler_t* d, const char* name, uint32_t match, uint32_t mask) +{ + d->add_insn(new disasm_insn_t(name, match, mask, {&xrd, &xrs1, &p_imm4})); +} + +static void NOINLINE add_pitype5_insn(disassembler_t* d, const char* name, uint32_t match, uint32_t mask) +{ + d->add_insn(new disasm_insn_t(name, match, mask, {&xrd, &xrs1, &p_imm5})); +} + +static void NOINLINE add_pitype6_insn(disassembler_t* d, const char* name, uint32_t match, uint32_t mask) +{ + d->add_insn(new disasm_insn_t(name, match, mask, {&xrd, &xrs1, &p_imm6})); +} + +static void NOINLINE add_vector_v_insn(disassembler_t* d, const char* name, uint32_t match, uint32_t mask) +{ + d->add_insn(new disasm_insn_t(name, match, mask, {&vd, &vs2, opt, &vm})); +} + +static void NOINLINE add_vector_vv_insn(disassembler_t* d, const char* name, uint32_t match, uint32_t mask) +{ + d->add_insn(new disasm_insn_t(name, match, mask, {&vd, &vs2, &vs1, opt, &vm})); +} + +static void NOINLINE add_vector_vx_insn(disassembler_t* d, const char* name, uint32_t match, uint32_t mask) +{ + d->add_insn(new disasm_insn_t(name, match, mask, {&vd, &vs2, &xrs1, opt, &vm})); +} + +static void NOINLINE add_vector_vf_insn(disassembler_t* d, const char* name, uint32_t match, uint32_t mask) +{ + d->add_insn(new disasm_insn_t(name, match, mask, {&vd, &vs2, &frs1, opt, &vm})); +} + +static void NOINLINE add_vector_vi_insn(disassembler_t* d, const char* name, uint32_t match, uint32_t mask) +{ + d->add_insn(new disasm_insn_t(name, match, mask, {&vd, &vs2, &v_simm5, opt, &vm})); +} + +static void NOINLINE add_vector_viu_insn(disassembler_t* d, const char* name, uint32_t match, uint32_t mask) +{ + d->add_insn(new disasm_insn_t(name, match, mask, {&vd, &vs2, &zimm5, opt, &vm})); +} + +static void NOINLINE add_vector_vvm_insn(disassembler_t* d, const char* name, uint32_t match, uint32_t mask) +{ + d->add_insn(new disasm_insn_t(name, match, mask, {&vd, &vs2, &vs1, &v0})); +} + +static void NOINLINE add_vector_vxm_insn(disassembler_t* d, const char* name, uint32_t match, uint32_t mask) +{ + d->add_insn(new disasm_insn_t(name, match, mask, {&vd, &vs2, &xrs1, &v0})); +} + +static void NOINLINE add_vector_vim_insn(disassembler_t* d, const char* name, uint32_t match, uint32_t mask) +{ + d->add_insn(new disasm_insn_t(name, match, mask, {&vd, &vs2, &v_simm5, &v0})); +} + +static void NOINLINE add_unknown_insn(disassembler_t* d, const char* name, uint32_t match, uint32_t mask) +{ + std::string s = name; + s += " (args unknown)"; + + d->add_insn(new disasm_insn_t(s.c_str(), match, mask, {})); +} + + +static void NOINLINE add_unknown_insns(disassembler_t* d) +{ + // provide a default disassembly for all instructions as a fallback + #define DECLARE_INSN(code, match, mask) \ + add_unknown_insn(d, #code, match, mask); + #include "encoding.h" + #undef DECLARE_INSN +} + +void disassembler_t::add_instructions(const isa_parser_t* isa) +{ + const uint32_t mask_rd = 0x1fUL << 7; + const uint32_t match_rd_ra = 1UL << 7; + const uint32_t mask_rs1 = 0x1fUL << 15; + const uint32_t match_rs1_ra = 1UL << 15; + const uint32_t mask_rs2 = 0x1fUL << 20; + const uint32_t mask_imm = 0xfffUL << 20; + const uint32_t imm_shift = 20; + const uint32_t mask_rvc_rs2 = 0x1fUL << 2; + const uint32_t mask_rvc_imm = mask_rvc_rs2 | 0x1000UL; + const uint32_t mask_nf = 0x7Ul << 29; + const uint32_t mask_wd = 0x1Ul << 26; + const uint32_t mask_vm = 0x1Ul << 25; + const uint32_t mask_vldst = 0x7Ul << 12 | 0x1UL << 28; + const uint32_t mask_amoop = 0x1fUl << 27; + const uint32_t mask_width = 0x7Ul << 12; + + #define DECLARE_INSN(code, match, mask) \ + const uint32_t match_##code = match; \ + const uint32_t mask_##code = mask; + #include "encoding.h" + #undef DECLARE_INSN + + // explicit per-instruction disassembly + #define DISASM_INSN(name, code, extra, ...) \ + add_insn(new disasm_insn_t(name, match_##code, mask_##code | (extra), __VA_ARGS__)); + #define DEFINE_NOARG(code) add_noarg_insn(this, #code, match_##code, mask_##code); + #define DEFINE_RTYPE(code) add_rtype_insn(this, #code, match_##code, mask_##code); + #define DEFINE_R1TYPE(code) add_r1type_insn(this, #code, match_##code, mask_##code); + #define DEFINE_R3TYPE(code) add_r3type_insn(this, #code, match_##code, mask_##code); + #define DEFINE_ITYPE(code) add_itype_insn(this, #code, match_##code, mask_##code); + #define DEFINE_ITYPE_SHIFT(code) add_itype_shift_insn(this, #code, match_##code, mask_##code); + #define DEFINE_I0TYPE(name, code) DISASM_INSN(name, code, mask_rs1, {&xrd, &imm}) + #define DEFINE_I1TYPE(name, code) DISASM_INSN(name, code, mask_imm, {&xrd, &xrs1}) + #define DEFINE_I2TYPE(name, code) DISASM_INSN(name, code, mask_rd | mask_imm, {&xrs1}) + #define DEFINE_PREFETCH(code) DISASM_INSN(#code, code, 0, {&store_address}) + #define DEFINE_LTYPE(code) DISASM_INSN(#code, code, 0, {&xrd, &bigimm}) + #define DEFINE_BTYPE(code) add_btype_insn(this, #code, match_##code, mask_##code); + #define DEFINE_B1TYPE(name, code) add_b1type_insn(this, name, match_##code, mask_##code); + #define DEFINE_XLOAD(code) add_xload_insn(this, #code, match_##code, mask_##code); + #define DEFINE_XSTORE(code) add_xstore_insn(this, #code, match_##code, mask_##code); + #define DEFINE_XAMO(code) add_xamo_insn(this, #code, match_##code, mask_##code); + #define DEFINE_XLOAD_BASE(code) add_xlr_insn(this, #code, match_##code, mask_##code); + #define DEFINE_XSTORE_BASE(code) add_xst_insn(this, #code, match_##code, mask_##code); + #define DEFINE_FLOAD(code) add_fload_insn(this, #code, match_##code, mask_##code); + #define DEFINE_FSTORE(code) add_fstore_insn(this, #code, match_##code, mask_##code); + #define DEFINE_FRTYPE(code) add_frtype_insn(this, #code, match_##code, mask_##code); + #define DEFINE_FR1TYPE(code) add_fr1type_insn(this, #code, match_##code, mask_##code); + #define DEFINE_FR3TYPE(code) add_fr3type_insn(this, #code, match_##code, mask_##code); + #define DEFINE_FXTYPE(code) add_fxtype_insn(this, #code, match_##code, mask_##code); + #define DEFINE_FX2TYPE(code) add_fx2type_insn(this, #code, match_##code, mask_##code); + #define DEFINE_XFTYPE(code) add_xftype_insn(this, #code, match_##code, mask_##code); + #define DEFINE_SFENCE_TYPE(code) add_sfence_insn(this, #code, match_##code, mask_##code); + + add_insn(new disasm_insn_t("unimp", match_csrrw|(CSR_CYCLE<<20), 0xffffffff, {})); + add_insn(new disasm_insn_t("c.unimp", 0, 0xffff, {})); + + // Following are HINTs, so they must precede their corresponding base-ISA + // instructions. We do not condition them on Zicbop/Zihintpause because, + // definitionally, all implementations provide them. + DEFINE_PREFETCH(prefetch_r); + DEFINE_PREFETCH(prefetch_w); + DEFINE_PREFETCH(prefetch_i); + DEFINE_NOARG(pause); + + DEFINE_XLOAD(lb) + DEFINE_XLOAD(lbu) + DEFINE_XLOAD(lh) + DEFINE_XLOAD(lhu) + DEFINE_XLOAD(lw) + DEFINE_XLOAD(lwu) + DEFINE_XLOAD(ld) + + DEFINE_XSTORE(sb) + DEFINE_XSTORE(sh) + DEFINE_XSTORE(sw) + DEFINE_XSTORE(sd) + + if (isa->extension_enabled('A')) { + DEFINE_XAMO(amoadd_w) + DEFINE_XAMO(amoswap_w) + DEFINE_XAMO(amoand_w) + DEFINE_XAMO(amoor_w) + DEFINE_XAMO(amoxor_w) + DEFINE_XAMO(amomin_w) + DEFINE_XAMO(amomax_w) + DEFINE_XAMO(amominu_w) + DEFINE_XAMO(amomaxu_w) + DEFINE_XAMO(amoadd_d) + DEFINE_XAMO(amoswap_d) + DEFINE_XAMO(amoand_d) + DEFINE_XAMO(amoor_d) + DEFINE_XAMO(amoxor_d) + DEFINE_XAMO(amomin_d) + DEFINE_XAMO(amomax_d) + DEFINE_XAMO(amominu_d) + DEFINE_XAMO(amomaxu_d) + DEFINE_XLOAD_BASE(lr_w) + DEFINE_XAMO(sc_w) + DEFINE_XLOAD_BASE(lr_d) + DEFINE_XAMO(sc_d) + } + + add_insn(new disasm_insn_t("j", match_jal, mask_jal | mask_rd, {&jump_target})); + add_insn(new disasm_insn_t("jal", match_jal | match_rd_ra, mask_jal | mask_rd, {&jump_target})); + add_insn(new disasm_insn_t("jal", match_jal, mask_jal, {&xrd, &jump_target})); + + DEFINE_B1TYPE("beqz", beq); + DEFINE_B1TYPE("bnez", bne); + DEFINE_B1TYPE("bltz", blt); + DEFINE_B1TYPE("bgez", bge); + DEFINE_BTYPE(beq) + DEFINE_BTYPE(bne) + DEFINE_BTYPE(blt) + DEFINE_BTYPE(bge) + DEFINE_BTYPE(bltu) + DEFINE_BTYPE(bgeu) + + DEFINE_LTYPE(lui); + DEFINE_LTYPE(auipc); + + add_insn(new disasm_insn_t("ret", match_jalr | match_rs1_ra, mask_jalr | mask_rd | mask_rs1 | mask_imm, {})); + DEFINE_I2TYPE("jr", jalr); + add_insn(new disasm_insn_t("jalr", match_jalr | match_rd_ra, mask_jalr | mask_rd | mask_imm, {&xrs1})); + DEFINE_ITYPE(jalr); + + add_noarg_insn(this, "nop", match_addi, mask_addi | mask_rd | mask_rs1 | mask_imm); + DEFINE_I0TYPE("li", addi); + DEFINE_I1TYPE("mv", addi); + DEFINE_ITYPE(addi); + DEFINE_ITYPE(slti); + add_insn(new disasm_insn_t("seqz", match_sltiu | (1 << imm_shift), mask_sltiu | mask_imm, {&xrd, &xrs1})); + DEFINE_ITYPE(sltiu); + add_insn(new disasm_insn_t("not", match_xori | mask_imm, mask_xori | mask_imm, {&xrd, &xrs1})); + DEFINE_ITYPE(xori); + + DEFINE_ITYPE_SHIFT(slli); + DEFINE_ITYPE_SHIFT(srli); + DEFINE_ITYPE_SHIFT(srai); + + DEFINE_ITYPE(ori); + DEFINE_ITYPE(andi); + DEFINE_I1TYPE("sext.w", addiw); + DEFINE_ITYPE(addiw); + + DEFINE_ITYPE_SHIFT(slliw); + DEFINE_ITYPE_SHIFT(srliw); + DEFINE_ITYPE_SHIFT(sraiw); + + DEFINE_RTYPE(add); + DEFINE_RTYPE(sub); + DEFINE_RTYPE(sll); + DEFINE_RTYPE(slt); + add_insn(new disasm_insn_t("snez", match_sltu, mask_sltu | mask_rs1, {&xrd, &xrs2})); + DEFINE_RTYPE(sltu); + DEFINE_RTYPE(xor); + DEFINE_RTYPE(srl); + DEFINE_RTYPE(sra); + DEFINE_RTYPE(or); + DEFINE_RTYPE(and); + DEFINE_RTYPE(addw); + DEFINE_RTYPE(subw); + DEFINE_RTYPE(sllw); + DEFINE_RTYPE(srlw); + DEFINE_RTYPE(sraw); + + DEFINE_NOARG(ecall); + DEFINE_NOARG(ebreak); + DEFINE_NOARG(mret); + DEFINE_NOARG(dret); + DEFINE_NOARG(wfi); + add_insn(new disasm_insn_t("fence", match_fence, mask_fence, {&iorw})); + DEFINE_NOARG(fence_i); + + add_insn(new disasm_insn_t("csrr", match_csrrs, mask_csrrs | mask_rs1, {&xrd, &csr})); + add_insn(new disasm_insn_t("csrw", match_csrrw, mask_csrrw | mask_rd, {&csr, &xrs1})); + add_insn(new disasm_insn_t("csrs", match_csrrs, mask_csrrs | mask_rd, {&csr, &xrs1})); + add_insn(new disasm_insn_t("csrc", match_csrrc, mask_csrrc | mask_rd, {&csr, &xrs1})); + add_insn(new disasm_insn_t("csrwi", match_csrrwi, mask_csrrwi | mask_rd, {&csr, &zimm5})); + add_insn(new disasm_insn_t("csrsi", match_csrrsi, mask_csrrsi | mask_rd, {&csr, &zimm5})); + add_insn(new disasm_insn_t("csrci", match_csrrci, mask_csrrci | mask_rd, {&csr, &zimm5})); + add_insn(new disasm_insn_t("csrrw", match_csrrw, mask_csrrw, {&xrd, &csr, &xrs1})); + add_insn(new disasm_insn_t("csrrs", match_csrrs, mask_csrrs, {&xrd, &csr, &xrs1})); + add_insn(new disasm_insn_t("csrrc", match_csrrc, mask_csrrc, {&xrd, &csr, &xrs1})); + add_insn(new disasm_insn_t("csrrwi", match_csrrwi, mask_csrrwi, {&xrd, &csr, &zimm5})); + add_insn(new disasm_insn_t("csrrsi", match_csrrsi, mask_csrrsi, {&xrd, &csr, &zimm5})); + add_insn(new disasm_insn_t("csrrci", match_csrrci, mask_csrrci, {&xrd, &csr, &zimm5})); + + if (isa->extension_enabled('S')) { + DEFINE_NOARG(sret); + DEFINE_SFENCE_TYPE(sfence_vma); + } + + if (isa->extension_enabled('M')) { + DEFINE_RTYPE(mul); + DEFINE_RTYPE(mulh); + DEFINE_RTYPE(mulhu); + DEFINE_RTYPE(mulhsu); + DEFINE_RTYPE(mulw); + DEFINE_RTYPE(div); + DEFINE_RTYPE(divu); + DEFINE_RTYPE(rem); + DEFINE_RTYPE(remu); + DEFINE_RTYPE(divw); + DEFINE_RTYPE(divuw); + DEFINE_RTYPE(remw); + DEFINE_RTYPE(remuw); + } + + if (isa->extension_enabled(EXT_ZBA)) { + DEFINE_RTYPE(sh1add); + DEFINE_RTYPE(sh2add); + DEFINE_RTYPE(sh3add); + if (isa->get_max_xlen() == 64) { + DEFINE_ITYPE_SHIFT(slli_uw); + add_insn(new disasm_insn_t("zext.w", match_add_uw, mask_add_uw | mask_rs2, {&xrd, &xrs1})); + DEFINE_RTYPE(add_uw); + DEFINE_RTYPE(sh1add_uw); + DEFINE_RTYPE(sh2add_uw); + DEFINE_RTYPE(sh3add_uw); + } + } + + if (isa->extension_enabled(EXT_ZBB)) { + DEFINE_RTYPE(ror); + DEFINE_RTYPE(rol); + DEFINE_ITYPE_SHIFT(rori); + DEFINE_R1TYPE(ctz); + DEFINE_R1TYPE(clz); + DEFINE_R1TYPE(cpop); + DEFINE_RTYPE(min); + DEFINE_RTYPE(minu); + DEFINE_RTYPE(max); + DEFINE_RTYPE(maxu); + DEFINE_RTYPE(andn); + DEFINE_RTYPE(orn); + DEFINE_RTYPE(xnor); + DEFINE_R1TYPE(sext_b); + DEFINE_R1TYPE(sext_h); + add_insn(new disasm_insn_t("rev8", match_grevi | ((isa->get_max_xlen() - 8) << imm_shift), mask_grevi | mask_imm, {&xrd, &xrs1})); + add_insn(new disasm_insn_t("orc.b", match_gorci | (0x7 << imm_shift), mask_grevi | mask_imm, {&xrd, &xrs1})); + add_insn(new disasm_insn_t("zext.h", (isa->get_max_xlen() == 32 ? match_pack : match_packw), mask_pack | mask_rs2, {&xrd, &xrs1})); + if (isa->get_max_xlen() == 64) { + DEFINE_RTYPE(rorw); + DEFINE_RTYPE(rolw); + DEFINE_ITYPE_SHIFT(roriw); + DEFINE_R1TYPE(ctzw); + DEFINE_R1TYPE(clzw); + DEFINE_R1TYPE(cpopw); + } + } + + if (isa->extension_enabled(EXT_ZBC)) { + DEFINE_RTYPE(clmul); + DEFINE_RTYPE(clmulh); + DEFINE_RTYPE(clmulr); + } + + if (isa->extension_enabled(EXT_ZBS)) { + DEFINE_RTYPE(bclr); + DEFINE_RTYPE(binv); + DEFINE_RTYPE(bset); + DEFINE_RTYPE(bext); + DEFINE_ITYPE_SHIFT(bclri); + DEFINE_ITYPE_SHIFT(binvi); + DEFINE_ITYPE_SHIFT(bseti); + DEFINE_ITYPE_SHIFT(bexti); + } + + if (isa->extension_enabled(EXT_ZBKB)) { + add_insn(new disasm_insn_t("brev8", match_grevi | (0x7 << imm_shift), mask_grevi | mask_imm, {&xrd, &xrs1})); // brev8 + add_insn(new disasm_insn_t("rev8", match_grevi | ((isa->get_max_xlen() - 8) << imm_shift), mask_grevi | mask_imm, {&xrd, &xrs1})); + DEFINE_RTYPE(pack); + DEFINE_RTYPE(packh); + if (isa->get_max_xlen() == 64) { + DEFINE_RTYPE(packw); + } + } + + if (isa->extension_enabled(EXT_SVINVAL)) { + DEFINE_NOARG(sfence_w_inval); + DEFINE_NOARG(sfence_inval_ir); + DEFINE_SFENCE_TYPE(sinval_vma); + DEFINE_SFENCE_TYPE(hinval_vvma); + DEFINE_SFENCE_TYPE(hinval_gvma); + } + + if (isa->extension_enabled('F')) { + DEFINE_FLOAD(flw) + DEFINE_FSTORE(fsw) + DEFINE_FRTYPE(fadd_s); + DEFINE_FRTYPE(fsub_s); + DEFINE_FRTYPE(fmul_s); + DEFINE_FRTYPE(fdiv_s); + DEFINE_FR1TYPE(fsqrt_s); + DEFINE_FRTYPE(fmin_s); + DEFINE_FRTYPE(fmax_s); + DEFINE_FR3TYPE(fmadd_s); + DEFINE_FR3TYPE(fmsub_s); + DEFINE_FR3TYPE(fnmadd_s); + DEFINE_FR3TYPE(fnmsub_s); + DEFINE_FRTYPE(fsgnj_s); + DEFINE_FRTYPE(fsgnjn_s); + DEFINE_FRTYPE(fsgnjx_s); + DEFINE_FR1TYPE(fcvt_s_d); + DEFINE_FR1TYPE(fcvt_s_q); + DEFINE_XFTYPE(fcvt_s_l); + DEFINE_XFTYPE(fcvt_s_lu); + DEFINE_XFTYPE(fcvt_s_w); + DEFINE_XFTYPE(fcvt_s_wu); + DEFINE_XFTYPE(fcvt_s_wu); + DEFINE_XFTYPE(fmv_w_x); + DEFINE_FXTYPE(fcvt_l_s); + DEFINE_FXTYPE(fcvt_lu_s); + DEFINE_FXTYPE(fcvt_w_s); + DEFINE_FXTYPE(fcvt_wu_s); + DEFINE_FXTYPE(fclass_s); + DEFINE_FXTYPE(fmv_x_w); + DEFINE_FX2TYPE(feq_s); + DEFINE_FX2TYPE(flt_s); + DEFINE_FX2TYPE(fle_s); + } + + if (isa->extension_enabled(EXT_ZFINX)) { + DEFINE_RTYPE(fadd_s); + DEFINE_RTYPE(fsub_s); + DEFINE_RTYPE(fmul_s); + DEFINE_RTYPE(fdiv_s); + DEFINE_R1TYPE(fsqrt_s); + DEFINE_RTYPE(fmin_s); + DEFINE_RTYPE(fmax_s); + DEFINE_R3TYPE(fmadd_s); + DEFINE_R3TYPE(fmsub_s); + DEFINE_R3TYPE(fnmadd_s); + DEFINE_R3TYPE(fnmsub_s); + DEFINE_RTYPE(fsgnj_s); + DEFINE_RTYPE(fsgnjn_s); + DEFINE_RTYPE(fsgnjx_s); + DEFINE_R1TYPE(fcvt_s_d); + //DEFINE_R1TYPE(fcvt_s_q); + DEFINE_R1TYPE(fcvt_s_l); + DEFINE_R1TYPE(fcvt_s_lu); + DEFINE_R1TYPE(fcvt_s_w); + DEFINE_R1TYPE(fcvt_s_wu); + DEFINE_R1TYPE(fcvt_s_wu); + DEFINE_R1TYPE(fcvt_l_s); + DEFINE_R1TYPE(fcvt_lu_s); + DEFINE_R1TYPE(fcvt_w_s); + DEFINE_R1TYPE(fcvt_wu_s); + DEFINE_R1TYPE(fclass_s); + DEFINE_RTYPE(feq_s); + DEFINE_RTYPE(flt_s); + DEFINE_RTYPE(fle_s); + } + + if (isa->extension_enabled('D')) { + DEFINE_FLOAD(fld) + DEFINE_FSTORE(fsd) + DEFINE_FRTYPE(fadd_d); + DEFINE_FRTYPE(fsub_d); + DEFINE_FRTYPE(fmul_d); + DEFINE_FRTYPE(fdiv_d); + DEFINE_FR1TYPE(fsqrt_d); + DEFINE_FRTYPE(fmin_d); + DEFINE_FRTYPE(fmax_d); + DEFINE_FR3TYPE(fmadd_d); + DEFINE_FR3TYPE(fmsub_d); + DEFINE_FR3TYPE(fnmadd_d); + DEFINE_FR3TYPE(fnmsub_d); + DEFINE_FRTYPE(fsgnj_d); + DEFINE_FRTYPE(fsgnjn_d); + DEFINE_FRTYPE(fsgnjx_d); + DEFINE_FR1TYPE(fcvt_d_s); + DEFINE_FR1TYPE(fcvt_d_q); + DEFINE_XFTYPE(fcvt_d_l); + DEFINE_XFTYPE(fcvt_d_lu); + DEFINE_XFTYPE(fcvt_d_w); + DEFINE_XFTYPE(fcvt_d_wu); + DEFINE_XFTYPE(fcvt_d_wu); + DEFINE_XFTYPE(fmv_d_x); + DEFINE_FXTYPE(fcvt_l_d); + DEFINE_FXTYPE(fcvt_lu_d); + DEFINE_FXTYPE(fcvt_w_d); + DEFINE_FXTYPE(fcvt_wu_d); + DEFINE_FXTYPE(fclass_d); + DEFINE_FXTYPE(fmv_x_d); + DEFINE_FX2TYPE(feq_d); + DEFINE_FX2TYPE(flt_d); + DEFINE_FX2TYPE(fle_d); + } + + if (isa->extension_enabled(EXT_ZDINX)) { + DEFINE_RTYPE(fadd_d); + DEFINE_RTYPE(fsub_d); + DEFINE_RTYPE(fmul_d); + DEFINE_RTYPE(fdiv_d); + DEFINE_R1TYPE(fsqrt_d); + DEFINE_RTYPE(fmin_d); + DEFINE_RTYPE(fmax_d); + DEFINE_R3TYPE(fmadd_d); + DEFINE_R3TYPE(fmsub_d); + DEFINE_R3TYPE(fnmadd_d); + DEFINE_R3TYPE(fnmsub_d); + DEFINE_RTYPE(fsgnj_d); + DEFINE_RTYPE(fsgnjn_d); + DEFINE_RTYPE(fsgnjx_d); + DEFINE_R1TYPE(fcvt_d_s); + //DEFINE_R1TYPE(fcvt_d_q); + DEFINE_R1TYPE(fcvt_d_l); + DEFINE_R1TYPE(fcvt_d_lu); + DEFINE_R1TYPE(fcvt_d_w); + DEFINE_R1TYPE(fcvt_d_wu); + DEFINE_R1TYPE(fcvt_d_wu); + DEFINE_R1TYPE(fcvt_l_d); + DEFINE_R1TYPE(fcvt_lu_d); + DEFINE_R1TYPE(fcvt_w_d); + DEFINE_R1TYPE(fcvt_wu_d); + DEFINE_R1TYPE(fclass_d); + DEFINE_RTYPE(feq_d); + DEFINE_RTYPE(flt_d); + DEFINE_RTYPE(fle_d); + } + + if (isa->extension_enabled(EXT_ZFH)) { + DEFINE_FRTYPE(fadd_h); + DEFINE_FRTYPE(fsub_h); + DEFINE_FRTYPE(fmul_h); + DEFINE_FRTYPE(fdiv_h); + DEFINE_FR1TYPE(fsqrt_h); + DEFINE_FRTYPE(fmin_h); + DEFINE_FRTYPE(fmax_h); + DEFINE_FR3TYPE(fmadd_h); + DEFINE_FR3TYPE(fmsub_h); + DEFINE_FR3TYPE(fnmadd_h); + DEFINE_FR3TYPE(fnmsub_h); + DEFINE_FRTYPE(fsgnj_h); + DEFINE_FRTYPE(fsgnjn_h); + DEFINE_FRTYPE(fsgnjx_h); + DEFINE_XFTYPE(fcvt_h_l); + DEFINE_XFTYPE(fcvt_h_lu); + DEFINE_XFTYPE(fcvt_h_w); + DEFINE_XFTYPE(fcvt_h_wu); + DEFINE_XFTYPE(fcvt_h_wu); + DEFINE_FXTYPE(fcvt_l_h); + DEFINE_FXTYPE(fcvt_lu_h); + DEFINE_FXTYPE(fcvt_w_h); + DEFINE_FXTYPE(fcvt_wu_h); + DEFINE_FXTYPE(fclass_h); + DEFINE_FX2TYPE(feq_h); + DEFINE_FX2TYPE(flt_h); + DEFINE_FX2TYPE(fle_h); + } + + if (isa->extension_enabled(EXT_ZHINX)) { + DEFINE_RTYPE(fadd_h); + DEFINE_RTYPE(fsub_h); + DEFINE_RTYPE(fmul_h); + DEFINE_RTYPE(fdiv_h); + DEFINE_R1TYPE(fsqrt_h); + DEFINE_RTYPE(fmin_h); + DEFINE_RTYPE(fmax_h); + DEFINE_R3TYPE(fmadd_h); + DEFINE_R3TYPE(fmsub_h); + DEFINE_R3TYPE(fnmadd_h); + DEFINE_R3TYPE(fnmsub_h); + DEFINE_RTYPE(fsgnj_h); + DEFINE_RTYPE(fsgnjn_h); + DEFINE_RTYPE(fsgnjx_h); + DEFINE_R1TYPE(fcvt_h_l); + DEFINE_R1TYPE(fcvt_h_lu); + DEFINE_R1TYPE(fcvt_h_w); + DEFINE_R1TYPE(fcvt_h_wu); + DEFINE_R1TYPE(fcvt_h_wu); + DEFINE_R1TYPE(fcvt_l_h); + DEFINE_R1TYPE(fcvt_lu_h); + DEFINE_R1TYPE(fcvt_w_h); + DEFINE_R1TYPE(fcvt_wu_h); + DEFINE_R1TYPE(fclass_h); + DEFINE_RTYPE(feq_h); + DEFINE_RTYPE(flt_h); + DEFINE_RTYPE(fle_h); + } + + if (isa->extension_enabled(EXT_ZFHMIN)) { + DEFINE_FLOAD(flh) + DEFINE_FSTORE(fsh) + DEFINE_FR1TYPE(fcvt_h_s); + DEFINE_FR1TYPE(fcvt_h_d); + DEFINE_FR1TYPE(fcvt_h_q); + DEFINE_FR1TYPE(fcvt_s_h); + DEFINE_FR1TYPE(fcvt_d_h); + DEFINE_FR1TYPE(fcvt_q_h); + DEFINE_XFTYPE(fmv_h_x); + DEFINE_FXTYPE(fmv_x_h); + } + + if (isa->extension_enabled(EXT_ZHINXMIN)) { + DEFINE_R1TYPE(fcvt_h_s); + DEFINE_R1TYPE(fcvt_h_d); + //DEFINE_R1TYPE(fcvt_h_q); + DEFINE_R1TYPE(fcvt_s_h); + DEFINE_R1TYPE(fcvt_d_h); + //DEFINE_R1TYPE(fcvt_q_h); + } + + if (isa->extension_enabled('Q')) { + DEFINE_FLOAD(flq) + DEFINE_FSTORE(fsq) + DEFINE_FRTYPE(fadd_q); + DEFINE_FRTYPE(fsub_q); + DEFINE_FRTYPE(fmul_q); + DEFINE_FRTYPE(fdiv_q); + DEFINE_FR1TYPE(fsqrt_q); + DEFINE_FRTYPE(fmin_q); + DEFINE_FRTYPE(fmax_q); + DEFINE_FR3TYPE(fmadd_q); + DEFINE_FR3TYPE(fmsub_q); + DEFINE_FR3TYPE(fnmadd_q); + DEFINE_FR3TYPE(fnmsub_q); + DEFINE_FRTYPE(fsgnj_q); + DEFINE_FRTYPE(fsgnjn_q); + DEFINE_FRTYPE(fsgnjx_q); + DEFINE_FR1TYPE(fcvt_q_s); + DEFINE_FR1TYPE(fcvt_q_d); + DEFINE_XFTYPE(fcvt_q_l); + DEFINE_XFTYPE(fcvt_q_lu); + DEFINE_XFTYPE(fcvt_q_w); + DEFINE_XFTYPE(fcvt_q_wu); + DEFINE_XFTYPE(fcvt_q_wu); + DEFINE_FXTYPE(fcvt_l_q); + DEFINE_FXTYPE(fcvt_lu_q); + DEFINE_FXTYPE(fcvt_w_q); + DEFINE_FXTYPE(fcvt_wu_q); + DEFINE_FXTYPE(fclass_q); + DEFINE_FX2TYPE(feq_q); + DEFINE_FX2TYPE(flt_q); + DEFINE_FX2TYPE(fle_q); + } + + // ext-h + if (isa->extension_enabled('H')) { + DEFINE_XLOAD_BASE(hlv_b) + DEFINE_XLOAD_BASE(hlv_bu) + DEFINE_XLOAD_BASE(hlv_h) + DEFINE_XLOAD_BASE(hlv_hu) + DEFINE_XLOAD_BASE(hlv_w) + DEFINE_XLOAD_BASE(hlv_wu) + DEFINE_XLOAD_BASE(hlv_d) + + DEFINE_XLOAD_BASE(hlvx_hu) + DEFINE_XLOAD_BASE(hlvx_wu) + + DEFINE_XSTORE_BASE(hsv_b) + DEFINE_XSTORE_BASE(hsv_h) + DEFINE_XSTORE_BASE(hsv_w) + DEFINE_XSTORE_BASE(hsv_d) + + DEFINE_SFENCE_TYPE(hfence_gvma); + DEFINE_SFENCE_TYPE(hfence_vvma); + } + + // ext-c + if (isa->extension_enabled(EXT_ZCA)) { + DISASM_INSN("c.ebreak", c_add, mask_rd | mask_rvc_rs2, {}); + add_insn(new disasm_insn_t("ret", match_c_jr | match_rd_ra, mask_c_jr | mask_rd | mask_rvc_imm, {})); + DISASM_INSN("c.jr", c_jr, mask_rvc_imm, {&rvc_rs1}); + DISASM_INSN("c.jalr", c_jalr, mask_rvc_imm, {&rvc_rs1}); + DISASM_INSN("c.nop", c_addi, mask_rd | mask_rvc_imm, {}); + DISASM_INSN("c.addi16sp", c_addi16sp, mask_rd, {&rvc_sp, &rvc_addi16sp_imm}); + DISASM_INSN("c.addi4spn", c_addi4spn, 0, {&rvc_rs2s, &rvc_sp, &rvc_addi4spn_imm}); + DISASM_INSN("c.li", c_li, 0, {&xrd, &rvc_imm}); + DISASM_INSN("c.lui", c_lui, 0, {&xrd, &rvc_uimm}); + DISASM_INSN("c.addi", c_addi, 0, {&xrd, &rvc_imm}); + DISASM_INSN("c.slli", c_slli, 0, {&rvc_rs1, &rvc_shamt}); + DISASM_INSN("c.srli", c_srli, 0, {&rvc_rs1s, &rvc_shamt}); + DISASM_INSN("c.srai", c_srai, 0, {&rvc_rs1s, &rvc_shamt}); + DISASM_INSN("c.andi", c_andi, 0, {&rvc_rs1s, &rvc_imm}); + DISASM_INSN("c.mv", c_mv, 0, {&xrd, &rvc_rs2}); + DISASM_INSN("c.add", c_add, 0, {&xrd, &rvc_rs2}); + DISASM_INSN("c.addw", c_addw, 0, {&rvc_rs1s, &rvc_rs2s}); + DISASM_INSN("c.sub", c_sub, 0, {&rvc_rs1s, &rvc_rs2s}); + DISASM_INSN("c.subw", c_subw, 0, {&rvc_rs1s, &rvc_rs2s}); + DISASM_INSN("c.and", c_and, 0, {&rvc_rs1s, &rvc_rs2s}); + DISASM_INSN("c.or", c_or, 0, {&rvc_rs1s, &rvc_rs2s}); + DISASM_INSN("c.xor", c_xor, 0, {&rvc_rs1s, &rvc_rs2s}); + DISASM_INSN("c.lwsp", c_lwsp, 0, {&xrd, &rvc_lwsp_address}); + DISASM_INSN("c.swsp", c_swsp, 0, {&rvc_rs2, &rvc_swsp_address}); + DISASM_INSN("c.lw", c_lw, 0, {&rvc_rs2s, &rvc_lw_address}); + DISASM_INSN("c.sw", c_sw, 0, {&rvc_rs2s, &rvc_lw_address}); + DISASM_INSN("c.beqz", c_beqz, 0, {&rvc_rs1s, &rvc_branch_target}); + DISASM_INSN("c.bnez", c_bnez, 0, {&rvc_rs1s, &rvc_branch_target}); + DISASM_INSN("c.j", c_j, 0, {&rvc_jump_target}); + if (isa->get_max_xlen() == 32) { + DISASM_INSN("c.jal", c_jal, 0, {&rvc_jump_target}); + } else { + DISASM_INSN("c.ld", c_ld, 0, {&rvc_rs2s, &rvc_ld_address}); + DISASM_INSN("c.ldsp", c_ldsp, 0, {&xrd, &rvc_ldsp_address}); + DISASM_INSN("c.sd", c_sd, 0, {&rvc_rs2s, &rvc_ld_address}); + DISASM_INSN("c.sdsp", c_sdsp, 0, {&rvc_rs2, &rvc_sdsp_address}); + DISASM_INSN("c.addiw", c_addiw, 0, {&xrd, &rvc_imm}); + } + } + + if (isa->extension_enabled(EXT_ZCD) && isa->extension_enabled('D')) { + DISASM_INSN("c.fld", c_fld, 0, {&rvc_fp_rs2s, &rvc_ld_address}); + DISASM_INSN("c.fldsp", c_fldsp, 0, {&frd, &rvc_ldsp_address}); + DISASM_INSN("c.fsd", c_fsd, 0, {&rvc_fp_rs2s, &rvc_ld_address}); + DISASM_INSN("c.fsdsp", c_fsdsp, 0, {&rvc_fp_rs2, &rvc_sdsp_address}); + } + + if (isa->extension_enabled(EXT_ZCF) && isa->extension_enabled('F')) { + DISASM_INSN("c.flw", c_flw, 0, {&rvc_fp_rs2s, &rvc_lw_address}); + DISASM_INSN("c.flwsp", c_flwsp, 0, {&frd, &rvc_lwsp_address}); + DISASM_INSN("c.fsw", c_fsw, 0, {&rvc_fp_rs2s, &rvc_lw_address}); + DISASM_INSN("c.fswsp", c_fswsp, 0, {&rvc_fp_rs2, &rvc_swsp_address}); + } + + if (isa->extension_enabled(EXT_ZCB)) { + DISASM_INSN("c.zext.b", c_zext_b, 0, {&rvc_rs1s}); + DISASM_INSN("c.sext.b", c_sext_b, 0, {&rvc_rs1s}); + DISASM_INSN("c.zext.h", c_zext_h, 0, {&rvc_rs1s}); + DISASM_INSN("c.sext.h", c_sext_h, 0, {&rvc_rs1s}); + if (isa->get_max_xlen() == 64) { + DISASM_INSN("c.zext.w", c_zext_w, 0, {&rvc_rs1s}); + } + DISASM_INSN("c.not", c_not, 0, {&rvc_rs1s}); + DISASM_INSN("c.mul", c_mul, 0, {&rvc_rs1s, &rvc_rs2s}); + DISASM_INSN("c.lbu", c_lbu, 0, {&rvc_rs2s, &rvb_b_address}); + DISASM_INSN("c.lhu", c_lhu, 0, {&rvc_rs2s, &rvb_h_address}); + DISASM_INSN("c.lh", c_lh, 0, {&rvc_rs2s, &rvb_h_address}); + DISASM_INSN("c.sb", c_sb, 0, {&rvc_rs2s, &rvb_b_address}); + DISASM_INSN("c.sh", c_sh, 0, {&rvc_rs2s, &rvb_h_address}); + } + + if (isa->extension_enabled(EXT_ZCMP)) { + if (isa->get_max_xlen() == 32) { + DISASM_INSN("cm.push", cm_push, 0, {&rvcm_pushpop_rlist, &rvcm_push_stack_adj_32}); + DISASM_INSN("cm.pop", cm_pop, 0, {&rvcm_pushpop_rlist, &rvcm_pop_stack_adj_32}); + DISASM_INSN("cm.popret", cm_popret, 0, {&rvcm_pushpop_rlist, &rvcm_pop_stack_adj_32}); + DISASM_INSN("cm.popretz", cm_popretz, 0, {&rvcm_pushpop_rlist, &rvcm_pop_stack_adj_32}); + } else { + DISASM_INSN("cm.push", cm_push, 0, {&rvcm_pushpop_rlist, &rvcm_push_stack_adj_64}); + DISASM_INSN("cm.pop", cm_pop, 0, {&rvcm_pushpop_rlist, &rvcm_pop_stack_adj_64}); + DISASM_INSN("cm.popret", cm_popret, 0, {&rvcm_pushpop_rlist, &rvcm_pop_stack_adj_64}); + DISASM_INSN("cm.popretz", cm_popretz, 0, {&rvcm_pushpop_rlist, &rvcm_pop_stack_adj_64}); + } + + DISASM_INSN("cm.mva01s", cm_mva01s, 0, {&rvc_rs1s, &rvc_rs2s}); + DISASM_INSN("cm.mvsa01", cm_mvsa01, 0, {&rvc_rs1s, &rvc_rs2s}); + } + + if (isa->extension_enabled(EXT_ZCMT)) { + DISASM_INSN("cm.jt", cm_jalt, 0x380, {&rvcm_jt_index}); + DISASM_INSN("cm.jalt", cm_jalt, 0, {&rvcm_jt_index}); + } + + if (isa->extension_enabled('V')) { + DISASM_INSN("vsetivli", vsetivli, 0, {&xrd, &zimm5, &v_vtype}); + DISASM_INSN("vsetvli", vsetvli, 0, {&xrd, &xrs1, &v_vtype}); + DEFINE_RTYPE(vsetvl); + + std::vector<const arg_t *> v_ld_unit = {&vd, &v_address, opt, &vm}; + std::vector<const arg_t *> v_st_unit = {&vs3, &v_address, opt, &vm}; + std::vector<const arg_t *> v_ld_stride = {&vd, &v_address, &xrs2, opt, &vm}; + std::vector<const arg_t *> v_st_stride = {&vs3, &v_address, &xrs2, opt, &vm}; + std::vector<const arg_t *> v_ld_index = {&vd, &v_address, &vs2, opt, &vm}; + std::vector<const arg_t *> v_st_index = {&vs3, &v_address, &vs2, opt, &vm}; + + add_insn(new disasm_insn_t("vlm.v", match_vlm_v, mask_vlm_v, v_ld_unit)); + add_insn(new disasm_insn_t("vsm.v", match_vsm_v, mask_vsm_v, v_st_unit)); + + // handle vector segment load/store + for (size_t elt = 0; elt <= 7; ++elt) { + const custom_fmt_t template_insn[] = { + {match_vle8_v, mask_vle8_v, "vl%se%d.v", v_ld_unit}, + {match_vse8_v, mask_vse8_v, "vs%se%d.v", v_st_unit}, + + {match_vluxei8_v, mask_vluxei8_v, "vlux%sei%d.v", v_ld_index}, + {match_vsuxei8_v, mask_vsuxei8_v, "vsux%sei%d.v", v_st_index}, + + {match_vlse8_v, mask_vlse8_v, "vls%se%d.v", v_ld_stride}, + {match_vsse8_v, mask_vsse8_v, "vss%se%d.v", v_st_stride}, + + {match_vloxei8_v, mask_vloxei8_v, "vlox%sei%d.v", v_ld_index}, + {match_vsoxei8_v, mask_vsoxei8_v, "vsox%sei%d.v", v_st_index}, + + {match_vle8ff_v, mask_vle8ff_v, "vl%se%dff.v", v_ld_unit} + }; + + reg_t elt_map[] = {0x00000000, 0x00005000, 0x00006000, 0x00007000, + 0x10000000, 0x10005000, 0x10006000, 0x10007000}; + + for (unsigned nf = 0; nf <= 7; ++nf) { + const auto seg_str = nf ? "seg" + std::to_string(nf + 1) : ""; + + for (auto item : template_insn) { + const reg_t match_nf = nf << 29; + char buf[128]; + snprintf(buf, sizeof(buf), item.fmt, seg_str.c_str(), 8 << elt); + add_insn(new disasm_insn_t( + buf, + ((item.match | match_nf) & ~mask_vldst) | elt_map[elt], + item.mask | mask_nf, + item.arg + )); + } + } + + const custom_fmt_t template_insn2[] = { + {match_vl1re8_v, mask_vl1re8_v, "vl%dre%d.v", v_ld_unit}, + }; + + for (reg_t i = 0, nf = 7; i < 4; i++, nf >>= 1) { + for (auto item : template_insn2) { + const reg_t match_nf = nf << 29; + char buf[128]; + snprintf(buf, sizeof(buf), item.fmt, nf + 1, 8 << elt); + add_insn(new disasm_insn_t( + buf, + item.match | match_nf | elt_map[elt], + item.mask | mask_nf, + item.arg + )); + } + } + } + + #define DISASM_ST_WHOLE_INSN(name, nf) \ + add_insn(new disasm_insn_t(#name, match_vs1r_v | (nf << 29), \ + mask_vs1r_v | mask_nf, \ + {&vs3, &v_address})); + DISASM_ST_WHOLE_INSN(vs1r.v, 0); + DISASM_ST_WHOLE_INSN(vs2r.v, 1); + DISASM_ST_WHOLE_INSN(vs4r.v, 3); + DISASM_ST_WHOLE_INSN(vs8r.v, 7); + + #undef DISASM_ST_WHOLE_INSN + + #define DEFINE_VECTOR_V(code) add_vector_v_insn(this, #code, match_##code, mask_##code) + #define DEFINE_VECTOR_VV(code) add_vector_vv_insn(this, #code, match_##code, mask_##code) + #define DEFINE_VECTOR_VX(code) add_vector_vx_insn(this, #code, match_##code, mask_##code) + #define DEFINE_VECTOR_VF(code) add_vector_vf_insn(this, #code, match_##code, mask_##code) + #define DEFINE_VECTOR_VI(code) add_vector_vi_insn(this, #code, match_##code, mask_##code) + #define DEFINE_VECTOR_VIU(code) add_vector_viu_insn(this, #code, match_##code, mask_##code) + + #define DISASM_OPIV_VXI_INSN(name, sign, suf) \ + DEFINE_VECTOR_VV(name##_##suf##v); \ + DEFINE_VECTOR_VX(name##_##suf##x); \ + if (sign) \ + DEFINE_VECTOR_VI(name##_##suf##i); \ + else \ + DEFINE_VECTOR_VIU(name##_##suf##i) + + #define DISASM_OPIV_VX__INSN(name, sign) \ + DEFINE_VECTOR_VV(name##_vv); \ + DEFINE_VECTOR_VX(name##_vx) + + #define DISASM_OPIV__XI_INSN(name, sign) \ + DEFINE_VECTOR_VX(name##_vx); \ + if (sign) \ + DEFINE_VECTOR_VI(name##_vi); \ + else \ + DEFINE_VECTOR_VIU(name##_vi) + + #define DISASM_OPIV_V___INSN(name, sign) DEFINE_VECTOR_VV(name##_vv) + + #define DISASM_OPIV_S___INSN(name, sign) DEFINE_VECTOR_VV(name##_vs) + + #define DISASM_OPIV_W___INSN(name, sign) \ + DEFINE_VECTOR_VV(name##_wv); \ + DEFINE_VECTOR_VX(name##_wx) + + #define DISASM_OPIV_M___INSN(name, sign) DEFINE_VECTOR_VV(name##_mm) + + #define DISASM_OPIV__X__INSN(name, sign) DEFINE_VECTOR_VX(name##_vx) + + #define DEFINE_VECTOR_VVM(name) \ + add_vector_vvm_insn(this, #name, match_##name, mask_##name | mask_vm) + + #define DEFINE_VECTOR_VXM(name) \ + add_vector_vxm_insn(this, #name, match_##name, mask_##name | mask_vm) + + #define DEFINE_VECTOR_VIM(name) \ + add_vector_vim_insn(this, #name, match_##name, mask_##name | mask_vm) + + #define DISASM_OPIV_VXIM_INSN(name) \ + DEFINE_VECTOR_VVM(name##_vvm); \ + DEFINE_VECTOR_VXM(name##_vxm); \ + DEFINE_VECTOR_VIM(name##_vim) + + #define DISASM_OPIV_VX_M_INSN(name) \ + DEFINE_VECTOR_VVM(name##_vvm); \ + DEFINE_VECTOR_VXM(name##_vxm) + + //OPFVV/OPFVF + //0b00_0000 + DISASM_OPIV_VXI_INSN(vadd, 1, v); + DISASM_OPIV_VX__INSN(vsub, 1); + DISASM_OPIV__XI_INSN(vrsub, 1); + DISASM_OPIV_VX__INSN(vminu, 0); + DISASM_OPIV_VX__INSN(vmin, 1); + DISASM_OPIV_VX__INSN(vmaxu, 1); + DISASM_OPIV_VX__INSN(vmax, 0); + DISASM_OPIV_VXI_INSN(vand, 1, v); + DISASM_OPIV_VXI_INSN(vor, 1, v); + DISASM_OPIV_VXI_INSN(vxor, 1, v); + DISASM_OPIV_VXI_INSN(vrgather, 0, v); + DISASM_OPIV_V___INSN(vrgatherei16, 0); + DISASM_OPIV__XI_INSN(vslideup, 0); + DISASM_OPIV__XI_INSN(vslidedown, 0); + + //0b01_0000 + DISASM_OPIV_VXIM_INSN(vadc); + DISASM_OPIV_VX_M_INSN(vsbc); + DISASM_OPIV_VXIM_INSN(vmadc); + DISASM_OPIV_VXI_INSN(vmadc, 1, v); + DISASM_OPIV_VX_M_INSN(vmsbc); + DISASM_OPIV_VX__INSN(vmsbc, 1); + DISASM_OPIV_VXIM_INSN(vmerge); + DISASM_INSN("vmv.v.i", vmv_v_i, 0, {&vd, &v_simm5}); + DISASM_INSN("vmv.v.v", vmv_v_v, 0, {&vd, &vs1}); + DISASM_INSN("vmv.v.x", vmv_v_x, 0, {&vd, &xrs1}); + DISASM_OPIV_VXI_INSN(vmseq, 1, v); + DISASM_OPIV_VXI_INSN(vmsne, 1, v); + DISASM_OPIV_VX__INSN(vmsltu, 0); + DISASM_OPIV_VX__INSN(vmslt, 1); + DISASM_OPIV_VXI_INSN(vmsleu, 0, v); + DISASM_OPIV_VXI_INSN(vmsle, 1, v); + DISASM_OPIV__XI_INSN(vmsgtu, 0); + DISASM_OPIV__XI_INSN(vmsgt, 1); + + //0b10_0000 + DISASM_OPIV_VXI_INSN(vsaddu, 0, v); + DISASM_OPIV_VXI_INSN(vsadd, 1, v); + DISASM_OPIV_VX__INSN(vssubu, 0); + DISASM_OPIV_VX__INSN(vssub, 1); + DISASM_OPIV_VXI_INSN(vsll, 1, v); + DISASM_INSN("vmv1r.v", vmv1r_v, 0, {&vd, &vs2}); + DISASM_INSN("vmv2r.v", vmv2r_v, 0, {&vd, &vs2}); + DISASM_INSN("vmv4r.v", vmv4r_v, 0, {&vd, &vs2}); + DISASM_INSN("vmv8r.v", vmv8r_v, 0, {&vd, &vs2}); + DISASM_OPIV_VX__INSN(vsmul, 1); + DISASM_OPIV_VXI_INSN(vsrl, 0, v); + DISASM_OPIV_VXI_INSN(vsra, 0, v); + DISASM_OPIV_VXI_INSN(vssrl, 0, v); + DISASM_OPIV_VXI_INSN(vssra, 0, v); + DISASM_OPIV_VXI_INSN(vnsrl, 0, w); + DISASM_OPIV_VXI_INSN(vnsra, 0, w); + DISASM_OPIV_VXI_INSN(vnclipu, 0, w); + DISASM_OPIV_VXI_INSN(vnclip, 0, w); + + //0b11_0000 + DISASM_OPIV_S___INSN(vwredsumu, 0); + DISASM_OPIV_S___INSN(vwredsum, 1); + + //OPMVV/OPMVX + //0b00_0000 + DISASM_OPIV_VX__INSN(vaaddu, 0); + DISASM_OPIV_VX__INSN(vaadd, 0); + DISASM_OPIV_VX__INSN(vasubu, 0); + DISASM_OPIV_VX__INSN(vasub, 0); + + DISASM_OPIV_S___INSN(vredsum, 1); + DISASM_OPIV_S___INSN(vredand, 1); + DISASM_OPIV_S___INSN(vredor, 1); + DISASM_OPIV_S___INSN(vredxor, 1); + DISASM_OPIV_S___INSN(vredminu, 0); + DISASM_OPIV_S___INSN(vredmin, 1); + DISASM_OPIV_S___INSN(vredmaxu, 0); + DISASM_OPIV_S___INSN(vredmax, 1); + DISASM_OPIV__X__INSN(vslide1up, 1); + DISASM_OPIV__X__INSN(vslide1down,1); + + //0b01_0000 + //VWXUNARY0 + DISASM_INSN("vmv.x.s", vmv_x_s, 0, {&xrd, &vs2}); + DISASM_INSN("vcpop.m", vcpop_m, 0, {&xrd, &vs2, opt, &vm}); + DISASM_INSN("vfirst.m", vfirst_m, 0, {&xrd, &vs2, opt, &vm}); + + //VRXUNARY0 + DISASM_INSN("vmv.s.x", vmv_s_x, 0, {&vd, &xrs1}); + + //VXUNARY0 + DEFINE_VECTOR_V(vzext_vf2); + DEFINE_VECTOR_V(vsext_vf2); + DEFINE_VECTOR_V(vzext_vf4); + DEFINE_VECTOR_V(vsext_vf4); + DEFINE_VECTOR_V(vzext_vf8); + DEFINE_VECTOR_V(vsext_vf8); + + //VMUNARY0 + DEFINE_VECTOR_V(vmsbf_m); + DEFINE_VECTOR_V(vmsof_m); + DEFINE_VECTOR_V(vmsif_m); + DEFINE_VECTOR_V(viota_m); + DISASM_INSN("vid.v", vid_v, 0, {&vd, opt, &vm}); + + DISASM_INSN("vid.v", vid_v, 0, {&vd, opt, &vm}); + + DISASM_INSN("vcompress.vm", vcompress_vm, 0, {&vd, &vs2, &vs1}); + + DISASM_OPIV_M___INSN(vmandn, 1); + DISASM_OPIV_M___INSN(vmand, 1); + DISASM_OPIV_M___INSN(vmor, 1); + DISASM_OPIV_M___INSN(vmxor, 1); + DISASM_OPIV_M___INSN(vmorn, 1); + DISASM_OPIV_M___INSN(vmnand, 1); + DISASM_OPIV_M___INSN(vmnor, 1); + DISASM_OPIV_M___INSN(vmxnor, 1); + + //0b10_0000 + DISASM_OPIV_VX__INSN(vdivu, 0); + DISASM_OPIV_VX__INSN(vdiv, 1); + DISASM_OPIV_VX__INSN(vremu, 0); + DISASM_OPIV_VX__INSN(vrem, 1); + DISASM_OPIV_VX__INSN(vmulhu, 0); + DISASM_OPIV_VX__INSN(vmul, 1); + DISASM_OPIV_VX__INSN(vmulhsu, 0); + DISASM_OPIV_VX__INSN(vmulh, 1); + DISASM_OPIV_VX__INSN(vmadd, 1); + DISASM_OPIV_VX__INSN(vnmsub, 1); + DISASM_OPIV_VX__INSN(vmacc, 1); + DISASM_OPIV_VX__INSN(vnmsac, 1); + + //0b11_0000 + DISASM_OPIV_VX__INSN(vwaddu, 0); + DISASM_OPIV_VX__INSN(vwadd, 1); + DISASM_OPIV_VX__INSN(vwsubu, 0); + DISASM_OPIV_VX__INSN(vwsub, 1); + DISASM_OPIV_W___INSN(vwaddu, 0); + DISASM_OPIV_W___INSN(vwadd, 1); + DISASM_OPIV_W___INSN(vwsubu, 0); + DISASM_OPIV_W___INSN(vwsub, 1); + DISASM_OPIV_VX__INSN(vwmulu, 0); + DISASM_OPIV_VX__INSN(vwmulsu, 0); + DISASM_OPIV_VX__INSN(vwmul, 1); + DISASM_OPIV_VX__INSN(vwmaccu, 0); + DISASM_OPIV_VX__INSN(vwmacc, 1); + DISASM_OPIV__X__INSN(vwmaccus, 1); + DISASM_OPIV_VX__INSN(vwmaccsu, 0); + + #undef DISASM_OPIV_VXI_INSN + #undef DISASM_OPIV_VX__INSN + #undef DISASM_OPIV__XI_INSN + #undef DISASM_OPIV_V___INSN + #undef DISASM_OPIV_S___INSN + #undef DISASM_OPIV_W___INSN + #undef DISASM_OPIV_M___INSN + #undef DISASM_OPIV__X__INSN + #undef DISASM_OPIV_VXIM_INSN + #undef DISASM_OPIV_VX_M_INSN + + #define DISASM_OPIV_VF_INSN(name) \ + DEFINE_VECTOR_VV(name##_vv); \ + DEFINE_VECTOR_VF(name##_vf) + + #define DISASM_OPIV_WF_INSN(name) \ + DEFINE_VECTOR_VV(name##_wv); \ + DEFINE_VECTOR_VF(name##_wf) + + #define DISASM_OPIV_S__INSN(name) \ + DEFINE_VECTOR_VV(name##_vs) + + #define DISASM_OPIV__F_INSN(name) \ + DEFINE_VECTOR_VF(name##_vf) + + #define DISASM_VFUNARY0_INSN(name, suf) \ + DEFINE_VECTOR_V(name##cvt_rtz_xu_f_##suf); \ + DEFINE_VECTOR_V(name##cvt_rtz_x_f_##suf); \ + DEFINE_VECTOR_V(name##cvt_xu_f_##suf); \ + DEFINE_VECTOR_V(name##cvt_x_f_##suf); \ + DEFINE_VECTOR_V(name##cvt_f_xu_##suf); \ + DEFINE_VECTOR_V(name##cvt_f_x_##suf) + + //OPFVV/OPFVF + //0b00_0000 + DISASM_OPIV_VF_INSN(vfadd); + DISASM_OPIV_S__INSN(vfredusum); + DISASM_OPIV_VF_INSN(vfsub); + DISASM_OPIV_S__INSN(vfredosum); + DISASM_OPIV_VF_INSN(vfmin); + DISASM_OPIV_S__INSN(vfredmin); + DISASM_OPIV_VF_INSN(vfmax); + DISASM_OPIV_S__INSN(vfredmax); + DISASM_OPIV_VF_INSN(vfsgnj); + DISASM_OPIV_VF_INSN(vfsgnjn); + DISASM_OPIV_VF_INSN(vfsgnjx); + DISASM_INSN("vfmv.f.s", vfmv_f_s, 0, {&frd, &vs2}); + DISASM_INSN("vfmv.s.f", vfmv_s_f, mask_vfmv_s_f, {&vd, &frs1}); + DISASM_OPIV__F_INSN(vfslide1up); + DISASM_OPIV__F_INSN(vfslide1down); + + //0b01_0000 + DISASM_INSN("vfmerge.vfm", vfmerge_vfm, 0, {&vd, &vs2, &frs1, &v0}); + DISASM_INSN("vfmv.v.f", vfmv_v_f, 0, {&vd, &frs1}); + DISASM_OPIV_VF_INSN(vmfeq); + DISASM_OPIV_VF_INSN(vmfle); + DISASM_OPIV_VF_INSN(vmflt); + DISASM_OPIV_VF_INSN(vmfne); + DISASM_OPIV__F_INSN(vmfgt); + DISASM_OPIV__F_INSN(vmfge); + + //0b10_0000 + DISASM_OPIV_VF_INSN(vfdiv); + DISASM_OPIV__F_INSN(vfrdiv); + + //vfunary0 + DISASM_VFUNARY0_INSN(vf, v); + DISASM_VFUNARY0_INSN(vfw, v); + DEFINE_VECTOR_V(vfwcvt_f_f_v); + + DISASM_VFUNARY0_INSN(vfn, w); + DEFINE_VECTOR_V(vfncvt_f_f_w); + DEFINE_VECTOR_V(vfncvt_rod_f_f_w); + + //vfunary1 + DEFINE_VECTOR_V(vfsqrt_v); + DEFINE_VECTOR_V(vfrsqrt7_v); + DEFINE_VECTOR_V(vfrec7_v); + DEFINE_VECTOR_V(vfclass_v); + + DISASM_OPIV_VF_INSN(vfmul); + DISASM_OPIV__F_INSN(vfrsub); + DISASM_OPIV_VF_INSN(vfmadd); + DISASM_OPIV_VF_INSN(vfnmadd); + DISASM_OPIV_VF_INSN(vfmsub); + DISASM_OPIV_VF_INSN(vfnmsub); + DISASM_OPIV_VF_INSN(vfmacc); + DISASM_OPIV_VF_INSN(vfnmacc); + DISASM_OPIV_VF_INSN(vfmsac); + DISASM_OPIV_VF_INSN(vfnmsac); + + //0b11_0000 + DISASM_OPIV_VF_INSN(vfwadd); + DISASM_OPIV_S__INSN(vfwredusum); + DISASM_OPIV_VF_INSN(vfwsub); + DISASM_OPIV_S__INSN(vfwredosum); + DISASM_OPIV_WF_INSN(vfwadd); + DISASM_OPIV_WF_INSN(vfwsub); + DISASM_OPIV_VF_INSN(vfwmul); + DISASM_OPIV_VF_INSN(vfwmacc); + DISASM_OPIV_VF_INSN(vfwnmacc); + DISASM_OPIV_VF_INSN(vfwmsac); + DISASM_OPIV_VF_INSN(vfwnmsac); + + #undef DISASM_OPIV_VF_INSN + #undef DISASM_OPIV__F_INSN + #undef DISASM_OPIV_S__INSN + #undef DISASM_OPIV_W__INSN + #undef DISASM_VFUNARY0_INSN + + // vector amo + std::vector<const arg_t *> v_fmt_amo_wd = {&vd, &v_address, &vs2, &vd, opt, &vm}; + std::vector<const arg_t *> v_fmt_amo = {&x0, &v_address, &vs2, &vd, opt, &vm}; + for (size_t elt = 0; elt <= 3; ++elt) { + const custom_fmt_t template_insn[] = { + {match_vamoaddei8_v | mask_wd, mask_vamoaddei8_v | mask_wd, + "%sei%d.v", v_fmt_amo_wd}, + {match_vamoaddei8_v, mask_vamoaddei8_v | mask_wd, + "%sei%d.v", v_fmt_amo}, + }; + std::pair<const char*, reg_t> amo_map[] = { + {"vamoswap", 0x01ul << 27}, + {"vamoadd", 0x00ul << 27}, + {"vamoxor", 0x04ul << 27}, + {"vamoand", 0x0cul << 27}, + {"vamoor", 0x08ul << 27}, + {"vamomin", 0x10ul << 27}, + {"vamomax", 0x14ul << 27}, + {"vamominu", 0x18ul << 27}, + {"vamomaxu", 0x1cul << 27}}; + const reg_t elt_map[] = {0x0ul << 12, 0x5ul << 12, + 0x6ul <<12, 0x7ul << 12}; + + for (size_t idx = 0; idx < sizeof(amo_map) / sizeof(amo_map[0]); ++idx) { + for (auto item : template_insn) { + char buf[128]; + snprintf(buf, sizeof(buf), item.fmt, amo_map[idx].first, 8 << elt); + add_insn(new disasm_insn_t(buf, + item.match | amo_map[idx].second | elt_map[elt], + item.mask, + item.arg)); + } + } + } + } + +#define DEFINE_PI3TYPE(code) add_pitype3_insn(this, #code, match_##code, mask_##code); +#define DEFINE_PI4TYPE(code) add_pitype4_insn(this, #code, match_##code, mask_##code); +#define DEFINE_PI5TYPE(code) add_pitype5_insn(this, #code, match_##code, mask_##code); +#define DEFINE_PI6TYPE(code) add_pitype6_insn(this, #code, match_##code, mask_##code); + +#define DISASM_8_AND_16_RINSN(code) \ + DEFINE_RTYPE(code##8); \ + DEFINE_RTYPE(code##16); + +#define DISASM_8_AND_16_RINSN_ROUND(code) \ + DEFINE_RTYPE(code##8_u); \ + DEFINE_RTYPE(code##16_u); + +#define DISASM_8_AND_16_PIINSN(code) \ + DEFINE_PI3TYPE(code##8); \ + DEFINE_PI4TYPE(code##16); + +#define DISASM_8_AND_16_PIINSN_ROUND(code) \ + DEFINE_PI3TYPE(code##8_u); \ + DEFINE_PI4TYPE(code##16_u); + +#define DISASM_RINSN_AND_ROUND(code) \ + DEFINE_RTYPE(code); \ + DEFINE_RTYPE(code##_u); \ + + if (isa->extension_enabled(EXT_ZMMUL)) { + DEFINE_RTYPE(mul); + DEFINE_RTYPE(mulh); + DEFINE_RTYPE(mulhu); + DEFINE_RTYPE(mulhsu); + DEFINE_RTYPE(mulw); + } + + if (isa->extension_enabled(EXT_ZBPBO)) { + DEFINE_RTYPE(min); + DEFINE_RTYPE(max); + DEFINE_R3TYPE(cmix); + DEFINE_RTYPE(pack); + DEFINE_RTYPE(packu); + add_insn(new disasm_insn_t("rev", match_grevi | ((isa->get_max_xlen() - 1) << imm_shift), mask_grevi | mask_imm, {&xrd, &xrs1})); + add_insn(new disasm_insn_t("rev8.h", match_grevi | (0x8 << imm_shift), mask_grevi | mask_imm, {&xrd, &xrs1})); // swap16 + if (isa->get_max_xlen() == 32) { + DEFINE_R1TYPE(clz); + DEFINE_R3TYPE(fsr); + DEFINE_R3TYPE(fsri); + } else { + DEFINE_R3TYPE(fsrw); + } + } + + if (isa->extension_enabled(EXT_ZPSFOPERAND)) { + DEFINE_RTYPE(smal) + DEFINE_RTYPE(radd64); + DEFINE_RTYPE(uradd64); + DEFINE_RTYPE(kadd64); + DEFINE_RTYPE(ukadd64); + DEFINE_RTYPE(rsub64); + DEFINE_RTYPE(ursub64); + DEFINE_RTYPE(ksub64); + DEFINE_RTYPE(uksub64); + DEFINE_RTYPE(smar64); + DEFINE_RTYPE(smsr64); + DEFINE_RTYPE(umar64); + DEFINE_RTYPE(umsr64); + DEFINE_RTYPE(kmar64); + DEFINE_RTYPE(kmsr64); + DEFINE_RTYPE(ukmar64); + DEFINE_RTYPE(ukmsr64); + DEFINE_RTYPE(smalbb); + DEFINE_RTYPE(smalbt); + DEFINE_RTYPE(smaltt); + DEFINE_RTYPE(smalda); + DEFINE_RTYPE(smalxda); + DEFINE_RTYPE(smalds); + DEFINE_RTYPE(smaldrs); + DEFINE_RTYPE(smalxds); + DEFINE_RTYPE(smslda); + DEFINE_RTYPE(smslxda); + DEFINE_RTYPE(mulr64); + DEFINE_RTYPE(mulsr64); + if (isa->get_max_xlen() == 32) { + DEFINE_RTYPE(add64); + DEFINE_RTYPE(sub64); + } + } + + if (isa->extension_enabled(EXT_ZPN)) { + DISASM_8_AND_16_RINSN(add); + DISASM_8_AND_16_RINSN(radd); + DISASM_8_AND_16_RINSN(uradd); + DISASM_8_AND_16_RINSN(kadd); + DISASM_8_AND_16_RINSN(ukadd); + DISASM_8_AND_16_RINSN(sub); + DISASM_8_AND_16_RINSN(rsub); + DISASM_8_AND_16_RINSN(ursub); + DISASM_8_AND_16_RINSN(ksub); + DISASM_8_AND_16_RINSN(uksub); + DEFINE_RTYPE(cras16); + DEFINE_RTYPE(rcras16); + DEFINE_RTYPE(urcras16); + DEFINE_RTYPE(kcras16); + DEFINE_RTYPE(ukcras16); + DEFINE_RTYPE(crsa16); + DEFINE_RTYPE(rcrsa16); + DEFINE_RTYPE(urcrsa16); + DEFINE_RTYPE(kcrsa16); + DEFINE_RTYPE(ukcrsa16); + DEFINE_RTYPE(stas16); + DEFINE_RTYPE(rstas16); + DEFINE_RTYPE(urstas16); + DEFINE_RTYPE(kstas16); + DEFINE_RTYPE(ukstas16); + DEFINE_RTYPE(stsa16); + DEFINE_RTYPE(rstsa16); + DEFINE_RTYPE(urstsa16); + DEFINE_RTYPE(kstsa16); + DEFINE_RTYPE(ukstsa16); + DISASM_8_AND_16_RINSN(sra); + DISASM_8_AND_16_RINSN(srl); + DISASM_8_AND_16_RINSN(sll); + DISASM_8_AND_16_RINSN(ksll); + DISASM_8_AND_16_RINSN(kslra); + DISASM_8_AND_16_PIINSN(srai); + DISASM_8_AND_16_PIINSN(srli); + DISASM_8_AND_16_PIINSN(slli); + DISASM_8_AND_16_PIINSN(kslli); + DISASM_8_AND_16_RINSN_ROUND(sra); + DISASM_8_AND_16_RINSN_ROUND(srl); + DISASM_8_AND_16_RINSN_ROUND(kslra); + DISASM_8_AND_16_PIINSN_ROUND(srai); + DISASM_8_AND_16_PIINSN_ROUND(srli); + + DISASM_8_AND_16_RINSN(cmpeq); + DISASM_8_AND_16_RINSN(scmplt); + DISASM_8_AND_16_RINSN(scmple); + DISASM_8_AND_16_RINSN(ucmplt); + DISASM_8_AND_16_RINSN(ucmple); + + DISASM_8_AND_16_RINSN(smul); + DISASM_8_AND_16_RINSN(smulx); + DISASM_8_AND_16_RINSN(umul); + DISASM_8_AND_16_RINSN(umulx); + DISASM_8_AND_16_RINSN(khm); + DISASM_8_AND_16_RINSN(khmx); + + DISASM_8_AND_16_RINSN(smin); + DISASM_8_AND_16_RINSN(umin); + DISASM_8_AND_16_RINSN(smax); + DISASM_8_AND_16_RINSN(umax); + DISASM_8_AND_16_PIINSN(sclip); + DISASM_8_AND_16_PIINSN(uclip); + DEFINE_R1TYPE(kabs16); + DEFINE_R1TYPE(clrs16); + DEFINE_R1TYPE(clz16); + DEFINE_R1TYPE(kabs8); + DEFINE_R1TYPE(clrs8); + DEFINE_R1TYPE(clz8); + + DEFINE_R1TYPE(sunpkd810); + DEFINE_R1TYPE(sunpkd820); + DEFINE_R1TYPE(sunpkd830); + DEFINE_R1TYPE(sunpkd831); + DEFINE_R1TYPE(sunpkd832); + DEFINE_R1TYPE(zunpkd810); + DEFINE_R1TYPE(zunpkd820); + DEFINE_R1TYPE(zunpkd830); + DEFINE_R1TYPE(zunpkd831); + DEFINE_R1TYPE(zunpkd832); + + DEFINE_RTYPE(pkbb16); + DEFINE_RTYPE(pkbt16); + DEFINE_RTYPE(pktb16); + DEFINE_RTYPE(pktt16); + DISASM_RINSN_AND_ROUND(smmul); + DISASM_RINSN_AND_ROUND(kmmac); + DISASM_RINSN_AND_ROUND(kmmsb); + DISASM_RINSN_AND_ROUND(kwmmul); + DISASM_RINSN_AND_ROUND(smmwb); + DISASM_RINSN_AND_ROUND(smmwt); + DISASM_RINSN_AND_ROUND(kmmawb); + DISASM_RINSN_AND_ROUND(kmmawt); + DISASM_RINSN_AND_ROUND(kmmwb2); + DISASM_RINSN_AND_ROUND(kmmwt2); + DISASM_RINSN_AND_ROUND(kmmawb2); + DISASM_RINSN_AND_ROUND(kmmawt2); + DEFINE_RTYPE(smbb16) + DEFINE_RTYPE(smbt16) + DEFINE_RTYPE(smtt16) + DEFINE_RTYPE(kmda) + DEFINE_RTYPE(kmxda) + DEFINE_RTYPE(smds) + DEFINE_RTYPE(smdrs) + DEFINE_RTYPE(smxds) + DEFINE_RTYPE(kmabb) + DEFINE_RTYPE(kmabt) + DEFINE_RTYPE(kmatt) + DEFINE_RTYPE(kmada) + DEFINE_RTYPE(kmaxda) + DEFINE_RTYPE(kmads) + DEFINE_RTYPE(kmadrs) + DEFINE_RTYPE(kmaxds) + DEFINE_RTYPE(kmsda) + DEFINE_RTYPE(kmsxda) + DEFINE_RTYPE(sclip32) + DEFINE_RTYPE(uclip32) + DEFINE_R1TYPE(clrs32); + DEFINE_R1TYPE(clz32); + DEFINE_RTYPE(pbsad); + DEFINE_RTYPE(pbsada); + DEFINE_RTYPE(smaqa); + DEFINE_RTYPE(umaqa); + DEFINE_RTYPE(smaqa_su); + + DEFINE_RTYPE(kaddh); + DEFINE_RTYPE(ksubh); + DEFINE_RTYPE(khmbb); + DEFINE_RTYPE(khmbt); + DEFINE_RTYPE(khmtt); + DEFINE_RTYPE(ukaddh); + DEFINE_RTYPE(uksubh); + DEFINE_RTYPE(kaddw); + DEFINE_RTYPE(ukaddw); + DEFINE_RTYPE(ksubw); + DEFINE_RTYPE(uksubw); + DEFINE_RTYPE(kdmbb); + DEFINE_RTYPE(kdmbt); + DEFINE_RTYPE(kdmtt); + DEFINE_RTYPE(kslraw); + DEFINE_RTYPE(kslraw_u); + DEFINE_RTYPE(ksllw); + DEFINE_PI5TYPE(kslliw); + DEFINE_RTYPE(kdmabb); + DEFINE_RTYPE(kdmabt); + DEFINE_RTYPE(kdmatt); + DEFINE_RTYPE(kabsw); + DEFINE_RTYPE(raddw); + DEFINE_RTYPE(uraddw); + DEFINE_RTYPE(rsubw); + DEFINE_RTYPE(ursubw); + DEFINE_RTYPE(msubr32); + DEFINE_RTYPE(ave); + DEFINE_RTYPE(sra_u); + DEFINE_PI6TYPE(srai_u); + DEFINE_PI3TYPE(insb); + DEFINE_RTYPE(maddr32) + + if (isa->get_max_xlen() == 64) { + DEFINE_RTYPE(add32); + DEFINE_RTYPE(radd32); + DEFINE_RTYPE(uradd32); + DEFINE_RTYPE(kadd32); + DEFINE_RTYPE(ukadd32); + DEFINE_RTYPE(sub32); + DEFINE_RTYPE(rsub32); + DEFINE_RTYPE(ursub32); + DEFINE_RTYPE(ksub32); + DEFINE_RTYPE(uksub32); + DEFINE_RTYPE(cras32); + DEFINE_RTYPE(rcras32); + DEFINE_RTYPE(urcras32); + DEFINE_RTYPE(kcras32); + DEFINE_RTYPE(ukcras32); + DEFINE_RTYPE(crsa32); + DEFINE_RTYPE(rcrsa32); + DEFINE_RTYPE(urcrsa32); + DEFINE_RTYPE(kcrsa32); + DEFINE_RTYPE(ukcrsa32); + DEFINE_RTYPE(stas32); + DEFINE_RTYPE(rstas32); + DEFINE_RTYPE(urstas32); + DEFINE_RTYPE(kstas32); + DEFINE_RTYPE(ukstas32); + DEFINE_RTYPE(stsa32); + DEFINE_RTYPE(rstsa32); + DEFINE_RTYPE(urstsa32); + DEFINE_RTYPE(kstsa32); + DEFINE_RTYPE(ukstsa32); + DEFINE_RTYPE(sra32); + DEFINE_PI5TYPE(srai32); + DEFINE_RTYPE(sra32_u); + DEFINE_PI5TYPE(srai32_u); + DEFINE_RTYPE(srl32); + DEFINE_PI5TYPE(srli32); + DEFINE_RTYPE(srl32_u); + DEFINE_PI5TYPE(srli32_u); + DEFINE_RTYPE(sll32); + DEFINE_PI5TYPE(slli32); + DEFINE_RTYPE(ksll32); + DEFINE_PI5TYPE(kslli32); + DEFINE_RTYPE(kslra32); + DEFINE_RTYPE(kslra32_u); + DEFINE_RTYPE(smin32); + DEFINE_RTYPE(umin32); + DEFINE_RTYPE(smax32); + DEFINE_RTYPE(umax32); + DEFINE_R1TYPE(kabs32); + DEFINE_RTYPE(khmbb16); + DEFINE_RTYPE(khmbt16); + DEFINE_RTYPE(khmtt16); + DEFINE_RTYPE(kdmbb16); + DEFINE_RTYPE(kdmbt16); + DEFINE_RTYPE(kdmtt16); + DEFINE_RTYPE(kdmabb16); + DEFINE_RTYPE(kdmabt16); + DEFINE_RTYPE(kdmatt16); + DEFINE_RTYPE(smbt32); + DEFINE_RTYPE(smtt32); + DEFINE_RTYPE(kmabb32); + DEFINE_RTYPE(kmabt32); + DEFINE_RTYPE(kmatt32); + DEFINE_RTYPE(kmda32); + DEFINE_RTYPE(kmxda32); + DEFINE_RTYPE(kmaxda32); + DEFINE_RTYPE(kmads32); + DEFINE_RTYPE(kmadrs32); + DEFINE_RTYPE(kmaxds32); + DEFINE_RTYPE(kmsda32); + DEFINE_RTYPE(kmsxda32); + DEFINE_RTYPE(smds32); + DEFINE_RTYPE(smdrs32); + DEFINE_RTYPE(smxds32); + DEFINE_PI5TYPE(sraiw_u); + DEFINE_RTYPE(pkbt32); + DEFINE_RTYPE(pktb32); + } + } + + if (isa->extension_enabled(EXT_XZBP)) { + DEFINE_ITYPE_SHIFT(grevi); + DEFINE_ITYPE_SHIFT(gorci); + DEFINE_RTYPE(pack); + DEFINE_RTYPE(packh); + DEFINE_RTYPE(packu); + DEFINE_RTYPE(grev); + DEFINE_RTYPE(gorc); + DEFINE_RTYPE(xperm4); + DEFINE_RTYPE(xperm8); + DEFINE_RTYPE(xperm16); + DEFINE_RTYPE(xperm32); + } + + if (isa->extension_enabled(EXT_XZBP) || + isa->extension_enabled(EXT_XZBE) || + isa->extension_enabled(EXT_XZBF)) { + if(isa->get_max_xlen() == 64) { + DEFINE_RTYPE(packw); + } + } + + if (isa->extension_enabled(EXT_XZBT)) { + DEFINE_R3TYPE(cmix); + DEFINE_R3TYPE(fsr); + DEFINE_R3TYPE(fsri); + if(isa->get_max_xlen() == 64) { + DEFINE_R3TYPE(fsriw); + DEFINE_R3TYPE(fsrw); + } + } + + if (isa->extension_enabled(EXT_ZICBOM)) { + DISASM_INSN("cbo.clean", cbo_clean, 0, {&base_only_address}); + DISASM_INSN("cbo.flush", cbo_flush, 0, {&base_only_address}); + DISASM_INSN("cbo.inval", cbo_inval, 0, {&base_only_address}); + } + + if (isa->extension_enabled(EXT_ZICBOZ)) { + DISASM_INSN("cbo.zero", cbo_zero, 0, {&base_only_address}); + } + + if (isa->extension_enabled(EXT_ZKND) || + isa->extension_enabled(EXT_ZKNE)) { + DISASM_INSN("aes64ks1i", aes64ks1i, 0, {&xrd, &xrs1, &rcon}); + DEFINE_RTYPE(aes64ks2); + } + + if (isa->extension_enabled(EXT_ZKND)) { + if(isa->get_max_xlen() == 64) { + DEFINE_RTYPE(aes64ds); + DEFINE_RTYPE(aes64dsm); + DEFINE_R1TYPE(aes64im); + } else if (isa->get_max_xlen() == 32) { + DISASM_INSN("aes32dsi", aes32dsi, 0, {&xrd, &xrs1, &xrs2, &bs}); + DISASM_INSN("aes32dsmi", aes32dsmi, 0, {&xrd, &xrs1, &xrs2, &bs}); + } + } + + if (isa->extension_enabled(EXT_ZKNE)) { + if(isa->get_max_xlen() == 64) { + DEFINE_RTYPE(aes64es); + DEFINE_RTYPE(aes64esm); + } else if (isa->get_max_xlen() == 32) { + DISASM_INSN("aes32esi", aes32esi, 0, {&xrd, &xrs1, &xrs2, &bs}); + DISASM_INSN("aes32esmi", aes32esmi, 0, {&xrd, &xrs1, &xrs2, &bs}); + } + } + + if (isa->extension_enabled(EXT_ZKNH)) { + DEFINE_R1TYPE(sha256sig0); + DEFINE_R1TYPE(sha256sig1); + DEFINE_R1TYPE(sha256sum0); + DEFINE_R1TYPE(sha256sum1); + if(isa->get_max_xlen() == 64) { + DEFINE_R1TYPE(sha512sig0); + DEFINE_R1TYPE(sha512sig1); + DEFINE_R1TYPE(sha512sum0); + DEFINE_R1TYPE(sha512sum1); + } else if (isa->get_max_xlen() == 32) { + DEFINE_RTYPE(sha512sig0h); + DEFINE_RTYPE(sha512sig0l); + DEFINE_RTYPE(sha512sig1h); + DEFINE_RTYPE(sha512sig1l); + DEFINE_RTYPE(sha512sum0r); + DEFINE_RTYPE(sha512sum1r); + } + } + + if (isa->extension_enabled(EXT_ZKSED)) { + DISASM_INSN("sm4ed", sm4ed, 0, {&xrd, &xrs1, &xrs2, &bs}); + DISASM_INSN("sm4ks", sm4ks, 0, {&xrd, &xrs1, &xrs2, &bs}); + } + + if (isa->extension_enabled(EXT_ZKSH)) { + DEFINE_R1TYPE(sm3p0); + DEFINE_R1TYPE(sm3p1); + } + +} + +disassembler_t::disassembler_t(const isa_parser_t *isa) +{ + // highest priority: instructions explicitly enabled + add_instructions(isa); + + // next-highest priority: other instructions in same base ISA + std::string fallback_isa_string = std::string("rv") + std::to_string(isa->get_max_xlen()) + + "gqchv_zfh_zba_zbb_zbc_zbs_zcb_zicbom_zicboz_zkn_zkr_zks_svinval_xbitmanip"; + isa_parser_t fallback_isa(fallback_isa_string.c_str(), DEFAULT_PRIV); + add_instructions(&fallback_isa); + + // finally: instructions with known opcodes but unknown arguments + add_unknown_insns(this); + + // Now, reverse the lists, because we search them back-to-front (so that + // custom instructions later added with add_insn have highest priority). + for (size_t i = 0; i < HASH_SIZE+1; i++) + std::reverse(chain[i].begin(), chain[i].end()); +} + +const disasm_insn_t* disassembler_t::probe_once(insn_t insn, size_t idx) const +{ + for (auto it = chain[idx].rbegin(); it != chain[idx].rend(); ++it) + if (*(*it) == insn) + return *it; + + return NULL; +} + +const disasm_insn_t* disassembler_t::lookup(insn_t insn) const +{ + if (auto p = probe_once(insn, hash(insn.bits(), MASK1))) + return p; + + if (auto p = probe_once(insn, hash(insn.bits(), MASK2))) + return p; + + return probe_once(insn, HASH_SIZE); +} + +void NOINLINE disassembler_t::add_insn(disasm_insn_t* insn) +{ + size_t idx = + (insn->get_mask() & MASK1) == MASK1 ? hash(insn->get_match(), MASK1) : + (insn->get_mask() & MASK2) == MASK2 ? hash(insn->get_match(), MASK2) : + HASH_SIZE; + + chain[idx].push_back(insn); +} + +disassembler_t::~disassembler_t() +{ + for (size_t i = 0; i < HASH_SIZE+1; i++) + for (size_t j = 0; j < chain[i].size(); j++) + delete chain[i][j]; +} diff --git a/vendor/riscv/riscv-isa-sim/disasm/disasm.mk.in b/vendor/riscv/riscv-isa-sim/disasm/disasm.mk.in new file mode 100644 index 0000000000..9eafb12f9b --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/disasm/disasm.mk.in @@ -0,0 +1,5 @@ +disasm_srcs = \ + disasm.cc \ + regnames.cc \ + +disasm_install_lib = yes diff --git a/vendor/riscv/riscv-isa-sim/disasm/regnames.cc b/vendor/riscv/riscv-isa-sim/disasm/regnames.cc new file mode 100644 index 0000000000..0a7fd4d22c --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/disasm/regnames.cc @@ -0,0 +1,33 @@ +// See LICENSE for license details. + +#include "disasm.h" + +const char* xpr_name[] = { + "zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", + "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", + "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", + "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6" +}; + +const char* fpr_name[] = { + "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", + "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5", + "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7", + "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11" +}; + +const char* vr_name[] = { + "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", + "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", + "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", + "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" +}; + +const char* csr_name(int which) { + switch (which) { + #define DECLARE_CSR(name, number) case number: return #name; + #include "encoding.h" + #undef DECLARE_CSR + } + return "unknown-csr"; +} diff --git a/vendor/riscv/riscv-isa-sim/fdt/fdt.ac b/vendor/riscv/riscv-isa-sim/fdt/fdt.ac new file mode 100644 index 0000000000..e69de29bb2 diff --git a/vendor/riscv/riscv-isa-sim/fdt/fdt.c b/vendor/riscv/riscv-isa-sim/fdt/fdt.c new file mode 100644 index 0000000000..16fd0612ed --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/fdt/fdt.c @@ -0,0 +1,291 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * libfdt - Flat Device Tree manipulation + * Copyright (C) 2006 David Gibson, IBM Corporation. + */ +#include "libfdt_env.h" + +#include "fdt.h" +#include "libfdt.h" + +#include "libfdt_internal.h" + +/* + * Minimal sanity check for a read-only tree. fdt_ro_probe_() checks + * that the given buffer contains what appears to be a flattened + * device tree with sane information in its header. + */ +int32_t fdt_ro_probe_(const void *fdt) +{ + uint32_t totalsize = fdt_totalsize(fdt); + + if (fdt_magic(fdt) == FDT_MAGIC) { + /* Complete tree */ + if (fdt_version(fdt) < FDT_FIRST_SUPPORTED_VERSION) + return -FDT_ERR_BADVERSION; + if (fdt_last_comp_version(fdt) > FDT_LAST_SUPPORTED_VERSION) + return -FDT_ERR_BADVERSION; + } else if (fdt_magic(fdt) == FDT_SW_MAGIC) { + /* Unfinished sequential-write blob */ + if (fdt_size_dt_struct(fdt) == 0) + return -FDT_ERR_BADSTATE; + } else { + return -FDT_ERR_BADMAGIC; + } + + if (totalsize < INT32_MAX) + return totalsize; + else + return -FDT_ERR_TRUNCATED; +} + +static int check_off_(uint32_t hdrsize, uint32_t totalsize, uint32_t off) +{ + return (off >= hdrsize) && (off <= totalsize); +} + +static int check_block_(uint32_t hdrsize, uint32_t totalsize, + uint32_t base, uint32_t size) +{ + if (!check_off_(hdrsize, totalsize, base)) + return 0; /* block start out of bounds */ + if ((base + size) < base) + return 0; /* overflow */ + if (!check_off_(hdrsize, totalsize, base + size)) + return 0; /* block end out of bounds */ + return 1; +} + +size_t fdt_header_size_(uint32_t version) +{ + if (version <= 1) + return FDT_V1_SIZE; + else if (version <= 2) + return FDT_V2_SIZE; + else if (version <= 3) + return FDT_V3_SIZE; + else if (version <= 16) + return FDT_V16_SIZE; + else + return FDT_V17_SIZE; +} + +int fdt_check_header(const void *fdt) +{ + size_t hdrsize; + + if (fdt_magic(fdt) != FDT_MAGIC) + return -FDT_ERR_BADMAGIC; + hdrsize = fdt_header_size(fdt); + if ((fdt_version(fdt) < FDT_FIRST_SUPPORTED_VERSION) + || (fdt_last_comp_version(fdt) > FDT_LAST_SUPPORTED_VERSION)) + return -FDT_ERR_BADVERSION; + if (fdt_version(fdt) < fdt_last_comp_version(fdt)) + return -FDT_ERR_BADVERSION; + + if ((fdt_totalsize(fdt) < hdrsize) + || (fdt_totalsize(fdt) > INT_MAX)) + return -FDT_ERR_TRUNCATED; + + /* Bounds check memrsv block */ + if (!check_off_(hdrsize, fdt_totalsize(fdt), fdt_off_mem_rsvmap(fdt))) + return -FDT_ERR_TRUNCATED; + + /* Bounds check structure block */ + if (fdt_version(fdt) < 17) { + if (!check_off_(hdrsize, fdt_totalsize(fdt), + fdt_off_dt_struct(fdt))) + return -FDT_ERR_TRUNCATED; + } else { + if (!check_block_(hdrsize, fdt_totalsize(fdt), + fdt_off_dt_struct(fdt), + fdt_size_dt_struct(fdt))) + return -FDT_ERR_TRUNCATED; + } + + /* Bounds check strings block */ + if (!check_block_(hdrsize, fdt_totalsize(fdt), + fdt_off_dt_strings(fdt), fdt_size_dt_strings(fdt))) + return -FDT_ERR_TRUNCATED; + + return 0; +} + +const void *fdt_offset_ptr(const void *fdt, int offset, unsigned int len) +{ + unsigned absoffset = offset + fdt_off_dt_struct(fdt); + + if ((absoffset < offset) + || ((absoffset + len) < absoffset) + || (absoffset + len) > fdt_totalsize(fdt)) + return NULL; + + if (fdt_version(fdt) >= 0x11) + if (((offset + len) < offset) + || ((offset + len) > fdt_size_dt_struct(fdt))) + return NULL; + + return fdt_offset_ptr_(fdt, offset); +} + +uint32_t fdt_next_tag(const void *fdt, int startoffset, int *nextoffset) +{ + const fdt32_t *tagp, *lenp; + uint32_t tag; + int offset = startoffset; + const char *p; + + *nextoffset = -FDT_ERR_TRUNCATED; + tagp = fdt_offset_ptr(fdt, offset, FDT_TAGSIZE); + if (!tagp) + return FDT_END; /* premature end */ + tag = fdt32_to_cpu(*tagp); + offset += FDT_TAGSIZE; + + *nextoffset = -FDT_ERR_BADSTRUCTURE; + switch (tag) { + case FDT_BEGIN_NODE: + /* skip name */ + do { + p = fdt_offset_ptr(fdt, offset++, 1); + } while (p && (*p != '\0')); + if (!p) + return FDT_END; /* premature end */ + break; + + case FDT_PROP: + lenp = fdt_offset_ptr(fdt, offset, sizeof(*lenp)); + if (!lenp) + return FDT_END; /* premature end */ + /* skip-name offset, length and value */ + offset += sizeof(struct fdt_property) - FDT_TAGSIZE + + fdt32_to_cpu(*lenp); + if (fdt_version(fdt) < 0x10 && fdt32_to_cpu(*lenp) >= 8 && + ((offset - fdt32_to_cpu(*lenp)) % 8) != 0) + offset += 4; + break; + + case FDT_END: + case FDT_END_NODE: + case FDT_NOP: + break; + + default: + return FDT_END; + } + + if (!fdt_offset_ptr(fdt, startoffset, offset - startoffset)) + return FDT_END; /* premature end */ + + *nextoffset = FDT_TAGALIGN(offset); + return tag; +} + +int fdt_check_node_offset_(const void *fdt, int offset) +{ + if ((offset < 0) || (offset % FDT_TAGSIZE) + || (fdt_next_tag(fdt, offset, &offset) != FDT_BEGIN_NODE)) + return -FDT_ERR_BADOFFSET; + + return offset; +} + +int fdt_check_prop_offset_(const void *fdt, int offset) +{ + if ((offset < 0) || (offset % FDT_TAGSIZE) + || (fdt_next_tag(fdt, offset, &offset) != FDT_PROP)) + return -FDT_ERR_BADOFFSET; + + return offset; +} + +int fdt_next_node(const void *fdt, int offset, int *depth) +{ + int nextoffset = 0; + uint32_t tag; + + if (offset >= 0) + if ((nextoffset = fdt_check_node_offset_(fdt, offset)) < 0) + return nextoffset; + + do { + offset = nextoffset; + tag = fdt_next_tag(fdt, offset, &nextoffset); + + switch (tag) { + case FDT_PROP: + case FDT_NOP: + break; + + case FDT_BEGIN_NODE: + if (depth) + (*depth)++; + break; + + case FDT_END_NODE: + if (depth && ((--(*depth)) < 0)) + return nextoffset; + break; + + case FDT_END: + if ((nextoffset >= 0) + || ((nextoffset == -FDT_ERR_TRUNCATED) && !depth)) + return -FDT_ERR_NOTFOUND; + else + return nextoffset; + } + } while (tag != FDT_BEGIN_NODE); + + return offset; +} + +int fdt_first_subnode(const void *fdt, int offset) +{ + int depth = 0; + + offset = fdt_next_node(fdt, offset, &depth); + if (offset < 0 || depth != 1) + return -FDT_ERR_NOTFOUND; + + return offset; +} + +int fdt_next_subnode(const void *fdt, int offset) +{ + int depth = 1; + + /* + * With respect to the parent, the depth of the next subnode will be + * the same as the last. + */ + do { + offset = fdt_next_node(fdt, offset, &depth); + if (offset < 0 || depth < 1) + return -FDT_ERR_NOTFOUND; + } while (depth > 1); + + return offset; +} + +const char *fdt_find_string_(const char *strtab, int tabsize, const char *s) +{ + int len = strlen(s) + 1; + const char *last = strtab + tabsize - len; + const char *p; + + for (p = strtab; p <= last; p++) + if (memcmp(p, s, len) == 0) + return p; + return NULL; +} + +int fdt_move(const void *fdt, void *buf, int bufsize) +{ + FDT_RO_PROBE(fdt); + + if (fdt_totalsize(fdt) > bufsize) + return -FDT_ERR_NOSPACE; + + memmove(buf, fdt, fdt_totalsize(fdt)); + return 0; +} diff --git a/vendor/riscv/riscv-isa-sim/fdt/fdt.h b/vendor/riscv/riscv-isa-sim/fdt/fdt.h new file mode 100644 index 0000000000..f2e68807f2 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/fdt/fdt.h @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) */ +#ifndef FDT_H +#define FDT_H +/* + * libfdt - Flat Device Tree manipulation + * Copyright (C) 2006 David Gibson, IBM Corporation. + * Copyright 2012 Kim Phillips, Freescale Semiconductor. + */ + +#ifndef __ASSEMBLY__ + +struct fdt_header { + fdt32_t magic; /* magic word FDT_MAGIC */ + fdt32_t totalsize; /* total size of DT block */ + fdt32_t off_dt_struct; /* offset to structure */ + fdt32_t off_dt_strings; /* offset to strings */ + fdt32_t off_mem_rsvmap; /* offset to memory reserve map */ + fdt32_t version; /* format version */ + fdt32_t last_comp_version; /* last compatible version */ + + /* version 2 fields below */ + fdt32_t boot_cpuid_phys; /* Which physical CPU id we're + booting on */ + /* version 3 fields below */ + fdt32_t size_dt_strings; /* size of the strings block */ + + /* version 17 fields below */ + fdt32_t size_dt_struct; /* size of the structure block */ +}; + +struct fdt_reserve_entry { + fdt64_t address; + fdt64_t size; +}; + +struct fdt_node_header { + fdt32_t tag; + char name[0]; +}; + +struct fdt_property { + fdt32_t tag; + fdt32_t len; + fdt32_t nameoff; + char data[0]; +}; + +#endif /* !__ASSEMBLY */ + +#define FDT_MAGIC 0xd00dfeed /* 4: version, 4: total size */ +#define FDT_TAGSIZE sizeof(fdt32_t) + +#define FDT_BEGIN_NODE 0x1 /* Start node: full name */ +#define FDT_END_NODE 0x2 /* End node */ +#define FDT_PROP 0x3 /* Property: name off, + size, content */ +#define FDT_NOP 0x4 /* nop */ +#define FDT_END 0x9 + +#define FDT_V1_SIZE (7*sizeof(fdt32_t)) +#define FDT_V2_SIZE (FDT_V1_SIZE + sizeof(fdt32_t)) +#define FDT_V3_SIZE (FDT_V2_SIZE + sizeof(fdt32_t)) +#define FDT_V16_SIZE FDT_V3_SIZE +#define FDT_V17_SIZE (FDT_V16_SIZE + sizeof(fdt32_t)) + +#endif /* FDT_H */ diff --git a/vendor/riscv/riscv-isa-sim/fdt/fdt.mk.in b/vendor/riscv/riscv-isa-sim/fdt/fdt.mk.in new file mode 100644 index 0000000000..8c8dbe53c7 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/fdt/fdt.mk.in @@ -0,0 +1,12 @@ +fdt_subproject_deps = \ + +fdt_c_srcs = \ + fdt.c \ + fdt_ro.c \ + fdt_wip.c \ + fdt_sw.c \ + fdt_rw.c \ + fdt_strerror.c \ + fdt_empty_tree.c \ + fdt_addresses.c \ + fdt_overlay.c \ diff --git a/vendor/riscv/riscv-isa-sim/fdt/fdt_addresses.c b/vendor/riscv/riscv-isa-sim/fdt/fdt_addresses.c new file mode 100644 index 0000000000..9a82cd0ba2 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/fdt/fdt_addresses.c @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * libfdt - Flat Device Tree manipulation + * Copyright (C) 2014 David Gibson <david@gibson.dropbear.id.au> + * Copyright (C) 2018 embedded brains GmbH + */ +#include "libfdt_env.h" + +#include <fdt.h> +#include <libfdt.h> + +#include "libfdt_internal.h" + +static int fdt_cells(const void *fdt, int nodeoffset, const char *name) +{ + const fdt32_t *c; + uint32_t val; + int len; + + c = fdt_getprop(fdt, nodeoffset, name, &len); + if (!c) + return len; + + if (len != sizeof(*c)) + return -FDT_ERR_BADNCELLS; + + val = fdt32_to_cpu(*c); + if (val > FDT_MAX_NCELLS) + return -FDT_ERR_BADNCELLS; + + return (int)val; +} + +int fdt_address_cells(const void *fdt, int nodeoffset) +{ + int val; + + val = fdt_cells(fdt, nodeoffset, "#address-cells"); + if (val == 0) + return -FDT_ERR_BADNCELLS; + if (val == -FDT_ERR_NOTFOUND) + return 2; + return val; +} + +int fdt_size_cells(const void *fdt, int nodeoffset) +{ + int val; + + val = fdt_cells(fdt, nodeoffset, "#size-cells"); + if (val == -FDT_ERR_NOTFOUND) + return 1; + return val; +} + +/* This function assumes that [address|size]_cells is 1 or 2 */ +int fdt_appendprop_addrrange(void *fdt, int parent, int nodeoffset, + const char *name, uint64_t addr, uint64_t size) +{ + int addr_cells, size_cells, ret; + uint8_t data[sizeof(fdt64_t) * 2], *prop; + + ret = fdt_address_cells(fdt, parent); + if (ret < 0) + return ret; + addr_cells = ret; + + ret = fdt_size_cells(fdt, parent); + if (ret < 0) + return ret; + size_cells = ret; + + /* check validity of address */ + prop = data; + if (addr_cells == 1) { + if ((addr > UINT32_MAX) || ((UINT32_MAX + 1 - addr) < size)) + return -FDT_ERR_BADVALUE; + + fdt32_st(prop, (uint32_t)addr); + } else if (addr_cells == 2) { + fdt64_st(prop, addr); + } else { + return -FDT_ERR_BADNCELLS; + } + + /* check validity of size */ + prop += addr_cells * sizeof(fdt32_t); + if (size_cells == 1) { + if (size > UINT32_MAX) + return -FDT_ERR_BADVALUE; + + fdt32_st(prop, (uint32_t)size); + } else if (size_cells == 2) { + fdt64_st(prop, size); + } else { + return -FDT_ERR_BADNCELLS; + } + + return fdt_appendprop(fdt, nodeoffset, name, data, + (addr_cells + size_cells) * sizeof(fdt32_t)); +} diff --git a/vendor/riscv/riscv-isa-sim/fdt/fdt_empty_tree.c b/vendor/riscv/riscv-isa-sim/fdt/fdt_empty_tree.c new file mode 100644 index 0000000000..49d54d44b8 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/fdt/fdt_empty_tree.c @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * libfdt - Flat Device Tree manipulation + * Copyright (C) 2012 David Gibson, IBM Corporation. + */ +#include "libfdt_env.h" + +#include <fdt.h> +#include <libfdt.h> + +#include "libfdt_internal.h" + +int fdt_create_empty_tree(void *buf, int bufsize) +{ + int err; + + err = fdt_create(buf, bufsize); + if (err) + return err; + + err = fdt_finish_reservemap(buf); + if (err) + return err; + + err = fdt_begin_node(buf, ""); + if (err) + return err; + + err = fdt_end_node(buf); + if (err) + return err; + + err = fdt_finish(buf); + if (err) + return err; + + return fdt_open_into(buf, buf, bufsize); +} diff --git a/vendor/riscv/riscv-isa-sim/fdt/fdt_overlay.c b/vendor/riscv/riscv-isa-sim/fdt/fdt_overlay.c new file mode 100644 index 0000000000..be71873366 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/fdt/fdt_overlay.c @@ -0,0 +1,881 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * libfdt - Flat Device Tree manipulation + * Copyright (C) 2016 Free Electrons + * Copyright (C) 2016 NextThing Co. + */ +#include "libfdt_env.h" + +#include <fdt.h> +#include <libfdt.h> + +#include "libfdt_internal.h" + +/** + * overlay_get_target_phandle - retrieves the target phandle of a fragment + * @fdto: pointer to the device tree overlay blob + * @fragment: node offset of the fragment in the overlay + * + * overlay_get_target_phandle() retrieves the target phandle of an + * overlay fragment when that fragment uses a phandle (target + * property) instead of a path (target-path property). + * + * returns: + * the phandle pointed by the target property + * 0, if the phandle was not found + * -1, if the phandle was malformed + */ +static uint32_t overlay_get_target_phandle(const void *fdto, int fragment) +{ + const fdt32_t *val; + int len; + + val = fdt_getprop(fdto, fragment, "target", &len); + if (!val) + return 0; + + if ((len != sizeof(*val)) || (fdt32_to_cpu(*val) == (uint32_t)-1)) + return (uint32_t)-1; + + return fdt32_to_cpu(*val); +} + +/** + * overlay_get_target - retrieves the offset of a fragment's target + * @fdt: Base device tree blob + * @fdto: Device tree overlay blob + * @fragment: node offset of the fragment in the overlay + * @pathp: pointer which receives the path of the target (or NULL) + * + * overlay_get_target() retrieves the target offset in the base + * device tree of a fragment, no matter how the actual targeting is + * done (through a phandle or a path) + * + * returns: + * the targeted node offset in the base device tree + * Negative error code on error + */ +static int overlay_get_target(const void *fdt, const void *fdto, + int fragment, char const **pathp) +{ + uint32_t phandle; + const char *path = NULL; + int path_len = 0, ret; + + /* Try first to do a phandle based lookup */ + phandle = overlay_get_target_phandle(fdto, fragment); + if (phandle == (uint32_t)-1) + return -FDT_ERR_BADPHANDLE; + + /* no phandle, try path */ + if (!phandle) { + /* And then a path based lookup */ + path = fdt_getprop(fdto, fragment, "target-path", &path_len); + if (path) + ret = fdt_path_offset(fdt, path); + else + ret = path_len; + } else + ret = fdt_node_offset_by_phandle(fdt, phandle); + + /* + * If we haven't found either a target or a + * target-path property in a node that contains a + * __overlay__ subnode (we wouldn't be called + * otherwise), consider it a improperly written + * overlay + */ + if (ret < 0 && path_len == -FDT_ERR_NOTFOUND) + ret = -FDT_ERR_BADOVERLAY; + + /* return on error */ + if (ret < 0) + return ret; + + /* return pointer to path (if available) */ + if (pathp) + *pathp = path ? path : NULL; + + return ret; +} + +/** + * overlay_phandle_add_offset - Increases a phandle by an offset + * @fdt: Base device tree blob + * @node: Device tree overlay blob + * @name: Name of the property to modify (phandle or linux,phandle) + * @delta: offset to apply + * + * overlay_phandle_add_offset() increments a node phandle by a given + * offset. + * + * returns: + * 0 on success. + * Negative error code on error + */ +static int overlay_phandle_add_offset(void *fdt, int node, + const char *name, uint32_t delta) +{ + const fdt32_t *val; + uint32_t adj_val; + int len; + + val = fdt_getprop(fdt, node, name, &len); + if (!val) + return len; + + if (len != sizeof(*val)) + return -FDT_ERR_BADPHANDLE; + + adj_val = fdt32_to_cpu(*val); + if ((adj_val + delta) < adj_val) + return -FDT_ERR_NOPHANDLES; + + adj_val += delta; + if (adj_val == (uint32_t)-1) + return -FDT_ERR_NOPHANDLES; + + return fdt_setprop_inplace_u32(fdt, node, name, adj_val); +} + +/** + * overlay_adjust_node_phandles - Offsets the phandles of a node + * @fdto: Device tree overlay blob + * @node: Offset of the node we want to adjust + * @delta: Offset to shift the phandles of + * + * overlay_adjust_node_phandles() adds a constant to all the phandles + * of a given node. This is mainly use as part of the overlay + * application process, when we want to update all the overlay + * phandles to not conflict with the overlays of the base device tree. + * + * returns: + * 0 on success + * Negative error code on failure + */ +static int overlay_adjust_node_phandles(void *fdto, int node, + uint32_t delta) +{ + int child; + int ret; + + ret = overlay_phandle_add_offset(fdto, node, "phandle", delta); + if (ret && ret != -FDT_ERR_NOTFOUND) + return ret; + + ret = overlay_phandle_add_offset(fdto, node, "linux,phandle", delta); + if (ret && ret != -FDT_ERR_NOTFOUND) + return ret; + + fdt_for_each_subnode(child, fdto, node) { + ret = overlay_adjust_node_phandles(fdto, child, delta); + if (ret) + return ret; + } + + return 0; +} + +/** + * overlay_adjust_local_phandles - Adjust the phandles of a whole overlay + * @fdto: Device tree overlay blob + * @delta: Offset to shift the phandles of + * + * overlay_adjust_local_phandles() adds a constant to all the + * phandles of an overlay. This is mainly use as part of the overlay + * application process, when we want to update all the overlay + * phandles to not conflict with the overlays of the base device tree. + * + * returns: + * 0 on success + * Negative error code on failure + */ +static int overlay_adjust_local_phandles(void *fdto, uint32_t delta) +{ + /* + * Start adjusting the phandles from the overlay root + */ + return overlay_adjust_node_phandles(fdto, 0, delta); +} + +/** + * overlay_update_local_node_references - Adjust the overlay references + * @fdto: Device tree overlay blob + * @tree_node: Node offset of the node to operate on + * @fixup_node: Node offset of the matching local fixups node + * @delta: Offset to shift the phandles of + * + * overlay_update_local_nodes_references() update the phandles + * pointing to a node within the device tree overlay by adding a + * constant delta. + * + * This is mainly used as part of a device tree application process, + * where you want the device tree overlays phandles to not conflict + * with the ones from the base device tree before merging them. + * + * returns: + * 0 on success + * Negative error code on failure + */ +static int overlay_update_local_node_references(void *fdto, + int tree_node, + int fixup_node, + uint32_t delta) +{ + int fixup_prop; + int fixup_child; + int ret; + + fdt_for_each_property_offset(fixup_prop, fdto, fixup_node) { + const fdt32_t *fixup_val; + const char *tree_val; + const char *name; + int fixup_len; + int tree_len; + int i; + + fixup_val = fdt_getprop_by_offset(fdto, fixup_prop, + &name, &fixup_len); + if (!fixup_val) + return fixup_len; + + if (fixup_len % sizeof(uint32_t)) + return -FDT_ERR_BADOVERLAY; + + tree_val = fdt_getprop(fdto, tree_node, name, &tree_len); + if (!tree_val) { + if (tree_len == -FDT_ERR_NOTFOUND) + return -FDT_ERR_BADOVERLAY; + + return tree_len; + } + + for (i = 0; i < (fixup_len / sizeof(uint32_t)); i++) { + fdt32_t adj_val; + uint32_t poffset; + + poffset = fdt32_to_cpu(fixup_val[i]); + + /* + * phandles to fixup can be unaligned. + * + * Use a memcpy for the architectures that do + * not support unaligned accesses. + */ + memcpy(&adj_val, tree_val + poffset, sizeof(adj_val)); + + adj_val = cpu_to_fdt32(fdt32_to_cpu(adj_val) + delta); + + ret = fdt_setprop_inplace_namelen_partial(fdto, + tree_node, + name, + strlen(name), + poffset, + &adj_val, + sizeof(adj_val)); + if (ret == -FDT_ERR_NOSPACE) + return -FDT_ERR_BADOVERLAY; + + if (ret) + return ret; + } + } + + fdt_for_each_subnode(fixup_child, fdto, fixup_node) { + const char *fixup_child_name = fdt_get_name(fdto, fixup_child, + NULL); + int tree_child; + + tree_child = fdt_subnode_offset(fdto, tree_node, + fixup_child_name); + if (tree_child == -FDT_ERR_NOTFOUND) + return -FDT_ERR_BADOVERLAY; + if (tree_child < 0) + return tree_child; + + ret = overlay_update_local_node_references(fdto, + tree_child, + fixup_child, + delta); + if (ret) + return ret; + } + + return 0; +} + +/** + * overlay_update_local_references - Adjust the overlay references + * @fdto: Device tree overlay blob + * @delta: Offset to shift the phandles of + * + * overlay_update_local_references() update all the phandles pointing + * to a node within the device tree overlay by adding a constant + * delta to not conflict with the base overlay. + * + * This is mainly used as part of a device tree application process, + * where you want the device tree overlays phandles to not conflict + * with the ones from the base device tree before merging them. + * + * returns: + * 0 on success + * Negative error code on failure + */ +static int overlay_update_local_references(void *fdto, uint32_t delta) +{ + int fixups; + + fixups = fdt_path_offset(fdto, "/__local_fixups__"); + if (fixups < 0) { + /* There's no local phandles to adjust, bail out */ + if (fixups == -FDT_ERR_NOTFOUND) + return 0; + + return fixups; + } + + /* + * Update our local references from the root of the tree + */ + return overlay_update_local_node_references(fdto, 0, fixups, + delta); +} + +/** + * overlay_fixup_one_phandle - Set an overlay phandle to the base one + * @fdt: Base Device Tree blob + * @fdto: Device tree overlay blob + * @symbols_off: Node offset of the symbols node in the base device tree + * @path: Path to a node holding a phandle in the overlay + * @path_len: number of path characters to consider + * @name: Name of the property holding the phandle reference in the overlay + * @name_len: number of name characters to consider + * @poffset: Offset within the overlay property where the phandle is stored + * @label: Label of the node referenced by the phandle + * + * overlay_fixup_one_phandle() resolves an overlay phandle pointing to + * a node in the base device tree. + * + * This is part of the device tree overlay application process, when + * you want all the phandles in the overlay to point to the actual + * base dt nodes. + * + * returns: + * 0 on success + * Negative error code on failure + */ +static int overlay_fixup_one_phandle(void *fdt, void *fdto, + int symbols_off, + const char *path, uint32_t path_len, + const char *name, uint32_t name_len, + int poffset, const char *label) +{ + const char *symbol_path; + uint32_t phandle; + fdt32_t phandle_prop; + int symbol_off, fixup_off; + int prop_len; + + if (symbols_off < 0) + return symbols_off; + + symbol_path = fdt_getprop(fdt, symbols_off, label, + &prop_len); + if (!symbol_path) + return prop_len; + + symbol_off = fdt_path_offset(fdt, symbol_path); + if (symbol_off < 0) + return symbol_off; + + phandle = fdt_get_phandle(fdt, symbol_off); + if (!phandle) + return -FDT_ERR_NOTFOUND; + + fixup_off = fdt_path_offset_namelen(fdto, path, path_len); + if (fixup_off == -FDT_ERR_NOTFOUND) + return -FDT_ERR_BADOVERLAY; + if (fixup_off < 0) + return fixup_off; + + phandle_prop = cpu_to_fdt32(phandle); + return fdt_setprop_inplace_namelen_partial(fdto, fixup_off, + name, name_len, poffset, + &phandle_prop, + sizeof(phandle_prop)); +}; + +/** + * overlay_fixup_phandle - Set an overlay phandle to the base one + * @fdt: Base Device Tree blob + * @fdto: Device tree overlay blob + * @symbols_off: Node offset of the symbols node in the base device tree + * @property: Property offset in the overlay holding the list of fixups + * + * overlay_fixup_phandle() resolves all the overlay phandles pointed + * to in a __fixups__ property, and updates them to match the phandles + * in use in the base device tree. + * + * This is part of the device tree overlay application process, when + * you want all the phandles in the overlay to point to the actual + * base dt nodes. + * + * returns: + * 0 on success + * Negative error code on failure + */ +static int overlay_fixup_phandle(void *fdt, void *fdto, int symbols_off, + int property) +{ + const char *value; + const char *label; + int len; + + value = fdt_getprop_by_offset(fdto, property, + &label, &len); + if (!value) { + if (len == -FDT_ERR_NOTFOUND) + return -FDT_ERR_INTERNAL; + + return len; + } + + do { + const char *path, *name, *fixup_end; + const char *fixup_str = value; + uint32_t path_len, name_len; + uint32_t fixup_len; + char *sep, *endptr; + int poffset, ret; + + fixup_end = memchr(value, '\0', len); + if (!fixup_end) + return -FDT_ERR_BADOVERLAY; + fixup_len = fixup_end - fixup_str; + + len -= fixup_len + 1; + value += fixup_len + 1; + + path = fixup_str; + sep = memchr(fixup_str, ':', fixup_len); + if (!sep || *sep != ':') + return -FDT_ERR_BADOVERLAY; + + path_len = sep - path; + if (path_len == (fixup_len - 1)) + return -FDT_ERR_BADOVERLAY; + + fixup_len -= path_len + 1; + name = sep + 1; + sep = memchr(name, ':', fixup_len); + if (!sep || *sep != ':') + return -FDT_ERR_BADOVERLAY; + + name_len = sep - name; + if (!name_len) + return -FDT_ERR_BADOVERLAY; + + poffset = strtoul(sep + 1, &endptr, 10); + if ((*endptr != '\0') || (endptr <= (sep + 1))) + return -FDT_ERR_BADOVERLAY; + + ret = overlay_fixup_one_phandle(fdt, fdto, symbols_off, + path, path_len, name, name_len, + poffset, label); + if (ret) + return ret; + } while (len > 0); + + return 0; +} + +/** + * overlay_fixup_phandles - Resolve the overlay phandles to the base + * device tree + * @fdt: Base Device Tree blob + * @fdto: Device tree overlay blob + * + * overlay_fixup_phandles() resolves all the overlay phandles pointing + * to nodes in the base device tree. + * + * This is one of the steps of the device tree overlay application + * process, when you want all the phandles in the overlay to point to + * the actual base dt nodes. + * + * returns: + * 0 on success + * Negative error code on failure + */ +static int overlay_fixup_phandles(void *fdt, void *fdto) +{ + int fixups_off, symbols_off; + int property; + + /* We can have overlays without any fixups */ + fixups_off = fdt_path_offset(fdto, "/__fixups__"); + if (fixups_off == -FDT_ERR_NOTFOUND) + return 0; /* nothing to do */ + if (fixups_off < 0) + return fixups_off; + + /* And base DTs without symbols */ + symbols_off = fdt_path_offset(fdt, "/__symbols__"); + if ((symbols_off < 0 && (symbols_off != -FDT_ERR_NOTFOUND))) + return symbols_off; + + fdt_for_each_property_offset(property, fdto, fixups_off) { + int ret; + + ret = overlay_fixup_phandle(fdt, fdto, symbols_off, property); + if (ret) + return ret; + } + + return 0; +} + +/** + * overlay_apply_node - Merges a node into the base device tree + * @fdt: Base Device Tree blob + * @target: Node offset in the base device tree to apply the fragment to + * @fdto: Device tree overlay blob + * @node: Node offset in the overlay holding the changes to merge + * + * overlay_apply_node() merges a node into a target base device tree + * node pointed. + * + * This is part of the final step in the device tree overlay + * application process, when all the phandles have been adjusted and + * resolved and you just have to merge overlay into the base device + * tree. + * + * returns: + * 0 on success + * Negative error code on failure + */ +static int overlay_apply_node(void *fdt, int target, + void *fdto, int node) +{ + int property; + int subnode; + + fdt_for_each_property_offset(property, fdto, node) { + const char *name; + const void *prop; + int prop_len; + int ret; + + prop = fdt_getprop_by_offset(fdto, property, &name, + &prop_len); + if (prop_len == -FDT_ERR_NOTFOUND) + return -FDT_ERR_INTERNAL; + if (prop_len < 0) + return prop_len; + + ret = fdt_setprop(fdt, target, name, prop, prop_len); + if (ret) + return ret; + } + + fdt_for_each_subnode(subnode, fdto, node) { + const char *name = fdt_get_name(fdto, subnode, NULL); + int nnode; + int ret; + + nnode = fdt_add_subnode(fdt, target, name); + if (nnode == -FDT_ERR_EXISTS) { + nnode = fdt_subnode_offset(fdt, target, name); + if (nnode == -FDT_ERR_NOTFOUND) + return -FDT_ERR_INTERNAL; + } + + if (nnode < 0) + return nnode; + + ret = overlay_apply_node(fdt, nnode, fdto, subnode); + if (ret) + return ret; + } + + return 0; +} + +/** + * overlay_merge - Merge an overlay into its base device tree + * @fdt: Base Device Tree blob + * @fdto: Device tree overlay blob + * + * overlay_merge() merges an overlay into its base device tree. + * + * This is the next to last step in the device tree overlay application + * process, when all the phandles have been adjusted and resolved and + * you just have to merge overlay into the base device tree. + * + * returns: + * 0 on success + * Negative error code on failure + */ +static int overlay_merge(void *fdt, void *fdto) +{ + int fragment; + + fdt_for_each_subnode(fragment, fdto, 0) { + int overlay; + int target; + int ret; + + /* + * Each fragments will have an __overlay__ node. If + * they don't, it's not supposed to be merged + */ + overlay = fdt_subnode_offset(fdto, fragment, "__overlay__"); + if (overlay == -FDT_ERR_NOTFOUND) + continue; + + if (overlay < 0) + return overlay; + + target = overlay_get_target(fdt, fdto, fragment, NULL); + if (target < 0) + return target; + + ret = overlay_apply_node(fdt, target, fdto, overlay); + if (ret) + return ret; + } + + return 0; +} + +static int get_path_len(const void *fdt, int nodeoffset) +{ + int len = 0, namelen; + const char *name; + + FDT_RO_PROBE(fdt); + + for (;;) { + name = fdt_get_name(fdt, nodeoffset, &namelen); + if (!name) + return namelen; + + /* root? we're done */ + if (namelen == 0) + break; + + nodeoffset = fdt_parent_offset(fdt, nodeoffset); + if (nodeoffset < 0) + return nodeoffset; + len += namelen + 1; + } + + /* in case of root pretend it's "/" */ + if (len == 0) + len++; + return len; +} + +/** + * overlay_symbol_update - Update the symbols of base tree after a merge + * @fdt: Base Device Tree blob + * @fdto: Device tree overlay blob + * + * overlay_symbol_update() updates the symbols of the base tree with the + * symbols of the applied overlay + * + * This is the last step in the device tree overlay application + * process, allowing the reference of overlay symbols by subsequent + * overlay operations. + * + * returns: + * 0 on success + * Negative error code on failure + */ +static int overlay_symbol_update(void *fdt, void *fdto) +{ + int root_sym, ov_sym, prop, path_len, fragment, target; + int len, frag_name_len, ret, rel_path_len; + const char *s, *e; + const char *path; + const char *name; + const char *frag_name; + const char *rel_path; + const char *target_path; + char *buf; + void *p; + + ov_sym = fdt_subnode_offset(fdto, 0, "__symbols__"); + + /* if no overlay symbols exist no problem */ + if (ov_sym < 0) + return 0; + + root_sym = fdt_subnode_offset(fdt, 0, "__symbols__"); + + /* it no root symbols exist we should create them */ + if (root_sym == -FDT_ERR_NOTFOUND) + root_sym = fdt_add_subnode(fdt, 0, "__symbols__"); + + /* any error is fatal now */ + if (root_sym < 0) + return root_sym; + + /* iterate over each overlay symbol */ + fdt_for_each_property_offset(prop, fdto, ov_sym) { + path = fdt_getprop_by_offset(fdto, prop, &name, &path_len); + if (!path) + return path_len; + + /* verify it's a string property (terminated by a single \0) */ + if (path_len < 1 || memchr(path, '\0', path_len) != &path[path_len - 1]) + return -FDT_ERR_BADVALUE; + + /* keep end marker to avoid strlen() */ + e = path + path_len; + + if (*path != '/') + return -FDT_ERR_BADVALUE; + + /* get fragment name first */ + s = strchr(path + 1, '/'); + if (!s) { + /* Symbol refers to something that won't end + * up in the target tree */ + continue; + } + + frag_name = path + 1; + frag_name_len = s - path - 1; + + /* verify format; safe since "s" lies in \0 terminated prop */ + len = sizeof("/__overlay__/") - 1; + if ((e - s) > len && (memcmp(s, "/__overlay__/", len) == 0)) { + /* /<fragment-name>/__overlay__/<relative-subnode-path> */ + rel_path = s + len; + rel_path_len = e - rel_path; + } else if ((e - s) == len + && (memcmp(s, "/__overlay__", len - 1) == 0)) { + /* /<fragment-name>/__overlay__ */ + rel_path = ""; + rel_path_len = 0; + } else { + /* Symbol refers to something that won't end + * up in the target tree */ + continue; + } + + /* find the fragment index in which the symbol lies */ + ret = fdt_subnode_offset_namelen(fdto, 0, frag_name, + frag_name_len); + /* not found? */ + if (ret < 0) + return -FDT_ERR_BADOVERLAY; + fragment = ret; + + /* an __overlay__ subnode must exist */ + ret = fdt_subnode_offset(fdto, fragment, "__overlay__"); + if (ret < 0) + return -FDT_ERR_BADOVERLAY; + + /* get the target of the fragment */ + ret = overlay_get_target(fdt, fdto, fragment, &target_path); + if (ret < 0) + return ret; + target = ret; + + /* if we have a target path use */ + if (!target_path) { + ret = get_path_len(fdt, target); + if (ret < 0) + return ret; + len = ret; + } else { + len = strlen(target_path); + } + + ret = fdt_setprop_placeholder(fdt, root_sym, name, + len + (len > 1) + rel_path_len + 1, &p); + if (ret < 0) + return ret; + + if (!target_path) { + /* again in case setprop_placeholder changed it */ + ret = overlay_get_target(fdt, fdto, fragment, &target_path); + if (ret < 0) + return ret; + target = ret; + } + + buf = p; + if (len > 1) { /* target is not root */ + if (!target_path) { + ret = fdt_get_path(fdt, target, buf, len + 1); + if (ret < 0) + return ret; + } else + memcpy(buf, target_path, len + 1); + + } else + len--; + + buf[len] = '/'; + memcpy(buf + len + 1, rel_path, rel_path_len); + buf[len + 1 + rel_path_len] = '\0'; + } + + return 0; +} + +int fdt_overlay_apply(void *fdt, void *fdto) +{ + uint32_t delta; + int ret; + + FDT_RO_PROBE(fdt); + FDT_RO_PROBE(fdto); + + ret = fdt_find_max_phandle(fdt, &delta); + if (ret) + goto err; + + ret = overlay_adjust_local_phandles(fdto, delta); + if (ret) + goto err; + + ret = overlay_update_local_references(fdto, delta); + if (ret) + goto err; + + ret = overlay_fixup_phandles(fdt, fdto); + if (ret) + goto err; + + ret = overlay_merge(fdt, fdto); + if (ret) + goto err; + + ret = overlay_symbol_update(fdt, fdto); + if (ret) + goto err; + + /* + * The overlay has been damaged, erase its magic. + */ + fdt_set_magic(fdto, ~0); + + return 0; + +err: + /* + * The overlay might have been damaged, erase its magic. + */ + fdt_set_magic(fdto, ~0); + + /* + * The base device tree might have been damaged, erase its + * magic. + */ + fdt_set_magic(fdt, ~0); + + return ret; +} diff --git a/vendor/riscv/riscv-isa-sim/fdt/fdt_ro.c b/vendor/riscv/riscv-isa-sim/fdt/fdt_ro.c new file mode 100644 index 0000000000..a5c2797cde --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/fdt/fdt_ro.c @@ -0,0 +1,898 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * libfdt - Flat Device Tree manipulation + * Copyright (C) 2006 David Gibson, IBM Corporation. + */ +#include "libfdt_env.h" + +#include <fdt.h> +#include <libfdt.h> + +#include "libfdt_internal.h" + +static int fdt_nodename_eq_(const void *fdt, int offset, + const char *s, int len) +{ + int olen; + const char *p = fdt_get_name(fdt, offset, &olen); + + if (!p || olen < len) + /* short match */ + return 0; + + if (memcmp(p, s, len) != 0) + return 0; + + if (p[len] == '\0') + return 1; + else if (!memchr(s, '@', len) && (p[len] == '@')) + return 1; + else + return 0; +} + +const char *fdt_get_string(const void *fdt, int stroffset, int *lenp) +{ + int32_t totalsize = fdt_ro_probe_(fdt); + uint32_t absoffset = stroffset + fdt_off_dt_strings(fdt); + size_t len; + int err; + const char *s, *n; + + err = totalsize; + if (totalsize < 0) + goto fail; + + err = -FDT_ERR_BADOFFSET; + if (absoffset >= totalsize) + goto fail; + len = totalsize - absoffset; + + if (fdt_magic(fdt) == FDT_MAGIC) { + if (stroffset < 0) + goto fail; + if (fdt_version(fdt) >= 17) { + if (stroffset >= fdt_size_dt_strings(fdt)) + goto fail; + if ((fdt_size_dt_strings(fdt) - stroffset) < len) + len = fdt_size_dt_strings(fdt) - stroffset; + } + } else if (fdt_magic(fdt) == FDT_SW_MAGIC) { + if ((stroffset >= 0) + || (stroffset < -fdt_size_dt_strings(fdt))) + goto fail; + if ((-stroffset) < len) + len = -stroffset; + } else { + err = -FDT_ERR_INTERNAL; + goto fail; + } + + s = (const char *)fdt + absoffset; + n = memchr(s, '\0', len); + if (!n) { + /* missing terminating NULL */ + err = -FDT_ERR_TRUNCATED; + goto fail; + } + + if (lenp) + *lenp = n - s; + return s; + +fail: + if (lenp) + *lenp = err; + return NULL; +} + +const char *fdt_string(const void *fdt, int stroffset) +{ + return fdt_get_string(fdt, stroffset, NULL); +} + +static int fdt_string_eq_(const void *fdt, int stroffset, + const char *s, int len) +{ + int slen; + const char *p = fdt_get_string(fdt, stroffset, &slen); + + return p && (slen == len) && (memcmp(p, s, len) == 0); +} + +int fdt_find_max_phandle(const void *fdt, uint32_t *phandle) +{ + uint32_t max = 0; + int offset = -1; + + while (true) { + uint32_t value; + + offset = fdt_next_node(fdt, offset, NULL); + if (offset < 0) { + if (offset == -FDT_ERR_NOTFOUND) + break; + + return offset; + } + + value = fdt_get_phandle(fdt, offset); + + if (value > max) + max = value; + } + + if (phandle) + *phandle = max; + + return 0; +} + +int fdt_generate_phandle(const void *fdt, uint32_t *phandle) +{ + uint32_t max; + int err; + + err = fdt_find_max_phandle(fdt, &max); + if (err < 0) + return err; + + if (max == FDT_MAX_PHANDLE) + return -FDT_ERR_NOPHANDLES; + + if (phandle) + *phandle = max + 1; + + return 0; +} + +static const struct fdt_reserve_entry *fdt_mem_rsv(const void *fdt, int n) +{ + int offset = n * sizeof(struct fdt_reserve_entry); + int absoffset = fdt_off_mem_rsvmap(fdt) + offset; + + if (absoffset < fdt_off_mem_rsvmap(fdt)) + return NULL; + if (absoffset > fdt_totalsize(fdt) - sizeof(struct fdt_reserve_entry)) + return NULL; + return fdt_mem_rsv_(fdt, n); +} + +int fdt_get_mem_rsv(const void *fdt, int n, uint64_t *address, uint64_t *size) +{ + const struct fdt_reserve_entry *re; + + FDT_RO_PROBE(fdt); + re = fdt_mem_rsv(fdt, n); + if (!re) + return -FDT_ERR_BADOFFSET; + + *address = fdt64_ld(&re->address); + *size = fdt64_ld(&re->size); + return 0; +} + +int fdt_num_mem_rsv(const void *fdt) +{ + int i; + const struct fdt_reserve_entry *re; + + for (i = 0; (re = fdt_mem_rsv(fdt, i)) != NULL; i++) { + if (fdt64_ld(&re->size) == 0) + return i; + } + return -FDT_ERR_TRUNCATED; +} + +static int nextprop_(const void *fdt, int offset) +{ + uint32_t tag; + int nextoffset; + + do { + tag = fdt_next_tag(fdt, offset, &nextoffset); + + switch (tag) { + case FDT_END: + if (nextoffset >= 0) + return -FDT_ERR_BADSTRUCTURE; + else + return nextoffset; + + case FDT_PROP: + return offset; + } + offset = nextoffset; + } while (tag == FDT_NOP); + + return -FDT_ERR_NOTFOUND; +} + +int fdt_subnode_offset_namelen(const void *fdt, int offset, + const char *name, int namelen) +{ + int depth; + + FDT_RO_PROBE(fdt); + + for (depth = 0; + (offset >= 0) && (depth >= 0); + offset = fdt_next_node(fdt, offset, &depth)) + if ((depth == 1) + && fdt_nodename_eq_(fdt, offset, name, namelen)) + return offset; + + if (depth < 0) + return -FDT_ERR_NOTFOUND; + return offset; /* error */ +} + +int fdt_subnode_offset(const void *fdt, int parentoffset, + const char *name) +{ + return fdt_subnode_offset_namelen(fdt, parentoffset, name, strlen(name)); +} + +int fdt_path_offset_namelen(const void *fdt, const char *path, int namelen) +{ + const char *end = path + namelen; + const char *p = path; + int offset = 0; + + FDT_RO_PROBE(fdt); + + /* see if we have an alias */ + if (*path != '/') { + const char *q = memchr(path, '/', end - p); + + if (!q) + q = end; + + p = fdt_get_alias_namelen(fdt, p, q - p); + if (!p) + return -FDT_ERR_BADPATH; + offset = fdt_path_offset(fdt, p); + + p = q; + } + + while (p < end) { + const char *q; + + while (*p == '/') { + p++; + if (p == end) + return offset; + } + q = memchr(p, '/', end - p); + if (! q) + q = end; + + offset = fdt_subnode_offset_namelen(fdt, offset, p, q-p); + if (offset < 0) + return offset; + + p = q; + } + + return offset; +} + +int fdt_path_offset(const void *fdt, const char *path) +{ + return fdt_path_offset_namelen(fdt, path, strlen(path)); +} + +const char *fdt_get_name(const void *fdt, int nodeoffset, int *len) +{ + const struct fdt_node_header *nh = fdt_offset_ptr_(fdt, nodeoffset); + const char *nameptr; + int err; + + if (((err = fdt_ro_probe_(fdt)) < 0) + || ((err = fdt_check_node_offset_(fdt, nodeoffset)) < 0)) + goto fail; + + nameptr = nh->name; + + if (fdt_version(fdt) < 0x10) { + /* + * For old FDT versions, match the naming conventions of V16: + * give only the leaf name (after all /). The actual tree + * contents are loosely checked. + */ + const char *leaf; + leaf = strrchr(nameptr, '/'); + if (leaf == NULL) { + err = -FDT_ERR_BADSTRUCTURE; + goto fail; + } + nameptr = leaf+1; + } + + if (len) + *len = strlen(nameptr); + + return nameptr; + + fail: + if (len) + *len = err; + return NULL; +} + +int fdt_first_property_offset(const void *fdt, int nodeoffset) +{ + int offset; + + if ((offset = fdt_check_node_offset_(fdt, nodeoffset)) < 0) + return offset; + + return nextprop_(fdt, offset); +} + +int fdt_next_property_offset(const void *fdt, int offset) +{ + if ((offset = fdt_check_prop_offset_(fdt, offset)) < 0) + return offset; + + return nextprop_(fdt, offset); +} + +static const struct fdt_property *fdt_get_property_by_offset_(const void *fdt, + int offset, + int *lenp) +{ + int err; + const struct fdt_property *prop; + + if ((err = fdt_check_prop_offset_(fdt, offset)) < 0) { + if (lenp) + *lenp = err; + return NULL; + } + + prop = fdt_offset_ptr_(fdt, offset); + + if (lenp) + *lenp = fdt32_ld(&prop->len); + + return prop; +} + +const struct fdt_property *fdt_get_property_by_offset(const void *fdt, + int offset, + int *lenp) +{ + /* Prior to version 16, properties may need realignment + * and this API does not work. fdt_getprop_*() will, however. */ + + if (fdt_version(fdt) < 0x10) { + if (lenp) + *lenp = -FDT_ERR_BADVERSION; + return NULL; + } + + return fdt_get_property_by_offset_(fdt, offset, lenp); +} + +static const struct fdt_property *fdt_get_property_namelen_(const void *fdt, + int offset, + const char *name, + int namelen, + int *lenp, + int *poffset) +{ + for (offset = fdt_first_property_offset(fdt, offset); + (offset >= 0); + (offset = fdt_next_property_offset(fdt, offset))) { + const struct fdt_property *prop; + + if (!(prop = fdt_get_property_by_offset_(fdt, offset, lenp))) { + offset = -FDT_ERR_INTERNAL; + break; + } + if (fdt_string_eq_(fdt, fdt32_ld(&prop->nameoff), + name, namelen)) { + if (poffset) + *poffset = offset; + return prop; + } + } + + if (lenp) + *lenp = offset; + return NULL; +} + + +const struct fdt_property *fdt_get_property_namelen(const void *fdt, + int offset, + const char *name, + int namelen, int *lenp) +{ + /* Prior to version 16, properties may need realignment + * and this API does not work. fdt_getprop_*() will, however. */ + if (fdt_version(fdt) < 0x10) { + if (lenp) + *lenp = -FDT_ERR_BADVERSION; + return NULL; + } + + return fdt_get_property_namelen_(fdt, offset, name, namelen, lenp, + NULL); +} + + +const struct fdt_property *fdt_get_property(const void *fdt, + int nodeoffset, + const char *name, int *lenp) +{ + return fdt_get_property_namelen(fdt, nodeoffset, name, + strlen(name), lenp); +} + +const void *fdt_getprop_namelen(const void *fdt, int nodeoffset, + const char *name, int namelen, int *lenp) +{ + int poffset; + const struct fdt_property *prop; + + prop = fdt_get_property_namelen_(fdt, nodeoffset, name, namelen, lenp, + &poffset); + if (!prop) + return NULL; + + /* Handle realignment */ + if (fdt_version(fdt) < 0x10 && (poffset + sizeof(*prop)) % 8 && + fdt32_ld(&prop->len) >= 8) + return prop->data + 4; + return prop->data; +} + +const void *fdt_getprop_by_offset(const void *fdt, int offset, + const char **namep, int *lenp) +{ + const struct fdt_property *prop; + + prop = fdt_get_property_by_offset_(fdt, offset, lenp); + if (!prop) + return NULL; + if (namep) { + const char *name; + int namelen; + name = fdt_get_string(fdt, fdt32_ld(&prop->nameoff), + &namelen); + if (!name) { + if (lenp) + *lenp = namelen; + return NULL; + } + *namep = name; + } + + /* Handle realignment */ + if (fdt_version(fdt) < 0x10 && (offset + sizeof(*prop)) % 8 && + fdt32_ld(&prop->len) >= 8) + return prop->data + 4; + return prop->data; +} + +const void *fdt_getprop(const void *fdt, int nodeoffset, + const char *name, int *lenp) +{ + return fdt_getprop_namelen(fdt, nodeoffset, name, strlen(name), lenp); +} + +uint32_t fdt_get_phandle(const void *fdt, int nodeoffset) +{ + const fdt32_t *php; + int len; + + /* FIXME: This is a bit sub-optimal, since we potentially scan + * over all the properties twice. */ + php = fdt_getprop(fdt, nodeoffset, "phandle", &len); + if (!php || (len != sizeof(*php))) { + php = fdt_getprop(fdt, nodeoffset, "linux,phandle", &len); + if (!php || (len != sizeof(*php))) + return 0; + } + + return fdt32_ld(php); +} + +const char *fdt_get_alias_namelen(const void *fdt, + const char *name, int namelen) +{ + int aliasoffset; + + aliasoffset = fdt_path_offset(fdt, "/aliases"); + if (aliasoffset < 0) + return NULL; + + return fdt_getprop_namelen(fdt, aliasoffset, name, namelen, NULL); +} + +const char *fdt_get_alias(const void *fdt, const char *name) +{ + return fdt_get_alias_namelen(fdt, name, strlen(name)); +} + +int fdt_get_path(const void *fdt, int nodeoffset, char *buf, int buflen) +{ + int pdepth = 0, p = 0; + int offset, depth, namelen; + const char *name; + + FDT_RO_PROBE(fdt); + + if (buflen < 2) + return -FDT_ERR_NOSPACE; + + for (offset = 0, depth = 0; + (offset >= 0) && (offset <= nodeoffset); + offset = fdt_next_node(fdt, offset, &depth)) { + while (pdepth > depth) { + do { + p--; + } while (buf[p-1] != '/'); + pdepth--; + } + + if (pdepth >= depth) { + name = fdt_get_name(fdt, offset, &namelen); + if (!name) + return namelen; + if ((p + namelen + 1) <= buflen) { + memcpy(buf + p, name, namelen); + p += namelen; + buf[p++] = '/'; + pdepth++; + } + } + + if (offset == nodeoffset) { + if (pdepth < (depth + 1)) + return -FDT_ERR_NOSPACE; + + if (p > 1) /* special case so that root path is "/", not "" */ + p--; + buf[p] = '\0'; + return 0; + } + } + + if ((offset == -FDT_ERR_NOTFOUND) || (offset >= 0)) + return -FDT_ERR_BADOFFSET; + else if (offset == -FDT_ERR_BADOFFSET) + return -FDT_ERR_BADSTRUCTURE; + + return offset; /* error from fdt_next_node() */ +} + +int fdt_supernode_atdepth_offset(const void *fdt, int nodeoffset, + int supernodedepth, int *nodedepth) +{ + int offset, depth; + int supernodeoffset = -FDT_ERR_INTERNAL; + + FDT_RO_PROBE(fdt); + + if (supernodedepth < 0) + return -FDT_ERR_NOTFOUND; + + for (offset = 0, depth = 0; + (offset >= 0) && (offset <= nodeoffset); + offset = fdt_next_node(fdt, offset, &depth)) { + if (depth == supernodedepth) + supernodeoffset = offset; + + if (offset == nodeoffset) { + if (nodedepth) + *nodedepth = depth; + + if (supernodedepth > depth) + return -FDT_ERR_NOTFOUND; + else + return supernodeoffset; + } + } + + if ((offset == -FDT_ERR_NOTFOUND) || (offset >= 0)) + return -FDT_ERR_BADOFFSET; + else if (offset == -FDT_ERR_BADOFFSET) + return -FDT_ERR_BADSTRUCTURE; + + return offset; /* error from fdt_next_node() */ +} + +int fdt_node_depth(const void *fdt, int nodeoffset) +{ + int nodedepth; + int err; + + err = fdt_supernode_atdepth_offset(fdt, nodeoffset, 0, &nodedepth); + if (err) + return (err < 0) ? err : -FDT_ERR_INTERNAL; + return nodedepth; +} + +int fdt_parent_offset(const void *fdt, int nodeoffset) +{ + int nodedepth = fdt_node_depth(fdt, nodeoffset); + + if (nodedepth < 0) + return nodedepth; + return fdt_supernode_atdepth_offset(fdt, nodeoffset, + nodedepth - 1, NULL); +} + +int fdt_node_offset_by_prop_value(const void *fdt, int startoffset, + const char *propname, + const void *propval, int proplen) +{ + int offset; + const void *val; + int len; + + FDT_RO_PROBE(fdt); + + /* FIXME: The algorithm here is pretty horrible: we scan each + * property of a node in fdt_getprop(), then if that didn't + * find what we want, we scan over them again making our way + * to the next node. Still it's the easiest to implement + * approach; performance can come later. */ + for (offset = fdt_next_node(fdt, startoffset, NULL); + offset >= 0; + offset = fdt_next_node(fdt, offset, NULL)) { + val = fdt_getprop(fdt, offset, propname, &len); + if (val && (len == proplen) + && (memcmp(val, propval, len) == 0)) + return offset; + } + + return offset; /* error from fdt_next_node() */ +} + +int fdt_node_offset_by_phandle(const void *fdt, uint32_t phandle) +{ + int offset; + + if ((phandle == 0) || (phandle == -1)) + return -FDT_ERR_BADPHANDLE; + + FDT_RO_PROBE(fdt); + + /* FIXME: The algorithm here is pretty horrible: we + * potentially scan each property of a node in + * fdt_get_phandle(), then if that didn't find what + * we want, we scan over them again making our way to the next + * node. Still it's the easiest to implement approach; + * performance can come later. */ + for (offset = fdt_next_node(fdt, -1, NULL); + offset >= 0; + offset = fdt_next_node(fdt, offset, NULL)) { + if (fdt_get_phandle(fdt, offset) == phandle) + return offset; + } + + return offset; /* error from fdt_next_node() */ +} + +int fdt_stringlist_contains(const char *strlist, int listlen, const char *str) +{ + int len = strlen(str); + const char *p; + + while (listlen >= len) { + if (memcmp(str, strlist, len+1) == 0) + return 1; + p = memchr(strlist, '\0', listlen); + if (!p) + return 0; /* malformed strlist.. */ + listlen -= (p-strlist) + 1; + strlist = p + 1; + } + return 0; +} + +int fdt_stringlist_count(const void *fdt, int nodeoffset, const char *property) +{ + const char *list, *end; + int length, count = 0; + + list = fdt_getprop(fdt, nodeoffset, property, &length); + if (!list) + return length; + + end = list + length; + + while (list < end) { + length = strnlen(list, end - list) + 1; + + /* Abort if the last string isn't properly NUL-terminated. */ + if (list + length > end) + return -FDT_ERR_BADVALUE; + + list += length; + count++; + } + + return count; +} + +int fdt_stringlist_search(const void *fdt, int nodeoffset, const char *property, + const char *string) +{ + int length, len, idx = 0; + const char *list, *end; + + list = fdt_getprop(fdt, nodeoffset, property, &length); + if (!list) + return length; + + len = strlen(string) + 1; + end = list + length; + + while (list < end) { + length = strnlen(list, end - list) + 1; + + /* Abort if the last string isn't properly NUL-terminated. */ + if (list + length > end) + return -FDT_ERR_BADVALUE; + + if (length == len && memcmp(list, string, length) == 0) + return idx; + + list += length; + idx++; + } + + return -FDT_ERR_NOTFOUND; +} + +const char *fdt_stringlist_get(const void *fdt, int nodeoffset, + const char *property, int idx, + int *lenp) +{ + const char *list, *end; + int length; + + list = fdt_getprop(fdt, nodeoffset, property, &length); + if (!list) { + if (lenp) + *lenp = length; + + return NULL; + } + + end = list + length; + + while (list < end) { + length = strnlen(list, end - list) + 1; + + /* Abort if the last string isn't properly NUL-terminated. */ + if (list + length > end) { + if (lenp) + *lenp = -FDT_ERR_BADVALUE; + + return NULL; + } + + if (idx == 0) { + if (lenp) + *lenp = length - 1; + + return list; + } + + list += length; + idx--; + } + + if (lenp) + *lenp = -FDT_ERR_NOTFOUND; + + return NULL; +} + +int fdt_node_check_compatible(const void *fdt, int nodeoffset, + const char *compatible) +{ + const void *prop; + int len; + + prop = fdt_getprop(fdt, nodeoffset, "compatible", &len); + if (!prop) + return len; + + return !fdt_stringlist_contains(prop, len, compatible); +} + +int fdt_node_offset_by_compatible(const void *fdt, int startoffset, + const char *compatible) +{ + int offset, err; + + FDT_RO_PROBE(fdt); + + /* FIXME: The algorithm here is pretty horrible: we scan each + * property of a node in fdt_node_check_compatible(), then if + * that didn't find what we want, we scan over them again + * making our way to the next node. Still it's the easiest to + * implement approach; performance can come later. */ + for (offset = fdt_next_node(fdt, startoffset, NULL); + offset >= 0; + offset = fdt_next_node(fdt, offset, NULL)) { + err = fdt_node_check_compatible(fdt, offset, compatible); + if ((err < 0) && (err != -FDT_ERR_NOTFOUND)) + return err; + else if (err == 0) + return offset; + } + + return offset; /* error from fdt_next_node() */ +} + +int fdt_check_full(const void *fdt, size_t bufsize) +{ + int err; + int num_memrsv; + int offset, nextoffset = 0; + uint32_t tag; + unsigned depth = 0; + const void *prop; + const char *propname; + + if (bufsize < FDT_V1_SIZE) + return -FDT_ERR_TRUNCATED; + err = fdt_check_header(fdt); + if (err != 0) + return err; + if (bufsize < fdt_totalsize(fdt)) + return -FDT_ERR_TRUNCATED; + + num_memrsv = fdt_num_mem_rsv(fdt); + if (num_memrsv < 0) + return num_memrsv; + + while (1) { + offset = nextoffset; + tag = fdt_next_tag(fdt, offset, &nextoffset); + + if (nextoffset < 0) + return nextoffset; + + switch (tag) { + case FDT_NOP: + break; + + case FDT_END: + if (depth != 0) + return -FDT_ERR_BADSTRUCTURE; + return 0; + + case FDT_BEGIN_NODE: + depth++; + if (depth > INT_MAX) + return -FDT_ERR_BADSTRUCTURE; + break; + + case FDT_END_NODE: + if (depth == 0) + return -FDT_ERR_BADSTRUCTURE; + depth--; + break; + + case FDT_PROP: + prop = fdt_getprop_by_offset(fdt, offset, &propname, + &err); + if (!prop) + return err; + break; + + default: + return -FDT_ERR_INTERNAL; + } + } +} diff --git a/vendor/riscv/riscv-isa-sim/fdt/fdt_rw.c b/vendor/riscv/riscv-isa-sim/fdt/fdt_rw.c new file mode 100644 index 0000000000..8795947c00 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/fdt/fdt_rw.c @@ -0,0 +1,476 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * libfdt - Flat Device Tree manipulation + * Copyright (C) 2006 David Gibson, IBM Corporation. + */ +#include "libfdt_env.h" + +#include <fdt.h> +#include <libfdt.h> + +#include "libfdt_internal.h" + +static int fdt_blocks_misordered_(const void *fdt, + int mem_rsv_size, int struct_size) +{ + return (fdt_off_mem_rsvmap(fdt) < FDT_ALIGN(sizeof(struct fdt_header), 8)) + || (fdt_off_dt_struct(fdt) < + (fdt_off_mem_rsvmap(fdt) + mem_rsv_size)) + || (fdt_off_dt_strings(fdt) < + (fdt_off_dt_struct(fdt) + struct_size)) + || (fdt_totalsize(fdt) < + (fdt_off_dt_strings(fdt) + fdt_size_dt_strings(fdt))); +} + +static int fdt_rw_probe_(void *fdt) +{ + FDT_RO_PROBE(fdt); + + if (fdt_version(fdt) < 17) + return -FDT_ERR_BADVERSION; + if (fdt_blocks_misordered_(fdt, sizeof(struct fdt_reserve_entry), + fdt_size_dt_struct(fdt))) + return -FDT_ERR_BADLAYOUT; + if (fdt_version(fdt) > 17) + fdt_set_version(fdt, 17); + + return 0; +} + +#define FDT_RW_PROBE(fdt) \ + { \ + int err_; \ + if ((err_ = fdt_rw_probe_(fdt)) != 0) \ + return err_; \ + } + +static inline int fdt_data_size_(void *fdt) +{ + return fdt_off_dt_strings(fdt) + fdt_size_dt_strings(fdt); +} + +static int fdt_splice_(void *fdt, void *splicepoint, int oldlen, int newlen) +{ + char *p = splicepoint; + char *end = (char *)fdt + fdt_data_size_(fdt); + + if (((p + oldlen) < p) || ((p + oldlen) > end)) + return -FDT_ERR_BADOFFSET; + if ((p < (char *)fdt) || ((end - oldlen + newlen) < (char *)fdt)) + return -FDT_ERR_BADOFFSET; + if ((end - oldlen + newlen) > ((char *)fdt + fdt_totalsize(fdt))) + return -FDT_ERR_NOSPACE; + memmove(p + newlen, p + oldlen, end - p - oldlen); + return 0; +} + +static int fdt_splice_mem_rsv_(void *fdt, struct fdt_reserve_entry *p, + int oldn, int newn) +{ + int delta = (newn - oldn) * sizeof(*p); + int err; + err = fdt_splice_(fdt, p, oldn * sizeof(*p), newn * sizeof(*p)); + if (err) + return err; + fdt_set_off_dt_struct(fdt, fdt_off_dt_struct(fdt) + delta); + fdt_set_off_dt_strings(fdt, fdt_off_dt_strings(fdt) + delta); + return 0; +} + +static int fdt_splice_struct_(void *fdt, void *p, + int oldlen, int newlen) +{ + int delta = newlen - oldlen; + int err; + + if ((err = fdt_splice_(fdt, p, oldlen, newlen))) + return err; + + fdt_set_size_dt_struct(fdt, fdt_size_dt_struct(fdt) + delta); + fdt_set_off_dt_strings(fdt, fdt_off_dt_strings(fdt) + delta); + return 0; +} + +/* Must only be used to roll back in case of error */ +static void fdt_del_last_string_(void *fdt, const char *s) +{ + int newlen = strlen(s) + 1; + + fdt_set_size_dt_strings(fdt, fdt_size_dt_strings(fdt) - newlen); +} + +static int fdt_splice_string_(void *fdt, int newlen) +{ + void *p = (char *)fdt + + fdt_off_dt_strings(fdt) + fdt_size_dt_strings(fdt); + int err; + + if ((err = fdt_splice_(fdt, p, 0, newlen))) + return err; + + fdt_set_size_dt_strings(fdt, fdt_size_dt_strings(fdt) + newlen); + return 0; +} + +static int fdt_find_add_string_(void *fdt, const char *s, int *allocated) +{ + char *strtab = (char *)fdt + fdt_off_dt_strings(fdt); + const char *p; + char *new; + int len = strlen(s) + 1; + int err; + + *allocated = 0; + + p = fdt_find_string_(strtab, fdt_size_dt_strings(fdt), s); + if (p) + /* found it */ + return (p - strtab); + + new = strtab + fdt_size_dt_strings(fdt); + err = fdt_splice_string_(fdt, len); + if (err) + return err; + + *allocated = 1; + + memcpy(new, s, len); + return (new - strtab); +} + +int fdt_add_mem_rsv(void *fdt, uint64_t address, uint64_t size) +{ + struct fdt_reserve_entry *re; + int err; + + FDT_RW_PROBE(fdt); + + re = fdt_mem_rsv_w_(fdt, fdt_num_mem_rsv(fdt)); + err = fdt_splice_mem_rsv_(fdt, re, 0, 1); + if (err) + return err; + + re->address = cpu_to_fdt64(address); + re->size = cpu_to_fdt64(size); + return 0; +} + +int fdt_del_mem_rsv(void *fdt, int n) +{ + struct fdt_reserve_entry *re = fdt_mem_rsv_w_(fdt, n); + + FDT_RW_PROBE(fdt); + + if (n >= fdt_num_mem_rsv(fdt)) + return -FDT_ERR_NOTFOUND; + + return fdt_splice_mem_rsv_(fdt, re, 1, 0); +} + +static int fdt_resize_property_(void *fdt, int nodeoffset, const char *name, + int len, struct fdt_property **prop) +{ + int oldlen; + int err; + + *prop = fdt_get_property_w(fdt, nodeoffset, name, &oldlen); + if (!*prop) + return oldlen; + + if ((err = fdt_splice_struct_(fdt, (*prop)->data, FDT_TAGALIGN(oldlen), + FDT_TAGALIGN(len)))) + return err; + + (*prop)->len = cpu_to_fdt32(len); + return 0; +} + +static int fdt_add_property_(void *fdt, int nodeoffset, const char *name, + int len, struct fdt_property **prop) +{ + int proplen; + int nextoffset; + int namestroff; + int err; + int allocated; + + if ((nextoffset = fdt_check_node_offset_(fdt, nodeoffset)) < 0) + return nextoffset; + + namestroff = fdt_find_add_string_(fdt, name, &allocated); + if (namestroff < 0) + return namestroff; + + *prop = fdt_offset_ptr_w_(fdt, nextoffset); + proplen = sizeof(**prop) + FDT_TAGALIGN(len); + + err = fdt_splice_struct_(fdt, *prop, 0, proplen); + if (err) { + if (allocated) + fdt_del_last_string_(fdt, name); + return err; + } + + (*prop)->tag = cpu_to_fdt32(FDT_PROP); + (*prop)->nameoff = cpu_to_fdt32(namestroff); + (*prop)->len = cpu_to_fdt32(len); + return 0; +} + +int fdt_set_name(void *fdt, int nodeoffset, const char *name) +{ + char *namep; + int oldlen, newlen; + int err; + + FDT_RW_PROBE(fdt); + + namep = (char *)(uintptr_t)fdt_get_name(fdt, nodeoffset, &oldlen); + if (!namep) + return oldlen; + + newlen = strlen(name); + + err = fdt_splice_struct_(fdt, namep, FDT_TAGALIGN(oldlen+1), + FDT_TAGALIGN(newlen+1)); + if (err) + return err; + + memcpy(namep, name, newlen+1); + return 0; +} + +int fdt_setprop_placeholder(void *fdt, int nodeoffset, const char *name, + int len, void **prop_data) +{ + struct fdt_property *prop; + int err; + + FDT_RW_PROBE(fdt); + + err = fdt_resize_property_(fdt, nodeoffset, name, len, &prop); + if (err == -FDT_ERR_NOTFOUND) + err = fdt_add_property_(fdt, nodeoffset, name, len, &prop); + if (err) + return err; + + *prop_data = prop->data; + return 0; +} + +int fdt_setprop(void *fdt, int nodeoffset, const char *name, + const void *val, int len) +{ + void *prop_data; + int err; + + err = fdt_setprop_placeholder(fdt, nodeoffset, name, len, &prop_data); + if (err) + return err; + + if (len) + memcpy(prop_data, val, len); + return 0; +} + +int fdt_appendprop(void *fdt, int nodeoffset, const char *name, + const void *val, int len) +{ + struct fdt_property *prop; + int err, oldlen, newlen; + + FDT_RW_PROBE(fdt); + + prop = fdt_get_property_w(fdt, nodeoffset, name, &oldlen); + if (prop) { + newlen = len + oldlen; + err = fdt_splice_struct_(fdt, prop->data, + FDT_TAGALIGN(oldlen), + FDT_TAGALIGN(newlen)); + if (err) + return err; + prop->len = cpu_to_fdt32(newlen); + memcpy(prop->data + oldlen, val, len); + } else { + err = fdt_add_property_(fdt, nodeoffset, name, len, &prop); + if (err) + return err; + memcpy(prop->data, val, len); + } + return 0; +} + +int fdt_delprop(void *fdt, int nodeoffset, const char *name) +{ + struct fdt_property *prop; + int len, proplen; + + FDT_RW_PROBE(fdt); + + prop = fdt_get_property_w(fdt, nodeoffset, name, &len); + if (!prop) + return len; + + proplen = sizeof(*prop) + FDT_TAGALIGN(len); + return fdt_splice_struct_(fdt, prop, proplen, 0); +} + +int fdt_add_subnode_namelen(void *fdt, int parentoffset, + const char *name, int namelen) +{ + struct fdt_node_header *nh; + int offset, nextoffset; + int nodelen; + int err; + uint32_t tag; + fdt32_t *endtag; + + FDT_RW_PROBE(fdt); + + offset = fdt_subnode_offset_namelen(fdt, parentoffset, name, namelen); + if (offset >= 0) + return -FDT_ERR_EXISTS; + else if (offset != -FDT_ERR_NOTFOUND) + return offset; + + /* Try to place the new node after the parent's properties */ + fdt_next_tag(fdt, parentoffset, &nextoffset); /* skip the BEGIN_NODE */ + do { + offset = nextoffset; + tag = fdt_next_tag(fdt, offset, &nextoffset); + } while ((tag == FDT_PROP) || (tag == FDT_NOP)); + + nh = fdt_offset_ptr_w_(fdt, offset); + nodelen = sizeof(*nh) + FDT_TAGALIGN(namelen+1) + FDT_TAGSIZE; + + err = fdt_splice_struct_(fdt, nh, 0, nodelen); + if (err) + return err; + + nh->tag = cpu_to_fdt32(FDT_BEGIN_NODE); + memset(nh->name, 0, FDT_TAGALIGN(namelen+1)); + memcpy(nh->name, name, namelen); + endtag = (fdt32_t *)((char *)nh + nodelen - FDT_TAGSIZE); + *endtag = cpu_to_fdt32(FDT_END_NODE); + + return offset; +} + +int fdt_add_subnode(void *fdt, int parentoffset, const char *name) +{ + return fdt_add_subnode_namelen(fdt, parentoffset, name, strlen(name)); +} + +int fdt_del_node(void *fdt, int nodeoffset) +{ + int endoffset; + + FDT_RW_PROBE(fdt); + + endoffset = fdt_node_end_offset_(fdt, nodeoffset); + if (endoffset < 0) + return endoffset; + + return fdt_splice_struct_(fdt, fdt_offset_ptr_w_(fdt, nodeoffset), + endoffset - nodeoffset, 0); +} + +static void fdt_packblocks_(const char *old, char *new, + int mem_rsv_size, int struct_size) +{ + int mem_rsv_off, struct_off, strings_off; + + mem_rsv_off = FDT_ALIGN(sizeof(struct fdt_header), 8); + struct_off = mem_rsv_off + mem_rsv_size; + strings_off = struct_off + struct_size; + + memmove(new + mem_rsv_off, old + fdt_off_mem_rsvmap(old), mem_rsv_size); + fdt_set_off_mem_rsvmap(new, mem_rsv_off); + + memmove(new + struct_off, old + fdt_off_dt_struct(old), struct_size); + fdt_set_off_dt_struct(new, struct_off); + fdt_set_size_dt_struct(new, struct_size); + + memmove(new + strings_off, old + fdt_off_dt_strings(old), + fdt_size_dt_strings(old)); + fdt_set_off_dt_strings(new, strings_off); + fdt_set_size_dt_strings(new, fdt_size_dt_strings(old)); +} + +int fdt_open_into(const void *fdt, void *buf, int bufsize) +{ + int err; + int mem_rsv_size, struct_size; + int newsize; + const char *fdtstart = fdt; + const char *fdtend = fdtstart + fdt_totalsize(fdt); + char *tmp; + + FDT_RO_PROBE(fdt); + + mem_rsv_size = (fdt_num_mem_rsv(fdt)+1) + * sizeof(struct fdt_reserve_entry); + + if (fdt_version(fdt) >= 17) { + struct_size = fdt_size_dt_struct(fdt); + } else { + struct_size = 0; + while (fdt_next_tag(fdt, struct_size, &struct_size) != FDT_END) + ; + if (struct_size < 0) + return struct_size; + } + + if (!fdt_blocks_misordered_(fdt, mem_rsv_size, struct_size)) { + /* no further work necessary */ + err = fdt_move(fdt, buf, bufsize); + if (err) + return err; + fdt_set_version(buf, 17); + fdt_set_size_dt_struct(buf, struct_size); + fdt_set_totalsize(buf, bufsize); + return 0; + } + + /* Need to reorder */ + newsize = FDT_ALIGN(sizeof(struct fdt_header), 8) + mem_rsv_size + + struct_size + fdt_size_dt_strings(fdt); + + if (bufsize < newsize) + return -FDT_ERR_NOSPACE; + + /* First attempt to build converted tree at beginning of buffer */ + tmp = buf; + /* But if that overlaps with the old tree... */ + if (((tmp + newsize) > fdtstart) && (tmp < fdtend)) { + /* Try right after the old tree instead */ + tmp = (char *)(uintptr_t)fdtend; + if ((tmp + newsize) > ((char *)buf + bufsize)) + return -FDT_ERR_NOSPACE; + } + + fdt_packblocks_(fdt, tmp, mem_rsv_size, struct_size); + memmove(buf, tmp, newsize); + + fdt_set_magic(buf, FDT_MAGIC); + fdt_set_totalsize(buf, bufsize); + fdt_set_version(buf, 17); + fdt_set_last_comp_version(buf, 16); + fdt_set_boot_cpuid_phys(buf, fdt_boot_cpuid_phys(fdt)); + + return 0; +} + +int fdt_pack(void *fdt) +{ + int mem_rsv_size; + + FDT_RW_PROBE(fdt); + + mem_rsv_size = (fdt_num_mem_rsv(fdt)+1) + * sizeof(struct fdt_reserve_entry); + fdt_packblocks_(fdt, fdt, mem_rsv_size, fdt_size_dt_struct(fdt)); + fdt_set_totalsize(fdt, fdt_data_size_(fdt)); + + return 0; +} diff --git a/vendor/riscv/riscv-isa-sim/fdt/fdt_strerror.c b/vendor/riscv/riscv-isa-sim/fdt/fdt_strerror.c new file mode 100644 index 0000000000..768db66ead --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/fdt/fdt_strerror.c @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * libfdt - Flat Device Tree manipulation + * Copyright (C) 2006 David Gibson, IBM Corporation. + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "libfdt_env.h" + +#include <fdt.h> +#include <libfdt.h> + +#include "libfdt_internal.h" + +struct fdt_errtabent { + const char *str; +}; + +#define FDT_ERRTABENT(val) \ + [(val)] = { .str = #val, } + +static struct fdt_errtabent fdt_errtable[] = { + FDT_ERRTABENT(FDT_ERR_NOTFOUND), + FDT_ERRTABENT(FDT_ERR_EXISTS), + FDT_ERRTABENT(FDT_ERR_NOSPACE), + + FDT_ERRTABENT(FDT_ERR_BADOFFSET), + FDT_ERRTABENT(FDT_ERR_BADPATH), + FDT_ERRTABENT(FDT_ERR_BADPHANDLE), + FDT_ERRTABENT(FDT_ERR_BADSTATE), + + FDT_ERRTABENT(FDT_ERR_TRUNCATED), + FDT_ERRTABENT(FDT_ERR_BADMAGIC), + FDT_ERRTABENT(FDT_ERR_BADVERSION), + FDT_ERRTABENT(FDT_ERR_BADSTRUCTURE), + FDT_ERRTABENT(FDT_ERR_BADLAYOUT), + FDT_ERRTABENT(FDT_ERR_INTERNAL), + FDT_ERRTABENT(FDT_ERR_BADNCELLS), + FDT_ERRTABENT(FDT_ERR_BADVALUE), + FDT_ERRTABENT(FDT_ERR_BADOVERLAY), + FDT_ERRTABENT(FDT_ERR_NOPHANDLES), + FDT_ERRTABENT(FDT_ERR_BADFLAGS), +}; +#define FDT_ERRTABSIZE (sizeof(fdt_errtable) / sizeof(fdt_errtable[0])) + +const char *fdt_strerror(int errval) +{ + if (errval > 0) + return "<valid offset/length>"; + else if (errval == 0) + return "<no error>"; + else if (errval > -FDT_ERRTABSIZE) { + const char *s = fdt_errtable[-errval].str; + + if (s) + return s; + } + + return "<unknown error>"; +} diff --git a/vendor/riscv/riscv-isa-sim/fdt/fdt_sw.c b/vendor/riscv/riscv-isa-sim/fdt/fdt_sw.c new file mode 100644 index 0000000000..76bea22f73 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/fdt/fdt_sw.c @@ -0,0 +1,376 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * libfdt - Flat Device Tree manipulation + * Copyright (C) 2006 David Gibson, IBM Corporation. + */ +#include "libfdt_env.h" + +#include <fdt.h> +#include <libfdt.h> + +#include "libfdt_internal.h" + +static int fdt_sw_probe_(void *fdt) +{ + if (fdt_magic(fdt) == FDT_MAGIC) + return -FDT_ERR_BADSTATE; + else if (fdt_magic(fdt) != FDT_SW_MAGIC) + return -FDT_ERR_BADMAGIC; + return 0; +} + +#define FDT_SW_PROBE(fdt) \ + { \ + int err; \ + if ((err = fdt_sw_probe_(fdt)) != 0) \ + return err; \ + } + +/* 'memrsv' state: Initial state after fdt_create() + * + * Allowed functions: + * fdt_add_reservmap_entry() + * fdt_finish_reservemap() [moves to 'struct' state] + */ +static int fdt_sw_probe_memrsv_(void *fdt) +{ + int err = fdt_sw_probe_(fdt); + if (err) + return err; + + if (fdt_off_dt_strings(fdt) != 0) + return -FDT_ERR_BADSTATE; + return 0; +} + +#define FDT_SW_PROBE_MEMRSV(fdt) \ + { \ + int err; \ + if ((err = fdt_sw_probe_memrsv_(fdt)) != 0) \ + return err; \ + } + +/* 'struct' state: Enter this state after fdt_finish_reservemap() + * + * Allowed functions: + * fdt_begin_node() + * fdt_end_node() + * fdt_property*() + * fdt_finish() [moves to 'complete' state] + */ +static int fdt_sw_probe_struct_(void *fdt) +{ + int err = fdt_sw_probe_(fdt); + if (err) + return err; + + if (fdt_off_dt_strings(fdt) != fdt_totalsize(fdt)) + return -FDT_ERR_BADSTATE; + return 0; +} + +#define FDT_SW_PROBE_STRUCT(fdt) \ + { \ + int err; \ + if ((err = fdt_sw_probe_struct_(fdt)) != 0) \ + return err; \ + } + +static inline uint32_t sw_flags(void *fdt) +{ + /* assert: (fdt_magic(fdt) == FDT_SW_MAGIC) */ + return fdt_last_comp_version(fdt); +} + +/* 'complete' state: Enter this state after fdt_finish() + * + * Allowed functions: none + */ + +static void *fdt_grab_space_(void *fdt, size_t len) +{ + int offset = fdt_size_dt_struct(fdt); + int spaceleft; + + spaceleft = fdt_totalsize(fdt) - fdt_off_dt_struct(fdt) + - fdt_size_dt_strings(fdt); + + if ((offset + len < offset) || (offset + len > spaceleft)) + return NULL; + + fdt_set_size_dt_struct(fdt, offset + len); + return fdt_offset_ptr_w_(fdt, offset); +} + +int fdt_create_with_flags(void *buf, int bufsize, uint32_t flags) +{ + const size_t hdrsize = FDT_ALIGN(sizeof(struct fdt_header), + sizeof(struct fdt_reserve_entry)); + void *fdt = buf; + + if (bufsize < hdrsize) + return -FDT_ERR_NOSPACE; + + if (flags & ~FDT_CREATE_FLAGS_ALL) + return -FDT_ERR_BADFLAGS; + + memset(buf, 0, bufsize); + + /* + * magic and last_comp_version keep intermediate state during the fdt + * creation process, which is replaced with the proper FDT format by + * fdt_finish(). + * + * flags should be accessed with sw_flags(). + */ + fdt_set_magic(fdt, FDT_SW_MAGIC); + fdt_set_version(fdt, FDT_LAST_SUPPORTED_VERSION); + fdt_set_last_comp_version(fdt, flags); + + fdt_set_totalsize(fdt, bufsize); + + fdt_set_off_mem_rsvmap(fdt, hdrsize); + fdt_set_off_dt_struct(fdt, fdt_off_mem_rsvmap(fdt)); + fdt_set_off_dt_strings(fdt, 0); + + return 0; +} + +int fdt_create(void *buf, int bufsize) +{ + return fdt_create_with_flags(buf, bufsize, 0); +} + +int fdt_resize(void *fdt, void *buf, int bufsize) +{ + size_t headsize, tailsize; + char *oldtail, *newtail; + + FDT_SW_PROBE(fdt); + + headsize = fdt_off_dt_struct(fdt) + fdt_size_dt_struct(fdt); + tailsize = fdt_size_dt_strings(fdt); + + if ((headsize + tailsize) > fdt_totalsize(fdt)) + return -FDT_ERR_INTERNAL; + + if ((headsize + tailsize) > bufsize) + return -FDT_ERR_NOSPACE; + + oldtail = (char *)fdt + fdt_totalsize(fdt) - tailsize; + newtail = (char *)buf + bufsize - tailsize; + + /* Two cases to avoid clobbering data if the old and new + * buffers partially overlap */ + if (buf <= fdt) { + memmove(buf, fdt, headsize); + memmove(newtail, oldtail, tailsize); + } else { + memmove(newtail, oldtail, tailsize); + memmove(buf, fdt, headsize); + } + + fdt_set_totalsize(buf, bufsize); + if (fdt_off_dt_strings(buf)) + fdt_set_off_dt_strings(buf, bufsize); + + return 0; +} + +int fdt_add_reservemap_entry(void *fdt, uint64_t addr, uint64_t size) +{ + struct fdt_reserve_entry *re; + int offset; + + FDT_SW_PROBE_MEMRSV(fdt); + + offset = fdt_off_dt_struct(fdt); + if ((offset + sizeof(*re)) > fdt_totalsize(fdt)) + return -FDT_ERR_NOSPACE; + + re = (struct fdt_reserve_entry *)((char *)fdt + offset); + re->address = cpu_to_fdt64(addr); + re->size = cpu_to_fdt64(size); + + fdt_set_off_dt_struct(fdt, offset + sizeof(*re)); + + return 0; +} + +int fdt_finish_reservemap(void *fdt) +{ + int err = fdt_add_reservemap_entry(fdt, 0, 0); + + if (err) + return err; + + fdt_set_off_dt_strings(fdt, fdt_totalsize(fdt)); + return 0; +} + +int fdt_begin_node(void *fdt, const char *name) +{ + struct fdt_node_header *nh; + int namelen; + + FDT_SW_PROBE_STRUCT(fdt); + + namelen = strlen(name) + 1; + nh = fdt_grab_space_(fdt, sizeof(*nh) + FDT_TAGALIGN(namelen)); + if (! nh) + return -FDT_ERR_NOSPACE; + + nh->tag = cpu_to_fdt32(FDT_BEGIN_NODE); + memcpy(nh->name, name, namelen); + return 0; +} + +int fdt_end_node(void *fdt) +{ + fdt32_t *en; + + FDT_SW_PROBE_STRUCT(fdt); + + en = fdt_grab_space_(fdt, FDT_TAGSIZE); + if (! en) + return -FDT_ERR_NOSPACE; + + *en = cpu_to_fdt32(FDT_END_NODE); + return 0; +} + +static int fdt_add_string_(void *fdt, const char *s) +{ + char *strtab = (char *)fdt + fdt_totalsize(fdt); + int strtabsize = fdt_size_dt_strings(fdt); + int len = strlen(s) + 1; + int struct_top, offset; + + offset = -strtabsize - len; + struct_top = fdt_off_dt_struct(fdt) + fdt_size_dt_struct(fdt); + if (fdt_totalsize(fdt) + offset < struct_top) + return 0; /* no more room :( */ + + memcpy(strtab + offset, s, len); + fdt_set_size_dt_strings(fdt, strtabsize + len); + return offset; +} + +/* Must only be used to roll back in case of error */ +static void fdt_del_last_string_(void *fdt, const char *s) +{ + int strtabsize = fdt_size_dt_strings(fdt); + int len = strlen(s) + 1; + + fdt_set_size_dt_strings(fdt, strtabsize - len); +} + +static int fdt_find_add_string_(void *fdt, const char *s, int *allocated) +{ + char *strtab = (char *)fdt + fdt_totalsize(fdt); + int strtabsize = fdt_size_dt_strings(fdt); + const char *p; + + *allocated = 0; + + p = fdt_find_string_(strtab - strtabsize, strtabsize, s); + if (p) + return p - strtab; + + *allocated = 1; + + return fdt_add_string_(fdt, s); +} + +int fdt_property_placeholder(void *fdt, const char *name, int len, void **valp) +{ + struct fdt_property *prop; + int nameoff; + int allocated; + + FDT_SW_PROBE_STRUCT(fdt); + + /* String de-duplication can be slow, _NO_NAME_DEDUP skips it */ + if (sw_flags(fdt) & FDT_CREATE_FLAG_NO_NAME_DEDUP) { + allocated = 1; + nameoff = fdt_add_string_(fdt, name); + } else { + nameoff = fdt_find_add_string_(fdt, name, &allocated); + } + if (nameoff == 0) + return -FDT_ERR_NOSPACE; + + prop = fdt_grab_space_(fdt, sizeof(*prop) + FDT_TAGALIGN(len)); + if (! prop) { + if (allocated) + fdt_del_last_string_(fdt, name); + return -FDT_ERR_NOSPACE; + } + + prop->tag = cpu_to_fdt32(FDT_PROP); + prop->nameoff = cpu_to_fdt32(nameoff); + prop->len = cpu_to_fdt32(len); + *valp = prop->data; + return 0; +} + +int fdt_property(void *fdt, const char *name, const void *val, int len) +{ + void *ptr; + int ret; + + ret = fdt_property_placeholder(fdt, name, len, &ptr); + if (ret) + return ret; + memcpy(ptr, val, len); + return 0; +} + +int fdt_finish(void *fdt) +{ + char *p = (char *)fdt; + fdt32_t *end; + int oldstroffset, newstroffset; + uint32_t tag; + int offset, nextoffset; + + FDT_SW_PROBE_STRUCT(fdt); + + /* Add terminator */ + end = fdt_grab_space_(fdt, sizeof(*end)); + if (! end) + return -FDT_ERR_NOSPACE; + *end = cpu_to_fdt32(FDT_END); + + /* Relocate the string table */ + oldstroffset = fdt_totalsize(fdt) - fdt_size_dt_strings(fdt); + newstroffset = fdt_off_dt_struct(fdt) + fdt_size_dt_struct(fdt); + memmove(p + newstroffset, p + oldstroffset, fdt_size_dt_strings(fdt)); + fdt_set_off_dt_strings(fdt, newstroffset); + + /* Walk the structure, correcting string offsets */ + offset = 0; + while ((tag = fdt_next_tag(fdt, offset, &nextoffset)) != FDT_END) { + if (tag == FDT_PROP) { + struct fdt_property *prop = + fdt_offset_ptr_w_(fdt, offset); + int nameoff; + + nameoff = fdt32_to_cpu(prop->nameoff); + nameoff += fdt_size_dt_strings(fdt); + prop->nameoff = cpu_to_fdt32(nameoff); + } + offset = nextoffset; + } + if (nextoffset < 0) + return nextoffset; + + /* Finally, adjust the header */ + fdt_set_totalsize(fdt, newstroffset + fdt_size_dt_strings(fdt)); + + /* And fix up fields that were keeping intermediate state. */ + fdt_set_last_comp_version(fdt, FDT_FIRST_SUPPORTED_VERSION); + fdt_set_magic(fdt, FDT_MAGIC); + + return 0; +} diff --git a/vendor/riscv/riscv-isa-sim/fdt/fdt_wip.c b/vendor/riscv/riscv-isa-sim/fdt/fdt_wip.c new file mode 100644 index 0000000000..f64139e0b3 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/fdt/fdt_wip.c @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * libfdt - Flat Device Tree manipulation + * Copyright (C) 2006 David Gibson, IBM Corporation. + */ +#include "libfdt_env.h" + +#include <fdt.h> +#include <libfdt.h> + +#include "libfdt_internal.h" + +int fdt_setprop_inplace_namelen_partial(void *fdt, int nodeoffset, + const char *name, int namelen, + uint32_t idx, const void *val, + int len) +{ + void *propval; + int proplen; + + propval = fdt_getprop_namelen_w(fdt, nodeoffset, name, namelen, + &proplen); + if (!propval) + return proplen; + + if (proplen < (len + idx)) + return -FDT_ERR_NOSPACE; + + memcpy((char *)propval + idx, val, len); + return 0; +} + +int fdt_setprop_inplace(void *fdt, int nodeoffset, const char *name, + const void *val, int len) +{ + const void *propval; + int proplen; + + propval = fdt_getprop(fdt, nodeoffset, name, &proplen); + if (!propval) + return proplen; + + if (proplen != len) + return -FDT_ERR_NOSPACE; + + return fdt_setprop_inplace_namelen_partial(fdt, nodeoffset, name, + strlen(name), 0, + val, len); +} + +static void fdt_nop_region_(void *start, int len) +{ + fdt32_t *p; + + for (p = start; (char *)p < ((char *)start + len); p++) + *p = cpu_to_fdt32(FDT_NOP); +} + +int fdt_nop_property(void *fdt, int nodeoffset, const char *name) +{ + struct fdt_property *prop; + int len; + + prop = fdt_get_property_w(fdt, nodeoffset, name, &len); + if (!prop) + return len; + + fdt_nop_region_(prop, len + sizeof(*prop)); + + return 0; +} + +int fdt_node_end_offset_(void *fdt, int offset) +{ + int depth = 0; + + while ((offset >= 0) && (depth >= 0)) + offset = fdt_next_node(fdt, offset, &depth); + + return offset; +} + +int fdt_nop_node(void *fdt, int nodeoffset) +{ + int endoffset; + + endoffset = fdt_node_end_offset_(fdt, nodeoffset); + if (endoffset < 0) + return endoffset; + + fdt_nop_region_(fdt_offset_ptr_w(fdt, nodeoffset, 0), + endoffset - nodeoffset); + return 0; +} diff --git a/vendor/riscv/riscv-isa-sim/fdt/libfdt.h b/vendor/riscv/riscv-isa-sim/fdt/libfdt.h new file mode 100644 index 0000000000..d2356cce43 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/fdt/libfdt.h @@ -0,0 +1,2077 @@ +/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) */ +#ifndef LIBFDT_H +#define LIBFDT_H +/* + * libfdt - Flat Device Tree manipulation + * Copyright (C) 2006 David Gibson, IBM Corporation. + */ + +#include <libfdt_env.h> +#include <fdt.h> + +#define FDT_FIRST_SUPPORTED_VERSION 0x02 +#define FDT_LAST_SUPPORTED_VERSION 0x11 + +/* Error codes: informative error codes */ +#define FDT_ERR_NOTFOUND 1 + /* FDT_ERR_NOTFOUND: The requested node or property does not exist */ +#define FDT_ERR_EXISTS 2 + /* FDT_ERR_EXISTS: Attempted to create a node or property which + * already exists */ +#define FDT_ERR_NOSPACE 3 + /* FDT_ERR_NOSPACE: Operation needed to expand the device + * tree, but its buffer did not have sufficient space to + * contain the expanded tree. Use fdt_open_into() to move the + * device tree to a buffer with more space. */ + +/* Error codes: codes for bad parameters */ +#define FDT_ERR_BADOFFSET 4 + /* FDT_ERR_BADOFFSET: Function was passed a structure block + * offset which is out-of-bounds, or which points to an + * unsuitable part of the structure for the operation. */ +#define FDT_ERR_BADPATH 5 + /* FDT_ERR_BADPATH: Function was passed a badly formatted path + * (e.g. missing a leading / for a function which requires an + * absolute path) */ +#define FDT_ERR_BADPHANDLE 6 + /* FDT_ERR_BADPHANDLE: Function was passed an invalid phandle. + * This can be caused either by an invalid phandle property + * length, or the phandle value was either 0 or -1, which are + * not permitted. */ +#define FDT_ERR_BADSTATE 7 + /* FDT_ERR_BADSTATE: Function was passed an incomplete device + * tree created by the sequential-write functions, which is + * not sufficiently complete for the requested operation. */ + +/* Error codes: codes for bad device tree blobs */ +#define FDT_ERR_TRUNCATED 8 + /* FDT_ERR_TRUNCATED: FDT or a sub-block is improperly + * terminated (overflows, goes outside allowed bounds, or + * isn't properly terminated). */ +#define FDT_ERR_BADMAGIC 9 + /* FDT_ERR_BADMAGIC: Given "device tree" appears not to be a + * device tree at all - it is missing the flattened device + * tree magic number. */ +#define FDT_ERR_BADVERSION 10 + /* FDT_ERR_BADVERSION: Given device tree has a version which + * can't be handled by the requested operation. For + * read-write functions, this may mean that fdt_open_into() is + * required to convert the tree to the expected version. */ +#define FDT_ERR_BADSTRUCTURE 11 + /* FDT_ERR_BADSTRUCTURE: Given device tree has a corrupt + * structure block or other serious error (e.g. misnested + * nodes, or subnodes preceding properties). */ +#define FDT_ERR_BADLAYOUT 12 + /* FDT_ERR_BADLAYOUT: For read-write functions, the given + * device tree has it's sub-blocks in an order that the + * function can't handle (memory reserve map, then structure, + * then strings). Use fdt_open_into() to reorganize the tree + * into a form suitable for the read-write operations. */ + +/* "Can't happen" error indicating a bug in libfdt */ +#define FDT_ERR_INTERNAL 13 + /* FDT_ERR_INTERNAL: libfdt has failed an internal assertion. + * Should never be returned, if it is, it indicates a bug in + * libfdt itself. */ + +/* Errors in device tree content */ +#define FDT_ERR_BADNCELLS 14 + /* FDT_ERR_BADNCELLS: Device tree has a #address-cells, #size-cells + * or similar property with a bad format or value */ + +#define FDT_ERR_BADVALUE 15 + /* FDT_ERR_BADVALUE: Device tree has a property with an unexpected + * value. For example: a property expected to contain a string list + * is not NUL-terminated within the length of its value. */ + +#define FDT_ERR_BADOVERLAY 16 + /* FDT_ERR_BADOVERLAY: The device tree overlay, while + * correctly structured, cannot be applied due to some + * unexpected or missing value, property or node. */ + +#define FDT_ERR_NOPHANDLES 17 + /* FDT_ERR_NOPHANDLES: The device tree doesn't have any + * phandle available anymore without causing an overflow */ + +#define FDT_ERR_BADFLAGS 18 + /* FDT_ERR_BADFLAGS: The function was passed a flags field that + * contains invalid flags or an invalid combination of flags. */ + +#define FDT_ERR_MAX 18 + +/* constants */ +#define FDT_MAX_PHANDLE 0xfffffffe + /* Valid values for phandles range from 1 to 2^32-2. */ + +#ifdef __cplusplus +extern "C" { +#endif +/**********************************************************************/ +/* Low-level functions (you probably don't need these) */ +/**********************************************************************/ + +#ifndef SWIG /* This function is not useful in Python */ +const void *fdt_offset_ptr(const void *fdt, int offset, unsigned int checklen); +#endif +static inline void *fdt_offset_ptr_w(void *fdt, int offset, int checklen) +{ + return (void *)(uintptr_t)fdt_offset_ptr(fdt, offset, checklen); +} + +uint32_t fdt_next_tag(const void *fdt, int offset, int *nextoffset); + +/* + * Alignment helpers: + * These helpers access words from a device tree blob. They're + * built to work even with unaligned pointers on platforms (ike + * ARM) that don't like unaligned loads and stores + */ + +static inline uint32_t fdt32_ld(const fdt32_t *p) +{ + const uint8_t *bp = (const uint8_t *)p; + + return ((uint32_t)bp[0] << 24) + | ((uint32_t)bp[1] << 16) + | ((uint32_t)bp[2] << 8) + | bp[3]; +} + +static inline void fdt32_st(void *property, uint32_t value) +{ + uint8_t *bp = (uint8_t *)property; + + bp[0] = value >> 24; + bp[1] = (value >> 16) & 0xff; + bp[2] = (value >> 8) & 0xff; + bp[3] = value & 0xff; +} + +static inline uint64_t fdt64_ld(const fdt64_t *p) +{ + const uint8_t *bp = (const uint8_t *)p; + + return ((uint64_t)bp[0] << 56) + | ((uint64_t)bp[1] << 48) + | ((uint64_t)bp[2] << 40) + | ((uint64_t)bp[3] << 32) + | ((uint64_t)bp[4] << 24) + | ((uint64_t)bp[5] << 16) + | ((uint64_t)bp[6] << 8) + | bp[7]; +} + +static inline void fdt64_st(void *property, uint64_t value) +{ + uint8_t *bp = (uint8_t *)property; + + bp[0] = value >> 56; + bp[1] = (value >> 48) & 0xff; + bp[2] = (value >> 40) & 0xff; + bp[3] = (value >> 32) & 0xff; + bp[4] = (value >> 24) & 0xff; + bp[5] = (value >> 16) & 0xff; + bp[6] = (value >> 8) & 0xff; + bp[7] = value & 0xff; +} + +/**********************************************************************/ +/* Traversal functions */ +/**********************************************************************/ + +int fdt_next_node(const void *fdt, int offset, int *depth); + +/** + * fdt_first_subnode() - get offset of first direct subnode + * + * @fdt: FDT blob + * @offset: Offset of node to check + * @return offset of first subnode, or -FDT_ERR_NOTFOUND if there is none + */ +int fdt_first_subnode(const void *fdt, int offset); + +/** + * fdt_next_subnode() - get offset of next direct subnode + * + * After first calling fdt_first_subnode(), call this function repeatedly to + * get direct subnodes of a parent node. + * + * @fdt: FDT blob + * @offset: Offset of previous subnode + * @return offset of next subnode, or -FDT_ERR_NOTFOUND if there are no more + * subnodes + */ +int fdt_next_subnode(const void *fdt, int offset); + +/** + * fdt_for_each_subnode - iterate over all subnodes of a parent + * + * @node: child node (int, lvalue) + * @fdt: FDT blob (const void *) + * @parent: parent node (int) + * + * This is actually a wrapper around a for loop and would be used like so: + * + * fdt_for_each_subnode(node, fdt, parent) { + * Use node + * ... + * } + * + * if ((node < 0) && (node != -FDT_ERR_NOTFOUND)) { + * Error handling + * } + * + * Note that this is implemented as a macro and @node is used as + * iterator in the loop. The parent variable be constant or even a + * literal. + * + */ +#define fdt_for_each_subnode(node, fdt, parent) \ + for (node = fdt_first_subnode(fdt, parent); \ + node >= 0; \ + node = fdt_next_subnode(fdt, node)) + +/**********************************************************************/ +/* General functions */ +/**********************************************************************/ +#define fdt_get_header(fdt, field) \ + (fdt32_ld(&((const struct fdt_header *)(fdt))->field)) +#define fdt_magic(fdt) (fdt_get_header(fdt, magic)) +#define fdt_totalsize(fdt) (fdt_get_header(fdt, totalsize)) +#define fdt_off_dt_struct(fdt) (fdt_get_header(fdt, off_dt_struct)) +#define fdt_off_dt_strings(fdt) (fdt_get_header(fdt, off_dt_strings)) +#define fdt_off_mem_rsvmap(fdt) (fdt_get_header(fdt, off_mem_rsvmap)) +#define fdt_version(fdt) (fdt_get_header(fdt, version)) +#define fdt_last_comp_version(fdt) (fdt_get_header(fdt, last_comp_version)) +#define fdt_boot_cpuid_phys(fdt) (fdt_get_header(fdt, boot_cpuid_phys)) +#define fdt_size_dt_strings(fdt) (fdt_get_header(fdt, size_dt_strings)) +#define fdt_size_dt_struct(fdt) (fdt_get_header(fdt, size_dt_struct)) + +#define fdt_set_hdr_(name) \ + static inline void fdt_set_##name(void *fdt, uint32_t val) \ + { \ + struct fdt_header *fdth = (struct fdt_header *)fdt; \ + fdth->name = cpu_to_fdt32(val); \ + } +fdt_set_hdr_(magic); +fdt_set_hdr_(totalsize); +fdt_set_hdr_(off_dt_struct); +fdt_set_hdr_(off_dt_strings); +fdt_set_hdr_(off_mem_rsvmap); +fdt_set_hdr_(version); +fdt_set_hdr_(last_comp_version); +fdt_set_hdr_(boot_cpuid_phys); +fdt_set_hdr_(size_dt_strings); +fdt_set_hdr_(size_dt_struct); +#undef fdt_set_hdr_ + +/** + * fdt_header_size - return the size of the tree's header + * @fdt: pointer to a flattened device tree + */ +size_t fdt_header_size_(uint32_t version); +static inline size_t fdt_header_size(const void *fdt) +{ + return fdt_header_size_(fdt_version(fdt)); +} + +/** + * fdt_check_header - sanity check a device tree header + + * @fdt: pointer to data which might be a flattened device tree + * + * fdt_check_header() checks that the given buffer contains what + * appears to be a flattened device tree, and that the header contains + * valid information (to the extent that can be determined from the + * header alone). + * + * returns: + * 0, if the buffer appears to contain a valid device tree + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_TRUNCATED, standard meanings, as above + */ +int fdt_check_header(const void *fdt); + +/** + * fdt_move - move a device tree around in memory + * @fdt: pointer to the device tree to move + * @buf: pointer to memory where the device is to be moved + * @bufsize: size of the memory space at buf + * + * fdt_move() relocates, if possible, the device tree blob located at + * fdt to the buffer at buf of size bufsize. The buffer may overlap + * with the existing device tree blob at fdt. Therefore, + * fdt_move(fdt, fdt, fdt_totalsize(fdt)) + * should always succeed. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, bufsize is insufficient to contain the device tree + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, standard meanings + */ +int fdt_move(const void *fdt, void *buf, int bufsize); + +/**********************************************************************/ +/* Read-only functions */ +/**********************************************************************/ + +int fdt_check_full(const void *fdt, size_t bufsize); + +/** + * fdt_get_string - retrieve a string from the strings block of a device tree + * @fdt: pointer to the device tree blob + * @stroffset: offset of the string within the strings block (native endian) + * @lenp: optional pointer to return the string's length + * + * fdt_get_string() retrieves a pointer to a single string from the + * strings block of the device tree blob at fdt, and optionally also + * returns the string's length in *lenp. + * + * returns: + * a pointer to the string, on success + * NULL, if stroffset is out of bounds, or doesn't point to a valid string + */ +const char *fdt_get_string(const void *fdt, int stroffset, int *lenp); + +/** + * fdt_string - retrieve a string from the strings block of a device tree + * @fdt: pointer to the device tree blob + * @stroffset: offset of the string within the strings block (native endian) + * + * fdt_string() retrieves a pointer to a single string from the + * strings block of the device tree blob at fdt. + * + * returns: + * a pointer to the string, on success + * NULL, if stroffset is out of bounds, or doesn't point to a valid string + */ +const char *fdt_string(const void *fdt, int stroffset); + +/** + * fdt_find_max_phandle - find and return the highest phandle in a tree + * @fdt: pointer to the device tree blob + * @phandle: return location for the highest phandle value found in the tree + * + * fdt_find_max_phandle() finds the highest phandle value in the given device + * tree. The value returned in @phandle is only valid if the function returns + * success. + * + * returns: + * 0 on success or a negative error code on failure + */ +int fdt_find_max_phandle(const void *fdt, uint32_t *phandle); + +/** + * fdt_get_max_phandle - retrieves the highest phandle in a tree + * @fdt: pointer to the device tree blob + * + * fdt_get_max_phandle retrieves the highest phandle in the given + * device tree. This will ignore badly formatted phandles, or phandles + * with a value of 0 or -1. + * + * This function is deprecated in favour of fdt_find_max_phandle(). + * + * returns: + * the highest phandle on success + * 0, if no phandle was found in the device tree + * -1, if an error occurred + */ +static inline uint32_t fdt_get_max_phandle(const void *fdt) +{ + uint32_t phandle; + int err; + + err = fdt_find_max_phandle(fdt, &phandle); + if (err < 0) + return (uint32_t)-1; + + return phandle; +} + +/** + * fdt_generate_phandle - return a new, unused phandle for a device tree blob + * @fdt: pointer to the device tree blob + * @phandle: return location for the new phandle + * + * Walks the device tree blob and looks for the highest phandle value. On + * success, the new, unused phandle value (one higher than the previously + * highest phandle value in the device tree blob) will be returned in the + * @phandle parameter. + * + * Returns: + * 0 on success or a negative error-code on failure + */ +int fdt_generate_phandle(const void *fdt, uint32_t *phandle); + +/** + * fdt_num_mem_rsv - retrieve the number of memory reserve map entries + * @fdt: pointer to the device tree blob + * + * Returns the number of entries in the device tree blob's memory + * reservation map. This does not include the terminating 0,0 entry + * or any other (0,0) entries reserved for expansion. + * + * returns: + * the number of entries + */ +int fdt_num_mem_rsv(const void *fdt); + +/** + * fdt_get_mem_rsv - retrieve one memory reserve map entry + * @fdt: pointer to the device tree blob + * @address, @size: pointers to 64-bit variables + * + * On success, *address and *size will contain the address and size of + * the n-th reserve map entry from the device tree blob, in + * native-endian format. + * + * returns: + * 0, on success + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, standard meanings + */ +int fdt_get_mem_rsv(const void *fdt, int n, uint64_t *address, uint64_t *size); + +/** + * fdt_subnode_offset_namelen - find a subnode based on substring + * @fdt: pointer to the device tree blob + * @parentoffset: structure block offset of a node + * @name: name of the subnode to locate + * @namelen: number of characters of name to consider + * + * Identical to fdt_subnode_offset(), but only examine the first + * namelen characters of name for matching the subnode name. This is + * useful for finding subnodes based on a portion of a larger string, + * such as a full path. + */ +#ifndef SWIG /* Not available in Python */ +int fdt_subnode_offset_namelen(const void *fdt, int parentoffset, + const char *name, int namelen); +#endif +/** + * fdt_subnode_offset - find a subnode of a given node + * @fdt: pointer to the device tree blob + * @parentoffset: structure block offset of a node + * @name: name of the subnode to locate + * + * fdt_subnode_offset() finds a subnode of the node at structure block + * offset parentoffset with the given name. name may include a unit + * address, in which case fdt_subnode_offset() will find the subnode + * with that unit address, or the unit address may be omitted, in + * which case fdt_subnode_offset() will find an arbitrary subnode + * whose name excluding unit address matches the given name. + * + * returns: + * structure block offset of the requested subnode (>=0), on success + * -FDT_ERR_NOTFOUND, if the requested subnode does not exist + * -FDT_ERR_BADOFFSET, if parentoffset did not point to an FDT_BEGIN_NODE + * tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings. + */ +int fdt_subnode_offset(const void *fdt, int parentoffset, const char *name); + +/** + * fdt_path_offset_namelen - find a tree node by its full path + * @fdt: pointer to the device tree blob + * @path: full path of the node to locate + * @namelen: number of characters of path to consider + * + * Identical to fdt_path_offset(), but only consider the first namelen + * characters of path as the path name. + */ +#ifndef SWIG /* Not available in Python */ +int fdt_path_offset_namelen(const void *fdt, const char *path, int namelen); +#endif + +/** + * fdt_path_offset - find a tree node by its full path + * @fdt: pointer to the device tree blob + * @path: full path of the node to locate + * + * fdt_path_offset() finds a node of a given path in the device tree. + * Each path component may omit the unit address portion, but the + * results of this are undefined if any such path component is + * ambiguous (that is if there are multiple nodes at the relevant + * level matching the given component, differentiated only by unit + * address). + * + * returns: + * structure block offset of the node with the requested path (>=0), on + * success + * -FDT_ERR_BADPATH, given path does not begin with '/' or is invalid + * -FDT_ERR_NOTFOUND, if the requested node does not exist + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings. + */ +int fdt_path_offset(const void *fdt, const char *path); + +/** + * fdt_get_name - retrieve the name of a given node + * @fdt: pointer to the device tree blob + * @nodeoffset: structure block offset of the starting node + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * fdt_get_name() retrieves the name (including unit address) of the + * device tree node at structure block offset nodeoffset. If lenp is + * non-NULL, the length of this name is also returned, in the integer + * pointed to by lenp. + * + * returns: + * pointer to the node's name, on success + * If lenp is non-NULL, *lenp contains the length of that name + * (>=0) + * NULL, on error + * if lenp is non-NULL *lenp contains an error code (<0): + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE + * tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, standard meanings + */ +const char *fdt_get_name(const void *fdt, int nodeoffset, int *lenp); + +/** + * fdt_first_property_offset - find the offset of a node's first property + * @fdt: pointer to the device tree blob + * @nodeoffset: structure block offset of a node + * + * fdt_first_property_offset() finds the first property of the node at + * the given structure block offset. + * + * returns: + * structure block offset of the property (>=0), on success + * -FDT_ERR_NOTFOUND, if the requested node has no properties + * -FDT_ERR_BADOFFSET, if nodeoffset did not point to an FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings. + */ +int fdt_first_property_offset(const void *fdt, int nodeoffset); + +/** + * fdt_next_property_offset - step through a node's properties + * @fdt: pointer to the device tree blob + * @offset: structure block offset of a property + * + * fdt_next_property_offset() finds the property immediately after the + * one at the given structure block offset. This will be a property + * of the same node as the given property. + * + * returns: + * structure block offset of the next property (>=0), on success + * -FDT_ERR_NOTFOUND, if the given property is the last in its node + * -FDT_ERR_BADOFFSET, if nodeoffset did not point to an FDT_PROP tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings. + */ +int fdt_next_property_offset(const void *fdt, int offset); + +/** + * fdt_for_each_property_offset - iterate over all properties of a node + * + * @property_offset: property offset (int, lvalue) + * @fdt: FDT blob (const void *) + * @node: node offset (int) + * + * This is actually a wrapper around a for loop and would be used like so: + * + * fdt_for_each_property_offset(property, fdt, node) { + * Use property + * ... + * } + * + * if ((property < 0) && (property != -FDT_ERR_NOTFOUND)) { + * Error handling + * } + * + * Note that this is implemented as a macro and property is used as + * iterator in the loop. The node variable can be constant or even a + * literal. + */ +#define fdt_for_each_property_offset(property, fdt, node) \ + for (property = fdt_first_property_offset(fdt, node); \ + property >= 0; \ + property = fdt_next_property_offset(fdt, property)) + +/** + * fdt_get_property_by_offset - retrieve the property at a given offset + * @fdt: pointer to the device tree blob + * @offset: offset of the property to retrieve + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * fdt_get_property_by_offset() retrieves a pointer to the + * fdt_property structure within the device tree blob at the given + * offset. If lenp is non-NULL, the length of the property value is + * also returned, in the integer pointed to by lenp. + * + * Note that this code only works on device tree versions >= 16. fdt_getprop() + * works on all versions. + * + * returns: + * pointer to the structure representing the property + * if lenp is non-NULL, *lenp contains the length of the property + * value (>=0) + * NULL, on error + * if lenp is non-NULL, *lenp contains an error code (<0): + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_PROP tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +const struct fdt_property *fdt_get_property_by_offset(const void *fdt, + int offset, + int *lenp); + +/** + * fdt_get_property_namelen - find a property based on substring + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to find + * @name: name of the property to find + * @namelen: number of characters of name to consider + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * Identical to fdt_get_property(), but only examine the first namelen + * characters of name for matching the property name. + */ +#ifndef SWIG /* Not available in Python */ +const struct fdt_property *fdt_get_property_namelen(const void *fdt, + int nodeoffset, + const char *name, + int namelen, int *lenp); +#endif + +/** + * fdt_get_property - find a given property in a given node + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to find + * @name: name of the property to find + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * fdt_get_property() retrieves a pointer to the fdt_property + * structure within the device tree blob corresponding to the property + * named 'name' of the node at offset nodeoffset. If lenp is + * non-NULL, the length of the property value is also returned, in the + * integer pointed to by lenp. + * + * returns: + * pointer to the structure representing the property + * if lenp is non-NULL, *lenp contains the length of the property + * value (>=0) + * NULL, on error + * if lenp is non-NULL, *lenp contains an error code (<0): + * -FDT_ERR_NOTFOUND, node does not have named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE + * tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +const struct fdt_property *fdt_get_property(const void *fdt, int nodeoffset, + const char *name, int *lenp); +static inline struct fdt_property *fdt_get_property_w(void *fdt, int nodeoffset, + const char *name, + int *lenp) +{ + return (struct fdt_property *)(uintptr_t) + fdt_get_property(fdt, nodeoffset, name, lenp); +} + +/** + * fdt_getprop_by_offset - retrieve the value of a property at a given offset + * @fdt: pointer to the device tree blob + * @offset: offset of the property to read + * @namep: pointer to a string variable (will be overwritten) or NULL + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * fdt_getprop_by_offset() retrieves a pointer to the value of the + * property at structure block offset 'offset' (this will be a pointer + * to within the device blob itself, not a copy of the value). If + * lenp is non-NULL, the length of the property value is also + * returned, in the integer pointed to by lenp. If namep is non-NULL, + * the property's namne will also be returned in the char * pointed to + * by namep (this will be a pointer to within the device tree's string + * block, not a new copy of the name). + * + * returns: + * pointer to the property's value + * if lenp is non-NULL, *lenp contains the length of the property + * value (>=0) + * if namep is non-NULL *namep contiains a pointer to the property + * name. + * NULL, on error + * if lenp is non-NULL, *lenp contains an error code (<0): + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_PROP tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +#ifndef SWIG /* This function is not useful in Python */ +const void *fdt_getprop_by_offset(const void *fdt, int offset, + const char **namep, int *lenp); +#endif + +/** + * fdt_getprop_namelen - get property value based on substring + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to find + * @name: name of the property to find + * @namelen: number of characters of name to consider + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * Identical to fdt_getprop(), but only examine the first namelen + * characters of name for matching the property name. + */ +#ifndef SWIG /* Not available in Python */ +const void *fdt_getprop_namelen(const void *fdt, int nodeoffset, + const char *name, int namelen, int *lenp); +static inline void *fdt_getprop_namelen_w(void *fdt, int nodeoffset, + const char *name, int namelen, + int *lenp) +{ + return (void *)(uintptr_t)fdt_getprop_namelen(fdt, nodeoffset, name, + namelen, lenp); +} +#endif + +/** + * fdt_getprop - retrieve the value of a given property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to find + * @name: name of the property to find + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * fdt_getprop() retrieves a pointer to the value of the property + * named 'name' of the node at offset nodeoffset (this will be a + * pointer to within the device blob itself, not a copy of the value). + * If lenp is non-NULL, the length of the property value is also + * returned, in the integer pointed to by lenp. + * + * returns: + * pointer to the property's value + * if lenp is non-NULL, *lenp contains the length of the property + * value (>=0) + * NULL, on error + * if lenp is non-NULL, *lenp contains an error code (<0): + * -FDT_ERR_NOTFOUND, node does not have named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE + * tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +const void *fdt_getprop(const void *fdt, int nodeoffset, + const char *name, int *lenp); +static inline void *fdt_getprop_w(void *fdt, int nodeoffset, + const char *name, int *lenp) +{ + return (void *)(uintptr_t)fdt_getprop(fdt, nodeoffset, name, lenp); +} + +/** + * fdt_get_phandle - retrieve the phandle of a given node + * @fdt: pointer to the device tree blob + * @nodeoffset: structure block offset of the node + * + * fdt_get_phandle() retrieves the phandle of the device tree node at + * structure block offset nodeoffset. + * + * returns: + * the phandle of the node at nodeoffset, on success (!= 0, != -1) + * 0, if the node has no phandle, or another error occurs + */ +uint32_t fdt_get_phandle(const void *fdt, int nodeoffset); + +/** + * fdt_get_alias_namelen - get alias based on substring + * @fdt: pointer to the device tree blob + * @name: name of the alias th look up + * @namelen: number of characters of name to consider + * + * Identical to fdt_get_alias(), but only examine the first namelen + * characters of name for matching the alias name. + */ +#ifndef SWIG /* Not available in Python */ +const char *fdt_get_alias_namelen(const void *fdt, + const char *name, int namelen); +#endif + +/** + * fdt_get_alias - retrieve the path referenced by a given alias + * @fdt: pointer to the device tree blob + * @name: name of the alias th look up + * + * fdt_get_alias() retrieves the value of a given alias. That is, the + * value of the property named 'name' in the node /aliases. + * + * returns: + * a pointer to the expansion of the alias named 'name', if it exists + * NULL, if the given alias or the /aliases node does not exist + */ +const char *fdt_get_alias(const void *fdt, const char *name); + +/** + * fdt_get_path - determine the full path of a node + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose path to find + * @buf: character buffer to contain the returned path (will be overwritten) + * @buflen: size of the character buffer at buf + * + * fdt_get_path() computes the full path of the node at offset + * nodeoffset, and records that path in the buffer at buf. + * + * NOTE: This function is expensive, as it must scan the device tree + * structure from the start to nodeoffset. + * + * returns: + * 0, on success + * buf contains the absolute path of the node at + * nodeoffset, as a NUL-terminated string. + * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag + * -FDT_ERR_NOSPACE, the path of the given node is longer than (bufsize-1) + * characters and will not fit in the given buffer. + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_get_path(const void *fdt, int nodeoffset, char *buf, int buflen); + +/** + * fdt_supernode_atdepth_offset - find a specific ancestor of a node + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose parent to find + * @supernodedepth: depth of the ancestor to find + * @nodedepth: pointer to an integer variable (will be overwritten) or NULL + * + * fdt_supernode_atdepth_offset() finds an ancestor of the given node + * at a specific depth from the root (where the root itself has depth + * 0, its immediate subnodes depth 1 and so forth). So + * fdt_supernode_atdepth_offset(fdt, nodeoffset, 0, NULL); + * will always return 0, the offset of the root node. If the node at + * nodeoffset has depth D, then: + * fdt_supernode_atdepth_offset(fdt, nodeoffset, D, NULL); + * will return nodeoffset itself. + * + * NOTE: This function is expensive, as it must scan the device tree + * structure from the start to nodeoffset. + * + * returns: + * structure block offset of the node at node offset's ancestor + * of depth supernodedepth (>=0), on success + * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag + * -FDT_ERR_NOTFOUND, supernodedepth was greater than the depth of + * nodeoffset + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_supernode_atdepth_offset(const void *fdt, int nodeoffset, + int supernodedepth, int *nodedepth); + +/** + * fdt_node_depth - find the depth of a given node + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose parent to find + * + * fdt_node_depth() finds the depth of a given node. The root node + * has depth 0, its immediate subnodes depth 1 and so forth. + * + * NOTE: This function is expensive, as it must scan the device tree + * structure from the start to nodeoffset. + * + * returns: + * depth of the node at nodeoffset (>=0), on success + * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_node_depth(const void *fdt, int nodeoffset); + +/** + * fdt_parent_offset - find the parent of a given node + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose parent to find + * + * fdt_parent_offset() locates the parent node of a given node (that + * is, it finds the offset of the node which contains the node at + * nodeoffset as a subnode). + * + * NOTE: This function is expensive, as it must scan the device tree + * structure from the start to nodeoffset, *twice*. + * + * returns: + * structure block offset of the parent of the node at nodeoffset + * (>=0), on success + * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_parent_offset(const void *fdt, int nodeoffset); + +/** + * fdt_node_offset_by_prop_value - find nodes with a given property value + * @fdt: pointer to the device tree blob + * @startoffset: only find nodes after this offset + * @propname: property name to check + * @propval: property value to search for + * @proplen: length of the value in propval + * + * fdt_node_offset_by_prop_value() returns the offset of the first + * node after startoffset, which has a property named propname whose + * value is of length proplen and has value equal to propval; or if + * startoffset is -1, the very first such node in the tree. + * + * To iterate through all nodes matching the criterion, the following + * idiom can be used: + * offset = fdt_node_offset_by_prop_value(fdt, -1, propname, + * propval, proplen); + * while (offset != -FDT_ERR_NOTFOUND) { + * // other code here + * offset = fdt_node_offset_by_prop_value(fdt, offset, propname, + * propval, proplen); + * } + * + * Note the -1 in the first call to the function, if 0 is used here + * instead, the function will never locate the root node, even if it + * matches the criterion. + * + * returns: + * structure block offset of the located node (>= 0, >startoffset), + * on success + * -FDT_ERR_NOTFOUND, no node matching the criterion exists in the + * tree after startoffset + * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_node_offset_by_prop_value(const void *fdt, int startoffset, + const char *propname, + const void *propval, int proplen); + +/** + * fdt_node_offset_by_phandle - find the node with a given phandle + * @fdt: pointer to the device tree blob + * @phandle: phandle value + * + * fdt_node_offset_by_phandle() returns the offset of the node + * which has the given phandle value. If there is more than one node + * in the tree with the given phandle (an invalid tree), results are + * undefined. + * + * returns: + * structure block offset of the located node (>= 0), on success + * -FDT_ERR_NOTFOUND, no node with that phandle exists + * -FDT_ERR_BADPHANDLE, given phandle value was invalid (0 or -1) + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_node_offset_by_phandle(const void *fdt, uint32_t phandle); + +/** + * fdt_node_check_compatible: check a node's compatible property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of a tree node + * @compatible: string to match against + * + * + * fdt_node_check_compatible() returns 0 if the given node contains a + * 'compatible' property with the given string as one of its elements, + * it returns non-zero otherwise, or on error. + * + * returns: + * 0, if the node has a 'compatible' property listing the given string + * 1, if the node has a 'compatible' property, but it does not list + * the given string + * -FDT_ERR_NOTFOUND, if the given node has no 'compatible' property + * -FDT_ERR_BADOFFSET, if nodeoffset does not refer to a BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_node_check_compatible(const void *fdt, int nodeoffset, + const char *compatible); + +/** + * fdt_node_offset_by_compatible - find nodes with a given 'compatible' value + * @fdt: pointer to the device tree blob + * @startoffset: only find nodes after this offset + * @compatible: 'compatible' string to match against + * + * fdt_node_offset_by_compatible() returns the offset of the first + * node after startoffset, which has a 'compatible' property which + * lists the given compatible string; or if startoffset is -1, the + * very first such node in the tree. + * + * To iterate through all nodes matching the criterion, the following + * idiom can be used: + * offset = fdt_node_offset_by_compatible(fdt, -1, compatible); + * while (offset != -FDT_ERR_NOTFOUND) { + * // other code here + * offset = fdt_node_offset_by_compatible(fdt, offset, compatible); + * } + * + * Note the -1 in the first call to the function, if 0 is used here + * instead, the function will never locate the root node, even if it + * matches the criterion. + * + * returns: + * structure block offset of the located node (>= 0, >startoffset), + * on success + * -FDT_ERR_NOTFOUND, no node matching the criterion exists in the + * tree after startoffset + * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_node_offset_by_compatible(const void *fdt, int startoffset, + const char *compatible); + +/** + * fdt_stringlist_contains - check a string list property for a string + * @strlist: Property containing a list of strings to check + * @listlen: Length of property + * @str: String to search for + * + * This is a utility function provided for convenience. The list contains + * one or more strings, each terminated by \0, as is found in a device tree + * "compatible" property. + * + * @return: 1 if the string is found in the list, 0 not found, or invalid list + */ +int fdt_stringlist_contains(const char *strlist, int listlen, const char *str); + +/** + * fdt_stringlist_count - count the number of strings in a string list + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of a tree node + * @property: name of the property containing the string list + * @return: + * the number of strings in the given property + * -FDT_ERR_BADVALUE if the property value is not NUL-terminated + * -FDT_ERR_NOTFOUND if the property does not exist + */ +int fdt_stringlist_count(const void *fdt, int nodeoffset, const char *property); + +/** + * fdt_stringlist_search - find a string in a string list and return its index + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of a tree node + * @property: name of the property containing the string list + * @string: string to look up in the string list + * + * Note that it is possible for this function to succeed on property values + * that are not NUL-terminated. That's because the function will stop after + * finding the first occurrence of @string. This can for example happen with + * small-valued cell properties, such as #address-cells, when searching for + * the empty string. + * + * @return: + * the index of the string in the list of strings + * -FDT_ERR_BADVALUE if the property value is not NUL-terminated + * -FDT_ERR_NOTFOUND if the property does not exist or does not contain + * the given string + */ +int fdt_stringlist_search(const void *fdt, int nodeoffset, const char *property, + const char *string); + +/** + * fdt_stringlist_get() - obtain the string at a given index in a string list + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of a tree node + * @property: name of the property containing the string list + * @index: index of the string to return + * @lenp: return location for the string length or an error code on failure + * + * Note that this will successfully extract strings from properties with + * non-NUL-terminated values. For example on small-valued cell properties + * this function will return the empty string. + * + * If non-NULL, the length of the string (on success) or a negative error-code + * (on failure) will be stored in the integer pointer to by lenp. + * + * @return: + * A pointer to the string at the given index in the string list or NULL on + * failure. On success the length of the string will be stored in the memory + * location pointed to by the lenp parameter, if non-NULL. On failure one of + * the following negative error codes will be returned in the lenp parameter + * (if non-NULL): + * -FDT_ERR_BADVALUE if the property value is not NUL-terminated + * -FDT_ERR_NOTFOUND if the property does not exist + */ +const char *fdt_stringlist_get(const void *fdt, int nodeoffset, + const char *property, int index, + int *lenp); + +/**********************************************************************/ +/* Read-only functions (addressing related) */ +/**********************************************************************/ + +/** + * FDT_MAX_NCELLS - maximum value for #address-cells and #size-cells + * + * This is the maximum value for #address-cells, #size-cells and + * similar properties that will be processed by libfdt. IEE1275 + * requires that OF implementations handle values up to 4. + * Implementations may support larger values, but in practice higher + * values aren't used. + */ +#define FDT_MAX_NCELLS 4 + +/** + * fdt_address_cells - retrieve address size for a bus represented in the tree + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node to find the address size for + * + * When the node has a valid #address-cells property, returns its value. + * + * returns: + * 0 <= n < FDT_MAX_NCELLS, on success + * 2, if the node has no #address-cells property + * -FDT_ERR_BADNCELLS, if the node has a badly formatted or invalid + * #address-cells property + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_address_cells(const void *fdt, int nodeoffset); + +/** + * fdt_size_cells - retrieve address range size for a bus represented in the + * tree + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node to find the address range size for + * + * When the node has a valid #size-cells property, returns its value. + * + * returns: + * 0 <= n < FDT_MAX_NCELLS, on success + * 1, if the node has no #size-cells property + * -FDT_ERR_BADNCELLS, if the node has a badly formatted or invalid + * #size-cells property + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_size_cells(const void *fdt, int nodeoffset); + + +/**********************************************************************/ +/* Write-in-place functions */ +/**********************************************************************/ + +/** + * fdt_setprop_inplace_namelen_partial - change a property's value, + * but not its size + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @namelen: number of characters of name to consider + * @idx: index of the property to change in the array + * @val: pointer to data to replace the property value with + * @len: length of the property value + * + * Identical to fdt_setprop_inplace(), but modifies the given property + * starting from the given index, and using only the first characters + * of the name. It is useful when you want to manipulate only one value of + * an array and you have a string that doesn't end with \0. + */ +#ifndef SWIG /* Not available in Python */ +int fdt_setprop_inplace_namelen_partial(void *fdt, int nodeoffset, + const char *name, int namelen, + uint32_t idx, const void *val, + int len); +#endif + +/** + * fdt_setprop_inplace - change a property's value, but not its size + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: pointer to data to replace the property value with + * @len: length of the property value + * + * fdt_setprop_inplace() replaces the value of a given property with + * the data in val, of length len. This function cannot change the + * size of a property, and so will only work if len is equal to the + * current length of the property. + * + * This function will alter only the bytes in the blob which contain + * the given property value, and will not alter or move any other part + * of the tree. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, if len is not equal to the property's current length + * -FDT_ERR_NOTFOUND, node does not have the named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +#ifndef SWIG /* Not available in Python */ +int fdt_setprop_inplace(void *fdt, int nodeoffset, const char *name, + const void *val, int len); +#endif + +/** + * fdt_setprop_inplace_u32 - change the value of a 32-bit integer property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: 32-bit integer value to replace the property with + * + * fdt_setprop_inplace_u32() replaces the value of a given property + * with the 32-bit integer value in val, converting val to big-endian + * if necessary. This function cannot change the size of a property, + * and so will only work if the property already exists and has length + * 4. + * + * This function will alter only the bytes in the blob which contain + * the given property value, and will not alter or move any other part + * of the tree. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, if the property's length is not equal to 4 + * -FDT_ERR_NOTFOUND, node does not have the named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +static inline int fdt_setprop_inplace_u32(void *fdt, int nodeoffset, + const char *name, uint32_t val) +{ + fdt32_t tmp = cpu_to_fdt32(val); + return fdt_setprop_inplace(fdt, nodeoffset, name, &tmp, sizeof(tmp)); +} + +/** + * fdt_setprop_inplace_u64 - change the value of a 64-bit integer property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: 64-bit integer value to replace the property with + * + * fdt_setprop_inplace_u64() replaces the value of a given property + * with the 64-bit integer value in val, converting val to big-endian + * if necessary. This function cannot change the size of a property, + * and so will only work if the property already exists and has length + * 8. + * + * This function will alter only the bytes in the blob which contain + * the given property value, and will not alter or move any other part + * of the tree. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, if the property's length is not equal to 8 + * -FDT_ERR_NOTFOUND, node does not have the named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +static inline int fdt_setprop_inplace_u64(void *fdt, int nodeoffset, + const char *name, uint64_t val) +{ + fdt64_t tmp = cpu_to_fdt64(val); + return fdt_setprop_inplace(fdt, nodeoffset, name, &tmp, sizeof(tmp)); +} + +/** + * fdt_setprop_inplace_cell - change the value of a single-cell property + * + * This is an alternative name for fdt_setprop_inplace_u32() + */ +static inline int fdt_setprop_inplace_cell(void *fdt, int nodeoffset, + const char *name, uint32_t val) +{ + return fdt_setprop_inplace_u32(fdt, nodeoffset, name, val); +} + +/** + * fdt_nop_property - replace a property with nop tags + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to nop + * @name: name of the property to nop + * + * fdt_nop_property() will replace a given property's representation + * in the blob with FDT_NOP tags, effectively removing it from the + * tree. + * + * This function will alter only the bytes in the blob which contain + * the property, and will not alter or move any other part of the + * tree. + * + * returns: + * 0, on success + * -FDT_ERR_NOTFOUND, node does not have the named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_nop_property(void *fdt, int nodeoffset, const char *name); + +/** + * fdt_nop_node - replace a node (subtree) with nop tags + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node to nop + * + * fdt_nop_node() will replace a given node's representation in the + * blob, including all its subnodes, if any, with FDT_NOP tags, + * effectively removing it from the tree. + * + * This function will alter only the bytes in the blob which contain + * the node and its properties and subnodes, and will not alter or + * move any other part of the tree. + * + * returns: + * 0, on success + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_nop_node(void *fdt, int nodeoffset); + +/**********************************************************************/ +/* Sequential write functions */ +/**********************************************************************/ + +/* fdt_create_with_flags flags */ +#define FDT_CREATE_FLAG_NO_NAME_DEDUP 0x1 + /* FDT_CREATE_FLAG_NO_NAME_DEDUP: Do not try to de-duplicate property + * names in the fdt. This can result in faster creation times, but + * a larger fdt. */ + +#define FDT_CREATE_FLAGS_ALL (FDT_CREATE_FLAG_NO_NAME_DEDUP) + +/** + * fdt_create_with_flags - begin creation of a new fdt + * @fdt: pointer to memory allocated where fdt will be created + * @bufsize: size of the memory space at fdt + * @flags: a valid combination of FDT_CREATE_FLAG_ flags, or 0. + * + * fdt_create_with_flags() begins the process of creating a new fdt with + * the sequential write interface. + * + * fdt creation process must end with fdt_finished() to produce a valid fdt. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, bufsize is insufficient for a minimal fdt + * -FDT_ERR_BADFLAGS, flags is not valid + */ +int fdt_create_with_flags(void *buf, int bufsize, uint32_t flags); + +/** + * fdt_create - begin creation of a new fdt + * @fdt: pointer to memory allocated where fdt will be created + * @bufsize: size of the memory space at fdt + * + * fdt_create() is equivalent to fdt_create_with_flags() with flags=0. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, bufsize is insufficient for a minimal fdt + */ +int fdt_create(void *buf, int bufsize); + +int fdt_resize(void *fdt, void *buf, int bufsize); +int fdt_add_reservemap_entry(void *fdt, uint64_t addr, uint64_t size); +int fdt_finish_reservemap(void *fdt); +int fdt_begin_node(void *fdt, const char *name); +int fdt_property(void *fdt, const char *name, const void *val, int len); +static inline int fdt_property_u32(void *fdt, const char *name, uint32_t val) +{ + fdt32_t tmp = cpu_to_fdt32(val); + return fdt_property(fdt, name, &tmp, sizeof(tmp)); +} +static inline int fdt_property_u64(void *fdt, const char *name, uint64_t val) +{ + fdt64_t tmp = cpu_to_fdt64(val); + return fdt_property(fdt, name, &tmp, sizeof(tmp)); +} + +#ifndef SWIG /* Not available in Python */ +static inline int fdt_property_cell(void *fdt, const char *name, uint32_t val) +{ + return fdt_property_u32(fdt, name, val); +} +#endif + +/** + * fdt_property_placeholder - add a new property and return a ptr to its value + * + * @fdt: pointer to the device tree blob + * @name: name of property to add + * @len: length of property value in bytes + * @valp: returns a pointer to where where the value should be placed + * + * returns: + * 0, on success + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_NOSPACE, standard meanings + */ +int fdt_property_placeholder(void *fdt, const char *name, int len, void **valp); + +#define fdt_property_string(fdt, name, str) \ + fdt_property(fdt, name, str, strlen(str)+1) +int fdt_end_node(void *fdt); +int fdt_finish(void *fdt); + +/**********************************************************************/ +/* Read-write functions */ +/**********************************************************************/ + +int fdt_create_empty_tree(void *buf, int bufsize); +int fdt_open_into(const void *fdt, void *buf, int bufsize); +int fdt_pack(void *fdt); + +/** + * fdt_add_mem_rsv - add one memory reserve map entry + * @fdt: pointer to the device tree blob + * @address, @size: 64-bit values (native endian) + * + * Adds a reserve map entry to the given blob reserving a region at + * address address of length size. + * + * This function will insert data into the reserve map and will + * therefore change the indexes of some entries in the table. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new reservation entry + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_add_mem_rsv(void *fdt, uint64_t address, uint64_t size); + +/** + * fdt_del_mem_rsv - remove a memory reserve map entry + * @fdt: pointer to the device tree blob + * @n: entry to remove + * + * fdt_del_mem_rsv() removes the n-th memory reserve map entry from + * the blob. + * + * This function will delete data from the reservation table and will + * therefore change the indexes of some entries in the table. + * + * returns: + * 0, on success + * -FDT_ERR_NOTFOUND, there is no entry of the given index (i.e. there + * are less than n+1 reserve map entries) + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_del_mem_rsv(void *fdt, int n); + +/** + * fdt_set_name - change the name of a given node + * @fdt: pointer to the device tree blob + * @nodeoffset: structure block offset of a node + * @name: name to give the node + * + * fdt_set_name() replaces the name (including unit address, if any) + * of the given node with the given string. NOTE: this function can't + * efficiently check if the new name is unique amongst the given + * node's siblings; results are undefined if this function is invoked + * with a name equal to one of the given node's siblings. + * + * This function may insert or delete data from the blob, and will + * therefore change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob + * to contain the new name + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, standard meanings + */ +int fdt_set_name(void *fdt, int nodeoffset, const char *name); + +/** + * fdt_setprop - create or change a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: pointer to data to set the property value to + * @len: length of the property value + * + * fdt_setprop() sets the value of the named property in the given + * node to the given value and length, creating the property if it + * does not already exist. + * + * This function may insert or delete data from the blob, and will + * therefore change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_setprop(void *fdt, int nodeoffset, const char *name, + const void *val, int len); + +/** + * fdt_setprop_placeholder - allocate space for a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @len: length of the property value + * @prop_data: return pointer to property data + * + * fdt_setprop_placeholer() allocates the named property in the given node. + * If the property exists it is resized. In either case a pointer to the + * property data is returned. + * + * This function may insert or delete data from the blob, and will + * therefore change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_setprop_placeholder(void *fdt, int nodeoffset, const char *name, + int len, void **prop_data); + +/** + * fdt_setprop_u32 - set a property to a 32-bit integer + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: 32-bit integer value for the property (native endian) + * + * fdt_setprop_u32() sets the value of the named property in the given + * node to the given 32-bit integer value (converting to big-endian if + * necessary), or creates a new property with that value if it does + * not already exist. + * + * This function may insert or delete data from the blob, and will + * therefore change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +static inline int fdt_setprop_u32(void *fdt, int nodeoffset, const char *name, + uint32_t val) +{ + fdt32_t tmp = cpu_to_fdt32(val); + return fdt_setprop(fdt, nodeoffset, name, &tmp, sizeof(tmp)); +} + +/** + * fdt_setprop_u64 - set a property to a 64-bit integer + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: 64-bit integer value for the property (native endian) + * + * fdt_setprop_u64() sets the value of the named property in the given + * node to the given 64-bit integer value (converting to big-endian if + * necessary), or creates a new property with that value if it does + * not already exist. + * + * This function may insert or delete data from the blob, and will + * therefore change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +static inline int fdt_setprop_u64(void *fdt, int nodeoffset, const char *name, + uint64_t val) +{ + fdt64_t tmp = cpu_to_fdt64(val); + return fdt_setprop(fdt, nodeoffset, name, &tmp, sizeof(tmp)); +} + +/** + * fdt_setprop_cell - set a property to a single cell value + * + * This is an alternative name for fdt_setprop_u32() + */ +static inline int fdt_setprop_cell(void *fdt, int nodeoffset, const char *name, + uint32_t val) +{ + return fdt_setprop_u32(fdt, nodeoffset, name, val); +} + +/** + * fdt_setprop_string - set a property to a string value + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @str: string value for the property + * + * fdt_setprop_string() sets the value of the named property in the + * given node to the given string value (using the length of the + * string to determine the new length of the property), or creates a + * new property with that value if it does not already exist. + * + * This function may insert or delete data from the blob, and will + * therefore change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +#define fdt_setprop_string(fdt, nodeoffset, name, str) \ + fdt_setprop((fdt), (nodeoffset), (name), (str), strlen(str)+1) + + +/** + * fdt_setprop_empty - set a property to an empty value + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * + * fdt_setprop_empty() sets the value of the named property in the + * given node to an empty (zero length) value, or creates a new empty + * property if it does not already exist. + * + * This function may insert or delete data from the blob, and will + * therefore change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +#define fdt_setprop_empty(fdt, nodeoffset, name) \ + fdt_setprop((fdt), (nodeoffset), (name), NULL, 0) + +/** + * fdt_appendprop - append to or create a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to append to + * @val: pointer to data to append to the property value + * @len: length of the data to append to the property value + * + * fdt_appendprop() appends the value to the named property in the + * given node, creating the property if it does not already exist. + * + * This function may insert data into the blob, and will therefore + * change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_appendprop(void *fdt, int nodeoffset, const char *name, + const void *val, int len); + +/** + * fdt_appendprop_u32 - append a 32-bit integer value to a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: 32-bit integer value to append to the property (native endian) + * + * fdt_appendprop_u32() appends the given 32-bit integer value + * (converting to big-endian if necessary) to the value of the named + * property in the given node, or creates a new property with that + * value if it does not already exist. + * + * This function may insert data into the blob, and will therefore + * change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +static inline int fdt_appendprop_u32(void *fdt, int nodeoffset, + const char *name, uint32_t val) +{ + fdt32_t tmp = cpu_to_fdt32(val); + return fdt_appendprop(fdt, nodeoffset, name, &tmp, sizeof(tmp)); +} + +/** + * fdt_appendprop_u64 - append a 64-bit integer value to a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: 64-bit integer value to append to the property (native endian) + * + * fdt_appendprop_u64() appends the given 64-bit integer value + * (converting to big-endian if necessary) to the value of the named + * property in the given node, or creates a new property with that + * value if it does not already exist. + * + * This function may insert data into the blob, and will therefore + * change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +static inline int fdt_appendprop_u64(void *fdt, int nodeoffset, + const char *name, uint64_t val) +{ + fdt64_t tmp = cpu_to_fdt64(val); + return fdt_appendprop(fdt, nodeoffset, name, &tmp, sizeof(tmp)); +} + +/** + * fdt_appendprop_cell - append a single cell value to a property + * + * This is an alternative name for fdt_appendprop_u32() + */ +static inline int fdt_appendprop_cell(void *fdt, int nodeoffset, + const char *name, uint32_t val) +{ + return fdt_appendprop_u32(fdt, nodeoffset, name, val); +} + +/** + * fdt_appendprop_string - append a string to a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @str: string value to append to the property + * + * fdt_appendprop_string() appends the given string to the value of + * the named property in the given node, or creates a new property + * with that value if it does not already exist. + * + * This function may insert data into the blob, and will therefore + * change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +#define fdt_appendprop_string(fdt, nodeoffset, name, str) \ + fdt_appendprop((fdt), (nodeoffset), (name), (str), strlen(str)+1) + +/** + * fdt_appendprop_addrrange - append a address range property + * @fdt: pointer to the device tree blob + * @parent: offset of the parent node + * @nodeoffset: offset of the node to add a property at + * @name: name of property + * @addr: start address of a given range + * @size: size of a given range + * + * fdt_appendprop_addrrange() appends an address range value (start + * address and size) to the value of the named property in the given + * node, or creates a new property with that value if it does not + * already exist. + * If "name" is not specified, a default "reg" is used. + * Cell sizes are determined by parent's #address-cells and #size-cells. + * + * This function may insert data into the blob, and will therefore + * change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADNCELLS, if the node has a badly formatted or invalid + * #address-cells property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADVALUE, addr or size doesn't fit to respective cells size + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain a new property + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_appendprop_addrrange(void *fdt, int parent, int nodeoffset, + const char *name, uint64_t addr, uint64_t size); + +/** + * fdt_delprop - delete a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to nop + * @name: name of the property to nop + * + * fdt_del_property() will delete the given property. + * + * This function will delete data from the blob, and will therefore + * change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOTFOUND, node does not have the named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_delprop(void *fdt, int nodeoffset, const char *name); + +/** + * fdt_add_subnode_namelen - creates a new node based on substring + * @fdt: pointer to the device tree blob + * @parentoffset: structure block offset of a node + * @name: name of the subnode to locate + * @namelen: number of characters of name to consider + * + * Identical to fdt_add_subnode(), but use only the first namelen + * characters of name as the name of the new node. This is useful for + * creating subnodes based on a portion of a larger string, such as a + * full path. + */ +#ifndef SWIG /* Not available in Python */ +int fdt_add_subnode_namelen(void *fdt, int parentoffset, + const char *name, int namelen); +#endif + +/** + * fdt_add_subnode - creates a new node + * @fdt: pointer to the device tree blob + * @parentoffset: structure block offset of a node + * @name: name of the subnode to locate + * + * fdt_add_subnode() creates a new node as a subnode of the node at + * structure block offset parentoffset, with the given name (which + * should include the unit address, if any). + * + * This function will insert data into the blob, and will therefore + * change the offsets of some existing nodes. + + * returns: + * structure block offset of the created nodeequested subnode (>=0), on + * success + * -FDT_ERR_NOTFOUND, if the requested subnode does not exist + * -FDT_ERR_BADOFFSET, if parentoffset did not point to an FDT_BEGIN_NODE + * tag + * -FDT_ERR_EXISTS, if the node at parentoffset already has a subnode of + * the given name + * -FDT_ERR_NOSPACE, if there is insufficient free space in the + * blob to contain the new node + * -FDT_ERR_NOSPACE + * -FDT_ERR_BADLAYOUT + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings. + */ +int fdt_add_subnode(void *fdt, int parentoffset, const char *name); + +/** + * fdt_del_node - delete a node (subtree) + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node to nop + * + * fdt_del_node() will remove the given node, including all its + * subnodes if any, from the blob. + * + * This function will delete data from the blob, and will therefore + * change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_del_node(void *fdt, int nodeoffset); + +/** + * fdt_overlay_apply - Applies a DT overlay on a base DT + * @fdt: pointer to the base device tree blob + * @fdto: pointer to the device tree overlay blob + * + * fdt_overlay_apply() will apply the given device tree overlay on the + * given base device tree. + * + * Expect the base device tree to be modified, even if the function + * returns an error. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there's not enough space in the base device tree + * -FDT_ERR_NOTFOUND, the overlay points to some inexistant nodes or + * properties in the base DT + * -FDT_ERR_BADPHANDLE, + * -FDT_ERR_BADOVERLAY, + * -FDT_ERR_NOPHANDLES, + * -FDT_ERR_INTERNAL, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADOFFSET, + * -FDT_ERR_BADPATH, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_overlay_apply(void *fdt, void *fdto); + +/**********************************************************************/ +/* Debugging / informational functions */ +/**********************************************************************/ + +const char *fdt_strerror(int errval); +#ifdef __cplusplus +} +#endif + +#endif /* LIBFDT_H */ diff --git a/vendor/riscv/riscv-isa-sim/fdt/libfdt_env.h b/vendor/riscv/riscv-isa-sim/fdt/libfdt_env.h new file mode 100644 index 0000000000..44bd12a0c9 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/fdt/libfdt_env.h @@ -0,0 +1,95 @@ +/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) */ +#ifndef LIBFDT_ENV_H +#define LIBFDT_ENV_H +/* + * libfdt - Flat Device Tree manipulation + * Copyright (C) 2006 David Gibson, IBM Corporation. + * Copyright 2012 Kim Phillips, Freescale Semiconductor. + */ + +#include <string.h> +#include <stdint.h> +#include <stdbool.h> +#include <stdlib.h> +#include <limits.h> + +#ifdef __CHECKER__ +#define FDT_FORCE __attribute__((force)) +#define FDT_BITWISE __attribute__((bitwise)) +#else +#define FDT_FORCE +#define FDT_BITWISE +#endif + +typedef uint16_t FDT_BITWISE fdt16_t; +typedef uint32_t FDT_BITWISE fdt32_t; +typedef uint64_t FDT_BITWISE fdt64_t; + +#define EXTRACT_BYTE(x, n) ((unsigned long long)((uint8_t *)&x)[n]) +#define CPU_TO_FDT16(x) ((EXTRACT_BYTE(x, 0) << 8) | EXTRACT_BYTE(x, 1)) +#define CPU_TO_FDT32(x) ((EXTRACT_BYTE(x, 0) << 24) | (EXTRACT_BYTE(x, 1) << 16) | \ + (EXTRACT_BYTE(x, 2) << 8) | EXTRACT_BYTE(x, 3)) +#define CPU_TO_FDT64(x) ((EXTRACT_BYTE(x, 0) << 56) | (EXTRACT_BYTE(x, 1) << 48) | \ + (EXTRACT_BYTE(x, 2) << 40) | (EXTRACT_BYTE(x, 3) << 32) | \ + (EXTRACT_BYTE(x, 4) << 24) | (EXTRACT_BYTE(x, 5) << 16) | \ + (EXTRACT_BYTE(x, 6) << 8) | EXTRACT_BYTE(x, 7)) + +static inline uint16_t fdt16_to_cpu(fdt16_t x) +{ + return (FDT_FORCE uint16_t)CPU_TO_FDT16(x); +} +static inline fdt16_t cpu_to_fdt16(uint16_t x) +{ + return (FDT_FORCE fdt16_t)CPU_TO_FDT16(x); +} + +static inline uint32_t fdt32_to_cpu(fdt32_t x) +{ + return (FDT_FORCE uint32_t)CPU_TO_FDT32(x); +} +static inline fdt32_t cpu_to_fdt32(uint32_t x) +{ + return (FDT_FORCE fdt32_t)CPU_TO_FDT32(x); +} + +static inline uint64_t fdt64_to_cpu(fdt64_t x) +{ + return (FDT_FORCE uint64_t)CPU_TO_FDT64(x); +} +static inline fdt64_t cpu_to_fdt64(uint64_t x) +{ + return (FDT_FORCE fdt64_t)CPU_TO_FDT64(x); +} +#undef CPU_TO_FDT64 +#undef CPU_TO_FDT32 +#undef CPU_TO_FDT16 +#undef EXTRACT_BYTE + +#ifdef __APPLE__ +#include <AvailabilityMacros.h> + +/* strnlen() is not available on Mac OS < 10.7 */ +# if !defined(MAC_OS_X_VERSION_10_7) || (MAC_OS_X_VERSION_MAX_ALLOWED < \ + MAC_OS_X_VERSION_10_7) + +#define strnlen fdt_strnlen + +/* + * fdt_strnlen: returns the length of a string or max_count - which ever is + * smallest. + * Input 1 string: the string whose size is to be determined + * Input 2 max_count: the maximum value returned by this function + * Output: length of the string or max_count (the smallest of the two) + */ +static inline size_t fdt_strnlen(const char *string, size_t max_count) +{ + const char *p = memchr(string, 0, max_count); + return p ? p - string : max_count; +} + +#endif /* !defined(MAC_OS_X_VERSION_10_7) || (MAC_OS_X_VERSION_MAX_ALLOWED < + MAC_OS_X_VERSION_10_7) */ + +#endif /* __APPLE__ */ + +#endif /* LIBFDT_ENV_H */ diff --git a/vendor/riscv/riscv-isa-sim/fdt/libfdt_internal.h b/vendor/riscv/riscv-isa-sim/fdt/libfdt_internal.h new file mode 100644 index 0000000000..741eeb3150 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/fdt/libfdt_internal.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) */ +#ifndef LIBFDT_INTERNAL_H +#define LIBFDT_INTERNAL_H +/* + * libfdt - Flat Device Tree manipulation + * Copyright (C) 2006 David Gibson, IBM Corporation. + */ +#include <fdt.h> + +#define FDT_ALIGN(x, a) (((x) + (a) - 1) & ~((a) - 1)) +#define FDT_TAGALIGN(x) (FDT_ALIGN((x), FDT_TAGSIZE)) + +int fdt_ro_probe_(const void *fdt); +#define FDT_RO_PROBE(fdt) \ + { \ + int totalsize_; \ + if ((totalsize_ = fdt_ro_probe_(fdt)) < 0) \ + return totalsize_; \ + } + +int fdt_check_node_offset_(const void *fdt, int offset); +int fdt_check_prop_offset_(const void *fdt, int offset); +const char *fdt_find_string_(const char *strtab, int tabsize, const char *s); +int fdt_node_end_offset_(void *fdt, int nodeoffset); + +static inline const void *fdt_offset_ptr_(const void *fdt, int offset) +{ + return (const char *)fdt + fdt_off_dt_struct(fdt) + offset; +} + +static inline void *fdt_offset_ptr_w_(void *fdt, int offset) +{ + return (void *)(uintptr_t)fdt_offset_ptr_(fdt, offset); +} + +static inline const struct fdt_reserve_entry *fdt_mem_rsv_(const void *fdt, int n) +{ + const struct fdt_reserve_entry *rsv_table = + (const struct fdt_reserve_entry *) + ((const char *)fdt + fdt_off_mem_rsvmap(fdt)); + + return rsv_table + n; +} +static inline struct fdt_reserve_entry *fdt_mem_rsv_w_(void *fdt, int n) +{ + return (void *)(uintptr_t)fdt_mem_rsv_(fdt, n); +} + +#define FDT_SW_MAGIC (~FDT_MAGIC) + +#endif /* LIBFDT_INTERNAL_H */ diff --git a/vendor/riscv/riscv-isa-sim/fesvr/byteorder.h b/vendor/riscv/riscv-isa-sim/fesvr/byteorder.h new file mode 100644 index 0000000000..2b1dbf981c --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/fesvr/byteorder.h @@ -0,0 +1,94 @@ +// See LICENSE for license details. + +#ifndef _RISCV_BYTEORDER_H +#define _RISCV_BYTEORDER_H + +#include "config.h" +#include <stdint.h> + +static inline uint8_t swap(uint8_t n) { return n; } +static inline uint16_t swap(uint16_t n) { return (n >> 8) | (n << 8); } +static inline uint32_t swap(uint32_t n) { return (swap(uint16_t(n)) << 16) | swap(uint16_t(n >> 16)); } +static inline uint64_t swap(uint64_t n) { return (uint64_t(swap(uint32_t(n))) << 32) | swap(uint32_t(n >> 32)); } +static inline int8_t swap(int8_t n) { return n; } +static inline int16_t swap(int16_t n) { return int16_t(swap(uint16_t(n))); } +static inline int32_t swap(int32_t n) { return int32_t(swap(uint32_t(n))); } +static inline int64_t swap(int64_t n) { return int64_t(swap(uint64_t(n))); } + +#ifdef WORDS_BIGENDIAN +template<typename T> static inline T from_be(T n) { return n; } +template<typename T> static inline T to_be(T n) { return n; } +template<typename T> static inline T from_le(T n) { return swap(n); } +template<typename T> static inline T to_le(T n) { return swap(n); } +#else +template<typename T> static inline T from_le(T n) { return n; } +template<typename T> static inline T to_le(T n) { return n; } +template<typename T> static inline T from_be(T n) { return swap(n); } +template<typename T> static inline T to_be(T n) { return swap(n); } +#endif + +// Wrapper to mark a value as target endian, to guide conversion code + +template<typename T> class base_endian { + + protected: + T value; + + base_endian(T n) : value(n) {} + + public: + // Setting to and testing against zero never needs swapping + base_endian() : value(0) {} + bool operator!() { return !value; } + + // Bitwise logic operations can be performed without swapping + base_endian& operator|=(const base_endian& rhs) { value |= rhs.value; return *this; } + base_endian& operator&=(const base_endian& rhs) { value &= rhs.value; return *this; } + base_endian& operator^=(const base_endian& rhs) { value ^= rhs.value; return *this; } + + inline T from_be() { return ::from_be(value); } + inline T from_le() { return ::from_le(value); } +}; + +template<typename T> class target_endian : public base_endian<T> { + protected: + target_endian(T n) : base_endian<T>(n) {} + + public: + target_endian() {} + + static inline target_endian to_be(T n) { return target_endian(::to_be(n)); } + static inline target_endian to_le(T n) { return target_endian(::to_le(n)); } + + // Useful values over which swapping is identity + static const target_endian zero; + static const target_endian all_ones; +}; + +template<typename T> const target_endian<T> target_endian<T>::zero = target_endian(T(0)); +template<typename T> const target_endian<T> target_endian<T>::all_ones = target_endian(~T(0)); + + +// Specializations with implicit conversions (no swap information needed) + +template<> class target_endian<uint8_t> : public base_endian<uint8_t> { + public: + target_endian() {} + target_endian(uint8_t n) : base_endian<uint8_t>(n) {} + operator uint8_t() { return value; } + + static inline target_endian to_be(uint8_t n) { return target_endian(n); } + static inline target_endian to_le(uint8_t n) { return target_endian(n); } +}; + +template<> class target_endian<int8_t> : public base_endian<int8_t> { + public: + target_endian() {} + target_endian(int8_t n) : base_endian<int8_t>(n) {} + operator int8_t() { return value; } + + static inline target_endian to_be(int8_t n) { return target_endian(n); } + static inline target_endian to_le(int8_t n) { return target_endian(n); } +}; + +#endif diff --git a/vendor/riscv/riscv-isa-sim/fesvr/context.cc b/vendor/riscv/riscv-isa-sim/fesvr/context.cc new file mode 100644 index 0000000000..1dceeec825 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/fesvr/context.cc @@ -0,0 +1,115 @@ +#include "context.h" +#include <assert.h> +#include <sched.h> +#include <stdlib.h> + +static __thread context_t* cur; + +context_t::context_t() + : creator(NULL), func(NULL), arg(NULL), +#ifndef USE_UCONTEXT + mutex(PTHREAD_MUTEX_INITIALIZER), + cond(PTHREAD_COND_INITIALIZER), flag(0) +#else + context(new ucontext_t) +#endif +{ +} + +#ifdef USE_UCONTEXT +#ifndef GLIBC_64BIT_PTR_BUG +void context_t::wrapper(context_t* ctx) +{ +#else +void context_t::wrapper(unsigned int hi, unsigned int lo) +{ + context_t* ctx = reinterpret_cast<context_t*>(static_cast<unsigned long>(lo) | (static_cast<unsigned long>(hi) << 32)); +#endif + ctx->creator->switch_to(); + ctx->func(ctx->arg); +} +#else +void* context_t::wrapper(void* a) +{ + context_t* ctx = static_cast<context_t*>(a); + cur = ctx; + ctx->creator->switch_to(); + + ctx->func(ctx->arg); + return NULL; +} +#endif + +void context_t::init(void (*f)(void*), void* a) +{ + func = f; + arg = a; + creator = current(); + +#ifdef USE_UCONTEXT + getcontext(context.get()); + context->uc_link = creator->context.get(); + context->uc_stack.ss_size = 1024 * 1024; + context->uc_stack.ss_sp = new void*[context->uc_stack.ss_size/sizeof(void*)]; +#ifndef GLIBC_64BIT_PTR_BUG + makecontext(context.get(), (void(*)(void))&context_t::wrapper, 1, this); +#else + unsigned int hi(reinterpret_cast<unsigned long>(this) >> 32); + unsigned int lo(reinterpret_cast<unsigned long>(this)); + makecontext(context.get(), (void(*)(void))&context_t::wrapper, 2, hi, lo); +#endif + switch_to(); +#else + assert(flag == 0); + + pthread_mutex_lock(&creator->mutex); + creator->flag = 0; + if (pthread_create(&thread, NULL, &context_t::wrapper, this) != 0) + abort(); + pthread_detach(thread); + while (!creator->flag) + pthread_cond_wait(&creator->cond, &creator->mutex); + pthread_mutex_unlock(&creator->mutex); +#endif +} + +context_t::~context_t() +{ + assert(this != cur); +} + +void context_t::switch_to() +{ + assert(this != cur); +#ifdef USE_UCONTEXT + context_t* prev = cur; + cur = this; + if (swapcontext(prev->context.get(), context.get()) != 0) + abort(); +#else + cur->flag = 0; + this->flag = 1; + pthread_mutex_lock(&this->mutex); + pthread_cond_signal(&this->cond); + pthread_mutex_unlock(&this->mutex); + pthread_mutex_lock(&cur->mutex); + while (!cur->flag) + pthread_cond_wait(&cur->cond, &cur->mutex); + pthread_mutex_unlock(&cur->mutex); +#endif +} + +context_t* context_t::current() +{ + if (cur == NULL) + { + cur = new context_t; +#ifdef USE_UCONTEXT + getcontext(cur->context.get()); +#else + cur->thread = pthread_self(); + cur->flag = 1; +#endif + } + return cur; +} diff --git a/vendor/riscv/riscv-isa-sim/fesvr/context.h b/vendor/riscv/riscv-isa-sim/fesvr/context.h new file mode 100644 index 0000000000..18bf50ef8d --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/fesvr/context.h @@ -0,0 +1,54 @@ +#ifndef _HTIF_CONTEXT_H +#define _HTIF_CONTEXT_H + +// A replacement for ucontext.h, which is sadly deprecated. + +#include <pthread.h> + +#if defined(__GLIBC__) +# undef USE_UCONTEXT +# define USE_UCONTEXT +# include <ucontext.h> +# include <memory> +#include <limits.h> + +#if (ULONG_MAX > UINT_MAX) // 64-bit systems only +#if (100*GLIB_MAJOR_VERSION+GLIB_MINOR_VERSION < 208) +#define GLIBC_64BIT_PTR_BUG +static_assert (sizeof(unsigned int) == 4, "uint size doesn't match expected 32bit"); +static_assert (sizeof(unsigned long) == 8, "ulong size doesn't match expected 64bit"); +static_assert (sizeof(void*) == 8, "ptr size doesn't match expected 64bit"); +#endif +#endif /* ULONG_MAX > UINT_MAX */ + +#endif + +class context_t +{ + public: + context_t(); + ~context_t(); + void init(void (*func)(void*), void* arg); + void switch_to(); + static context_t* current(); + private: + context_t* creator; + void (*func)(void*); + void* arg; +#ifdef USE_UCONTEXT + std::unique_ptr<ucontext_t> context; +#ifndef GLIBC_64BIT_PTR_BUG + static void wrapper(context_t*); +#else + static void wrapper(unsigned int, unsigned int); +#endif +#else + pthread_t thread; + pthread_mutex_t mutex; + pthread_cond_t cond; + volatile int flag; + static void* wrapper(void*); +#endif +}; + +#endif diff --git a/vendor/riscv/riscv-isa-sim/fesvr/device.cc b/vendor/riscv/riscv-isa-sim/fesvr/device.cc new file mode 100644 index 0000000000..cbfdb5046f --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/fesvr/device.cc @@ -0,0 +1,154 @@ +#include "device.h" +#include "term.h" +#include "memif.h" +#include <cassert> +#include <algorithm> +#include <climits> +#include <iostream> +#include <thread> +#include <fcntl.h> +#include <unistd.h> +#include <sys/stat.h> +using namespace std::placeholders; + +device_t::device_t() + : command_handlers(command_t::MAX_COMMANDS), + command_names(command_t::MAX_COMMANDS) +{ + for (size_t cmd = 0; cmd < command_t::MAX_COMMANDS; cmd++) + register_command(cmd, std::bind(&device_t::handle_null_command, this, _1), ""); + register_command(command_t::MAX_COMMANDS-1, std::bind(&device_t::handle_identify, this, _1), "identity"); +} + +void device_t::register_command(size_t cmd, command_func_t handler, const char* name) +{ + assert(cmd < command_t::MAX_COMMANDS); + assert(strlen(name) < IDENTITY_SIZE); + command_handlers[cmd] = handler; + command_names[cmd] = name; +} + +void device_t::handle_command(command_t cmd) +{ + command_handlers[cmd.cmd()](cmd); +} + +void device_t::handle_null_command(command_t) +{ +} + +void device_t::handle_identify(command_t cmd) +{ + size_t what = cmd.payload() % command_t::MAX_COMMANDS; + uint64_t addr = cmd.payload() / command_t::MAX_COMMANDS; + + char id[IDENTITY_SIZE] = {0}; + if (what == command_t::MAX_COMMANDS-1) + { + assert(strlen(identity()) < IDENTITY_SIZE); + strcpy(id, identity()); + } + else + strcpy(id, command_names[what].c_str()); + + cmd.memif().write(addr, IDENTITY_SIZE, id); + cmd.respond(1); +} + +bcd_t::bcd_t() +{ + register_command(0, std::bind(&bcd_t::handle_read, this, _1), "read"); + register_command(1, std::bind(&bcd_t::handle_write, this, _1), "write"); +} + +void bcd_t::handle_read(command_t cmd) +{ + pending_reads.push(cmd); +} + +void bcd_t::handle_write(command_t cmd) +{ + canonical_terminal_t::write(cmd.payload()); +} + +void bcd_t::tick() +{ + int ch; + if (!pending_reads.empty() && (ch = canonical_terminal_t::read()) != -1) + { + pending_reads.front().respond(0x100 | ch); + pending_reads.pop(); + } +} + +disk_t::disk_t(const char* fn) +{ + fd = ::open(fn, O_RDWR); + if (fd < 0) + throw std::runtime_error("could not open " + std::string(fn)); + + register_command(0, std::bind(&disk_t::handle_read, this, _1), "read"); + register_command(1, std::bind(&disk_t::handle_write, this, _1), "write"); + + struct stat st; + if (fstat(fd, &st) < 0) + throw std::runtime_error("could not stat " + std::string(fn)); + + size = st.st_size; + id = "disk size=" + std::to_string(size); +} + +disk_t::~disk_t() +{ + close(fd); +} + +void disk_t::handle_read(command_t cmd) +{ + request_t req; + cmd.memif().read(cmd.payload(), sizeof(req), &req); + + std::vector<uint8_t> buf(req.size); + if ((size_t)::pread(fd, buf.data(), buf.size(), req.offset) != req.size) + throw std::runtime_error("could not read " + id + " @ " + std::to_string(req.offset)); + + cmd.memif().write(req.addr, buf.size(), buf.data()); + cmd.respond(req.tag); +} + +void disk_t::handle_write(command_t cmd) +{ + request_t req; + cmd.memif().read(cmd.payload(), sizeof(req), &req); + + std::vector<uint8_t> buf(req.size); + cmd.memif().read(req.addr, buf.size(), buf.data()); + + if ((size_t)::pwrite(fd, buf.data(), buf.size(), req.offset) != req.size) + throw std::runtime_error("could not write " + id + " @ " + std::to_string(req.offset)); + + cmd.respond(req.tag); +} + +device_list_t::device_list_t() + : devices(command_t::MAX_COMMANDS, &null_device), num_devices(0) +{ +} + +void device_list_t::register_device(device_t* dev) +{ + num_devices++; + assert(num_devices < command_t::MAX_DEVICES); + devices[num_devices-1] = dev; +} + +void device_list_t::handle_command(command_t cmd) +{ + devices[cmd.device()]->handle_command(cmd); +} + +void device_list_t::tick() +{ + for (size_t i = 0; i < num_devices; i++) + devices[i]->tick(); +} diff --git a/vendor/riscv/riscv-isa-sim/fesvr/device.h b/vendor/riscv/riscv-isa-sim/fesvr/device.h new file mode 100644 index 0000000000..639b837481 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/fesvr/device.h @@ -0,0 +1,119 @@ +#ifndef _DEVICE_H +#define _DEVICE_H + +#include <vector> +#include <queue> +#include <cstring> +#include <string> +#include <functional> +#include <cstdint> + +class memif_t; + +class command_t +{ + public: + typedef std::function<void(uint64_t)> callback_t; + command_t(memif_t& memif, uint64_t tohost, callback_t cb) + : _memif(memif), tohost(tohost), cb(cb) {} + + memif_t& memif() { return _memif; } + uint8_t device() { return tohost >> 56; } + uint8_t cmd() { return tohost >> 48; } + uint64_t payload() { return tohost << 16 >> 16; } + void respond(uint64_t resp) { cb((tohost >> 48 << 48) | (resp << 16 >> 16)); } + + static const size_t MAX_COMMANDS = 256; + static const size_t MAX_DEVICES = 256; + + private: + memif_t& _memif; + uint64_t tohost; + callback_t cb; +}; + +class device_t +{ + public: + device_t(); + virtual ~device_t() {} + virtual const char* identity() = 0; + virtual void tick() {} + + void handle_command(command_t cmd); + + protected: + typedef std::function<void(command_t)> command_func_t; + void register_command(size_t, command_func_t, const char*); + + private: + device_t& operator = (const device_t&); // disallow + device_t(const device_t&); // disallow + + static const size_t IDENTITY_SIZE = 64; + void handle_null_command(command_t cmd); + void handle_identify(command_t cmd); + + std::vector<command_func_t> command_handlers; + std::vector<std::string> command_names; +}; + +class bcd_t : public device_t +{ + public: + bcd_t(); + const char* identity() { return "bcd"; } + void tick(); + + private: + void handle_read(command_t cmd); + void handle_write(command_t cmd); + + std::queue<command_t> pending_reads; +}; + +class disk_t : public device_t +{ + public: + disk_t(const char* fn); + ~disk_t(); + const char* identity() { return id.c_str(); } + + private: + struct request_t + { + uint64_t addr; + uint64_t offset; + uint64_t size; + uint64_t tag; + }; + + void handle_read(command_t cmd); + void handle_write(command_t cmd); + + std::string id; + size_t size; + int fd; +}; + +class null_device_t : public device_t +{ + public: + const char* identity() { return ""; } +}; + +class device_list_t +{ + public: + device_list_t(); + void register_device(device_t* dev); + void handle_command(command_t cmd); + void tick(); + + private: + std::vector<device_t*> devices; + null_device_t null_device; + size_t num_devices; +}; + +#endif diff --git a/vendor/riscv/riscv-isa-sim/fesvr/dtm.cc b/vendor/riscv/riscv-isa-sim/fesvr/dtm.cc new file mode 100644 index 0000000000..0f810e7233 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/fesvr/dtm.cc @@ -0,0 +1,641 @@ +#include "dtm.h" +#include "riscv/debug_defines.h" +#include <stdlib.h> +#include <stdio.h> +#include <string.h> +#include <assert.h> +#include <pthread.h> +#include <stdexcept> + +#define RV_X(x, s, n) \ + (((x) >> (s)) & ((1 << (n)) - 1)) +#define ENCODE_ITYPE_IMM(x) \ + (RV_X(x, 0, 12) << 20) +#define ENCODE_STYPE_IMM(x) \ + ((RV_X(x, 0, 5) << 7) | (RV_X(x, 5, 7) << 25)) +#define ENCODE_SBTYPE_IMM(x) \ + ((RV_X(x, 1, 4) << 8) | (RV_X(x, 5, 6) << 25) | (RV_X(x, 11, 1) << 7) | (RV_X(x, 12, 1) << 31)) +#define ENCODE_UTYPE_IMM(x) \ + (RV_X(x, 12, 20) << 12) +#define ENCODE_UJTYPE_IMM(x) \ + ((RV_X(x, 1, 10) << 21) | (RV_X(x, 11, 1) << 20) | (RV_X(x, 12, 8) << 12) | (RV_X(x, 20, 1) << 31)) + +#define LOAD(xlen, dst, base, imm) \ + (((xlen) == 64 ? 0x00003003 : 0x00002003) \ + | ((dst) << 7) | ((base) << 15) | (uint32_t)ENCODE_ITYPE_IMM(imm)) +#define STORE(xlen, src, base, imm) \ + (((xlen) == 64 ? 0x00003023 : 0x00002023) \ + | ((src) << 20) | ((base) << 15) | (uint32_t)ENCODE_STYPE_IMM(imm)) +#define JUMP(there, here) (0x6f | (uint32_t)ENCODE_UJTYPE_IMM((there) - (here))) +#define BNE(r1, r2, there, here) (0x1063 | ((r1) << 15) | ((r2) << 20) | (uint32_t)ENCODE_SBTYPE_IMM((there) - (here))) +#define ADDI(dst, src, imm) (0x13 | ((dst) << 7) | ((src) << 15) | (uint32_t)ENCODE_ITYPE_IMM(imm)) +#define SRL(dst, src, sh) (0x5033 | ((dst) << 7) | ((src) << 15) | ((sh) << 20)) +#define FENCE_I 0x100f +#define EBREAK 0x00100073 +#define X0 0 +#define S0 8 +#define S1 9 + +#define AC_AR_REGNO(x) ((0x1000 | x) << AC_ACCESS_REGISTER_REGNO_OFFSET) +#define AC_AR_SIZE(x) (((x == 128)? 4 : (x == 64 ? 3 : 2)) << AC_ACCESS_REGISTER_AARSIZE_OFFSET) + +#define WRITE 1 +#define SET 2 +#define CLEAR 3 +#define CSRRx(type, dst, csr, src) (0x73 | ((type) << 12) | ((dst) << 7) | ((src) << 15) | (uint32_t)((csr) << 20)) + +#define RUN_AC_OR_DIE(a, b, c, d, e) { \ + uint32_t cmderr = run_abstract_command(a, b, c, d, e); \ + if (cmderr) { \ + die(cmderr); \ + } \ + } + +uint32_t dtm_t::do_command(dtm_t::req r) +{ + req_buf = r; + target->switch_to(); + assert(resp_buf.resp == 0); + return resp_buf.data; +} + +uint32_t dtm_t::read(uint32_t addr) +{ + return do_command((req){addr, 1, 0}); +} + +uint32_t dtm_t::write(uint32_t addr, uint32_t data) +{ + return do_command((req){addr, 2, data}); +} + +void dtm_t::nop() +{ + do_command((req){0, 0, 0}); +} + +void dtm_t::select_hart(int hartsel) { + int dmcontrol = read(DM_DMCONTROL); + write (DM_DMCONTROL, set_field(dmcontrol, DM_DMCONTROL_HASEL, hartsel)); + current_hart = hartsel; +} + +int dtm_t::enumerate_harts() { + int max_hart = (1 << DM_DMCONTROL_HASEL_LENGTH) - 1; + write(DM_DMCONTROL, set_field(read(DM_DMCONTROL), DM_DMCONTROL_HASEL, max_hart)); + read(DM_DMSTATUS); + max_hart = get_field(read(DM_DMCONTROL), DM_DMCONTROL_HASEL); + + int hartsel; + for (hartsel = 0; hartsel <= max_hart; hartsel++) { + select_hart(hartsel); + int dmstatus = read(DM_DMSTATUS); + if (get_field(dmstatus, DM_DMSTATUS_ANYNONEXISTENT)) + break; + } + return hartsel; +} + +void dtm_t::halt(int hartsel) +{ + if (running) { + write(DM_DMCONTROL, DM_DMCONTROL_DMACTIVE); + // Read dmstatus to avoid back-to-back writes to dmcontrol. + read(DM_DMSTATUS); + } + + int dmcontrol = DM_DMCONTROL_HALTREQ | DM_DMCONTROL_DMACTIVE; + dmcontrol = set_field(dmcontrol, DM_DMCONTROL_HASEL, hartsel); + write(DM_DMCONTROL, dmcontrol); + int dmstatus; + do { + dmstatus = read(DM_DMSTATUS); + } while(get_field(dmstatus, DM_DMSTATUS_ALLHALTED) == 0); + dmcontrol &= ~DM_DMCONTROL_HALTREQ; + write(DM_DMCONTROL, dmcontrol); + // Read dmstatus to avoid back-to-back writes to dmcontrol. + read(DM_DMSTATUS); + current_hart = hartsel; +} + +void dtm_t::resume(int hartsel) +{ + int dmcontrol = DM_DMCONTROL_RESUMEREQ | DM_DMCONTROL_DMACTIVE; + dmcontrol = set_field(dmcontrol, DM_DMCONTROL_HASEL, hartsel); + write(DM_DMCONTROL, dmcontrol); + int dmstatus; + do { + dmstatus = read(DM_DMSTATUS); + } while (get_field(dmstatus, DM_DMSTATUS_ALLRESUMEACK) == 0); + dmcontrol &= ~DM_DMCONTROL_RESUMEREQ; + write(DM_DMCONTROL, dmcontrol); + // Read dmstatus to avoid back-to-back writes to dmcontrol. + read(DM_DMSTATUS); + current_hart = hartsel; + + if (running) { + write(DM_DMCONTROL, DM_DMCONTROL_DMACTIVE); + // Read dmstatus to avoid back-to-back writes to dmcontrol. + read(DM_DMSTATUS); + } +} + +uint64_t dtm_t::save_reg(unsigned regno) +{ + uint32_t data[xlen/(8*4)]; + uint32_t command = AC_ACCESS_REGISTER_TRANSFER | AC_AR_SIZE(xlen) | AC_AR_REGNO(regno); + RUN_AC_OR_DIE(command, 0, 0, data, xlen / (8*4)); + + uint64_t result = data[0]; + if (xlen > 32) { + result |= ((uint64_t)data[1]) << 32; + } + return result; +} + +void dtm_t::restore_reg(unsigned regno, uint64_t val) +{ + uint32_t data[xlen/(8*4)]; + data[0] = (uint32_t) val; + if (xlen > 32) { + data[1] = (uint32_t) (val >> 32); + } + + uint32_t command = AC_ACCESS_REGISTER_TRANSFER | + AC_ACCESS_REGISTER_WRITE | + AC_AR_SIZE(xlen) | + AC_AR_REGNO(regno); + + RUN_AC_OR_DIE(command, 0, 0, data, xlen / (8*4)); + +} + +uint32_t dtm_t::run_abstract_command(uint32_t command, + const uint32_t program[], size_t program_n, + uint32_t data[], size_t data_n) +{ + assert(program_n <= ram_words); + assert(data_n <= data_words); + + for (size_t i = 0; i < program_n; i++) { + write(DM_PROGBUF0 + i, program[i]); + } + + if (get_field(command, AC_ACCESS_REGISTER_WRITE) && + get_field(command, AC_ACCESS_REGISTER_TRANSFER)) { + for (size_t i = 0; i < data_n; i++) { + write(DM_DATA0 + i, data[i]); + } + } + + write(DM_COMMAND, command); + + // Wait for not busy and then check for error. + uint32_t abstractcs; + do { + abstractcs = read(DM_ABSTRACTCS); + } while (abstractcs & DM_ABSTRACTCS_BUSY); + + if ((get_field(command, AC_ACCESS_REGISTER_WRITE) == 0) && + get_field(command, AC_ACCESS_REGISTER_TRANSFER)) { + for (size_t i = 0; i < data_n; i++){ + data[i] = read(DM_DATA0 + i); + } + } + + return get_field(abstractcs, DM_ABSTRACTCS_CMDERR); + +} + +size_t dtm_t::chunk_align() +{ + return xlen / 8; +} + +void dtm_t::read_chunk(uint64_t taddr, size_t len, void* dst) +{ + uint32_t prog[ram_words]; + uint32_t data[data_words]; + + uint8_t * curr = (uint8_t*) dst; + + halt(current_hart); + + uint64_t s0 = save_reg(S0); + uint64_t s1 = save_reg(S1); + + prog[0] = LOAD(xlen, S1, S0, 0); + prog[1] = ADDI(S0, S0, xlen/8); + prog[2] = EBREAK; + + data[0] = (uint32_t) taddr; + if (xlen > 32) { + data[1] = (uint32_t) (taddr >> 32); + } + + // Write s0 with the address, then execute program buffer. + // This will get S1 with the data and increment s0. + uint32_t command = AC_ACCESS_REGISTER_TRANSFER | + AC_ACCESS_REGISTER_WRITE | + AC_ACCESS_REGISTER_POSTEXEC | + AC_AR_SIZE(xlen) | + AC_AR_REGNO(S0); + + RUN_AC_OR_DIE(command, prog, 3, data, xlen/(4*8)); + + // TODO: could use autoexec here. + for (size_t i = 0; i < (len * 8 / xlen); i++){ + command = AC_ACCESS_REGISTER_TRANSFER | + AC_AR_SIZE(xlen) | + AC_AR_REGNO(S1); + if ((i + 1) < (len * 8 / xlen)) { + command |= AC_ACCESS_REGISTER_POSTEXEC; + } + + RUN_AC_OR_DIE(command, 0, 0, data, xlen/(4*8)); + + memcpy(curr, data, xlen/8); + curr += xlen/8; + } + + restore_reg(S0, s0); + restore_reg(S1, s1); + + resume(current_hart); + +} + +void dtm_t::write_chunk(uint64_t taddr, size_t len, const void* src) +{ + uint32_t prog[ram_words]; + uint32_t data[data_words]; + + const uint8_t * curr = (const uint8_t*) src; + + halt(current_hart); + + uint64_t s0 = save_reg(S0); + uint64_t s1 = save_reg(S1); + + prog[0] = STORE(xlen, S1, S0, 0); + prog[1] = ADDI(S0, S0, xlen/8); + prog[2] = EBREAK; + + data[0] = (uint32_t) taddr; + if (xlen > 32) { + data[1] = (uint32_t) (taddr >> 32); + } + + // Write the program (not used yet). + // Write s0 with the address. + uint32_t command = AC_ACCESS_REGISTER_TRANSFER | + AC_ACCESS_REGISTER_WRITE | + AC_AR_SIZE(xlen) | + AC_AR_REGNO(S0); + + RUN_AC_OR_DIE(command, prog, 3, data, xlen/(4*8)); + + // Use Autoexec for more than one word of transfer. + // Write S1 with data, then execution stores S1 to + // 0(S0) and increments S0. + // Each time we write XLEN bits. + memcpy(data, curr, xlen/8); + curr += xlen/8; + + command = AC_ACCESS_REGISTER_TRANSFER | + AC_ACCESS_REGISTER_POSTEXEC | + AC_ACCESS_REGISTER_WRITE | + AC_AR_SIZE(xlen) | + AC_AR_REGNO(S1); + + RUN_AC_OR_DIE(command, 0, 0, data, xlen/(4*8)); + + uint32_t abstractcs; + for (size_t i = 1; i < (len * 8 / xlen); i++){ + if (i == 1) { + write(DM_ABSTRACTAUTO, 1 << DM_ABSTRACTAUTO_AUTOEXECDATA_OFFSET); + } + memcpy(data, curr, xlen/8); + curr += xlen/8; + if (xlen == 64) { + write(DM_DATA0 + 1, data[1]); + } + write(DM_DATA0, data[0]); //Triggers a command w/ autoexec. + + do { + abstractcs = read(DM_ABSTRACTCS); + } while (abstractcs & DM_ABSTRACTCS_BUSY); + if ( get_field(abstractcs, DM_ABSTRACTCS_CMDERR)) { + die(get_field(abstractcs, DM_ABSTRACTCS_CMDERR)); + } + } + if ((len * 8 / xlen) > 1) { + write(DM_ABSTRACTAUTO, 0); + } + + restore_reg(S0, s0); + restore_reg(S1, s1); + resume(current_hart); +} + +void dtm_t::die(uint32_t cmderr) +{ + const char * codes[] = { + "OK", + "BUSY", + "NOT_SUPPORTED", + "EXCEPTION", + "HALT/RESUME" + }; + const char * msg; + if (cmderr < (sizeof(codes) / sizeof(*codes))){ + msg = codes[cmderr]; + } else { + msg = "OTHER"; + } + //throw std::runtime_error("Debug Abstract Command Error #" + std::to_string(cmderr) + "(" + msg + ")"); + printf("ERROR: %s:%d, Debug Abstract Command Error #%d (%s)", __FILE__, __LINE__, cmderr, msg); + printf("ERROR: %s:%d, Should die, but allowing simulation to continue and fail.", __FILE__, __LINE__); + write(DM_ABSTRACTCS, DM_ABSTRACTCS_CMDERR); + +} + +void dtm_t::clear_chunk(uint64_t taddr, size_t len) +{ + uint32_t prog[ram_words]; + uint32_t data[data_words]; + + halt(current_hart); + uint64_t s0 = save_reg(S0); + uint64_t s1 = save_reg(S1); + + uint32_t command; + + // S0 = Addr + data[0] = (uint32_t) taddr; + data[1] = (uint32_t) (taddr >> 32); + command = AC_ACCESS_REGISTER_TRANSFER | + AC_ACCESS_REGISTER_WRITE | + AC_AR_SIZE(xlen) | + AC_AR_REGNO(S0); + RUN_AC_OR_DIE(command, 0, 0, data, xlen/(4*8)); + + // S1 = Addr + len, loop until S0 = S1 + prog[0] = STORE(xlen, X0, S0, 0); + prog[1] = ADDI(S0, S0, xlen/8); + prog[2] = BNE(S0, S1, 0*4, 2*4); + prog[3] = EBREAK; + + data[0] = (uint32_t) (taddr + len); + data[1] = (uint32_t) ((taddr + len) >> 32); + command = AC_ACCESS_REGISTER_TRANSFER | + AC_ACCESS_REGISTER_WRITE | + AC_AR_SIZE(xlen) | + AC_AR_REGNO(S1) | + AC_ACCESS_REGISTER_POSTEXEC; + RUN_AC_OR_DIE(command, prog, 4, data, xlen/(4*8)); + + restore_reg(S0, s0); + restore_reg(S1, s1); + + resume(current_hart); +} + +uint64_t dtm_t::write_csr(unsigned which, uint64_t data) +{ + return modify_csr(which, data, WRITE); +} + +uint64_t dtm_t::set_csr(unsigned which, uint64_t data) +{ + return modify_csr(which, data, SET); +} + +uint64_t dtm_t::clear_csr(unsigned which, uint64_t data) +{ + return modify_csr(which, data, CLEAR); +} + +uint64_t dtm_t::read_csr(unsigned which) +{ + return set_csr(which, 0); +} + +uint64_t dtm_t::modify_csr(unsigned which, uint64_t data, uint32_t type) +{ + halt(current_hart); + + // This code just uses DSCRATCH to save S0 + // and data_base to do the transfer so we don't + // need to run more commands to save and restore + // S0. + uint32_t prog[] = { + CSRRx(WRITE, S0, CSR_DSCRATCH0, S0), + LOAD(xlen, S0, X0, data_base), + CSRRx(type, S0, which, S0), + STORE(xlen, S0, X0, data_base), + CSRRx(WRITE, S0, CSR_DSCRATCH0, S0), + EBREAK + }; + + //TODO: Use transfer = 0. For now both HW and OpenOCD + // ignore transfer bit, so use "store to X0" NOOP. + // We sort of need this anyway because run_abstract_command + // needs the DATA to be written so may as well use the WRITE flag. + + uint32_t adata[] = {(uint32_t) data, + (uint32_t) (data >> 32)}; + + uint32_t command = AC_ACCESS_REGISTER_POSTEXEC | + AC_ACCESS_REGISTER_TRANSFER | + AC_ACCESS_REGISTER_WRITE | + AC_AR_SIZE(xlen) | + AC_AR_REGNO(X0); + + RUN_AC_OR_DIE(command, prog, sizeof(prog) / sizeof(*prog), adata, xlen/(4*8)); + + uint64_t res = read(DM_DATA0);//adata[0]; + if (xlen == 64) + res |= read(DM_DATA0 + 1);//((uint64_t) adata[1]) << 32; + + resume(current_hart); + return res; +} + +size_t dtm_t::chunk_max_size() +{ + // Arbitrary choice. 4k Page size seems reasonable. + return 4096; +} + +uint32_t dtm_t::get_xlen() +{ + // Attempt to read S0 to find out what size it is. + // You could also attempt to run code, but you need to save registers + // to do that anyway. If what you really want to do is figure out + // the size of S0 so you can save it later, then do that. + uint32_t command = AC_ACCESS_REGISTER_TRANSFER | AC_AR_REGNO(S0); + uint32_t cmderr; + + const uint32_t prog[] = {}; + uint32_t data[] = {}; + + cmderr = run_abstract_command(command | AC_AR_SIZE(128), prog, 0, data, 0); + if (cmderr == 0){ + throw std::runtime_error("FESVR DTM Does not support 128-bit"); + abort(); + return 128; + } + write(DM_ABSTRACTCS, DM_ABSTRACTCS_CMDERR); + + cmderr = run_abstract_command(command | AC_AR_SIZE(64), prog, 0, data, 0); + if (cmderr == 0){ + return 64; + } + write(DM_ABSTRACTCS, DM_ABSTRACTCS_CMDERR); + + cmderr = run_abstract_command(command | AC_AR_SIZE(32), prog, 0, data, 0); + if (cmderr == 0){ + return 32; + } + + throw std::runtime_error("FESVR DTM can't determine XLEN. Aborting"); +} + +void dtm_t::fence_i() +{ + halt(current_hart); + + const uint32_t prog[] = { + FENCE_I, + EBREAK + }; + + //TODO: Use the transfer = 0. + uint32_t command = AC_ACCESS_REGISTER_POSTEXEC | + AC_ACCESS_REGISTER_TRANSFER | + AC_ACCESS_REGISTER_WRITE | + AC_AR_SIZE(xlen) | + AC_AR_REGNO(X0); + + RUN_AC_OR_DIE(command, prog, sizeof(prog)/sizeof(*prog), 0, 0); + + resume(current_hart); + +} + +void host_thread_main(void* arg) +{ + ((dtm_t*)arg)->producer_thread(); +} + +void dtm_t::reset() +{ + for (int hartsel = 0; hartsel < num_harts; hartsel ++ ){ + select_hart(hartsel); + // this command also does a halt and resume + fence_i(); + // after this command, the hart will run from _start. + write_csr(0x7b1, get_entry_point()); + } + // In theory any hart can handle the memory accesses, + // this will enforce that hart 0 handles them. + select_hart(0); + read(DM_DMSTATUS); +} + +void dtm_t::idle() +{ + for (int idle_cycles = 0; idle_cycles < max_idle_cycles; idle_cycles++) + nop(); +} + +void dtm_t::producer_thread() +{ + // Learn about the Debug Module and assert things we + // depend on in this code. + + // Enable the debugger. + write(DM_DMCONTROL, DM_DMCONTROL_DMACTIVE); + // Poll until the debugger agrees it's enabled. + while ((read(DM_DMCONTROL) & DM_DMCONTROL_DMACTIVE) == 0) ; + + // These are checked every time we run an abstract command. + uint32_t abstractcs = read(DM_ABSTRACTCS); + ram_words = get_field(abstractcs, DM_ABSTRACTCS_PROGBUFSIZE); + data_words = get_field(abstractcs, DM_ABSTRACTCS_DATACOUNT); + + // These things are only needed for the 'modify_csr' function. + // That could be re-written to not use these at some performance + // overhead. + uint32_t hartinfo = read(DM_HARTINFO); + assert(get_field(hartinfo, DM_HARTINFO_NSCRATCH) > 0); + assert(get_field(hartinfo, DM_HARTINFO_DATAACCESS)); + + data_base = get_field(hartinfo, DM_HARTINFO_DATAADDR); + + num_harts = enumerate_harts(); + halt(0); + // Note: We don't support systems with heterogeneous XLEN. + // It's possible to do this at the cost of extra cycles. + xlen = get_xlen(); + resume(0); + + running = true; + + htif_t::run(); + + while (true) + nop(); +} + +void dtm_t::start_host_thread() +{ + req_wait = false; + resp_wait = false; + + target = context_t::current(); + host.init(host_thread_main, this); + host.switch_to(); +} + +dtm_t::dtm_t(int argc, char** argv) + : htif_t(argc, argv), running(false) +{ + start_host_thread(); +} + +dtm_t::~dtm_t() +{ +} + +void dtm_t::tick( + bool req_ready, + bool resp_valid, + resp resp_bits) +{ + if (!resp_wait) { + if (!req_wait) { + req_wait = true; + } else if (req_ready) { + req_wait = false; + resp_wait = true; + } + } + + if (resp_valid) { + assert(resp_wait); + resp_wait = false; + + resp_buf = resp_bits; + // update the target with the current context + target = context_t::current(); + host.switch_to(); + } +} + +void dtm_t::return_resp(resp resp_bits){ + resp_buf = resp_bits; + target = context_t::current(); + host.switch_to(); +} diff --git a/vendor/riscv/riscv-isa-sim/fesvr/dtm.h b/vendor/riscv/riscv-isa-sim/fesvr/dtm.h new file mode 100644 index 0000000000..1f5ee3e890 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/fesvr/dtm.h @@ -0,0 +1,117 @@ +#ifndef _ROCKET_DTM_H +#define _ROCKET_DTM_H + +#include "htif.h" +#include "context.h" +#include <stdint.h> +#include <queue> +#include <semaphore.h> +#include <vector> +#include <string> +#include <stdlib.h> + +// abstract debug transport module +class dtm_t : public htif_t +{ + public: + dtm_t(int argc, char**argv); + ~dtm_t(); + + struct req { + uint32_t addr; + uint32_t op; + uint32_t data; + }; + + struct resp { + uint32_t resp; + uint32_t data; + }; + + void tick( + bool req_ready, + bool resp_valid, + resp resp_bits + ); + // Akin to tick, but the target thread returns a response on every invocation + void return_resp( + resp resp_bits + ); + + + bool req_valid() { return req_wait; } + req req_bits() { return req_buf; } + bool resp_ready() { return true; } + + uint32_t read(uint32_t addr); + uint32_t write(uint32_t addr, uint32_t data); + void nop(); + + uint64_t read_csr(unsigned which); + uint64_t write_csr(unsigned which, uint64_t data); + uint64_t clear_csr(unsigned which, uint64_t data); + uint64_t set_csr(unsigned which, uint64_t data); + void fence_i(); + + void producer_thread(); + + protected: + virtual void read_chunk(addr_t taddr, size_t len, void* dst) override; + virtual void write_chunk(addr_t taddr, size_t len, const void* src) override; + virtual void clear_chunk(addr_t taddr, size_t len) override; + virtual size_t chunk_align() override; + virtual size_t chunk_max_size() override; + virtual void reset() override; + virtual void idle() override; + + uint32_t run_abstract_command(uint32_t command, const uint32_t program[], size_t program_n, + uint32_t data[], size_t data_n); + + void die(uint32_t cmderr); + void halt(int); + int enumerate_harts(); + void select_hart(int); + void resume(int); + uint32_t get_data_base() { return data_base; }; + + private: + context_t host; + context_t* target; + pthread_t producer; + sem_t req_produce; + sem_t req_consume; + sem_t resp_produce; + sem_t resp_consume; + req req_buf; + resp resp_buf; + bool running; + + uint64_t save_reg(unsigned regno); + void restore_reg(unsigned regno, uint64_t val); + + uint64_t modify_csr(unsigned which, uint64_t data, uint32_t type); + + bool req_wait; + bool resp_wait; + uint32_t data_base; + + uint32_t xlen; + + static const int max_idle_cycles = 10000; + + size_t ram_words; + size_t data_words; + int num_harts; + int current_hart; + + uint32_t get_xlen(); + uint32_t do_command(dtm_t::req r); + + void parse_args(const std::vector<std::string>& args); + void register_devices(); + void start_host_thread(); + + friend class memif_t; +}; + +#endif diff --git a/vendor/riscv/riscv-isa-sim/fesvr/dummy.cc b/vendor/riscv/riscv-isa-sim/fesvr/dummy.cc new file mode 100644 index 0000000000..a155d3e56c --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/fesvr/dummy.cc @@ -0,0 +1,4 @@ +// See LICENSE for license details. + +// help out poor, C-centric autoconf +extern "C" void libfesvr_is_present() {} diff --git a/vendor/riscv/riscv-isa-sim/fesvr/elf.h b/vendor/riscv/riscv-isa-sim/fesvr/elf.h new file mode 100644 index 0000000000..7b38bf1165 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/fesvr/elf.h @@ -0,0 +1,134 @@ +// See LICENSE for details. + +#ifndef _ELF_H +#define _ELF_H + +#include <stdint.h> + +#define ET_EXEC 2 +#define EM_RISCV 243 +#define EM_NONE 0 +#define EV_CURRENT 1 + +#define IS_ELF(hdr) \ + ((hdr).e_ident[0] == 0x7f && (hdr).e_ident[1] == 'E' && \ + (hdr).e_ident[2] == 'L' && (hdr).e_ident[3] == 'F') + +#define ELF_SWAP(hdr, val) (IS_ELFLE(hdr)? from_le((val)) : from_be((val))) + +#define IS_ELF32(hdr) (IS_ELF(hdr) && (hdr).e_ident[4] == 1) +#define IS_ELF64(hdr) (IS_ELF(hdr) && (hdr).e_ident[4] == 2) +#define IS_ELFLE(hdr) (IS_ELF(hdr) && (hdr).e_ident[5] == 1) +#define IS_ELFBE(hdr) (IS_ELF(hdr) && (hdr).e_ident[5] == 2) +#define IS_ELF_EXEC(hdr) (IS_ELF(hdr) && ELF_SWAP((hdr), (hdr).e_type) == ET_EXEC) +#define IS_ELF_RISCV(hdr) (IS_ELF(hdr) && ELF_SWAP((hdr), (hdr).e_machine) == EM_RISCV) +#define IS_ELF_EM_NONE(hdr) (IS_ELF(hdr) && ELF_SWAP((hdr), (hdr).e_machine) == EM_NONE) +#define IS_ELF_VCURRENT(hdr) (IS_ELF(hdr) && ELF_SWAP((hdr), (hdr).e_version) == EV_CURRENT) + +#define PT_LOAD 1 + +#define SHT_NOBITS 8 + +typedef struct { + uint8_t e_ident[16]; + uint16_t e_type; + uint16_t e_machine; + uint32_t e_version; + uint32_t e_entry; + uint32_t e_phoff; + uint32_t e_shoff; + uint32_t e_flags; + uint16_t e_ehsize; + uint16_t e_phentsize; + uint16_t e_phnum; + uint16_t e_shentsize; + uint16_t e_shnum; + uint16_t e_shstrndx; +} Elf32_Ehdr; + +typedef struct { + uint32_t sh_name; + uint32_t sh_type; + uint32_t sh_flags; + uint32_t sh_addr; + uint32_t sh_offset; + uint32_t sh_size; + uint32_t sh_link; + uint32_t sh_info; + uint32_t sh_addralign; + uint32_t sh_entsize; +} Elf32_Shdr; + +typedef struct +{ + uint32_t p_type; + uint32_t p_offset; + uint32_t p_vaddr; + uint32_t p_paddr; + uint32_t p_filesz; + uint32_t p_memsz; + uint32_t p_flags; + uint32_t p_align; +} Elf32_Phdr; + +typedef struct +{ + uint32_t st_name; + uint32_t st_value; + uint32_t st_size; + uint8_t st_info; + uint8_t st_other; + uint16_t st_shndx; +} Elf32_Sym; + +typedef struct { + uint8_t e_ident[16]; + uint16_t e_type; + uint16_t e_machine; + uint32_t e_version; + uint64_t e_entry; + uint64_t e_phoff; + uint64_t e_shoff; + uint32_t e_flags; + uint16_t e_ehsize; + uint16_t e_phentsize; + uint16_t e_phnum; + uint16_t e_shentsize; + uint16_t e_shnum; + uint16_t e_shstrndx; +} Elf64_Ehdr; + +typedef struct { + uint32_t sh_name; + uint32_t sh_type; + uint64_t sh_flags; + uint64_t sh_addr; + uint64_t sh_offset; + uint64_t sh_size; + uint32_t sh_link; + uint32_t sh_info; + uint64_t sh_addralign; + uint64_t sh_entsize; +} Elf64_Shdr; + +typedef struct { + uint32_t p_type; + uint32_t p_flags; + uint64_t p_offset; + uint64_t p_vaddr; + uint64_t p_paddr; + uint64_t p_filesz; + uint64_t p_memsz; + uint64_t p_align; +} Elf64_Phdr; + +typedef struct { + uint32_t st_name; + uint8_t st_info; + uint8_t st_other; + uint16_t st_shndx; + uint64_t st_value; + uint64_t st_size; +} Elf64_Sym; + +#endif diff --git a/vendor/riscv/riscv-isa-sim/fesvr/elf2hex.cc b/vendor/riscv/riscv-isa-sim/fesvr/elf2hex.cc new file mode 100644 index 0000000000..327cf2d933 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/fesvr/elf2hex.cc @@ -0,0 +1,47 @@ +// See LICENSE for license details. + +#include <iostream> +#include "htif_hexwriter.h" +#include "memif.h" +#include "elfloader.h" + +int main(int argc, char** argv) +{ + if(argc < 4 || argc > 5) + { + std::cerr << "Usage: " << argv[0] << " <width> <depth> <elf_file> [base]" << std::endl; + return 1; + } + + unsigned width = atoi(argv[1]); + if(width == 0 || (width & (width-1))) + { + std::cerr << "width must be a power of 2" << std::endl; + return 1; + } + + unsigned long long int base = 0; + if(argc==5) { + base = atoll(argv[4]); + if(base & (width-1)) + { + std::cerr << "base must be divisible by width" << std::endl; + return 1; + } + } + + unsigned depth = atoi(argv[2]); + if(depth == 0 || (depth & (depth-1))) + { + std::cerr << "depth must be a power of 2" << std::endl; + return 1; + } + + htif_hexwriter_t htif(base, width, depth); + memif_t memif(&htif); + reg_t entry; + load_elf(argv[3], &memif, &entry); + std::cout << htif; + + return 0; +} diff --git a/vendor/riscv/riscv-isa-sim/fesvr/elfloader.cc b/vendor/riscv/riscv-isa-sim/fesvr/elfloader.cc new file mode 100644 index 0000000000..c70de12dbb --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/fesvr/elfloader.cc @@ -0,0 +1,128 @@ +// See LICENSE for license details. + +#include "config.h" +#include "elf.h" +#include "memif.h" +#include "byteorder.h" +#include <cstring> +#include <string> +#include <sys/stat.h> +#include <fcntl.h> +#include <sys/mman.h> +#include <assert.h> +#include <unistd.h> +#include <stdexcept> +#include <stdlib.h> +#include <stdio.h> +#include <vector> +#include <map> + +std::map<std::string, uint64_t> load_elf(const char* fn, memif_t* memif, reg_t* entry, unsigned required_xlen = 0) +{ + int fd = open(fn, O_RDONLY); + struct stat s; + if (fd == -1) + throw std::invalid_argument(std::string("Specified ELF can't be opened: ") + strerror(errno)); + if (fstat(fd, &s) < 0) + abort(); + size_t size = s.st_size; + + char* buf = (char*)mmap(NULL, size, PROT_READ, MAP_PRIVATE, fd, 0); + if (buf == MAP_FAILED) + throw std::invalid_argument(std::string("Specified ELF can't be mapped: ") + strerror(errno)); + close(fd); + + assert(size >= sizeof(Elf64_Ehdr)); + const Elf64_Ehdr* eh64 = (const Elf64_Ehdr*)buf; + assert(IS_ELF32(*eh64) || IS_ELF64(*eh64)); + unsigned xlen = IS_ELF32(*eh64) ? 32 : 64; + if (required_xlen != 0 && required_xlen != xlen) { + throw incompat_xlen(required_xlen, xlen); + } + assert(IS_ELFLE(*eh64) || IS_ELFBE(*eh64)); + assert(IS_ELF_EXEC(*eh64)); + assert(IS_ELF_RISCV(*eh64) || IS_ELF_EM_NONE(*eh64)); + assert(IS_ELF_VCURRENT(*eh64)); + + std::vector<uint8_t> zeros; + std::map<std::string, uint64_t> symbols; + +#define LOAD_ELF(ehdr_t, phdr_t, shdr_t, sym_t, bswap) \ + do { \ + ehdr_t* eh = (ehdr_t*)buf; \ + phdr_t* ph = (phdr_t*)(buf + bswap(eh->e_phoff)); \ + *entry = bswap(eh->e_entry); \ + assert(size >= bswap(eh->e_phoff) + bswap(eh->e_phnum) * sizeof(*ph)); \ + for (unsigned i = 0; i < bswap(eh->e_phnum); i++) { \ + if (bswap(ph[i].p_type) == PT_LOAD && bswap(ph[i].p_memsz)) { \ + if (bswap(ph[i].p_filesz)) { \ + assert(size >= bswap(ph[i].p_offset) + bswap(ph[i].p_filesz)); \ + memif->write(bswap(ph[i].p_paddr), bswap(ph[i].p_filesz), \ + (uint8_t*)buf + bswap(ph[i].p_offset)); \ + } \ + if (size_t pad = bswap(ph[i].p_memsz) - bswap(ph[i].p_filesz)) { \ + zeros.resize(pad); \ + memif->write(bswap(ph[i].p_paddr) + bswap(ph[i].p_filesz), pad, \ + zeros.data()); \ + } \ + } \ + } \ + shdr_t* sh = (shdr_t*)(buf + bswap(eh->e_shoff)); \ + assert(size >= bswap(eh->e_shoff) + bswap(eh->e_shnum) * sizeof(*sh)); \ + assert(bswap(eh->e_shstrndx) < bswap(eh->e_shnum)); \ + assert(size >= bswap(sh[bswap(eh->e_shstrndx)].sh_offset) + \ + bswap(sh[bswap(eh->e_shstrndx)].sh_size)); \ + char* shstrtab = buf + bswap(sh[bswap(eh->e_shstrndx)].sh_offset); \ + unsigned strtabidx = 0, symtabidx = 0; \ + for (unsigned i = 0; i < bswap(eh->e_shnum); i++) { \ + unsigned max_len = \ + bswap(sh[bswap(eh->e_shstrndx)].sh_size) - bswap(sh[i].sh_name); \ + assert(bswap(sh[i].sh_name) < bswap(sh[bswap(eh->e_shstrndx)].sh_size)); \ + assert(strnlen(shstrtab + bswap(sh[i].sh_name), max_len) < max_len); \ + if (bswap(sh[i].sh_type) & SHT_NOBITS) continue; \ + assert(size >= bswap(sh[i].sh_offset) + bswap(sh[i].sh_size)); \ + if (strcmp(shstrtab + bswap(sh[i].sh_name), ".strtab") == 0) \ + strtabidx = i; \ + if (strcmp(shstrtab + bswap(sh[i].sh_name), ".symtab") == 0) \ + symtabidx = i; \ + } \ + if (strtabidx && symtabidx) { \ + char* strtab = buf + bswap(sh[strtabidx].sh_offset); \ + sym_t* sym = (sym_t*)(buf + bswap(sh[symtabidx].sh_offset)); \ + for (unsigned i = 0; i < bswap(sh[symtabidx].sh_size) / sizeof(sym_t); \ + i++) { \ + unsigned max_len = \ + bswap(sh[strtabidx].sh_size) - bswap(sym[i].st_name); \ + assert(bswap(sym[i].st_name) < bswap(sh[strtabidx].sh_size)); \ + assert(strnlen(strtab + bswap(sym[i].st_name), max_len) < max_len); \ + symbols[strtab + bswap(sym[i].st_name)] = bswap(sym[i].st_value); \ + } \ + } \ + } while (0) + + if (IS_ELFLE(*eh64)) { + if (memif->get_target_endianness() != endianness_little) { + throw std::invalid_argument("Specified ELF is little endian, but system uses a big-endian memory system. Rerun without --big-endian"); + } + if (IS_ELF32(*eh64)) + LOAD_ELF(Elf32_Ehdr, Elf32_Phdr, Elf32_Shdr, Elf32_Sym, from_le); + else + LOAD_ELF(Elf64_Ehdr, Elf64_Phdr, Elf64_Shdr, Elf64_Sym, from_le); + } else { +#ifndef RISCV_ENABLE_DUAL_ENDIAN + throw std::invalid_argument("Specified ELF is big endian. Configure with --enable-dual-endian to enable support"); +#else + if (memif->get_target_endianness() != endianness_big) { + throw std::invalid_argument("Specified ELF is big endian, but system uses a little-endian memory system. Rerun with --big-endian"); + } + if (IS_ELF32(*eh64)) + LOAD_ELF(Elf32_Ehdr, Elf32_Phdr, Elf32_Shdr, Elf32_Sym, from_be); + else + LOAD_ELF(Elf64_Ehdr, Elf64_Phdr, Elf64_Shdr, Elf64_Sym, from_be); +#endif + } + + munmap(buf, size); + + return symbols; +} diff --git a/vendor/riscv/riscv-isa-sim/fesvr/elfloader.h b/vendor/riscv/riscv-isa-sim/fesvr/elfloader.h new file mode 100644 index 0000000000..ae4ee78c2b --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/fesvr/elfloader.h @@ -0,0 +1,13 @@ +// See LICENSE for license details. + +#ifndef _ELFLOADER_H +#define _ELFLOADER_H + +#include "elf.h" +#include <map> +#include <string> + +class memif_t; +std::map<std::string, uint64_t> load_elf(const char* fn, memif_t* memif, reg_t* entry, unsigned required_xlen = 0); + +#endif diff --git a/vendor/riscv/riscv-isa-sim/fesvr/fesvr.ac b/vendor/riscv/riscv-isa-sim/fesvr/fesvr.ac new file mode 100644 index 0000000000..f741baea7f --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/fesvr/fesvr.ac @@ -0,0 +1,11 @@ +AC_CHECK_LIB(pthread, pthread_create, [], [AC_MSG_ERROR([libpthread is required])]) + +AC_CHECK_MEMBER(struct statx.stx_ino, + AC_DEFINE_UNQUOTED(HAVE_STATX, 1, [Define to 1 if struct statx exists.]), + , +) + +AC_CHECK_MEMBER(struct statx.stx_mnt_id, + AC_DEFINE_UNQUOTED(HAVE_STATX_MNT_ID, 1, [Define to 1 if struct statx has stx_mnt_id.]), + , +) diff --git a/vendor/riscv/riscv-isa-sim/fesvr/fesvr.mk.in b/vendor/riscv/riscv-isa-sim/fesvr/fesvr.mk.in new file mode 100644 index 0000000000..c854939917 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/fesvr/fesvr.mk.in @@ -0,0 +1,40 @@ +fesvr_install_hdrs = \ + byteorder.h \ + elf.h \ + elfloader.h \ + htif.h \ + dtm.h \ + memif.h \ + syscall.h \ + context.h \ + htif_pthread.h \ + htif_hexwriter.h \ + option_parser.h \ + term.h \ + device.h \ + rfb.h \ + tsi.h \ + +fesvr_install_config_hdr = yes + +fesvr_install_lib = yes +fesvr_install_shared_lib = yes + +fesvr_srcs = \ + elfloader.cc \ + htif.cc \ + memif.cc \ + dtm.cc \ + syscall.cc \ + device.cc \ + rfb.cc \ + context.cc \ + htif_pthread.cc \ + htif_hexwriter.cc \ + dummy.cc \ + option_parser.cc \ + term.cc \ + tsi.cc \ + +fesvr_install_prog_srcs = \ + elf2hex.cc \ diff --git a/vendor/riscv/riscv-isa-sim/fesvr/fesvr.pc.in b/vendor/riscv/riscv-isa-sim/fesvr/fesvr.pc.in new file mode 100644 index 0000000000..f2d12563b4 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/fesvr/fesvr.pc.in @@ -0,0 +1,26 @@ +#========================================================================= +# Modular C++ Build System Subproject Package Config +#========================================================================= +# Please read the documenation in 'mcppbs-uguide.txt' for more details +# on how the Modular C++ Build System works. + +#------------------------------------------------------------------------- +# Generic variables +#------------------------------------------------------------------------- + +prefix=@prefix@ +include_dir=${prefix}/include/fesvr +lib_dir=${prefix}/lib + +#------------------------------------------------------------------------- +# Keywords +#------------------------------------------------------------------------- + +Name : fesvr +Version : @PACKAGE_VERSION@ +Description : Frontend Server C/C++ API +Requires : @fesvr_pkcdeps@ +Cflags : -I${include_dir} @CPPFLAGS@ @fesvr_extra_cppflags@ +Libs : -L${lib_dir} @LDFLAGS@ @fesvr_extra_ldflags@ \ + -lfesvr @fesvr_extra_libs@ + diff --git a/vendor/riscv/riscv-isa-sim/fesvr/htif.cc b/vendor/riscv/riscv-isa-sim/fesvr/htif.cc new file mode 100644 index 0000000000..3f93f7b507 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/fesvr/htif.cc @@ -0,0 +1,455 @@ +// See LICENSE for license details. + +#include "config.h" +#include "htif.h" +#include "rfb.h" +#include "elfloader.h" +#include "platform.h" +#include "byteorder.h" +#include "trap.h" +#include "../riscv/common.h" +#include <algorithm> +#include <assert.h> +#include <vector> +#include <queue> +#include <iostream> +#include <fstream> +#include <sstream> +#include <iomanip> +#include <stdio.h> +#include <unistd.h> +#include <signal.h> +#include <getopt.h> + +/* Attempt to determine the execution prefix automatically. autoconf + * sets PREFIX, and pconfigure sets __PCONFIGURE__PREFIX. */ +#if !defined(PREFIX) && defined(__PCONFIGURE__PREFIX) +# define PREFIX __PCONFIGURE__PREFIX +#endif + +#ifndef TARGET_ARCH +# define TARGET_ARCH "riscv64-unknown-elf" +#endif + +#ifndef TARGET_DIR +# define TARGET_DIR "/" TARGET_ARCH "/bin/" +#endif + +static volatile bool signal_exit = false; +static void handle_signal(int sig) +{ + if (sig == SIGABRT || signal_exit) // someone set up us the bomb! + exit(-1); + signal_exit = true; + signal(sig, &handle_signal); +} + +htif_t::htif_t() + : mem(this), entry(DRAM_BASE), sig_addr(0), sig_len(0), + tohost_addr(0), fromhost_addr(0), exitcode(0), stopped(false), + syscall_proxy(this) +{ + signal(SIGINT, &handle_signal); + signal(SIGTERM, &handle_signal); + signal(SIGABRT, &handle_signal); // we still want to call static destructors +} + +htif_t::htif_t(int argc, char** argv) : htif_t() +{ + //Set line size as 16 by default. + line_size = 16; + parse_arguments(argc, argv); + register_devices(); +} + +htif_t::htif_t(const std::vector<std::string>& args) : htif_t() +{ + int argc = args.size() + 1; + char * argv[argc]; + argv[0] = (char *) "htif"; + for (unsigned int i = 0; i < args.size(); i++) { + argv[i+1] = (char *) args[i].c_str(); + } + //Set line size as 16 by default. + line_size = 16; + parse_arguments(argc, argv); + register_devices(); +} + +htif_t::~htif_t() +{ + for (auto d : dynamic_devices) + delete d; +} + +void htif_t::start() +{ + if (!targs.empty() && targs[0] != "none") { + try { + load_program(); + } catch (const incompat_xlen & err) { + fprintf(stderr, "Error: cannot execute %d-bit program on RV%d hart\n", err.actual_xlen, err.expected_xlen); + exit(1); + } + } + + reset(); +} + +static void bad_address(const std::string& situation, reg_t addr) +{ + std::cerr << "Access exception occurred while " << situation << ":\n"; + std::cerr << "Memory address 0x" << std::hex << addr << " is invalid\n"; + exit(-1); +} + +std::map<std::string, uint64_t> htif_t::load_payload(const std::string& payload, reg_t* entry) +{ + std::string path; + if (access(payload.c_str(), F_OK) == 0) + path = payload; + else if (payload.find('/') == std::string::npos) + { + std::string test_path = PREFIX TARGET_DIR + payload; + if (access(test_path.c_str(), F_OK) == 0) + path = test_path; + else + throw std::runtime_error( + "could not open " + payload + "; searched paths:\n" + + "\t. (current directory)\n" + + "\t" + PREFIX TARGET_DIR + " (based on configured --prefix and --with-target)" + ); + } + + if (path.empty()) + throw std::runtime_error( + "could not open " + payload + + " (did you misspell it? If VCS, did you forget +permissive/+permissive-off?)"); + + // temporarily construct a memory interface that skips writing bytes + // that have already been preloaded through a sideband + class preload_aware_memif_t : public memif_t { + public: + preload_aware_memif_t(htif_t* htif) : memif_t(htif), htif(htif) {} + + void write(addr_t taddr, size_t len, const void* src) override + { + if (!htif->is_address_preloaded(taddr, len)) + memif_t::write(taddr, len, src); + } + + private: + htif_t* htif; + } preload_aware_memif(this); + + try { + return load_elf(path.c_str(), &preload_aware_memif, entry, expected_xlen); + } catch (mem_trap_t& t) { + bad_address("loading payload " + payload, t.get_tval()); + abort(); + } +} + +void htif_t::load_program() +{ + std::map<std::string, uint64_t> symbols = load_payload(targs[0], &entry); + + if (symbols.count("tohost") && symbols.count("fromhost")) { + tohost_addr = symbols["tohost"]; + fromhost_addr = symbols["fromhost"]; + } else { + fprintf(stderr, "warning: tohost and fromhost symbols not in ELF; can't communicate with target\n"); + } + + // detect torture tests so we can print the memory signature at the end + if (symbols.count("begin_signature") && symbols.count("end_signature")) { + sig_addr = symbols["begin_signature"]; + sig_len = symbols["end_signature"] - sig_addr; + } + + for (auto payload : payloads) { + reg_t dummy_entry; + load_payload(payload, &dummy_entry); + } + + class nop_memif_t : public memif_t { + public: + nop_memif_t(htif_t* htif) : memif_t(htif), htif(htif) {} + void read(addr_t UNUSED addr, size_t UNUSED len, void UNUSED *bytes) override {} + void write(addr_t UNUSED taddr, size_t UNUSED len, const void UNUSED *src) override {} + private: + htif_t* htif; + } nop_memif(this); + + reg_t nop_entry; + for (auto &s : symbol_elfs) { + std::map<std::string, uint64_t> other_symbols = load_elf(s.c_str(), &nop_memif, &nop_entry, + expected_xlen); + symbols.merge(other_symbols); + } + + for (auto i : symbols) { + auto it = addr2symbol.find(i.second); + if ( it == addr2symbol.end()) + addr2symbol[i.second] = i.first; + } + + return; +} + +const char* htif_t::get_symbol(uint64_t addr) +{ + auto it = addr2symbol.find(addr); + + if(it == addr2symbol.end()) + return nullptr; + + return it->second.c_str(); +} + +void htif_t::stop() +{ + if (!sig_file.empty() && sig_len) // print final torture test signature + { + std::vector<uint8_t> buf(sig_len); + mem.read(sig_addr, sig_len, buf.data()); + + std::ofstream sigs(sig_file); + assert(sigs && "can't open signature file!"); + sigs << std::setfill('0') << std::hex; + + for (addr_t i = 0; i < sig_len; i += line_size) + { + for (addr_t j = line_size; j > 0; j--) + if (i+j <= sig_len) + sigs << std::setw(2) << (uint16_t)buf[i+j-1]; + else + sigs << std::setw(2) << (uint16_t)0; + sigs << '\n'; + } + + sigs.close(); + } + + stopped = true; +} + +void htif_t::clear_chunk(addr_t taddr, size_t len) +{ + char zeros[chunk_max_size()]; + memset(zeros, 0, chunk_max_size()); + + for (size_t pos = 0; pos < len; pos += chunk_max_size()) + write_chunk(taddr + pos, std::min(len - pos, chunk_max_size()), zeros); +} + +int htif_t::run() +{ + start(); + + auto enq_func = [](std::queue<reg_t>* q, uint64_t x) { q->push(x); }; + std::queue<reg_t> fromhost_queue; + std::function<void(reg_t)> fromhost_callback = + std::bind(enq_func, &fromhost_queue, std::placeholders::_1); + + if (tohost_addr == 0) { + while (true) + idle(); + } + + while (!signal_exit && exitcode == 0) + { + uint64_t tohost; + + try { + if ((tohost = from_target(mem.read_uint64(tohost_addr))) != 0) + mem.write_uint64(tohost_addr, target_endian<uint64_t>::zero); + } catch (mem_trap_t& t) { + bad_address("accessing tohost", t.get_tval()); + } + + try { + if (tohost != 0) { + command_t cmd(mem, tohost, fromhost_callback); + device_list.handle_command(cmd); + } else { + idle(); + } + + device_list.tick(); + } catch (mem_trap_t& t) { + std::stringstream tohost_hex; + tohost_hex << std::hex << tohost; + bad_address("host was accessing memory on behalf of target (tohost = 0x" + tohost_hex.str() + ")", t.get_tval()); + } + + try { + if (!fromhost_queue.empty() && !mem.read_uint64(fromhost_addr)) { + mem.write_uint64(fromhost_addr, to_target(fromhost_queue.front())); + fromhost_queue.pop(); + } + } catch (mem_trap_t& t) { + bad_address("accessing fromhost", t.get_tval()); + } + } + + stop(); + + return exit_code(); +} + +bool htif_t::done() +{ + return stopped; +} + +int htif_t::exit_code() +{ + return exitcode >> 1; +} + +void htif_t::parse_arguments(int argc, char ** argv) +{ + optind = 0; // reset optind as HTIF may run getopt _after_ others + while (1) { + static struct option long_options[] = { HTIF_LONG_OPTIONS }; + int option_index = 0; + int c = getopt_long(argc, argv, "-h", long_options, &option_index); + + if (c == -1) break; + retry: + switch (c) { + case 'h': usage(argv[0]); + throw std::invalid_argument("User queried htif_t help text"); + case HTIF_LONG_OPTIONS_OPTIND: + if (optarg) dynamic_devices.push_back(new rfb_t(atoi(optarg))); + else dynamic_devices.push_back(new rfb_t); + break; + case HTIF_LONG_OPTIONS_OPTIND + 1: + // [TODO] Remove once disks are supported again + throw std::invalid_argument("--disk/+disk unsupported (use a ramdisk)"); + dynamic_devices.push_back(new disk_t(optarg)); + break; + case HTIF_LONG_OPTIONS_OPTIND + 2: + sig_file = optarg; + break; + case HTIF_LONG_OPTIONS_OPTIND + 3: + syscall_proxy.set_chroot(optarg); + break; + case HTIF_LONG_OPTIONS_OPTIND + 4: + payloads.push_back(optarg); + break; + case HTIF_LONG_OPTIONS_OPTIND + 5: + line_size = atoi(optarg); + break; + case HTIF_LONG_OPTIONS_OPTIND + 6: + targs.push_back(optarg); + break; + case HTIF_LONG_OPTIONS_OPTIND + 7: + symbol_elfs.push_back(optarg); + break; + case '?': + if (!opterr) + break; + throw std::invalid_argument("Unknown argument (did you mean to enable +permissive parsing?)"); + case 1: { + std::string arg = optarg; + if (arg == "+h" || arg == "+help") { + c = 'h'; + optarg = nullptr; + } + else if (arg == "+rfb") { + c = HTIF_LONG_OPTIONS_OPTIND; + optarg = nullptr; + } + else if (arg.find("+rfb=") == 0) { + c = HTIF_LONG_OPTIONS_OPTIND; + optarg = optarg + 5; + } + else if (arg.find("+disk=") == 0) { + c = HTIF_LONG_OPTIONS_OPTIND + 1; + optarg = optarg + 6; + } + else if (arg.find("+signature=") == 0) { + c = HTIF_LONG_OPTIONS_OPTIND + 2; + optarg = optarg + 11; + } + else if (arg.find("+chroot=") == 0) { + c = HTIF_LONG_OPTIONS_OPTIND + 3; + optarg = optarg + 8; + } + else if (arg.find("+payload=") == 0) { + c = HTIF_LONG_OPTIONS_OPTIND + 4; + optarg = optarg + 9; + } + else if (arg.find("+signature-granularity=") == 0) { + c = HTIF_LONG_OPTIONS_OPTIND + 5; + optarg = optarg + 23; + } + else if (arg.find("+target-argument=") == 0) { + c = HTIF_LONG_OPTIONS_OPTIND + 6; + optarg = optarg + 17; + } + else if (arg.find("+symbol-elf=") == 0) { + c = HTIF_LONG_OPTIONS_OPTIND + 7; + optarg = optarg + 12; + } + else if (arg.find("+permissive-off") == 0) { + if (opterr) + throw std::invalid_argument("Found +permissive-off when not parsing permissively"); + opterr = 1; + break; + } + else if (arg.find("+permissive") == 0) { + if (!opterr) + throw std::invalid_argument("Found +permissive when already parsing permissively"); + opterr = 0; + break; + } + else { + if (!opterr) + break; + else { + optind--; + goto done_processing; + } + } + goto retry; + } + } + } + +done_processing: + while (optind < argc) + targs.push_back(argv[optind++]); + if (!targs.size()) { + usage(argv[0]); + throw std::invalid_argument("No binary specified (Did you forget it? Did you forget '+permissive-off' if running with +permissive?)"); + } +} + +void htif_t::register_devices() +{ + device_list.register_device(&syscall_proxy); + device_list.register_device(&bcd); + for (auto d : dynamic_devices) + device_list.register_device(d); +} + +void htif_t::usage(const char * program_name) +{ + printf("Usage: %s [EMULATOR OPTION]... [VERILOG PLUSARG]... [HOST OPTION]... BINARY [TARGET OPTION]...\n ", + program_name); + fputs("\ +Run a BINARY on the Rocket Chip emulator.\n\ +\n\ +Mandatory arguments to long options are mandatory for short options too.\n\ +\n\ +EMULATOR OPTIONS\n\ + Consult emulator.cc if using Verilator or VCS documentation if using VCS\n\ + for available options.\n\ +EMUALTOR VERILOG PLUSARGS\n\ + Consult generated-src*/*.plusArgs for available options\n\ +", stdout); + fputs("\n" HTIF_USAGE_OPTIONS, stdout); +} diff --git a/vendor/riscv/riscv-isa-sim/fesvr/htif.h b/vendor/riscv/riscv-isa-sim/fesvr/htif.h new file mode 100644 index 0000000000..dd7c060e41 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/fesvr/htif.h @@ -0,0 +1,155 @@ +// See LICENSE for license details. + +#ifndef __HTIF_H +#define __HTIF_H + +#include "memif.h" +#include "syscall.h" +#include "device.h" +#include "byteorder.h" +#include <string.h> +#include <map> +#include <vector> +#include <assert.h> + +class htif_t : public chunked_memif_t +{ + public: + htif_t(); + htif_t(int argc, char** argv); + htif_t(const std::vector<std::string>& args); + virtual ~htif_t(); + + virtual void start(); + virtual void stop(); + + int run(); + bool done(); + int exit_code(); + void set_expected_xlen(unsigned int m) { expected_xlen = m; } + virtual memif_t& memif() { return mem; } + + template<typename T> inline T from_target(target_endian<T> n) const + { + endianness_t endianness = get_target_endianness(); + assert(endianness == endianness_little || endianness == endianness_big); + + return endianness == endianness_big? n.from_be() : n.from_le(); + } + + template<typename T> inline target_endian<T> to_target(T n) const + { + endianness_t endianness = get_target_endianness(); + assert(endianness == endianness_little || endianness == endianness_big); + + return endianness == endianness_big? target_endian<T>::to_be(n) : target_endian<T>::to_le(n); + } + + addr_t get_tohost_addr() { return tohost_addr; } + addr_t get_fromhost_addr() { return fromhost_addr; } + + protected: + virtual void reset() = 0; + + virtual void read_chunk(addr_t taddr, size_t len, void* dst) = 0; + virtual void write_chunk(addr_t taddr, size_t len, const void* src) = 0; + virtual void clear_chunk(addr_t taddr, size_t len); + + virtual size_t chunk_align() = 0; + virtual size_t chunk_max_size() = 0; + + virtual std::map<std::string, uint64_t> load_payload(const std::string& payload, reg_t* entry); + virtual void load_program(); + virtual void idle() {} + + const std::vector<std::string>& host_args() { return hargs; } + const std::vector<std::string>& target_args() { return targs; } + + reg_t get_entry_point() { return entry; } + + // indicates that the initial program load can skip writing this address + // range to memory, because it has already been loaded through a sideband + virtual bool is_address_preloaded(addr_t, size_t) { return false; } + + // Given an address, return symbol from addr2symbol map + const char* get_symbol(uint64_t addr); + + private: + void parse_arguments(int argc, char ** argv); + void register_devices(); + void usage(const char * program_name); + unsigned int expected_xlen = 0; + memif_t mem; + reg_t entry; + bool writezeros; + std::vector<std::string> hargs; + std::vector<std::string> targs; + std::string sig_file; + unsigned int line_size; + addr_t sig_addr; // torture + addr_t sig_len; // torture + addr_t tohost_addr; + addr_t fromhost_addr; + int exitcode; + bool stopped; + + device_list_t device_list; + syscall_t syscall_proxy; + bcd_t bcd; + std::vector<device_t*> dynamic_devices; + std::vector<std::string> payloads; + + std::vector<std::string> symbol_elfs; + std::map<uint64_t, std::string> addr2symbol; + + friend class memif_t; + friend class syscall_t; +}; + +/* Alignment guide for emulator.cc options: + -x, --long-option Description with max 80 characters --------------->\n\ + +plus-arg-equivalent\n\ + */ +#define HTIF_USAGE_OPTIONS \ +"HOST OPTIONS\n\ + -h, --help Display this help and exit\n\ + +h, +help\n\ + +permissive The host will ignore any unparsed options up until\n\ + +permissive-off (Only needed for VCS)\n\ + +permissive-off Stop ignoring options. This is mandatory if using\n\ + +permissive (Only needed for VCS)\n\ + --rfb=DISPLAY Add new remote frame buffer on display DISPLAY\n\ + +rfb=DISPLAY to be accessible on 5900 + DISPLAY (default = 0)\n\ + --signature=FILE Write torture test signature to FILE\n\ + +signature=FILE\n\ + --signature-granularity=VAL Size of each line in signature.\n\ + +signature-granularity=VAL\n\ + --chroot=PATH Use PATH as location of syscall-servicing binaries\n\ + +chroot=PATH\n\ + --payload=PATH Load PATH memory as an additional ELF payload\n\ + +payload=PATH\n\ + --symbol-elf=PATH Populate the symbol table with the ELF file at PATH\n\ + +symbol-elf=PATH\n\ +\n\ +HOST OPTIONS (currently unsupported)\n\ + --disk=DISK Add DISK device. Use a ramdisk since this isn't\n\ + +disk=DISK supported\n\ +\n\ +TARGET (RISC-V BINARY) OPTIONS\n\ + These are the options passed to the program executing on the emulated RISC-V\n\ + microprocessor.\n" + +#define HTIF_LONG_OPTIONS_OPTIND 1024 +#define HTIF_LONG_OPTIONS \ +{"help", no_argument, 0, 'h' }, \ +{"rfb", optional_argument, 0, HTIF_LONG_OPTIONS_OPTIND }, \ +{"disk", required_argument, 0, HTIF_LONG_OPTIONS_OPTIND + 1 }, \ +{"signature", required_argument, 0, HTIF_LONG_OPTIONS_OPTIND + 2 }, \ +{"chroot", required_argument, 0, HTIF_LONG_OPTIONS_OPTIND + 3 }, \ +{"payload", required_argument, 0, HTIF_LONG_OPTIONS_OPTIND + 4 }, \ +{"signature-granularity", required_argument, 0, HTIF_LONG_OPTIONS_OPTIND + 5 }, \ +{"target-argument", required_argument, 0, HTIF_LONG_OPTIONS_OPTIND + 6 }, \ +{"symbol-elf", required_argument, 0, HTIF_LONG_OPTIONS_OPTIND + 7 }, \ +{0, 0, 0, 0} + +#endif // __HTIF_H diff --git a/vendor/riscv/riscv-isa-sim/fesvr/htif_hexwriter.cc b/vendor/riscv/riscv-isa-sim/fesvr/htif_hexwriter.cc new file mode 100644 index 0000000000..e4811b3bee --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/fesvr/htif_hexwriter.cc @@ -0,0 +1,76 @@ +// See LICENSE for license details. + +#include <iostream> +#include <assert.h> +#include "htif_hexwriter.h" + +htif_hexwriter_t::htif_hexwriter_t(size_t b, size_t w, size_t d) + : base(b), width(w), depth(d) +{ +} + +void htif_hexwriter_t::read_chunk(addr_t taddr, size_t len, void* vdst) +{ + taddr -= base; + + assert(len % chunk_align() == 0); + assert(taddr < width*depth); + assert(taddr+len <= width*depth); + + uint8_t* dst = (uint8_t*)vdst; + while(len) + { + if(mem[taddr/width].size() == 0) + mem[taddr/width].resize(width,0); + + for(size_t j = 0; j < width; j++) + dst[j] = mem[taddr/width][j]; + + len -= width; + taddr += width; + dst += width; + } +} + +void htif_hexwriter_t::write_chunk(addr_t taddr, size_t len, const void* vsrc) +{ + taddr -= base; + + assert(len % chunk_align() == 0); + assert(taddr < width*depth); + assert(taddr+len <= width*depth); + + const uint8_t* src = (const uint8_t*)vsrc; + while(len) + { + if(mem[taddr/width].size() == 0) + mem[taddr/width].resize(width,0); + + for(size_t j = 0; j < width; j++) + mem[taddr/width][j] = src[j]; + + len -= width; + taddr += width; + } +} + +std::ostream& operator<< (std::ostream& o, const htif_hexwriter_t& h) +{ + std::ios_base::fmtflags flags = o.setf(std::ios::hex,std::ios::basefield); + + for(size_t addr = 0; addr < h.depth; addr++) + { + std::map<addr_t,std::vector<char> >::const_iterator i = h.mem.find(addr); + if(i == h.mem.end()) + for(size_t j = 0; j < h.width; j++) + o << "00"; + else + for(size_t j = 0; j < h.width; j++) + o << ((i->second[h.width-j-1] >> 4) & 0xF) << (i->second[h.width-j-1] & 0xF); + o << std::endl; + } + + o.setf(flags); + + return o; +} diff --git a/vendor/riscv/riscv-isa-sim/fesvr/htif_hexwriter.h b/vendor/riscv/riscv-isa-sim/fesvr/htif_hexwriter.h new file mode 100644 index 0000000000..0cd859b1b1 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/fesvr/htif_hexwriter.h @@ -0,0 +1,32 @@ +// See LICENSE for license details. + +#ifndef __HTIF_HEXWRITER_H +#define __HTIF_HEXWRITER_H + +#include <map> +#include <vector> +#include <stdlib.h> +#include "memif.h" + +class htif_hexwriter_t : public chunked_memif_t +{ +public: + htif_hexwriter_t(size_t b, size_t w, size_t d); + +protected: + size_t base; + size_t width; + size_t depth; + std::map<addr_t,std::vector<char> > mem; + + void read_chunk(addr_t taddr, size_t len, void* dst); + void write_chunk(addr_t taddr, size_t len, const void* src); + void clear_chunk(addr_t, size_t) {} + + size_t chunk_max_size() { return width; } + size_t chunk_align() { return width; } + + friend std::ostream& operator<< (std::ostream&, const htif_hexwriter_t&); +}; + +#endif // __HTIF_HEXWRITER_H diff --git a/vendor/riscv/riscv-isa-sim/fesvr/htif_pthread.cc b/vendor/riscv/riscv-isa-sim/fesvr/htif_pthread.cc new file mode 100644 index 0000000000..b9e3832b94 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/fesvr/htif_pthread.cc @@ -0,0 +1,66 @@ +// See LICENSE for license details. + +#include "htif_pthread.h" +#include <algorithm> +#include <stdio.h> + +void htif_pthread_t::thread_main(void* arg) +{ + htif_pthread_t* htif = static_cast<htif_pthread_t*>(arg); + htif->run(); + while (true) + htif->target->switch_to(); +} + +htif_pthread_t::htif_pthread_t(int argc, char** argv) + : htif_t(argc, argv) +{ + target = context_t::current(); + host.init(thread_main, this); +} + +htif_pthread_t::~htif_pthread_t() +{ +} + +ssize_t htif_pthread_t::read(void* buf, size_t max_size) +{ + while (th_data.size() == 0) + target->switch_to(); + + size_t s = std::min(max_size, th_data.size()); + std::copy(th_data.begin(), th_data.begin() + s, (char*)buf); + th_data.erase(th_data.begin(), th_data.begin() + s); + + return s; +} + +ssize_t htif_pthread_t::write(const void* buf, size_t size) +{ + ht_data.insert(ht_data.end(), (const char*)buf, (const char*)buf + size); + return size; +} + +void htif_pthread_t::send(const void* buf, size_t size) +{ + th_data.insert(th_data.end(), (const char*)buf, (const char*)buf + size); +} + +void htif_pthread_t::recv(void* buf, size_t size) +{ + while (!this->recv_nonblocking(buf, size)) + ; +} + +bool htif_pthread_t::recv_nonblocking(void* buf, size_t size) +{ + if (ht_data.size() < size) + { + host.switch_to(); + return false; + } + + std::copy(ht_data.begin(), ht_data.begin() + size, (char*)buf); + ht_data.erase(ht_data.begin(), ht_data.begin() + size); + return true; +} diff --git a/vendor/riscv/riscv-isa-sim/fesvr/htif_pthread.h b/vendor/riscv/riscv-isa-sim/fesvr/htif_pthread.h new file mode 100644 index 0000000000..c00c38230c --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/fesvr/htif_pthread.h @@ -0,0 +1,38 @@ +// See LICENSE for license details. + +#ifndef _HTIF_PTHREAD_H +#define _HTIF_PTHREAD_H + +#include "htif.h" +#include "context.h" +#include <deque> + +class htif_pthread_t : public htif_t +{ + public: + htif_pthread_t(int argc, char** argv); + virtual ~htif_pthread_t(); + + // target inteface + void send(const void* buf, size_t size); + void recv(void* buf, size_t size); + bool recv_nonblocking(void* buf, size_t size); + + protected: + // host interface + virtual ssize_t read(void* buf, size_t max_size); + virtual ssize_t write(const void* buf, size_t size); + + virtual size_t chunk_align() { return 64; } + virtual size_t chunk_max_size() { return 1024; } + + private: + context_t host; + context_t* target; + std::deque<char> th_data; + std::deque<char> ht_data; + + static void thread_main(void* htif); +}; + +#endif diff --git a/vendor/riscv/riscv-isa-sim/fesvr/memif.cc b/vendor/riscv/riscv-isa-sim/fesvr/memif.cc new file mode 100644 index 0000000000..e56bd94326 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/fesvr/memif.cc @@ -0,0 +1,183 @@ +// See LICENSE for license details. + +#include <algorithm> +#include <stdlib.h> +#include <string.h> +#include <stdexcept> +#include "memif.h" + +void memif_t::read(addr_t addr, size_t len, void* bytes) +{ + size_t align = cmemif->chunk_align(); + if (len && (addr & (align-1))) + { + size_t this_len = std::min(len, align - size_t(addr & (align-1))); + uint8_t chunk[align]; + + cmemif->read_chunk(addr & ~(align-1), align, chunk); + memcpy(bytes, chunk + (addr & (align-1)), this_len); + + bytes = (char*)bytes + this_len; + addr += this_len; + len -= this_len; + } + + if (len & (align-1)) + { + size_t this_len = len & (align-1); + size_t start = len - this_len; + uint8_t chunk[align]; + + cmemif->read_chunk(addr + start, align, chunk); + memcpy((char*)bytes + start, chunk, this_len); + + len -= this_len; + } + + // now we're aligned + for (size_t pos = 0; pos < len; pos += cmemif->chunk_max_size()) + cmemif->read_chunk(addr + pos, std::min(cmemif->chunk_max_size(), len - pos), (char*)bytes + pos); +} + +void memif_t::write(addr_t addr, size_t len, const void* bytes) +{ + size_t align = cmemif->chunk_align(); + if (len && (addr & (align-1))) + { + size_t this_len = std::min(len, align - size_t(addr & (align-1))); + uint8_t chunk[align]; + + cmemif->read_chunk(addr & ~(align-1), align, chunk); + memcpy(chunk + (addr & (align-1)), bytes, this_len); + cmemif->write_chunk(addr & ~(align-1), align, chunk); + + bytes = (char*)bytes + this_len; + addr += this_len; + len -= this_len; + } + + if (len & (align-1)) + { + size_t this_len = len & (align-1); + size_t start = len - this_len; + uint8_t chunk[align]; + + cmemif->read_chunk(addr + start, align, chunk); + memcpy(chunk, (char*)bytes + start, this_len); + cmemif->write_chunk(addr + start, align, chunk); + + len -= this_len; + } + + // now we're aligned + bool all_zero = len != 0; + for (size_t i = 0; i < len; i++) + all_zero &= ((const char*)bytes)[i] == 0; + + if (all_zero) { + cmemif->clear_chunk(addr, len); + } else { + size_t max_chunk = cmemif->chunk_max_size(); + for (size_t pos = 0; pos < len; pos += max_chunk) + cmemif->write_chunk(addr + pos, std::min(max_chunk, len - pos), (char*)bytes + pos); + } +} + +#define MEMIF_READ_FUNC \ + if(addr & (sizeof(val)-1)) \ + throw std::runtime_error("misaligned address"); \ + this->read(addr, sizeof(val), &val); \ + return val + +#define MEMIF_WRITE_FUNC \ + if(addr & (sizeof(val)-1)) \ + throw std::runtime_error("misaligned address"); \ + this->write(addr, sizeof(val), &val) + +target_endian<uint8_t> memif_t::read_uint8(addr_t addr) +{ + target_endian<uint8_t> val; + MEMIF_READ_FUNC; +} + +target_endian<int8_t> memif_t::read_int8(addr_t addr) +{ + target_endian<int8_t> val; + MEMIF_READ_FUNC; +} + +void memif_t::write_uint8(addr_t addr, target_endian<uint8_t> val) +{ + MEMIF_WRITE_FUNC; +} + +void memif_t::write_int8(addr_t addr, target_endian<int8_t> val) +{ + MEMIF_WRITE_FUNC; +} + +target_endian<uint16_t> memif_t::read_uint16(addr_t addr) +{ + target_endian<uint16_t> val; + MEMIF_READ_FUNC; +} + +target_endian<int16_t> memif_t::read_int16(addr_t addr) +{ + target_endian<int16_t> val; + MEMIF_READ_FUNC; +} + +void memif_t::write_uint16(addr_t addr, target_endian<uint16_t> val) +{ + MEMIF_WRITE_FUNC; +} + +void memif_t::write_int16(addr_t addr, target_endian<int16_t> val) +{ + MEMIF_WRITE_FUNC; +} + +target_endian<uint32_t> memif_t::read_uint32(addr_t addr) +{ + target_endian<uint32_t> val; + MEMIF_READ_FUNC; +} + +target_endian<int32_t> memif_t::read_int32(addr_t addr) +{ + target_endian<int32_t> val; + MEMIF_READ_FUNC; +} + +void memif_t::write_uint32(addr_t addr, target_endian<uint32_t> val) +{ + MEMIF_WRITE_FUNC; +} + +void memif_t::write_int32(addr_t addr, target_endian<int32_t> val) +{ + MEMIF_WRITE_FUNC; +} + +target_endian<uint64_t> memif_t::read_uint64(addr_t addr) +{ + target_endian<uint64_t> val; + MEMIF_READ_FUNC; +} + +target_endian<int64_t> memif_t::read_int64(addr_t addr) +{ + target_endian<int64_t> val; + MEMIF_READ_FUNC; +} + +void memif_t::write_uint64(addr_t addr, target_endian<uint64_t> val) +{ + MEMIF_WRITE_FUNC; +} + +void memif_t::write_int64(addr_t addr, target_endian<int64_t> val) +{ + MEMIF_WRITE_FUNC; +} diff --git a/vendor/riscv/riscv-isa-sim/fesvr/memif.h b/vendor/riscv/riscv-isa-sim/fesvr/memif.h new file mode 100644 index 0000000000..ebed3d7289 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/fesvr/memif.h @@ -0,0 +1,83 @@ +// See LICENSE for license details. + +#ifndef __MEMIF_H +#define __MEMIF_H + +#include <stdint.h> +#include <stddef.h> +#include <stdexcept> +#include "byteorder.h" +#include "../riscv/cfg.h" + +typedef uint64_t reg_t; +typedef int64_t sreg_t; +typedef reg_t addr_t; + +class chunked_memif_t +{ +public: + virtual void read_chunk(addr_t taddr, size_t len, void* dst) = 0; + virtual void write_chunk(addr_t taddr, size_t len, const void* src) = 0; + virtual void clear_chunk(addr_t taddr, size_t len) = 0; + + virtual size_t chunk_align() = 0; + virtual size_t chunk_max_size() = 0; + + virtual endianness_t get_target_endianness() const { + return endianness_little; + } + + virtual ~chunked_memif_t() = default; +}; + +class memif_t +{ +public: + memif_t(chunked_memif_t* _cmemif) : cmemif(_cmemif) {} + virtual ~memif_t(){} + + // read and write byte arrays + virtual void read(addr_t addr, size_t len, void* bytes); + virtual void write(addr_t addr, size_t len, const void* bytes); + + // read and write 8-bit words + virtual target_endian<uint8_t> read_uint8(addr_t addr); + virtual target_endian<int8_t> read_int8(addr_t addr); + virtual void write_uint8(addr_t addr, target_endian<uint8_t> val); + virtual void write_int8(addr_t addr, target_endian<int8_t> val); + + // read and write 16-bit words + virtual target_endian<uint16_t> read_uint16(addr_t addr); + virtual target_endian<int16_t> read_int16(addr_t addr); + virtual void write_uint16(addr_t addr, target_endian<uint16_t> val); + virtual void write_int16(addr_t addr, target_endian<int16_t> val); + + // read and write 32-bit words + virtual target_endian<uint32_t> read_uint32(addr_t addr); + virtual target_endian<int32_t> read_int32(addr_t addr); + virtual void write_uint32(addr_t addr, target_endian<uint32_t> val); + virtual void write_int32(addr_t addr, target_endian<int32_t> val); + + // read and write 64-bit words + virtual target_endian<uint64_t> read_uint64(addr_t addr); + virtual target_endian<int64_t> read_int64(addr_t addr); + virtual void write_uint64(addr_t addr, target_endian<uint64_t> val); + virtual void write_int64(addr_t addr, target_endian<int64_t> val); + + // endianness + virtual endianness_t get_target_endianness() const { + return cmemif->get_target_endianness(); + } + +protected: + chunked_memif_t* cmemif; +}; + +class incompat_xlen : public std::exception { +public: + const unsigned expected_xlen; + const unsigned actual_xlen; + incompat_xlen(unsigned _expected_xlen, unsigned _actual_xlen) : expected_xlen(_expected_xlen), actual_xlen(_actual_xlen) {} +}; + +#endif // __MEMIF_H diff --git a/vendor/riscv/riscv-isa-sim/fesvr/option_parser.cc b/vendor/riscv/riscv-isa-sim/fesvr/option_parser.cc new file mode 100644 index 0000000000..72daec40ef --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/fesvr/option_parser.cc @@ -0,0 +1,51 @@ +// See LICENSE for license details. + +#include "option_parser.h" +#include <cstdio> +#include <cstdlib> +#include <cstring> +#include <cassert> + +void option_parser_t::option(char c, const char* s, int arg, std::function<void(const char*)> action) +{ + opts.push_back(option_t(c, s, arg, action)); +} + +const char* const* option_parser_t::parse(const char* const* argv0) +{ + assert(argv0); + const char* const* argv = argv0 + 1; + for (const char* opt; (opt = *argv) != NULL && opt[0] == '-'; argv++) + { + bool found = false; + for (auto it = opts.begin(); !found && it != opts.end(); it++) + { + size_t slen = it->str ? strlen(it->str) : 0; + bool chr_match = opt[1] != '-' && it->chr && opt[1] == it->chr; + bool str_match = opt[1] == '-' && slen && strncmp(opt+2, it->str, slen) == 0; + if (chr_match || (str_match && (opt[2+slen] == '=' || opt[2+slen] == '\0'))) + { + const char* optarg = + chr_match ? (opt[2] ? &opt[2] : NULL) : + opt[2+slen] ? &opt[3+slen] : + it->arg ? *(++argv) : NULL; + if (optarg && !it->arg) + error("no argument allowed for option", *argv0, opt); + if (!optarg && it->arg) + error("argument required for option", *argv0, opt); + it->func(optarg); + found = true; + } + } + if (!found) + error("unrecognized option", *argv0, opt); + } + return argv; +} + +void option_parser_t::error(const char* msg, const char* argv0, const char* arg) +{ + fprintf(stderr, "%s: %s %s\n", argv0, msg, arg ? arg : ""); + if (helpmsg) helpmsg(); + exit(1); +} diff --git a/vendor/riscv/riscv-isa-sim/fesvr/option_parser.h b/vendor/riscv/riscv-isa-sim/fesvr/option_parser.h new file mode 100644 index 0000000000..b2cb8edf9d --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/fesvr/option_parser.h @@ -0,0 +1,31 @@ +// See LICENSE for license details. + +#ifndef _OPTION_PARSER_H +#define _OPTION_PARSER_H + +#include <vector> +#include <functional> + +class option_parser_t +{ + public: + option_parser_t() : helpmsg(0) {} + void help(void (*helpm)(void)) { helpmsg = helpm; } + void option(char c, const char* s, int arg, std::function<void(const char*)> action); + const char* const* parse(const char* const* argv0); + private: + struct option_t + { + char chr; + const char* str; + int arg; + std::function<void(const char*)> func; + option_t(char chr, const char* str, int arg, std::function<void(const char*)> func) + : chr(chr), str(str), arg(arg), func(func) {} + }; + std::vector<option_t> opts; + void (*helpmsg)(void); + void error(const char* msg, const char* argv0, const char* arg); +}; + +#endif diff --git a/vendor/riscv/riscv-isa-sim/fesvr/rfb.cc b/vendor/riscv/riscv-isa-sim/fesvr/rfb.cc new file mode 100644 index 0000000000..bd72fda7b2 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/fesvr/rfb.cc @@ -0,0 +1,230 @@ +#include "rfb.h" +#include "memif.h" +#include <sys/types.h> +#include <sys/socket.h> +#include <sched.h> +#include <netinet/in.h> +#include <unistd.h> +#include <cstdlib> +#include <stdexcept> +#include <string> +#include <cstring> +#include <cinttypes> +using namespace std::placeholders; + +rfb_t::rfb_t(int display) + : sockfd(-1), afd(-1), + memif(0), addr(0), width(0), height(0), bpp(0), display(display), + thread(pthread_self()), fb1(0), fb2(0), read_pos(0), + lock(PTHREAD_MUTEX_INITIALIZER) +{ + register_command(0, std::bind(&rfb_t::handle_configure, this, _1), "configure"); + register_command(1, std::bind(&rfb_t::handle_set_address, this, _1), "set_address"); +} + +void* rfb_thread_main(void* arg) +{ + ((rfb_t*)arg)->thread_main(); + return 0; +} + +void rfb_t::thread_main() +{ + pthread_mutex_lock(&lock); + + int port = 5900 + display; + sockfd = socket(PF_INET, SOCK_STREAM, 0); + if (sockfd < 0) + throw std::runtime_error("could not acquire tcp socket"); + + struct sockaddr_in saddr, caddr; + saddr.sin_family = AF_INET; + saddr.sin_addr.s_addr = INADDR_ANY; + saddr.sin_port = htons(port); + if (bind(sockfd, (struct sockaddr*)&saddr, sizeof(saddr)) < 0) + throw std::runtime_error("could not bind to port " + std::to_string(port)); + if (listen(sockfd, 0) < 0) + throw std::runtime_error("could not listen on port " + std::to_string(port)); + + socklen_t clen = sizeof(caddr); + afd = accept(sockfd, (struct sockaddr*)&caddr, &clen); + if (afd < 0) + throw std::runtime_error("could not accept connection"); + + std::string version = "RFB 003.003\n"; + write(version); + if (read() != version) + throw std::runtime_error("bad client version"); + + write(str(uint32_t(htonl(1)))); + + read(); // clientinit + + std::string serverinit; + serverinit += str(uint16_t(htons(width))); + serverinit += str(uint16_t(htons(height))); + serverinit += pixel_format(); + std::string name = "RISC-V"; + serverinit += str(uint32_t(htonl(name.length()))); + serverinit += name; + write(serverinit); + + pthread_mutex_unlock(&lock); + + while (memif == NULL) + sched_yield(); + + while (memif != NULL) + { + std::string s = read(); + if (s.length() < 4) + break; //throw std::runtime_error("bad command"); + + switch (s[0]) + { + case 0: set_pixel_format(s); break; + case 2: set_encodings(s); break; + case 3: break; + } + } + + pthread_mutex_lock(&lock); + close(afd); + close(sockfd); + afd = -1; + sockfd = -1; + pthread_mutex_unlock(&lock); + + thread_main(); +} + +rfb_t::~rfb_t() +{ + memif = 0; + if (!pthread_equal(pthread_self(), thread)) + pthread_join(thread, 0); + delete [] fb1; + delete [] fb2; +} + +void rfb_t::set_encodings(const std::string& s) +{ + uint16_t n = htons(*(uint16_t*)&s[2]); + for (size_t b = s.length(); b < 4U+4U*n; b += read().length()); +} + +void rfb_t::set_pixel_format(const std::string& s) +{ + if (s.length() != 20 || s.substr(4, 16) != pixel_format()) + throw std::runtime_error("bad pixel format"); +} + +void rfb_t::fb_update() +{ + std::string u; + u += str(uint8_t(0)); + u += str(uint8_t(0)); + u += str(uint16_t(htons(1))); + u += str(uint16_t(htons(0))); + u += str(uint16_t(htons(0))); + u += str(uint16_t(htons(width))); + u += str(uint16_t(htons(height))); + u += str(uint32_t(htonl(0))); + u += std::string((char*)fb1, fb_bytes()); + + try + { + write(u); + } + catch (std::runtime_error& e) + { + } +} + +void rfb_t::tick() +{ + if (fb_bytes() == 0 || memif == NULL) + return; + + memif->read(addr + read_pos, FB_ALIGN, const_cast<char*>(fb2 + read_pos)); + read_pos = (read_pos + FB_ALIGN) % fb_bytes(); + if (read_pos == 0) + { + std::swap(fb1, fb2); + if (pthread_mutex_trylock(&lock) == 0) + { + fb_update(); + pthread_mutex_unlock(&lock); + } + } +} + +std::string rfb_t::pixel_format() +{ + int red_bits = 8, green_bits = 8, blue_bits = 8; + int bpp = red_bits + green_bits + blue_bits; + while (bpp & (bpp-1)) bpp++; + + std::string fmt; + fmt += str(uint8_t(bpp)); + fmt += str(uint8_t(red_bits + green_bits + blue_bits)); + fmt += str(uint8_t(0)); // little-endian + fmt += str(uint8_t(1)); // true color + fmt += str(uint16_t(htons((1<<red_bits)-1))); + fmt += str(uint16_t(htons((1<<green_bits)-1))); + fmt += str(uint16_t(htons((1<<blue_bits)-1))); + fmt += str(uint8_t(blue_bits+green_bits)); + fmt += str(uint8_t(blue_bits)); + fmt += str(uint8_t(0)); + fmt += str(uint16_t(0)); // pad + fmt += str(uint8_t(0)); // pad + return fmt; +} + +void rfb_t::write(const std::string& s) +{ + if ((size_t)::write(afd, s.c_str(), s.length()) != s.length()) + throw std::runtime_error("could not write"); +} + +std::string rfb_t::read() +{ + char buf[2048]; + ssize_t len = ::read(afd, buf, sizeof(buf)); + if (len < 0) + throw std::runtime_error("could not read"); + if (len == sizeof(buf)) + throw std::runtime_error("received oversized packet"); + return std::string(buf, len); +} + +void rfb_t::handle_configure(command_t cmd) +{ + if (fb1) + throw std::runtime_error("you must only set the rfb configuration once"); + + width = cmd.payload(); + height = cmd.payload() >> 16; + + bpp = cmd.payload() >> 32; + if (bpp != 32) + throw std::runtime_error("rfb requires 32 bpp true color"); + + if (fb_bytes() % FB_ALIGN != 0) + throw std::runtime_error("rfb size must be a multiple of " + std::to_string(FB_ALIGN)); + + fb1 = new char[fb_bytes()]; + fb2 = new char[fb_bytes()]; + if (pthread_create(&thread, 0, rfb_thread_main, this)) + throw std::runtime_error("could not create thread"); + cmd.respond(1); +} + +void rfb_t::handle_set_address(command_t cmd) +{ + addr = cmd.payload(); + if (addr % FB_ALIGN != 0) + throw std::runtime_error("rfb address must be " + std::to_string(FB_ALIGN) + "-byte aligned"); + memif = &cmd.memif(); + cmd.respond(1); +} diff --git a/vendor/riscv/riscv-isa-sim/fesvr/rfb.h b/vendor/riscv/riscv-isa-sim/fesvr/rfb.h new file mode 100644 index 0000000000..e153bc80a1 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/fesvr/rfb.h @@ -0,0 +1,53 @@ +#ifndef _RFB_H +#define _RFB_H + +#include "device.h" +#include "memif.h" +#include <pthread.h> + +// remote frame buffer +class rfb_t : public device_t +{ + public: + rfb_t(int display = 0); + ~rfb_t(); + void tick(); + std::string name() { return "RISC-V"; } + const char* identity() { return "rfb"; } + + private: + template <typename T> + std::string str(T x) + { + return std::string((char*)&x, sizeof(x)); + } + size_t fb_bytes() { return size_t(width) * height * bpp/8; } + void thread_main(); + friend void* rfb_thread_main(void*); + std::string pixel_format(); + void fb_update(); + void set_encodings(const std::string& s); + void set_pixel_format(const std::string& s); + void write(const std::string& s); + std::string read(); + void handle_configure(command_t cmd); + void handle_set_address(command_t cmd); + + int sockfd; + int afd; + memif_t* memif; + reg_t addr; + uint16_t width; + uint16_t height; + uint16_t bpp; + int display; + pthread_t thread; + volatile char* volatile fb1; + volatile char* volatile fb2; + size_t read_pos; + pthread_mutex_t lock; + + static const int FB_ALIGN = 256; +}; + +#endif diff --git a/vendor/riscv/riscv-isa-sim/fesvr/syscall.cc b/vendor/riscv/riscv-isa-sim/fesvr/syscall.cc new file mode 100644 index 0000000000..e277be19bf --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/fesvr/syscall.cc @@ -0,0 +1,514 @@ +// See LICENSE for license details. + +#include "config.h" +#include "syscall.h" +#include "htif.h" +#include "byteorder.h" +#include <unistd.h> +#include <fcntl.h> +#include <sys/stat.h> +#include <limits.h> +#include <errno.h> +#include <stdlib.h> +#include <assert.h> +#include <termios.h> +#include <sstream> +#include <iostream> +using namespace std::placeholders; + +#define RISCV_AT_FDCWD -100 + +#ifdef __GNUC__ +# pragma GCC diagnostic ignored "-Wunused-parameter" +#endif + +struct riscv_stat +{ + target_endian<uint64_t> dev; + target_endian<uint64_t> ino; + target_endian<uint32_t> mode; + target_endian<uint32_t> nlink; + target_endian<uint32_t> uid; + target_endian<uint32_t> gid; + target_endian<uint64_t> rdev; + target_endian<uint64_t> __pad1; + target_endian<uint64_t> size; + target_endian<uint32_t> blksize; + target_endian<uint32_t> __pad2; + target_endian<uint64_t> blocks; + target_endian<uint64_t> atime; + target_endian<uint64_t> __pad3; + target_endian<uint64_t> mtime; + target_endian<uint64_t> __pad4; + target_endian<uint64_t> ctime; + target_endian<uint64_t> __pad5; + target_endian<uint32_t> __unused4; + target_endian<uint32_t> __unused5; + + riscv_stat(const struct stat& s, htif_t* htif) + : dev(htif->to_target<uint64_t>(s.st_dev)), + ino(htif->to_target<uint64_t>(s.st_ino)), + mode(htif->to_target<uint32_t>(s.st_mode)), + nlink(htif->to_target<uint32_t>(s.st_nlink)), + uid(htif->to_target<uint32_t>(s.st_uid)), + gid(htif->to_target<uint32_t>(s.st_gid)), + rdev(htif->to_target<uint64_t>(s.st_rdev)), __pad1(), + size(htif->to_target<uint64_t>(s.st_size)), + blksize(htif->to_target<uint32_t>(s.st_blksize)), __pad2(), + blocks(htif->to_target<uint64_t>(s.st_blocks)), + atime(htif->to_target<uint64_t>(s.st_atime)), __pad3(), + mtime(htif->to_target<uint64_t>(s.st_mtime)), __pad4(), + ctime(htif->to_target<uint64_t>(s.st_ctime)), __pad5(), + __unused4(), __unused5() {} +}; + + +struct riscv_statx_timestamp { + target_endian<int64_t> tv_sec; + target_endian<uint32_t> tv_nsec; + target_endian<int32_t> __reserved; +}; + +#ifdef HAVE_STATX +struct riscv_statx +{ + target_endian<uint32_t> mask; + target_endian<uint32_t> blksize; + target_endian<uint64_t> attributes; + target_endian<uint32_t> nlink; + target_endian<uint32_t> uid; + target_endian<uint32_t> gid; + target_endian<uint16_t> mode; + target_endian<uint16_t> __spare0[1]; + target_endian<uint64_t> ino; + target_endian<uint64_t> size; + target_endian<uint64_t> blocks; + target_endian<uint64_t> attributes_mask; + struct riscv_statx_timestamp atime; + struct riscv_statx_timestamp btime; + struct riscv_statx_timestamp ctime; + struct riscv_statx_timestamp mtime; + target_endian<uint32_t> rdev_major; + target_endian<uint32_t> rdev_minor; + target_endian<uint32_t> dev_major; + target_endian<uint32_t> dev_minor; +#ifdef HAVE_STATX_MNT_ID + target_endian<uint64_t> mnt_id; + target_endian<uint64_t> __spare2; + target_endian<uint64_t> __spare3[12]; +#else + target_endian<uint64_t> __spare2[14]; +#endif + + riscv_statx(const struct statx& s, htif_t* htif) + : mask(htif->to_target<uint32_t>(s.stx_mask)), + blksize(htif->to_target<uint32_t>(s.stx_blksize)), + attributes(htif->to_target<uint64_t>(s.stx_attributes)), + nlink(htif->to_target<uint32_t>(s.stx_nlink)), + uid(htif->to_target<uint32_t>(s.stx_uid)), + gid(htif->to_target<uint32_t>(s.stx_gid)), + mode(htif->to_target<uint16_t>(s.stx_mode)), __spare0(), + ino(htif->to_target<uint64_t>(s.stx_ino)), + size(htif->to_target<uint64_t>(s.stx_size)), + blocks(htif->to_target<uint64_t>(s.stx_blocks)), + attributes_mask(htif->to_target<uint64_t>(s.stx_attributes_mask)), + atime { + htif->to_target<int64_t>(s.stx_atime.tv_sec), + htif->to_target<uint32_t>(s.stx_atime.tv_nsec) + }, + btime { + htif->to_target<int64_t>(s.stx_btime.tv_sec), + htif->to_target<uint32_t>(s.stx_btime.tv_nsec) + }, + ctime { + htif->to_target<int64_t>(s.stx_ctime.tv_sec), + htif->to_target<uint32_t>(s.stx_ctime.tv_nsec) + }, + mtime { + htif->to_target<int64_t>(s.stx_mtime.tv_sec), + htif->to_target<uint32_t>(s.stx_mtime.tv_nsec) + }, + rdev_major(htif->to_target<uint32_t>(s.stx_rdev_major)), + rdev_minor(htif->to_target<uint32_t>(s.stx_rdev_minor)), + dev_major(htif->to_target<uint32_t>(s.stx_dev_major)), + dev_minor(htif->to_target<uint32_t>(s.stx_dev_minor)), +#ifdef HAVE_STATX_MNT_ID + mnt_id(htif->to_target<uint64_t>(s.stx_mnt_id)), + __spare2(), __spare3() +#else + __spare2() +#endif + {} +}; +#endif + +syscall_t::syscall_t(htif_t* htif) + : htif(htif), memif(&htif->memif()), table(2048) +{ + table[17] = &syscall_t::sys_getcwd; + table[25] = &syscall_t::sys_fcntl; + table[34] = &syscall_t::sys_mkdirat; + table[35] = &syscall_t::sys_unlinkat; + table[37] = &syscall_t::sys_linkat; + table[38] = &syscall_t::sys_renameat; + table[46] = &syscall_t::sys_ftruncate; + table[48] = &syscall_t::sys_faccessat; + table[49] = &syscall_t::sys_chdir; + table[56] = &syscall_t::sys_openat; + table[57] = &syscall_t::sys_close; + table[62] = &syscall_t::sys_lseek; + table[63] = &syscall_t::sys_read; + table[64] = &syscall_t::sys_write; + table[67] = &syscall_t::sys_pread; + table[68] = &syscall_t::sys_pwrite; + table[79] = &syscall_t::sys_fstatat; + table[80] = &syscall_t::sys_fstat; + table[93] = &syscall_t::sys_exit; + table[291] = &syscall_t::sys_statx; + table[1039] = &syscall_t::sys_lstat; + table[2011] = &syscall_t::sys_getmainvars; + + register_command(0, std::bind(&syscall_t::handle_syscall, this, _1), "syscall"); + + int stdin_fd = dup(0), stdout_fd0 = dup(1), stdout_fd1 = dup(1); + if (stdin_fd < 0 || stdout_fd0 < 0 || stdout_fd1 < 0) + throw std::runtime_error("could not dup stdin/stdout"); + + fds_index.push_back(fds.alloc(stdin_fd)); // stdin -> stdin + fds_index.push_back(fds.alloc(stdout_fd0)); // stdout -> stdout + fds_index.push_back(fds.alloc(stdout_fd1)); // stderr -> stdout +} + +syscall_t::~syscall_t() { + for (auto i: fds_index) { + close(fds.lookup(i)); + fds.dealloc(i); + } +} + +std::string syscall_t::do_chroot(const char* fn) +{ + if (!chroot.empty() && *fn == '/') + return chroot + fn; + return fn; +} + +std::string syscall_t::undo_chroot(const char* fn) +{ + if (chroot.empty()) + return fn; + if (strncmp(fn, chroot.c_str(), chroot.size()) == 0 + && (chroot.back() == '/' || fn[chroot.size()] == '/')) + return fn + chroot.size() - (chroot.back() == '/'); + return "/"; +} + +void syscall_t::handle_syscall(command_t cmd) +{ + if (cmd.payload() & 1) // test pass/fail + { + htif->exitcode = cmd.payload(); + if (htif->exit_code()) + std::cerr << "*** FAILED *** (tohost = " << htif->exit_code() << ")" << std::endl; + return; + } + else // proxied system call + dispatch(cmd.payload()); + + cmd.respond(1); +} + +reg_t syscall_t::sys_exit(reg_t code, reg_t a1, reg_t a2, reg_t a3, reg_t a4, reg_t a5, reg_t a6) +{ + htif->exitcode = code << 1 | 1; + return 0; +} + +static reg_t sysret_errno(sreg_t ret) +{ + return ret == -1 ? -errno : ret; +} + +reg_t syscall_t::sys_read(reg_t fd, reg_t pbuf, reg_t len, reg_t a3, reg_t a4, reg_t a5, reg_t a6) +{ + std::vector<char> buf(len); + ssize_t ret = read(fds.lookup(fd), buf.data(), len); + reg_t ret_errno = sysret_errno(ret); + if (ret > 0) + memif->write(pbuf, ret, buf.data()); + return ret_errno; +} + +reg_t syscall_t::sys_pread(reg_t fd, reg_t pbuf, reg_t len, reg_t off, reg_t a4, reg_t a5, reg_t a6) +{ + std::vector<char> buf(len); + ssize_t ret = pread(fds.lookup(fd), buf.data(), len, off); + reg_t ret_errno = sysret_errno(ret); + if (ret > 0) + memif->write(pbuf, ret, buf.data()); + return ret_errno; +} + +reg_t syscall_t::sys_write(reg_t fd, reg_t pbuf, reg_t len, reg_t a3, reg_t a4, reg_t a5, reg_t a6) +{ + std::vector<char> buf(len); + memif->read(pbuf, len, buf.data()); + reg_t ret = sysret_errno(write(fds.lookup(fd), buf.data(), len)); + return ret; +} + +reg_t syscall_t::sys_pwrite(reg_t fd, reg_t pbuf, reg_t len, reg_t off, reg_t a4, reg_t a5, reg_t a6) +{ + std::vector<char> buf(len); + memif->read(pbuf, len, buf.data()); + reg_t ret = sysret_errno(pwrite(fds.lookup(fd), buf.data(), len, off)); + return ret; +} + +reg_t syscall_t::sys_close(reg_t fd, reg_t a1, reg_t a2, reg_t a3, reg_t a4, reg_t a5, reg_t a6) +{ + if (close(fds.lookup(fd)) < 0) + return sysret_errno(-1); + fds.dealloc(fd); + return 0; +} + +reg_t syscall_t::sys_lseek(reg_t fd, reg_t ptr, reg_t dir, reg_t a3, reg_t a4, reg_t a5, reg_t a6) +{ + return sysret_errno(lseek(fds.lookup(fd), ptr, dir)); +} + +reg_t syscall_t::sys_fstat(reg_t fd, reg_t pbuf, reg_t a2, reg_t a3, reg_t a4, reg_t a5, reg_t a6) +{ + struct stat buf; + reg_t ret = sysret_errno(fstat(fds.lookup(fd), &buf)); + if (ret != (reg_t)-1) + { + riscv_stat rbuf(buf, htif); + memif->write(pbuf, sizeof(rbuf), &rbuf); + } + return ret; +} + +reg_t syscall_t::sys_fcntl(reg_t fd, reg_t cmd, reg_t arg, reg_t a3, reg_t a4, reg_t a5, reg_t a6) +{ + return sysret_errno(fcntl(fds.lookup(fd), cmd, arg)); +} + +reg_t syscall_t::sys_ftruncate(reg_t fd, reg_t len, reg_t a2, reg_t a3, reg_t a4, reg_t a5, reg_t a6) +{ + return sysret_errno(ftruncate(fds.lookup(fd), len)); +} + +reg_t syscall_t::sys_lstat(reg_t pname, reg_t len, reg_t pbuf, reg_t a3, reg_t a4, reg_t a5, reg_t a6) +{ + std::vector<char> name(len); + memif->read(pname, len, name.data()); + + struct stat buf; + reg_t ret = sysret_errno(lstat(do_chroot(name.data()).c_str(), &buf)); + if (ret != (reg_t)-1) + { + riscv_stat rbuf(buf, htif); + memif->write(pbuf, sizeof(rbuf), &rbuf); + } + return ret; +} + +reg_t syscall_t::sys_statx(reg_t fd, reg_t pname, reg_t len, reg_t flags, reg_t mask, reg_t pbuf, reg_t a6) +{ +#ifndef HAVE_STATX + return -ENOSYS; +#else + std::vector<char> name(len); + memif->read(pname, len, name.data()); + + struct statx buf; + reg_t ret = sysret_errno(statx(fds.lookup(fd), do_chroot(name.data()).c_str(), flags, mask, &buf)); + if (ret != (reg_t)-1) + { + riscv_statx rbuf(buf, htif); + memif->write(pbuf, sizeof(rbuf), &rbuf); + } + return ret; +#endif +} + +#define AT_SYSCALL(syscall, fd, name, ...) \ + (syscall(fds.lookup(fd), int(fd) == RISCV_AT_FDCWD ? do_chroot(name).c_str() : (name), __VA_ARGS__)) + +reg_t syscall_t::sys_openat(reg_t dirfd, reg_t pname, reg_t len, reg_t flags, reg_t mode, reg_t a5, reg_t a6) +{ + std::vector<char> name(len); + memif->read(pname, len, name.data()); + int fd = sysret_errno(AT_SYSCALL(openat, dirfd, name.data(), flags, mode)); + if (fd < 0) + return sysret_errno(-1); + return fds.alloc(fd); +} + +reg_t syscall_t::sys_fstatat(reg_t dirfd, reg_t pname, reg_t len, reg_t pbuf, reg_t flags, reg_t a5, reg_t a6) +{ + std::vector<char> name(len); + memif->read(pname, len, name.data()); + + struct stat buf; + reg_t ret = sysret_errno(AT_SYSCALL(fstatat, dirfd, name.data(), &buf, flags)); + if (ret != (reg_t)-1) + { + riscv_stat rbuf(buf, htif); + memif->write(pbuf, sizeof(rbuf), &rbuf); + } + return ret; +} + +reg_t syscall_t::sys_faccessat(reg_t dirfd, reg_t pname, reg_t len, reg_t mode, reg_t a4, reg_t a5, reg_t a6) +{ + std::vector<char> name(len); + memif->read(pname, len, name.data()); + return sysret_errno(AT_SYSCALL(faccessat, dirfd, name.data(), mode, 0)); +} + +reg_t syscall_t::sys_renameat(reg_t odirfd, reg_t popath, reg_t olen, reg_t ndirfd, reg_t pnpath, reg_t nlen, reg_t a6) +{ + std::vector<char> opath(olen), npath(nlen); + memif->read(popath, olen, opath.data()); + memif->read(pnpath, nlen, npath.data()); + return sysret_errno(renameat(fds.lookup(odirfd), int(odirfd) == RISCV_AT_FDCWD ? do_chroot(opath.data()).c_str() : opath.data(), + fds.lookup(ndirfd), int(ndirfd) == RISCV_AT_FDCWD ? do_chroot(npath.data()).c_str() : npath.data())); +} + +reg_t syscall_t::sys_linkat(reg_t odirfd, reg_t poname, reg_t olen, reg_t ndirfd, reg_t pnname, reg_t nlen, reg_t flags) +{ + std::vector<char> oname(olen), nname(nlen); + memif->read(poname, olen, oname.data()); + memif->read(pnname, nlen, nname.data()); + return sysret_errno(linkat(fds.lookup(odirfd), int(odirfd) == RISCV_AT_FDCWD ? do_chroot(oname.data()).c_str() : oname.data(), + fds.lookup(ndirfd), int(ndirfd) == RISCV_AT_FDCWD ? do_chroot(nname.data()).c_str() : nname.data(), + flags)); +} + +reg_t syscall_t::sys_unlinkat(reg_t dirfd, reg_t pname, reg_t len, reg_t flags, reg_t a4, reg_t a5, reg_t a6) +{ + std::vector<char> name(len); + memif->read(pname, len, name.data()); + return sysret_errno(AT_SYSCALL(unlinkat, dirfd, name.data(), flags)); +} + +reg_t syscall_t::sys_mkdirat(reg_t dirfd, reg_t pname, reg_t len, reg_t mode, reg_t a4, reg_t a5, reg_t a6) +{ + std::vector<char> name(len); + memif->read(pname, len, name.data()); + return sysret_errno(AT_SYSCALL(mkdirat, dirfd, name.data(), mode)); +} + +reg_t syscall_t::sys_getcwd(reg_t pbuf, reg_t size, reg_t a2, reg_t a3, reg_t a4, reg_t a5, reg_t a6) +{ + std::vector<char> buf(size); + char* ret = getcwd(buf.data(), size); + if (ret == NULL) + return sysret_errno(-1); + std::string tmp = undo_chroot(buf.data()); + if (size <= tmp.size()) + return -ENOMEM; + memif->write(pbuf, tmp.size() + 1, tmp.data()); + return tmp.size() + 1; +} + +reg_t syscall_t::sys_getmainvars(reg_t pbuf, reg_t limit, reg_t a2, reg_t a3, reg_t a4, reg_t a5, reg_t a6) +{ + std::vector<std::string> args = htif->target_args(); + std::vector<target_endian<uint64_t>> words(args.size() + 3); + words[0] = htif->to_target<uint64_t>(args.size()); + words[args.size()+1] = target_endian<uint64_t>::zero; // argv[argc] = NULL + words[args.size()+2] = target_endian<uint64_t>::zero; // envp[0] = NULL + + size_t sz = (args.size() + 3) * sizeof(words[0]); + for (size_t i = 0; i < args.size(); i++) + { + words[i+1] = htif->to_target<uint64_t>(sz + pbuf); + sz += args[i].length() + 1; + } + + std::vector<char> bytes(sz); + memcpy(bytes.data(), words.data(), sizeof(words[0]) * words.size()); + for (size_t i = 0; i < args.size(); i++) + strcpy(&bytes[htif->from_target(words[i+1]) - pbuf], args[i].c_str()); + + if (bytes.size() > limit) + return -ENOMEM; + + memif->write(pbuf, bytes.size(), bytes.data()); + return 0; +} + +reg_t syscall_t::sys_chdir(reg_t path, reg_t a1, reg_t a2, reg_t a3, reg_t a4, reg_t a5, reg_t a6) +{ + size_t size = 0; + while (memif->read_uint8(path + size++)) + ; + std::vector<char> buf(size); + for (size_t offset = 0;; offset++) + { + buf[offset] = memif->read_uint8(path + offset); + if (!buf[offset]) + break; + } + return sysret_errno(chdir(buf.data())); +} + +void syscall_t::dispatch(reg_t mm) +{ + target_endian<reg_t> magicmem[8]; + memif->read(mm, sizeof(magicmem), magicmem); + + reg_t n = htif->from_target(magicmem[0]); + if (n >= table.size() || !table[n]) + throw std::runtime_error("bad syscall #" + std::to_string(n)); + + magicmem[0] = htif->to_target((this->*table[n])(htif->from_target(magicmem[1]), htif->from_target(magicmem[2]), htif->from_target(magicmem[3]), htif->from_target(magicmem[4]), htif->from_target(magicmem[5]), htif->from_target(magicmem[6]), htif->from_target(magicmem[7]))); + + memif->write(mm, sizeof(magicmem), magicmem); +} + +reg_t fds_t::alloc(int fd) +{ + reg_t i; + for (i = 0; i < fds.size(); i++) + if (fds[i] == -1) + break; + + if (i == fds.size()) + fds.resize(i+1); + + fds[i] = fd; + return i; +} + +void fds_t::dealloc(reg_t fd) +{ + fds[fd] = -1; +} + +int fds_t::lookup(reg_t fd) +{ + if (int(fd) == RISCV_AT_FDCWD) + return AT_FDCWD; + return fd >= fds.size() ? -1 : fds[fd]; +} + +void syscall_t::set_chroot(const char* where) +{ + char buf1[PATH_MAX], buf2[PATH_MAX]; + + if (getcwd(buf1, sizeof(buf1)) == NULL + || chdir(where) != 0 + || getcwd(buf2, sizeof(buf2)) == NULL + || chdir(buf1) != 0) + { + fprintf(stderr, "could not chroot to %s\n", where); + exit(-1); + } + + chroot = buf2; +} diff --git a/vendor/riscv/riscv-isa-sim/fesvr/syscall.h b/vendor/riscv/riscv-isa-sim/fesvr/syscall.h new file mode 100644 index 0000000000..c002e6c66e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/fesvr/syscall.h @@ -0,0 +1,75 @@ +// See LICENSE for license details. + +#ifndef __SYSCALL_H +#define __SYSCALL_H + +#include "device.h" +#include "memif.h" +#include <vector> +#include <string> + +class syscall_t; +typedef reg_t (syscall_t::*syscall_func_t)(reg_t, reg_t, reg_t, reg_t, reg_t, reg_t, reg_t); + +class htif_t; +class memif_t; + +class fds_t +{ + public: + reg_t alloc(int fd); + void dealloc(reg_t fd); + int lookup(reg_t fd); + private: + std::vector<int> fds; +}; + +class syscall_t : public device_t +{ + public: + syscall_t(htif_t*); + ~syscall_t(); + + void set_chroot(const char* where); + + private: + const char* identity() { return "syscall_proxy"; } + + htif_t* htif; + memif_t* memif; + std::vector<syscall_func_t> table; + fds_t fds; + std::vector<reg_t> fds_index; + + void handle_syscall(command_t cmd); + void dispatch(addr_t mm); + + std::string chroot; + std::string do_chroot(const char* fn); + std::string undo_chroot(const char* fn); + + reg_t sys_exit(reg_t, reg_t, reg_t, reg_t, reg_t, reg_t, reg_t); + reg_t sys_openat(reg_t, reg_t, reg_t, reg_t, reg_t, reg_t, reg_t); + reg_t sys_read(reg_t, reg_t, reg_t, reg_t, reg_t, reg_t, reg_t); + reg_t sys_pread(reg_t, reg_t, reg_t, reg_t, reg_t, reg_t, reg_t); + reg_t sys_write(reg_t, reg_t, reg_t, reg_t, reg_t, reg_t, reg_t); + reg_t sys_pwrite(reg_t, reg_t, reg_t, reg_t, reg_t, reg_t, reg_t); + reg_t sys_close(reg_t, reg_t, reg_t, reg_t, reg_t, reg_t, reg_t); + reg_t sys_lseek(reg_t, reg_t, reg_t, reg_t, reg_t, reg_t, reg_t); + reg_t sys_fstat(reg_t, reg_t, reg_t, reg_t, reg_t, reg_t, reg_t); + reg_t sys_lstat(reg_t, reg_t, reg_t, reg_t, reg_t, reg_t, reg_t); + reg_t sys_statx(reg_t, reg_t, reg_t, reg_t, reg_t, reg_t, reg_t); + reg_t sys_fstatat(reg_t, reg_t, reg_t, reg_t, reg_t, reg_t, reg_t); + reg_t sys_faccessat(reg_t, reg_t, reg_t, reg_t, reg_t, reg_t, reg_t); + reg_t sys_fcntl(reg_t, reg_t, reg_t, reg_t, reg_t, reg_t, reg_t); + reg_t sys_ftruncate(reg_t, reg_t, reg_t, reg_t, reg_t, reg_t, reg_t); + reg_t sys_renameat(reg_t, reg_t, reg_t, reg_t, reg_t, reg_t, reg_t); + reg_t sys_linkat(reg_t, reg_t, reg_t, reg_t, reg_t, reg_t, reg_t); + reg_t sys_unlinkat(reg_t, reg_t, reg_t, reg_t, reg_t, reg_t, reg_t); + reg_t sys_mkdirat(reg_t, reg_t, reg_t, reg_t, reg_t, reg_t, reg_t); + reg_t sys_getcwd(reg_t, reg_t, reg_t, reg_t, reg_t, reg_t, reg_t); + reg_t sys_getmainvars(reg_t, reg_t, reg_t, reg_t, reg_t, reg_t, reg_t); + reg_t sys_chdir(reg_t, reg_t, reg_t, reg_t, reg_t, reg_t, reg_t); +}; + +#endif diff --git a/vendor/riscv/riscv-isa-sim/fesvr/term.cc b/vendor/riscv/riscv-isa-sim/fesvr/term.cc new file mode 100644 index 0000000000..c4cba0c07c --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/fesvr/term.cc @@ -0,0 +1,53 @@ +#include "term.h" +#include <termios.h> +#include <unistd.h> +#include <poll.h> +#include <signal.h> +#include <stdlib.h> + +class canonical_termios_t +{ + public: + canonical_termios_t() + : restore_tios(false) + { + if (tcgetattr(0, &old_tios) == 0) + { + struct termios new_tios = old_tios; + new_tios.c_lflag &= ~(ICANON | ECHO); + if (tcsetattr(0, TCSANOW, &new_tios) == 0) + restore_tios = true; + } + } + + ~canonical_termios_t() + { + if (restore_tios) + tcsetattr(0, TCSANOW, &old_tios); + } + private: + struct termios old_tios; + bool restore_tios; +}; + +static canonical_termios_t tios; // exit() will clean up for us + +int canonical_terminal_t::read() +{ + struct pollfd pfd; + pfd.fd = 0; + pfd.events = POLLIN; + int ret = poll(&pfd, 1, 0); + if (ret <= 0 || !(pfd.revents & POLLIN)) + return -1; + + unsigned char ch; + ret = ::read(0, &ch, 1); + return ret <= 0 ? -1 : ch; +} + +void canonical_terminal_t::write(char ch) +{ + if (::write(1, &ch, 1) != 1) + abort(); +} diff --git a/vendor/riscv/riscv-isa-sim/fesvr/term.h b/vendor/riscv/riscv-isa-sim/fesvr/term.h new file mode 100644 index 0000000000..7a2c22fc28 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/fesvr/term.h @@ -0,0 +1,11 @@ +#ifndef _TERM_H +#define _TERM_H + +class canonical_terminal_t +{ + public: + static int read(); + static void write(char); +}; + +#endif diff --git a/vendor/riscv/riscv-isa-sim/fesvr/tsi.cc b/vendor/riscv/riscv-isa-sim/fesvr/tsi.cc new file mode 100644 index 0000000000..5ccafc4b77 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/fesvr/tsi.cc @@ -0,0 +1,115 @@ +#include "tsi.h" +#include <cstdio> +#include <cstdlib> + +#define NHARTS_MAX 16 + +void tsi_t::host_thread(void *arg) +{ + tsi_t *tsi = static_cast<tsi_t*>(arg); + tsi->run(); + + while (true) + tsi->target->switch_to(); +} + +tsi_t::tsi_t(int argc, char** argv) : htif_t(argc, argv) +{ + target = context_t::current(); + host.init(host_thread, this); +} + +tsi_t::~tsi_t(void) +{ +} + +#define MSIP_BASE 0x2000000 + +// Interrupt core 0 to make it start executing the program in DRAM +void tsi_t::reset() +{ + uint32_t one = 1; + + write_chunk(MSIP_BASE, sizeof(uint32_t), &one); +} + +void tsi_t::push_addr(addr_t addr) +{ + for (int i = 0; i < SAI_ADDR_CHUNKS; i++) { + in_data.push_back(addr & 0xffffffff); + addr = addr >> 32; + } +} + +void tsi_t::push_len(addr_t len) +{ + for (int i = 0; i < SAI_LEN_CHUNKS; i++) { + in_data.push_back(len & 0xffffffff); + len = len >> 32; + } +} + +void tsi_t::read_chunk(addr_t taddr, size_t nbytes, void* dst) +{ + uint32_t *result = static_cast<uint32_t*>(dst); + size_t len = nbytes / sizeof(uint32_t); + + in_data.push_back(SAI_CMD_READ); + push_addr(taddr); + push_len(len - 1); + + for (size_t i = 0; i < len; i++) { + while (out_data.empty()) + switch_to_target(); + result[i] = out_data.front(); + out_data.pop_front(); + } +} + +void tsi_t::write_chunk(addr_t taddr, size_t nbytes, const void* src) +{ + const uint32_t *src_data = static_cast<const uint32_t*>(src); + size_t len = nbytes / sizeof(uint32_t); + + in_data.push_back(SAI_CMD_WRITE); + push_addr(taddr); + push_len(len - 1); + + in_data.insert(in_data.end(), src_data, src_data + len); +} + +void tsi_t::send_word(uint32_t word) +{ + out_data.push_back(word); +} + +uint32_t tsi_t::recv_word(void) +{ + uint32_t word = in_data.front(); + in_data.pop_front(); + return word; +} + +bool tsi_t::data_available(void) +{ + return !in_data.empty(); +} + +void tsi_t::switch_to_host(void) +{ + host.switch_to(); +} + +void tsi_t::switch_to_target(void) +{ + target->switch_to(); +} + +void tsi_t::tick(bool out_valid, uint32_t out_bits, bool in_ready) +{ + if (out_valid && out_ready()) + out_data.push_back(out_bits); + + if (in_valid() && in_ready) + in_data.pop_front(); +} diff --git a/vendor/riscv/riscv-isa-sim/fesvr/tsi.h b/vendor/riscv/riscv-isa-sim/fesvr/tsi.h new file mode 100644 index 0000000000..825a3a0038 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/fesvr/tsi.h @@ -0,0 +1,57 @@ +#ifndef __SAI_H +#define __SAI_H + +#include "htif.h" +#include "context.h" + +#include <string> +#include <vector> +#include <deque> +#include <stdint.h> + +#define SAI_CMD_READ 0 +#define SAI_CMD_WRITE 1 + +#define SAI_ADDR_CHUNKS 2 +#define SAI_LEN_CHUNKS 2 + +class tsi_t : public htif_t +{ + public: + tsi_t(int argc, char** argv); + virtual ~tsi_t(); + + bool data_available(); + void send_word(uint32_t word); + uint32_t recv_word(); + void switch_to_host(); + + uint32_t in_bits() { return in_data.front(); } + bool in_valid() { return !in_data.empty(); } + bool out_ready() { return true; } + void tick(bool out_valid, uint32_t out_bits, bool in_ready); + + protected: + void reset() override; + void read_chunk(addr_t taddr, size_t nbytes, void* dst) override; + void write_chunk(addr_t taddr, size_t nbytes, const void* src) override; + void switch_to_target(); + + size_t chunk_align() override { return 4; } + size_t chunk_max_size() override { return 1024; } + + int get_ipi_addrs(addr_t *addrs); + + private: + context_t host; + context_t* target; + std::deque<uint32_t> in_data; + std::deque<uint32_t> out_data; + + void push_addr(addr_t addr); + void push_len(addr_t len); + + static void host_thread(void *tsi); +}; + +#endif diff --git a/vendor/riscv/riscv-isa-sim/riscv-disasm.pc.in b/vendor/riscv/riscv-isa-sim/riscv-disasm.pc.in new file mode 100644 index 0000000000..915136aa3f --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv-disasm.pc.in @@ -0,0 +1,11 @@ +prefix=@prefix@ +exec_prefix=@prefix@ +libdir=@libdir@ +includedir=@includedir@ + +Name: riscv-disasm +Description: RISC-V disassembler +Version: git +Libs: -Wl,-rpath,${libdir} -L${libdir} -ldisasm +Cflags: -I${includedir} +URL: http://riscv.org/download.html#tab_disasm diff --git a/vendor/riscv/riscv-isa-sim/riscv-fesvr.pc.in b/vendor/riscv/riscv-isa-sim/riscv-fesvr.pc.in new file mode 100644 index 0000000000..82a95693d1 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv-fesvr.pc.in @@ -0,0 +1,11 @@ +prefix=@prefix@ +exec_prefix=@prefix@ +libdir=@libdir@ +includedir=@includedir@ + +Name: riscv-fesvr +Description: RISC-V front-end server +Version: git +Libs: -Wl,-rpath,${libdir} -L${libdir} -lfesvr +Cflags: -I${includedir} +URL: http://riscv.org/download.html#tab_fesvr diff --git a/vendor/riscv/riscv-isa-sim/riscv/abstract_device.h b/vendor/riscv/riscv-isa-sim/riscv/abstract_device.h new file mode 100644 index 0000000000..559c64f6d6 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/abstract_device.h @@ -0,0 +1,15 @@ +#ifndef _RISCV_ABSTRACT_DEVICE_H +#define _RISCV_ABSTRACT_DEVICE_H + +#include "decode.h" +#include <cstdint> +#include <cstddef> + +class abstract_device_t { + public: + virtual bool load(reg_t addr, size_t len, uint8_t* bytes) = 0; + virtual bool store(reg_t addr, size_t len, const uint8_t* bytes) = 0; + virtual ~abstract_device_t() {} +}; + +#endif diff --git a/vendor/riscv/riscv-isa-sim/riscv/abstract_interrupt_controller.h b/vendor/riscv/riscv-isa-sim/riscv/abstract_interrupt_controller.h new file mode 100644 index 0000000000..946b079f74 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/abstract_interrupt_controller.h @@ -0,0 +1,14 @@ +#ifndef _RISCV_ABSTRACT_INTERRUPT_CONTROLLER_H +#define _RISCV_ABSTRACT_INTERRUPT_CONTROLLER_H + +#include "decode.h" +#include <cstdint> +#include <cstddef> + +class abstract_interrupt_controller_t { + public: + virtual void set_interrupt_level(uint32_t interrupt_id, int level) = 0; + virtual ~abstract_interrupt_controller_t() {} +}; + +#endif diff --git a/vendor/riscv/riscv-isa-sim/riscv/arith.h b/vendor/riscv/riscv-isa-sim/riscv/arith.h new file mode 100644 index 0000000000..3b807e9698 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/arith.h @@ -0,0 +1,224 @@ +// See LICENSE for license details. + +#ifndef _RISCV_ARITH_H +#define _RISCV_ARITH_H + +#include <cassert> +#include <cstdint> +#include <climits> +#include <cstddef> + +inline uint64_t mulhu(uint64_t a, uint64_t b) +{ + uint64_t t; + uint32_t y1, y2, y3; + uint64_t a0 = (uint32_t)a, a1 = a >> 32; + uint64_t b0 = (uint32_t)b, b1 = b >> 32; + + t = a1*b0 + ((a0*b0) >> 32); + y1 = t; + y2 = t >> 32; + + t = a0*b1 + y1; + + t = a1*b1 + y2 + (t >> 32); + y2 = t; + y3 = t >> 32; + + return ((uint64_t)y3 << 32) | y2; +} + +inline int64_t mulh(int64_t a, int64_t b) +{ + int negate = (a < 0) != (b < 0); + uint64_t res = mulhu(a < 0 ? -a : a, b < 0 ? -b : b); + return negate ? ~res + (a * b == 0) : res; +} + +inline int64_t mulhsu(int64_t a, uint64_t b) +{ + int negate = a < 0; + uint64_t res = mulhu(a < 0 ? -a : a, b); + return negate ? ~res + (a * b == 0) : res; +} + +//ref: https://locklessinc.com/articles/sat_arithmetic/ +template<typename T, typename UT> +static inline T sat_add(T x, T y, bool &sat) +{ + UT ux = x; + UT uy = y; + UT res = ux + uy; + sat = false; + int sh = sizeof(T) * 8 - 1; + + /* Calculate overflowed result. (Don't change the sign bit of ux) */ + ux = (ux >> sh) + (((UT)0x1 << sh) - 1); + + /* Force compiler to use cmovns instruction */ + if ((T) ((ux ^ uy) | ~(uy ^ res)) >= 0) { + res = ux; + sat = true; + } + + return res; +} + +template<typename T, typename UT> +static inline T sat_add(T x, T y, T z, bool &sat) +{ + bool sat1, sat2; + T a = y; + T b = z; + T res; + + /* Force compiler to use cmovs instruction */ + if (((y ^ z) & (x ^ z)) < 0) { + a = z; + b = y; + } + + res = sat_add<T, UT>(x, a, sat1); + res = sat_add<T, UT>(res, b, sat2); + sat = sat1 || sat2; + + return res; +} + +template<typename T, typename UT> +static inline T sat_sub(T x, T y, bool &sat) +{ + UT ux = x; + UT uy = y; + UT res = ux - uy; + sat = false; + int sh = sizeof(T) * 8 - 1; + + /* Calculate overflowed result. (Don't change the sign bit of ux) */ + ux = (ux >> sh) + (((UT)0x1 << sh) - 1); + + /* Force compiler to use cmovns instruction */ + if ((T) ((ux ^ uy) & (ux ^ res)) < 0) { + res = ux; + sat = true; + } + + return res; +} + +template<typename T> +T sat_addu(T x, T y, bool &sat) +{ + T res = x + y; + sat = false; + + sat = res < x; + res |= -(res < x); + + return res; +} + +template<typename T> +T sat_subu(T x, T y, bool &sat) +{ + T res = x - y; + sat = false; + + sat = !(res <= x); + res &= -(res <= x); + + return res; +} + +static inline uint64_t extract64(uint64_t val, int pos, int len) +{ + assert(pos >= 0 && len > 0 && len <= 64 - pos); + return (val >> pos) & (~UINT64_C(0) >> (64 - len)); +} + +static inline uint64_t make_mask64(int pos, int len) +{ + assert(pos >= 0 && len > 0 && pos < 64 && len <= 64); + return (UINT64_MAX >> (64 - len)) << pos; +} + +static inline int popcount(uint64_t val) +{ + val = (val & 0x5555555555555555U) + ((val >> 1) & 0x5555555555555555U); + val = (val & 0x3333333333333333U) + ((val >> 2) & 0x3333333333333333U); + val = (val & 0x0f0f0f0f0f0f0f0fU) + ((val >> 4) & 0x0f0f0f0f0f0f0f0fU); + val = (val & 0x00ff00ff00ff00ffU) + ((val >> 8) & 0x00ff00ff00ff00ffU); + val = (val & 0x0000ffff0000ffffU) + ((val >> 16) & 0x0000ffff0000ffffU); + val = (val & 0x00000000ffffffffU) + ((val >> 32) & 0x00000000ffffffffU); + return val; +} + +static inline int ctz(uint64_t val) +{ + if (!val) + return 0; + + int res = 0; + + if ((val << 32) == 0) res += 32, val >>= 32; + if ((val << 48) == 0) res += 16, val >>= 16; + if ((val << 56) == 0) res += 8, val >>= 8; + if ((val << 60) == 0) res += 4, val >>= 4; + if ((val << 62) == 0) res += 2, val >>= 2; + if ((val << 63) == 0) res += 1, val >>= 1; + + return res; +} + +static inline int clz(uint64_t val) +{ + if (!val) + return 0; + + int res = 0; + + if ((val >> 32) == 0) res += 32, val <<= 32; + if ((val >> 48) == 0) res += 16, val <<= 16; + if ((val >> 56) == 0) res += 8, val <<= 8; + if ((val >> 60) == 0) res += 4, val <<= 4; + if ((val >> 62) == 0) res += 2, val <<= 2; + if ((val >> 63) == 0) res += 1, val <<= 1; + + return res; +} + +// Count number of contiguous 1 bits starting from the LSB. +static inline int cto(uint64_t val) +{ + int res = 0; + while ((val & 1) == 1) + val >>= 1, res++; + return res; +} + +static inline int log2(uint64_t val) +{ + if (!val) + return 0; + + return 63 - clz(val); +} + +static inline uint64_t xperm(uint64_t rs1, uint64_t rs2, size_t sz_log2, size_t len) +{ + uint64_t r = 0; + uint64_t sz = 1LL << sz_log2; + uint64_t mask = (1LL << sz) - 1; + + assert(sz_log2 <= 6 && len <= 64); + + for (size_t i = 0; i < len; i += sz) { + uint64_t pos = ((rs2 >> i) & mask) << sz_log2; + if (pos < len) + r |= ((rs1 >> pos) & mask) << i; + } + + return r; +} + +#endif diff --git a/vendor/riscv/riscv-isa-sim/riscv/cachesim.cc b/vendor/riscv/riscv-isa-sim/riscv/cachesim.cc new file mode 100644 index 0000000000..24e87d3778 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/cachesim.cc @@ -0,0 +1,207 @@ +// See LICENSE for license details. + +#include "cachesim.h" +#include "common.h" +#include <cstdlib> +#include <iostream> +#include <iomanip> + +cache_sim_t::cache_sim_t(size_t _sets, size_t _ways, size_t _linesz, const char* _name) +: sets(_sets), ways(_ways), linesz(_linesz), name(_name), log(false) +{ + init(); +} + +static void help() +{ + std::cerr << "Cache configurations must be of the form" << std::endl; + std::cerr << " sets:ways:blocksize" << std::endl; + std::cerr << "where sets, ways, and blocksize are positive integers, with" << std::endl; + std::cerr << "sets and blocksize both powers of two and blocksize at least 8." << std::endl; + exit(1); +} + +cache_sim_t* cache_sim_t::construct(const char* config, const char* name) +{ + const char* wp = strchr(config, ':'); + if (!wp++) help(); + const char* bp = strchr(wp, ':'); + if (!bp++) help(); + + size_t sets = atoi(std::string(config, wp).c_str()); + size_t ways = atoi(std::string(wp, bp).c_str()); + size_t linesz = atoi(bp); + + if (ways > 4 /* empirical */ && sets == 1) + return new fa_cache_sim_t(ways, linesz, name); + return new cache_sim_t(sets, ways, linesz, name); +} + +void cache_sim_t::init() +{ + if (sets == 0 || (sets & (sets-1))) + help(); + if (linesz < 8 || (linesz & (linesz-1))) + help(); + + idx_shift = 0; + for (size_t x = linesz; x>1; x >>= 1) + idx_shift++; + + tags = new uint64_t[sets*ways](); + read_accesses = 0; + read_misses = 0; + bytes_read = 0; + write_accesses = 0; + write_misses = 0; + bytes_written = 0; + writebacks = 0; + + miss_handler = NULL; +} + +cache_sim_t::cache_sim_t(const cache_sim_t& rhs) + : sets(rhs.sets), ways(rhs.ways), linesz(rhs.linesz), + idx_shift(rhs.idx_shift), name(rhs.name), log(false) +{ + tags = new uint64_t[sets*ways]; + memcpy(tags, rhs.tags, sets*ways*sizeof(uint64_t)); +} + +cache_sim_t::~cache_sim_t() +{ + print_stats(); + delete [] tags; +} + +void cache_sim_t::print_stats() +{ + float mr = 100.0f*(read_misses+write_misses)/(read_accesses+write_accesses); + + std::cout << std::setprecision(3) << std::fixed; + std::cout << name << " "; + std::cout << "Bytes Read: " << bytes_read << std::endl; + std::cout << name << " "; + std::cout << "Bytes Written: " << bytes_written << std::endl; + std::cout << name << " "; + std::cout << "Read Accesses: " << read_accesses << std::endl; + std::cout << name << " "; + std::cout << "Write Accesses: " << write_accesses << std::endl; + std::cout << name << " "; + std::cout << "Read Misses: " << read_misses << std::endl; + std::cout << name << " "; + std::cout << "Write Misses: " << write_misses << std::endl; + std::cout << name << " "; + std::cout << "Writebacks: " << writebacks << std::endl; + std::cout << name << " "; + std::cout << "Miss Rate: " << mr << '%' << std::endl; +} + +uint64_t* cache_sim_t::check_tag(uint64_t addr) +{ + size_t idx = (addr >> idx_shift) & (sets-1); + size_t tag = (addr >> idx_shift) | VALID; + + for (size_t i = 0; i < ways; i++) + if (tag == (tags[idx*ways + i] & ~DIRTY)) + return &tags[idx*ways + i]; + + return NULL; +} + +uint64_t cache_sim_t::victimize(uint64_t addr) +{ + size_t idx = (addr >> idx_shift) & (sets-1); + size_t way = lfsr.next() % ways; + uint64_t victim = tags[idx*ways + way]; + tags[idx*ways + way] = (addr >> idx_shift) | VALID; + return victim; +} + +void cache_sim_t::access(uint64_t addr, size_t bytes, bool store) +{ + store ? write_accesses++ : read_accesses++; + (store ? bytes_written : bytes_read) += bytes; + + uint64_t* hit_way = check_tag(addr); + if (likely(hit_way != NULL)) + { + if (store) + *hit_way |= DIRTY; + return; + } + + store ? write_misses++ : read_misses++; + if (log) + { + std::cerr << name << " " + << (store ? "write" : "read") << " miss 0x" + << std::hex << addr << std::endl; + } + + uint64_t victim = victimize(addr); + + if ((victim & (VALID | DIRTY)) == (VALID | DIRTY)) + { + uint64_t dirty_addr = (victim & ~(VALID | DIRTY)) << idx_shift; + if (miss_handler) + miss_handler->access(dirty_addr, linesz, true); + writebacks++; + } + + if (miss_handler) + miss_handler->access(addr & ~(linesz-1), linesz, false); + + if (store) + *check_tag(addr) |= DIRTY; +} + +void cache_sim_t::clean_invalidate(uint64_t addr, size_t bytes, bool clean, bool inval) +{ + uint64_t start_addr = addr & ~(linesz-1); + uint64_t end_addr = (addr + bytes + linesz-1) & ~(linesz-1); + uint64_t cur_addr = start_addr; + while (cur_addr < end_addr) { + uint64_t* hit_way = check_tag(cur_addr); + if (likely(hit_way != NULL)) + { + if (clean) { + if (*hit_way & DIRTY) { + writebacks++; + *hit_way &= ~DIRTY; + } + } + + if (inval) + *hit_way &= ~VALID; + } + cur_addr += linesz; + } + if (miss_handler) + miss_handler->clean_invalidate(addr, bytes, clean, inval); +} + +fa_cache_sim_t::fa_cache_sim_t(size_t ways, size_t linesz, const char* name) + : cache_sim_t(1, ways, linesz, name) +{ +} + +uint64_t* fa_cache_sim_t::check_tag(uint64_t addr) +{ + auto it = tags.find(addr >> idx_shift); + return it == tags.end() ? NULL : &it->second; +} + +uint64_t fa_cache_sim_t::victimize(uint64_t addr) +{ + uint64_t old_tag = 0; + if (tags.size() == ways) + { + auto it = tags.begin(); + std::advance(it, lfsr.next() % ways); + old_tag = it->second; + tags.erase(it); + } + tags[addr >> idx_shift] = (addr >> idx_shift) | VALID; + return old_tag; +} diff --git a/vendor/riscv/riscv-isa-sim/riscv/cachesim.h b/vendor/riscv/riscv-isa-sim/riscv/cachesim.h new file mode 100644 index 0000000000..a96e639f88 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/cachesim.h @@ -0,0 +1,142 @@ +// See LICENSE for license details. + +#ifndef _RISCV_CACHE_SIM_H +#define _RISCV_CACHE_SIM_H + +#include "memtracer.h" +#include "common.h" +#include <cstring> +#include <string> +#include <map> +#include <cstdint> + +class lfsr_t +{ + public: + lfsr_t() : reg(1) {} + lfsr_t(const lfsr_t& lfsr) : reg(lfsr.reg) {} + uint32_t next() { return reg = (reg>>1)^(-(reg&1) & 0xd0000001); } + private: + uint32_t reg; +}; + +class cache_sim_t +{ + public: + cache_sim_t(size_t sets, size_t ways, size_t linesz, const char* name); + cache_sim_t(const cache_sim_t& rhs); + virtual ~cache_sim_t(); + + void access(uint64_t addr, size_t bytes, bool store); + void clean_invalidate(uint64_t addr, size_t bytes, bool clean, bool inval); + void print_stats(); + void set_miss_handler(cache_sim_t* mh) { miss_handler = mh; } + void set_log(bool _log) { log = _log; } + + static cache_sim_t* construct(const char* config, const char* name); + + protected: + static const uint64_t VALID = 1ULL << 63; + static const uint64_t DIRTY = 1ULL << 62; + + virtual uint64_t* check_tag(uint64_t addr); + virtual uint64_t victimize(uint64_t addr); + + lfsr_t lfsr; + cache_sim_t* miss_handler; + + size_t sets; + size_t ways; + size_t linesz; + size_t idx_shift; + + uint64_t* tags; + + uint64_t read_accesses; + uint64_t read_misses; + uint64_t bytes_read; + uint64_t write_accesses; + uint64_t write_misses; + uint64_t bytes_written; + uint64_t writebacks; + + std::string name; + bool log; + + void init(); +}; + +class fa_cache_sim_t : public cache_sim_t +{ + public: + fa_cache_sim_t(size_t ways, size_t linesz, const char* name); + uint64_t* check_tag(uint64_t addr); + uint64_t victimize(uint64_t addr); + private: + static bool cmp(uint64_t a, uint64_t b); + std::map<uint64_t, uint64_t> tags; +}; + +class cache_memtracer_t : public memtracer_t +{ + public: + cache_memtracer_t(const char* config, const char* name) + { + cache = cache_sim_t::construct(config, name); + } + ~cache_memtracer_t() + { + delete cache; + } + void set_miss_handler(cache_sim_t* mh) + { + cache->set_miss_handler(mh); + } + void clean_invalidate(uint64_t addr, size_t bytes, bool clean, bool inval) + { + cache->clean_invalidate(addr, bytes, clean, inval); + } + void set_log(bool log) + { + cache->set_log(log); + } + void print_stats() + { + cache->print_stats(); + } + + protected: + cache_sim_t* cache; +}; + +class icache_sim_t : public cache_memtracer_t +{ + public: + icache_sim_t(const char* config, const char* name = "I$") + : cache_memtracer_t(config, name) {} + bool interested_in_range(uint64_t UNUSED begin, uint64_t UNUSED end, access_type type) + { + return type == FETCH; + } + void trace(uint64_t addr, size_t bytes, access_type type) + { + if (type == FETCH) cache->access(addr, bytes, false); + } +}; + +class dcache_sim_t : public cache_memtracer_t +{ + public: + dcache_sim_t(const char* config, const char* name = "D$") + : cache_memtracer_t(config, name) {} + bool interested_in_range(uint64_t UNUSED begin, uint64_t UNUSED end, access_type type) + { + return type == LOAD || type == STORE; + } + void trace(uint64_t addr, size_t bytes, access_type type) + { + if (type == LOAD || type == STORE) cache->access(addr, bytes, type == STORE); + } +}; + +#endif diff --git a/vendor/riscv/riscv-isa-sim/riscv/cfg.cc b/vendor/riscv/riscv-isa-sim/riscv/cfg.cc new file mode 100644 index 0000000000..457aa92baa --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/cfg.cc @@ -0,0 +1,27 @@ +// See LICENSE for license details. + +#include "cfg.h" +#include "mmu.h" +#include "decode.h" + +mem_cfg_t::mem_cfg_t(reg_t base, reg_t size) : base(base), size(size) +{ + assert(mem_cfg_t::check_if_supported(base, size)); +} + +bool mem_cfg_t::check_if_supported(reg_t base, reg_t size) +{ + // The truth of these conditions should be ensured by whatever is creating + // the regions in the first place, but we have them here to make sure that + // we can't end up describing memory regions that don't make sense. They + // ask that the page size is a multiple of the minimum page size, that the + // page is aligned to the minimum page size, that the page is non-empty and + // that the top address is still representable in a reg_t. + // + // Note: (base + size == 0) part of the assertion is to handle cases like + // { base = 0xffff_ffff_ffff_f000, size: 0x1000 } + return (size % PGSIZE == 0) && + (base % PGSIZE == 0) && + (size > 0) && + ((base + size > base) || (base + size == 0)); +} diff --git a/vendor/riscv/riscv-isa-sim/riscv/cfg.h b/vendor/riscv/riscv-isa-sim/riscv/cfg.h new file mode 100644 index 0000000000..8ead618b7a --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/cfg.h @@ -0,0 +1,109 @@ +// See LICENSE for license details. +#ifndef _RISCV_CFG_H +#define _RISCV_CFG_H + +#include <optional> +#include <vector> +#include "decode.h" +#include <cassert> + +typedef enum { + endianness_little, + endianness_big +} endianness_t; + +template <typename T> +class cfg_arg_t { +public: + cfg_arg_t(T default_val) + : value(default_val), was_set(false) {} + + bool overridden() const { return was_set; } + + T operator()() const { return value; } + + T operator=(const T v) { + value = v; + was_set = true; + return value; + } + +private: + T value; + bool was_set; +}; + +// Configuration that describes a memory region +class mem_cfg_t +{ +public: + static bool check_if_supported(reg_t base, reg_t size); + + mem_cfg_t(reg_t base, reg_t size); + + reg_t get_base() const { + return base; + } + + reg_t get_size() const { + return size; + } + + reg_t get_inclusive_end() const { + return base + size - 1; + } + +private: + reg_t base; + reg_t size; +}; + +class cfg_t +{ +public: + cfg_t(std::pair<reg_t, reg_t> default_initrd_bounds, + const char *default_bootargs, + const char *default_isa, const char *default_priv, + const char *default_varch, + const bool default_misaligned, + const endianness_t default_endianness, + const reg_t default_pmpregions, + const std::vector<mem_cfg_t> &default_mem_layout, + const std::vector<size_t> default_hartids, + bool default_real_time_clint, + const reg_t default_trigger_count) + : initrd_bounds(default_initrd_bounds), + bootargs(default_bootargs), + isa(default_isa), + priv(default_priv), + varch(default_varch), + misaligned(default_misaligned), + endianness(default_endianness), + pmpregions(default_pmpregions), + mem_layout(default_mem_layout), + hartids(default_hartids), + explicit_hartids(false), + real_time_clint(default_real_time_clint), + trigger_count(default_trigger_count) + {} + + cfg_arg_t<std::pair<reg_t, reg_t>> initrd_bounds; + cfg_arg_t<const char *> bootargs; + cfg_arg_t<const char *> isa; + cfg_arg_t<const char *> priv; + cfg_arg_t<const char *> varch; + bool misaligned; + endianness_t endianness; + reg_t pmpregions; + cfg_arg_t<std::vector<mem_cfg_t>> mem_layout; + std::optional<reg_t> start_pc; + cfg_arg_t<std::vector<size_t>> hartids; + bool explicit_hartids; + cfg_arg_t<bool> real_time_clint; + reg_t trigger_count; + + size_t nprocs() const { return hartids().size(); } + size_t max_hartid() const { return hartids().back(); } +}; + +#endif diff --git a/vendor/riscv/riscv-isa-sim/riscv/clint.cc b/vendor/riscv/riscv-isa-sim/riscv/clint.cc new file mode 100644 index 0000000000..f27f02c342 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/clint.cc @@ -0,0 +1,114 @@ +#include <sys/time.h> +#include "devices.h" +#include "processor.h" +#include "simif.h" + +clint_t::clint_t(simif_t* sim, uint64_t freq_hz, bool real_time) + : sim(sim), freq_hz(freq_hz), real_time(real_time), mtime(0) +{ + struct timeval base; + + gettimeofday(&base, NULL); + + real_time_ref_secs = base.tv_sec; + real_time_ref_usecs = base.tv_usec; + increment(0); +} + +/* 0000 msip hart 0 + * 0004 msip hart 1 + * 4000 mtimecmp hart 0 lo + * 4004 mtimecmp hart 0 hi + * 4008 mtimecmp hart 1 lo + * 400c mtimecmp hart 1 hi + * bff8 mtime lo + * bffc mtime hi + */ + +#define MSIP_BASE 0x0 +#define MTIMECMP_BASE 0x4000 +#define MTIME_BASE 0xbff8 + +bool clint_t::load(reg_t addr, size_t len, uint8_t* bytes) +{ + if (len > 8) + return false; + + increment(0); + + if (addr >= MSIP_BASE && addr < MTIMECMP_BASE) { + if (len == 8) { + // Implement double-word loads as a pair of word loads + return load(addr, 4, bytes) && load(addr + 4, 4, bytes + 4); + } + + const auto hart_id = (addr - MSIP_BASE) / sizeof(msip_t); + const msip_t res = sim->get_harts().count(hart_id) && (sim->get_harts().at(hart_id)->state.mip->read() & MIP_MSIP); + read_little_endian_reg(res, addr, len, bytes); + return true; + } else if (addr >= MTIMECMP_BASE && addr < MTIME_BASE) { + const auto hart_id = (addr - MTIMECMP_BASE) / sizeof(mtimecmp_t); + const mtime_t res = sim->get_harts().count(hart_id) ? mtimecmp[hart_id] : 0; + read_little_endian_reg(res, addr, len, bytes); + } else if (addr >= MTIME_BASE && addr < MTIME_BASE + sizeof(mtime_t)) { + read_little_endian_reg(mtime, addr, len, bytes); + } else if (addr + len <= CLINT_SIZE) { + memset(bytes, 0, len); + } else { + return false; + } + return true; +} + +bool clint_t::store(reg_t addr, size_t len, const uint8_t* bytes) +{ + if (len > 8) + return false; + + if (addr >= MSIP_BASE && addr < MTIMECMP_BASE) { + if (len == 8) { + // Implement double-word stores as a pair of word stores + return store(addr, 4, bytes) && store(addr + 4, 4, bytes + 4); + } + + if (addr % sizeof(msip_t) == 0) { // ignore in-between bytes + msip_t msip = 0; + write_little_endian_reg(&msip, addr, len, bytes); + + const auto hart_id = (addr - MSIP_BASE) / sizeof(msip_t); + if (sim->get_harts().count(hart_id)) + sim->get_harts().at(hart_id)->state.mip->backdoor_write_with_mask(MIP_MSIP, msip & 1 ? MIP_MSIP : 0); + } + } else if (addr >= MTIMECMP_BASE && addr < MTIME_BASE) { + const auto hart_id = (addr - MTIMECMP_BASE) / sizeof(mtimecmp_t); + if (sim->get_harts().count(hart_id)) + write_little_endian_reg(&mtimecmp[hart_id], addr, len, bytes); + } else if (addr >= MTIME_BASE && addr < MTIME_BASE + sizeof(mtime_t)) { + write_little_endian_reg(&mtime, addr, len, bytes); + } else if (addr + len <= CLINT_SIZE) { + // Do nothing + } else { + return false; + } + increment(0); + return true; +} + +void clint_t::increment(reg_t inc) +{ + if (real_time) { + struct timeval now; + uint64_t diff_usecs; + + gettimeofday(&now, NULL); + diff_usecs = ((now.tv_sec - real_time_ref_secs) * 1000000) + (now.tv_usec - real_time_ref_usecs); + mtime = diff_usecs * freq_hz / 1000000; + } else { + mtime += inc; + } + + for (const auto& [hart_id, hart] : sim->get_harts()) { + hart->state.time->sync(mtime); + hart->state.mip->backdoor_write_with_mask(MIP_MTIP, mtime >= mtimecmp[hart_id] ? MIP_MTIP : 0); + } +} diff --git a/vendor/riscv/riscv-isa-sim/riscv/common.h b/vendor/riscv/riscv-isa-sim/riscv/common.h new file mode 100644 index 0000000000..a354ced0cc --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/common.h @@ -0,0 +1,22 @@ +// See LICENSE for license details. + +#ifndef _RISCV_COMMON_H +#define _RISCV_COMMON_H + +#ifdef __GNUC__ +# define likely(x) __builtin_expect(x, 1) +# define unlikely(x) __builtin_expect(x, 0) +# define NOINLINE __attribute__ ((noinline)) +# define NORETURN __attribute__ ((noreturn)) +# define ALWAYS_INLINE __attribute__ ((always_inline)) +# define UNUSED __attribute__ ((unused)) +#else +# define likely(x) (x) +# define unlikely(x) (x) +# define NOINLINE +# define NORETURN +# define ALWAYS_INLINE +# define UNUSED +#endif + +#endif diff --git a/vendor/riscv/riscv-isa-sim/riscv/csrs.cc b/vendor/riscv/riscv-isa-sim/riscv/csrs.cc new file mode 100644 index 0000000000..2e01983b64 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/csrs.cc @@ -0,0 +1,1566 @@ +// See LICENSE for license details. + +// For std::any_of +#include <algorithm> + +#include "csrs.h" +// For processor_t: +#include "processor.h" +#include "mmu.h" +// For get_field(): +#include "decode_macros.h" +// For trap_virtual_instruction and trap_illegal_instruction: +#include "trap.h" +// For require(): +#include "insn_macros.h" + +// STATE macro used by require_privilege() macro: +#undef STATE +#define STATE (*state) + +// implement class csr_t +csr_t::csr_t(processor_t* const proc, const reg_t addr): + proc(proc), + state(proc->get_state()), + address(addr), + csr_priv(get_field(addr, 0x300)), + csr_read_only(get_field(addr, 0xC00) == 3) { +} + +void csr_t::verify_permissions(insn_t insn, bool write) const { + // Check permissions. Raise virtual-instruction exception if V=1, + // privileges are insufficient, and the CSR belongs to supervisor or + // hypervisor. Raise illegal-instruction exception otherwise. + unsigned priv = state->prv == PRV_S && !state->v ? PRV_HS : state->prv; + + if ((csr_priv == PRV_S && !proc->extension_enabled('S')) || + (csr_priv == PRV_HS && !proc->extension_enabled('H'))) + throw trap_illegal_instruction(insn.bits()); + + if (write && csr_read_only) + throw trap_illegal_instruction(insn.bits()); + if (priv < csr_priv) { + if (state->v && csr_priv <= PRV_HS) + throw trap_virtual_instruction(insn.bits()); + throw trap_illegal_instruction(insn.bits()); + } +} + +csr_t::~csr_t() { +} + +void csr_t::write(const reg_t val) noexcept { + const bool success = unlogged_write(val); + if (success) { + log_write(); + } +} + +void csr_t::log_write() const noexcept { + log_special_write(address, written_value()); +} + +void csr_t::log_special_write(const reg_t UNUSED address, const reg_t UNUSED val) const noexcept { + if (proc->get_log_commits_enabled()) + proc->get_state()->log_reg_write[((address) << 4) | 4] = {val, 0}; +} + +reg_t csr_t::written_value() const noexcept { + return read(); +} + +// implement class basic_csr_t +basic_csr_t::basic_csr_t(processor_t* const proc, const reg_t addr, const reg_t init): + csr_t(proc, addr), + val(init) { +} + +bool basic_csr_t::unlogged_write(const reg_t val) noexcept { + this->val = val; + return true; +} + +// implement class pmpaddr_csr_t +pmpaddr_csr_t::pmpaddr_csr_t(processor_t* const proc, const reg_t addr): + csr_t(proc, addr), + val(0), + cfg(0), + pmpidx(address - CSR_PMPADDR0) { +} + +void pmpaddr_csr_t::verify_permissions(insn_t insn, bool write) const { + csr_t::verify_permissions(insn, write); + // If n_pmp is zero, that means pmp is not implemented hence raise + // trap if it tries to access the csr. I would prefer to implement + // this by not instantiating any pmpaddr_csr_t for these regs, but + // n_pmp can change after reset() is run. + if (proc->n_pmp == 0) + throw trap_illegal_instruction(insn.bits()); +} + +reg_t pmpaddr_csr_t::read() const noexcept { + if ((cfg & PMP_A) >= PMP_NAPOT) + return val | (~proc->pmp_tor_mask() >> 1); + return val & proc->pmp_tor_mask(); +} + +bool pmpaddr_csr_t::unlogged_write(const reg_t val) noexcept { + // If no PMPs are configured, disallow access to all. Otherwise, + // allow access to all, but unimplemented ones are hardwired to + // zero. Note that n_pmp can change after reset(); otherwise I would + // implement this in state_t::reset() by instantiating the correct + // number of pmpaddr_csr_t. + if (proc->n_pmp == 0) + return false; + + const bool lock_bypass = state->mseccfg->get_rlb(); + const bool locked = !lock_bypass && (cfg & PMP_L); + + if (pmpidx < proc->n_pmp && !locked && !next_locked_and_tor()) { + this->val = val & ((reg_t(1) << (MAX_PADDR_BITS - PMP_SHIFT)) - 1); + } + else + return false; + proc->get_mmu()->flush_tlb(); + return true; +} + +bool pmpaddr_csr_t::next_locked_and_tor() const noexcept { + if (pmpidx+1 >= state->max_pmp) return false; // this is the last entry + const bool lock_bypass = state->mseccfg->get_rlb(); + const bool next_locked = !lock_bypass && (state->pmpaddr[pmpidx+1]->cfg & PMP_L); + const bool next_tor = (state->pmpaddr[pmpidx+1]->cfg & PMP_A) == PMP_TOR; + return next_locked && next_tor; +} + +reg_t pmpaddr_csr_t::tor_paddr() const noexcept { + return (val & proc->pmp_tor_mask()) << PMP_SHIFT; +} + +reg_t pmpaddr_csr_t::tor_base_paddr() const noexcept { + if (pmpidx == 0) return 0; // entry 0 always uses 0 as base + return state->pmpaddr[pmpidx-1]->tor_paddr(); +} + +reg_t pmpaddr_csr_t::napot_mask() const noexcept { + bool is_na4 = (cfg & PMP_A) == PMP_NA4; + reg_t mask = (val << 1) | (!is_na4) | ~proc->pmp_tor_mask(); + return ~(mask & ~(mask + 1)) << PMP_SHIFT; +} + +bool pmpaddr_csr_t::match4(reg_t addr) const noexcept { + if ((cfg & PMP_A) == 0) return false; + bool is_tor = (cfg & PMP_A) == PMP_TOR; + if (is_tor) return tor_base_paddr() <= addr && addr < tor_paddr(); + // NAPOT or NA4: + return ((addr ^ tor_paddr()) & napot_mask()) == 0; +} + +bool pmpaddr_csr_t::subset_match(reg_t addr, reg_t len) const noexcept { + if ((addr | len) & (len - 1)) + abort(); + reg_t base = tor_base_paddr(); + reg_t tor = tor_paddr(); + + if ((cfg & PMP_A) == 0) return false; + + bool is_tor = (cfg & PMP_A) == PMP_TOR; + bool begins_after_lower = addr >= base; + bool begins_after_upper = addr >= tor; + bool ends_before_lower = (addr & -len) < (base & -len); + bool ends_before_upper = (addr & -len) < (tor & -len); + bool tor_homogeneous = ends_before_lower || begins_after_upper || + (begins_after_lower && ends_before_upper); + + bool mask_homogeneous = ~(napot_mask() << 1) & len; + bool napot_homogeneous = mask_homogeneous || ((addr ^ tor) / len) != 0; + + return !(is_tor ? tor_homogeneous : napot_homogeneous); +} + +bool pmpaddr_csr_t::access_ok(access_type type, reg_t mode) const noexcept { + const bool cfgx = cfg & PMP_X; + const bool cfgw = cfg & PMP_W; + const bool cfgr = cfg & PMP_R; + const bool cfgl = cfg & PMP_L; + + const bool prvm = mode == PRV_M; + + const bool typer = type == LOAD; + const bool typex = type == FETCH; + const bool typew = type == STORE; + const bool normal_rwx = (typer && cfgr) || (typew && cfgw) || (typex && cfgx); + const bool mseccfg_mml = state->mseccfg->get_mml(); + + if (mseccfg_mml) { + if (cfgx && cfgw && cfgr && cfgl) { + // Locked Shared data region: Read only on both M and S/U mode. + return typer; + } else { + const bool mml_shared_region = !cfgr && cfgw; + const bool mml_chk_normal = (prvm == cfgl) && normal_rwx; + const bool mml_chk_shared = + (!cfgl && cfgx && (typer || typew)) || + (!cfgl && !cfgx && (typer || (typew && prvm))) || + (cfgl && typex) || + (cfgl && typer && cfgx && prvm); + return mml_shared_region ? mml_chk_shared : mml_chk_normal; + } + } else { + const bool m_bypass = (prvm && !cfgl); + return m_bypass || normal_rwx; + } +} + +// implement class pmpcfg_csr_t +pmpcfg_csr_t::pmpcfg_csr_t(processor_t* const proc, const reg_t addr): + csr_t(proc, addr) { +} + +void pmpcfg_csr_t::verify_permissions(insn_t insn, bool write) const { + csr_t::verify_permissions(insn, write); + // If n_pmp is zero, that means pmp is not implemented hence raise + // trap if it tries to access the csr. I would prefer to implement + // this by not instantiating any pmpcfg_csr_t for these regs, but + // n_pmp can change after reset() is run. + if (proc->n_pmp == 0) + throw trap_illegal_instruction(insn.bits()); +} + +reg_t pmpcfg_csr_t::read() const noexcept { + reg_t cfg_res = 0; + for (size_t i0 = (address - CSR_PMPCFG0) * 4, i = i0; i < i0 + proc->get_xlen() / 8 && i < state->max_pmp; i++) + cfg_res |= reg_t(state->pmpaddr[i]->cfg) << (8 * (i - i0)); + return cfg_res; +} + +bool pmpcfg_csr_t::unlogged_write(const reg_t val) noexcept { + if (proc->n_pmp == 0) + return false; + + bool write_success = false; + const bool rlb = state->mseccfg->get_rlb(); + const bool mml = state->mseccfg->get_mml(); + for (size_t i0 = (address - CSR_PMPCFG0) * 4, i = i0; i < i0 + proc->get_xlen() / 8; i++) { + if (i < proc->n_pmp) { + const bool locked = (state->pmpaddr[i]->cfg & PMP_L); + if (rlb || !locked) { + uint8_t cfg = (val >> (8 * (i - i0))) & (PMP_R | PMP_W | PMP_X | PMP_A | PMP_L); + // Drop R=0 W=1 when MML = 0 + // Remove the restriction when MML = 1 + if (!mml) { + cfg &= ~PMP_W | ((cfg & PMP_R) ? PMP_W : 0); + } + // Disallow A=NA4 when granularity > 4 + if (proc->lg_pmp_granularity != PMP_SHIFT && (cfg & PMP_A) == PMP_NA4) + cfg |= PMP_NAPOT; + /* + * Adding a rule with executable privileges that either is M-mode-only or a locked Shared-Region + * is not possible and such pmpcfg writes are ignored, leaving pmpcfg unchanged. + * This restriction can be temporarily lifted e.g. during the boot process, by setting mseccfg.RLB. + */ + const bool cfgx = cfg & PMP_X; + const bool cfgw = cfg & PMP_W; + const bool cfgr = cfg & PMP_R; + if (rlb || !(mml && ((cfg & PMP_L) // M-mode-only or a locked Shared-Region + && !(cfgx && cfgw && cfgr) // RWX = 111 is allowed + && (cfgx || (cfgw && !cfgr)) // X=1 or RW=01 is not allowed + ))) { + state->pmpaddr[i]->cfg = cfg; + } + } + write_success = true; + } + } + proc->get_mmu()->flush_tlb(); + return write_success; +} + +// implement class mseccfg_csr_t +mseccfg_csr_t::mseccfg_csr_t(processor_t* const proc, const reg_t addr): + basic_csr_t(proc, addr, 0) { +} + +void mseccfg_csr_t::verify_permissions(insn_t insn, bool write) const { + basic_csr_t::verify_permissions(insn, write); + if (!proc->extension_enabled(EXT_SMEPMP)) + throw trap_illegal_instruction(insn.bits()); +} + +bool mseccfg_csr_t::get_mml() const noexcept { + return (read() & MSECCFG_MML); +} + +bool mseccfg_csr_t::get_mmwp() const noexcept { + return (read() & MSECCFG_MMWP); +} + +bool mseccfg_csr_t::get_rlb() const noexcept { + return (read() & MSECCFG_RLB); +} + +bool mseccfg_csr_t::unlogged_write(const reg_t val) noexcept { + if (proc->n_pmp == 0) + return false; + + // pmpcfg.L is 1 in any rule or entry (including disabled entries) + const bool pmplock_recorded = std::any_of(state->pmpaddr, state->pmpaddr + proc->n_pmp, + [](const pmpaddr_csr_t_p & c) { return c->is_locked(); } ); + reg_t new_val = read(); + + // When RLB is 0 and pmplock_recorded, RLB is locked to 0. + // Otherwise set the RLB bit according val + if (!(pmplock_recorded && (read() & MSECCFG_RLB) == 0)) { + new_val &= ~MSECCFG_RLB; + new_val |= (val & MSECCFG_RLB); + } + + new_val |= (val & MSECCFG_MMWP); //MMWP is sticky + new_val |= (val & MSECCFG_MML); //MML is sticky + + proc->get_mmu()->flush_tlb(); + + return basic_csr_t::unlogged_write(new_val); +} + +// implement class virtualized_csr_t +virtualized_csr_t::virtualized_csr_t(processor_t* const proc, csr_t_p orig, csr_t_p virt): + csr_t(proc, orig->address), + orig_csr(orig), + virt_csr(virt) { +} + +reg_t virtualized_csr_t::read() const noexcept { + return readvirt(state->v); +} + +reg_t virtualized_csr_t::readvirt(bool virt) const noexcept { + return virt ? virt_csr->read() : orig_csr->read(); +} + +bool virtualized_csr_t::unlogged_write(const reg_t val) noexcept { + if (state->v) + virt_csr->write(val); + else + orig_csr->write(val); + return false; // virt_csr or orig_csr has already logged +} + +// implement class epc_csr_t +epc_csr_t::epc_csr_t(processor_t* const proc, const reg_t addr): + csr_t(proc, addr), + val(0) { +} + +reg_t epc_csr_t::read() const noexcept { + return val & proc->pc_alignment_mask(); +} + +bool epc_csr_t::unlogged_write(const reg_t val) noexcept { + this->val = val & ~(reg_t)1; + return true; +} + +// implement class tvec_csr_t +tvec_csr_t::tvec_csr_t(processor_t* const proc, const reg_t addr): + csr_t(proc, addr), + val(0) { +} + +reg_t tvec_csr_t::read() const noexcept { + return val; +} + +bool tvec_csr_t::unlogged_write(const reg_t val) noexcept { + this->val = val & ~(reg_t)2; + return true; +} + +// implement class cause_csr_t +cause_csr_t::cause_csr_t(processor_t* const proc, const reg_t addr): + basic_csr_t(proc, addr, 0) { +} + +reg_t cause_csr_t::read() const noexcept { + reg_t val = basic_csr_t::read(); + // When reading, the interrupt bit needs to adjust to xlen. Spike does + // not generally support dynamic xlen, but this code was (partly) + // there since at least 2015 (ea58df8 and c4350ef). + if (proc->get_isa().get_max_xlen() > proc->get_xlen()) // Move interrupt bit to top of xlen + return val | ((val >> (proc->get_isa().get_max_xlen()-1)) << (proc->get_xlen()-1)); + return val; +} + +// implement class base_status_csr_t +base_status_csr_t::base_status_csr_t(processor_t* const proc, const reg_t addr): + csr_t(proc, addr), + has_page(proc->extension_enabled_const('S') && proc->supports_impl(IMPL_MMU)), + sstatus_write_mask(compute_sstatus_write_mask()), + sstatus_read_mask(sstatus_write_mask | SSTATUS_UBE | SSTATUS_UXL + | (proc->get_const_xlen() == 32 ? SSTATUS32_SD : SSTATUS64_SD)) { +} + +reg_t base_status_csr_t::compute_sstatus_write_mask() const noexcept { + // If a configuration has FS bits, they will always be accessible no + // matter the state of misa. + const bool has_fs = (proc->extension_enabled('S') || proc->extension_enabled('F') + || proc->extension_enabled('V')) && !proc->extension_enabled(EXT_ZFINX); + const bool has_vs = proc->extension_enabled('V'); + return 0 + | (proc->extension_enabled('S') ? (SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP) : 0) + | (has_page ? (SSTATUS_SUM | SSTATUS_MXR) : 0) + | (has_fs ? SSTATUS_FS : 0) + | (proc->any_custom_extensions() ? SSTATUS_XS : 0) + | (has_vs ? SSTATUS_VS : 0) + ; +} + +reg_t base_status_csr_t::adjust_sd(const reg_t val) const noexcept { + // This uses get_const_xlen() instead of get_xlen() not only because + // the variable is static, so it's only called once, but also + // because the SD bit moves when XLEN changes, which means we would + // need to call adjust_sd() on every read, instead of on every + // write. + static const reg_t sd_bit = proc->get_const_xlen() == 64 ? SSTATUS64_SD : SSTATUS32_SD; + if (((val & SSTATUS_FS) == SSTATUS_FS) || + ((val & SSTATUS_VS) == SSTATUS_VS) || + ((val & SSTATUS_XS) == SSTATUS_XS)) { + return val | sd_bit; + } + return val & ~sd_bit; +} + +void base_status_csr_t::maybe_flush_tlb(const reg_t newval) noexcept { + if ((newval ^ read()) & + (MSTATUS_MPP | MSTATUS_MPRV + | (has_page ? (MSTATUS_MXR | MSTATUS_SUM) : 0) + )) + proc->get_mmu()->flush_tlb(); +} + +namespace { + int xlen_to_uxl(int xlen) { + if (xlen == 32) + return 1; + if (xlen == 64) + return 2; + abort(); + } +} + +// implement class vsstatus_csr_t +vsstatus_csr_t::vsstatus_csr_t(processor_t* const proc, const reg_t addr): + base_status_csr_t(proc, addr), + val(proc->get_state()->mstatus->read() & sstatus_read_mask) { +} + +bool vsstatus_csr_t::unlogged_write(const reg_t val) noexcept { + const reg_t newval = (this->val & ~sstatus_write_mask) | (val & sstatus_write_mask); + if (state->v) maybe_flush_tlb(newval); + this->val = adjust_sd(newval); + return true; +} + +// implement class sstatus_proxy_csr_t +sstatus_proxy_csr_t::sstatus_proxy_csr_t(processor_t* const proc, const reg_t addr, mstatus_csr_t_p mstatus): + base_status_csr_t(proc, addr), + mstatus(mstatus) { +} + +bool sstatus_proxy_csr_t::unlogged_write(const reg_t val) noexcept { + const reg_t new_mstatus = (mstatus->read() & ~sstatus_write_mask) | (val & sstatus_write_mask); + + // On RV32 this will only log the low 32 bits, so make sure we're + // not modifying anything in the upper 32 bits. + assert((sstatus_write_mask & 0xffffffffU) == sstatus_write_mask); + + mstatus->write(new_mstatus); + return false; // avoid double logging: already logged by mstatus->write() +} + +// implement class mstatus_csr_t +mstatus_csr_t::mstatus_csr_t(processor_t* const proc, const reg_t addr): + base_status_csr_t(proc, addr), + val(compute_mstatus_initial_value()) { +} + +bool mstatus_csr_t::unlogged_write(const reg_t val) noexcept { + const bool has_mpv = proc->extension_enabled('H'); + const bool has_gva = has_mpv; + + const reg_t mask = sstatus_write_mask + | MSTATUS_MIE | MSTATUS_MPIE + | (proc->extension_enabled('U') ? MSTATUS_MPRV : 0) + | MSTATUS_MPP | MSTATUS_TW + | (proc->extension_enabled('S') ? MSTATUS_TSR : 0) + | (has_page ? MSTATUS_TVM : 0) + | (has_gva ? MSTATUS_GVA : 0) + | (has_mpv ? MSTATUS_MPV : 0); + + const reg_t requested_mpp = proc->legalize_privilege(get_field(val, MSTATUS_MPP)); + const reg_t adjusted_val = set_field(val, MSTATUS_MPP, requested_mpp); + const reg_t new_mstatus = (read() & ~mask) | (adjusted_val & mask); + maybe_flush_tlb(new_mstatus); + this->val = adjust_sd(new_mstatus); + return true; +} + +reg_t mstatus_csr_t::compute_mstatus_initial_value() const noexcept { + const reg_t big_endian_bits = (proc->extension_enabled_const('U') ? MSTATUS_UBE : 0) + | (proc->extension_enabled_const('S') ? MSTATUS_SBE : 0) + | MSTATUS_MBE; + return 0 + | (proc->extension_enabled_const('U') && (proc->get_const_xlen() != 32) ? set_field((reg_t)0, MSTATUS_UXL, xlen_to_uxl(proc->get_const_xlen())) : 0) + | (proc->extension_enabled_const('S') && (proc->get_const_xlen() != 32) ? set_field((reg_t)0, MSTATUS_SXL, xlen_to_uxl(proc->get_const_xlen())) : 0) + | (proc->get_mmu()->is_target_big_endian() ? big_endian_bits : 0) + | 0; // initial value for mstatus +} + +// implement class mnstatus_csr_t +mnstatus_csr_t::mnstatus_csr_t(processor_t* const proc, const reg_t addr): + basic_csr_t(proc, addr, 0) { +} + +bool mnstatus_csr_t::unlogged_write(const reg_t val) noexcept { + // NMIE can be set but not cleared + const reg_t mask = (~read() & MNSTATUS_NMIE) + | (proc->extension_enabled('H') ? MNSTATUS_MNPV : 0) + | MNSTATUS_MNPP; + + const reg_t requested_mnpp = proc->legalize_privilege(get_field(val, MNSTATUS_MNPP)); + const reg_t adjusted_val = set_field(val, MNSTATUS_MNPP, requested_mnpp); + const reg_t new_mnstatus = (read() & ~mask) | (adjusted_val & mask); + + return basic_csr_t::unlogged_write(new_mnstatus); +} + +// implement class rv32_low_csr_t +rv32_low_csr_t::rv32_low_csr_t(processor_t* const proc, const reg_t addr, csr_t_p orig): + csr_t(proc, addr), + orig(orig) { +} + +reg_t rv32_low_csr_t::read() const noexcept { + return orig->read() & 0xffffffffU; +} + +void rv32_low_csr_t::verify_permissions(insn_t insn, bool write) const { + orig->verify_permissions(insn, write); +} + +bool rv32_low_csr_t::unlogged_write(const reg_t val) noexcept { + return orig->unlogged_write((orig->written_value() >> 32 << 32) | (val & 0xffffffffU)); +} + +reg_t rv32_low_csr_t::written_value() const noexcept { + return orig->written_value() & 0xffffffffU; +} + +// implement class rv32_high_csr_t +rv32_high_csr_t::rv32_high_csr_t(processor_t* const proc, const reg_t addr, csr_t_p orig): + csr_t(proc, addr), + orig(orig) { +} + +reg_t rv32_high_csr_t::read() const noexcept { + return (orig->read() >> 32) & 0xffffffffU; +} + +void rv32_high_csr_t::verify_permissions(insn_t insn, bool write) const { + orig->verify_permissions(insn, write); +} + +bool rv32_high_csr_t::unlogged_write(const reg_t val) noexcept { + return orig->unlogged_write((orig->written_value() << 32 >> 32) | ((val & 0xffffffffU) << 32)); +} + +reg_t rv32_high_csr_t::written_value() const noexcept { + return (orig->written_value() >> 32) & 0xffffffffU; +} + +// implement class sstatus_csr_t +sstatus_csr_t::sstatus_csr_t(processor_t* const proc, sstatus_proxy_csr_t_p orig, vsstatus_csr_t_p virt): + virtualized_csr_t(proc, orig, virt), + orig_sstatus(orig), + virt_sstatus(virt) { +} + +void sstatus_csr_t::dirty(const reg_t dirties) { + // As an optimization, return early if already dirty. + if ((orig_sstatus->read() & dirties) == dirties) { + if (likely(!state->v || (virt_sstatus->read() & dirties) == dirties)) + return; + } + + // Catch problems like #823 where P-extension instructions were not + // checking for mstatus.VS!=Off: + if (!enabled(dirties)) abort(); + + orig_sstatus->write(orig_sstatus->read() | dirties); + if (state->v) { + virt_sstatus->write(virt_sstatus->read() | dirties); + } +} + +bool sstatus_csr_t::enabled(const reg_t which) { + if ((orig_sstatus->read() & which) != 0) { + if (!state->v || (virt_sstatus->read() & which) != 0) + return true; + } + + // If the field doesn't exist, it is always enabled. See #823. + if (!orig_sstatus->field_exists(which)) + return true; + + return false; +} + +// implement class misa_csr_t +misa_csr_t::misa_csr_t(processor_t* const proc, const reg_t addr, const reg_t max_isa): + basic_csr_t(proc, addr, max_isa), + max_isa(max_isa), + write_mask(max_isa & (0 // allow MAFDQCHV bits in MISA to be modified + | (1L << ('M' - 'A')) + | (1L << ('A' - 'A')) + | (1L << ('F' - 'A')) + | (1L << ('D' - 'A')) + | (1L << ('Q' - 'A')) + | (1L << ('C' - 'A')) + | (1L << ('H' - 'A')) + | (1L << ('V' - 'A')) + ) + ) { +} + +reg_t misa_csr_t::dependency(const reg_t val, const char feature, const char depends_on) const noexcept { + return (val & (1L << (depends_on - 'A'))) ? val : (val & ~(1L << (feature - 'A'))); +} + +bool misa_csr_t::unlogged_write(const reg_t val) noexcept { + const reg_t old_misa = read(); + + // the write is ignored if increasing IALIGN would misalign the PC + if (!(val & (1L << ('C' - 'A'))) && (old_misa & (1L << ('C' - 'A'))) && (state->pc & 2)) + return false; + + reg_t adjusted_val = val; + adjusted_val = dependency(adjusted_val, 'D', 'F'); + adjusted_val = dependency(adjusted_val, 'Q', 'D'); + adjusted_val = dependency(adjusted_val, 'V', 'D'); + + const bool prev_h = old_misa & (1L << ('H' - 'A')); + const reg_t new_misa = (adjusted_val & write_mask) | (old_misa & ~write_mask); + const bool new_h = new_misa & (1L << ('H' - 'A')); + + proc->set_extension_enable(EXT_ZCA, (new_misa & (1L << ('C' - 'A'))) || !proc->get_isa().extension_enabled('C')); + proc->set_extension_enable(EXT_ZCF, (new_misa & (1L << ('F' - 'A'))) && proc->extension_enabled(EXT_ZCA)); + proc->set_extension_enable(EXT_ZCD, (new_misa & (1L << ('D' - 'A'))) && proc->extension_enabled(EXT_ZCA)); + proc->set_extension_enable(EXT_ZCB, proc->extension_enabled(EXT_ZCA)); + proc->set_extension_enable(EXT_ZCMP, proc->extension_enabled(EXT_ZCA)); + proc->set_extension_enable(EXT_ZCMT, proc->extension_enabled(EXT_ZCA)); + proc->set_extension_enable(EXT_ZFH, new_misa & (1L << ('F' - 'A'))); + proc->set_extension_enable(EXT_ZFHMIN, new_misa & (1L << ('F' - 'A'))); + proc->set_extension_enable(EXT_ZVFH, (new_misa & (1L << ('V' - 'A'))) && proc->extension_enabled(EXT_ZFHMIN)); + proc->set_extension_enable(EXT_ZVFHMIN, new_misa & (1L << ('V' - 'A'))); + + // update the hypervisor-only bits in MEDELEG and other CSRs + if (!new_h && prev_h) { + reg_t hypervisor_exceptions = 0 + | (1 << CAUSE_VIRTUAL_SUPERVISOR_ECALL) + | (1 << CAUSE_FETCH_GUEST_PAGE_FAULT) + | (1 << CAUSE_LOAD_GUEST_PAGE_FAULT) + | (1 << CAUSE_VIRTUAL_INSTRUCTION) + | (1 << CAUSE_STORE_GUEST_PAGE_FAULT) + ; + + state->medeleg->write(state->medeleg->read() & ~hypervisor_exceptions); + if (state->mnstatus) state->mnstatus->write(state->mnstatus->read() & ~MNSTATUS_MNPV); + const reg_t new_mstatus = state->mstatus->read() & ~(MSTATUS_GVA | MSTATUS_MPV); + state->mstatus->write(new_mstatus); + if (state->mstatush) state->mstatush->write(new_mstatus >> 32); // log mstatush change + state->mie->write_with_mask(MIP_HS_MASK, 0); // also takes care of hie, sie + state->mip->write_with_mask(MIP_HS_MASK, 0); // also takes care of hip, sip, hvip + state->hstatus->write(0); + for (reg_t i = 3; i < N_HPMCOUNTERS + 3; ++i) { + const reg_t new_mevent = state->mevent[i - 3]->read() & ~(MHPMEVENT_VUINH | MHPMEVENT_VSINH); + state->mevent[i - 3]->write(new_mevent); + } + } + + return basic_csr_t::unlogged_write(new_misa); +} + +bool misa_csr_t::extension_enabled_const(unsigned char ext) const noexcept { + assert(!(1 & (write_mask >> (ext - 'A')))); + return extension_enabled(ext); +} + +// implement class mip_or_mie_csr_t +mip_or_mie_csr_t::mip_or_mie_csr_t(processor_t* const proc, const reg_t addr): + csr_t(proc, addr), + val(0) { +} + +reg_t mip_or_mie_csr_t::read() const noexcept { + return val; +} + +void mip_or_mie_csr_t::write_with_mask(const reg_t mask, const reg_t val) noexcept { + this->val = (this->val & ~mask) | (val & mask); + log_write(); +} + +bool mip_or_mie_csr_t::unlogged_write(const reg_t val) noexcept { + write_with_mask(write_mask(), val); + return false; // avoid double logging: already logged by write_with_mask() +} + +mip_csr_t::mip_csr_t(processor_t* const proc, const reg_t addr): + mip_or_mie_csr_t(proc, addr) { +} + +void mip_csr_t::backdoor_write_with_mask(const reg_t mask, const reg_t val) noexcept { + this->val = (this->val & ~mask) | (val & mask); +} + +reg_t mip_csr_t::write_mask() const noexcept { + // MIP_STIP is writable unless SSTC exists and STCE is set in MENVCFG + const reg_t supervisor_ints = proc->extension_enabled('S') ? MIP_SSIP | ((state->menvcfg->read() & MENVCFG_STCE) ? 0 : MIP_STIP) | MIP_SEIP : 0; + const reg_t lscof_int = proc->extension_enabled(EXT_SSCOFPMF) ? MIP_LCOFIP : 0; + const reg_t vssip_int = proc->extension_enabled('H') ? MIP_VSSIP : 0; + const reg_t hypervisor_ints = proc->extension_enabled('H') ? MIP_HS_MASK : 0; + // We must mask off sgeip, vstip, and vseip. All three of these + // bits are aliases for the same bits in hip. The hip spec says: + // * sgeip is read-only -- write hgeip instead + // * vseip is read-only -- write hvip instead + // * vstip is read-only -- write hvip instead + return (supervisor_ints | hypervisor_ints | lscof_int) & + (MIP_SEIP | MIP_SSIP | MIP_STIP | MIP_LCOFIP | vssip_int); +} + +mie_csr_t::mie_csr_t(processor_t* const proc, const reg_t addr): + mip_or_mie_csr_t(proc, addr) { +} + +reg_t mie_csr_t::write_mask() const noexcept { + const reg_t supervisor_ints = proc->extension_enabled('S') ? MIP_SSIP | MIP_STIP | MIP_SEIP : 0; + const reg_t lscof_int = proc->extension_enabled(EXT_SSCOFPMF) ? MIP_LCOFIP : 0; + const reg_t hypervisor_ints = proc->extension_enabled('H') ? MIP_HS_MASK : 0; + const reg_t coprocessor_ints = (reg_t)proc->any_custom_extensions() << IRQ_COP; + const reg_t delegable_ints = supervisor_ints | coprocessor_ints | lscof_int; + const reg_t all_ints = delegable_ints | hypervisor_ints | MIP_MSIP | MIP_MTIP | MIP_MEIP; + return all_ints; +} + +// implement class generic_int_accessor_t +generic_int_accessor_t::generic_int_accessor_t(state_t* const state, + const reg_t read_mask, + const reg_t ip_write_mask, + const reg_t ie_write_mask, + const mask_mode_t mask_mode, + const int shiftamt): + state(state), + read_mask(read_mask), + ip_write_mask(ip_write_mask), + ie_write_mask(ie_write_mask), + mask_mideleg(mask_mode == MIDELEG), + mask_hideleg(mask_mode == HIDELEG), + shiftamt(shiftamt) { +} + +reg_t generic_int_accessor_t::ip_read() const noexcept { + return (state->mip->read() & deleg_mask() & read_mask) >> shiftamt; +} + +void generic_int_accessor_t::ip_write(const reg_t val) noexcept { + const reg_t mask = deleg_mask() & ip_write_mask; + state->mip->write_with_mask(mask, val << shiftamt); +} + +reg_t generic_int_accessor_t::ie_read() const noexcept { + return (state->mie->read() & deleg_mask() & read_mask) >> shiftamt; +} + +void generic_int_accessor_t::ie_write(const reg_t val) noexcept { + const reg_t mask = deleg_mask() & ie_write_mask; + state->mie->write_with_mask(mask, val << shiftamt); +} + +reg_t generic_int_accessor_t::deleg_mask() const { + const reg_t hideleg_mask = mask_hideleg ? state->hideleg->read() : (reg_t)~0; + const reg_t mideleg_mask = mask_mideleg ? state->mideleg->read() : (reg_t)~0; + return hideleg_mask & mideleg_mask; +} + +// implement class mip_proxy_csr_t +mip_proxy_csr_t::mip_proxy_csr_t(processor_t* const proc, const reg_t addr, generic_int_accessor_t_p accr): + csr_t(proc, addr), + accr(accr) { +} + +reg_t mip_proxy_csr_t::read() const noexcept { + return accr->ip_read(); +} + +bool mip_proxy_csr_t::unlogged_write(const reg_t val) noexcept { + accr->ip_write(val); + return false; // accr has already logged +} + +// implement class mie_proxy_csr_t +mie_proxy_csr_t::mie_proxy_csr_t(processor_t* const proc, const reg_t addr, generic_int_accessor_t_p accr): + csr_t(proc, addr), + accr(accr) { +} + +reg_t mie_proxy_csr_t::read() const noexcept { + return accr->ie_read(); +} + +bool mie_proxy_csr_t::unlogged_write(const reg_t val) noexcept { + accr->ie_write(val); + return false; // accr has already logged +} + +// implement class mideleg_csr_t +mideleg_csr_t::mideleg_csr_t(processor_t* const proc, const reg_t addr): + basic_csr_t(proc, addr, 0) { +} + +reg_t mideleg_csr_t::read() const noexcept { + reg_t val = basic_csr_t::read(); + if (proc->extension_enabled('H')) return val | MIDELEG_FORCED_MASK; + // No need to clear MIDELEG_FORCED_MASK because those bits can never + // get set in val. + return val; +} + +void mideleg_csr_t::verify_permissions(insn_t insn, bool write) const { + basic_csr_t::verify_permissions(insn, write); + if (!proc->extension_enabled('S')) + throw trap_illegal_instruction(insn.bits()); +} + +bool mideleg_csr_t::unlogged_write(const reg_t val) noexcept { + const reg_t supervisor_ints = proc->extension_enabled('S') ? MIP_SSIP | MIP_STIP | MIP_SEIP : 0; + const reg_t lscof_int = proc->extension_enabled(EXT_SSCOFPMF) ? MIP_LCOFIP : 0; + const reg_t coprocessor_ints = (reg_t)proc->any_custom_extensions() << IRQ_COP; + const reg_t delegable_ints = supervisor_ints | coprocessor_ints | lscof_int; + + return basic_csr_t::unlogged_write(val & delegable_ints); +} + +// implement class medeleg_csr_t +medeleg_csr_t::medeleg_csr_t(processor_t* const proc, const reg_t addr): + basic_csr_t(proc, addr, 0), + hypervisor_exceptions(0 + | (1 << CAUSE_VIRTUAL_SUPERVISOR_ECALL) + | (1 << CAUSE_FETCH_GUEST_PAGE_FAULT) + | (1 << CAUSE_LOAD_GUEST_PAGE_FAULT) + | (1 << CAUSE_VIRTUAL_INSTRUCTION) + | (1 << CAUSE_STORE_GUEST_PAGE_FAULT) + ) { +} + +void medeleg_csr_t::verify_permissions(insn_t insn, bool write) const { + basic_csr_t::verify_permissions(insn, write); + if (!proc->extension_enabled('S')) + throw trap_illegal_instruction(insn.bits()); +} + +bool medeleg_csr_t::unlogged_write(const reg_t val) noexcept { + const reg_t mask = 0 + | (1 << CAUSE_MISALIGNED_FETCH) + | (1 << CAUSE_FETCH_ACCESS) + | (1 << CAUSE_ILLEGAL_INSTRUCTION) + | (1 << CAUSE_BREAKPOINT) + | (1 << CAUSE_MISALIGNED_LOAD) + | (1 << CAUSE_LOAD_ACCESS) + | (1 << CAUSE_MISALIGNED_STORE) + | (1 << CAUSE_STORE_ACCESS) + | (1 << CAUSE_USER_ECALL) + | (1 << CAUSE_SUPERVISOR_ECALL) + | (1 << CAUSE_FETCH_PAGE_FAULT) + | (1 << CAUSE_LOAD_PAGE_FAULT) + | (1 << CAUSE_STORE_PAGE_FAULT) + | (proc->extension_enabled('H') ? hypervisor_exceptions : 0) + ; + return basic_csr_t::unlogged_write((read() & ~mask) | (val & mask)); +} + +// implement class masked_csr_t +masked_csr_t::masked_csr_t(processor_t* const proc, const reg_t addr, const reg_t mask, const reg_t init): + basic_csr_t(proc, addr, init), + mask(mask) { +} + +bool masked_csr_t::unlogged_write(const reg_t val) noexcept { + return basic_csr_t::unlogged_write((read() & ~mask) | (val & mask)); +} + +// implement class henvcfg_csr_t +henvcfg_csr_t::henvcfg_csr_t(processor_t* const proc, const reg_t addr, const reg_t mask, const reg_t init, csr_t_p menvcfg): + masked_csr_t(proc, addr, mask, init), + menvcfg(menvcfg) { +} + +// implement class base_atp_csr_t and family +base_atp_csr_t::base_atp_csr_t(processor_t* const proc, const reg_t addr): + basic_csr_t(proc, addr, 0) { +} + +bool base_atp_csr_t::unlogged_write(const reg_t val) noexcept { + const reg_t newval = proc->supports_impl(IMPL_MMU) ? compute_new_satp(val) : 0; + if (newval != read()) + proc->get_mmu()->flush_tlb(); + return basic_csr_t::unlogged_write(newval); +} + +bool base_atp_csr_t::satp_valid(reg_t val) const noexcept { + if (proc->get_xlen() == 32) { + switch (get_field(val, SATP32_MODE)) { + case SATP_MODE_SV32: return proc->supports_impl(IMPL_MMU_SV32); + case SATP_MODE_OFF: return true; + default: return false; + } + } else { + switch (get_field(val, SATP64_MODE)) { + case SATP_MODE_SV39: return proc->supports_impl(IMPL_MMU_SV39); + case SATP_MODE_SV48: return proc->supports_impl(IMPL_MMU_SV48); + case SATP_MODE_SV57: return proc->supports_impl(IMPL_MMU_SV57); + case SATP_MODE_OFF: return true; + default: return false; + } + } +} + +reg_t base_atp_csr_t::compute_new_satp(reg_t val) const noexcept { + reg_t rv64_ppn_mask = (reg_t(1) << (MAX_PADDR_BITS - PGSHIFT)) - 1; + + reg_t mode_mask = proc->get_xlen() == 32 ? SATP32_MODE : SATP64_MODE; + reg_t asid_mask_if_enabled = proc->get_xlen() == 32 ? SATP32_ASID : SATP64_ASID; + reg_t asid_mask = proc->supports_impl(IMPL_MMU_ASID) ? asid_mask_if_enabled : 0; + reg_t ppn_mask = proc->get_xlen() == 32 ? SATP32_PPN : SATP64_PPN & rv64_ppn_mask; + reg_t new_mask = (satp_valid(val) ? mode_mask : 0) | asid_mask | ppn_mask; + reg_t old_mask = satp_valid(val) ? 0 : mode_mask; + + return (new_mask & val) | (old_mask & read()); +} + +satp_csr_t::satp_csr_t(processor_t* const proc, const reg_t addr): + base_atp_csr_t(proc, addr) { +} + +void satp_csr_t::verify_permissions(insn_t insn, bool write) const { + base_atp_csr_t::verify_permissions(insn, write); + if (get_field(state->mstatus->read(), MSTATUS_TVM)) + require(state->prv == PRV_M); +} + +virtualized_satp_csr_t::virtualized_satp_csr_t(processor_t* const proc, satp_csr_t_p orig, csr_t_p virt): + virtualized_csr_t(proc, orig, virt), + orig_satp(orig) { +} + +void virtualized_satp_csr_t::verify_permissions(insn_t insn, bool write) const { + virtualized_csr_t::verify_permissions(insn, write); + + // If satp is accessed from VS mode, it's really accessing vsatp, + // and the hstatus.VTVM bit controls. + if (state->v) { + if (get_field(state->hstatus->read(), HSTATUS_VTVM)) + throw trap_virtual_instruction(insn.bits()); + } + else { + orig_csr->verify_permissions(insn, write); + } +} + +bool virtualized_satp_csr_t::unlogged_write(const reg_t val) noexcept { + // If unsupported Mode field: no change to contents + const reg_t newval = orig_satp->satp_valid(val) ? val : read(); + return virtualized_csr_t::unlogged_write(newval); +} + +// implement class wide_counter_csr_t +wide_counter_csr_t::wide_counter_csr_t(processor_t* const proc, const reg_t addr): + csr_t(proc, addr), + val(0) { +} + +reg_t wide_counter_csr_t::read() const noexcept { + return val; +} + +void wide_counter_csr_t::bump(const reg_t howmuch) noexcept { + val += howmuch; // to keep log reasonable size, don't log every bump +} + +bool wide_counter_csr_t::unlogged_write(const reg_t val) noexcept { + this->val = val; + // The ISA mandates that if an instruction writes instret, the write + // takes precedence over the increment to instret. However, Spike + // unconditionally increments instret after executing an instruction. + // Correct for this artifact by decrementing instret here. + this->val--; + return true; +} + +reg_t wide_counter_csr_t::written_value() const noexcept { + // Re-adjust for upcoming bump() + return this->val + 1; +} + +// implement class time_counter_csr_t +time_counter_csr_t::time_counter_csr_t(processor_t* const proc, const reg_t addr): + csr_t(proc, addr), + shadow_val(0) { +} + +reg_t time_counter_csr_t::read() const noexcept { + // reading the time CSR in VS or VU mode returns the sum of the contents of + // htimedelta and the actual value of time. + if (state->v) + return shadow_val + state->htimedelta->read(); + else + return shadow_val; +} + +void time_counter_csr_t::sync(const reg_t val) noexcept { + shadow_val = val; + if (proc->extension_enabled(EXT_SSTC)) { + const reg_t mip_val = (shadow_val >= state->stimecmp->read() ? MIP_STIP : 0) | + (shadow_val + state->htimedelta->read() >= state->vstimecmp->read() ? MIP_VSTIP : 0); + state->mip->backdoor_write_with_mask(MIP_STIP | MIP_VSTIP, mip_val); + } +} + +proxy_csr_t::proxy_csr_t(processor_t* const proc, const reg_t addr, csr_t_p delegate): + csr_t(proc, addr), + delegate(delegate) { +} + +reg_t proxy_csr_t::read() const noexcept { + return delegate->read(); +} + +bool proxy_csr_t::unlogged_write(const reg_t val) noexcept { + delegate->write(val); // log only under the original (delegate's) name + return false; +} + +const_csr_t::const_csr_t(processor_t* const proc, const reg_t addr, reg_t val): + csr_t(proc, addr), + val(val) { +} + +reg_t const_csr_t::read() const noexcept { + return val; +} + +bool const_csr_t::unlogged_write(const reg_t UNUSED val) noexcept { + return false; +} + +counter_proxy_csr_t::counter_proxy_csr_t(processor_t* const proc, const reg_t addr, csr_t_p delegate): + proxy_csr_t(proc, addr, delegate) { +} + +bool counter_proxy_csr_t::myenable(csr_t_p counteren) const noexcept { + return 1 & (counteren->read() >> (address & 31)); +} + +void counter_proxy_csr_t::verify_permissions(insn_t insn, bool write) const { + proxy_csr_t::verify_permissions(insn, write); + + const bool mctr_ok = (state->prv < PRV_M) ? myenable(state->mcounteren) : true; + const bool hctr_ok = state->v ? myenable(state->hcounteren) : true; + const bool sctr_ok = (proc->extension_enabled('S') && state->prv < PRV_S) ? myenable(state->scounteren) : true; + + if (!mctr_ok) + throw trap_illegal_instruction(insn.bits()); + if (!hctr_ok) + throw trap_virtual_instruction(insn.bits()); + if (!sctr_ok) { + if (state->v) + throw trap_virtual_instruction(insn.bits()); + else + throw trap_illegal_instruction(insn.bits()); + } +} + +mevent_csr_t::mevent_csr_t(processor_t* const proc, const reg_t addr): + basic_csr_t(proc, addr, 0) { +} + +bool mevent_csr_t::unlogged_write(const reg_t val) noexcept { + const reg_t mask = proc->extension_enabled(EXT_SSCOFPMF) ? MHPMEVENT_OF | MHPMEVENT_MINH + | (proc->extension_enabled_const('U') ? MHPMEVENT_UINH : 0) + | (proc->extension_enabled_const('S') ? MHPMEVENT_SINH : 0) + | (proc->extension_enabled('H') ? MHPMEVENT_VUINH | MHPMEVENT_VSINH : 0) : 0; + return basic_csr_t::unlogged_write((read() & ~mask) | (val & mask)); +} + +hypervisor_csr_t::hypervisor_csr_t(processor_t* const proc, const reg_t addr): + basic_csr_t(proc, addr, 0) { +} + +void hypervisor_csr_t::verify_permissions(insn_t insn, bool write) const { + basic_csr_t::verify_permissions(insn, write); + if (!proc->extension_enabled('H')) + throw trap_illegal_instruction(insn.bits()); +} + +hideleg_csr_t::hideleg_csr_t(processor_t* const proc, const reg_t addr, csr_t_p mideleg): + masked_csr_t(proc, addr, MIP_VS_MASK, 0), + mideleg(mideleg) { +} + +reg_t hideleg_csr_t::read() const noexcept { + return masked_csr_t::read() & mideleg->read(); +}; + +hgatp_csr_t::hgatp_csr_t(processor_t* const proc, const reg_t addr): + basic_csr_t(proc, addr, 0) { +} + +void hgatp_csr_t::verify_permissions(insn_t insn, bool write) const { + basic_csr_t::verify_permissions(insn, write); + if (!state->v && get_field(state->mstatus->read(), MSTATUS_TVM)) + require_privilege(PRV_M); +} + +bool hgatp_csr_t::unlogged_write(const reg_t val) noexcept { + proc->get_mmu()->flush_tlb(); + + reg_t mask; + if (proc->get_const_xlen() == 32) { + mask = HGATP32_PPN | + HGATP32_MODE | + (proc->supports_impl(IMPL_MMU_VMID) ? HGATP32_VMID : 0); + } else { + mask = (HGATP64_PPN & ((reg_t(1) << (MAX_PADDR_BITS - PGSHIFT)) - 1)) | + (proc->supports_impl(IMPL_MMU_VMID) ? HGATP64_VMID : 0); + + if (get_field(val, HGATP64_MODE) == HGATP_MODE_OFF || + (proc->supports_impl(IMPL_MMU_SV39) && get_field(val, HGATP64_MODE) == HGATP_MODE_SV39X4) || + (proc->supports_impl(IMPL_MMU_SV48) && get_field(val, HGATP64_MODE) == HGATP_MODE_SV48X4) || + (proc->supports_impl(IMPL_MMU_SV57) && get_field(val, HGATP64_MODE) == HGATP_MODE_SV57X4)) + mask |= HGATP64_MODE; + } + mask &= ~(reg_t)3; + return basic_csr_t::unlogged_write((read() & ~mask) | (val & mask)); +} + +tselect_csr_t::tselect_csr_t(processor_t* const proc, const reg_t addr): + basic_csr_t(proc, addr, 0) { +} + +bool tselect_csr_t::unlogged_write(const reg_t val) noexcept { + return basic_csr_t::unlogged_write((val < proc->TM.count()) ? val : read()); +} + +tdata1_csr_t::tdata1_csr_t(processor_t* const proc, const reg_t addr): + csr_t(proc, addr) { +} + +reg_t tdata1_csr_t::read() const noexcept { + return proc->TM.tdata1_read(state->tselect->read()); +} + +bool tdata1_csr_t::unlogged_write(const reg_t val) noexcept { + return proc->TM.tdata1_write(state->tselect->read(), val); +} + +tdata2_csr_t::tdata2_csr_t(processor_t* const proc, const reg_t addr): + csr_t(proc, addr) { +} + +reg_t tdata2_csr_t::read() const noexcept { + return proc->TM.tdata2_read(state->tselect->read()); +} + +bool tdata2_csr_t::unlogged_write(const reg_t val) noexcept { + return proc->TM.tdata2_write(state->tselect->read(), val); +} + +tdata3_csr_t::tdata3_csr_t(processor_t* const proc, const reg_t addr): + csr_t(proc, addr) { +} + +reg_t tdata3_csr_t::read() const noexcept { + return proc->TM.tdata3_read(state->tselect->read()); +} + +bool tdata3_csr_t::unlogged_write(const reg_t val) noexcept { + return proc->TM.tdata3_write(state->tselect->read(), val); +} + +tinfo_csr_t::tinfo_csr_t(processor_t* const proc, const reg_t addr) : + csr_t(proc, addr) { +} + +reg_t tinfo_csr_t::read() const noexcept { + return proc->TM.tinfo_read(state->tselect->read()); +} + +debug_mode_csr_t::debug_mode_csr_t(processor_t* const proc, const reg_t addr): + basic_csr_t(proc, addr, 0) { +} + +void debug_mode_csr_t::verify_permissions(insn_t insn, bool write) const { + basic_csr_t::verify_permissions(insn, write); + if (!state->debug_mode) + throw trap_illegal_instruction(insn.bits()); +} + +dpc_csr_t::dpc_csr_t(processor_t* const proc, const reg_t addr): + epc_csr_t(proc, addr) { +} + +void dpc_csr_t::verify_permissions(insn_t insn, bool write) const { + epc_csr_t::verify_permissions(insn, write); + if (!state->debug_mode) + throw trap_illegal_instruction(insn.bits()); +} + +dcsr_csr_t::dcsr_csr_t(processor_t* const proc, const reg_t addr): + csr_t(proc, addr), + prv(0), + step(false), + ebreakm(false), + ebreakh(false), + ebreaks(false), + ebreaku(false), + halt(false), + cause(0) { +} + +void dcsr_csr_t::verify_permissions(insn_t insn, bool write) const { + csr_t::verify_permissions(insn, write); + if (!state->debug_mode) + throw trap_illegal_instruction(insn.bits()); +} + +reg_t dcsr_csr_t::read() const noexcept { + uint32_t v = 0; + v = set_field(v, DCSR_XDEBUGVER, 1); + v = set_field(v, DCSR_EBREAKM, ebreakm); + v = set_field(v, DCSR_EBREAKH, ebreakh); + v = set_field(v, DCSR_EBREAKS, ebreaks); + v = set_field(v, DCSR_EBREAKU, ebreaku); + v = set_field(v, DCSR_STOPCYCLE, 0); + v = set_field(v, DCSR_STOPTIME, 0); + v = set_field(v, DCSR_CAUSE, cause); + v = set_field(v, DCSR_STEP, step); + v = set_field(v, DCSR_PRV, prv); + return v; +} + +bool dcsr_csr_t::unlogged_write(const reg_t val) noexcept { + prv = get_field(val, DCSR_PRV); + step = get_field(val, DCSR_STEP); + // TODO: ndreset and fullreset + ebreakm = get_field(val, DCSR_EBREAKM); + ebreakh = get_field(val, DCSR_EBREAKH); + ebreaks = get_field(val, DCSR_EBREAKS); + ebreaku = get_field(val, DCSR_EBREAKU); + halt = get_field(val, DCSR_HALT); + return true; +} + +void dcsr_csr_t::write_cause_and_prv(uint8_t cause, reg_t prv) noexcept { + this->cause = cause; + this->prv = prv; + log_write(); +} + +float_csr_t::float_csr_t(processor_t* const proc, const reg_t addr, const reg_t mask, const reg_t init): + masked_csr_t(proc, addr, mask, init) { +} + +void float_csr_t::verify_permissions(insn_t insn, bool write) const { + masked_csr_t::verify_permissions(insn, write); + require_fs; + if (!proc->extension_enabled('F') && !proc->extension_enabled(EXT_ZFINX)) + throw trap_illegal_instruction(insn.bits()); + + if (proc->extension_enabled(EXT_SMSTATEEN) && proc->extension_enabled(EXT_ZFINX)) { + if ((state->prv < PRV_M) && !(state->mstateen[0]->read() & MSTATEEN0_FCSR)) + throw trap_illegal_instruction(insn.bits()); + + if (state->v && !(state->hstateen[0]->read() & HSTATEEN0_FCSR)) + throw trap_virtual_instruction(insn.bits()); + + if ((proc->extension_enabled('S') && state->prv < PRV_S) && !(state->sstateen[0]->read() & SSTATEEN0_FCSR)) { + if (state->v) + throw trap_virtual_instruction(insn.bits()); + else + throw trap_illegal_instruction(insn.bits()); + } + } +} + +bool float_csr_t::unlogged_write(const reg_t val) noexcept { + dirty_fp_state; + return masked_csr_t::unlogged_write(val); +} + +composite_csr_t::composite_csr_t(processor_t* const proc, const reg_t addr, csr_t_p upper_csr, csr_t_p lower_csr, const unsigned upper_lsb): + csr_t(proc, addr), + upper_csr(upper_csr), + lower_csr(lower_csr), + upper_lsb(upper_lsb) { +} + +void composite_csr_t::verify_permissions(insn_t insn, bool write) const { + // It is reasonable to assume that either underlying CSR will have + // the same permissions as this composite. + upper_csr->verify_permissions(insn, write); +} + +reg_t composite_csr_t::read() const noexcept { + return (upper_csr->read() << upper_lsb) | lower_csr->read(); +} + +bool composite_csr_t::unlogged_write(const reg_t val) noexcept { + upper_csr->write(val >> upper_lsb); + lower_csr->write(val); + return false; // logging is done only by the underlying CSRs +} + +seed_csr_t::seed_csr_t(processor_t* const proc, const reg_t addr): + csr_t(proc, addr) { +} + +void seed_csr_t::verify_permissions(insn_t insn, bool write) const { + /* Read-only access disallowed due to wipe-on-read side effect */ + /* XXX mseccfg.sseed and mseccfg.useed should be verified. */ + if (!proc->extension_enabled(EXT_ZKR) || !write) + throw trap_illegal_instruction(insn.bits()); + csr_t::verify_permissions(insn, write); +} + +reg_t seed_csr_t::read() const noexcept { + return proc->es.get_seed(); +} + +bool seed_csr_t::unlogged_write(const reg_t val) noexcept { + proc->es.set_seed(val); + return true; +} + +vector_csr_t::vector_csr_t(processor_t* const proc, const reg_t addr, const reg_t mask, const reg_t init): + basic_csr_t(proc, addr, init), + mask(mask) { +} + +void vector_csr_t::verify_permissions(insn_t insn, bool write) const { + require_vector_vs; + if (!proc->extension_enabled('V')) + throw trap_illegal_instruction(insn.bits()); + basic_csr_t::verify_permissions(insn, write); +} + +void vector_csr_t::write_raw(const reg_t val) noexcept { + const bool success = basic_csr_t::unlogged_write(val); + if (success) + log_write(); +} + +bool vector_csr_t::unlogged_write(const reg_t val) noexcept { + if (mask == 0) return false; + dirty_vs_state; + return basic_csr_t::unlogged_write(val & mask); +} + +vxsat_csr_t::vxsat_csr_t(processor_t* const proc, const reg_t addr): + masked_csr_t(proc, addr, /*mask*/ 1, /*init*/ 0) { +} + +void vxsat_csr_t::verify_permissions(insn_t insn, bool write) const { + require_vector_vs; + if (!proc->extension_enabled('V') && !proc->extension_enabled(EXT_ZPN)) + throw trap_illegal_instruction(insn.bits()); + masked_csr_t::verify_permissions(insn, write); +} + +bool vxsat_csr_t::unlogged_write(const reg_t val) noexcept { + dirty_vs_state; + return masked_csr_t::unlogged_write(val); +} + +// implement class hstateen_csr_t +hstateen_csr_t::hstateen_csr_t(processor_t* const proc, const reg_t addr, const reg_t mask, + const reg_t init, uint8_t index): + masked_csr_t(proc, addr, mask, init), + index(index) { +} + +reg_t hstateen_csr_t::read() const noexcept { + // For every bit in an mstateen CSR that is zero (whether read-only zero or set to zero), + // the same bit appears as read-only zero in the matching hstateen and sstateen CSRs + return masked_csr_t::read() & state->mstateen[index]->read(); +} + +bool hstateen_csr_t::unlogged_write(const reg_t val) noexcept { + // For every bit in an mstateen CSR that is zero (whether read-only zero or set to zero), + // the same bit appears as read-only zero in the matching hstateen and sstateen CSRs + return masked_csr_t::unlogged_write(val & state->mstateen[index]->read()); +} + +void hstateen_csr_t::verify_permissions(insn_t insn, bool write) const { + if ((state->prv < PRV_M) && !(state->mstateen[index]->read() & MSTATEEN_HSTATEEN)) + throw trap_illegal_instruction(insn.bits()); + masked_csr_t::verify_permissions(insn, write); +} + +// implement class sstateen_csr_t +sstateen_csr_t::sstateen_csr_t(processor_t* const proc, const reg_t addr, const reg_t mask, + const reg_t init, uint8_t index): + hstateen_csr_t(proc, addr, mask, init, index) { +} + +reg_t sstateen_csr_t::read() const noexcept { + // For every bit in an mstateen CSR that is zero (whether read-only zero or set to zero), + // the same bit appears as read-only zero in the matching hstateen and sstateen CSRs + // For every bit in an hstateen CSR that is zero (whether read-only zero or set to zero), + // the same bit appears as read-only zero in sstateen when accessed in VS-mode + if (state->v) + return hstateen_csr_t::read() & state->hstateen[index]->read(); + else + return hstateen_csr_t::read(); +} + +bool sstateen_csr_t::unlogged_write(const reg_t val) noexcept { + // For every bit in an mstateen CSR that is zero (whether read-only zero or set to zero), + // the same bit appears as read-only zero in the matching hstateen and sstateen CSRs + // For every bit in an hstateen CSR that is zero (whether read-only zero or set to zero), + // the same bit appears as read-only zero in sstateen when accessed in VS-mode + if (state->v) + return hstateen_csr_t::unlogged_write(val & state->hstateen[index]->read()); + else + return hstateen_csr_t::unlogged_write(val); +} + +void sstateen_csr_t::verify_permissions(insn_t insn, bool write) const { + hstateen_csr_t::verify_permissions(insn, write); + + if (state->v && !(state->hstateen[index]->read() & HSTATEEN_SSTATEEN)) + throw trap_virtual_instruction(insn.bits()); +} + +// implement class senvcfg_csr_t +senvcfg_csr_t::senvcfg_csr_t(processor_t* const proc, const reg_t addr, const reg_t mask, + const reg_t init): + masked_csr_t(proc, addr, mask, init) { +} + +void senvcfg_csr_t::verify_permissions(insn_t insn, bool write) const { + if (proc->extension_enabled(EXT_SMSTATEEN)) { + if ((state->prv < PRV_M) && !(state->mstateen[0]->read() & MSTATEEN0_HENVCFG)) + throw trap_illegal_instruction(insn.bits()); + + if (state->v && !(state->hstateen[0]->read() & HSTATEEN0_SENVCFG)) + throw trap_virtual_instruction(insn.bits()); + } + + masked_csr_t::verify_permissions(insn, write); +} + +void henvcfg_csr_t::verify_permissions(insn_t insn, bool write) const { + if (proc->extension_enabled(EXT_SMSTATEEN)) { + if ((state->prv < PRV_M) && !(state->mstateen[0]->read() & MSTATEEN0_HENVCFG)) + throw trap_illegal_instruction(insn.bits()); + } + + masked_csr_t::verify_permissions(insn, write); +} + +stimecmp_csr_t::stimecmp_csr_t(processor_t* const proc, const reg_t addr, const reg_t imask): + basic_csr_t(proc, addr, 0), intr_mask(imask) { +} + +bool stimecmp_csr_t::unlogged_write(const reg_t val) noexcept { + state->mip->backdoor_write_with_mask(intr_mask, state->time->read() >= val ? intr_mask : 0); + return basic_csr_t::unlogged_write(val); +} + +virtualized_stimecmp_csr_t::virtualized_stimecmp_csr_t(processor_t* const proc, csr_t_p orig, csr_t_p virt): + virtualized_csr_t(proc, orig, virt) { +} + +void virtualized_stimecmp_csr_t::verify_permissions(insn_t insn, bool write) const { + if (!(state->menvcfg->read() & MENVCFG_STCE)) { + // access to (v)stimecmp with MENVCFG.STCE = 0 + if (state->prv < PRV_M) + throw trap_illegal_instruction(insn.bits()); + } + + state->time_proxy->verify_permissions(insn, false); + + if (state->v && !(state->henvcfg->read() & HENVCFG_STCE)) { + // access to vstimecmp with MENVCFG.STCE = 1 and HENVCFG.STCE = 0 when V = 1 + throw trap_virtual_instruction(insn.bits()); + } + + virtualized_csr_t::verify_permissions(insn, write); +} + +scountovf_csr_t::scountovf_csr_t(processor_t* const proc, const reg_t addr): + csr_t(proc, addr) { +} + +void scountovf_csr_t::verify_permissions(insn_t insn, bool write) const { + if (!proc->extension_enabled(EXT_SSCOFPMF)) + throw trap_illegal_instruction(insn.bits()); + csr_t::verify_permissions(insn, write); +} + +reg_t scountovf_csr_t::read() const noexcept { + reg_t val = 0; + for (reg_t i = 3; i < N_HPMCOUNTERS + 3; ++i) { + bool of = state->mevent[i - 3]->read() & MHPMEVENT_OF; + val |= of << i; + } + + /* In M and S modes, scountovf bit X is readable when mcounteren bit X is set, */ + /* and otherwise reads as zero. Similarly, in VS mode, scountovf bit X is readable */ + /* when mcounteren bit X and hcounteren bit X are both set, and otherwise reads as zero. */ + val &= state->mcounteren->read(); + if (state->v) + val &= state->hcounteren->read(); + return val; +} + +bool scountovf_csr_t::unlogged_write(const reg_t UNUSED val) noexcept { + /* this function is unused */ + return false; +} + +// implement class jvt_csr_t +jvt_csr_t::jvt_csr_t(processor_t* const proc, const reg_t addr, const reg_t init): + basic_csr_t(proc, addr, init) { +} + +void jvt_csr_t::verify_permissions(insn_t insn, bool write) const { + basic_csr_t::verify_permissions(insn, write); + + if (!proc->extension_enabled(EXT_ZCMT)) + throw trap_illegal_instruction(insn.bits()); + + if (proc->extension_enabled(EXT_SMSTATEEN)) { + if ((state->prv < PRV_M) && !(state->mstateen[0]->read() & SSTATEEN0_JVT)) + throw trap_illegal_instruction(insn.bits()); + + if (state->v && !(state->hstateen[0]->read() & SSTATEEN0_JVT)) + throw trap_virtual_instruction(insn.bits()); + + if ((proc->extension_enabled('S') && state->prv < PRV_S) && !(state->sstateen[0]->read() & SSTATEEN0_JVT)) { + if (state->v) + throw trap_virtual_instruction(insn.bits()); + else + throw trap_illegal_instruction(insn.bits()); + } + } +} diff --git a/vendor/riscv/riscv-isa-sim/riscv/csrs.h b/vendor/riscv/riscv-isa-sim/riscv/csrs.h new file mode 100644 index 0000000000..65be799320 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/csrs.h @@ -0,0 +1,788 @@ +// See LICENSE for license details. +#ifndef _RISCV_CSRS_H +#define _RISCV_CSRS_H + +#include "common.h" +#include "encoding.h" +// For reg_t: +#include "decode.h" +// For std::shared_ptr +#include <memory> +// For access_type: +#include "memtracer.h" +#include <cassert> + +class processor_t; +struct state_t; + +// Parent, abstract class for all CSRs +class csr_t { + public: + csr_t(processor_t* const proc, const reg_t addr); + + // Throw exception if read/write disallowed. + virtual void verify_permissions(insn_t insn, bool write) const; + + // read() returns the architectural value of this CSR. No permission + // checking needed or allowed. Side effects not allowed. + virtual reg_t read() const noexcept = 0; + + // write() updates the architectural value of this CSR. No + // permission checking needed or allowed. + // Child classes must implement unlogged_write() + void write(const reg_t val) noexcept; + + virtual ~csr_t(); + + protected: + // Return value indicates success; false means no write actually occurred + virtual bool unlogged_write(const reg_t val) noexcept = 0; + + // Record this CSR update (which has already happened) in the commit log + void log_write() const noexcept; + + // Record a write to an alternate CSR (e.g. minstreth instead of minstret) + void log_special_write(const reg_t address, const reg_t val) const noexcept; + + // What value was written to this reg? Default implementation simply + // calls read(), but a few CSRs are special. + virtual reg_t written_value() const noexcept; + + processor_t* const proc; + state_t* const state; + public: + const reg_t address; + private: + const unsigned csr_priv; + const bool csr_read_only; + + // For access to written_value() and unlogged_write(): + friend class rv32_high_csr_t; + friend class rv32_low_csr_t; +}; + +typedef std::shared_ptr<csr_t> csr_t_p; + +// Basic CSRs, with XLEN bits fully readable and writable. +class basic_csr_t: public csr_t { + public: + basic_csr_t(processor_t* const proc, const reg_t addr, const reg_t init); + + virtual reg_t read() const noexcept override { + return val; + } + + protected: + virtual bool unlogged_write(const reg_t val) noexcept override; + private: + reg_t val; +}; + +class pmpaddr_csr_t: public csr_t { + public: + pmpaddr_csr_t(processor_t* const proc, const reg_t addr); + virtual void verify_permissions(insn_t insn, bool write) const override; + virtual reg_t read() const noexcept override; + + // Does a 4-byte access at the specified address match this PMP entry? + bool match4(reg_t addr) const noexcept; + + // Does the specified range match only a proper subset of this page? + bool subset_match(reg_t addr, reg_t len) const noexcept; + + // Is the specified access allowed given the pmpcfg privileges? + bool access_ok(access_type type, reg_t mode) const noexcept; + + // To check lock bit status from outside like mseccfg + bool is_locked() const noexcept { + return cfg & PMP_L; + } + + protected: + virtual bool unlogged_write(const reg_t val) noexcept override; + private: + // Assuming this is configured as TOR, return address for top of + // range. Also forms bottom-of-range for next-highest pmpaddr + // register if that one is TOR. + reg_t tor_paddr() const noexcept; + + // Assuming this is configured as TOR, return address for bottom of + // range. This is tor_paddr() from the previous pmpaddr register. + reg_t tor_base_paddr() const noexcept; + + // Assuming this is configured as NAPOT or NA4, return mask for paddr. + // E.g. for 4KiB region, returns 0xffffffff_fffff000. + reg_t napot_mask() const noexcept; + + bool next_locked_and_tor() const noexcept; + reg_t val; + friend class pmpcfg_csr_t; // so he can access cfg + uint8_t cfg; + const size_t pmpidx; +}; + +typedef std::shared_ptr<pmpaddr_csr_t> pmpaddr_csr_t_p; + +class pmpcfg_csr_t: public csr_t { + public: + pmpcfg_csr_t(processor_t* const proc, const reg_t addr); + virtual void verify_permissions(insn_t insn, bool write) const override; + virtual reg_t read() const noexcept override; + protected: + virtual bool unlogged_write(const reg_t val) noexcept override; +}; + +class mseccfg_csr_t: public basic_csr_t { + public: + mseccfg_csr_t(processor_t* const proc, const reg_t addr); + virtual void verify_permissions(insn_t insn, bool write) const override; + bool get_mml() const noexcept; + bool get_mmwp() const noexcept; + bool get_rlb() const noexcept; + protected: + virtual bool unlogged_write(const reg_t val) noexcept override; +}; + +typedef std::shared_ptr<mseccfg_csr_t> mseccfg_csr_t_p; + +// For CSRs that have a virtualized copy under another name. Each +// instance of virtualized_csr_t will read/write one of two CSRs, +// based on state.v. E.g. sscratch, stval, etc. +// +// Example: sscratch and vsscratch are both instances of basic_csr_t. +// The csrmap will contain a virtualized_csr_t under sscratch's +// address, plus the vsscratch basic_csr_t under its address. + +class virtualized_csr_t: public csr_t { + public: + virtualized_csr_t(processor_t* const proc, csr_t_p orig, csr_t_p virt); + + virtual reg_t read() const noexcept override; + // Instead of using state.v, explicitly request original or virtual: + reg_t readvirt(bool virt) const noexcept; + protected: + virtual bool unlogged_write(const reg_t val) noexcept override; + csr_t_p orig_csr; + csr_t_p virt_csr; +}; + +typedef std::shared_ptr<virtualized_csr_t> virtualized_csr_t_p; + +// For mepc, sepc, and vsepc +class epc_csr_t: public csr_t { + public: + epc_csr_t(processor_t* const proc, const reg_t addr); + + virtual reg_t read() const noexcept override; + protected: + virtual bool unlogged_write(const reg_t val) noexcept override; + private: + reg_t val; +}; + +// For mtvec, stvec, and vstvec +class tvec_csr_t: public csr_t { + public: + tvec_csr_t(processor_t* const proc, const reg_t addr); + + virtual reg_t read() const noexcept override; + protected: + virtual bool unlogged_write(const reg_t val) noexcept override; + private: + reg_t val; +}; + +// For mcause, scause, and vscause +class cause_csr_t: public basic_csr_t { + public: + cause_csr_t(processor_t* const proc, const reg_t addr); + + virtual reg_t read() const noexcept override; +}; + +// For *status family of CSRs +class base_status_csr_t: public csr_t { + public: + base_status_csr_t(processor_t* const proc, const reg_t addr); + + bool field_exists(const reg_t which) { + return (sstatus_write_mask & which) != 0; + } + + protected: + reg_t adjust_sd(const reg_t val) const noexcept; + void maybe_flush_tlb(const reg_t newval) noexcept; + const bool has_page; + const reg_t sstatus_write_mask; + const reg_t sstatus_read_mask; + private: + reg_t compute_sstatus_write_mask() const noexcept; +}; + +typedef std::shared_ptr<base_status_csr_t> base_status_csr_t_p; + +// For vsstatus, which is its own separate architectural register +// (unlike sstatus) +class vsstatus_csr_t final: public base_status_csr_t { + public: + vsstatus_csr_t(processor_t* const proc, const reg_t addr); + + reg_t read() const noexcept override { + return val; + } + + protected: + virtual bool unlogged_write(const reg_t val) noexcept override; + private: + reg_t val; +}; + +typedef std::shared_ptr<vsstatus_csr_t> vsstatus_csr_t_p; + +class mstatus_csr_t final: public base_status_csr_t { + public: + mstatus_csr_t(processor_t* const proc, const reg_t addr); + + reg_t read() const noexcept override { + return val; + } + + protected: + virtual bool unlogged_write(const reg_t val) noexcept override; + private: + reg_t compute_mstatus_initial_value() const noexcept; + reg_t val; +}; + +typedef std::shared_ptr<mstatus_csr_t> mstatus_csr_t_p; + +class mnstatus_csr_t final: public basic_csr_t { + public: + mnstatus_csr_t(processor_t* const proc, const reg_t addr); + protected: + virtual bool unlogged_write(const reg_t val) noexcept override; +}; + +// For RV32 CSRs that are split into two, e.g. mstatus/mstatush +// CSRW should only modify the lower half +class rv32_low_csr_t: public csr_t { + public: + rv32_low_csr_t(processor_t* const proc, const reg_t addr, csr_t_p orig); + virtual reg_t read() const noexcept override; + virtual void verify_permissions(insn_t insn, bool write) const override; + protected: + virtual bool unlogged_write(const reg_t val) noexcept override; + virtual reg_t written_value() const noexcept override; + private: + csr_t_p orig; +}; + +class rv32_high_csr_t: public csr_t { + public: + rv32_high_csr_t(processor_t* const proc, const reg_t addr, csr_t_p orig); + virtual reg_t read() const noexcept override; + virtual void verify_permissions(insn_t insn, bool write) const override; + protected: + virtual bool unlogged_write(const reg_t val) noexcept override; + virtual reg_t written_value() const noexcept override; + private: + csr_t_p orig; +}; + +class sstatus_proxy_csr_t final: public base_status_csr_t { + public: + sstatus_proxy_csr_t(processor_t* const proc, const reg_t addr, mstatus_csr_t_p mstatus); + + reg_t read() const noexcept override { + return mstatus->read() & sstatus_read_mask; + } + + protected: + virtual bool unlogged_write(const reg_t val) noexcept override; + private: + mstatus_csr_t_p mstatus; +}; + +typedef std::shared_ptr<sstatus_proxy_csr_t> sstatus_proxy_csr_t_p; + +class sstatus_csr_t: public virtualized_csr_t { + public: + sstatus_csr_t(processor_t* const proc, sstatus_proxy_csr_t_p orig, vsstatus_csr_t_p virt); + + // Set FS, VS, or XS bits to dirty + void dirty(const reg_t dirties); + // Return true if the specified bits are not 00 (Off) + bool enabled(const reg_t which); + private: + sstatus_proxy_csr_t_p orig_sstatus; + vsstatus_csr_t_p virt_sstatus; +}; + +typedef std::shared_ptr<sstatus_csr_t> sstatus_csr_t_p; + +class misa_csr_t final: public basic_csr_t { + public: + misa_csr_t(processor_t* const proc, const reg_t addr, const reg_t max_isa); + + bool extension_enabled(unsigned char ext) const noexcept { + assert(ext >= 'A' && ext <= 'Z'); + return (read() >> (ext - 'A')) & 1; + } + + bool extension_enabled_const(unsigned char ext) const noexcept; + protected: + virtual bool unlogged_write(const reg_t val) noexcept override; + private: + const reg_t max_isa; + const reg_t write_mask; + reg_t dependency(const reg_t val, const char feature, const char depends_on) const noexcept; +}; + +typedef std::shared_ptr<misa_csr_t> misa_csr_t_p; + +class mip_or_mie_csr_t: public csr_t { + public: + mip_or_mie_csr_t(processor_t* const proc, const reg_t addr); + virtual reg_t read() const noexcept override final; + + void write_with_mask(const reg_t mask, const reg_t val) noexcept; + + protected: + virtual bool unlogged_write(const reg_t val) noexcept override final; + reg_t val; + private: + virtual reg_t write_mask() const noexcept = 0; +}; + +// mip is special because some of the bits are driven by hardware pins +class mip_csr_t: public mip_or_mie_csr_t { + public: + mip_csr_t(processor_t* const proc, const reg_t addr); + + // Does not log. Used by external things (clint) that wiggle bits in mip. + void backdoor_write_with_mask(const reg_t mask, const reg_t val) noexcept; + private: + virtual reg_t write_mask() const noexcept override; +}; + +typedef std::shared_ptr<mip_csr_t> mip_csr_t_p; + +class mie_csr_t: public mip_or_mie_csr_t { + public: + mie_csr_t(processor_t* const proc, const reg_t addr); + private: + virtual reg_t write_mask() const noexcept override; +}; + +typedef std::shared_ptr<mie_csr_t> mie_csr_t_p; + +// For sip, hip, hvip, vsip, sie, hie, vsie which are all just (masked +// & shifted) views into mip or mie. Each pair will have one of these +// objects describing the view, e.g. one for sip+sie, one for hip+hie, +// etc. +class generic_int_accessor_t { + public: + enum mask_mode_t { NONE, MIDELEG, HIDELEG }; + + generic_int_accessor_t(state_t* const state, + const reg_t read_mask, + const reg_t ip_write_mask, + const reg_t ie_write_mask, + const mask_mode_t mask_mode, + const int shiftamt); + reg_t ip_read() const noexcept; + void ip_write(const reg_t val) noexcept; + reg_t ie_read() const noexcept; + void ie_write(const reg_t val) noexcept; + private: + state_t* const state; + const reg_t read_mask; + const reg_t ip_write_mask; + const reg_t ie_write_mask; + const bool mask_mideleg; + const bool mask_hideleg; + const int shiftamt; + reg_t deleg_mask() const; +}; + +typedef std::shared_ptr<generic_int_accessor_t> generic_int_accessor_t_p; + +// For all CSRs that are simply (masked & shifted) views into mip +class mip_proxy_csr_t: public csr_t { + public: + mip_proxy_csr_t(processor_t* const proc, const reg_t addr, generic_int_accessor_t_p accr); + virtual reg_t read() const noexcept override; + protected: + virtual bool unlogged_write(const reg_t val) noexcept override; + private: + generic_int_accessor_t_p accr; +}; + +// For all CSRs that are simply (masked & shifted) views into mie +class mie_proxy_csr_t: public csr_t { + public: + mie_proxy_csr_t(processor_t* const proc, const reg_t addr, generic_int_accessor_t_p accr); + virtual reg_t read() const noexcept override; + protected: + virtual bool unlogged_write(const reg_t val) noexcept override; + private: + generic_int_accessor_t_p accr; +}; + +class mideleg_csr_t: public basic_csr_t { + public: + mideleg_csr_t(processor_t* const proc, const reg_t addr); + virtual void verify_permissions(insn_t insn, bool write) const override; + virtual reg_t read() const noexcept override; + protected: + virtual bool unlogged_write(const reg_t val) noexcept override; +}; + +class medeleg_csr_t: public basic_csr_t { + public: + medeleg_csr_t(processor_t* const proc, const reg_t addr); + virtual void verify_permissions(insn_t insn, bool write) const override; + protected: + virtual bool unlogged_write(const reg_t val) noexcept override; + private: + const reg_t hypervisor_exceptions; +}; + +// For CSRs with certain bits hardwired +class masked_csr_t: public basic_csr_t { + public: + masked_csr_t(processor_t* const proc, const reg_t addr, const reg_t mask, const reg_t init); + protected: + virtual bool unlogged_write(const reg_t val) noexcept override; + private: + const reg_t mask; +}; + +// henvcfg.pbmte is read_only 0 when menvcfg.pbmte = 0 +// henvcfg.stce is read_only 0 when menvcfg.stce = 0 +// henvcfg.hade is read_only 0 when menvcfg.hade = 0 +class henvcfg_csr_t final: public masked_csr_t { + public: + henvcfg_csr_t(processor_t* const proc, const reg_t addr, const reg_t mask, const reg_t init, csr_t_p menvcfg); + + reg_t read() const noexcept override { + return (menvcfg->read() | ~(MENVCFG_PBMTE | MENVCFG_STCE | MENVCFG_HADE)) & masked_csr_t::read(); + } + + virtual void verify_permissions(insn_t insn, bool write) const override; + + private: + csr_t_p menvcfg; +}; + +// For satp and vsatp +// These are three classes in order to handle the [V]TVM bits permission checks +class base_atp_csr_t: public basic_csr_t { + public: + base_atp_csr_t(processor_t* const proc, const reg_t addr); + bool satp_valid(reg_t val) const noexcept; + protected: + virtual bool unlogged_write(const reg_t val) noexcept override; + private: + reg_t compute_new_satp(reg_t val) const noexcept; +}; + +class satp_csr_t: public base_atp_csr_t { + public: + satp_csr_t(processor_t* const proc, const reg_t addr); + virtual void verify_permissions(insn_t insn, bool write) const override; +}; + +typedef std::shared_ptr<satp_csr_t> satp_csr_t_p; + +class virtualized_satp_csr_t: public virtualized_csr_t { + public: + virtualized_satp_csr_t(processor_t* const proc, satp_csr_t_p orig, csr_t_p virt); + virtual void verify_permissions(insn_t insn, bool write) const override; + protected: + virtual bool unlogged_write(const reg_t val) noexcept override; + private: + satp_csr_t_p orig_satp; +}; + +// For minstret and mcycle, which are always 64 bits, but in RV32 are +// split into high and low halves. The first class always holds the +// full 64-bit value. +class wide_counter_csr_t: public csr_t { + public: + wide_counter_csr_t(processor_t* const proc, const reg_t addr); + // Always returns full 64-bit value + virtual reg_t read() const noexcept override; + void bump(const reg_t howmuch) noexcept; + protected: + virtual bool unlogged_write(const reg_t val) noexcept override; + virtual reg_t written_value() const noexcept override; + private: + reg_t val; +}; + +typedef std::shared_ptr<wide_counter_csr_t> wide_counter_csr_t_p; + +class time_counter_csr_t: public csr_t { + public: + time_counter_csr_t(processor_t* const proc, const reg_t addr); + virtual reg_t read() const noexcept override; + + void sync(const reg_t val) noexcept; + + protected: + virtual bool unlogged_write(const reg_t UNUSED val) noexcept override { return false; }; + private: + reg_t shadow_val; +}; + +typedef std::shared_ptr<time_counter_csr_t> time_counter_csr_t_p; + +// For a CSR that is an alias of another +class proxy_csr_t: public csr_t { + public: + proxy_csr_t(processor_t* const proc, const reg_t addr, csr_t_p delegate); + virtual reg_t read() const noexcept override; + protected: + bool unlogged_write(const reg_t val) noexcept override; + private: + csr_t_p delegate; +}; + +// For a CSR with a fixed, unchanging value +class const_csr_t: public csr_t { + public: + const_csr_t(processor_t* const proc, const reg_t addr, reg_t val); + virtual reg_t read() const noexcept override; + protected: + bool unlogged_write(const reg_t val) noexcept override; + private: + const reg_t val; +}; + +// For a CSR that is an unprivileged accessor of a privileged counter +class counter_proxy_csr_t: public proxy_csr_t { + public: + counter_proxy_csr_t(processor_t* const proc, const reg_t addr, csr_t_p delegate); + virtual void verify_permissions(insn_t insn, bool write) const override; + private: + bool myenable(csr_t_p counteren) const noexcept; +}; + +class mevent_csr_t: public basic_csr_t { + public: + mevent_csr_t(processor_t* const proc, const reg_t addr); + protected: + virtual bool unlogged_write(const reg_t val) noexcept override; +}; + +// For machine-level CSRs that only exist with Hypervisor +class hypervisor_csr_t: public basic_csr_t { + public: + hypervisor_csr_t(processor_t* const proc, const reg_t addr); + virtual void verify_permissions(insn_t insn, bool write) const override; +}; + +class hideleg_csr_t: public masked_csr_t { + public: + hideleg_csr_t(processor_t* const proc, const reg_t addr, csr_t_p mideleg); + virtual reg_t read() const noexcept override; + private: + csr_t_p mideleg; +}; + +class hgatp_csr_t: public basic_csr_t { + public: + hgatp_csr_t(processor_t* const proc, const reg_t addr); + virtual void verify_permissions(insn_t insn, bool write) const override; + protected: + virtual bool unlogged_write(const reg_t val) noexcept override; +}; + +class tselect_csr_t: public basic_csr_t { + public: + tselect_csr_t(processor_t* const proc, const reg_t addr); + protected: + virtual bool unlogged_write(const reg_t val) noexcept override; +}; + +class tdata1_csr_t: public csr_t { + public: + tdata1_csr_t(processor_t* const proc, const reg_t addr); + virtual reg_t read() const noexcept override; + protected: + virtual bool unlogged_write(const reg_t val) noexcept override; +}; + +class tdata2_csr_t: public csr_t { + public: + tdata2_csr_t(processor_t* const proc, const reg_t addr); + virtual reg_t read() const noexcept override; + protected: + virtual bool unlogged_write(const reg_t val) noexcept override; +}; + +class tdata3_csr_t: public csr_t { + public: + tdata3_csr_t(processor_t* const proc, const reg_t addr); + virtual reg_t read() const noexcept override; + protected: + virtual bool unlogged_write(const reg_t val) noexcept override; +}; + +class tinfo_csr_t: public csr_t { + public: + tinfo_csr_t(processor_t* const proc, const reg_t addr); + virtual reg_t read() const noexcept override; + protected: + virtual bool unlogged_write(const reg_t UNUSED val) noexcept override { return false; }; +}; + +// For CSRs that are only writable from debug mode +class debug_mode_csr_t: public basic_csr_t { + public: + debug_mode_csr_t(processor_t* const proc, const reg_t addr); + virtual void verify_permissions(insn_t insn, bool write) const override; +}; + +class dpc_csr_t: public epc_csr_t { + public: + dpc_csr_t(processor_t* const proc, const reg_t addr); + virtual void verify_permissions(insn_t insn, bool write) const override; +}; + +class dcsr_csr_t: public csr_t { + public: + dcsr_csr_t(processor_t* const proc, const reg_t addr); + virtual void verify_permissions(insn_t insn, bool write) const override; + virtual reg_t read() const noexcept override; + void write_cause_and_prv(uint8_t cause, reg_t prv) noexcept; + protected: + virtual bool unlogged_write(const reg_t val) noexcept override; + public: + uint8_t prv; + bool step; + bool ebreakm; + bool ebreakh; + bool ebreaks; + bool ebreaku; + bool halt; + uint8_t cause; +}; + +typedef std::shared_ptr<dcsr_csr_t> dcsr_csr_t_p; + +class float_csr_t final: public masked_csr_t { + public: + float_csr_t(processor_t* const proc, const reg_t addr, const reg_t mask, const reg_t init); + virtual void verify_permissions(insn_t insn, bool write) const override; + protected: + virtual bool unlogged_write(const reg_t val) noexcept override; +}; + +typedef std::shared_ptr<float_csr_t> float_csr_t_p; + +// For a CSR like FCSR, that is actually a view into multiple +// underlying registers. +class composite_csr_t: public csr_t { + public: + // We assume the lower_csr maps to bit 0. + composite_csr_t(processor_t* const proc, const reg_t addr, csr_t_p upper_csr, csr_t_p lower_csr, const unsigned upper_lsb); + virtual void verify_permissions(insn_t insn, bool write) const override; + virtual reg_t read() const noexcept override; + protected: + virtual bool unlogged_write(const reg_t val) noexcept override; + private: + csr_t_p upper_csr; + csr_t_p lower_csr; + const unsigned upper_lsb; +}; + +class seed_csr_t: public csr_t { + public: + seed_csr_t(processor_t* const proc, const reg_t addr); + virtual void verify_permissions(insn_t insn, bool write) const override; + virtual reg_t read() const noexcept override; + protected: + virtual bool unlogged_write(const reg_t val) noexcept override; +}; + +class vector_csr_t: public basic_csr_t { + public: + vector_csr_t(processor_t* const proc, const reg_t addr, const reg_t mask, const reg_t init=0); + virtual void verify_permissions(insn_t insn, bool write) const override; + // Write without regard to mask, and without touching mstatus.VS + void write_raw(const reg_t val) noexcept; + protected: + virtual bool unlogged_write(const reg_t val) noexcept override; + private: + reg_t mask; +}; + +typedef std::shared_ptr<vector_csr_t> vector_csr_t_p; + +// For CSRs shared between Vector and P extensions (vxsat) +class vxsat_csr_t: public masked_csr_t { + public: + vxsat_csr_t(processor_t* const proc, const reg_t addr); + virtual void verify_permissions(insn_t insn, bool write) const override; + protected: + virtual bool unlogged_write(const reg_t val) noexcept override; +}; + +class hstateen_csr_t: public masked_csr_t { + public: + hstateen_csr_t(processor_t* const proc, const reg_t addr, const reg_t mask, const reg_t init, uint8_t index); + virtual reg_t read() const noexcept override; + virtual void verify_permissions(insn_t insn, bool write) const override; + protected: + virtual bool unlogged_write(const reg_t val) noexcept override; +protected: + uint8_t index; +}; + +class sstateen_csr_t: public hstateen_csr_t { + public: + sstateen_csr_t(processor_t* const proc, const reg_t addr, const reg_t mask, const reg_t init, uint8_t index); + virtual reg_t read() const noexcept override; + virtual void verify_permissions(insn_t insn, bool write) const override; + protected: + virtual bool unlogged_write(const reg_t val) noexcept override; +}; + +class senvcfg_csr_t final: public masked_csr_t { + public: + senvcfg_csr_t(processor_t* const proc, const reg_t addr, const reg_t mask, const reg_t init); + virtual void verify_permissions(insn_t insn, bool write) const override; +}; + +class stimecmp_csr_t: public basic_csr_t { + public: + stimecmp_csr_t(processor_t* const proc, const reg_t addr, const reg_t imask); + protected: + virtual bool unlogged_write(const reg_t val) noexcept override; + private: + reg_t intr_mask; +}; + +class virtualized_stimecmp_csr_t: public virtualized_csr_t { + public: + virtualized_stimecmp_csr_t(processor_t* const proc, csr_t_p orig, csr_t_p virt); + virtual void verify_permissions(insn_t insn, bool write) const override; +}; + +class scountovf_csr_t: public csr_t { + public: + scountovf_csr_t(processor_t* const proc, const reg_t addr); + virtual void verify_permissions(insn_t insn, bool write) const override; + virtual reg_t read() const noexcept override; + protected: + virtual bool unlogged_write(const reg_t val) noexcept override; +}; + +class jvt_csr_t: public basic_csr_t { + public: + jvt_csr_t(processor_t* const proc, const reg_t addr, const reg_t init); + virtual void verify_permissions(insn_t insn, bool write) const override; +}; +#endif diff --git a/vendor/riscv/riscv-isa-sim/riscv/cvxif.h b/vendor/riscv/riscv-isa-sim/riscv/cvxif.h new file mode 100644 index 0000000000..0b0a72467b --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/cvxif.h @@ -0,0 +1,81 @@ +// Copyright (C) 2022 Thales DIS Design Services SAS +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0. +// +// Original Author: Zbigniew CHAMSKI <zbigniew.chamski@thalesgroup.com> + +#ifndef _RISCV_CVXIF_H +#define _RISCV_CVXIF_H + +#include "extension.h" + +// R-type instruction format +struct cvxif_r_insn_t +{ + unsigned opcode : 7; + unsigned rd : 5; + unsigned funct3 : 3; + unsigned rs1 : 5; + unsigned rs2 : 5; + unsigned funct7 : 7; +}; + +// R4-type instruction format +struct cvxif_r4_insn_t +{ + unsigned opcode : 7; + unsigned rd : 5; + unsigned funct3 : 3; + unsigned rs1 : 5; + unsigned rs2 : 5; + unsigned funct2 : 2; + unsigned rs3 : 5; +}; + +// I-type instruction format +struct cvxif_i_insn_t +{ + unsigned opcode : 7; + unsigned rd : 5; + unsigned funct3 : 3; + unsigned rs1 : 5; + unsigned imm : 12; +}; + +// S-type instruction format +struct cvxif_s_insn_t +{ + unsigned opcode : 7; + unsigned imm_low : 5; + unsigned funct3 : 3; + unsigned rs1 : 5; + unsigned rs2 : 5; + unsigned imm_high : 7; +}; + +union cvxif_insn_t +{ + cvxif_r_insn_t r_type; + cvxif_r4_insn_t r4_type; + cvxif_i_insn_t i_type; + cvxif_s_insn_t s_type; + insn_t i; +}; + +enum Func3 {FUNC3_0, FUNC3_1, FUNC3_2}; +enum Need_rs3 {NO_RS3, RS3_IN}; +enum Cus {CUS_NOP = 0, CUS_U_ADD = 2, CUS_S_ADD = 6, CUS_ADD_MULTI = 8}; + +class cvxif_extn_t : public extension_t +{ + public: + virtual bool do_writeback_p(cvxif_insn_t insn); + virtual reg_t custom0(cvxif_insn_t insn); + virtual reg_t custom1(cvxif_insn_t insn); + virtual reg_t custom2(cvxif_insn_t insn); + virtual reg_t custom3(cvxif_insn_t insn); + std::vector<insn_desc_t> get_instructions(); + std::vector<disasm_insn_t*> get_disasms(); +}; + +#endif diff --git a/vendor/riscv/riscv-isa-sim/riscv/cvxif_base.cc b/vendor/riscv/riscv-isa-sim/riscv/cvxif_base.cc new file mode 100644 index 0000000000..c9c045e6dc --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/cvxif_base.cc @@ -0,0 +1,66 @@ +// Copyright (C) 2022 Thales DIS Design Services SAS +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0. +// +// Original Author: Zbigniew CHAMSKI <zbigniew.chamski@thalesgroup.com> + +#define DECODE_MACRO_USAGE_LOGGED 1 +#include "decode_macros.h" +#include "cvxif.h" +#include "trap.h" +#include <cstdlib> + +// Virtual base class of CVXIF. + +// Return true if writeback is required. +// Be on the safe side, disable writeback. +bool cvxif_extn_t::do_writeback_p(cvxif_insn_t insn) +{ + return false; +} + +// Define custom insns templates. +// The insn-level wrapper is 'c##n' (default implementation, +// writeback disabled), the default implementation +// is 'custom##n': illegal instruction, return 0. +// The writeback controller 'cvxif_extn_t::do_writeback_p' +// is in charge of determining if writeback is required or not. +// Expected instruction encoding is 4 bytes. +#define customX(n) \ +static reg_t c##n(processor_t* p, insn_t insn, reg_t pc) \ + { \ + cvxif_extn_t* cvxif = static_cast<cvxif_extn_t*>(p->get_extension()); \ + cvxif_insn_t custom_insn; \ + custom_insn.i = insn; \ + reg_t xd = cvxif->custom##n(custom_insn); \ + if (cvxif->do_writeback_p(custom_insn)) \ + WRITE_RD(xd); \ + return pc+4; \ + } \ + \ + reg_t cvxif_extn_t::custom##n(cvxif_insn_t insn) \ + { \ + illegal_instruction(); \ + return -1; \ + } + +customX(0) +customX(1) +customX(2) +customX(3) + +std::vector<insn_desc_t> cvxif_extn_t::get_instructions() +{ + std::vector<insn_desc_t> insns; + insns.push_back((insn_desc_t){0x0b, 0x7f, &::illegal_instruction, c0}); + insns.push_back((insn_desc_t){0x2b, 0x7f, &::illegal_instruction, c1}); + insns.push_back((insn_desc_t){0x5b, 0x7f, &::illegal_instruction, c2}); + insns.push_back((insn_desc_t){0x7b, 0x7f, &::illegal_instruction, c3}); + return insns; +} + +std::vector<disasm_insn_t*> cvxif_extn_t::get_disasms() +{ + std::vector<disasm_insn_t*> insns; + return insns; +} diff --git a/vendor/riscv/riscv-isa-sim/riscv/debug_defines.h b/vendor/riscv/riscv-isa-sim/riscv/debug_defines.h new file mode 100644 index 0000000000..06ba082d95 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/debug_defines.h @@ -0,0 +1,3078 @@ +/* + * This file is auto-generated by running 'make debug_defines.h' in + * https://github.com/riscv/riscv-debug-spec/ (0e4d91e) + */ + +#define DTM_IDCODE 0x01 +/* + * Identifies the release version of this part. + */ +#define DTM_IDCODE_VERSION_OFFSET 0x1c +#define DTM_IDCODE_VERSION_LENGTH 4 +#define DTM_IDCODE_VERSION 0xf0000000U +/* + * Identifies the designer's part number of this part. + */ +#define DTM_IDCODE_PARTNUMBER_OFFSET 0xc +#define DTM_IDCODE_PARTNUMBER_LENGTH 0x10 +#define DTM_IDCODE_PARTNUMBER 0xffff000 +/* + * Identifies the designer/manufacturer of this part. Bits 6:0 must be + * bits 6:0 of the designer/manufacturer's Identification Code as + * assigned by JEDEC Standard JEP106. Bits 10:7 contain the modulo-16 + * count of the number of continuation characters (0x7f) in that same + * Identification Code. + */ +#define DTM_IDCODE_MANUFID_OFFSET 1 +#define DTM_IDCODE_MANUFID_LENGTH 0xb +#define DTM_IDCODE_MANUFID 0xffe +#define DTM_IDCODE_1_OFFSET 0 +#define DTM_IDCODE_1_LENGTH 1 +#define DTM_IDCODE_1 1 +#define DTM_DTMCS 0x10 +/* + * Writing 1 to this bit does a hard reset of the DTM, + * causing the DTM to forget about any outstanding DMI transactions, and + * returning all registers and internal state to their reset value. + * In general this should only be used when the Debugger has + * reason to expect that the outstanding DMI transaction will never + * complete (e.g. a reset condition caused an inflight DMI transaction to + * be cancelled). + */ +#define DTM_DTMCS_DMIHARDRESET_OFFSET 0x11 +#define DTM_DTMCS_DMIHARDRESET_LENGTH 1 +#define DTM_DTMCS_DMIHARDRESET 0x20000 +/* + * Writing 1 to this bit clears the sticky error state, but does + * not affect outstanding DMI transactions. + */ +#define DTM_DTMCS_DMIRESET_OFFSET 0x10 +#define DTM_DTMCS_DMIRESET_LENGTH 1 +#define DTM_DTMCS_DMIRESET 0x10000 +/* + * This is a hint to the debugger of the minimum number of + * cycles a debugger should spend in + * Run-Test/Idle after every DMI scan to avoid a `busy' + * return code (\FdtmDtmcsDmistat of 3). A debugger must still + * check \FdtmDtmcsDmistat when necessary. + * + * 0: It is not necessary to enter Run-Test/Idle at all. + * + * 1: Enter Run-Test/Idle and leave it immediately. + * + * 2: Enter Run-Test/Idle and stay there for 1 cycle before leaving. + * + * And so on. + */ +#define DTM_DTMCS_IDLE_OFFSET 0xc +#define DTM_DTMCS_IDLE_LENGTH 3 +#define DTM_DTMCS_IDLE 0x7000 +/* + * Read-only alias of \FdtmDmiOp. + */ +#define DTM_DTMCS_DMISTAT_OFFSET 0xa +#define DTM_DTMCS_DMISTAT_LENGTH 2 +#define DTM_DTMCS_DMISTAT 0xc00 +/* + * The size of \FdmSbaddressZeroAddress in \RdtmDmi. + */ +#define DTM_DTMCS_ABITS_OFFSET 4 +#define DTM_DTMCS_ABITS_LENGTH 6 +#define DTM_DTMCS_ABITS 0x3f0 +#define DTM_DTMCS_VERSION_OFFSET 0 +#define DTM_DTMCS_VERSION_LENGTH 4 +#define DTM_DTMCS_VERSION 0xf +/* + * 0.11: Version described in spec version 0.11. + */ +#define DTM_DTMCS_VERSION_0_11 0 +/* + * 1.0: Version described in spec versions 0.13 and 1.0. + */ +#define DTM_DTMCS_VERSION_1_0 1 +/* + * custom: Version not described in any available version of this spec. + */ +#define DTM_DTMCS_VERSION_CUSTOM 15 +#define DTM_DMI 0x11 +/* + * Address used for DMI access. In Update-DR this value is used + * to access the DM over the DMI. + */ +#define DTM_DMI_ADDRESS_OFFSET 0x22 +#define DTM_DMI_ADDRESS_LENGTH(abits) abits +#define DTM_DMI_ADDRESS(abits) ((0x400000000ULL * (1ULL<<abits)) + -0x400000000ULL) +/* + * The data to send to the DM over the DMI during Update-DR, and + * the data returned from the DM as a result of the previous operation. + */ +#define DTM_DMI_DATA_OFFSET 2 +#define DTM_DMI_DATA_LENGTH 0x20 +#define DTM_DMI_DATA 0x3fffffffcULL +/* + * When the debugger writes this field, it has the following meaning: + */ +#define DTM_DMI_OP_OFFSET 0 +#define DTM_DMI_OP_LENGTH 2 +#define DTM_DMI_OP 3 +/* + * nop: Ignore \FdmSbdataZeroData and \FdmSbaddressZeroAddress. + * + * Don't send anything over the DMI during Update-DR. + * This operation should never result in a busy or error response. + * The address and data reported in the following Capture-DR + * are undefined. + * + * This operation leaves the values in \FdtmDmiAddress and \FdtmDmiData + * \unspecified. + */ +#define DTM_DMI_OP_NOP 0 +/* + * read: Read from \FdtmDmiAddress. + * + * When this operation succeeds, \FdtmDmiAddress contains the address + * that was read from, and \FdtmDmiData contains the value that was + * read. + */ +#define DTM_DMI_OP_READ 1 +/* + * write: Write \FdtmDmiData to \FdtmDmiAddress. + * + * This operation leaves the values in \FdtmDmiAddress and \FdtmDmiData + * \unspecified. + */ +#define DTM_DMI_OP_WRITE 2 +/* + * reserved: Reserved. + */ +/* + * When the debugger reads this field, it means the following: + */ +/* + * success: The previous operation completed successfully. + */ +#define DTM_DMI_OP_SUCCESS 0 +/* + * reserved: Reserved. + */ +/* + * failed: A previous operation failed. The data scanned into \RdtmDmi in + * this access will be ignored. This status is sticky and can be + * cleared by writing \FdtmDtmcsDmireset in \RdtmDtmcs. + * + * This indicates that the DM itself responded with an error. + * There are no specified cases in which the DM would + * respond with an error, and DMI is not required to support + * returning errors. + */ +#define DTM_DMI_OP_FAILED 2 +/* + * busy: An operation was attempted while a DMI request is still in + * progress. The data scanned into \RdtmDmi in this access will be + * ignored. This status is sticky and can be cleared by writing + * \FdtmDtmcsDmireset in \RdtmDtmcs. If a debugger sees this status, it + * needs to give the target more TCK edges between Update-DR and + * Capture-DR. The simplest way to do that is to add extra transitions + * in Run-Test/Idle. + */ +#define DTM_DMI_OP_BUSY 3 +#define CSR_DCSR 0x7b0 +#define CSR_DCSR_DEBUGVER_OFFSET 0x1c +#define CSR_DCSR_DEBUGVER_LENGTH 4 +#define CSR_DCSR_DEBUGVER 0xf0000000U +/* + * none: There is no debug support. + */ +#define CSR_DCSR_DEBUGVER_NONE 0 +/* + * 1.0: Debug support exists as it is described in this document. + */ +#define CSR_DCSR_DEBUGVER_1_0 4 +/* + * custom: There is debug support, but it does not conform to any + * available version of this spec. + */ +#define CSR_DCSR_DEBUGVER_CUSTOM 15 +#define CSR_DCSR_EBREAKVS_OFFSET 0x11 +#define CSR_DCSR_EBREAKVS_LENGTH 1 +#define CSR_DCSR_EBREAKVS 0x20000 +/* + * exception: {\tt ebreak} instructions in VS-mode behave as described in the + * Privileged Spec. + */ +#define CSR_DCSR_EBREAKVS_EXCEPTION 0 +/* + * debug mode: {\tt ebreak} instructions in VS-mode enter Debug Mode. + */ +#define CSR_DCSR_EBREAKVS_DEBUG_MODE 1 +/* + * This bit is hardwired to 0 if the hart does not support virtualization mode. + */ +#define CSR_DCSR_EBREAKVU_OFFSET 0x10 +#define CSR_DCSR_EBREAKVU_LENGTH 1 +#define CSR_DCSR_EBREAKVU 0x10000 +/* + * exception: {\tt ebreak} instructions in VU-mode behave as described in the + * Privileged Spec. + */ +#define CSR_DCSR_EBREAKVU_EXCEPTION 0 +/* + * debug mode: {\tt ebreak} instructions in VU-mode enter Debug Mode. + */ +#define CSR_DCSR_EBREAKVU_DEBUG_MODE 1 +/* + * This bit is hardwired to 0 if the hart does not support virtualization mode. + */ +#define CSR_DCSR_EBREAKM_OFFSET 0xf +#define CSR_DCSR_EBREAKM_LENGTH 1 +#define CSR_DCSR_EBREAKM 0x8000 +/* + * exception: {\tt ebreak} instructions in M-mode behave as described in the + * Privileged Spec. + */ +#define CSR_DCSR_EBREAKM_EXCEPTION 0 +/* + * debug mode: {\tt ebreak} instructions in M-mode enter Debug Mode. + */ +#define CSR_DCSR_EBREAKM_DEBUG_MODE 1 +#define CSR_DCSR_EBREAKS_OFFSET 0xd +#define CSR_DCSR_EBREAKS_LENGTH 1 +#define CSR_DCSR_EBREAKS 0x2000 +/* + * exception: {\tt ebreak} instructions in S-mode behave as described in the + * Privileged Spec. + */ +#define CSR_DCSR_EBREAKS_EXCEPTION 0 +/* + * debug mode: {\tt ebreak} instructions in S-mode enter Debug Mode. + */ +#define CSR_DCSR_EBREAKS_DEBUG_MODE 1 +/* + * This bit is hardwired to 0 if the hart does not support S-mode. + */ +#define CSR_DCSR_EBREAKU_OFFSET 0xc +#define CSR_DCSR_EBREAKU_LENGTH 1 +#define CSR_DCSR_EBREAKU 0x1000 +/* + * exception: {\tt ebreak} instructions in U-mode behave as described in the + * Privileged Spec. + */ +#define CSR_DCSR_EBREAKU_EXCEPTION 0 +/* + * debug mode: {\tt ebreak} instructions in U-mode enter Debug Mode. + */ +#define CSR_DCSR_EBREAKU_DEBUG_MODE 1 +/* + * This bit is hardwired to 0 if the hart does not support U-mode. + */ +#define CSR_DCSR_STEPIE_OFFSET 0xb +#define CSR_DCSR_STEPIE_LENGTH 1 +#define CSR_DCSR_STEPIE 0x800 +/* + * interrupts disabled: Interrupts (including NMI) are disabled during single stepping. + */ +#define CSR_DCSR_STEPIE_INTERRUPTS_DISABLED 0 +/* + * interrupts enabled: Interrupts (including NMI) are enabled during single stepping. + */ +#define CSR_DCSR_STEPIE_INTERRUPTS_ENABLED 1 +/* + * Implementations may hard wire this bit to 0. + * In that case interrupt behavior can be emulated by the debugger. + * + * The debugger must not change the value of this bit while the hart + * is running. + */ +#define CSR_DCSR_STOPCOUNT_OFFSET 0xa +#define CSR_DCSR_STOPCOUNT_LENGTH 1 +#define CSR_DCSR_STOPCOUNT 0x400 +/* + * normal: Increment counters as usual. + */ +#define CSR_DCSR_STOPCOUNT_NORMAL 0 +/* + * freeze: Don't increment any hart-local counters while in Debug Mode or + * on {\tt ebreak} instructions that cause entry into Debug Mode. + * These counters include the {\tt instret} CSR. On single-hart cores + * {\tt cycle} should be stopped, but on multi-hart cores it must keep + * incrementing. + */ +#define CSR_DCSR_STOPCOUNT_FREEZE 1 +/* + * An implementation may hardwire this bit to 0 or 1. + */ +#define CSR_DCSR_STOPTIME_OFFSET 9 +#define CSR_DCSR_STOPTIME_LENGTH 1 +#define CSR_DCSR_STOPTIME 0x200 +/* + * normal: Increment \Rtime as usual. + */ +#define CSR_DCSR_STOPTIME_NORMAL 0 +/* + * freeze: Don't increment \Rtime while in Debug Mode. If all harts + * have \FcsrDcsrStoptime=1 and are in Debug Mode then \Rmtime + * is also allowed to stop incrementing. + */ +#define CSR_DCSR_STOPTIME_FREEZE 1 +/* + * An implementation may hardwire this bit to 0 or 1. + */ +/* + * Explains why Debug Mode was entered. + * + * When there are multiple reasons to enter Debug Mode in a single + * cycle, hardware should set \FcsrDcsrCause to the cause with the highest + * priority. See table~\ref{tab:dcsrcausepriority} for priorities. + */ +#define CSR_DCSR_CAUSE_OFFSET 6 +#define CSR_DCSR_CAUSE_LENGTH 3 +#define CSR_DCSR_CAUSE 0x1c0 +/* + * ebreak: An {\tt ebreak} instruction was executed. + */ +#define CSR_DCSR_CAUSE_EBREAK 1 +/* + * trigger: A Trigger Module trigger fired with action=1. + */ +#define CSR_DCSR_CAUSE_TRIGGER 2 +/* + * haltreq: The debugger requested entry to Debug Mode using \FdmDmcontrolHaltreq. + */ +#define CSR_DCSR_CAUSE_HALTREQ 3 +/* + * step: The hart single stepped because \FcsrDcsrStep was set. + */ +#define CSR_DCSR_CAUSE_STEP 4 +/* + * resethaltreq: The hart halted directly out of reset due to \Fresethaltreq. It + * is also acceptable to report 3 when this happens. + */ +#define CSR_DCSR_CAUSE_RESETHALTREQ 5 +/* + * group: The hart halted because it's part of a halt group. + * Harts may report 3 for this cause instead. + */ +#define CSR_DCSR_CAUSE_GROUP 6 +/* + * Other values are reserved for future use. + */ +/* + * Extends the prv field with the virtualization mode the hart was operating + * in when Debug Mode was entered. The encoding is described in Table + * \ref{tab:privmode}. + * A debugger can change this value to change the hart's virtualization mode + * when exiting Debug Mode. + * This bit is hardwired to 0 on harts that do not support virtualization mode. + */ +#define CSR_DCSR_V_OFFSET 5 +#define CSR_DCSR_V_LENGTH 1 +#define CSR_DCSR_V 0x20 +#define CSR_DCSR_MPRVEN_OFFSET 4 +#define CSR_DCSR_MPRVEN_LENGTH 1 +#define CSR_DCSR_MPRVEN 0x10 +/* + * disabled: \FcsrMstatusMprv in \Rmstatus is ignored in Debug Mode. + */ +#define CSR_DCSR_MPRVEN_DISABLED 0 +/* + * enabled: \FcsrMstatusMprv in \Rmstatus takes effect in Debug Mode. + */ +#define CSR_DCSR_MPRVEN_ENABLED 1 +/* + * Implementing this bit is optional. It may be tied to either 0 or 1. + */ +/* + * When set, there is a Non-Maskable-Interrupt (NMI) pending for the hart. + * + * Since an NMI can indicate a hardware error condition, + * reliable debugging may no longer be possible once this bit becomes set. + * This is implementation-dependent. + */ +#define CSR_DCSR_NMIP_OFFSET 3 +#define CSR_DCSR_NMIP_LENGTH 1 +#define CSR_DCSR_NMIP 8 +/* + * When set and not in Debug Mode, the hart will only execute a single + * instruction and then enter Debug Mode. See Section~\ref{stepBit} + * for details. + * + * The debugger must not change the value of this bit while the hart + * is running. + */ +#define CSR_DCSR_STEP_OFFSET 2 +#define CSR_DCSR_STEP_LENGTH 1 +#define CSR_DCSR_STEP 4 +/* + * Contains the privilege mode the hart was operating in when Debug + * Mode was entered. The encoding is described in Table + * \ref{tab:privmode}. A debugger can change this value to change + * the hart's privilege mode when exiting Debug Mode. + * + * Not all privilege modes are supported on all harts. If the + * encoding written is not supported or the debugger is not allowed to + * change to it, the hart may change to any supported privilege mode. + */ +#define CSR_DCSR_PRV_OFFSET 0 +#define CSR_DCSR_PRV_LENGTH 2 +#define CSR_DCSR_PRV 3 +#define CSR_DPC 0x7b1 +#define CSR_DPC_DPC_OFFSET 0 +#define CSR_DPC_DPC_LENGTH(DXLEN) DXLEN +#define CSR_DPC_DPC(DXLEN) ((1ULL<<DXLEN) + -1) +#define CSR_DSCRATCH0 0x7b2 +#define CSR_DSCRATCH1 0x7b3 +#define CSR_TSELECT 0x7a0 +#define CSR_TSELECT_INDEX_OFFSET 0 +#define CSR_TSELECT_INDEX_LENGTH(XLEN) XLEN +#define CSR_TSELECT_INDEX(XLEN) ((1ULL<<XLEN) + -1) +#define CSR_TDATA1 0x7a1 +#define CSR_TDATA1_TYPE_OFFSET(XLEN) (XLEN + -4) +#define CSR_TDATA1_TYPE_LENGTH 4 +#define CSR_TDATA1_TYPE(XLEN) (0xf * (1ULL<<(XLEN + -4))) +/* + * none: There is no trigger at this \RcsrTselect. + */ +#define CSR_TDATA1_TYPE_NONE 0 +/* + * legacy: The trigger is a legacy SiFive address match trigger. These + * should not be implemented and aren't further documented here. + */ +#define CSR_TDATA1_TYPE_LEGACY 1 +/* + * mcontrol: The trigger is an address/data match trigger. The remaining bits + * in this register act as described in \RcsrMcontrol. + */ +#define CSR_TDATA1_TYPE_MCONTROL 2 +/* + * icount: The trigger is an instruction count trigger. The remaining bits + * in this register act as described in \RcsrIcount. + */ +#define CSR_TDATA1_TYPE_ICOUNT 3 +/* + * itrigger: The trigger is an interrupt trigger. The remaining bits + * in this register act as described in \RcsrItrigger. + */ +#define CSR_TDATA1_TYPE_ITRIGGER 4 +/* + * etrigger: The trigger is an exception trigger. The remaining bits + * in this register act as described in \RcsrEtrigger. + */ +#define CSR_TDATA1_TYPE_ETRIGGER 5 +/* + * mcontrol6: The trigger is an address/data match trigger. The remaining bits + * in this register act as described in \RcsrMcontrolSix. This is similar + * to a type 2 trigger, but provides additional functionality and + * should be used instead of type 2 in newer implementations. + */ +#define CSR_TDATA1_TYPE_MCONTROL6 6 +/* + * tmexttrigger: The trigger is a trigger source external to the TM. The + * remaining bits in this register act as described in \RcsrTmexttrigger. + */ +#define CSR_TDATA1_TYPE_TMEXTTRIGGER 7 +/* + * custom: These trigger types are available for non-standard use. + */ +#define CSR_TDATA1_TYPE_CUSTOM_LOW 12 +#define CSR_TDATA1_TYPE_CUSTOM_HIGH 14 +/* + * disabled: This trigger is disabled. In this state, \RcsrTdataTwo and + * \RcsrTdataThree can be written with any value that is supported for + * any of the types this trigger implements. The remaining bits in this + * register are ignored. + */ +#define CSR_TDATA1_TYPE_DISABLED 15 +/* + * Other values are reserved for future use. + */ +/* + * If \FcsrTdataOneType is 0, then this bit is hard-wired to 0. + */ +#define CSR_TDATA1_DMODE_OFFSET(XLEN) (XLEN + -5) +#define CSR_TDATA1_DMODE_LENGTH 1 +#define CSR_TDATA1_DMODE(XLEN) (1ULL<<(XLEN + -5)) +/* + * both: Both Debug and M-mode can write the {\tt tdata} registers at the + * selected \RcsrTselect. + */ +#define CSR_TDATA1_DMODE_BOTH 0 +/* + * dmode: Only Debug Mode can write the {\tt tdata} registers at the + * selected \RcsrTselect. Writes from other modes are ignored. + */ +#define CSR_TDATA1_DMODE_DMODE 1 +/* + * This bit is only writable from Debug Mode. + * In ordinary use, external debuggers will always set this bit when + * configuring a trigger. + * When clearing this bit, debuggers should also set the action field + * (whose location depends on \FcsrTdataOneType) to something other + * than 1. + */ +/* + * If \FcsrTdataOneType is 0, then this field is hard-wired to 0. + * + * Trigger-specific data. + */ +#define CSR_TDATA1_DATA_OFFSET 0 +#define CSR_TDATA1_DATA_LENGTH(XLEN) (XLEN + -5) +#define CSR_TDATA1_DATA(XLEN) ((1ULL<<(XLEN + -5)) + -1) +#define CSR_TDATA2 0x7a2 +#define CSR_TDATA2_DATA_OFFSET 0 +#define CSR_TDATA2_DATA_LENGTH(XLEN) XLEN +#define CSR_TDATA2_DATA(XLEN) ((1ULL<<XLEN) + -1) +#define CSR_TDATA3 0x7a3 +#define CSR_TDATA3_DATA_OFFSET 0 +#define CSR_TDATA3_DATA_LENGTH(XLEN) XLEN +#define CSR_TDATA3_DATA(XLEN) ((1ULL<<XLEN) + -1) +#define CSR_TINFO 0x7a4 +/* + * One bit for each possible \FcsrTdataOneType enumerated in \RcsrTdataOne. Bit N + * corresponds to type N. If the bit is set, then that type is + * supported by the currently selected trigger. + * + * If the currently selected trigger doesn't exist, this field + * contains 1. + */ +#define CSR_TINFO_INFO_OFFSET 0 +#define CSR_TINFO_INFO_LENGTH 0x10 +#define CSR_TINFO_INFO 0xffff +#define CSR_TCONTROL 0x7a5 +/* + * M-mode previous trigger enable field. + * + * \FcsrTcontrolMpte and \FcsrTcontrolMte provide one solution to a problem + * regarding triggers with action=0 firing in M-mode trap handlers. See + * Section~\ref{sec:nativetrigger} for more details. + * + * When a breakpoint trap into M-mode is taken, \FcsrTcontrolMpte is set to the value of + * \FcsrTcontrolMte. + */ +#define CSR_TCONTROL_MPTE_OFFSET 7 +#define CSR_TCONTROL_MPTE_LENGTH 1 +#define CSR_TCONTROL_MPTE 0x80 +/* + * M-mode trigger enable field. + */ +#define CSR_TCONTROL_MTE_OFFSET 3 +#define CSR_TCONTROL_MTE_LENGTH 1 +#define CSR_TCONTROL_MTE 8 +/* + * disabled: Triggers with action=0 do not match/fire while the hart is in M-mode. + */ +#define CSR_TCONTROL_MTE_DISABLED 0 +/* + * enabled: Triggers do match/fire while the hart is in M-mode. + */ +#define CSR_TCONTROL_MTE_ENABLED 1 +/* + * When a breakpoint trap into M-mode is taken, \FcsrTcontrolMte is set to 0. When {\tt + * mret} is executed, \FcsrTcontrolMte is set to the value of \FcsrTcontrolMpte. + */ +#define CSR_HCONTEXT 0x6a8 +/* + * Hypervisor mode software can write a context number to this register, + * which can be used to set triggers that only fire in that specific + * context. + * + * An implementation may tie any number of upper bits in this field to + * 0. If the H extension is not implemented, it's recommended to implement + * no more than 6 bits on RV32 and 13 on RV64 (as visible through the + * \RcsrMcontext register). If the H extension is implemented, + * it's recommended to implement no more than 7 bits on RV32 + * and 14 on RV64. + */ +#define CSR_HCONTEXT_HCONTEXT_OFFSET 0 +#define CSR_HCONTEXT_HCONTEXT_LENGTH(XLEN) XLEN +#define CSR_HCONTEXT_HCONTEXT(XLEN) ((1ULL<<XLEN) + -1) +#define CSR_SCONTEXT 0x5a8 +/* + * Supervisor mode software can write a context number to this + * register, which can be used to set triggers that only fire in that + * specific context. + * + * An implementation may tie any number of high bits in this field to + * 0. It's recommended to implement no more than 16 bits on RV32, and + * 34 on RV64. + */ +#define CSR_SCONTEXT_DATA_OFFSET 0 +#define CSR_SCONTEXT_DATA_LENGTH(XLEN) XLEN +#define CSR_SCONTEXT_DATA(XLEN) ((1ULL<<XLEN) + -1) +#define CSR_MCONTEXT 0x7a8 +#define CSR_MSCONTEXT 0x7aa +#define CSR_MCONTROL 0x7a1 +#define CSR_MCONTROL_TYPE_OFFSET(XLEN) (XLEN + -4) +#define CSR_MCONTROL_TYPE_LENGTH 4 +#define CSR_MCONTROL_TYPE(XLEN) (0xf * (1ULL<<(XLEN + -4))) +#define CSR_MCONTROL_DMODE_OFFSET(XLEN) (XLEN + -5) +#define CSR_MCONTROL_DMODE_LENGTH 1 +#define CSR_MCONTROL_DMODE(XLEN) (1ULL<<(XLEN + -5)) +/* + * Specifies the largest naturally aligned powers-of-two (NAPOT) range + * supported by the hardware when \FcsrMcontrolMatch is 1. The value is the + * logarithm base 2 of the number of bytes in that range. + * A value of 0 indicates \FcsrMcontrolMatch 1 is not supported. + * A value of 63 corresponds to the maximum NAPOT range, which is + * $2^{63}$ bytes in size. + */ +#define CSR_MCONTROL_MASKMAX_OFFSET(XLEN) (XLEN + -0xb) +#define CSR_MCONTROL_MASKMAX_LENGTH 6 +#define CSR_MCONTROL_MASKMAX(XLEN) (0x3f * (1ULL<<(XLEN + -0xb))) +/* + * This field only exists when XLEN is at least 64. + * It contains the 2 high bits of the access size. The low bits + * come from \FcsrMcontrolSizelo. See \FcsrMcontrolSizelo for how this + * is used. + */ +#define CSR_MCONTROL_SIZEHI_OFFSET 0x15 +#define CSR_MCONTROL_SIZEHI_LENGTH 2 +#define CSR_MCONTROL_SIZEHI 0x600000 +/* + * If this bit is implemented then it must become set when this + * trigger fires and may become set when this trigger matches. + * The trigger's user can set or clear it at any + * time. It is used to determine which + * trigger(s) matched. If the bit is not implemented, it is always 0 + * and writing it has no effect. + */ +#define CSR_MCONTROL_HIT_OFFSET 0x14 +#define CSR_MCONTROL_HIT_LENGTH 1 +#define CSR_MCONTROL_HIT 0x100000 +/* + * This bit determines the contents of the XLEN-bit compare values. + */ +#define CSR_MCONTROL_SELECT_OFFSET 0x13 +#define CSR_MCONTROL_SELECT_LENGTH 1 +#define CSR_MCONTROL_SELECT 0x80000 +/* + * address: There is at least one compare value and it contains the lowest + * virtual address of the access. + * It is recommended that there are additional compare values for + * the other accessed virtual addresses. + * (E.g. on a 32-bit read from 0x4000, the lowest address is 0x4000 + * and the other addresses are 0x4001, 0x4002, and 0x4003.) + */ +#define CSR_MCONTROL_SELECT_ADDRESS 0 +/* + * data: There is exactly one compare value and it contains the data + * value loaded or stored, or the instruction executed. + * Any bits beyond the size of the data access will contain 0. + */ +#define CSR_MCONTROL_SELECT_DATA 1 +#define CSR_MCONTROL_TIMING_OFFSET 0x12 +#define CSR_MCONTROL_TIMING_LENGTH 1 +#define CSR_MCONTROL_TIMING 0x40000 +/* + * before: The action for this trigger will be taken just before the + * instruction that triggered it is committed, but after all preceding + * instructions are committed. \Rxepc or \RcsrDpc (depending + * on \FcsrMcontrolAction) must be set to the virtual address of the + * instruction that matched. + * + * If this is combined with \FcsrMcontrolLoad and + * \FcsrMcontrolSelect=1 then a memory access will be + * performed (including any side effects of performing such an access) even + * though the load will not update its destination register. Debuggers + * should consider this when setting such breakpoints on, for example, + * memory-mapped I/O addresses. + */ +#define CSR_MCONTROL_TIMING_BEFORE 0 +/* + * after: The action for this trigger will be taken after the instruction + * that triggered it is committed. It should be taken before the next + * instruction is committed, but it is better to implement triggers imprecisely + * than to not implement them at all. \Rxepc or + * \RcsrDpc (depending on \FcsrMcontrolAction) must be set to + * the virtual address of the next instruction that must be executed to + * preserve the program flow. + */ +#define CSR_MCONTROL_TIMING_AFTER 1 +/* + * Most hardware will only implement one timing or the other, possibly + * dependent on \FcsrMcontrolSelect, \FcsrMcontrolExecute, + * \FcsrMcontrolLoad, and \FcsrMcontrolStore. This bit + * primarily exists for the hardware to communicate to the debugger + * what will happen. Hardware may implement the bit fully writable, in + * which case the debugger has a little more control. + * + * Data load triggers with \FcsrMcontrolTiming of 0 will result in the same load + * happening again when the debugger lets the hart run. For data load + * triggers, debuggers must first attempt to set the breakpoint with + * \FcsrMcontrolTiming of 1. + * + * If a trigger with \FcsrMcontrolTiming of 0 matches, it is + * implementation-dependent whether that prevents a trigger with + * \FcsrMcontrolTiming of 1 matching as well. + */ +/* + * This field contains the 2 low bits of the access size. The high bits come + * from \FcsrMcontrolSizehi. The combined value is interpreted as follows: + */ +#define CSR_MCONTROL_SIZELO_OFFSET 0x10 +#define CSR_MCONTROL_SIZELO_LENGTH 2 +#define CSR_MCONTROL_SIZELO 0x30000 +/* + * any: The trigger will attempt to match against an access of any size. + * The behavior is only well-defined if $|select|=0$, or if the access + * size is XLEN. + */ +#define CSR_MCONTROL_SIZELO_ANY 0 +/* + * 8bit: The trigger will only match against 8-bit memory accesses. + */ +#define CSR_MCONTROL_SIZELO_8BIT 1 +/* + * 16bit: The trigger will only match against 16-bit memory accesses or + * execution of 16-bit instructions. + */ +#define CSR_MCONTROL_SIZELO_16BIT 2 +/* + * 32bit: The trigger will only match against 32-bit memory accesses or + * execution of 32-bit instructions. + */ +#define CSR_MCONTROL_SIZELO_32BIT 3 +/* + * 48bit: The trigger will only match against execution of 48-bit instructions. + */ +#define CSR_MCONTROL_SIZELO_48BIT 4 +/* + * 64bit: The trigger will only match against 64-bit memory accesses or + * execution of 64-bit instructions. + */ +#define CSR_MCONTROL_SIZELO_64BIT 5 +/* + * 80bit: The trigger will only match against execution of 80-bit instructions. + */ +#define CSR_MCONTROL_SIZELO_80BIT 6 +/* + * 96bit: The trigger will only match against execution of 96-bit instructions. + */ +#define CSR_MCONTROL_SIZELO_96BIT 7 +/* + * 112bit: The trigger will only match against execution of 112-bit instructions. + */ +#define CSR_MCONTROL_SIZELO_112BIT 8 +/* + * 128bit: The trigger will only match against 128-bit memory accesses or + * execution of 128-bit instructions. + */ +#define CSR_MCONTROL_SIZELO_128BIT 9 +/* + * An implementation must support the value of 0, but all other values + * are optional. When an implementation supports address triggers + * (\FcsrMcontrolSelect=0), it is recommended that those triggers + * support every access size that the hart supports, as well as for + * every instruction size that the hart supports. + * + * Implementations such as RV32D or RV64V are able to perform loads + * and stores that are wider than XLEN. Custom extensions may also + * support instructions that are wider than XLEN. Because + * \RcsrTdataTwo is of size XLEN, there is a known limitation that + * data value triggers (\FcsrMcontrolSelect=1) can only be supported + * for access sizes up to XLEN bits. When an implementation supports + * data value triggers (\FcsrMcontrolSelect=1), it is recommended + * that those triggers support every access size up to XLEN that the + * hart supports, as well as for every instruction length up to XLEN + * that the hart supports. + */ +/* + * The action to take when the trigger fires. The values are explained + * in Table~\ref{tab:action}. + */ +#define CSR_MCONTROL_ACTION_OFFSET 0xc +#define CSR_MCONTROL_ACTION_LENGTH 4 +#define CSR_MCONTROL_ACTION 0xf000 +/* + * breakpoint: + */ +#define CSR_MCONTROL_ACTION_BREAKPOINT 0 +/* + * debug mode: + */ +#define CSR_MCONTROL_ACTION_DEBUG_MODE 1 +/* + * trace on: + */ +#define CSR_MCONTROL_ACTION_TRACE_ON 2 +/* + * trace off: + */ +#define CSR_MCONTROL_ACTION_TRACE_OFF 3 +/* + * trace notify: + */ +#define CSR_MCONTROL_ACTION_TRACE_NOTIFY 4 +/* + * external0: + */ +#define CSR_MCONTROL_ACTION_EXTERNAL0 8 +/* + * external1: + */ +#define CSR_MCONTROL_ACTION_EXTERNAL1 9 +#define CSR_MCONTROL_CHAIN_OFFSET 0xb +#define CSR_MCONTROL_CHAIN_LENGTH 1 +#define CSR_MCONTROL_CHAIN 0x800 +/* + * disabled: When this trigger matches, the configured action is taken. + */ +#define CSR_MCONTROL_CHAIN_DISABLED 0 +/* + * enabled: While this trigger does not match, it prevents the trigger with + * the next index from matching. + */ +#define CSR_MCONTROL_CHAIN_ENABLED 1 +/* + * A trigger chain starts on the first trigger with $|chain|=1$ after + * a trigger with $|chain|=0$, or simply on the first trigger if that + * has $|chain|=1$. It ends on the first trigger after that which has + * $|chain|=0$. This final trigger is part of the chain. The action + * on all but the final trigger is ignored. The action on that final + * trigger will be taken if and only if all the triggers in the chain + * match at the same time. + * + * Debuggers should not terminate a chain with a trigger with a + * different type. It is undefined when exactly such a chain fires. + * + * Because \FcsrMcontrolChain affects the next trigger, hardware must zero it in + * writes to \RcsrMcontrol that set \FcsrTdataOneDmode to 0 if the next trigger has + * \FcsrTdataOneDmode of 1. + * In addition hardware should ignore writes to \RcsrMcontrol that set + * \FcsrTdataOneDmode to 1 if the previous trigger has both \FcsrTdataOneDmode of 0 and + * \FcsrMcontrolChain of 1. Debuggers must avoid the latter case by checking + * \FcsrMcontrolChain on the previous trigger if they're writing \RcsrMcontrol. + * + * Implementations that wish to limit the maximum length of a trigger + * chain (eg. to meet timing requirements) may do so by zeroing + * \FcsrMcontrolChain in writes to \RcsrMcontrol that would make the chain too long. + */ +#define CSR_MCONTROL_MATCH_OFFSET 7 +#define CSR_MCONTROL_MATCH_LENGTH 4 +#define CSR_MCONTROL_MATCH 0x780 +/* + * equal: Matches when any compare value equals \RcsrTdataTwo. + */ +#define CSR_MCONTROL_MATCH_EQUAL 0 +/* + * napot: Matches when the top $M$ bits of any compare value match the top + * $M$ bits of \RcsrTdataTwo. + * $M$ is $|XLEN|-1$ minus the index of the least-significant + * bit containing 0 in \RcsrTdataTwo. Debuggers should only write values + * to \RcsrTdataTwo such that $M + $\FcsrMcontrolMaskmax$ \geq |XLEN|$ + * and $M\gt0$ , otherwise it's undefined on what conditions the + * trigger will match. + */ +#define CSR_MCONTROL_MATCH_NAPOT 1 +/* + * ge: Matches when any compare value is greater than (unsigned) or + * equal to \RcsrTdataTwo. + */ +#define CSR_MCONTROL_MATCH_GE 2 +/* + * lt: Matches when any compare value is less than (unsigned) + * \RcsrTdataTwo. + */ +#define CSR_MCONTROL_MATCH_LT 3 +/* + * mask low: Matches when $\frac{|XLEN|}{2}-1$:$0$ of any compare value + * equals $\frac{|XLEN|}{2}-1$:$0$ of \RcsrTdataTwo after + * $\frac{|XLEN|}{2}-1$:$0$ of the compare value is ANDed with + * $|XLEN|-1$:$\frac{|XLEN|}{2}$ of \RcsrTdataTwo. + */ +#define CSR_MCONTROL_MATCH_MASK_LOW 4 +/* + * mask high: Matches when $|XLEN|-1$:$\frac{|XLEN|}{2}$ of any compare + * value equals $\frac{|XLEN|}{2}-1$:$0$ of \RcsrTdataTwo after + * $|XLEN|-1$:$\frac{|XLEN|}{2}$ of the compare value is ANDed with + * $|XLEN|-1$:$\frac{|XLEN|}{2}$ of \RcsrTdataTwo. + */ +#define CSR_MCONTROL_MATCH_MASK_HIGH 5 +/* + * not equal: Matches when \FcsrMcontrolMatch$=0$ would not match. + */ +#define CSR_MCONTROL_MATCH_NOT_EQUAL 8 +/* + * not napot: Matches when \FcsrMcontrolMatch$=1$ would not match. + */ +#define CSR_MCONTROL_MATCH_NOT_NAPOT 9 +/* + * not mask low: Matches when \FcsrMcontrolMatch$=4$ would not match. + */ +#define CSR_MCONTROL_MATCH_NOT_MASK_LOW 12 +/* + * not mask high: Matches when \FcsrMcontrolMatch$=5$ would not match. + */ +#define CSR_MCONTROL_MATCH_NOT_MASK_HIGH 13 +/* + * Other values are reserved for future use. + * + * All comparisons only look at the lower XLEN (in the current mode) + * bits of the compare values and of \RcsrTdataTwo. + * When \FcsrMcontrolSelect=1 and access size is N, this is further + * reduced, and comparisons only look at the lower N bits of the + * compare values and of \RcsrTdataTwo. + */ +/* + * When set, enable this trigger in M-mode. + */ +#define CSR_MCONTROL_M_OFFSET 6 +#define CSR_MCONTROL_M_LENGTH 1 +#define CSR_MCONTROL_M 0x40 +/* + * When set, enable this trigger in S/HS-mode. + * This bit is hard-wired to 0 if the hart does not support + * S-mode. + */ +#define CSR_MCONTROL_S_OFFSET 4 +#define CSR_MCONTROL_S_LENGTH 1 +#define CSR_MCONTROL_S 0x10 +/* + * When set, enable this trigger in U-mode. + * This bit is hard-wired to 0 if the hart does not support + * U-mode. + */ +#define CSR_MCONTROL_U_OFFSET 3 +#define CSR_MCONTROL_U_LENGTH 1 +#define CSR_MCONTROL_U 8 +/* + * When set, the trigger fires on the virtual address or opcode of an + * instruction that is executed. + */ +#define CSR_MCONTROL_EXECUTE_OFFSET 2 +#define CSR_MCONTROL_EXECUTE_LENGTH 1 +#define CSR_MCONTROL_EXECUTE 4 +/* + * When set, the trigger fires on the virtual address or data of any + * store. + */ +#define CSR_MCONTROL_STORE_OFFSET 1 +#define CSR_MCONTROL_STORE_LENGTH 1 +#define CSR_MCONTROL_STORE 2 +/* + * When set, the trigger fires on the virtual address or data of any + * load. + */ +#define CSR_MCONTROL_LOAD_OFFSET 0 +#define CSR_MCONTROL_LOAD_LENGTH 1 +#define CSR_MCONTROL_LOAD 1 +#define CSR_MCONTROL6 0x7a1 +#define CSR_MCONTROL6_TYPE_OFFSET(XLEN) (XLEN + -4) +#define CSR_MCONTROL6_TYPE_LENGTH 4 +#define CSR_MCONTROL6_TYPE(XLEN) (0xf * (1ULL<<(XLEN + -4))) +#define CSR_MCONTROL6_DMODE_OFFSET(XLEN) (XLEN + -5) +#define CSR_MCONTROL6_DMODE_LENGTH 1 +#define CSR_MCONTROL6_DMODE(XLEN) (1ULL<<(XLEN + -5)) +/* + * When set, enable this trigger in VS-mode. + * This bit is hard-wired to 0 if the hart does not support + * virtualization mode. + */ +#define CSR_MCONTROL6_VS_OFFSET 0x18 +#define CSR_MCONTROL6_VS_LENGTH 1 +#define CSR_MCONTROL6_VS 0x1000000 +/* + * When set, enable this trigger in VU-mode. + * This bit is hard-wired to 0 if the hart does not support + * virtualization mode. + */ +#define CSR_MCONTROL6_VU_OFFSET 0x17 +#define CSR_MCONTROL6_VU_LENGTH 1 +#define CSR_MCONTROL6_VU 0x800000 +/* + * If this bit is implemented then it must become set when this + * trigger fires and may become set when this trigger matches. + * The trigger's user can set or clear it at any + * time. It is used to determine which + * trigger(s) matched. If the bit is not implemented, it is always 0 + * and writing it has no effect. + */ +#define CSR_MCONTROL6_HIT_OFFSET 0x16 +#define CSR_MCONTROL6_HIT_LENGTH 1 +#define CSR_MCONTROL6_HIT 0x400000 +/* + * This bit determines the contents of the XLEN-bit compare values. + */ +#define CSR_MCONTROL6_SELECT_OFFSET 0x15 +#define CSR_MCONTROL6_SELECT_LENGTH 1 +#define CSR_MCONTROL6_SELECT 0x200000 +/* + * address: There is at least one compare value and it contains the lowest + * virtual address of the access. + * In addition, it is recommended that there are additional compare + * values for the other accessed virtual addresses match. + * (E.g. on a 32-bit read from 0x4000, the lowest address is 0x4000 + * and the other addresses are 0x4001, 0x4002, and 0x4003.) + */ +#define CSR_MCONTROL6_SELECT_ADDRESS 0 +/* + * data: There is exactly one compare value and it contains the data + * value loaded or stored, or the instruction executed. + * Any bits beyond the size of the data access will contain 0. + */ +#define CSR_MCONTROL6_SELECT_DATA 1 +#define CSR_MCONTROL6_TIMING_OFFSET 0x14 +#define CSR_MCONTROL6_TIMING_LENGTH 1 +#define CSR_MCONTROL6_TIMING 0x100000 +/* + * before: The action for this trigger will be taken just before the + * instruction that triggered it is committed, but after all preceding + * instructions are committed. \Rxepc or \RcsrDpc (depending + * on \FcsrMcontrolSixAction) must be set to the virtual address of the + * instruction that matched. + * + * If this is combined with \FcsrMcontrolSixLoad and + * \FcsrMcontrolSixSelect=1 then a memory access will be + * performed (including any side effects of performing such an access) even + * though the load will not update its destination register. Debuggers + * should consider this when setting such breakpoints on, for example, + * memory-mapped I/O addresses. + */ +#define CSR_MCONTROL6_TIMING_BEFORE 0 +/* + * after: The action for this trigger will be taken after the instruction + * that triggered it is committed. It should be taken before the next + * instruction is committed, but it is better to implement triggers imprecisely + * than to not implement them at all. \Rxepc or + * \RcsrDpc (depending on \FcsrMcontrolSixAction) must be set to + * the virtual address of the next instruction that must be executed to + * preserve the program flow. + */ +#define CSR_MCONTROL6_TIMING_AFTER 1 +/* + * Most hardware will only implement one timing or the other, possibly + * dependent on \FcsrMcontrolSixSelect, \FcsrMcontrolSixExecute, + * \FcsrMcontrolSixLoad, and \FcsrMcontrolSixStore. This bit + * primarily exists for the hardware to communicate to the debugger + * what will happen. Hardware may implement the bit fully writable, in + * which case the debugger has a little more control. + * + * Data load triggers with \FcsrMcontrolSixTiming of 0 will result in the same load + * happening again when the debugger lets the hart run. For data load + * triggers, debuggers must first attempt to set the breakpoint with + * \FcsrMcontrolSixTiming of 1. + * + * If a trigger with \FcsrMcontrolSixTiming of 0 matches, it is + * implementation-dependent whether that prevents a trigger with + * \FcsrMcontrolSixTiming of 1 matching as well. + */ +#define CSR_MCONTROL6_SIZE_OFFSET 0x10 +#define CSR_MCONTROL6_SIZE_LENGTH 4 +#define CSR_MCONTROL6_SIZE 0xf0000 +/* + * any: The trigger will attempt to match against an access of any size. + * The behavior is only well-defined if $|select|=0$, or if the access + * size is XLEN. + */ +#define CSR_MCONTROL6_SIZE_ANY 0 +/* + * 8bit: The trigger will only match against 8-bit memory accesses. + */ +#define CSR_MCONTROL6_SIZE_8BIT 1 +/* + * 16bit: The trigger will only match against 16-bit memory accesses or + * execution of 16-bit instructions. + */ +#define CSR_MCONTROL6_SIZE_16BIT 2 +/* + * 32bit: The trigger will only match against 32-bit memory accesses or + * execution of 32-bit instructions. + */ +#define CSR_MCONTROL6_SIZE_32BIT 3 +/* + * 48bit: The trigger will only match against execution of 48-bit instructions. + */ +#define CSR_MCONTROL6_SIZE_48BIT 4 +/* + * 64bit: The trigger will only match against 64-bit memory accesses or + * execution of 64-bit instructions. + */ +#define CSR_MCONTROL6_SIZE_64BIT 5 +/* + * 80bit: The trigger will only match against execution of 80-bit instructions. + */ +#define CSR_MCONTROL6_SIZE_80BIT 6 +/* + * 96bit: The trigger will only match against execution of 96-bit instructions. + */ +#define CSR_MCONTROL6_SIZE_96BIT 7 +/* + * 112bit: The trigger will only match against execution of 112-bit instructions. + */ +#define CSR_MCONTROL6_SIZE_112BIT 8 +/* + * 128bit: The trigger will only match against 128-bit memory accesses or + * execution of 128-bit instructions. + */ +#define CSR_MCONTROL6_SIZE_128BIT 9 +/* + * An implementation must support the value of 0, but all other values + * are optional. When an implementation supports address triggers + * (\FcsrMcontrolSixSelect=0), it is recommended that those triggers + * support every access size that the hart supports, as well as for + * every instruction size that the hart supports. + * + * Implementations such as RV32D or RV64V are able to perform loads + * and stores that are wider than XLEN. Custom extensions may also + * support instructions that are wider than XLEN. Because + * \RcsrTdataTwo is of size XLEN, there is a known limitation that + * data value triggers (\FcsrMcontrolSixSelect=1) can only be supported + * for access sizes up to XLEN bits. When an implementation supports + * data value triggers (\FcsrMcontrolSixSelect=1), it is recommended + * that those triggers support every access size up to XLEN that the + * hart supports, as well as for every instruction length up to XLEN + * that the hart supports. + */ +/* + * The action to take when the trigger fires. The values are explained + * in Table~\ref{tab:action}. + */ +#define CSR_MCONTROL6_ACTION_OFFSET 0xc +#define CSR_MCONTROL6_ACTION_LENGTH 4 +#define CSR_MCONTROL6_ACTION 0xf000 +/* + * breakpoint: + */ +#define CSR_MCONTROL6_ACTION_BREAKPOINT 0 +/* + * debug mode: + */ +#define CSR_MCONTROL6_ACTION_DEBUG_MODE 1 +/* + * trace on: + */ +#define CSR_MCONTROL6_ACTION_TRACE_ON 2 +/* + * trace off: + */ +#define CSR_MCONTROL6_ACTION_TRACE_OFF 3 +/* + * trace notify: + */ +#define CSR_MCONTROL6_ACTION_TRACE_NOTIFY 4 +/* + * external0: + */ +#define CSR_MCONTROL6_ACTION_EXTERNAL0 8 +/* + * external1: + */ +#define CSR_MCONTROL6_ACTION_EXTERNAL1 9 +#define CSR_MCONTROL6_CHAIN_OFFSET 0xb +#define CSR_MCONTROL6_CHAIN_LENGTH 1 +#define CSR_MCONTROL6_CHAIN 0x800 +/* + * disabled: When this trigger matches, the configured action is taken. + */ +#define CSR_MCONTROL6_CHAIN_DISABLED 0 +/* + * enabled: While this trigger does not match, it prevents the trigger with + * the next index from matching. + */ +#define CSR_MCONTROL6_CHAIN_ENABLED 1 +/* + * A trigger chain starts on the first trigger with $|chain|=1$ after + * a trigger with $|chain|=0$, or simply on the first trigger if that + * has $|chain|=1$. It ends on the first trigger after that which has + * $|chain|=0$. This final trigger is part of the chain. The action + * on all but the final trigger is ignored. The action on that final + * trigger will be taken if and only if all the triggers in the chain + * match at the same time. + * + * Debuggers should not terminate a chain with a trigger with a + * different type. It is undefined when exactly such a chain fires. + * + * Because \FcsrMcontrolSixChain affects the next trigger, hardware must zero it in + * writes to \RcsrMcontrolSix that set \FcsrTdataOneDmode to 0 if the next trigger has + * \FcsrTdataOneDmode of 1. + * In addition hardware should ignore writes to \RcsrMcontrolSix that set + * \FcsrTdataOneDmode to 1 if the previous trigger has both \FcsrTdataOneDmode of 0 and + * \FcsrMcontrolSixChain of 1. Debuggers must avoid the latter case by checking + * \FcsrMcontrolSixChain on the previous trigger if they're writing \RcsrMcontrolSix. + * + * Implementations that wish to limit the maximum length of a trigger + * chain (eg. to meet timing requirements) may do so by zeroing + * \FcsrMcontrolSixChain in writes to \RcsrMcontrolSix that would make the chain too long. + */ +#define CSR_MCONTROL6_MATCH_OFFSET 7 +#define CSR_MCONTROL6_MATCH_LENGTH 4 +#define CSR_MCONTROL6_MATCH 0x780 +/* + * equal: Matches when any compare value equals \RcsrTdataTwo. + */ +#define CSR_MCONTROL6_MATCH_EQUAL 0 +/* + * napot: Matches when the top $M$ bits of any compare value match the top + * $M$ bits of \RcsrTdataTwo. + * $M$ is $|XLEN|-1$ minus the index of the least-significant bit + * containing 0 in \RcsrTdataTwo. + * \RcsrTdataTwo is WARL and if bits $|maskmax6|-1$:0 are written with all + * ones then bit $|maskmax6|-1$ will be set to 0 while the values of bits $|maskmax6|-2$:0 + * are \unspecified. + * Legal values for \RcsrTdataTwo require $M + |maskmax6| \geq |XLEN|$ and $M\gt0$. + * See above for how to determine maskmax6. + */ +#define CSR_MCONTROL6_MATCH_NAPOT 1 +/* + * ge: Matches when any compare value is greater than (unsigned) or + * equal to \RcsrTdataTwo. + */ +#define CSR_MCONTROL6_MATCH_GE 2 +/* + * lt: Matches when any compare value is less than (unsigned) + * \RcsrTdataTwo. + */ +#define CSR_MCONTROL6_MATCH_LT 3 +/* + * mask low: Matches when $\frac{|XLEN|}{2}-1$:$0$ of any compare value + * equals $\frac{|XLEN|}{2}-1$:$0$ of \RcsrTdataTwo after + * $\frac{|XLEN|}{2}-1$:$0$ of the compare value is ANDed with + * $|XLEN|-1$:$\frac{|XLEN|}{2}$ of \RcsrTdataTwo. + */ +#define CSR_MCONTROL6_MATCH_MASK_LOW 4 +/* + * mask high: Matches when $|XLEN|-1$:$\frac{|XLEN|}{2}$ of any compare + * value equals $\frac{|XLEN|}{2}-1$:$0$ of \RcsrTdataTwo after + * $|XLEN|-1$:$\frac{|XLEN|}{2}$ of the compare value is ANDed with + * $|XLEN|-1$:$\frac{|XLEN|}{2}$ of \RcsrTdataTwo. + */ +#define CSR_MCONTROL6_MATCH_MASK_HIGH 5 +/* + * not equal: Matches when \FcsrMcontrolSixMatch$=0$ would not match. + */ +#define CSR_MCONTROL6_MATCH_NOT_EQUAL 8 +/* + * not napot: Matches when \FcsrMcontrolSixMatch$=1$ would not match. + */ +#define CSR_MCONTROL6_MATCH_NOT_NAPOT 9 +/* + * not mask low: Matches when \FcsrMcontrolSixMatch$=4$ would not match. + */ +#define CSR_MCONTROL6_MATCH_NOT_MASK_LOW 12 +/* + * not mask high: Matches when \FcsrMcontrolSixMatch$=5$ would not match. + */ +#define CSR_MCONTROL6_MATCH_NOT_MASK_HIGH 13 +/* + * Other values are reserved for future use. + * + * All comparisons only look at the lower XLEN (in the current mode) + * bits of the compare values and of \RcsrTdataTwo. + * When \FcsrMcontrolSelect=1 and access size is N, this is further + * reduced, and comparisons only look at the lower N bits of the + * compare values and of \RcsrTdataTwo. + */ +/* + * When set, enable this trigger in M-mode. + */ +#define CSR_MCONTROL6_M_OFFSET 6 +#define CSR_MCONTROL6_M_LENGTH 1 +#define CSR_MCONTROL6_M 0x40 +/* + * When set, enable this trigger in S/HS-mode. + * This bit is hard-wired to 0 if the hart does not support + * S-mode. + */ +#define CSR_MCONTROL6_S_OFFSET 4 +#define CSR_MCONTROL6_S_LENGTH 1 +#define CSR_MCONTROL6_S 0x10 +/* + * When set, enable this trigger in U-mode. + * This bit is hard-wired to 0 if the hart does not support + * U-mode. + */ +#define CSR_MCONTROL6_U_OFFSET 3 +#define CSR_MCONTROL6_U_LENGTH 1 +#define CSR_MCONTROL6_U 8 +/* + * When set, the trigger fires on the virtual address or opcode of an + * instruction that is executed. + */ +#define CSR_MCONTROL6_EXECUTE_OFFSET 2 +#define CSR_MCONTROL6_EXECUTE_LENGTH 1 +#define CSR_MCONTROL6_EXECUTE 4 +/* + * When set, the trigger fires on the virtual address or data of any + * store. + */ +#define CSR_MCONTROL6_STORE_OFFSET 1 +#define CSR_MCONTROL6_STORE_LENGTH 1 +#define CSR_MCONTROL6_STORE 2 +/* + * When set, the trigger fires on the virtual address or data of any + * load. + */ +#define CSR_MCONTROL6_LOAD_OFFSET 0 +#define CSR_MCONTROL6_LOAD_LENGTH 1 +#define CSR_MCONTROL6_LOAD 1 +#define CSR_ICOUNT 0x7a1 +#define CSR_ICOUNT_TYPE_OFFSET(XLEN) (XLEN + -4) +#define CSR_ICOUNT_TYPE_LENGTH 4 +#define CSR_ICOUNT_TYPE(XLEN) (0xf * (1ULL<<(XLEN + -4))) +#define CSR_ICOUNT_DMODE_OFFSET(XLEN) (XLEN + -5) +#define CSR_ICOUNT_DMODE_LENGTH 1 +#define CSR_ICOUNT_DMODE(XLEN) (1ULL<<(XLEN + -5)) +/* + * When set, enable this trigger in VS-mode. + * This bit is hard-wired to 0 if the hart does not support + * virtualization mode. + */ +#define CSR_ICOUNT_VS_OFFSET 0x1a +#define CSR_ICOUNT_VS_LENGTH 1 +#define CSR_ICOUNT_VS 0x4000000 +/* + * When set, enable this trigger in VU-mode. + * This bit is hard-wired to 0 if the hart does not support + * virtualization mode. + */ +#define CSR_ICOUNT_VU_OFFSET 0x19 +#define CSR_ICOUNT_VU_LENGTH 1 +#define CSR_ICOUNT_VU 0x2000000 +/* + * If this bit is implemented, the hardware sets it when this + * trigger fires. The trigger's user can set or clear it at any + * time. It is used to determine which + * trigger(s) fires. If the bit is not implemented, it is always 0 + * and writing it has no effect. + */ +#define CSR_ICOUNT_HIT_OFFSET 0x18 +#define CSR_ICOUNT_HIT_LENGTH 1 +#define CSR_ICOUNT_HIT 0x1000000 +/* + * The trigger will generally fire after \FcsrIcountCount instructions + * in enabled modes have been executed. See above for the precise behavior. + */ +#define CSR_ICOUNT_COUNT_OFFSET 0xa +#define CSR_ICOUNT_COUNT_LENGTH 0xe +#define CSR_ICOUNT_COUNT 0xfffc00 +/* + * When set, enable this trigger in M-mode. + */ +#define CSR_ICOUNT_M_OFFSET 9 +#define CSR_ICOUNT_M_LENGTH 1 +#define CSR_ICOUNT_M 0x200 +/* + * This bit becomes set when \FcsrIcountCount is decremented from 1 + * to 0. It is cleared when the trigger fires, which will happen just + * before executing the next instruction in one of the enabled modes. + */ +#define CSR_ICOUNT_PENDING_OFFSET 8 +#define CSR_ICOUNT_PENDING_LENGTH 1 +#define CSR_ICOUNT_PENDING 0x100 +/* + * When set, enable this trigger in S/HS-mode. + * This bit is hard-wired to 0 if the hart does not support + * S-mode. + */ +#define CSR_ICOUNT_S_OFFSET 7 +#define CSR_ICOUNT_S_LENGTH 1 +#define CSR_ICOUNT_S 0x80 +/* + * When set, enable this trigger in U-mode. + * This bit is hard-wired to 0 if the hart does not support + * U-mode. + */ +#define CSR_ICOUNT_U_OFFSET 6 +#define CSR_ICOUNT_U_LENGTH 1 +#define CSR_ICOUNT_U 0x40 +/* + * The action to take when the trigger fires. The values are explained + * in Table~\ref{tab:action}. + */ +#define CSR_ICOUNT_ACTION_OFFSET 0 +#define CSR_ICOUNT_ACTION_LENGTH 6 +#define CSR_ICOUNT_ACTION 0x3f +/* + * breakpoint: + */ +#define CSR_ICOUNT_ACTION_BREAKPOINT 0 +/* + * debug mode: + */ +#define CSR_ICOUNT_ACTION_DEBUG_MODE 1 +/* + * trace on: + */ +#define CSR_ICOUNT_ACTION_TRACE_ON 2 +/* + * trace off: + */ +#define CSR_ICOUNT_ACTION_TRACE_OFF 3 +/* + * trace notify: + */ +#define CSR_ICOUNT_ACTION_TRACE_NOTIFY 4 +/* + * external0: + */ +#define CSR_ICOUNT_ACTION_EXTERNAL0 8 +/* + * external1: + */ +#define CSR_ICOUNT_ACTION_EXTERNAL1 9 +#define CSR_ITRIGGER 0x7a1 +#define CSR_ITRIGGER_TYPE_OFFSET(XLEN) (XLEN + -4) +#define CSR_ITRIGGER_TYPE_LENGTH 4 +#define CSR_ITRIGGER_TYPE(XLEN) (0xf * (1ULL<<(XLEN + -4))) +#define CSR_ITRIGGER_DMODE_OFFSET(XLEN) (XLEN + -5) +#define CSR_ITRIGGER_DMODE_LENGTH 1 +#define CSR_ITRIGGER_DMODE(XLEN) (1ULL<<(XLEN + -5)) +/* + * If this bit is implemented, the hardware sets it when this + * trigger matches. The trigger's user can set or clear it at any + * time. It is used to determine which + * trigger(s) matched. If the bit is not implemented, it is always 0 + * and writing it has no effect. + */ +#define CSR_ITRIGGER_HIT_OFFSET(XLEN) (XLEN + -6) +#define CSR_ITRIGGER_HIT_LENGTH 1 +#define CSR_ITRIGGER_HIT(XLEN) (1ULL<<(XLEN + -6)) +/* + * When set, enable this trigger for interrupts that are taken from VS + * mode. + * This bit is hard-wired to 0 if the hart does not support + * virtualization mode. + */ +#define CSR_ITRIGGER_VS_OFFSET 0xc +#define CSR_ITRIGGER_VS_LENGTH 1 +#define CSR_ITRIGGER_VS 0x1000 +/* + * When set, enable this trigger for interrupts that are taken from VU + * mode. + * This bit is hard-wired to 0 if the hart does not support + * virtualization mode. + */ +#define CSR_ITRIGGER_VU_OFFSET 0xb +#define CSR_ITRIGGER_VU_LENGTH 1 +#define CSR_ITRIGGER_VU 0x800 +/* + * When set, non-maskable interrupts cause this + * trigger to fire if the trigger is enabled for the current mode. + */ +#define CSR_ITRIGGER_NMI_OFFSET 0xa +#define CSR_ITRIGGER_NMI_LENGTH 1 +#define CSR_ITRIGGER_NMI 0x400 +/* + * When set, enable this trigger for interrupts that are taken from M + * mode. + */ +#define CSR_ITRIGGER_M_OFFSET 9 +#define CSR_ITRIGGER_M_LENGTH 1 +#define CSR_ITRIGGER_M 0x200 +/* + * When set, enable this trigger for interrupts that are taken from S/HS + * mode. + * This bit is hard-wired to 0 if the hart does not support + * S-mode. + */ +#define CSR_ITRIGGER_S_OFFSET 7 +#define CSR_ITRIGGER_S_LENGTH 1 +#define CSR_ITRIGGER_S 0x80 +/* + * When set, enable this trigger for interrupts that are taken from U + * mode. + * This bit is hard-wired to 0 if the hart does not support + * U-mode. + */ +#define CSR_ITRIGGER_U_OFFSET 6 +#define CSR_ITRIGGER_U_LENGTH 1 +#define CSR_ITRIGGER_U 0x40 +/* + * The action to take when the trigger fires. The values are explained + * in Table~\ref{tab:action}. + */ +#define CSR_ITRIGGER_ACTION_OFFSET 0 +#define CSR_ITRIGGER_ACTION_LENGTH 6 +#define CSR_ITRIGGER_ACTION 0x3f +/* + * breakpoint: + */ +#define CSR_ITRIGGER_ACTION_BREAKPOINT 0 +/* + * debug mode: + */ +#define CSR_ITRIGGER_ACTION_DEBUG_MODE 1 +/* + * trace on: + */ +#define CSR_ITRIGGER_ACTION_TRACE_ON 2 +/* + * trace off: + */ +#define CSR_ITRIGGER_ACTION_TRACE_OFF 3 +/* + * trace notify: + */ +#define CSR_ITRIGGER_ACTION_TRACE_NOTIFY 4 +/* + * external0: + */ +#define CSR_ITRIGGER_ACTION_EXTERNAL0 8 +/* + * external1: + */ +#define CSR_ITRIGGER_ACTION_EXTERNAL1 9 +#define CSR_ETRIGGER 0x7a1 +#define CSR_ETRIGGER_TYPE_OFFSET(XLEN) (XLEN + -4) +#define CSR_ETRIGGER_TYPE_LENGTH 4 +#define CSR_ETRIGGER_TYPE(XLEN) (0xf * (1ULL<<(XLEN + -4))) +#define CSR_ETRIGGER_DMODE_OFFSET(XLEN) (XLEN + -5) +#define CSR_ETRIGGER_DMODE_LENGTH 1 +#define CSR_ETRIGGER_DMODE(XLEN) (1ULL<<(XLEN + -5)) +/* + * If this bit is implemented, the hardware sets it when this + * trigger matches. The trigger's user can set or clear it at any + * time. It is used to determine which + * trigger(s) matched. If the bit is not implemented, it is always 0 + * and writing it has no effect. + */ +#define CSR_ETRIGGER_HIT_OFFSET(XLEN) (XLEN + -6) +#define CSR_ETRIGGER_HIT_LENGTH 1 +#define CSR_ETRIGGER_HIT(XLEN) (1ULL<<(XLEN + -6)) +/* + * When set, enable this trigger for exceptions that are taken from VS + * mode. + * This bit is hard-wired to 0 if the hart does not support + * virtualization mode. + */ +#define CSR_ETRIGGER_VS_OFFSET 0xc +#define CSR_ETRIGGER_VS_LENGTH 1 +#define CSR_ETRIGGER_VS 0x1000 +/* + * When set, enable this trigger for exceptions that are taken from VU + * mode. + * This bit is hard-wired to 0 if the hart does not support + * virtualization mode. + */ +#define CSR_ETRIGGER_VU_OFFSET 0xb +#define CSR_ETRIGGER_VU_LENGTH 1 +#define CSR_ETRIGGER_VU 0x800 +/* + * When set, enable this trigger for exceptions that are taken from M + * mode. + */ +#define CSR_ETRIGGER_M_OFFSET 9 +#define CSR_ETRIGGER_M_LENGTH 1 +#define CSR_ETRIGGER_M 0x200 +/* + * When set, enable this trigger for exceptions that are taken from S/HS + * mode. + * This bit is hard-wired to 0 if the hart does not support + * S-mode. + */ +#define CSR_ETRIGGER_S_OFFSET 7 +#define CSR_ETRIGGER_S_LENGTH 1 +#define CSR_ETRIGGER_S 0x80 +/* + * When set, enable this trigger for exceptions that are taken from U + * mode. + * This bit is hard-wired to 0 if the hart does not support + * U-mode. + */ +#define CSR_ETRIGGER_U_OFFSET 6 +#define CSR_ETRIGGER_U_LENGTH 1 +#define CSR_ETRIGGER_U 0x40 +/* + * The action to take when the trigger fires. The values are explained + * in Table~\ref{tab:action}. + */ +#define CSR_ETRIGGER_ACTION_OFFSET 0 +#define CSR_ETRIGGER_ACTION_LENGTH 6 +#define CSR_ETRIGGER_ACTION 0x3f +/* + * breakpoint: + */ +#define CSR_ETRIGGER_ACTION_BREAKPOINT 0 +/* + * debug mode: + */ +#define CSR_ETRIGGER_ACTION_DEBUG_MODE 1 +/* + * trace on: + */ +#define CSR_ETRIGGER_ACTION_TRACE_ON 2 +/* + * trace off: + */ +#define CSR_ETRIGGER_ACTION_TRACE_OFF 3 +/* + * trace notify: + */ +#define CSR_ETRIGGER_ACTION_TRACE_NOTIFY 4 +/* + * external0: + */ +#define CSR_ETRIGGER_ACTION_EXTERNAL0 8 +/* + * external1: + */ +#define CSR_ETRIGGER_ACTION_EXTERNAL1 9 +#define CSR_TMEXTTRIGGER 0x7a1 +#define CSR_TMEXTTRIGGER_TYPE_OFFSET(XLEN) (XLEN + -4) +#define CSR_TMEXTTRIGGER_TYPE_LENGTH 4 +#define CSR_TMEXTTRIGGER_TYPE(XLEN) (0xf * (1ULL<<(XLEN + -4))) +#define CSR_TMEXTTRIGGER_DMODE_OFFSET(XLEN) (XLEN + -5) +#define CSR_TMEXTTRIGGER_DMODE_LENGTH 1 +#define CSR_TMEXTTRIGGER_DMODE(XLEN) (1ULL<<(XLEN + -5)) +/* + * If this bit is implemented, the hardware sets it when this + * trigger matches. The trigger's user can set or clear it at any + * time. It is used to determine which + * trigger(s) matched. If the bit is not implemented, it is always 0 + * and writing it has no effect. + */ +#define CSR_TMEXTTRIGGER_HIT_OFFSET(XLEN) (XLEN + -6) +#define CSR_TMEXTTRIGGER_HIT_LENGTH 1 +#define CSR_TMEXTTRIGGER_HIT(XLEN) (1ULL<<(XLEN + -6)) +/* + * This optional bit, when set, causes this trigger to fire whenever an attached + * interrupt controller signals a trigger. + */ +#define CSR_TMEXTTRIGGER_INTCTL_OFFSET 0x16 +#define CSR_TMEXTTRIGGER_INTCTL_LENGTH 1 +#define CSR_TMEXTTRIGGER_INTCTL 0x400000 +/* + * Selects any combination of up to 16 external debug trigger inputs + * that cause this trigger to fire. + */ +#define CSR_TMEXTTRIGGER_SELECT_OFFSET 6 +#define CSR_TMEXTTRIGGER_SELECT_LENGTH 0x10 +#define CSR_TMEXTTRIGGER_SELECT 0x3fffc0 +/* + * The action to take when the trigger fires. The values are explained + * in Table~\ref{tab:action}. + */ +#define CSR_TMEXTTRIGGER_ACTION_OFFSET 0 +#define CSR_TMEXTTRIGGER_ACTION_LENGTH 6 +#define CSR_TMEXTTRIGGER_ACTION 0x3f +/* + * breakpoint: + */ +#define CSR_TMEXTTRIGGER_ACTION_BREAKPOINT 0 +/* + * debug mode: + */ +#define CSR_TMEXTTRIGGER_ACTION_DEBUG_MODE 1 +/* + * trace on: + */ +#define CSR_TMEXTTRIGGER_ACTION_TRACE_ON 2 +/* + * trace off: + */ +#define CSR_TMEXTTRIGGER_ACTION_TRACE_OFF 3 +/* + * trace notify: + */ +#define CSR_TMEXTTRIGGER_ACTION_TRACE_NOTIFY 4 +/* + * external0: + */ +#define CSR_TMEXTTRIGGER_ACTION_EXTERNAL0 8 +/* + * external1: + */ +#define CSR_TMEXTTRIGGER_ACTION_EXTERNAL1 9 +#define CSR_TEXTRA32 0x7a3 +/* + * Data used together with \FcsrTextraThirtytwoMhselect. + */ +#define CSR_TEXTRA32_MHVALUE_OFFSET 0x1a +#define CSR_TEXTRA32_MHVALUE_LENGTH 6 +#define CSR_TEXTRA32_MHVALUE 0xfc000000U +#define CSR_TEXTRA32_MHSELECT_OFFSET 0x17 +#define CSR_TEXTRA32_MHSELECT_LENGTH 3 +#define CSR_TEXTRA32_MHSELECT 0x3800000 +/* + * ignore: Ignore \FcsrTextraThirtytwoMhvalue. + */ +#define CSR_TEXTRA32_MHSELECT_IGNORE 0 +/* + * mcontext: This trigger will only match if the low bits of + * \RcsrMcontext/\RcsrHcontext equal \FcsrTextraThirtytwoMhvalue. + */ +#define CSR_TEXTRA32_MHSELECT_MCONTEXT 4 +/* + * 1, 5 (mcontext\_select): This trigger will only match if the low bits of + * \RcsrMcontext/\RcsrHcontext equal \{\FcsrTextraThirtytwoMhvalue, mhselect[2]\}. + * + * 2, 6 (vmid\_select): This trigger will only match if VMID in hgatp equals the lower VMIDMAX + * (defined in the Privileged Spec) bits of \{\FcsrTextraThirtytwoMhvalue, mhselect[2]\}. + * + * 3, 7 (reserved): Reserved. + * + * If the H extension is not supported, the only legal values are 0 and 4. + */ +/* + * When the least significant bit of this field is 1, it causes bits 7:0 + * in the comparison to be ignored, when \FcsrTextraThirtytwoSselect=1. + * When the next most significant bit of this field is 1, it causes bits 15:8 + * to be ignored in the comparison, when \FcsrTextraThirtytwoSselect=1. + */ +#define CSR_TEXTRA32_SBYTEMASK_OFFSET 0x12 +#define CSR_TEXTRA32_SBYTEMASK_LENGTH 2 +#define CSR_TEXTRA32_SBYTEMASK 0xc0000 +/* + * Data used together with \FcsrTextraThirtytwoSselect. + * + * This field should be tied to 0 when S-mode is not supported. + */ +#define CSR_TEXTRA32_SVALUE_OFFSET 2 +#define CSR_TEXTRA32_SVALUE_LENGTH 0x10 +#define CSR_TEXTRA32_SVALUE 0x3fffc +#define CSR_TEXTRA32_SSELECT_OFFSET 0 +#define CSR_TEXTRA32_SSELECT_LENGTH 2 +#define CSR_TEXTRA32_SSELECT 3 +/* + * ignore: Ignore \FcsrTextraThirtytwoSvalue. + */ +#define CSR_TEXTRA32_SSELECT_IGNORE 0 +/* + * scontext: This trigger will only match if the low bits of + * \RcsrScontext equal \FcsrTextraThirtytwoSvalue. + */ +#define CSR_TEXTRA32_SSELECT_SCONTEXT 1 +/* + * asid: This trigger will only match if: + * \begin{itemize}[noitemsep,nolistsep] + * \item the mode is VS-mode or VU-mode and ASID in \Rvsatp + * equals the lower ASIDMAX (defined in the Privileged Spec) bits + * of \FcsrTextraThirtytwoSvalue. + * \item in all other modes, ASID in \Rsatp equals the lower + * ASIDMAX (defined in the Privileged Spec) bits of + * \FcsrTextraThirtytwoSvalue. + * \end{itemize} + */ +#define CSR_TEXTRA32_SSELECT_ASID 2 +/* + * This field should be tied to 0 when S-mode is not supported. + */ +#define CSR_TEXTRA64 0x7a3 +#define CSR_TEXTRA64_MHVALUE_OFFSET 0x33 +#define CSR_TEXTRA64_MHVALUE_LENGTH 0xd +#define CSR_TEXTRA64_MHVALUE 0xfff8000000000000ULL +#define CSR_TEXTRA64_MHSELECT_OFFSET 0x30 +#define CSR_TEXTRA64_MHSELECT_LENGTH 3 +#define CSR_TEXTRA64_MHSELECT 0x7000000000000ULL +/* + * When the least significant bit of this field is 1, it causes bits 7:0 + * in the comparison to be ignored, when \FcsrTextraSixtyfourSselect=1. + * Likewise, the second bit controls the comparison of bits 15:8, + * third bit controls the comparison of bits 23:16, + * fourth bit controls the comparison of bits 31:24, and + * fifth bit controls the comparison of bits 33:32. + */ +#define CSR_TEXTRA64_SBYTEMASK_OFFSET 0x24 +#define CSR_TEXTRA64_SBYTEMASK_LENGTH 5 +#define CSR_TEXTRA64_SBYTEMASK 0x1f000000000ULL +#define CSR_TEXTRA64_SVALUE_OFFSET 2 +#define CSR_TEXTRA64_SVALUE_LENGTH 0x22 +#define CSR_TEXTRA64_SVALUE 0xffffffffcULL +#define CSR_TEXTRA64_SSELECT_OFFSET 0 +#define CSR_TEXTRA64_SSELECT_LENGTH 2 +#define CSR_TEXTRA64_SSELECT 3 +#define DM_DMSTATUS 0x11 +#define DM_DMSTATUS_NDMRESETPENDING_OFFSET 0x18 +#define DM_DMSTATUS_NDMRESETPENDING_LENGTH 1 +#define DM_DMSTATUS_NDMRESETPENDING 0x1000000 +/* + * false: Unimplemented, or \FdmDmcontrolNdmreset is zero and no ndmreset is currently + * in progress. + */ +#define DM_DMSTATUS_NDMRESETPENDING_FALSE 0 +/* + * true: \FdmDmcontrolNdmreset is currently nonzero, or there is an ndmreset in progress. + */ +#define DM_DMSTATUS_NDMRESETPENDING_TRUE 1 +#define DM_DMSTATUS_STICKYUNAVAIL_OFFSET 0x17 +#define DM_DMSTATUS_STICKYUNAVAIL_LENGTH 1 +#define DM_DMSTATUS_STICKYUNAVAIL 0x800000 +/* + * current: The per-hart {\tt unavail} bits reflect the current state of the hart. + */ +#define DM_DMSTATUS_STICKYUNAVAIL_CURRENT 0 +/* + * sticky: The per-hart {\tt unavail} bits are sticky. Once they are set, they will + * not clear until the debugger acknowledges them using \FdmDmcontrolAckunavail. + */ +#define DM_DMSTATUS_STICKYUNAVAIL_STICKY 1 +/* + * If 1, then there is an implicit {\tt ebreak} instruction at the + * non-existent word immediately after the Program Buffer. This saves + * the debugger from having to write the {\tt ebreak} itself, and + * allows the Program Buffer to be one word smaller. + * + * This must be 1 when \FdmAbstractcsProgbufsize is 1. + */ +#define DM_DMSTATUS_IMPEBREAK_OFFSET 0x16 +#define DM_DMSTATUS_IMPEBREAK_LENGTH 1 +#define DM_DMSTATUS_IMPEBREAK 0x400000 +/* + * This field is 1 when all currently selected harts have been reset + * and reset has not been acknowledged for any of them. + */ +#define DM_DMSTATUS_ALLHAVERESET_OFFSET 0x13 +#define DM_DMSTATUS_ALLHAVERESET_LENGTH 1 +#define DM_DMSTATUS_ALLHAVERESET 0x80000 +/* + * This field is 1 when at least one currently selected hart has been + * reset and reset has not been acknowledged for that hart. + */ +#define DM_DMSTATUS_ANYHAVERESET_OFFSET 0x12 +#define DM_DMSTATUS_ANYHAVERESET_LENGTH 1 +#define DM_DMSTATUS_ANYHAVERESET 0x40000 +/* + * This field is 1 when all currently selected harts have their + * resume ack bit\index{resume ack bit} set. + */ +#define DM_DMSTATUS_ALLRESUMEACK_OFFSET 0x11 +#define DM_DMSTATUS_ALLRESUMEACK_LENGTH 1 +#define DM_DMSTATUS_ALLRESUMEACK 0x20000 +/* + * This field is 1 when any currently selected hart has its + * resume ack bit\index{resume ack bit} set. + */ +#define DM_DMSTATUS_ANYRESUMEACK_OFFSET 0x10 +#define DM_DMSTATUS_ANYRESUMEACK_LENGTH 1 +#define DM_DMSTATUS_ANYRESUMEACK 0x10000 +/* + * This field is 1 when all currently selected harts do not exist in + * this hardware platform. + */ +#define DM_DMSTATUS_ALLNONEXISTENT_OFFSET 0xf +#define DM_DMSTATUS_ALLNONEXISTENT_LENGTH 1 +#define DM_DMSTATUS_ALLNONEXISTENT 0x8000 +/* + * This field is 1 when any currently selected hart does not exist in + * this hardware platform. + */ +#define DM_DMSTATUS_ANYNONEXISTENT_OFFSET 0xe +#define DM_DMSTATUS_ANYNONEXISTENT_LENGTH 1 +#define DM_DMSTATUS_ANYNONEXISTENT 0x4000 +/* + * This field is 1 when all currently selected harts are + * unavailable, or (if \FdmDmstatusStickyunavail is 1) were + * unavailable without that being acknowledged. + */ +#define DM_DMSTATUS_ALLUNAVAIL_OFFSET 0xd +#define DM_DMSTATUS_ALLUNAVAIL_LENGTH 1 +#define DM_DMSTATUS_ALLUNAVAIL 0x2000 +/* + * This field is 1 when any currently selected hart is unavailable, + * or (if \FdmDmstatusStickyunavail is 1) was unavailable without + * that being acknowledged. + */ +#define DM_DMSTATUS_ANYUNAVAIL_OFFSET 0xc +#define DM_DMSTATUS_ANYUNAVAIL_LENGTH 1 +#define DM_DMSTATUS_ANYUNAVAIL 0x1000 +/* + * This field is 1 when all currently selected harts are running. + */ +#define DM_DMSTATUS_ALLRUNNING_OFFSET 0xb +#define DM_DMSTATUS_ALLRUNNING_LENGTH 1 +#define DM_DMSTATUS_ALLRUNNING 0x800 +/* + * This field is 1 when any currently selected hart is running. + */ +#define DM_DMSTATUS_ANYRUNNING_OFFSET 0xa +#define DM_DMSTATUS_ANYRUNNING_LENGTH 1 +#define DM_DMSTATUS_ANYRUNNING 0x400 +/* + * This field is 1 when all currently selected harts are halted. + */ +#define DM_DMSTATUS_ALLHALTED_OFFSET 9 +#define DM_DMSTATUS_ALLHALTED_LENGTH 1 +#define DM_DMSTATUS_ALLHALTED 0x200 +/* + * This field is 1 when any currently selected hart is halted. + */ +#define DM_DMSTATUS_ANYHALTED_OFFSET 8 +#define DM_DMSTATUS_ANYHALTED_LENGTH 1 +#define DM_DMSTATUS_ANYHALTED 0x100 +#define DM_DMSTATUS_AUTHENTICATED_OFFSET 7 +#define DM_DMSTATUS_AUTHENTICATED_LENGTH 1 +#define DM_DMSTATUS_AUTHENTICATED 0x80 +/* + * false: Authentication is required before using the DM. + */ +#define DM_DMSTATUS_AUTHENTICATED_FALSE 0 +/* + * true: The authentication check has passed. + */ +#define DM_DMSTATUS_AUTHENTICATED_TRUE 1 +/* + * On components that don't implement authentication, this bit must be + * preset as 1. + */ +#define DM_DMSTATUS_AUTHBUSY_OFFSET 6 +#define DM_DMSTATUS_AUTHBUSY_LENGTH 1 +#define DM_DMSTATUS_AUTHBUSY 0x40 +/* + * ready: The authentication module is ready to process the next + * read/write to \RdmAuthdata. + */ +#define DM_DMSTATUS_AUTHBUSY_READY 0 +/* + * busy: The authentication module is busy. Accessing \RdmAuthdata results + * in unspecified behavior. + */ +#define DM_DMSTATUS_AUTHBUSY_BUSY 1 +/* + * \FdmDmstatusAuthbusy only becomes set in immediate response to an access to + * \RdmAuthdata. + */ +/* + * 1 if this Debug Module supports halt-on-reset functionality + * controllable by the \FdmDmcontrolSetresethaltreq and \FdmDmcontrolClrresethaltreq bits. + * 0 otherwise. + */ +#define DM_DMSTATUS_HASRESETHALTREQ_OFFSET 5 +#define DM_DMSTATUS_HASRESETHALTREQ_LENGTH 1 +#define DM_DMSTATUS_HASRESETHALTREQ 0x20 +#define DM_DMSTATUS_CONFSTRPTRVALID_OFFSET 4 +#define DM_DMSTATUS_CONFSTRPTRVALID_LENGTH 1 +#define DM_DMSTATUS_CONFSTRPTRVALID 0x10 +/* + * invalid: \RdmConfstrptrZero--\RdmConfstrptrThree hold information which + * is not relevant to the configuration structure. + */ +#define DM_DMSTATUS_CONFSTRPTRVALID_INVALID 0 +/* + * valid: \RdmConfstrptrZero--\RdmConfstrptrThree hold the address of the + * configuration structure. + */ +#define DM_DMSTATUS_CONFSTRPTRVALID_VALID 1 +#define DM_DMSTATUS_VERSION_OFFSET 0 +#define DM_DMSTATUS_VERSION_LENGTH 4 +#define DM_DMSTATUS_VERSION 0xf +/* + * none: There is no Debug Module present. + */ +#define DM_DMSTATUS_VERSION_NONE 0 +/* + * 0.11: There is a Debug Module and it conforms to version 0.11 of this + * specification. + */ +#define DM_DMSTATUS_VERSION_0_11 1 +/* + * 0.13: There is a Debug Module and it conforms to version 0.13 of this + * specification. + */ +#define DM_DMSTATUS_VERSION_0_13 2 +/* + * 1.0: There is a Debug Module and it conforms to version 1.0 of this + * specification. + */ +#define DM_DMSTATUS_VERSION_1_0 3 +/* + * custom: There is a Debug Module but it does not conform to any + * available version of this spec. + */ +#define DM_DMSTATUS_VERSION_CUSTOM 15 +#define DM_DMCONTROL 0x10 +/* + * Writing 0 clears the halt request bit for all currently selected + * harts. This may cancel outstanding halt requests for those harts. + * + * Writing 1 sets the halt request bit for all currently selected + * harts. Running harts will halt whenever their halt request bit is + * set. + * + * Writes apply to the new value of \Fhartsel and \FdmDmcontrolHasel. + */ +#define DM_DMCONTROL_HALTREQ_OFFSET 0x1f +#define DM_DMCONTROL_HALTREQ_LENGTH 1 +#define DM_DMCONTROL_HALTREQ 0x80000000U +/* + * Writing 1 causes the currently selected harts to resume once, if + * they are halted when the write occurs. It also clears the resume + * ack bit for those harts. + * + * \FdmDmcontrolResumereq is ignored if \FdmDmcontrolHaltreq is set. + * + * Writes apply to the new value of \Fhartsel and \FdmDmcontrolHasel. + */ +#define DM_DMCONTROL_RESUMEREQ_OFFSET 0x1e +#define DM_DMCONTROL_RESUMEREQ_LENGTH 1 +#define DM_DMCONTROL_RESUMEREQ 0x40000000 +/* + * This optional field writes the reset bit for all the currently + * selected harts. To perform a reset the debugger writes 1, and then + * writes 0 to deassert the reset signal. + * + * While this bit is 1, the debugger must not change which harts are + * selected. + * + * If this feature is not implemented, the bit always stays 0, so + * after writing 1 the debugger can read the register back to see if + * the feature is supported. + * + * Writes apply to the new value of \Fhartsel and \FdmDmcontrolHasel. + */ +#define DM_DMCONTROL_HARTRESET_OFFSET 0x1d +#define DM_DMCONTROL_HARTRESET_LENGTH 1 +#define DM_DMCONTROL_HARTRESET 0x20000000 +#define DM_DMCONTROL_ACKHAVERESET_OFFSET 0x1c +#define DM_DMCONTROL_ACKHAVERESET_LENGTH 1 +#define DM_DMCONTROL_ACKHAVERESET 0x10000000 +/* + * nop: No effect. + */ +#define DM_DMCONTROL_ACKHAVERESET_NOP 0 +/* + * ack: Clears {\tt havereset} for any selected harts. + */ +#define DM_DMCONTROL_ACKHAVERESET_ACK 1 +/* + * Writes apply to the new value of \Fhartsel and \FdmDmcontrolHasel. + */ +#define DM_DMCONTROL_ACKUNAVAIL_OFFSET 0x1b +#define DM_DMCONTROL_ACKUNAVAIL_LENGTH 1 +#define DM_DMCONTROL_ACKUNAVAIL 0x8000000 +/* + * nop: No effect. + */ +#define DM_DMCONTROL_ACKUNAVAIL_NOP 0 +/* + * ack: Clears {\tt unavail} for any selected harts that are currently available. + */ +#define DM_DMCONTROL_ACKUNAVAIL_ACK 1 +/* + * Writes apply to the new value of \Fhartsel and \FdmDmcontrolHasel. + */ +/* + * Selects the definition of currently selected harts. + */ +#define DM_DMCONTROL_HASEL_OFFSET 0x1a +#define DM_DMCONTROL_HASEL_LENGTH 1 +#define DM_DMCONTROL_HASEL 0x4000000 +/* + * single: There is a single currently selected hart, that is selected by \Fhartsel. + */ +#define DM_DMCONTROL_HASEL_SINGLE 0 +/* + * multiple: There may be multiple currently selected harts -- the hart + * selected by \Fhartsel, plus those selected by the hart array mask + * register. + */ +#define DM_DMCONTROL_HASEL_MULTIPLE 1 +/* + * An implementation which does not implement the hart array mask register + * must tie this field to 0. A debugger which wishes to use the hart array + * mask register feature should set this bit and read back to see if the functionality + * is supported. + */ +/* + * The low 10 bits of \Fhartsel: the DM-specific index of the hart to + * select. This hart is always part of the currently selected harts. + */ +#define DM_DMCONTROL_HARTSELLO_OFFSET 0x10 +#define DM_DMCONTROL_HARTSELLO_LENGTH 0xa +#define DM_DMCONTROL_HARTSELLO 0x3ff0000 +/* + * The high 10 bits of \Fhartsel: the DM-specific index of the hart to + * select. This hart is always part of the currently selected harts. + */ +#define DM_DMCONTROL_HARTSELHI_OFFSET 6 +#define DM_DMCONTROL_HARTSELHI_LENGTH 0xa +#define DM_DMCONTROL_HARTSELHI 0xffc0 +/* + * This optional field sets \Fkeepalive for all currently selected + * harts, unless \FdmDmcontrolClrkeepalive is simultaneously set to + * 1. + * + * Writes apply to the new value of \Fhartsel and \FdmDmcontrolHasel. + */ +#define DM_DMCONTROL_SETKEEPALIVE_OFFSET 5 +#define DM_DMCONTROL_SETKEEPALIVE_LENGTH 1 +#define DM_DMCONTROL_SETKEEPALIVE 0x20 +/* + * This optional field clears \Fkeepalive for all currently selected + * harts. + * + * Writes apply to the new value of \Fhartsel and \FdmDmcontrolHasel. + */ +#define DM_DMCONTROL_CLRKEEPALIVE_OFFSET 4 +#define DM_DMCONTROL_CLRKEEPALIVE_LENGTH 1 +#define DM_DMCONTROL_CLRKEEPALIVE 0x10 +/* + * This optional field writes the halt-on-reset request bit for all + * currently selected harts, unless \FdmDmcontrolClrresethaltreq is + * simultaneously set to 1. + * When set to 1, each selected hart will halt upon the next deassertion + * of its reset. The halt-on-reset request bit is not automatically + * cleared. The debugger must write to \FdmDmcontrolClrresethaltreq to clear it. + * + * Writes apply to the new value of \Fhartsel and \FdmDmcontrolHasel. + * + * If \FdmDmstatusHasresethaltreq is 0, this field is not implemented. + */ +#define DM_DMCONTROL_SETRESETHALTREQ_OFFSET 3 +#define DM_DMCONTROL_SETRESETHALTREQ_LENGTH 1 +#define DM_DMCONTROL_SETRESETHALTREQ 8 +/* + * This optional field clears the halt-on-reset request bit for all + * currently selected harts. + * + * Writes apply to the new value of \Fhartsel and \FdmDmcontrolHasel. + */ +#define DM_DMCONTROL_CLRRESETHALTREQ_OFFSET 2 +#define DM_DMCONTROL_CLRRESETHALTREQ_LENGTH 1 +#define DM_DMCONTROL_CLRRESETHALTREQ 4 +/* + * This bit controls the reset signal from the DM to the rest of the + * hardware platform. The signal should reset every part of the hardware platform, including + * every hart, except for the DM and any logic required to access the + * DM. + * To perform a hardware platform reset the debugger writes 1, + * and then writes 0 + * to deassert the reset. + */ +#define DM_DMCONTROL_NDMRESET_OFFSET 1 +#define DM_DMCONTROL_NDMRESET_LENGTH 1 +#define DM_DMCONTROL_NDMRESET 2 +/* + * This bit serves as a reset signal for the Debug Module itself. + * After changing the value of this bit, the debugger must poll + * \RdmDmcontrol until \FdmDmcontrolDmactive has taken the requested value + * before performing any action that assumes the requested \FdmDmcontrolDmactive + * state change has completed. Hardware may + * take an arbitrarily long time to complete activation or deactivation and will + * indicate completion by setting \FdmDmcontrolDmactive to the requested value. + */ +#define DM_DMCONTROL_DMACTIVE_OFFSET 0 +#define DM_DMCONTROL_DMACTIVE_LENGTH 1 +#define DM_DMCONTROL_DMACTIVE 1 +/* + * inactive: The module's state, including authentication mechanism, + * takes its reset values (the \FdmDmcontrolDmactive bit is the only bit which can + * be written to something other than its reset value). Any accesses + * to the module may fail. Specifically, \FdmDmstatusVersion might not return + * correct data. + */ +#define DM_DMCONTROL_DMACTIVE_INACTIVE 0 +/* + * active: The module functions normally. + */ +#define DM_DMCONTROL_DMACTIVE_ACTIVE 1 +/* + * No other mechanism should exist that may result in resetting the + * Debug Module after power up. + * + * To place the Debug Module into a known state, a debugger may write 0 to \FdmDmcontrolDmactive, + * poll until \FdmDmcontrolDmactive is observed 0, write 1 to \FdmDmcontrolDmactive, and + * poll until \FdmDmcontrolDmactive is observed 1. + * + * Implementations may pay attention to this bit to further aid + * debugging, for example by preventing the Debug Module from being + * power gated while debugging is active. + */ +#define DM_HARTINFO 0x12 +/* + * Number of {\tt dscratch} registers available for the debugger + * to use during program buffer execution, starting from \RcsrDscratchZero. + * The debugger can make no assumptions about the contents of these + * registers between commands. + */ +#define DM_HARTINFO_NSCRATCH_OFFSET 0x14 +#define DM_HARTINFO_NSCRATCH_LENGTH 4 +#define DM_HARTINFO_NSCRATCH 0xf00000 +#define DM_HARTINFO_DATAACCESS_OFFSET 0x10 +#define DM_HARTINFO_DATAACCESS_LENGTH 1 +#define DM_HARTINFO_DATAACCESS 0x10000 +/* + * csr: The {\tt data} registers are shadowed in the hart by CSRs. + * Each CSR is DXLEN bits in size, and corresponds + * to a single argument, per Table~\ref{tab:datareg}. + */ +#define DM_HARTINFO_DATAACCESS_CSR 0 +/* + * memory: The {\tt data} registers are shadowed in the hart's memory map. + * Each register takes up 4 bytes in the memory map. + */ +#define DM_HARTINFO_DATAACCESS_MEMORY 1 +/* + * If \FdmHartinfoDataaccess is 0: Number of CSRs dedicated to + * shadowing the {\tt data} registers. + * + * If \FdmHartinfoDataaccess is 1: Number of 32-bit words in the memory map + * dedicated to shadowing the {\tt data} registers. + * + * If this value is non-zero, then the {tt data} registers must go + * beyond being MRs and guarantee they each store a single value, that is + * readable/writable by either side. + * + * Since there are at most 12 {\tt data} registers, the value in this + * register must be 12 or smaller. + */ +#define DM_HARTINFO_DATASIZE_OFFSET 0xc +#define DM_HARTINFO_DATASIZE_LENGTH 4 +#define DM_HARTINFO_DATASIZE 0xf000 +/* + * If \FdmHartinfoDataaccess is 0: The number of the first CSR dedicated to + * shadowing the {\tt data} registers. + * + * If \FdmHartinfoDataaccess is 1: Address of RAM where the data + * registers are shadowed. This address is sign extended giving a + * range of -2048 to 2047, easily addressed with a load or store using + * \Xzero as the address register. + */ +#define DM_HARTINFO_DATAADDR_OFFSET 0 +#define DM_HARTINFO_DATAADDR_LENGTH 0xc +#define DM_HARTINFO_DATAADDR 0xfff +#define DM_HAWINDOWSEL 0x14 +/* + * The high bits of this field may be tied to 0, depending on how large + * the array mask register is. E.g.\ on a hardware platform with 48 harts only bit 0 + * of this field may actually be writable. + */ +#define DM_HAWINDOWSEL_HAWINDOWSEL_OFFSET 0 +#define DM_HAWINDOWSEL_HAWINDOWSEL_LENGTH 0xf +#define DM_HAWINDOWSEL_HAWINDOWSEL 0x7fff +#define DM_HAWINDOW 0x15 +#define DM_HAWINDOW_MASKDATA_OFFSET 0 +#define DM_HAWINDOW_MASKDATA_LENGTH 0x20 +#define DM_HAWINDOW_MASKDATA 0xffffffffU +#define DM_ABSTRACTCS 0x16 +/* + * Size of the Program Buffer, in 32-bit words. Valid sizes are 0 - 16. + */ +#define DM_ABSTRACTCS_PROGBUFSIZE_OFFSET 0x18 +#define DM_ABSTRACTCS_PROGBUFSIZE_LENGTH 5 +#define DM_ABSTRACTCS_PROGBUFSIZE 0x1f000000 +#define DM_ABSTRACTCS_BUSY_OFFSET 0xc +#define DM_ABSTRACTCS_BUSY_LENGTH 1 +#define DM_ABSTRACTCS_BUSY 0x1000 +/* + * ready: There is no abstract command currently being executed. + */ +#define DM_ABSTRACTCS_BUSY_READY 0 +/* + * busy: An abstract command is currently being executed. + */ +#define DM_ABSTRACTCS_BUSY_BUSY 1 +/* + * This bit is set as soon as \RdmCommand is written, and is + * not cleared until that command has completed. + */ +/* + * This optional bit controls whether program buffer and abstract + * memory accesses are performed with the exact and full set of + * permission checks that apply based on the current architectural + * state of the hart performing the access, or with a relaxed set of + * permission checks (e.g. PMP restrictions are ignored). The + * details of the latter are implementation-specific. + */ +#define DM_ABSTRACTCS_RELAXEDPRIV_OFFSET 0xb +#define DM_ABSTRACTCS_RELAXEDPRIV_LENGTH 1 +#define DM_ABSTRACTCS_RELAXEDPRIV 0x800 +/* + * full checks: Full permission checks apply. + */ +#define DM_ABSTRACTCS_RELAXEDPRIV_FULL_CHECKS 0 +/* + * relaxed checks: Relaxed permission checks apply. + */ +#define DM_ABSTRACTCS_RELAXEDPRIV_RELAXED_CHECKS 1 +/* + * Gets set if an abstract command fails. The bits in this field remain set until + * they are cleared by writing 1 to them. No abstract command is + * started until the value is reset to 0. + * + * This field only contains a valid value if \FdmAbstractcsBusy is 0. + */ +#define DM_ABSTRACTCS_CMDERR_OFFSET 8 +#define DM_ABSTRACTCS_CMDERR_LENGTH 3 +#define DM_ABSTRACTCS_CMDERR 0x700 +/* + * none: No error. + */ +#define DM_ABSTRACTCS_CMDERR_NONE 0 +/* + * busy: An abstract command was executing while \RdmCommand, + * \RdmAbstractcs, or \RdmAbstractauto was written, or when one + * of the {\tt data} or {\tt progbuf} registers was read or written. + * This status is only written if \FdmAbstractcsCmderr contains 0. + */ +#define DM_ABSTRACTCS_CMDERR_BUSY 1 +/* + * not supported: The command in \RdmCommand is not supported. It + * may be supported with different options set, but it will not be + * supported at a later time when the hart or system state are + * different. + */ +#define DM_ABSTRACTCS_CMDERR_NOT_SUPPORTED 2 +/* + * exception: An exception occurred while executing the command + * (e.g.\ while executing the Program Buffer). + */ +#define DM_ABSTRACTCS_CMDERR_EXCEPTION 3 +/* + * halt/resume: The abstract command couldn't execute because the + * hart wasn't in the required state (running/halted), or unavailable. + */ +#define DM_ABSTRACTCS_CMDERR_HALT_RESUME 4 +/* + * bus: The abstract command failed due to a bus error (e.g.\ + * alignment, access size, or timeout). + */ +#define DM_ABSTRACTCS_CMDERR_BUS 5 +/* + * reserved: Reserved for future use. + */ +#define DM_ABSTRACTCS_CMDERR_RESERVED 6 +/* + * other: The command failed for another reason. + */ +#define DM_ABSTRACTCS_CMDERR_OTHER 7 +/* + * Number of {\tt data} registers that are implemented as part of the + * abstract command interface. Valid sizes are 1 -- 12. + */ +#define DM_ABSTRACTCS_DATACOUNT_OFFSET 0 +#define DM_ABSTRACTCS_DATACOUNT_LENGTH 4 +#define DM_ABSTRACTCS_DATACOUNT 0xf +#define DM_COMMAND 0x17 +/* + * The type determines the overall functionality of this + * abstract command. + */ +#define DM_COMMAND_CMDTYPE_OFFSET 0x18 +#define DM_COMMAND_CMDTYPE_LENGTH 8 +#define DM_COMMAND_CMDTYPE 0xff000000U +/* + * This field is interpreted in a command-specific manner, + * described for each abstract command. + */ +#define DM_COMMAND_CONTROL_OFFSET 0 +#define DM_COMMAND_CONTROL_LENGTH 0x18 +#define DM_COMMAND_CONTROL 0xffffff +#define DM_ABSTRACTAUTO 0x18 +/* + * When a bit in this field is 1, read or write accesses to the + * corresponding {\tt progbuf} word cause the DM to act as if the + * current value in \RdmCommand was written there again after the + * access to {\tt progbuf} completes. + */ +#define DM_ABSTRACTAUTO_AUTOEXECPROGBUF_OFFSET 0x10 +#define DM_ABSTRACTAUTO_AUTOEXECPROGBUF_LENGTH 0x10 +#define DM_ABSTRACTAUTO_AUTOEXECPROGBUF 0xffff0000U +/* + * When a bit in this field is 1, read or write accesses to the + * corresponding {\tt data} word cause the DM to act as if the current + * value in \RdmCommand was written there again after the + * access to {\tt data} completes. + */ +#define DM_ABSTRACTAUTO_AUTOEXECDATA_OFFSET 0 +#define DM_ABSTRACTAUTO_AUTOEXECDATA_LENGTH 0xc +#define DM_ABSTRACTAUTO_AUTOEXECDATA 0xfff +#define DM_CONFSTRPTR0 0x19 +#define DM_CONFSTRPTR0_ADDR_OFFSET 0 +#define DM_CONFSTRPTR0_ADDR_LENGTH 0x20 +#define DM_CONFSTRPTR0_ADDR 0xffffffffU +#define DM_CONFSTRPTR1 0x1a +#define DM_CONFSTRPTR1_ADDR_OFFSET 0 +#define DM_CONFSTRPTR1_ADDR_LENGTH 0x20 +#define DM_CONFSTRPTR1_ADDR 0xffffffffU +#define DM_CONFSTRPTR2 0x1b +#define DM_CONFSTRPTR2_ADDR_OFFSET 0 +#define DM_CONFSTRPTR2_ADDR_LENGTH 0x20 +#define DM_CONFSTRPTR2_ADDR 0xffffffffU +#define DM_CONFSTRPTR3 0x1c +#define DM_CONFSTRPTR3_ADDR_OFFSET 0 +#define DM_CONFSTRPTR3_ADDR_LENGTH 0x20 +#define DM_CONFSTRPTR3_ADDR 0xffffffffU +#define DM_NEXTDM 0x1d +#define DM_NEXTDM_ADDR_OFFSET 0 +#define DM_NEXTDM_ADDR_LENGTH 0x20 +#define DM_NEXTDM_ADDR 0xffffffffU +#define DM_DATA0 0x04 +#define DM_DATA0_DATA_OFFSET 0 +#define DM_DATA0_DATA_LENGTH 0x20 +#define DM_DATA0_DATA 0xffffffffU +#define DM_DATA1 0x05 +#define DM_DATA2 0x06 +#define DM_DATA3 0x07 +#define DM_DATA4 0x08 +#define DM_DATA5 0x09 +#define DM_DATA6 0x0a +#define DM_DATA7 0x0b +#define DM_DATA8 0x0c +#define DM_DATA9 0x0d +#define DM_DATA10 0x0e +#define DM_DATA11 0x0f +#define DM_PROGBUF0 0x20 +#define DM_PROGBUF0_DATA_OFFSET 0 +#define DM_PROGBUF0_DATA_LENGTH 0x20 +#define DM_PROGBUF0_DATA 0xffffffffU +#define DM_PROGBUF1 0x21 +#define DM_PROGBUF2 0x22 +#define DM_PROGBUF3 0x23 +#define DM_PROGBUF4 0x24 +#define DM_PROGBUF5 0x25 +#define DM_PROGBUF6 0x26 +#define DM_PROGBUF7 0x27 +#define DM_PROGBUF8 0x28 +#define DM_PROGBUF9 0x29 +#define DM_PROGBUF10 0x2a +#define DM_PROGBUF11 0x2b +#define DM_PROGBUF12 0x2c +#define DM_PROGBUF13 0x2d +#define DM_PROGBUF14 0x2e +#define DM_PROGBUF15 0x2f +#define DM_AUTHDATA 0x30 +#define DM_AUTHDATA_DATA_OFFSET 0 +#define DM_AUTHDATA_DATA_LENGTH 0x20 +#define DM_AUTHDATA_DATA 0xffffffffU +#define DM_DMCS2 0x32 +#define DM_DMCS2_GROUPTYPE_OFFSET 0xb +#define DM_DMCS2_GROUPTYPE_LENGTH 1 +#define DM_DMCS2_GROUPTYPE 0x800 +/* + * halt: The remaining fields in this register configure halt groups. + */ +#define DM_DMCS2_GROUPTYPE_HALT 0 +/* + * resume: The remaining fields in this register configure resume groups. + */ +#define DM_DMCS2_GROUPTYPE_RESUME 1 +/* + * This field contains the currently selected DM external trigger. + * + * If a non-existent trigger value is written here, the hardware will + * change it to a valid one or 0 if no DM external triggers exist. + */ +#define DM_DMCS2_DMEXTTRIGGER_OFFSET 7 +#define DM_DMCS2_DMEXTTRIGGER_LENGTH 4 +#define DM_DMCS2_DMEXTTRIGGER 0x780 +/* + * When \FdmDmcsTwoHgselect is 0, contains the group of the hart + * specified by \Fhartsel. + * + * When \FdmDmcsTwoHgselect is 1, contains the group of the DM external + * trigger selected by \FdmDmcsTwoDmexttrigger. + * + * The value written to this field is ignored unless \FdmDmcsTwoHgwrite + * is also written 1. + * + * Group numbers are contiguous starting at 0, with the highest number + * being implementation-dependent, and possibly different between + * different group types. Debuggers should read back this field after + * writing to confirm they are using a hart group that is supported. + * + * If groups aren't implemented, then this entire field is 0. + */ +#define DM_DMCS2_GROUP_OFFSET 2 +#define DM_DMCS2_GROUP_LENGTH 5 +#define DM_DMCS2_GROUP 0x7c +/* + * When 1 is written and \FdmDmcsTwoHgselect is 0, for every selected + * hart the DM will change its group to the value written to \FdmDmcsTwoGroup, + * if the hardware supports that group for that hart. + * Implementations may also change the group of a minimal set of + * unselected harts in the same way, if that is necessary due to + * a hardware limitation. + * + * When 1 is written and \FdmDmcsTwoHgselect is 1, the DM will change + * the group of the DM external trigger selected by \FdmDmcsTwoDmexttrigger + * to the value written to \FdmDmcsTwoGroup, if the hardware supports + * that group for that trigger. + * + * Writing 0 has no effect. + */ +#define DM_DMCS2_HGWRITE_OFFSET 1 +#define DM_DMCS2_HGWRITE_LENGTH 1 +#define DM_DMCS2_HGWRITE 2 +#define DM_DMCS2_HGSELECT_OFFSET 0 +#define DM_DMCS2_HGSELECT_LENGTH 1 +#define DM_DMCS2_HGSELECT 1 +/* + * harts: Operate on harts. + */ +#define DM_DMCS2_HGSELECT_HARTS 0 +/* + * triggers: Operate on DM external triggers. + */ +#define DM_DMCS2_HGSELECT_TRIGGERS 1 +/* + * If there are no DM external triggers, this field must be tied to 0. + */ +#define DM_HALTSUM0 0x40 +#define DM_HALTSUM0_HALTSUM0_OFFSET 0 +#define DM_HALTSUM0_HALTSUM0_LENGTH 0x20 +#define DM_HALTSUM0_HALTSUM0 0xffffffffU +#define DM_HALTSUM1 0x13 +#define DM_HALTSUM1_HALTSUM1_OFFSET 0 +#define DM_HALTSUM1_HALTSUM1_LENGTH 0x20 +#define DM_HALTSUM1_HALTSUM1 0xffffffffU +#define DM_HALTSUM2 0x34 +#define DM_HALTSUM2_HALTSUM2_OFFSET 0 +#define DM_HALTSUM2_HALTSUM2_LENGTH 0x20 +#define DM_HALTSUM2_HALTSUM2 0xffffffffU +#define DM_HALTSUM3 0x35 +#define DM_HALTSUM3_HALTSUM3_OFFSET 0 +#define DM_HALTSUM3_HALTSUM3_LENGTH 0x20 +#define DM_HALTSUM3_HALTSUM3 0xffffffffU +#define DM_SBCS 0x38 +#define DM_SBCS_SBVERSION_OFFSET 0x1d +#define DM_SBCS_SBVERSION_LENGTH 3 +#define DM_SBCS_SBVERSION 0xe0000000U +/* + * legacy: The System Bus interface conforms to mainline drafts of this + * spec older than 1 January, 2018. + */ +#define DM_SBCS_SBVERSION_LEGACY 0 +/* + * 1.0: The System Bus interface conforms to this version of the spec. + */ +#define DM_SBCS_SBVERSION_1_0 1 +/* + * Other values are reserved for future versions. + */ +/* + * Set when the debugger attempts to read data while a read is in + * progress, or when the debugger initiates a new access while one is + * already in progress (while \FdmSbcsSbbusy is set). It remains set until + * it's explicitly cleared by the debugger. + * + * While this field is set, no more system bus accesses can be + * initiated by the Debug Module. + */ +#define DM_SBCS_SBBUSYERROR_OFFSET 0x16 +#define DM_SBCS_SBBUSYERROR_LENGTH 1 +#define DM_SBCS_SBBUSYERROR 0x400000 +/* + * When 1, indicates the system bus master is busy. (Whether the + * system bus itself is busy is related, but not the same thing.) This + * bit goes high immediately when a read or write is requested for any + * reason, and does not go low until the access is fully completed. + * + * Writes to \RdmSbcs while \FdmSbcsSbbusy is high result in undefined + * behavior. A debugger must not write to \RdmSbcs until it reads + * \FdmSbcsSbbusy as 0. + */ +#define DM_SBCS_SBBUSY_OFFSET 0x15 +#define DM_SBCS_SBBUSY_LENGTH 1 +#define DM_SBCS_SBBUSY 0x200000 +/* + * When 1, every write to \RdmSbaddressZero automatically triggers a + * system bus read at the new address. + */ +#define DM_SBCS_SBREADONADDR_OFFSET 0x14 +#define DM_SBCS_SBREADONADDR_LENGTH 1 +#define DM_SBCS_SBREADONADDR 0x100000 +/* + * Select the access size to use for system bus accesses. + */ +#define DM_SBCS_SBACCESS_OFFSET 0x11 +#define DM_SBCS_SBACCESS_LENGTH 3 +#define DM_SBCS_SBACCESS 0xe0000 +/* + * 8bit: 8-bit + */ +#define DM_SBCS_SBACCESS_8BIT 0 +/* + * 16bit: 16-bit + */ +#define DM_SBCS_SBACCESS_16BIT 1 +/* + * 32bit: 32-bit + */ +#define DM_SBCS_SBACCESS_32BIT 2 +/* + * 64bit: 64-bit + */ +#define DM_SBCS_SBACCESS_64BIT 3 +/* + * 128bit: 128-bit + */ +#define DM_SBCS_SBACCESS_128BIT 4 +/* + * If \FdmSbcsSbaccess has an unsupported value when the DM starts a bus + * access, the access is not performed and \FdmSbcsSberror is set to 4. + */ +/* + * When 1, {\tt sbaddress} is incremented by the access size (in + * bytes) selected in \FdmSbcsSbaccess after every system bus access. + */ +#define DM_SBCS_SBAUTOINCREMENT_OFFSET 0x10 +#define DM_SBCS_SBAUTOINCREMENT_LENGTH 1 +#define DM_SBCS_SBAUTOINCREMENT 0x10000 +/* + * When 1, every read from \RdmSbdataZero automatically triggers a + * system bus read at the (possibly auto-incremented) address. + */ +#define DM_SBCS_SBREADONDATA_OFFSET 0xf +#define DM_SBCS_SBREADONDATA_LENGTH 1 +#define DM_SBCS_SBREADONDATA 0x8000 +/* + * When the Debug Module's system bus + * master encounters an error, this field gets set. The bits in this + * field remain set until they are cleared by writing 1 to them. + * While this field is non-zero, no more system bus accesses can be + * initiated by the Debug Module. + * + * An implementation may report ``Other'' (7) for any error condition. + */ +#define DM_SBCS_SBERROR_OFFSET 0xc +#define DM_SBCS_SBERROR_LENGTH 3 +#define DM_SBCS_SBERROR 0x7000 +/* + * none: There was no bus error. + */ +#define DM_SBCS_SBERROR_NONE 0 +/* + * timeout: There was a timeout. + */ +#define DM_SBCS_SBERROR_TIMEOUT 1 +/* + * address: A bad address was accessed. + */ +#define DM_SBCS_SBERROR_ADDRESS 2 +/* + * alignment: There was an alignment error. + */ +#define DM_SBCS_SBERROR_ALIGNMENT 3 +/* + * size: An access of unsupported size was requested. + */ +#define DM_SBCS_SBERROR_SIZE 4 +/* + * other: Other. + */ +#define DM_SBCS_SBERROR_OTHER 7 +/* + * Width of system bus addresses in bits. (0 indicates there is no bus + * access support.) + */ +#define DM_SBCS_SBASIZE_OFFSET 5 +#define DM_SBCS_SBASIZE_LENGTH 7 +#define DM_SBCS_SBASIZE 0xfe0 +/* + * 1 when 128-bit system bus accesses are supported. + */ +#define DM_SBCS_SBACCESS128_OFFSET 4 +#define DM_SBCS_SBACCESS128_LENGTH 1 +#define DM_SBCS_SBACCESS128 0x10 +/* + * 1 when 64-bit system bus accesses are supported. + */ +#define DM_SBCS_SBACCESS64_OFFSET 3 +#define DM_SBCS_SBACCESS64_LENGTH 1 +#define DM_SBCS_SBACCESS64 8 +/* + * 1 when 32-bit system bus accesses are supported. + */ +#define DM_SBCS_SBACCESS32_OFFSET 2 +#define DM_SBCS_SBACCESS32_LENGTH 1 +#define DM_SBCS_SBACCESS32 4 +/* + * 1 when 16-bit system bus accesses are supported. + */ +#define DM_SBCS_SBACCESS16_OFFSET 1 +#define DM_SBCS_SBACCESS16_LENGTH 1 +#define DM_SBCS_SBACCESS16 2 +/* + * 1 when 8-bit system bus accesses are supported. + */ +#define DM_SBCS_SBACCESS8_OFFSET 0 +#define DM_SBCS_SBACCESS8_LENGTH 1 +#define DM_SBCS_SBACCESS8 1 +#define DM_SBADDRESS0 0x39 +/* + * Accesses bits 31:0 of the physical address in {\tt sbaddress}. + */ +#define DM_SBADDRESS0_ADDRESS_OFFSET 0 +#define DM_SBADDRESS0_ADDRESS_LENGTH 0x20 +#define DM_SBADDRESS0_ADDRESS 0xffffffffU +#define DM_SBADDRESS1 0x3a +/* + * Accesses bits 63:32 of the physical address in {\tt sbaddress} (if + * the system address bus is that wide). + */ +#define DM_SBADDRESS1_ADDRESS_OFFSET 0 +#define DM_SBADDRESS1_ADDRESS_LENGTH 0x20 +#define DM_SBADDRESS1_ADDRESS 0xffffffffU +#define DM_SBADDRESS2 0x3b +/* + * Accesses bits 95:64 of the physical address in {\tt sbaddress} (if + * the system address bus is that wide). + */ +#define DM_SBADDRESS2_ADDRESS_OFFSET 0 +#define DM_SBADDRESS2_ADDRESS_LENGTH 0x20 +#define DM_SBADDRESS2_ADDRESS 0xffffffffU +#define DM_SBADDRESS3 0x37 +/* + * Accesses bits 127:96 of the physical address in {\tt sbaddress} (if + * the system address bus is that wide). + */ +#define DM_SBADDRESS3_ADDRESS_OFFSET 0 +#define DM_SBADDRESS3_ADDRESS_LENGTH 0x20 +#define DM_SBADDRESS3_ADDRESS 0xffffffffU +#define DM_SBDATA0 0x3c +/* + * Accesses bits 31:0 of {\tt sbdata}. + */ +#define DM_SBDATA0_DATA_OFFSET 0 +#define DM_SBDATA0_DATA_LENGTH 0x20 +#define DM_SBDATA0_DATA 0xffffffffU +#define DM_SBDATA1 0x3d +/* + * Accesses bits 63:32 of {\tt sbdata} (if the system bus is that + * wide). + */ +#define DM_SBDATA1_DATA_OFFSET 0 +#define DM_SBDATA1_DATA_LENGTH 0x20 +#define DM_SBDATA1_DATA 0xffffffffU +#define DM_SBDATA2 0x3e +/* + * Accesses bits 95:64 of {\tt sbdata} (if the system bus is that + * wide). + */ +#define DM_SBDATA2_DATA_OFFSET 0 +#define DM_SBDATA2_DATA_LENGTH 0x20 +#define DM_SBDATA2_DATA 0xffffffffU +#define DM_SBDATA3 0x3f +/* + * Accesses bits 127:96 of {\tt sbdata} (if the system bus is that + * wide). + */ +#define DM_SBDATA3_DATA_OFFSET 0 +#define DM_SBDATA3_DATA_LENGTH 0x20 +#define DM_SBDATA3_DATA 0xffffffffU +#define DM_CUSTOM 0x1f +#define DM_CUSTOM0 0x70 +#define DM_CUSTOM1 0x71 +#define DM_CUSTOM2 0x72 +#define DM_CUSTOM3 0x73 +#define DM_CUSTOM4 0x74 +#define DM_CUSTOM5 0x75 +#define DM_CUSTOM6 0x76 +#define DM_CUSTOM7 0x77 +#define DM_CUSTOM8 0x78 +#define DM_CUSTOM9 0x79 +#define DM_CUSTOM10 0x7a +#define DM_CUSTOM11 0x7b +#define DM_CUSTOM12 0x7c +#define DM_CUSTOM13 0x7d +#define DM_CUSTOM14 0x7e +#define DM_CUSTOM15 0x7f +#define SHORTNAME 0x123 +/* + * Description of what this field is used for. + */ +#define SHORTNAME_FIELD_OFFSET 0 +#define SHORTNAME_FIELD_LENGTH 8 +#define SHORTNAME_FIELD 0xff +/* + * This is 0 to indicate Access Register Command. + */ +#define AC_ACCESS_REGISTER_CMDTYPE_OFFSET 0x18 +#define AC_ACCESS_REGISTER_CMDTYPE_LENGTH 8 +#define AC_ACCESS_REGISTER_CMDTYPE 0xff000000U +#define AC_ACCESS_REGISTER_AARSIZE_OFFSET 0x14 +#define AC_ACCESS_REGISTER_AARSIZE_LENGTH 3 +#define AC_ACCESS_REGISTER_AARSIZE 0x700000 +/* + * 32bit: Access the lowest 32 bits of the register. + */ +#define AC_ACCESS_REGISTER_AARSIZE_32BIT 2 +/* + * 64bit: Access the lowest 64 bits of the register. + */ +#define AC_ACCESS_REGISTER_AARSIZE_64BIT 3 +/* + * 128bit: Access the lowest 128 bits of the register. + */ +#define AC_ACCESS_REGISTER_AARSIZE_128BIT 4 +/* + * If \FacAccessregisterAarsize specifies a size larger than the register's actual size, + * then the access must fail. If a register is accessible, then reads of \FacAccessregisterAarsize + * less than or equal to the register's actual size must be supported. + * Writing less than the full register may be supported, but what + * happens to the high bits in that case is \unspecified. + * + * This field controls the Argument Width as referenced in + * Table~\ref{tab:datareg}. + */ +#define AC_ACCESS_REGISTER_AARPOSTINCREMENT_OFFSET 0x13 +#define AC_ACCESS_REGISTER_AARPOSTINCREMENT_LENGTH 1 +#define AC_ACCESS_REGISTER_AARPOSTINCREMENT 0x80000 +/* + * disabled: No effect. This variant must be supported. + */ +#define AC_ACCESS_REGISTER_AARPOSTINCREMENT_DISABLED 0 +/* + * enabled: After a successful register access, \FacAccessregisterRegno is + * incremented. Incrementing past the highest supported value + * causes \FacAccessregisterRegno to become \unspecified. Supporting + * this variant is optional. It is undefined whether the increment + * happens when \FacAccessregisterTransfer is 0. + */ +#define AC_ACCESS_REGISTER_AARPOSTINCREMENT_ENABLED 1 +#define AC_ACCESS_REGISTER_POSTEXEC_OFFSET 0x12 +#define AC_ACCESS_REGISTER_POSTEXEC_LENGTH 1 +#define AC_ACCESS_REGISTER_POSTEXEC 0x40000 +/* + * disabled: No effect. This variant must be supported, and is the only + * supported one if \FdmAbstractcsProgbufsize is 0. + */ +#define AC_ACCESS_REGISTER_POSTEXEC_DISABLED 0 +/* + * enabled: Execute the program in the Program Buffer exactly once after + * performing the transfer, if any. Supporting this variant is + * optional. + */ +#define AC_ACCESS_REGISTER_POSTEXEC_ENABLED 1 +#define AC_ACCESS_REGISTER_TRANSFER_OFFSET 0x11 +#define AC_ACCESS_REGISTER_TRANSFER_LENGTH 1 +#define AC_ACCESS_REGISTER_TRANSFER 0x20000 +/* + * disabled: Don't do the operation specified by \FacAccessregisterWrite. + */ +#define AC_ACCESS_REGISTER_TRANSFER_DISABLED 0 +/* + * enabled: Do the operation specified by \FacAccessregisterWrite. + */ +#define AC_ACCESS_REGISTER_TRANSFER_ENABLED 1 +/* + * This bit can be used to just execute the Program Buffer without + * having to worry about placing valid values into \FacAccessregisterAarsize or \FacAccessregisterRegno. + */ +/* + * When \FacAccessregisterTransfer is set: + */ +#define AC_ACCESS_REGISTER_WRITE_OFFSET 0x10 +#define AC_ACCESS_REGISTER_WRITE_LENGTH 1 +#define AC_ACCESS_REGISTER_WRITE 0x10000 +/* + * arg0: Copy data from the specified register into {\tt arg0} portion + * of {\tt data}. + */ +#define AC_ACCESS_REGISTER_WRITE_ARG0 0 +/* + * register: Copy data from {\tt arg0} portion of {\tt data} into the + * specified register. + */ +#define AC_ACCESS_REGISTER_WRITE_REGISTER 1 +/* + * Number of the register to access, as described in + * Table~\ref{tab:regno}. + * \RcsrDpc may be used as an alias for PC if this command is + * supported on a non-halted hart. + */ +#define AC_ACCESS_REGISTER_REGNO_OFFSET 0 +#define AC_ACCESS_REGISTER_REGNO_LENGTH 0x10 +#define AC_ACCESS_REGISTER_REGNO 0xffff +/* + * This is 1 to indicate Quick Access command. + */ +#define AC_QUICK_ACCESS_CMDTYPE_OFFSET 0x18 +#define AC_QUICK_ACCESS_CMDTYPE_LENGTH 8 +#define AC_QUICK_ACCESS_CMDTYPE 0xff000000U +/* + * This is 2 to indicate Access Memory Command. + */ +#define AC_ACCESS_MEMORY_CMDTYPE_OFFSET 0x18 +#define AC_ACCESS_MEMORY_CMDTYPE_LENGTH 8 +#define AC_ACCESS_MEMORY_CMDTYPE 0xff000000U +/* + * An implementation does not have to implement both virtual and + * physical accesses, but it must fail accesses that it doesn't + * support. + */ +#define AC_ACCESS_MEMORY_AAMVIRTUAL_OFFSET 0x17 +#define AC_ACCESS_MEMORY_AAMVIRTUAL_LENGTH 1 +#define AC_ACCESS_MEMORY_AAMVIRTUAL 0x800000 +/* + * physical: Addresses are physical (to the hart they are performed on). + */ +#define AC_ACCESS_MEMORY_AAMVIRTUAL_PHYSICAL 0 +/* + * virtual: Addresses are virtual, and translated the way they would be from + * M-mode, with \FcsrMstatusMprv set. + */ +#define AC_ACCESS_MEMORY_AAMVIRTUAL_VIRTUAL 1 +/* + * Debug Modules on systems without address translation (i.e. virtual addresses equal physical) + * may optionally allow \FacAccessmemoryAamvirtual set to 1, which would produce the same result as + * that same abstract command with \FacAccessmemoryAamvirtual cleared. + */ +#define AC_ACCESS_MEMORY_AAMSIZE_OFFSET 0x14 +#define AC_ACCESS_MEMORY_AAMSIZE_LENGTH 3 +#define AC_ACCESS_MEMORY_AAMSIZE 0x700000 +/* + * 8bit: Access the lowest 8 bits of the memory location. + */ +#define AC_ACCESS_MEMORY_AAMSIZE_8BIT 0 +/* + * 16bit: Access the lowest 16 bits of the memory location. + */ +#define AC_ACCESS_MEMORY_AAMSIZE_16BIT 1 +/* + * 32bit: Access the lowest 32 bits of the memory location. + */ +#define AC_ACCESS_MEMORY_AAMSIZE_32BIT 2 +/* + * 64bit: Access the lowest 64 bits of the memory location. + */ +#define AC_ACCESS_MEMORY_AAMSIZE_64BIT 3 +/* + * 128bit: Access the lowest 128 bits of the memory location. + */ +#define AC_ACCESS_MEMORY_AAMSIZE_128BIT 4 +/* + * After a memory access has completed, if this bit is 1, increment + * {\tt arg1} (which contains the address used) by the number of bytes + * encoded in \FacAccessmemoryAamsize. + * + * Supporting this variant is optional, but highly recommended for + * performance reasons. + */ +#define AC_ACCESS_MEMORY_AAMPOSTINCREMENT_OFFSET 0x13 +#define AC_ACCESS_MEMORY_AAMPOSTINCREMENT_LENGTH 1 +#define AC_ACCESS_MEMORY_AAMPOSTINCREMENT 0x80000 +#define AC_ACCESS_MEMORY_WRITE_OFFSET 0x10 +#define AC_ACCESS_MEMORY_WRITE_LENGTH 1 +#define AC_ACCESS_MEMORY_WRITE 0x10000 +/* + * arg0: Copy data from the memory location specified in {\tt arg1} into + * the low bits of {\tt arg0}. The value of the remaining bits of + * {\tt arg0} are \unspecified. + */ +#define AC_ACCESS_MEMORY_WRITE_ARG0 0 +/* + * memory: Copy data from the low bits of {\tt arg0} into the memory + * location specified in {\tt arg1}. + */ +#define AC_ACCESS_MEMORY_WRITE_MEMORY 1 +/* + * These bits are reserved for target-specific uses. + */ +#define AC_ACCESS_MEMORY_TARGET_SPECIFIC_OFFSET 0xe +#define AC_ACCESS_MEMORY_TARGET_SPECIFIC_LENGTH 2 +#define AC_ACCESS_MEMORY_TARGET_SPECIFIC 0xc000 +#define VIRT_PRIV virtual +/* + * Contains the virtualization mode the hart was operating in when Debug + * Mode was entered. The encoding is described in Table \ref{tab:privmode}, + * and matches the virtualization mode encoding from the Privileged Spec. + * A user can write this value to change the hart's virtualization mode + * when exiting Debug Mode. + */ +#define VIRT_PRIV_V_OFFSET 2 +#define VIRT_PRIV_V_LENGTH 1 +#define VIRT_PRIV_V 4 +/* + * Contains the privilege mode the hart was operating in when Debug + * Mode was entered. The encoding is described in Table + * \ref{tab:privmode}, and matches the privilege mode encoding from + * the Privileged Spec. A user can write this + * value to change the hart's privilege mode when exiting Debug Mode. + */ +#define VIRT_PRIV_PRV_OFFSET 0 +#define VIRT_PRIV_PRV_LENGTH 2 +#define VIRT_PRIV_PRV 3 +#define DMI_SERCS 0x34 +/* + * Number of supported serial ports. + */ +#define DMI_SERCS_SERIALCOUNT_OFFSET 0x1c +#define DMI_SERCS_SERIALCOUNT_LENGTH 4 +#define DMI_SERCS_SERIALCOUNT 0xf0000000U +/* + * Select which serial port is accessed by \RdmiSerrx and \RdmiSertx. + */ +#define DMI_SERCS_SERIAL_OFFSET 0x18 +#define DMI_SERCS_SERIAL_LENGTH 3 +#define DMI_SERCS_SERIAL 0x7000000 +#define DMI_SERCS_ERROR7_OFFSET 0x17 +#define DMI_SERCS_ERROR7_LENGTH 1 +#define DMI_SERCS_ERROR7 0x800000 +#define DMI_SERCS_VALID7_OFFSET 0x16 +#define DMI_SERCS_VALID7_LENGTH 1 +#define DMI_SERCS_VALID7 0x400000 +#define DMI_SERCS_FULL7_OFFSET 0x15 +#define DMI_SERCS_FULL7_LENGTH 1 +#define DMI_SERCS_FULL7 0x200000 +#define DMI_SERCS_ERROR6_OFFSET 0x14 +#define DMI_SERCS_ERROR6_LENGTH 1 +#define DMI_SERCS_ERROR6 0x100000 +#define DMI_SERCS_VALID6_OFFSET 0x13 +#define DMI_SERCS_VALID6_LENGTH 1 +#define DMI_SERCS_VALID6 0x80000 +#define DMI_SERCS_FULL6_OFFSET 0x12 +#define DMI_SERCS_FULL6_LENGTH 1 +#define DMI_SERCS_FULL6 0x40000 +#define DMI_SERCS_ERROR5_OFFSET 0x11 +#define DMI_SERCS_ERROR5_LENGTH 1 +#define DMI_SERCS_ERROR5 0x20000 +#define DMI_SERCS_VALID5_OFFSET 0x10 +#define DMI_SERCS_VALID5_LENGTH 1 +#define DMI_SERCS_VALID5 0x10000 +#define DMI_SERCS_FULL5_OFFSET 0xf +#define DMI_SERCS_FULL5_LENGTH 1 +#define DMI_SERCS_FULL5 0x8000 +#define DMI_SERCS_ERROR4_OFFSET 0xe +#define DMI_SERCS_ERROR4_LENGTH 1 +#define DMI_SERCS_ERROR4 0x4000 +#define DMI_SERCS_VALID4_OFFSET 0xd +#define DMI_SERCS_VALID4_LENGTH 1 +#define DMI_SERCS_VALID4 0x2000 +#define DMI_SERCS_FULL4_OFFSET 0xc +#define DMI_SERCS_FULL4_LENGTH 1 +#define DMI_SERCS_FULL4 0x1000 +#define DMI_SERCS_ERROR3_OFFSET 0xb +#define DMI_SERCS_ERROR3_LENGTH 1 +#define DMI_SERCS_ERROR3 0x800 +#define DMI_SERCS_VALID3_OFFSET 0xa +#define DMI_SERCS_VALID3_LENGTH 1 +#define DMI_SERCS_VALID3 0x400 +#define DMI_SERCS_FULL3_OFFSET 9 +#define DMI_SERCS_FULL3_LENGTH 1 +#define DMI_SERCS_FULL3 0x200 +#define DMI_SERCS_ERROR2_OFFSET 8 +#define DMI_SERCS_ERROR2_LENGTH 1 +#define DMI_SERCS_ERROR2 0x100 +#define DMI_SERCS_VALID2_OFFSET 7 +#define DMI_SERCS_VALID2_LENGTH 1 +#define DMI_SERCS_VALID2 0x80 +#define DMI_SERCS_FULL2_OFFSET 6 +#define DMI_SERCS_FULL2_LENGTH 1 +#define DMI_SERCS_FULL2 0x40 +#define DMI_SERCS_ERROR1_OFFSET 5 +#define DMI_SERCS_ERROR1_LENGTH 1 +#define DMI_SERCS_ERROR1 0x20 +#define DMI_SERCS_VALID1_OFFSET 4 +#define DMI_SERCS_VALID1_LENGTH 1 +#define DMI_SERCS_VALID1 0x10 +#define DMI_SERCS_FULL1_OFFSET 3 +#define DMI_SERCS_FULL1_LENGTH 1 +#define DMI_SERCS_FULL1 8 +/* + * 1 when the debugger-to-core queue for serial port 0 has + * over or underflowed. This bit will remain set until it is reset by + * writing 1 to this bit. + */ +#define DMI_SERCS_ERROR0_OFFSET 2 +#define DMI_SERCS_ERROR0_LENGTH 1 +#define DMI_SERCS_ERROR0 4 +/* + * 1 when the core-to-debugger queue for serial port 0 is not empty. + */ +#define DMI_SERCS_VALID0_OFFSET 1 +#define DMI_SERCS_VALID0_LENGTH 1 +#define DMI_SERCS_VALID0 2 +/* + * 1 when the debugger-to-core queue for serial port 0 is full. + */ +#define DMI_SERCS_FULL0_OFFSET 0 +#define DMI_SERCS_FULL0_LENGTH 1 +#define DMI_SERCS_FULL0 1 +#define DMI_SERTX 0x35 +#define DMI_SERTX_DATA_OFFSET 0 +#define DMI_SERTX_DATA_LENGTH 0x20 +#define DMI_SERTX_DATA 0xffffffffU +#define DMI_SERRX 0x36 +#define DMI_SERRX_DATA_OFFSET 0 +#define DMI_SERRX_DATA_LENGTH 0x20 +#define DMI_SERRX_DATA 0xffffffffU diff --git a/vendor/riscv/riscv-isa-sim/riscv/debug_module.cc b/vendor/riscv/riscv-isa-sim/riscv/debug_module.cc new file mode 100644 index 0000000000..27dbe66ecb --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/debug_module.cc @@ -0,0 +1,926 @@ +#include <cassert> + +#include "simif.h" +#include "devices.h" +#include "debug_module.h" +#include "debug_defines.h" +#include "opcodes.h" +#include "mmu.h" + +#include "debug_rom/debug_rom.h" +#include "debug_rom_defines.h" + +#if 0 +# define D(x) x +#else +# define D(x) +#endif + +// Return the number of bits wide that a field has to be to encode up to n +// different values. +// 1->0, 2->1, 3->2, 4->2 +static unsigned field_width(unsigned n) +{ + unsigned i = 0; + n -= 1; + while (n) { + i++; + n >>= 1; + } + return i; +} + +///////////////////////// debug_module_t + +debug_module_t::debug_module_t(simif_t *sim, const debug_module_config_t &config) : + config(config), + program_buffer_bytes((config.support_impebreak ? 4 : 0) + 4*config.progbufsize), + debug_progbuf_start(debug_data_start - program_buffer_bytes), + debug_abstract_start(debug_progbuf_start - debug_abstract_size*4), + custom_base(0), + sim(sim), + // The spec lets a debugger select nonexistent harts. Create hart_state for + // them because I'm too lazy to add the code to just ignore accesses. + hart_state(1 << field_width(sim->get_cfg().max_hartid() + 1)), + hart_array_mask(sim->get_cfg().max_hartid() + 1), + rti_remaining(0) +{ + D(fprintf(stderr, "debug_data_start=0x%x\n", debug_data_start)); + D(fprintf(stderr, "debug_progbuf_start=0x%x\n", debug_progbuf_start)); + D(fprintf(stderr, "debug_abstract_start=0x%x\n", debug_abstract_start)); + + const unsigned max_procs = 1024; + if (sim->get_cfg().max_hartid() >= max_procs) { + fprintf(stderr, "Hart IDs must not exceed %u (%zu harts with max hart ID %zu requested)\n", + max_procs - 1, sim->get_cfg().nprocs(), sim->get_cfg().max_hartid()); + exit(1); + } + + program_buffer = new uint8_t[program_buffer_bytes]; + + memset(debug_rom_flags, 0, sizeof(debug_rom_flags)); + memset(program_buffer, 0, program_buffer_bytes); + memset(dmdata, 0, sizeof(dmdata)); + + if (config.support_impebreak) { + program_buffer[4*config.progbufsize] = ebreak(); + program_buffer[4*config.progbufsize+1] = ebreak() >> 8; + program_buffer[4*config.progbufsize+2] = ebreak() >> 16; + program_buffer[4*config.progbufsize+3] = ebreak() >> 24; + } + + write32(debug_rom_whereto, 0, + jal(ZERO, debug_abstract_start - DEBUG_ROM_WHERETO)); + + memset(debug_abstract, 0, sizeof(debug_abstract)); + + reset(); +} + +debug_module_t::~debug_module_t() +{ + delete[] program_buffer; +} + +void debug_module_t::reset() +{ + for (const auto& [hart_id, hart] : sim->get_harts()) { + hart->halt_request = hart->HR_NONE; + } + + memset(&dmcontrol, 0, sizeof(dmcontrol)); + + memset(&dmstatus, 0, sizeof(dmstatus)); + dmstatus.impebreak = config.support_impebreak; + dmstatus.authenticated = !config.require_authentication; + dmstatus.version = 2; + + memset(&abstractcs, 0, sizeof(abstractcs)); + abstractcs.datacount = sizeof(dmdata) / 4; + abstractcs.progbufsize = config.progbufsize; + + memset(&abstractauto, 0, sizeof(abstractauto)); + + memset(&sbcs, 0, sizeof(sbcs)); + if (config.max_sba_data_width > 0) { + sbcs.version = 1; + sbcs.asize = sizeof(reg_t) * 8; + } + if (config.max_sba_data_width >= 64) + sbcs.access64 = true; + if (config.max_sba_data_width >= 32) + sbcs.access32 = true; + if (config.max_sba_data_width >= 16) + sbcs.access16 = true; + if (config.max_sba_data_width >= 8) + sbcs.access8 = true; + + challenge = random(); +} + +void debug_module_t::add_device(bus_t *bus) { + bus->add_device(DEBUG_START, this); +} + +bool debug_module_t::load(reg_t addr, size_t len, uint8_t* bytes) +{ + addr = DEBUG_START + addr; + + if (addr >= DEBUG_ROM_ENTRY && + (addr + len) <= (DEBUG_ROM_ENTRY + debug_rom_raw_len)) { + memcpy(bytes, debug_rom_raw + addr - DEBUG_ROM_ENTRY, len); + return true; + } + + if (addr >= DEBUG_ROM_WHERETO && (addr + len) <= (DEBUG_ROM_WHERETO + 4)) { + memcpy(bytes, debug_rom_whereto + addr - DEBUG_ROM_WHERETO, len); + return true; + } + + if (addr >= DEBUG_ROM_FLAGS && ((addr + len) <= DEBUG_ROM_FLAGS + 1024)) { + memcpy(bytes, debug_rom_flags + addr - DEBUG_ROM_FLAGS, len); + return true; + } + + if (addr >= debug_abstract_start && ((addr + len) <= (debug_abstract_start + sizeof(debug_abstract)))) { + memcpy(bytes, debug_abstract + addr - debug_abstract_start, len); + return true; + } + + if (addr >= debug_data_start && (addr + len) <= (debug_data_start + sizeof(dmdata))) { + memcpy(bytes, dmdata + addr - debug_data_start, len); + return true; + } + + if (addr >= debug_progbuf_start && ((addr + len) <= (debug_progbuf_start + program_buffer_bytes))) { + memcpy(bytes, program_buffer + addr - debug_progbuf_start, len); + return true; + } + + D(fprintf(stderr, "ERROR: invalid load from debug module: %zd bytes at 0x%016" + PRIx64 "\n", len, addr)); + + return false; +} + +bool debug_module_t::store(reg_t addr, size_t len, const uint8_t* bytes) +{ + D( + switch (len) { + case 4: + fprintf(stderr, "store(addr=0x%lx, len=%d, bytes=0x%08x); " + "hartsel=0x%x\n", addr, (unsigned) len, *(uint32_t *) bytes, + dmcontrol.hartsel); + break; + default: + fprintf(stderr, "store(addr=0x%lx, len=%d, bytes=...); " + "hartsel=0x%x\n", addr, (unsigned) len, dmcontrol.hartsel); + break; + } + ); + + uint8_t id_bytes[4]; + uint32_t id = 0; + if (len == 4) { + memcpy(id_bytes, bytes, 4); + id = read32(id_bytes, 0); + } + + addr = DEBUG_START + addr; + + if (addr >= debug_data_start && (addr + len) <= (debug_data_start + sizeof(dmdata))) { + memcpy(dmdata + addr - debug_data_start, bytes, len); + return true; + } + + if (addr >= debug_progbuf_start && ((addr + len) <= (debug_progbuf_start + program_buffer_bytes))) { + memcpy(program_buffer + addr - debug_progbuf_start, bytes, len); + + return true; + } + + if (addr == DEBUG_ROM_HALTED) { + assert (len == 4); + if (!hart_state[id].halted) { + hart_state[id].halted = true; + if (hart_state[id].haltgroup) { + for (const auto& [hart_id, hart] : sim->get_harts()) { + if (!hart_state[hart_id].halted && + hart_state[hart_id].haltgroup == hart_state[id].haltgroup) { + hart->halt_request = hart->HR_GROUP; + // TODO: What if the debugger comes and writes dmcontrol before the + // halt occurs? + } + } + } + } + if (selected_hart_id() == id) { + if (0 == (debug_rom_flags[id] & (1 << DEBUG_ROM_FLAG_GO))) { + abstract_command_completed = true; + } + } + return true; + } + + if (addr == DEBUG_ROM_GOING) { + assert(len == 4); + debug_rom_flags[id] &= ~(1 << DEBUG_ROM_FLAG_GO); + return true; + } + + if (addr == DEBUG_ROM_RESUMING) { + assert (len == 4); + hart_state[id].halted = false; + hart_state[id].resumeack = true; + debug_rom_flags[id] &= ~(1 << DEBUG_ROM_FLAG_RESUME); + return true; + } + + if (addr == DEBUG_ROM_EXCEPTION) { + if (abstractcs.cmderr == CMDERR_NONE) { + abstractcs.cmderr = CMDERR_EXCEPTION; + } + return true; + } + + D(fprintf(stderr, "ERROR: invalid store to debug module: %zd bytes at 0x%016" + PRIx64 "\n", len, addr)); + return false; +} + +void debug_module_t::write32(uint8_t *memory, unsigned int index, uint32_t value) +{ + uint8_t* base = memory + index * 4; + base[0] = value & 0xff; + base[1] = (value >> 8) & 0xff; + base[2] = (value >> 16) & 0xff; + base[3] = (value >> 24) & 0xff; +} + +uint32_t debug_module_t::read32(uint8_t *memory, unsigned int index) +{ + uint8_t* base = memory + index * 4; + uint32_t value = ((uint32_t) base[0]) | + (((uint32_t) base[1]) << 8) | + (((uint32_t) base[2]) << 16) | + (((uint32_t) base[3]) << 24); + return value; +} + +bool debug_module_t::hart_selected(unsigned hartid) const +{ + return hartid == selected_hart_id() || (dmcontrol.hasel && hart_array_mask[hartid]); +} + +unsigned debug_module_t::sb_access_bits() +{ + return 8 << sbcs.sbaccess; +} + +void debug_module_t::sb_autoincrement() +{ + if (!sbcs.autoincrement || !config.max_sba_data_width) + return; + + uint64_t value = sbaddress[0] + sb_access_bits() / 8; + sbaddress[0] = value; + uint32_t carry = value >> 32; + + value = sbaddress[1] + carry; + sbaddress[1] = value; + carry = value >> 32; + + value = sbaddress[2] + carry; + sbaddress[2] = value; + carry = value >> 32; + + sbaddress[3] += carry; +} + +void debug_module_t::sb_read() +{ + reg_t address = ((uint64_t) sbaddress[1] << 32) | sbaddress[0]; + try { + if (sbcs.sbaccess == 0 && config.max_sba_data_width >= 8) { + sbdata[0] = sim->debug_mmu->load<uint8_t>(address); + } else if (sbcs.sbaccess == 1 && config.max_sba_data_width >= 16) { + sbdata[0] = sim->debug_mmu->load<uint16_t>(address); + } else if (sbcs.sbaccess == 2 && config.max_sba_data_width >= 32) { + sbdata[0] = sim->debug_mmu->load<uint32_t>(address); + } else if (sbcs.sbaccess == 3 && config.max_sba_data_width >= 64) { + uint64_t value = sim->debug_mmu->load<uint64_t>(address); + sbdata[0] = value; + sbdata[1] = value >> 32; + } else { + sbcs.error = 3; + } + } catch (trap_load_access_fault& t) { + sbcs.error = 2; + } +} + +void debug_module_t::sb_write() +{ + reg_t address = ((uint64_t) sbaddress[1] << 32) | sbaddress[0]; + D(fprintf(stderr, "sb_write() 0x%x @ 0x%lx\n", sbdata[0], address)); + if (sbcs.sbaccess == 0 && config.max_sba_data_width >= 8) { + sim->debug_mmu->store<uint8_t>(address, sbdata[0]); + } else if (sbcs.sbaccess == 1 && config.max_sba_data_width >= 16) { + sim->debug_mmu->store<uint16_t>(address, sbdata[0]); + } else if (sbcs.sbaccess == 2 && config.max_sba_data_width >= 32) { + sim->debug_mmu->store<uint32_t>(address, sbdata[0]); + } else if (sbcs.sbaccess == 3 && config.max_sba_data_width >= 64) { + sim->debug_mmu->store<uint64_t>(address, + (((uint64_t) sbdata[1]) << 32) | sbdata[0]); + } else { + sbcs.error = 3; + } +} + +bool debug_module_t::dmi_read(unsigned address, uint32_t *value) +{ + uint32_t result = 0; + D(fprintf(stderr, "dmi_read(0x%x) -> ", address)); + if (address >= DM_DATA0 && address < DM_DATA0 + abstractcs.datacount) { + unsigned i = address - DM_DATA0; + result = read32(dmdata, i); + if (abstractcs.busy) { + result = -1; + D(fprintf(stderr, "\ndmi_read(0x%02x (data[%d]) -> -1 because abstractcs.busy==true\n", address, i)); + } + + if (abstractcs.busy && abstractcs.cmderr == CMDERR_NONE) { + abstractcs.cmderr = CMDERR_BUSY; + } + + if (!abstractcs.busy && ((abstractauto.autoexecdata >> i) & 1)) { + perform_abstract_command(); + } + } else if (address >= DM_PROGBUF0 && address < DM_PROGBUF0 + config.progbufsize) { + unsigned i = address - DM_PROGBUF0; + result = read32(program_buffer, i); + if (abstractcs.busy) { + result = -1; + D(fprintf(stderr, "\ndmi_read(0x%02x (progbuf[%d]) -> -1 because abstractcs.busy==true\n", address, i)); + } + if (!abstractcs.busy && ((abstractauto.autoexecprogbuf >> i) & 1)) { + perform_abstract_command(); + } + + } else { + switch (address) { + case DM_DMCONTROL: + { + result = set_field(result, DM_DMCONTROL_HALTREQ, dmcontrol.haltreq); + result = set_field(result, DM_DMCONTROL_RESUMEREQ, dmcontrol.resumereq); + result = set_field(result, DM_DMCONTROL_HARTSELHI, + dmcontrol.hartsel >> DM_DMCONTROL_HARTSELLO_LENGTH); + result = set_field(result, DM_DMCONTROL_HASEL, dmcontrol.hasel); + result = set_field(result, DM_DMCONTROL_HARTSELLO, dmcontrol.hartsel); + result = set_field(result, DM_DMCONTROL_HARTRESET, dmcontrol.hartreset); + result = set_field(result, DM_DMCONTROL_NDMRESET, dmcontrol.ndmreset); + result = set_field(result, DM_DMCONTROL_DMACTIVE, dmcontrol.dmactive); + } + break; + case DM_DMSTATUS: + { + dmstatus.allhalted = true; + dmstatus.anyhalted = false; + dmstatus.allrunning = true; + dmstatus.anyrunning = false; + dmstatus.allnonexistant = true; + dmstatus.allresumeack = true; + dmstatus.anyresumeack = false; + for (const auto& [hart_id, hart] : sim->get_harts()) { + if (hart_selected(hart_id)) { + dmstatus.allnonexistant = false; + if (hart_state[hart_id].resumeack) { + dmstatus.anyresumeack = true; + } else { + dmstatus.allresumeack = false; + } + if (hart_state[hart_id].halted) { + dmstatus.allrunning = false; + dmstatus.anyhalted = true; + } else { + dmstatus.allhalted = false; + dmstatus.anyrunning = true; + } + } + } + + // We don't allow selecting non-existant harts through + // hart_array_mask, so the only way it's possible is by writing a + // non-existant hartsel. + dmstatus.anynonexistant = dmcontrol.hartsel >= sim->get_cfg().nprocs(); + + dmstatus.allunavail = false; + dmstatus.anyunavail = false; + + result = set_field(result, DM_DMSTATUS_IMPEBREAK, + dmstatus.impebreak); + result = set_field(result, DM_DMSTATUS_ALLHAVERESET, selected_hart_state().havereset); + result = set_field(result, DM_DMSTATUS_ANYHAVERESET, selected_hart_state().havereset); + result = set_field(result, DM_DMSTATUS_ALLNONEXISTENT, dmstatus.allnonexistant); + result = set_field(result, DM_DMSTATUS_ALLUNAVAIL, dmstatus.allunavail); + result = set_field(result, DM_DMSTATUS_ALLRUNNING, dmstatus.allrunning); + result = set_field(result, DM_DMSTATUS_ALLHALTED, dmstatus.allhalted); + result = set_field(result, DM_DMSTATUS_ALLRESUMEACK, dmstatus.allresumeack); + result = set_field(result, DM_DMSTATUS_ANYNONEXISTENT, dmstatus.anynonexistant); + result = set_field(result, DM_DMSTATUS_ANYUNAVAIL, dmstatus.anyunavail); + result = set_field(result, DM_DMSTATUS_ANYRUNNING, dmstatus.anyrunning); + result = set_field(result, DM_DMSTATUS_ANYHALTED, dmstatus.anyhalted); + result = set_field(result, DM_DMSTATUS_ANYRESUMEACK, dmstatus.anyresumeack); + result = set_field(result, DM_DMSTATUS_AUTHENTICATED, dmstatus.authenticated); + result = set_field(result, DM_DMSTATUS_AUTHBUSY, dmstatus.authbusy); + result = set_field(result, DM_DMSTATUS_VERSION, dmstatus.version); + } + break; + case DM_ABSTRACTCS: + result = set_field(result, DM_ABSTRACTCS_CMDERR, abstractcs.cmderr); + result = set_field(result, DM_ABSTRACTCS_BUSY, abstractcs.busy); + result = set_field(result, DM_ABSTRACTCS_DATACOUNT, abstractcs.datacount); + result = set_field(result, DM_ABSTRACTCS_PROGBUFSIZE, + abstractcs.progbufsize); + break; + case DM_ABSTRACTAUTO: + result = set_field(result, DM_ABSTRACTAUTO_AUTOEXECPROGBUF, abstractauto.autoexecprogbuf); + result = set_field(result, DM_ABSTRACTAUTO_AUTOEXECDATA, abstractauto.autoexecdata); + break; + case DM_COMMAND: + result = 0; + break; + case DM_HARTINFO: + result = set_field(result, DM_HARTINFO_NSCRATCH, 1); + result = set_field(result, DM_HARTINFO_DATAACCESS, 1); + result = set_field(result, DM_HARTINFO_DATASIZE, abstractcs.datacount); + result = set_field(result, DM_HARTINFO_DATAADDR, debug_data_start); + break; + case DM_HAWINDOWSEL: + result = hawindowsel; + break; + case DM_HAWINDOW: + { + unsigned base = hawindowsel * 32; + for (unsigned i = 0; i < 32; i++) { + unsigned n = base + i; + if (n < sim->get_cfg().nprocs() && hart_array_mask[sim->get_cfg().hartids()[n]]) { + result |= 1 << i; + } + } + } + break; + case DM_SBCS: + result = set_field(result, DM_SBCS_SBVERSION, sbcs.version); + result = set_field(result, DM_SBCS_SBREADONADDR, sbcs.readonaddr); + result = set_field(result, DM_SBCS_SBACCESS, sbcs.sbaccess); + result = set_field(result, DM_SBCS_SBAUTOINCREMENT, sbcs.autoincrement); + result = set_field(result, DM_SBCS_SBREADONDATA, sbcs.readondata); + result = set_field(result, DM_SBCS_SBERROR, sbcs.error); + result = set_field(result, DM_SBCS_SBASIZE, sbcs.asize); + result = set_field(result, DM_SBCS_SBACCESS128, sbcs.access128); + result = set_field(result, DM_SBCS_SBACCESS64, sbcs.access64); + result = set_field(result, DM_SBCS_SBACCESS32, sbcs.access32); + result = set_field(result, DM_SBCS_SBACCESS16, sbcs.access16); + result = set_field(result, DM_SBCS_SBACCESS8, sbcs.access8); + break; + case DM_SBADDRESS0: + result = sbaddress[0]; + break; + case DM_SBADDRESS1: + result = sbaddress[1]; + break; + case DM_SBADDRESS2: + result = sbaddress[2]; + break; + case DM_SBADDRESS3: + result = sbaddress[3]; + break; + case DM_SBDATA0: + result = sbdata[0]; + if (sbcs.error == 0) { + if (sbcs.readondata) { + sb_read(); + } + if (sbcs.error == 0) { + sb_autoincrement(); + } + } + break; + case DM_SBDATA1: + result = sbdata[1]; + break; + case DM_SBDATA2: + result = sbdata[2]; + break; + case DM_SBDATA3: + result = sbdata[3]; + break; + case DM_AUTHDATA: + result = challenge; + break; + case DM_DMCS2: + result = set_field(result, DM_DMCS2_GROUP, selected_hart_state().haltgroup); + break; + default: + result = 0; + D(fprintf(stderr, "Unexpected. Returning Error.")); + return false; + } + } + D(fprintf(stderr, "0x%x\n", result)); + *value = result; + return true; +} + +void debug_module_t::run_test_idle() +{ + if (rti_remaining > 0) { + rti_remaining--; + } + if (rti_remaining == 0 && abstractcs.busy && abstract_command_completed) { + abstractcs.busy = false; + } +} + +static bool is_fpu_reg(unsigned regno) +{ + return (regno >= 0x1020 && regno <= 0x103f) || regno == CSR_FFLAGS || + regno == CSR_FRM || regno == CSR_FCSR; +} + +bool debug_module_t::perform_abstract_command() +{ + if (abstractcs.cmderr != CMDERR_NONE) + return true; + if (abstractcs.busy) { + abstractcs.cmderr = CMDERR_BUSY; + return true; + } + + if ((command >> 24) == 0) { + // register access + unsigned size = get_field(command, AC_ACCESS_REGISTER_AARSIZE); + bool write = get_field(command, AC_ACCESS_REGISTER_WRITE); + unsigned regno = get_field(command, AC_ACCESS_REGISTER_REGNO); + + if (!selected_hart_state().halted) { + abstractcs.cmderr = CMDERR_HALTRESUME; + return true; + } + + unsigned i = 0; + if (get_field(command, AC_ACCESS_REGISTER_TRANSFER)) { + + if (is_fpu_reg(regno)) { + // Save S0 + write32(debug_abstract, i++, csrw(S0, CSR_DSCRATCH0)); + // Save mstatus + write32(debug_abstract, i++, csrr(S0, CSR_MSTATUS)); + write32(debug_abstract, i++, csrw(S0, CSR_DSCRATCH1)); + // Set mstatus.fs + assert((MSTATUS_FS & 0xfff) == 0); + write32(debug_abstract, i++, lui(S0, MSTATUS_FS >> 12)); + write32(debug_abstract, i++, csrrs(ZERO, S0, CSR_MSTATUS)); + } + + if (regno < 0x1000 && config.support_abstract_csr_access) { + if (!is_fpu_reg(regno)) { + write32(debug_abstract, i++, csrw(S0, CSR_DSCRATCH0)); + } + + if (write) { + switch (size) { + case 2: + write32(debug_abstract, i++, lw(S0, ZERO, debug_data_start)); + break; + case 3: + write32(debug_abstract, i++, ld(S0, ZERO, debug_data_start)); + break; + default: + abstractcs.cmderr = CMDERR_NOTSUP; + return true; + } + write32(debug_abstract, i++, csrw(S0, regno)); + + } else { + write32(debug_abstract, i++, csrr(S0, regno)); + switch (size) { + case 2: + write32(debug_abstract, i++, sw(S0, ZERO, debug_data_start)); + break; + case 3: + write32(debug_abstract, i++, sd(S0, ZERO, debug_data_start)); + break; + default: + abstractcs.cmderr = CMDERR_NOTSUP; + return true; + } + } + if (!is_fpu_reg(regno)) { + write32(debug_abstract, i++, csrr(S0, CSR_DSCRATCH0)); + } + + } else if (regno >= 0x1000 && regno < 0x1020) { + unsigned regnum = regno - 0x1000; + + switch (size) { + case 2: + if (write) + write32(debug_abstract, i++, lw(regnum, ZERO, debug_data_start)); + else + write32(debug_abstract, i++, sw(regnum, ZERO, debug_data_start)); + break; + case 3: + if (write) + write32(debug_abstract, i++, ld(regnum, ZERO, debug_data_start)); + else + write32(debug_abstract, i++, sd(regnum, ZERO, debug_data_start)); + break; + default: + abstractcs.cmderr = CMDERR_NOTSUP; + return true; + } + + if (regno == 0x1000 + S0 && write) { + /* + * The exception handler starts out be restoring dscratch to s0, + * which was saved before executing the abstract memory region. Since + * we just wrote s0, also make sure to write that same value to + * dscratch in case an exception occurs in a program buffer that + * might be executed later. + */ + write32(debug_abstract, i++, csrw(S0, CSR_DSCRATCH0)); + } + + } else if (regno >= 0x1020 && regno < 0x1040 && config.support_abstract_fpr_access) { + unsigned fprnum = regno - 0x1020; + + if (write) { + switch (size) { + case 2: + write32(debug_abstract, i++, flw(fprnum, ZERO, debug_data_start)); + break; + case 3: + write32(debug_abstract, i++, fld(fprnum, ZERO, debug_data_start)); + break; + default: + abstractcs.cmderr = CMDERR_NOTSUP; + return true; + } + + } else { + switch (size) { + case 2: + write32(debug_abstract, i++, fsw(fprnum, ZERO, debug_data_start)); + break; + case 3: + write32(debug_abstract, i++, fsd(fprnum, ZERO, debug_data_start)); + break; + default: + abstractcs.cmderr = CMDERR_NOTSUP; + return true; + } + } + + } else if (regno >= 0xc000 && (regno & 1) == 1) { + // Support odd-numbered custom registers, to allow for debugger testing. + unsigned custom_number = regno - 0xc000; + abstractcs.cmderr = CMDERR_NONE; + if (write) { + // Writing V to custom register N will cause future reads of N to + // return V, reads of N-1 will return V-1, etc. + custom_base = read32(dmdata, 0) - custom_number; + } else { + write32(dmdata, 0, custom_number + custom_base); + write32(dmdata, 1, 0); + } + return true; + + } else { + abstractcs.cmderr = CMDERR_NOTSUP; + return true; + } + + if (is_fpu_reg(regno)) { + // restore mstatus + write32(debug_abstract, i++, csrr(S0, CSR_DSCRATCH1)); + write32(debug_abstract, i++, csrw(S0, CSR_MSTATUS)); + // restore s0 + write32(debug_abstract, i++, csrr(S0, CSR_DSCRATCH0)); + } + } + + if (get_field(command, AC_ACCESS_REGISTER_POSTEXEC)) { + write32(debug_abstract, i, + jal(ZERO, debug_progbuf_start - debug_abstract_start - 4 * i)); + i++; + } else { + write32(debug_abstract, i++, ebreak()); + } + + debug_rom_flags[selected_hart_id()] |= 1 << DEBUG_ROM_FLAG_GO; + rti_remaining = config.abstract_rti; + abstract_command_completed = false; + + abstractcs.busy = true; + } else { + abstractcs.cmderr = CMDERR_NOTSUP; + } + return true; +} + +bool debug_module_t::dmi_write(unsigned address, uint32_t value) +{ + D(fprintf(stderr, "dmi_write(0x%x, 0x%x)\n", address, value)); + + if (!dmstatus.authenticated && address != DM_AUTHDATA && + address != DM_DMCONTROL) + return false; + + if (address >= DM_DATA0 && address < DM_DATA0 + abstractcs.datacount) { + unsigned i = address - DM_DATA0; + if (!abstractcs.busy) + write32(dmdata, address - DM_DATA0, value); + + if (abstractcs.busy && abstractcs.cmderr == CMDERR_NONE) { + abstractcs.cmderr = CMDERR_BUSY; + } + + if (!abstractcs.busy && ((abstractauto.autoexecdata >> i) & 1)) { + perform_abstract_command(); + } + return true; + + } else if (address >= DM_PROGBUF0 && address < DM_PROGBUF0 + config.progbufsize) { + unsigned i = address - DM_PROGBUF0; + + if (!abstractcs.busy) + write32(program_buffer, i, value); + + if (!abstractcs.busy && ((abstractauto.autoexecprogbuf >> i) & 1)) { + perform_abstract_command(); + } + return true; + + } else { + switch (address) { + case DM_DMCONTROL: + { + if (!dmcontrol.dmactive && get_field(value, DM_DMCONTROL_DMACTIVE)) + reset(); + dmcontrol.dmactive = get_field(value, DM_DMCONTROL_DMACTIVE); + if (!dmstatus.authenticated || !dmcontrol.dmactive) + return true; + + dmcontrol.haltreq = get_field(value, DM_DMCONTROL_HALTREQ); + dmcontrol.resumereq = get_field(value, DM_DMCONTROL_RESUMEREQ); + dmcontrol.hartreset = get_field(value, DM_DMCONTROL_HARTRESET); + dmcontrol.ndmreset = get_field(value, DM_DMCONTROL_NDMRESET); + if (config.support_hasel) + dmcontrol.hasel = get_field(value, DM_DMCONTROL_HASEL); + else + dmcontrol.hasel = 0; + dmcontrol.hartsel = get_field(value, DM_DMCONTROL_HARTSELHI) << + DM_DMCONTROL_HARTSELLO_LENGTH; + dmcontrol.hartsel |= get_field(value, DM_DMCONTROL_HARTSELLO); + dmcontrol.hartsel = std::min(size_t(dmcontrol.hartsel), sim->get_cfg().nprocs() - 1); + for (const auto& [hart_id, hart] : sim->get_harts()) { + if (hart_selected(hart_id)) { + if (get_field(value, DM_DMCONTROL_ACKHAVERESET)) { + hart_state[hart_id].havereset = false; + } + hart->halt_request = dmcontrol.haltreq ? hart->HR_REGULAR : hart->HR_NONE; + if (dmcontrol.haltreq) { + D(fprintf(stderr, "halt hart %d\n", hart_id)); + } + if (dmcontrol.resumereq) { + D(fprintf(stderr, "resume hart %d\n", hart_id)); + debug_rom_flags[hart_id] |= (1 << DEBUG_ROM_FLAG_RESUME); + hart_state[hart_id].resumeack = false; + } + if (dmcontrol.hartreset) { + hart->reset(); + } + } + } + + if (dmcontrol.ndmreset) { + for (const auto& [hart_id, hart] : sim->get_harts()) { + hart->reset(); + } + } + } + return true; + + case DM_COMMAND: + command = value; + return perform_abstract_command(); + + case DM_HAWINDOWSEL: + hawindowsel = value & ((1U<<field_width(hart_array_mask.size()))-1); + return true; + + case DM_HAWINDOW: + { + unsigned base = hawindowsel * 32; + for (unsigned i = 0; i < 32; i++) { + unsigned n = base + i; + if (n < sim->get_cfg().nprocs()) { + hart_array_mask[sim->get_cfg().hartids()[n]] = (value >> i) & 1; + } + } + } + return true; + + case DM_ABSTRACTCS: + abstractcs.cmderr = (cmderr_t) (((uint32_t) (abstractcs.cmderr)) & (~(uint32_t)(get_field(value, DM_ABSTRACTCS_CMDERR)))); + return true; + + case DM_ABSTRACTAUTO: + abstractauto.autoexecprogbuf = get_field(value, + DM_ABSTRACTAUTO_AUTOEXECPROGBUF); + abstractauto.autoexecdata = get_field(value, + DM_ABSTRACTAUTO_AUTOEXECDATA); + return true; + case DM_SBCS: + sbcs.readonaddr = get_field(value, DM_SBCS_SBREADONADDR); + sbcs.sbaccess = get_field(value, DM_SBCS_SBACCESS); + sbcs.autoincrement = get_field(value, DM_SBCS_SBAUTOINCREMENT); + sbcs.readondata = get_field(value, DM_SBCS_SBREADONDATA); + sbcs.error &= ~get_field(value, DM_SBCS_SBERROR); + return true; + case DM_SBADDRESS0: + sbaddress[0] = value; + if (sbcs.error == 0 && sbcs.readonaddr) { + sb_read(); + sb_autoincrement(); + } + return true; + case DM_SBADDRESS1: + sbaddress[1] = value; + return true; + case DM_SBADDRESS2: + sbaddress[2] = value; + return true; + case DM_SBADDRESS3: + sbaddress[3] = value; + return true; + case DM_SBDATA0: + sbdata[0] = value; + if (sbcs.error == 0) { + sb_write(); + if (sbcs.error == 0) { + sb_autoincrement(); + } + } + return true; + case DM_SBDATA1: + sbdata[1] = value; + return true; + case DM_SBDATA2: + sbdata[2] = value; + return true; + case DM_SBDATA3: + sbdata[3] = value; + return true; + case DM_AUTHDATA: + D(fprintf(stderr, "debug authentication: got 0x%x; 0x%x unlocks\n", value, + challenge + secret)); + if (config.require_authentication) { + if (value == challenge + secret) { + dmstatus.authenticated = true; + } else { + dmstatus.authenticated = false; + challenge = random(); + } + } + return true; + case DM_DMCS2: + if (config.support_haltgroups && + get_field(value, DM_DMCS2_HGWRITE) && + get_field(value, DM_DMCS2_GROUPTYPE) == 0) { + selected_hart_state().haltgroup = get_field(value, DM_DMCS2_GROUP); + } + return true; + } + } + return false; +} + +void debug_module_t::proc_reset(unsigned id) +{ + hart_state[id].havereset = true; + hart_state[id].halted = false; + hart_state[id].haltgroup = 0; +} + +hart_debug_state_t& debug_module_t::selected_hart_state() +{ + return hart_state[selected_hart_id()]; +} + +size_t debug_module_t::selected_hart_id() const +{ + return sim->get_cfg().hartids().at(dmcontrol.hartsel); +} diff --git a/vendor/riscv/riscv-isa-sim/riscv/debug_module.h b/vendor/riscv/riscv-isa-sim/riscv/debug_module.h new file mode 100644 index 0000000000..0a62d77585 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/debug_module.h @@ -0,0 +1,192 @@ +// See LICENSE for license details. +#ifndef _RISCV_DEBUG_MODULE_H +#define _RISCV_DEBUG_MODULE_H + +#include <set> +#include <vector> + +#include "abstract_device.h" + +class simif_t; +class bus_t; +class processor_t; + +typedef struct { + // Size of program_buffer in 32-bit words, as exposed to the rest of the + // world. + unsigned progbufsize; + unsigned max_sba_data_width; + bool require_authentication; + unsigned abstract_rti; + bool support_hasel; + bool support_abstract_csr_access; + bool support_abstract_fpr_access; + bool support_haltgroups; + bool support_impebreak; +} debug_module_config_t; + +typedef struct { + bool haltreq; + bool resumereq; + bool hasel; + unsigned hartsel; + bool hartreset; + bool dmactive; + bool ndmreset; +} dmcontrol_t; + +typedef struct { + bool impebreak; + bool allhavereset; + bool anyhavereset; + bool allnonexistant; + bool anynonexistant; + bool allunavail; + bool anyunavail; + bool allrunning; + bool anyrunning; + bool allhalted; + bool anyhalted; + bool allresumeack; + bool anyresumeack; + bool authenticated; + bool authbusy; + bool cfgstrvalid; + unsigned version; +} dmstatus_t; + +typedef enum cmderr { + CMDERR_NONE = 0, + CMDERR_BUSY = 1, + CMDERR_NOTSUP = 2, + CMDERR_EXCEPTION = 3, + CMDERR_HALTRESUME = 4, + CMDERR_OTHER = 7 +} cmderr_t; + +typedef struct { + bool busy; + unsigned datacount; + unsigned progbufsize; + cmderr_t cmderr; +} abstractcs_t; + +typedef struct { + unsigned autoexecprogbuf; + unsigned autoexecdata; +} abstractauto_t; + +typedef struct { + unsigned version; + bool readonaddr; + unsigned sbaccess; + bool autoincrement; + bool readondata; + unsigned error; + unsigned asize; + bool access128; + bool access64; + bool access32; + bool access16; + bool access8; +} sbcs_t; + +typedef struct { + bool halted; + bool resumeack; + bool havereset; + uint8_t haltgroup; +} hart_debug_state_t; + +class debug_module_t : public abstract_device_t +{ + public: + /* + * If require_authentication is true, then a debugger must authenticate as + * follows: + * 1. Read a 32-bit value from authdata: + * 2. Write the value that was read back, plus one, to authdata. + * + * abstract_rti is extra run-test/idle cycles that each abstract command + * takes to execute. Useful for testing OpenOCD. + */ + debug_module_t(simif_t *sim, const debug_module_config_t &config); + ~debug_module_t(); + + void add_device(bus_t *bus); + + bool load(reg_t addr, size_t len, uint8_t* bytes); + bool store(reg_t addr, size_t len, const uint8_t* bytes); + + // Debug Module Interface that the debugger (in our case through JTAG DTM) + // uses to access the DM. + // Return true for success, false for failure. + bool dmi_read(unsigned address, uint32_t *value); + bool dmi_write(unsigned address, uint32_t value); + + // Called for every cycle the JTAG TAP spends in Run-Test/Idle. + void run_test_idle(); + + // Called when one of the attached harts was reset. + void proc_reset(unsigned id); + + private: + static const unsigned datasize = 2; + debug_module_config_t config; + // Actual size of the program buffer, which is 1 word bigger than we let on + // to implement the implicit ebreak at the end. + unsigned program_buffer_bytes; + static const unsigned debug_data_start = 0x380; + unsigned debug_progbuf_start; + + static const unsigned debug_abstract_size = 12; + unsigned debug_abstract_start; + // R/W this through custom registers, to allow debuggers to test that + // functionality. + unsigned custom_base; + + simif_t *sim; + + uint8_t debug_rom_whereto[4]; + uint8_t debug_abstract[debug_abstract_size * 4]; + uint8_t *program_buffer; + uint8_t dmdata[datasize * 4]; + + std::vector<hart_debug_state_t> hart_state; + uint8_t debug_rom_flags[1024]; + + void write32(uint8_t *rom, unsigned int index, uint32_t value); + uint32_t read32(uint8_t *rom, unsigned int index); + + void sb_autoincrement(); + void sb_read(); + void sb_write(); + unsigned sb_access_bits(); + + dmcontrol_t dmcontrol; + dmstatus_t dmstatus; + abstractcs_t abstractcs; + abstractauto_t abstractauto; + uint32_t command; + uint16_t hawindowsel; + std::vector<bool> hart_array_mask; + + sbcs_t sbcs; + uint32_t sbaddress[4]; + uint32_t sbdata[4]; + + uint32_t challenge; + const uint32_t secret = 1; + + bool hart_selected(unsigned hartid) const; + void reset(); + bool perform_abstract_command(); + + bool abstract_command_completed; + unsigned rti_remaining; + + size_t selected_hart_id() const; + hart_debug_state_t& selected_hart_state(); +}; + +#endif diff --git a/vendor/riscv/riscv-isa-sim/riscv/debug_rom_defines.h b/vendor/riscv/riscv-isa-sim/riscv/debug_rom_defines.h new file mode 100644 index 0000000000..616cf59045 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/debug_rom_defines.h @@ -0,0 +1,23 @@ +// See LICENSE file for license details. + +#ifndef DEBUG_ROM_DEFINES_H +#define DEBUG_ROM_DEFINES_H + +// These are implementation-specific addresses in the Debug Module +#define DEBUG_ROM_HALTED 0x100 +#define DEBUG_ROM_GOING 0x104 +#define DEBUG_ROM_RESUMING 0x108 +#define DEBUG_ROM_EXCEPTION 0x10C + +// Region of memory where each hart has 1 +// byte to read. +#define DEBUG_ROM_FLAGS 0x400 +#define DEBUG_ROM_FLAG_GO 0 +#define DEBUG_ROM_FLAG_RESUME 1 + +// These needs to match the link.ld +#define DEBUG_ROM_WHERETO 0x300 +#define DEBUG_ROM_ENTRY 0x800 +#define DEBUG_ROM_TVEC 0x808 + +#endif diff --git a/vendor/riscv/riscv-isa-sim/riscv/decode.h b/vendor/riscv/riscv-isa-sim/riscv/decode.h new file mode 100644 index 0000000000..a55b06946b --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/decode.h @@ -0,0 +1,243 @@ +// See LICENSE for license details. + +#ifndef _RISCV_DECODE_H +#define _RISCV_DECODE_H + +#if (-1 != ~0) || ((-1 >> 1) != -1) +# error spike requires a two''s-complement c++ implementation +#endif + +#include "../softfloat/softfloat_types.h" +#include <algorithm> +#include <cstdint> +#include <string.h> +#include <strings.h> +#include <cinttypes> +#include <type_traits> + +typedef int64_t sreg_t; +typedef uint64_t reg_t; +typedef float128_t freg_t; + +#ifdef __SIZEOF_INT128__ +typedef __int128 int128_t; +typedef unsigned __int128 uint128_t; +#endif + +const int NXPR = 32; +const int NFPR = 32; +const int NVPR = 32; +const int NCSR = 4096; + +#define X_RA 1 +#define X_SP 2 +#define X_S0 8 +#define X_A0 10 +#define X_A1 11 +#define X_Sn 16 + +#define VCSR_VXRM_SHIFT 1 +#define VCSR_VXRM (0x3 << VCSR_VXRM_SHIFT) + +#define VCSR_VXSAT_SHIFT 0 +#define VCSR_VXSAT (0x1 << VCSR_VXSAT_SHIFT) + +#define FP_RD_NE 0 +#define FP_RD_0 1 +#define FP_RD_DN 2 +#define FP_RD_UP 3 +#define FP_RD_NMM 4 + +#define FSR_RD_SHIFT 5 +#define FSR_RD (0x7 << FSR_RD_SHIFT) + +#define FPEXC_NX 0x01 +#define FPEXC_UF 0x02 +#define FPEXC_OF 0x04 +#define FPEXC_DZ 0x08 +#define FPEXC_NV 0x10 + +#define FSR_AEXC_SHIFT 0 +#define FSR_NVA (FPEXC_NV << FSR_AEXC_SHIFT) +#define FSR_OFA (FPEXC_OF << FSR_AEXC_SHIFT) +#define FSR_UFA (FPEXC_UF << FSR_AEXC_SHIFT) +#define FSR_DZA (FPEXC_DZ << FSR_AEXC_SHIFT) +#define FSR_NXA (FPEXC_NX << FSR_AEXC_SHIFT) +#define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA) + +#define insn_length(x) \ + (((x) & 0x03) < 0x03 ? 2 : \ + ((x) & 0x1f) < 0x1f ? 4 : \ + ((x) & 0x3f) < 0x3f ? 6 : \ + 8) +#define MAX_INSN_LENGTH 8 +#define PC_ALIGN 2 + +#define Sn(n) ((n) < 2 ? X_S0 + (n) : X_Sn + (n)) + +typedef uint64_t insn_bits_t; +class insn_t +{ +public: + insn_t() = default; + insn_t(insn_bits_t bits) : b(bits) {} + insn_bits_t bits() { return b; } + int length() { return insn_length(b); } + int64_t i_imm() { return xs(20, 12); } + int64_t shamt() { return x(20, 6); } + int64_t s_imm() { return x(7, 5) + (xs(25, 7) << 5); } + int64_t sb_imm() { return (x(8, 4) << 1) + (x(25, 6) << 5) + (x(7, 1) << 11) + (imm_sign() << 12); } + int64_t u_imm() { return xs(12, 20) << 12; } + int64_t uj_imm() { return (x(21, 10) << 1) + (x(20, 1) << 11) + (x(12, 8) << 12) + (imm_sign() << 20); } + uint64_t rd() { return x(7, 5); } + uint64_t rs1() { return x(15, 5); } + uint64_t rs2() { return x(20, 5); } + uint64_t rs3() { return x(27, 5); } + uint64_t rm() { return x(12, 3); } + uint64_t csr() { return x(20, 12); } + uint64_t iorw() { return x(20, 8); } + uint64_t bs() { return x(30, 2); } // Crypto ISE - SM4/AES32 byte select. + uint64_t rcon() { return x(20, 4); } // Crypto ISE - AES64 round const. + + int64_t rvc_imm() { return x(2, 5) + (xs(12, 1) << 5); } + int64_t rvc_zimm() { return x(2, 5) + (x(12, 1) << 5); } + int64_t rvc_addi4spn_imm() { return (x(6, 1) << 2) + (x(5, 1) << 3) + (x(11, 2) << 4) + (x(7, 4) << 6); } + int64_t rvc_addi16sp_imm() { return (x(6, 1) << 4) + (x(2, 1) << 5) + (x(5, 1) << 6) + (x(3, 2) << 7) + (xs(12, 1) << 9); } + int64_t rvc_lwsp_imm() { return (x(4, 3) << 2) + (x(12, 1) << 5) + (x(2, 2) << 6); } + int64_t rvc_ldsp_imm() { return (x(5, 2) << 3) + (x(12, 1) << 5) + (x(2, 3) << 6); } + int64_t rvc_swsp_imm() { return (x(9, 4) << 2) + (x(7, 2) << 6); } + int64_t rvc_sdsp_imm() { return (x(10, 3) << 3) + (x(7, 3) << 6); } + int64_t rvc_lw_imm() { return (x(6, 1) << 2) + (x(10, 3) << 3) + (x(5, 1) << 6); } + int64_t rvc_ld_imm() { return (x(10, 3) << 3) + (x(5, 2) << 6); } + int64_t rvc_j_imm() { return (x(3, 3) << 1) + (x(11, 1) << 4) + (x(2, 1) << 5) + (x(7, 1) << 6) + (x(6, 1) << 7) + (x(9, 2) << 8) + (x(8, 1) << 10) + (xs(12, 1) << 11); } + int64_t rvc_b_imm() { return (x(3, 2) << 1) + (x(10, 2) << 3) + (x(2, 1) << 5) + (x(5, 2) << 6) + (xs(12, 1) << 8); } + int64_t rvc_simm3() { return x(10, 3); } + uint64_t rvc_rd() { return rd(); } + uint64_t rvc_rs1() { return rd(); } + uint64_t rvc_rs2() { return x(2, 5); } + uint64_t rvc_rs1s() { return 8 + x(7, 3); } + uint64_t rvc_rs2s() { return 8 + x(2, 3); } + + uint64_t rvc_lbimm() { return (x(5, 1) << 1) + x(6, 1); } + uint64_t rvc_lhimm() { return (x(5, 1) << 1); } + + uint64_t rvc_r1sc() { return x(7, 3); } + uint64_t rvc_r2sc() { return x(2, 3); } + uint64_t rvc_rlist() { return x(4, 4); } + uint64_t rvc_spimm() { return x(2, 2) << 4; } + + uint64_t rvc_index() { return x(2, 8); } + + uint64_t v_vm() { return x(25, 1); } + uint64_t v_wd() { return x(26, 1); } + uint64_t v_nf() { return x(29, 3); } + uint64_t v_simm5() { return xs(15, 5); } + uint64_t v_zimm5() { return x(15, 5); } + uint64_t v_zimm10() { return x(20, 10); } + uint64_t v_zimm11() { return x(20, 11); } + uint64_t v_lmul() { return x(20, 2); } + uint64_t v_frac_lmul() { return x(22, 1); } + uint64_t v_sew() { return 1 << (x(23, 3) + 3); } + uint64_t v_width() { return x(12, 3); } + uint64_t v_mop() { return x(26, 2); } + uint64_t v_lumop() { return x(20, 5); } + uint64_t v_sumop() { return x(20, 5); } + uint64_t v_vta() { return x(26, 1); } + uint64_t v_vma() { return x(27, 1); } + uint64_t v_mew() { return x(28, 1); } + + uint64_t p_imm2() { return x(20, 2); } + uint64_t p_imm3() { return x(20, 3); } + uint64_t p_imm4() { return x(20, 4); } + uint64_t p_imm5() { return x(20, 5); } + uint64_t p_imm6() { return x(20, 6); } + + uint64_t zcmp_regmask() { + unsigned mask = 0; + uint64_t rlist = rvc_rlist(); + + if (rlist >= 4) + mask |= 1U << X_RA; + + for (reg_t i = 5; i <= rlist; i++) + mask |= 1U << Sn(i - 5); + + if (rlist == 15) + mask |= 1U << Sn(11); + + return mask; + } + + uint64_t zcmp_stack_adjustment(int xlen) { + reg_t stack_adj_base = 0; + switch (rvc_rlist()) { + case 15: + stack_adj_base += 16; + case 14: + if (xlen == 64) + stack_adj_base += 16; + case 13: + case 12: + stack_adj_base += 16; + case 11: + case 10: + if (xlen == 64) + stack_adj_base += 16; + case 9: + case 8: + stack_adj_base += 16; + case 7: + case 6: + if (xlen == 64) + stack_adj_base += 16; + case 5: + case 4: + stack_adj_base += 16; + break; + } + + return stack_adj_base + rvc_spimm(); + } + +private: + insn_bits_t b; + uint64_t x(int lo, int len) { return (b >> lo) & ((insn_bits_t(1) << len) - 1); } + uint64_t xs(int lo, int len) { return int64_t(b) << (64 - lo - len) >> (64 - len); } + uint64_t imm_sign() { return xs(31, 1); } +}; + +template <class T, size_t N, bool zero_reg> +class regfile_t +{ +public: + void write(size_t i, T value) + { + if (!zero_reg || i != 0) + data[i] = value; + } + const T& operator [] (size_t i) const + { + return data[i]; + } + regfile_t() + { + reset(); + } + void reset() + { + memset(data, 0, sizeof(data)); + } +private: + T data[N]; +}; + +#define get_field(reg, mask) \ + (((reg) & (std::remove_cv<decltype(reg)>::type)(mask)) / ((mask) & ~((mask) << 1))) + +#define set_field(reg, mask, val) \ + (((reg) & ~(std::remove_cv<decltype(reg)>::type)(mask)) | (((std::remove_cv<decltype(reg)>::type)(val) * ((mask) & ~((mask) << 1))) & (std::remove_cv<decltype(reg)>::type)(mask))) + +#define DEBUG_START 0x0 +#define DEBUG_END (0x1000 - 1) + +#endif diff --git a/vendor/riscv/riscv-isa-sim/riscv/decode_macros.h b/vendor/riscv/riscv-isa-sim/riscv/decode_macros.h new file mode 100644 index 0000000000..fee8ae7fae --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/decode_macros.h @@ -0,0 +1,312 @@ +// See LICENSE for license details. + +#ifndef _RISCV_DECODE_MACROS_H +#define _RISCV_DECODE_MACROS_H + +#include "config.h" +#include "decode.h" +#include "encoding.h" +#include "common.h" +#include "softfloat_types.h" +#include "specialize.h" + +// helpful macros, etc +#define MMU (*p->get_mmu()) +#define STATE (*p->get_state()) +#define FLEN (p->get_flen()) +#define CHECK_REG(reg) ((void) 0) +#define READ_REG(reg) (CHECK_REG(reg), STATE.XPR[reg]) +#define READ_FREG(reg) STATE.FPR[reg] +#define RD READ_REG(insn.rd()) +#define RS1 READ_REG(insn.rs1()) +#define RS2 READ_REG(insn.rs2()) +#define RS3 READ_REG(insn.rs3()) +#define WRITE_RD(value) WRITE_REG(insn.rd(), value) + +/* 0 : int + * 1 : floating + * 2 : vector reg + * 3 : vector hint + * 4 : csr + */ +#define WRITE_REG(reg, value) ({ \ + reg_t wdata = (value); /* value may have side effects */ \ + if (DECODE_MACRO_USAGE_LOGGED) STATE.log_reg_write[(reg) << 4] = {wdata, 0}; \ + CHECK_REG(reg); \ + STATE.XPR.write(reg, wdata); \ + }) +#define WRITE_FREG(reg, value) ({ \ + freg_t wdata = freg(value); /* value may have side effects */ \ + if (DECODE_MACRO_USAGE_LOGGED) STATE.log_reg_write[((reg) << 4) | 1] = wdata; \ + DO_WRITE_FREG(reg, wdata); \ + }) +#define WRITE_VSTATUS STATE.log_reg_write[3] = {0, 0}; + +// RVC macros +#define WRITE_RVC_RS1S(value) WRITE_REG(insn.rvc_rs1s(), value) +#define WRITE_RVC_RS2S(value) WRITE_REG(insn.rvc_rs2s(), value) +#define WRITE_RVC_FRS2S(value) WRITE_FREG(insn.rvc_rs2s(), value) +#define RVC_RS1 READ_REG(insn.rvc_rs1()) +#define RVC_RS2 READ_REG(insn.rvc_rs2()) +#define RVC_RS1S READ_REG(insn.rvc_rs1s()) +#define RVC_RS2S READ_REG(insn.rvc_rs2s()) +#define RVC_FRS2 READ_FREG(insn.rvc_rs2()) +#define RVC_FRS2S READ_FREG(insn.rvc_rs2s()) +#define RVC_SP READ_REG(X_SP) + +// Zc* macros +#define RVC_R1S (Sn(insn.rvc_r1sc())) +#define RVC_R2S (Sn(insn.rvc_r2sc())) +#define SP READ_REG(X_SP) +#define RA READ_REG(X_RA) + +// FPU macros +#define READ_ZDINX_REG(reg) (xlen == 32 ? f64(READ_REG_PAIR(reg)) : f64(STATE.XPR[reg] & (uint64_t)-1)) +#define READ_FREG_H(reg) (p->extension_enabled(EXT_ZFINX) ? f16(STATE.XPR[reg] & (uint16_t)-1) : f16(READ_FREG(reg))) +#define READ_FREG_F(reg) (p->extension_enabled(EXT_ZFINX) ? f32(STATE.XPR[reg] & (uint32_t)-1) : f32(READ_FREG(reg))) +#define READ_FREG_D(reg) (p->extension_enabled(EXT_ZFINX) ? READ_ZDINX_REG(reg) : f64(READ_FREG(reg))) +#define FRS1 READ_FREG(insn.rs1()) +#define FRS2 READ_FREG(insn.rs2()) +#define FRS3 READ_FREG(insn.rs3()) +#define FRS1_H READ_FREG_H(insn.rs1()) +#define FRS1_F READ_FREG_F(insn.rs1()) +#define FRS1_D READ_FREG_D(insn.rs1()) +#define FRS2_H READ_FREG_H(insn.rs2()) +#define FRS2_F READ_FREG_F(insn.rs2()) +#define FRS2_D READ_FREG_D(insn.rs2()) +#define FRS3_H READ_FREG_H(insn.rs3()) +#define FRS3_F READ_FREG_F(insn.rs3()) +#define FRS3_D READ_FREG_D(insn.rs3()) +#define dirty_fp_state STATE.sstatus->dirty(SSTATUS_FS) +#define dirty_ext_state STATE.sstatus->dirty(SSTATUS_XS) +#define dirty_vs_state STATE.sstatus->dirty(SSTATUS_VS) +#define DO_WRITE_FREG(reg, value) (STATE.FPR.write(reg, value), dirty_fp_state) +#define WRITE_FRD(value) WRITE_FREG(insn.rd(), value) +#define WRITE_FRD_H(value) \ +do { \ + if (p->extension_enabled(EXT_ZFINX)) \ + WRITE_REG(insn.rd(), sext_xlen((int16_t)((value).v))); \ + else { \ + WRITE_FRD(value); \ + } \ +} while (0) +#define WRITE_FRD_F(value) \ +do { \ + if (p->extension_enabled(EXT_ZFINX)) \ + WRITE_REG(insn.rd(), sext_xlen((value).v)); \ + else { \ + WRITE_FRD(value); \ + } \ +} while (0) +#define WRITE_FRD_D(value) \ +do { \ + if (p->extension_enabled(EXT_ZFINX)) { \ + if (xlen == 32) { \ + uint64_t val = (value).v; \ + WRITE_RD_PAIR(val); \ + } else { \ + WRITE_REG(insn.rd(), (value).v); \ + } \ + } else { \ + WRITE_FRD(value); \ + } \ +} while (0) + +#define SHAMT (insn.i_imm() & 0x3F) +#define BRANCH_TARGET (pc + insn.sb_imm()) +#define JUMP_TARGET (pc + insn.uj_imm()) +#define RM ({ int rm = insn.rm(); \ + if (rm == 7) rm = STATE.frm->read(); \ + if (rm > 4) throw trap_illegal_instruction(insn.bits()); \ + rm; }) + + +#define require_privilege(p) require(STATE.prv >= (p)) +#define require_novirt() (unlikely(STATE.v) ? throw trap_virtual_instruction(insn.bits()) : (void) 0) +#define require_hs_qualified(cond) (STATE.v && !(cond) ? require_novirt() : require(cond)) +#define require_privilege_hs_qualified(p) require_hs_qualified(STATE.prv >= (p)) +#define require_rv64 require(xlen == 64) +#define require_rv32 require(xlen == 32) +#define require_extension(s) require(p->extension_enabled(s)) +#define require_either_extension(A,B) require(p->extension_enabled(A) || p->extension_enabled(B)); +#define require_impl(s) require(p->supports_impl(s)) +#define require_fs require(STATE.sstatus->enabled(SSTATUS_FS)) +#define require_fp STATE.fflags->verify_permissions(insn, false) +#define require_accelerator require(STATE.sstatus->enabled(SSTATUS_XS)) +#define require_vector_vs require(STATE.sstatus->enabled(SSTATUS_VS)) +#define require_vector(alu) \ + do { \ + require_vector_vs; \ + require_extension('V'); \ + require(!P.VU.vill); \ + if (alu && !P.VU.vstart_alu) \ + require(P.VU.vstart->read() == 0); \ + WRITE_VSTATUS; \ + dirty_vs_state; \ + } while (0); +#define require_vector_novtype(is_log) \ + do { \ + require_vector_vs; \ + require_extension('V'); \ + if (is_log) \ + WRITE_VSTATUS; \ + dirty_vs_state; \ + } while (0); +#define require_align(val, pos) require(is_aligned(val, pos)) +#define require_noover(astart, asize, bstart, bsize) \ + require(!is_overlapped(astart, asize, bstart, bsize)) +#define require_noover_widen(astart, asize, bstart, bsize) \ + require(!is_overlapped_widen(astart, asize, bstart, bsize)) +#define require_vm do { if (insn.v_vm() == 0) require(insn.rd() != 0); } while (0); +#define require_envcfg(field) \ + do { \ + if (((STATE.prv != PRV_M) && (m##field == 0)) || \ + ((STATE.prv == PRV_U && !STATE.v) && (s##field == 0))) \ + throw trap_illegal_instruction(insn.bits()); \ + else if (STATE.v && ((h##field == 0) || \ + ((STATE.prv == PRV_U) && (s##field == 0)))) \ + throw trap_virtual_instruction(insn.bits()); \ + } while (0); + +#define require_zcmp_pushpop \ + do { \ + require_extension(EXT_ZCMP); \ + reg_t rlist = insn.rvc_rlist(); \ + require(rlist >= 4); \ + \ + if (p->extension_enabled('E')) { \ + require(rlist <= 6); \ + } \ + } while (0); + +#define set_fp_exceptions ({ if (softfloat_exceptionFlags) { \ + STATE.fflags->write(STATE.fflags->read() | softfloat_exceptionFlags); \ + } \ + softfloat_exceptionFlags = 0; }) + +#define sext32(x) ((sreg_t)(int32_t)(x)) +#define zext32(x) ((reg_t)(uint32_t)(x)) +#define sext_xlen(x) (((sreg_t)(x) << (64 - xlen)) >> (64 - xlen)) +#define zext(x, pos) (((reg_t)(x) << (64 - (pos))) >> (64 - (pos))) +#define zext_xlen(x) zext(x, xlen) + +#define set_pc(x) \ + do { p->check_pc_alignment(x); \ + npc = sext_xlen(x); \ + } while (0) + +#define set_pc_and_serialize(x) \ + do { reg_t __npc = (x) & p->pc_alignment_mask(); \ + npc = PC_SERIALIZE_AFTER; \ + STATE.pc = __npc; \ + } while (0) + +class wait_for_interrupt_t {}; + +#define wfi() \ + do { set_pc_and_serialize(npc); \ + throw wait_for_interrupt_t(); \ + } while (0) + +#define serialize() set_pc_and_serialize(npc) + +/* Sentinel PC values to serialize simulator pipeline */ +#define PC_SERIALIZE_BEFORE 3 +#define PC_SERIALIZE_AFTER 5 +#define invalid_pc(pc) ((pc) & 1) + +/* Convenience wrappers to simplify softfloat code sequences */ +#define isBoxedF16(r) (isBoxedF32(r) && ((uint64_t)((r.v[0] >> 16) + 1) == ((uint64_t)1 << 48))) +#define unboxF16(r) (isBoxedF16(r) ? (uint16_t)r.v[0] : defaultNaNF16UI) +#define isBoxedF32(r) (isBoxedF64(r) && ((uint32_t)((r.v[0] >> 32) + 1) == 0)) +#define unboxF32(r) (isBoxedF32(r) ? (uint32_t)r.v[0] : defaultNaNF32UI) +#define isBoxedF64(r) ((r.v[1] + 1) == 0) +#define unboxF64(r) (isBoxedF64(r) ? r.v[0] : defaultNaNF64UI) +inline float16_t f16(uint16_t v) { return { v }; } +inline float32_t f32(uint32_t v) { return { v }; } +inline float64_t f64(uint64_t v) { return { v }; } +inline float16_t f16(freg_t r) { return f16(unboxF16(r)); } +inline float32_t f32(freg_t r) { return f32(unboxF32(r)); } +inline float64_t f64(freg_t r) { return f64(unboxF64(r)); } +inline float128_t f128(freg_t r) { return r; } +inline freg_t freg(float16_t f) { return { ((uint64_t)-1 << 16) | f.v, (uint64_t)-1 }; } +inline freg_t freg(float32_t f) { return { ((uint64_t)-1 << 32) | f.v, (uint64_t)-1 }; } +inline freg_t freg(float64_t f) { return { f.v, (uint64_t)-1 }; } +inline freg_t freg(float128_t f) { return f; } +#define F16_SIGN ((uint16_t)1 << 15) +#define F32_SIGN ((uint32_t)1 << 31) +#define F64_SIGN ((uint64_t)1 << 63) +#define fsgnj16(a, b, n, x) \ + f16((f16(a).v & ~F16_SIGN) | ((((x) ? f16(a).v : (n) ? F16_SIGN : 0) ^ f16(b).v) & F16_SIGN)) +#define fsgnj32(a, b, n, x) \ + f32((f32(a).v & ~F32_SIGN) | ((((x) ? f32(a).v : (n) ? F32_SIGN : 0) ^ f32(b).v) & F32_SIGN)) +#define fsgnj64(a, b, n, x) \ + f64((f64(a).v & ~F64_SIGN) | ((((x) ? f64(a).v : (n) ? F64_SIGN : 0) ^ f64(b).v) & F64_SIGN)) + +#define isNaNF128(x) isNaNF128UI(x.v[1], x.v[0]) +inline float128_t defaultNaNF128() +{ + float128_t nan; + nan.v[1] = defaultNaNF128UI64; + nan.v[0] = defaultNaNF128UI0; + return nan; +} +inline freg_t fsgnj128(freg_t a, freg_t b, bool n, bool x) +{ + a.v[1] = (a.v[1] & ~F64_SIGN) | (((x ? a.v[1] : n ? F64_SIGN : 0) ^ b.v[1]) & F64_SIGN); + return a; +} +inline freg_t f128_negate(freg_t a) +{ + a.v[1] ^= F64_SIGN; + return a; +} + +#define validate_csr(which, write) ({ \ + if (!STATE.serialized) return PC_SERIALIZE_BEFORE; \ + STATE.serialized = false; \ + /* permissions check occurs in get_csr */ \ + (which); }) + +/* For debug only. This will fail if the native machine's float types are not IEEE */ +inline float to_f(float32_t f) { float r; memcpy(&r, &f, sizeof(r)); return r; } +inline double to_f(float64_t f) { double r; memcpy(&r, &f, sizeof(r)); return r; } +inline long double to_f(float128_t f) { long double r; memcpy(&r, &f, sizeof(r)); return r; } + +// Vector macros +#define e8 8 // 8b elements +#define e16 16 // 16b elements +#define e32 32 // 32b elements +#define e64 64 // 64b elements +#define e128 128 // 128b elements +#define e256 256 // 256b elements +#define e512 512 // 512b elements +#define e1024 1024 // 1024b elements + +#define vsext(x, sew) (((sreg_t)(x) << (64 - sew)) >> (64 - sew)) +#define vzext(x, sew) (((reg_t)(x) << (64 - sew)) >> (64 - sew)) + +#define DEBUG_RVV 0 + +#if DEBUG_RVV +#define DEBUG_RVV_FP_VV \ + printf("vfp(%lu) vd=%f vs1=%f vs2=%f\n", i, to_f(vd), to_f(vs1), to_f(vs2)); +#define DEBUG_RVV_FP_VF \ + printf("vfp(%lu) vd=%f vs1=%f vs2=%f\n", i, to_f(vd), to_f(rs1), to_f(vs2)); +#define DEBUG_RVV_FMA_VV \ + printf("vfma(%lu) vd=%f vs1=%f vs2=%f vd_old=%f\n", i, to_f(vd), to_f(vs1), to_f(vs2), to_f(vd_old)); +#define DEBUG_RVV_FMA_VF \ + printf("vfma(%lu) vd=%f vs1=%f vs2=%f vd_old=%f\n", i, to_f(vd), to_f(rs1), to_f(vs2), to_f(vd_old)); +#else +#define DEBUG_RVV_FP_VV 0 +#define DEBUG_RVV_FP_VF 0 +#define DEBUG_RVV_FMA_VV 0 +#define DEBUG_RVV_FMA_VF 0 +#endif + +#define DECLARE_XENVCFG_VARS(field) \ + reg_t m##field = get_field(STATE.menvcfg->read(), MENVCFG_##field); \ + reg_t s##field = get_field(STATE.senvcfg->read(), SENVCFG_##field); \ + reg_t h##field = get_field(STATE.henvcfg->read(), HENVCFG_##field) + +#endif diff --git a/vendor/riscv/riscv-isa-sim/riscv/devices.cc b/vendor/riscv/riscv-isa-sim/riscv/devices.cc new file mode 100644 index 0000000000..81b232d120 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/devices.cc @@ -0,0 +1,152 @@ +#include "devices.h" +#include "mmu.h" +#include <stdexcept> + +void bus_t::add_device(reg_t addr, abstract_device_t* dev) +{ + // Searching devices via lower_bound/upper_bound + // implicitly relies on the underlying std::map + // container to sort the keys and provide ordered + // iteration over this sort, which it does. (python's + // SortedDict is a good analogy) + devices[addr] = dev; +} + +bool bus_t::load(reg_t addr, size_t len, uint8_t* bytes) +{ + // Find the device with the base address closest to but + // less than addr (price-is-right search) + auto it = devices.upper_bound(addr); + if (devices.empty() || it == devices.begin()) { + // Either the bus is empty, or there weren't + // any items with a base address <= addr + return false; + } + // Found at least one item with base address <= addr + // The iterator points to the device after this, so + // go back by one item. + it--; + return it->second->load(addr - it->first, len, bytes); +} + +bool bus_t::store(reg_t addr, size_t len, const uint8_t* bytes) +{ + // See comments in bus_t::load + auto it = devices.upper_bound(addr); + if (devices.empty() || it == devices.begin()) { + return false; + } + it--; + return it->second->store(addr - it->first, len, bytes); +} + +std::pair<reg_t, abstract_device_t*> bus_t::find_device(reg_t addr) +{ + // See comments in bus_t::load + auto it = devices.upper_bound(addr); + if (devices.empty() || it == devices.begin()) { + return std::make_pair((reg_t)0, (abstract_device_t*)NULL); + } + it--; + return std::make_pair(it->first, it->second); +} + +// Type for holding all registered MMIO plugins by name. +using mmio_plugin_map_t = std::map<std::string, mmio_plugin_t>; + +// Simple singleton instance of an mmio_plugin_map_t. +static mmio_plugin_map_t& mmio_plugin_map() +{ + static mmio_plugin_map_t instance; + return instance; +} + +void register_mmio_plugin(const char* name_cstr, + const mmio_plugin_t* mmio_plugin) +{ + std::string name(name_cstr); + if (!mmio_plugin_map().emplace(name, *mmio_plugin).second) { + throw std::runtime_error("Plugin \"" + name + "\" already registered!"); + } +} + +mmio_plugin_device_t::mmio_plugin_device_t(const std::string& name, + const std::string& args) + : plugin(mmio_plugin_map().at(name)), user_data((*plugin.alloc)(args.c_str())) +{ +} + +mmio_plugin_device_t::~mmio_plugin_device_t() +{ + (*plugin.dealloc)(user_data); +} + +bool mmio_plugin_device_t::load(reg_t addr, size_t len, uint8_t* bytes) +{ + return (*plugin.load)(user_data, addr, len, bytes); +} + +bool mmio_plugin_device_t::store(reg_t addr, size_t len, const uint8_t* bytes) +{ + return (*plugin.store)(user_data, addr, len, bytes); +} + +mem_t::mem_t(reg_t size) + : sz(size) +{ + if (size == 0 || size % PGSIZE != 0) + throw std::runtime_error("memory size must be a positive multiple of 4 KiB"); +} + +mem_t::~mem_t() +{ + for (auto& entry : sparse_memory_map) + free(entry.second); +} + +bool mem_t::load_store(reg_t addr, size_t len, uint8_t* bytes, bool store) +{ + if (addr + len < addr || addr + len > sz) + return false; + + while (len > 0) { + auto n = std::min(PGSIZE - (addr % PGSIZE), reg_t(len)); + + if (store) + memcpy(this->contents(addr), bytes, n); + else + memcpy(bytes, this->contents(addr), n); + + addr += n; + bytes += n; + len -= n; + } + + return true; +} + +char* mem_t::contents(reg_t addr) { + reg_t ppn = addr >> PGSHIFT, pgoff = addr % PGSIZE; + auto search = sparse_memory_map.find(ppn); + if (search == sparse_memory_map.end()) { + auto res = (char*)calloc(PGSIZE, 1); + if (res == nullptr) + throw std::bad_alloc(); + sparse_memory_map[ppn] = res; + return res + pgoff; + } + return search->second + pgoff; +} + +void mem_t::dump(std::ostream& o) { + const char empty[PGSIZE] = {0}; + for (reg_t i = 0; i < sz; i += PGSIZE) { + reg_t ppn = i >> PGSHIFT; + auto search = sparse_memory_map.find(ppn); + if (search == sparse_memory_map.end()) { + o.write(empty, PGSIZE); + } else { + o.write(sparse_memory_map[ppn], PGSIZE); + } + } +} diff --git a/vendor/riscv/riscv-isa-sim/riscv/devices.h b/vendor/riscv/riscv-isa-sim/riscv/devices.h new file mode 100644 index 0000000000..02d9e98068 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/devices.h @@ -0,0 +1,196 @@ +#ifndef _RISCV_DEVICES_H +#define _RISCV_DEVICES_H + +#include "decode.h" +#include "mmio_plugin.h" +#include "abstract_device.h" +#include "abstract_interrupt_controller.h" +#include "platform.h" +#include <map> +#include <queue> +#include <vector> +#include <utility> +#include <cassert> + +class processor_t; +class simif_t; + +class bus_t : public abstract_device_t { + public: + bool load(reg_t addr, size_t len, uint8_t* bytes); + bool store(reg_t addr, size_t len, const uint8_t* bytes); + void add_device(reg_t addr, abstract_device_t* dev); + + std::pair<reg_t, abstract_device_t*> find_device(reg_t addr); + + private: + std::map<reg_t, abstract_device_t*> devices; +}; + +class rom_device_t : public abstract_device_t { + public: + rom_device_t(std::vector<char> data); + bool load(reg_t addr, size_t len, uint8_t* bytes); + bool store(reg_t addr, size_t len, const uint8_t* bytes); + const std::vector<char>& contents() { return data; } + private: + std::vector<char> data; +}; + +class mem_t : public abstract_device_t { + public: + mem_t(reg_t size); + mem_t(const mem_t& that) = delete; + ~mem_t(); + + bool load(reg_t addr, size_t len, uint8_t* bytes) { return load_store(addr, len, bytes, false); } + bool store(reg_t addr, size_t len, const uint8_t* bytes) { return load_store(addr, len, const_cast<uint8_t*>(bytes), true); } + char* contents(reg_t addr); + reg_t size() { return sz; } + void dump(std::ostream& o); + + private: + bool load_store(reg_t addr, size_t len, uint8_t* bytes, bool store); + + std::map<reg_t, char*> sparse_memory_map; + reg_t sz; +}; + +class clint_t : public abstract_device_t { + public: + clint_t(simif_t*, uint64_t freq_hz, bool real_time); + bool load(reg_t addr, size_t len, uint8_t* bytes); + bool store(reg_t addr, size_t len, const uint8_t* bytes); + size_t size() { return CLINT_SIZE; } + void increment(reg_t inc); + uint64_t get_mtimecmp(reg_t hartid) { return mtimecmp[hartid]; } + uint64_t get_mtime() { return mtime; } + private: + typedef uint64_t mtime_t; + typedef uint64_t mtimecmp_t; + typedef uint32_t msip_t; + simif_t* sim; + uint64_t freq_hz; + bool real_time; + uint64_t real_time_ref_secs; + uint64_t real_time_ref_usecs; + mtime_t mtime; + std::map<size_t, mtimecmp_t> mtimecmp; +}; + +#define PLIC_MAX_DEVICES 1024 + +struct plic_context_t { + plic_context_t(processor_t* proc, bool mmode) + : proc(proc), mmode(mmode) + {} + + processor_t *proc; + bool mmode; + + uint8_t priority_threshold {}; + uint32_t enable[PLIC_MAX_DEVICES/32] {}; + uint32_t pending[PLIC_MAX_DEVICES/32] {}; + uint8_t pending_priority[PLIC_MAX_DEVICES] {}; + uint32_t claimed[PLIC_MAX_DEVICES/32] {}; +}; + +class plic_t : public abstract_device_t, public abstract_interrupt_controller_t { + public: + plic_t(simif_t*, uint32_t ndev); + bool load(reg_t addr, size_t len, uint8_t* bytes); + bool store(reg_t addr, size_t len, const uint8_t* bytes); + void set_interrupt_level(uint32_t id, int lvl); + size_t size() { return PLIC_SIZE; } + private: + std::vector<plic_context_t> contexts; + uint32_t num_ids; + uint32_t num_ids_word; + uint32_t max_prio; + uint8_t priority[PLIC_MAX_DEVICES]; + uint32_t level[PLIC_MAX_DEVICES/32]; + uint32_t context_best_pending(const plic_context_t *c); + void context_update(const plic_context_t *context); + uint32_t context_claim(plic_context_t *c); + bool priority_read(reg_t offset, uint32_t *val); + bool priority_write(reg_t offset, uint32_t val); + bool pending_read(reg_t offset, uint32_t *val); + bool context_enable_read(const plic_context_t *context, + reg_t offset, uint32_t *val); + bool context_enable_write(plic_context_t *context, + reg_t offset, uint32_t val); + bool context_read(plic_context_t *context, + reg_t offset, uint32_t *val); + bool context_write(plic_context_t *context, + reg_t offset, uint32_t val); +}; + +class ns16550_t : public abstract_device_t { + public: + ns16550_t(class bus_t *bus, abstract_interrupt_controller_t *intctrl, + uint32_t interrupt_id, uint32_t reg_shift, uint32_t reg_io_width); + bool load(reg_t addr, size_t len, uint8_t* bytes); + bool store(reg_t addr, size_t len, const uint8_t* bytes); + void tick(void); + size_t size() { return NS16550_SIZE; } + private: + class bus_t *bus; + abstract_interrupt_controller_t *intctrl; + uint32_t interrupt_id; + uint32_t reg_shift; + uint32_t reg_io_width; + std::queue<uint8_t> rx_queue; + uint8_t dll; + uint8_t dlm; + uint8_t iir; + uint8_t ier; + uint8_t fcr; + uint8_t lcr; + uint8_t mcr; + uint8_t lsr; + uint8_t msr; + uint8_t scr; + void update_interrupt(void); + uint8_t rx_byte(void); + void tx_byte(uint8_t val); + + int backoff_counter; + static const int MAX_BACKOFF = 16; +}; + +class mmio_plugin_device_t : public abstract_device_t { + public: + mmio_plugin_device_t(const std::string& name, const std::string& args); + virtual ~mmio_plugin_device_t() override; + + virtual bool load(reg_t addr, size_t len, uint8_t* bytes) override; + virtual bool store(reg_t addr, size_t len, const uint8_t* bytes) override; + + private: + mmio_plugin_t plugin; + void* user_data; +}; + +template<typename T> +void write_little_endian_reg(T* word, reg_t addr, size_t len, const uint8_t* bytes) +{ + assert(len <= sizeof(T)); + + for (size_t i = 0; i < len; i++) { + const int shift = 8 * ((addr + i) % sizeof(T)); + *word = (*word & ~(T(0xFF) << shift)) | (T(bytes[i]) << shift); + } +} + +template<typename T> +void read_little_endian_reg(T word, reg_t addr, size_t len, uint8_t* bytes) +{ + assert(len <= sizeof(T)); + + for (size_t i = 0; i < len; i++) { + const int shift = 8 * ((addr + i) % sizeof(T)); + bytes[i] = word >> shift; + } +} + +#endif diff --git a/vendor/riscv/riscv-isa-sim/riscv/disasm.h b/vendor/riscv/riscv-isa-sim/riscv/disasm.h new file mode 100644 index 0000000000..d4b8c2c40e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/disasm.h @@ -0,0 +1,110 @@ +// See LICENSE for license details. + +#ifndef _RISCV_DISASM_H +#define _RISCV_DISASM_H + +#include "common.h" +#include "decode.h" +#include "isa_parser.h" +#include <string> +#include <sstream> +#include <algorithm> +#include <vector> + +extern const char* xpr_name[NXPR]; +extern const char* fpr_name[NFPR]; +extern const char* vr_name[NVPR]; +extern const char* csr_name(int which); + +class arg_t +{ + public: + virtual std::string to_string(insn_t val) const = 0; + virtual ~arg_t() {} +}; + +class disasm_insn_t +{ + public: + NOINLINE disasm_insn_t(const char* name_, uint32_t match, uint32_t mask, + const std::vector<const arg_t*>& args) + : match(match), mask(mask), args(args) + { + name = name_; + std::replace(name.begin(), name.end(), '_', '.'); + } + + bool operator == (insn_t insn) const + { + return (insn.bits() & mask) == match; + } + + const char* get_name() const + { + return name.c_str(); + } + + std::string to_string(insn_t insn) const + { + std::string s(name); + + if (args.size()) + { + bool next_arg_optional = false; + s += std::string(std::max(1, 8 - int(name.size())), ' '); + for (size_t i = 0; i < args.size(); i++) { + if (args[i] == nullptr) { + next_arg_optional = true; + continue; + } + std::string argString = args[i]->to_string(insn); + if (next_arg_optional) { + next_arg_optional = false; + if (argString.empty()) continue; + } + if (i != 0) s += ", "; + s += argString; + } + } + return s; + } + + uint32_t get_match() const { return match; } + uint32_t get_mask() const { return mask; } + + private: + uint32_t match; + uint32_t mask; + std::vector<const arg_t*> args; + std::string name; +}; + +class disassembler_t +{ + public: + disassembler_t(const isa_parser_t *isa); + ~disassembler_t(); + + std::string disassemble(insn_t insn) const; + const disasm_insn_t* lookup(insn_t insn) const; + + void add_insn(disasm_insn_t* insn); + + private: + static const int HASH_SIZE = 255; + std::vector<const disasm_insn_t*> chain[HASH_SIZE+1]; + + void add_instructions(const isa_parser_t* isa); + + const disasm_insn_t* probe_once(insn_t insn, size_t idx) const; + + static const unsigned int MASK1 = 0x7f; + static const unsigned int MASK2 = 0xe003; + + static unsigned int hash(insn_bits_t insn, unsigned int mask) + { + return (insn & mask) % HASH_SIZE; + } +}; + +#endif diff --git a/vendor/riscv/riscv-isa-sim/riscv/dts.cc b/vendor/riscv/riscv-isa-sim/riscv/dts.cc new file mode 100644 index 0000000000..200288ef2c --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/dts.cc @@ -0,0 +1,415 @@ +// See LICENSE for license details. + +#include "config.h" +#include "dts.h" +#include "libfdt.h" +#include "platform.h" +#include <cassert> +#include <iostream> +#include <sstream> +#include <signal.h> +#include <unistd.h> +#include <sys/wait.h> +#include <sys/types.h> + +std::string make_dts(size_t insns_per_rtc_tick, size_t cpu_hz, + reg_t initrd_start, reg_t initrd_end, + const char* bootargs, + size_t pmpregions, + std::vector<processor_t*> procs, + std::vector<std::pair<reg_t, mem_t*>> mems) +{ + std::stringstream s; + s << std::dec << + "/dts-v1/;\n" + "\n" + "/ {\n" + " #address-cells = <2>;\n" + " #size-cells = <2>;\n" + " compatible = \"ucbbar,spike-bare-dev\";\n" + " model = \"ucbbar,spike-bare\";\n" + " chosen {\n" + " stdout-path = &SERIAL0;\n"; + if (initrd_start < initrd_end) { + s << " linux,initrd-start = <" << (size_t)initrd_start << ">;\n" + " linux,initrd-end = <" << (size_t)initrd_end << ">;\n"; + if (!bootargs) + bootargs = "root=/dev/ram " DEFAULT_KERNEL_BOOTARGS; + } else { + if (!bootargs) + bootargs = DEFAULT_KERNEL_BOOTARGS; + } + s << " bootargs = \""; + for (size_t i = 0; i < strlen(bootargs); i++) { + if (bootargs[i] == '"') + s << '\\' << bootargs[i]; + else + s << bootargs[i]; + } + s << "\";\n"; + s << " };\n" + " cpus {\n" + " #address-cells = <1>;\n" + " #size-cells = <0>;\n" + " timebase-frequency = <" << (cpu_hz/insns_per_rtc_tick) << ">;\n"; + for (size_t i = 0; i < procs.size(); i++) { + s << " CPU" << i << ": cpu@" << i << " {\n" + " device_type = \"cpu\";\n" + " reg = <" << i << ">;\n" + " status = \"okay\";\n" + " compatible = \"riscv\";\n" + " riscv,isa = \"" << procs[i]->get_isa().get_isa_string() << "\";\n" + " mmu-type = \"riscv," << (procs[i]->get_isa().get_max_xlen() <= 32 ? "sv32" : "sv57") << "\";\n" + " riscv,pmpregions = <" << pmpregions << ">;\n" + " riscv,pmpgranularity = <" << (1 << PMP_SHIFT) << ">;\n" + " clock-frequency = <" << cpu_hz << ">;\n" + " CPU" << i << "_intc: interrupt-controller {\n" + " #address-cells = <2>;\n" + " #interrupt-cells = <1>;\n" + " interrupt-controller;\n" + " compatible = \"riscv,cpu-intc\";\n" + " };\n" + " };\n"; + } + s << " };\n"; + for (auto& m : mems) { + s << std::hex << + " memory@" << m.first << " {\n" + " device_type = \"memory\";\n" + " reg = <0x" << (m.first >> 32) << " 0x" << (m.first & (uint32_t)-1) << + " 0x" << (m.second->size() >> 16 >> 16) << " 0x" << (m.second->size() & (uint32_t)-1) << ">;\n" + " };\n"; + } + s << " soc {\n" + " #address-cells = <2>;\n" + " #size-cells = <2>;\n" + " compatible = \"ucbbar,spike-bare-soc\", \"simple-bus\";\n" + " ranges;\n" + " clint@" << CLINT_BASE << " {\n" + " compatible = \"riscv,clint0\";\n" + " interrupts-extended = <" << std::dec; + for (size_t i = 0; i < procs.size(); i++) + s << "&CPU" << i << "_intc 3 &CPU" << i << "_intc 7 "; + reg_t clintbs = CLINT_BASE; + reg_t clintsz = CLINT_SIZE; + s << std::hex << ">;\n" + " reg = <0x" << (clintbs >> 32) << " 0x" << (clintbs & (uint32_t)-1) << + " 0x" << (clintsz >> 32) << " 0x" << (clintsz & (uint32_t)-1) << ">;\n" + " };\n" + " PLIC: plic@" << PLIC_BASE << " {\n" + " compatible = \"riscv,plic0\";\n" + " #address-cells = <2>;\n" + " interrupts-extended = <" << std::dec; + for (size_t i = 0; i < procs.size(); i++) + s << "&CPU" << i << "_intc 11 &CPU" << i << "_intc 9 "; + reg_t plicbs = PLIC_BASE; + reg_t plicsz = PLIC_SIZE; + s << std::hex << ">;\n" + " reg = <0x" << (plicbs >> 32) << " 0x" << (plicbs & (uint32_t)-1) << + " 0x" << (plicsz >> 32) << " 0x" << (plicsz & (uint32_t)-1) << ">;\n" + " riscv,ndev = <0x" << PLIC_NDEV << ">;\n" + " riscv,max-priority = <0x" << ((1U << PLIC_PRIO_BITS) - 1) << ">;\n" + " #interrupt-cells = <1>;\n" + " interrupt-controller;\n" + " };\n" + " SERIAL0: ns16550@" << NS16550_BASE << " {\n" + " compatible = \"ns16550a\";\n" + " clock-frequency = <" << std::dec << (cpu_hz/insns_per_rtc_tick) << ">;\n" + " interrupt-parent = <&PLIC>;\n" + " interrupts = <" << std::dec << NS16550_INTERRUPT_ID; + reg_t ns16550bs = NS16550_BASE; + reg_t ns16550sz = NS16550_SIZE; + s << std::hex << ">;\n" + " reg = <0x" << (ns16550bs >> 32) << " 0x" << (ns16550bs & (uint32_t)-1) << + " 0x" << (ns16550sz >> 32) << " 0x" << (ns16550sz & (uint32_t)-1) << ">;\n" + " reg-shift = <0x" << NS16550_REG_SHIFT << ">;\n" + " reg-io-width = <0x" << NS16550_REG_IO_WIDTH << ">;\n" + " };\n" + " };\n" + " htif {\n" + " compatible = \"ucb,htif0\";\n" + " };\n" + "};\n"; + return s.str(); +} + +std::string dts_compile(const std::string& dts) +{ + // Convert the DTS to DTB + int dts_pipe[2]; + pid_t dts_pid; + + fflush(NULL); // flush stdout/stderr before forking + if (pipe(dts_pipe) != 0 || (dts_pid = fork()) < 0) { + std::cerr << "Failed to fork dts child: " << strerror(errno) << std::endl; + exit(1); + } + + // Child process to output dts + if (dts_pid == 0) { + close(dts_pipe[0]); + int step, len = dts.length(); + const char *buf = dts.c_str(); + for (int done = 0; done < len; done += step) { + step = write(dts_pipe[1], buf+done, len-done); + if (step == -1) { + std::cerr << "Failed to write dts: " << strerror(errno) << std::endl; + exit(1); + } + } + close(dts_pipe[1]); + exit(0); + } + + pid_t dtb_pid; + int dtb_pipe[2]; + if (pipe(dtb_pipe) != 0 || (dtb_pid = fork()) < 0) { + std::cerr << "Failed to fork dtb child: " << strerror(errno) << std::endl; + exit(1); + } + + // Child process to output dtb + if (dtb_pid == 0) { + dup2(dts_pipe[0], 0); + dup2(dtb_pipe[1], 1); + close(dts_pipe[0]); + close(dts_pipe[1]); + close(dtb_pipe[0]); + close(dtb_pipe[1]); + execlp(DTC, DTC, "-O", "dtb", (char *)0); + std::cerr << "Failed to run " DTC ": " << strerror(errno) << std::endl; + exit(1); + } + + close(dts_pipe[1]); + close(dts_pipe[0]); + close(dtb_pipe[1]); + + // Read-out dtb + std::stringstream dtb; + + int got; + char buf[4096]; + while ((got = read(dtb_pipe[0], buf, sizeof(buf))) > 0) { + dtb.write(buf, got); + } + if (got == -1) { + std::cerr << "Failed to read dtb: " << strerror(errno) << std::endl; + exit(1); + } + close(dtb_pipe[0]); + + // Reap children + int status; + waitpid(dts_pid, &status, 0); + if (!WIFEXITED(status) || WEXITSTATUS(status) != 0) { + std::cerr << "Child dts process failed" << std::endl; + exit(1); + } + waitpid(dtb_pid, &status, 0); + if (!WIFEXITED(status) || WEXITSTATUS(status) != 0) { + std::cerr << "Child dtb process failed" << std::endl; + exit(1); + } + + return dtb.str(); +} + +static int fdt_get_node_addr_size(void *fdt, int node, reg_t *addr, + unsigned long *size, const char *field) +{ + int parent, len, i; + int cell_addr, cell_size; + const fdt32_t *prop_addr, *prop_size; + uint64_t temp = 0; + + parent = fdt_parent_offset(fdt, node); + if (parent < 0) + return parent; + + cell_addr = fdt_address_cells(fdt, parent); + if (cell_addr < 1) + return -ENODEV; + + cell_size = fdt_size_cells(fdt, parent); + if (cell_size < 0) + return -ENODEV; + + if (!field) + return -ENODEV; + + prop_addr = (fdt32_t *)fdt_getprop(fdt, node, field, &len); + if (!prop_addr) + return -ENODEV; + prop_size = prop_addr + cell_addr; + + if (addr) { + for (i = 0; i < cell_addr; i++) + temp = (temp << 32) | fdt32_to_cpu(*prop_addr++); + *addr = temp; + } + temp = 0; + + if (size) { + for (i = 0; i < cell_size; i++) + temp = (temp << 32) | fdt32_to_cpu(*prop_size++); + *size = temp; + } + + return 0; +} + +static int check_cpu_node(void *fdt, int cpu_offset) +{ + int len; + const void *prop; + + if (!fdt || cpu_offset < 0) + return -EINVAL; + + prop = fdt_getprop(fdt, cpu_offset, "device_type", &len); + if (!prop || !len) + return -EINVAL; + if (strncmp ((char *)prop, "cpu", strlen ("cpu"))) + return -EINVAL; + + return 0; +} + +int fdt_get_offset(void *fdt, const char *field) +{ + return fdt_path_offset(fdt, field); +} + +int fdt_get_first_subnode(void *fdt, int node) +{ + return fdt_first_subnode(fdt, node); +} + +int fdt_get_next_subnode(void *fdt, int node) +{ + return fdt_next_subnode(fdt, node); +} + +int fdt_parse_clint(void *fdt, reg_t *clint_addr, + const char *compatible) +{ + int nodeoffset, rc; + + nodeoffset = fdt_node_offset_by_compatible(fdt, -1, compatible); + if (nodeoffset < 0) + return nodeoffset; + + rc = fdt_get_node_addr_size(fdt, nodeoffset, clint_addr, NULL, "reg"); + if (rc < 0 || !clint_addr) + return -ENODEV; + + return 0; +} + +int fdt_parse_plic(void *fdt, reg_t *plic_addr, uint32_t *ndev, + const char *compatible) +{ + int nodeoffset, len, rc; + const fdt32_t *ndev_p; + + nodeoffset = fdt_node_offset_by_compatible(fdt, -1, compatible); + if (nodeoffset < 0) + return nodeoffset; + + rc = fdt_get_node_addr_size(fdt, nodeoffset, plic_addr, NULL, "reg"); + if (rc < 0 || !plic_addr) + return -ENODEV; + + ndev_p = (fdt32_t *)fdt_getprop(fdt, nodeoffset, "riscv,ndev", &len); + if (!ndev || !ndev_p) + return -ENODEV; + *ndev = fdt32_to_cpu(*ndev_p); + + return 0; +} + +int fdt_parse_ns16550(void *fdt, reg_t *ns16550_addr, + uint32_t *reg_shift, uint32_t *reg_io_width, + const char *compatible) +{ + int nodeoffset, len, rc; + const fdt32_t *reg_p; + + nodeoffset = fdt_node_offset_by_compatible(fdt, -1, compatible); + if (nodeoffset < 0) + return nodeoffset; + + rc = fdt_get_node_addr_size(fdt, nodeoffset, ns16550_addr, NULL, "reg"); + if (rc < 0 || !ns16550_addr) + return -ENODEV; + + reg_p = (fdt32_t *)fdt_getprop(fdt, nodeoffset, "reg-shift", &len); + if (reg_shift) { + if (reg_p) { + *reg_shift = fdt32_to_cpu(*reg_p); + } else { + *reg_shift = NS16550_REG_SHIFT; + } + } + + reg_p = (fdt32_t *)fdt_getprop(fdt, nodeoffset, "reg-io-width", &len); + if (reg_io_width) { + if (reg_p) { + *reg_io_width = fdt32_to_cpu(*reg_p); + } else { + *reg_io_width = NS16550_REG_IO_WIDTH; + } + } + + return 0; +} + +int fdt_parse_pmp_num(void *fdt, int cpu_offset, reg_t *pmp_num) +{ + int rc; + + if ((rc = check_cpu_node(fdt, cpu_offset)) < 0) + return rc; + + rc = fdt_get_node_addr_size(fdt, cpu_offset, pmp_num, NULL, + "riscv,pmpregions"); + if (rc < 0 || !pmp_num) + return -ENODEV; + + return 0; +} + +int fdt_parse_pmp_alignment(void *fdt, int cpu_offset, reg_t *pmp_align) +{ + int rc; + + if ((rc = check_cpu_node(fdt, cpu_offset)) < 0) + return rc; + + rc = fdt_get_node_addr_size(fdt, cpu_offset, pmp_align, NULL, + "riscv,pmpgranularity"); + if (rc < 0 || !pmp_align) + return -ENODEV; + + return 0; +} + +int fdt_parse_mmu_type(void *fdt, int cpu_offset, const char **mmu_type) +{ + assert(mmu_type); + + int len, rc; + const void *prop; + + if ((rc = check_cpu_node(fdt, cpu_offset)) < 0) + return rc; + + prop = fdt_getprop(fdt, cpu_offset, "mmu-type", &len); + if (!prop || !len) + return -EINVAL; + + *mmu_type = (const char *)prop; + + return 0; +} diff --git a/vendor/riscv/riscv-isa-sim/riscv/dts.h b/vendor/riscv/riscv-isa-sim/riscv/dts.h new file mode 100644 index 0000000000..7a64d7bc63 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/dts.h @@ -0,0 +1,33 @@ +// See LICENSE for license details. +#ifndef _RISCV_DTS_H +#define _RISCV_DTS_H + +#include "devices.h" +#include "processor.h" +#include "mmu.h" +#include <string> + +std::string make_dts(size_t insns_per_rtc_tick, size_t cpu_hz, + reg_t initrd_start, reg_t initrd_end, + const char* bootargs, + size_t pmpregions, + std::vector<processor_t*> procs, + std::vector<std::pair<reg_t, mem_t*>> mems); + +std::string dts_compile(const std::string& dts); + +int fdt_get_offset(void *fdt, const char *field); +int fdt_get_first_subnode(void *fdt, int node); +int fdt_get_next_subnode(void *fdt, int node); + +int fdt_parse_clint(void *fdt, reg_t *clint_addr, + const char *compatible); +int fdt_parse_plic(void *fdt, reg_t *plic_addr, uint32_t *ndev, + const char *compatible); +int fdt_parse_ns16550(void *fdt, reg_t *ns16550_addr, + uint32_t *reg_shift, uint32_t *reg_io_width, + const char *compatible); +int fdt_parse_pmp_num(void *fdt, int cpu_offset, reg_t *pmp_num); +int fdt_parse_pmp_alignment(void *fdt, int cpu_offset, reg_t *pmp_align); +int fdt_parse_mmu_type(void *fdt, int cpu_offset, const char **mmu_type); +#endif diff --git a/vendor/riscv/riscv-isa-sim/riscv/encoding.h b/vendor/riscv/riscv-isa-sim/riscv/encoding.h new file mode 100644 index 0000000000..48cb5c0058 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/encoding.h @@ -0,0 +1,5163 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +/* Copyright (c) 2023 RISC-V International */ + +/* + * This file is auto-generated by running 'make' in + * https://github.com/riscv/riscv-opcodes (5adef50) + */ + +#ifndef RISCV_CSR_ENCODING_H +#define RISCV_CSR_ENCODING_H + +#define MSTATUS_UIE 0x00000001 +#define MSTATUS_SIE 0x00000002 +#define MSTATUS_HIE 0x00000004 +#define MSTATUS_MIE 0x00000008 +#define MSTATUS_UPIE 0x00000010 +#define MSTATUS_SPIE 0x00000020 +#define MSTATUS_UBE 0x00000040 +#define MSTATUS_MPIE 0x00000080 +#define MSTATUS_SPP 0x00000100 +#define MSTATUS_VS 0x00000600 +#define MSTATUS_MPP 0x00001800 +#define MSTATUS_FS 0x00006000 +#define MSTATUS_XS 0x00018000 +#define MSTATUS_MPRV 0x00020000 +#define MSTATUS_SUM 0x00040000 +#define MSTATUS_MXR 0x00080000 +#define MSTATUS_TVM 0x00100000 +#define MSTATUS_TW 0x00200000 +#define MSTATUS_TSR 0x00400000 +#define MSTATUS32_SD 0x80000000 +#define MSTATUS_UXL 0x0000000300000000 +#define MSTATUS_SXL 0x0000000C00000000 +#define MSTATUS_SBE 0x0000001000000000 +#define MSTATUS_MBE 0x0000002000000000 +#define MSTATUS_GVA 0x0000004000000000 +#define MSTATUS_MPV 0x0000008000000000 +#define MSTATUS64_SD 0x8000000000000000 + +#define MSTATUSH_SBE 0x00000010 +#define MSTATUSH_MBE 0x00000020 +#define MSTATUSH_GVA 0x00000040 +#define MSTATUSH_MPV 0x00000080 + +#define SSTATUS_UIE 0x00000001 +#define SSTATUS_SIE 0x00000002 +#define SSTATUS_UPIE 0x00000010 +#define SSTATUS_SPIE 0x00000020 +#define SSTATUS_UBE 0x00000040 +#define SSTATUS_SPP 0x00000100 +#define SSTATUS_VS 0x00000600 +#define SSTATUS_FS 0x00006000 +#define SSTATUS_XS 0x00018000 +#define SSTATUS_SUM 0x00040000 +#define SSTATUS_MXR 0x00080000 +#define SSTATUS32_SD 0x80000000 +#define SSTATUS_UXL 0x0000000300000000 +#define SSTATUS64_SD 0x8000000000000000 + +#define HSTATUS_VSXL 0x300000000 +#define HSTATUS_VTSR 0x00400000 +#define HSTATUS_VTW 0x00200000 +#define HSTATUS_VTVM 0x00100000 +#define HSTATUS_VGEIN 0x0003f000 +#define HSTATUS_HU 0x00000200 +#define HSTATUS_SPVP 0x00000100 +#define HSTATUS_SPV 0x00000080 +#define HSTATUS_GVA 0x00000040 +#define HSTATUS_VSBE 0x00000020 + +#define USTATUS_UIE 0x00000001 +#define USTATUS_UPIE 0x00000010 + +#define MNSTATUS_NMIE 0x00000008 +#define MNSTATUS_MNPP 0x00001800 +#define MNSTATUS_MNPV 0x00000080 + +#define DCSR_XDEBUGVER (3U<<30) +#define DCSR_NDRESET (1<<29) +#define DCSR_FULLRESET (1<<28) +#define DCSR_EBREAKM (1<<15) +#define DCSR_EBREAKH (1<<14) +#define DCSR_EBREAKS (1<<13) +#define DCSR_EBREAKU (1<<12) +#define DCSR_STOPCYCLE (1<<10) +#define DCSR_STOPTIME (1<<9) +#define DCSR_CAUSE (7<<6) +#define DCSR_DEBUGINT (1<<5) +#define DCSR_HALT (1<<3) +#define DCSR_STEP (1<<2) +#define DCSR_PRV (3<<0) + +#define DCSR_CAUSE_NONE 0 +#define DCSR_CAUSE_SWBP 1 +#define DCSR_CAUSE_HWBP 2 +#define DCSR_CAUSE_DEBUGINT 3 +#define DCSR_CAUSE_STEP 4 +#define DCSR_CAUSE_HALT 5 +#define DCSR_CAUSE_GROUP 6 + +#define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4)) +#define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5)) +#define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11)) + +#define MCONTROL_SELECT (1<<19) +#define MCONTROL_TIMING (1<<18) +#define MCONTROL_ACTION (0x3f<<12) +#define MCONTROL_CHAIN (1<<11) +#define MCONTROL_MATCH (0xf<<7) +#define MCONTROL_M (1<<6) +#define MCONTROL_H (1<<5) +#define MCONTROL_S (1<<4) +#define MCONTROL_U (1<<3) +#define MCONTROL_EXECUTE (1<<2) +#define MCONTROL_STORE (1<<1) +#define MCONTROL_LOAD (1<<0) + +#define MCONTROL_TYPE_NONE 0 +#define MCONTROL_TYPE_MATCH 2 + +#define MCONTROL_ACTION_DEBUG_EXCEPTION 0 +#define MCONTROL_ACTION_DEBUG_MODE 1 +#define MCONTROL_ACTION_TRACE_START 2 +#define MCONTROL_ACTION_TRACE_STOP 3 +#define MCONTROL_ACTION_TRACE_EMIT 4 + +#define MCONTROL_MATCH_EQUAL 0 +#define MCONTROL_MATCH_NAPOT 1 +#define MCONTROL_MATCH_GE 2 +#define MCONTROL_MATCH_LT 3 +#define MCONTROL_MATCH_MASK_LOW 4 +#define MCONTROL_MATCH_MASK_HIGH 5 + +#define MIP_USIP (1 << IRQ_U_SOFT) +#define MIP_SSIP (1 << IRQ_S_SOFT) +#define MIP_VSSIP (1 << IRQ_VS_SOFT) +#define MIP_MSIP (1 << IRQ_M_SOFT) +#define MIP_UTIP (1 << IRQ_U_TIMER) +#define MIP_STIP (1 << IRQ_S_TIMER) +#define MIP_VSTIP (1 << IRQ_VS_TIMER) +#define MIP_MTIP (1 << IRQ_M_TIMER) +#define MIP_UEIP (1 << IRQ_U_EXT) +#define MIP_SEIP (1 << IRQ_S_EXT) +#define MIP_VSEIP (1 << IRQ_VS_EXT) +#define MIP_MEIP (1 << IRQ_M_EXT) +#define MIP_SGEIP (1 << IRQ_S_GEXT) +#define MIP_LCOFIP (1 << IRQ_LCOF) + +#define MIP_S_MASK (MIP_SSIP | MIP_STIP | MIP_SEIP) +#define MIP_VS_MASK (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP) +#define MIP_HS_MASK (MIP_VS_MASK | MIP_SGEIP) + +#define MIDELEG_FORCED_MASK MIP_HS_MASK + +#define SIP_SSIP MIP_SSIP +#define SIP_STIP MIP_STIP + +#define MENVCFG_FIOM 0x00000001 +#define MENVCFG_CBIE 0x00000030 +#define MENVCFG_CBCFE 0x00000040 +#define MENVCFG_CBZE 0x00000080 +#define MENVCFG_HADE 0x2000000000000000 +#define MENVCFG_PBMTE 0x4000000000000000 +#define MENVCFG_STCE 0x8000000000000000 + +#define MENVCFGH_HADE 0x20000000 +#define MENVCFGH_PBMTE 0x40000000 +#define MENVCFGH_STCE 0x80000000 + +#define MSTATEEN0_CS 0x00000001 +#define MSTATEEN0_FCSR 0x00000002 +#define MSTATEEN0_JVT 0x00000004 +#define MSTATEEN0_HCONTEXT 0x0200000000000000 +#define MSTATEEN0_HENVCFG 0x4000000000000000 +#define MSTATEEN_HSTATEEN 0x8000000000000000 + +#define MSTATEEN0H_HCONTEXT 0x02000000 +#define MSTATEEN0H_HENVCFG 0x40000000 +#define MSTATEENH_HSTATEEN 0x80000000 + +#define MHPMEVENT_VUINH 0x0400000000000000 +#define MHPMEVENT_VSINH 0x0800000000000000 +#define MHPMEVENT_UINH 0x1000000000000000 +#define MHPMEVENT_SINH 0x2000000000000000 +#define MHPMEVENT_MINH 0x4000000000000000 +#define MHPMEVENT_OF 0x8000000000000000 + +#define MHPMEVENTH_VUINH 0x04000000 +#define MHPMEVENTH_VSINH 0x08000000 +#define MHPMEVENTH_UINH 0x10000000 +#define MHPMEVENTH_SINH 0x20000000 +#define MHPMEVENTH_MINH 0x40000000 +#define MHPMEVENTH_OF 0x80000000 + +#define HENVCFG_FIOM 0x00000001 +#define HENVCFG_CBIE 0x00000030 +#define HENVCFG_CBCFE 0x00000040 +#define HENVCFG_CBZE 0x00000080 +#define HENVCFG_HADE 0x2000000000000000 +#define HENVCFG_PBMTE 0x4000000000000000 +#define HENVCFG_STCE 0x8000000000000000 + +#define HENVCFGH_HADE 0x20000000 +#define HENVCFGH_PBMTE 0x40000000 +#define HENVCFGH_STCE 0x80000000 + +#define HSTATEEN0_CS 0x00000001 +#define HSTATEEN0_FCSR 0x00000002 +#define HSTATEEN0_JVT 0x00000004 +#define HSTATEEN0_SCONTEXT 0x0200000000000000 +#define HSTATEEN0_SENVCFG 0x4000000000000000 +#define HSTATEEN_SSTATEEN 0x8000000000000000 + +#define HSTATEEN0H_SCONTEXT 0x02000000 +#define HSTATEEN0H_SENVCFG 0x40000000 +#define HSTATEENH_SSTATEEN 0x80000000 + +#define SENVCFG_FIOM 0x00000001 +#define SENVCFG_CBIE 0x00000030 +#define SENVCFG_CBCFE 0x00000040 +#define SENVCFG_CBZE 0x00000080 + +#define SSTATEEN0_CS 0x00000001 +#define SSTATEEN0_FCSR 0x00000002 +#define SSTATEEN0_JVT 0x00000004 + +#define MSECCFG_MML 0x00000001 +#define MSECCFG_MMWP 0x00000002 +#define MSECCFG_RLB 0x00000004 +#define MSECCFG_USEED 0x00000100 +#define MSECCFG_SSEED 0x00000200 + +/* jvt fields */ +#define JVT_MODE 0x3F +#define JVT_BASE (~0x3F) + +#define PRV_U 0 +#define PRV_S 1 +#define PRV_M 3 + +#define PRV_HS (PRV_S + 1) + +#define SATP32_MODE 0x80000000 +#define SATP32_ASID 0x7FC00000 +#define SATP32_PPN 0x003FFFFF +#define SATP64_MODE 0xF000000000000000 +#define SATP64_ASID 0x0FFFF00000000000 +#define SATP64_PPN 0x00000FFFFFFFFFFF + +#define SATP_MODE_OFF 0 +#define SATP_MODE_SV32 1 +#define SATP_MODE_SV39 8 +#define SATP_MODE_SV48 9 +#define SATP_MODE_SV57 10 +#define SATP_MODE_SV64 11 + +#define HGATP32_MODE 0x80000000 +#define HGATP32_VMID 0x1FC00000 +#define HGATP32_PPN 0x003FFFFF + +#define HGATP64_MODE 0xF000000000000000 +#define HGATP64_VMID 0x03FFF00000000000 +#define HGATP64_PPN 0x00000FFFFFFFFFFF + +#define HGATP_MODE_OFF 0 +#define HGATP_MODE_SV32X4 1 +#define HGATP_MODE_SV39X4 8 +#define HGATP_MODE_SV48X4 9 +#define HGATP_MODE_SV57X4 10 + +#define PMP_R 0x01 +#define PMP_W 0x02 +#define PMP_X 0x04 +#define PMP_A 0x18 +#define PMP_L 0x80 +#define PMP_SHIFT 2 + +#define PMP_TOR 0x08 +#define PMP_NA4 0x10 +#define PMP_NAPOT 0x18 + +#define IRQ_U_SOFT 0 +#define IRQ_S_SOFT 1 +#define IRQ_VS_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_U_TIMER 4 +#define IRQ_S_TIMER 5 +#define IRQ_VS_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_U_EXT 8 +#define IRQ_S_EXT 9 +#define IRQ_VS_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_S_GEXT 12 +#define IRQ_COP 12 +#define IRQ_LCOF 13 + +/* page table entry (PTE) fields */ +#define PTE_V 0x001 /* Valid */ +#define PTE_R 0x002 /* Read */ +#define PTE_W 0x004 /* Write */ +#define PTE_X 0x008 /* Execute */ +#define PTE_U 0x010 /* User */ +#define PTE_G 0x020 /* Global */ +#define PTE_A 0x040 /* Accessed */ +#define PTE_D 0x080 /* Dirty */ +#define PTE_SOFT 0x300 /* Reserved for Software */ +#define PTE_RSVD 0x1FC0000000000000 /* Reserved for future standard use */ +#define PTE_PBMT 0x6000000000000000 /* Svpbmt: Page-based memory types */ +#define PTE_N 0x8000000000000000 /* Svnapot: NAPOT translation contiguity */ +#define PTE_ATTR 0xFFC0000000000000 /* All attributes and reserved bits */ + +#define PTE_PPN_SHIFT 10 + +#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V) + +#ifdef __riscv + +#if __riscv_xlen == 64 +# define MSTATUS_SD MSTATUS64_SD +# define SSTATUS_SD SSTATUS64_SD +# define RISCV_PGLEVEL_BITS 9 +# define SATP_MODE SATP64_MODE +#else +# define MSTATUS_SD MSTATUS32_SD +# define SSTATUS_SD SSTATUS32_SD +# define RISCV_PGLEVEL_BITS 10 +# define SATP_MODE SATP32_MODE +#endif +#define RISCV_PGSHIFT 12 +#define RISCV_PGSIZE (1 << RISCV_PGSHIFT) + +#ifndef __ASSEMBLER__ + +#ifdef __GNUC__ + +#define read_csr(reg) ({ unsigned long __tmp; \ + asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ + __tmp; }) + +#define write_csr(reg, val) ({ \ + asm volatile ("csrw " #reg ", %0" :: "rK"(val)); }) + +#define swap_csr(reg, val) ({ unsigned long __tmp; \ + asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "rK"(val)); \ + __tmp; }) + +#define set_csr(reg, bit) ({ unsigned long __tmp; \ + asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ + __tmp; }) + +#define clear_csr(reg, bit) ({ unsigned long __tmp; \ + asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ + __tmp; }) + +#define rdtime() read_csr(time) +#define rdcycle() read_csr(cycle) +#define rdinstret() read_csr(instret) + +#endif + +#endif + +#endif + +#endif + +/* Automatically generated by parse_opcodes. */ +#ifndef RISCV_ENCODING_H +#define RISCV_ENCODING_H +#define MATCH_ADD 0x33 +#define MASK_ADD 0xfe00707f +#define MATCH_ADD16 0x40000077 +#define MASK_ADD16 0xfe00707f +#define MATCH_ADD32 0x40002077 +#define MASK_ADD32 0xfe00707f +#define MATCH_ADD64 0xc0001077 +#define MASK_ADD64 0xfe00707f +#define MATCH_ADD8 0x48000077 +#define MASK_ADD8 0xfe00707f +#define MATCH_ADD_UW 0x800003b +#define MASK_ADD_UW 0xfe00707f +#define MATCH_ADDD 0x7b +#define MASK_ADDD 0xfe00707f +#define MATCH_ADDI 0x13 +#define MASK_ADDI 0x707f +#define MATCH_ADDID 0x5b +#define MASK_ADDID 0x707f +#define MATCH_ADDIW 0x1b +#define MASK_ADDIW 0x707f +#define MATCH_ADDW 0x3b +#define MASK_ADDW 0xfe00707f +#define MATCH_AES32DSI 0x2a000033 +#define MASK_AES32DSI 0x3e00707f +#define MATCH_AES32DSMI 0x2e000033 +#define MASK_AES32DSMI 0x3e00707f +#define MATCH_AES32ESI 0x22000033 +#define MASK_AES32ESI 0x3e00707f +#define MATCH_AES32ESMI 0x26000033 +#define MASK_AES32ESMI 0x3e00707f +#define MATCH_AES64DS 0x3a000033 +#define MASK_AES64DS 0xfe00707f +#define MATCH_AES64DSM 0x3e000033 +#define MASK_AES64DSM 0xfe00707f +#define MATCH_AES64ES 0x32000033 +#define MASK_AES64ES 0xfe00707f +#define MATCH_AES64ESM 0x36000033 +#define MASK_AES64ESM 0xfe00707f +#define MATCH_AES64IM 0x30001013 +#define MASK_AES64IM 0xfff0707f +#define MATCH_AES64KS1I 0x31001013 +#define MASK_AES64KS1I 0xff00707f +#define MATCH_AES64KS2 0x7e000033 +#define MASK_AES64KS2 0xfe00707f +#define MATCH_AMOADD_D 0x302f +#define MASK_AMOADD_D 0xf800707f +#define MATCH_AMOADD_W 0x202f +#define MASK_AMOADD_W 0xf800707f +#define MATCH_AMOAND_D 0x6000302f +#define MASK_AMOAND_D 0xf800707f +#define MATCH_AMOAND_W 0x6000202f +#define MASK_AMOAND_W 0xf800707f +#define MATCH_AMOMAX_D 0xa000302f +#define MASK_AMOMAX_D 0xf800707f +#define MATCH_AMOMAX_W 0xa000202f +#define MASK_AMOMAX_W 0xf800707f +#define MATCH_AMOMAXU_D 0xe000302f +#define MASK_AMOMAXU_D 0xf800707f +#define MATCH_AMOMAXU_W 0xe000202f +#define MASK_AMOMAXU_W 0xf800707f +#define MATCH_AMOMIN_D 0x8000302f +#define MASK_AMOMIN_D 0xf800707f +#define MATCH_AMOMIN_W 0x8000202f +#define MASK_AMOMIN_W 0xf800707f +#define MATCH_AMOMINU_D 0xc000302f +#define MASK_AMOMINU_D 0xf800707f +#define MATCH_AMOMINU_W 0xc000202f +#define MASK_AMOMINU_W 0xf800707f +#define MATCH_AMOOR_D 0x4000302f +#define MASK_AMOOR_D 0xf800707f +#define MATCH_AMOOR_W 0x4000202f +#define MASK_AMOOR_W 0xf800707f +#define MATCH_AMOSWAP_D 0x800302f +#define MASK_AMOSWAP_D 0xf800707f +#define MATCH_AMOSWAP_W 0x800202f +#define MASK_AMOSWAP_W 0xf800707f +#define MATCH_AMOXOR_D 0x2000302f +#define MASK_AMOXOR_D 0xf800707f +#define MATCH_AMOXOR_W 0x2000202f +#define MASK_AMOXOR_W 0xf800707f +#define MATCH_AND 0x7033 +#define MASK_AND 0xfe00707f +#define MATCH_ANDI 0x7013 +#define MASK_ANDI 0x707f +#define MATCH_ANDN 0x40007033 +#define MASK_ANDN 0xfe00707f +#define MATCH_AUIPC 0x17 +#define MASK_AUIPC 0x7f +#define MATCH_AVE 0xe0000077 +#define MASK_AVE 0xfe00707f +#define MATCH_BCLR 0x48001033 +#define MASK_BCLR 0xfe00707f +#define MATCH_BCLRI 0x48001013 +#define MASK_BCLRI 0xfc00707f +#define MATCH_BCOMPRESS 0x8006033 +#define MASK_BCOMPRESS 0xfe00707f +#define MATCH_BCOMPRESSW 0x800603b +#define MASK_BCOMPRESSW 0xfe00707f +#define MATCH_BDECOMPRESS 0x48006033 +#define MASK_BDECOMPRESS 0xfe00707f +#define MATCH_BDECOMPRESSW 0x4800603b +#define MASK_BDECOMPRESSW 0xfe00707f +#define MATCH_BEQ 0x63 +#define MASK_BEQ 0x707f +#define MATCH_BEXT 0x48005033 +#define MASK_BEXT 0xfe00707f +#define MATCH_BEXTI 0x48005013 +#define MASK_BEXTI 0xfc00707f +#define MATCH_BFP 0x48007033 +#define MASK_BFP 0xfe00707f +#define MATCH_BFPW 0x4800703b +#define MASK_BFPW 0xfe00707f +#define MATCH_BGE 0x5063 +#define MASK_BGE 0x707f +#define MATCH_BGEU 0x7063 +#define MASK_BGEU 0x707f +#define MATCH_BINV 0x68001033 +#define MASK_BINV 0xfe00707f +#define MATCH_BINVI 0x68001013 +#define MASK_BINVI 0xfc00707f +#define MATCH_BLT 0x4063 +#define MASK_BLT 0x707f +#define MATCH_BLTU 0x6063 +#define MASK_BLTU 0x707f +#define MATCH_BMATFLIP 0x60301013 +#define MASK_BMATFLIP 0xfff0707f +#define MATCH_BMATOR 0x8003033 +#define MASK_BMATOR 0xfe00707f +#define MATCH_BMATXOR 0x48003033 +#define MASK_BMATXOR 0xfe00707f +#define MATCH_BNE 0x1063 +#define MASK_BNE 0x707f +#define MATCH_BSET 0x28001033 +#define MASK_BSET 0xfe00707f +#define MATCH_BSETI 0x28001013 +#define MASK_BSETI 0xfc00707f +#define MATCH_C_ADD 0x9002 +#define MASK_C_ADD 0xf003 +#define MATCH_C_ADDI 0x1 +#define MASK_C_ADDI 0xe003 +#define MATCH_C_ADDI16SP 0x6101 +#define MASK_C_ADDI16SP 0xef83 +#define MATCH_C_ADDI4SPN 0x0 +#define MASK_C_ADDI4SPN 0xe003 +#define MATCH_C_ADDIW 0x2001 +#define MASK_C_ADDIW 0xe003 +#define MATCH_C_ADDW 0x9c21 +#define MASK_C_ADDW 0xfc63 +#define MATCH_C_AND 0x8c61 +#define MASK_C_AND 0xfc63 +#define MATCH_C_ANDI 0x8801 +#define MASK_C_ANDI 0xec03 +#define MATCH_C_BEQZ 0xc001 +#define MASK_C_BEQZ 0xe003 +#define MATCH_C_BNEZ 0xe001 +#define MASK_C_BNEZ 0xe003 +#define MATCH_C_EBREAK 0x9002 +#define MASK_C_EBREAK 0xffff +#define MATCH_C_FLD 0x2000 +#define MASK_C_FLD 0xe003 +#define MATCH_C_FLDSP 0x2002 +#define MASK_C_FLDSP 0xe003 +#define MATCH_C_FLW 0x6000 +#define MASK_C_FLW 0xe003 +#define MATCH_C_FLWSP 0x6002 +#define MASK_C_FLWSP 0xe003 +#define MATCH_C_FSD 0xa000 +#define MASK_C_FSD 0xe003 +#define MATCH_C_FSDSP 0xa002 +#define MASK_C_FSDSP 0xe003 +#define MATCH_C_FSW 0xe000 +#define MASK_C_FSW 0xe003 +#define MATCH_C_FSWSP 0xe002 +#define MASK_C_FSWSP 0xe003 +#define MATCH_C_J 0xa001 +#define MASK_C_J 0xe003 +#define MATCH_C_JAL 0x2001 +#define MASK_C_JAL 0xe003 +#define MATCH_C_JALR 0x9002 +#define MASK_C_JALR 0xf07f +#define MATCH_C_JR 0x8002 +#define MASK_C_JR 0xf07f +#define MATCH_C_LBU 0x8000 +#define MASK_C_LBU 0xfc03 +#define MATCH_C_LD 0x6000 +#define MASK_C_LD 0xe003 +#define MATCH_C_LDSP 0x6002 +#define MASK_C_LDSP 0xe003 +#define MATCH_C_LH 0x8440 +#define MASK_C_LH 0xfc43 +#define MATCH_C_LHU 0x8400 +#define MASK_C_LHU 0xfc43 +#define MATCH_C_LI 0x4001 +#define MASK_C_LI 0xe003 +#define MATCH_C_LQ 0x2000 +#define MASK_C_LQ 0xe003 +#define MATCH_C_LQSP 0x2002 +#define MASK_C_LQSP 0xe003 +#define MATCH_C_LUI 0x6001 +#define MASK_C_LUI 0xe003 +#define MATCH_C_LW 0x4000 +#define MASK_C_LW 0xe003 +#define MATCH_C_LWSP 0x4002 +#define MASK_C_LWSP 0xe003 +#define MATCH_C_MUL 0x9c41 +#define MASK_C_MUL 0xfc63 +#define MATCH_C_MV 0x8002 +#define MASK_C_MV 0xf003 +#define MATCH_C_NOP 0x1 +#define MASK_C_NOP 0xef83 +#define MATCH_C_NOT 0x9c75 +#define MASK_C_NOT 0xfc7f +#define MATCH_C_OR 0x8c41 +#define MASK_C_OR 0xfc63 +#define MATCH_C_SB 0x8800 +#define MASK_C_SB 0xfc03 +#define MATCH_C_SD 0xe000 +#define MASK_C_SD 0xe003 +#define MATCH_C_SDSP 0xe002 +#define MASK_C_SDSP 0xe003 +#define MATCH_C_SEXT_B 0x9c65 +#define MASK_C_SEXT_B 0xfc7f +#define MATCH_C_SEXT_H 0x9c6d +#define MASK_C_SEXT_H 0xfc7f +#define MATCH_C_SH 0x8c00 +#define MASK_C_SH 0xfc43 +#define MATCH_C_SLLI 0x2 +#define MASK_C_SLLI 0xe003 +#define MATCH_C_SQ 0xa000 +#define MASK_C_SQ 0xe003 +#define MATCH_C_SQSP 0xa002 +#define MASK_C_SQSP 0xe003 +#define MATCH_C_SRAI 0x8401 +#define MASK_C_SRAI 0xec03 +#define MATCH_C_SRLI 0x8001 +#define MASK_C_SRLI 0xec03 +#define MATCH_C_SUB 0x8c01 +#define MASK_C_SUB 0xfc63 +#define MATCH_C_SUBW 0x9c01 +#define MASK_C_SUBW 0xfc63 +#define MATCH_C_SW 0xc000 +#define MASK_C_SW 0xe003 +#define MATCH_C_SWSP 0xc002 +#define MASK_C_SWSP 0xe003 +#define MATCH_C_XOR 0x8c21 +#define MASK_C_XOR 0xfc63 +#define MATCH_C_ZEXT_B 0x9c61 +#define MASK_C_ZEXT_B 0xfc7f +#define MATCH_C_ZEXT_H 0x9c69 +#define MASK_C_ZEXT_H 0xfc7f +#define MATCH_C_ZEXT_W 0x9c71 +#define MASK_C_ZEXT_W 0xfc7f +#define MATCH_CBO_CLEAN 0x10200f +#define MASK_CBO_CLEAN 0xfff07fff +#define MATCH_CBO_FLUSH 0x20200f +#define MASK_CBO_FLUSH 0xfff07fff +#define MATCH_CBO_INVAL 0x200f +#define MASK_CBO_INVAL 0xfff07fff +#define MATCH_CBO_ZERO 0x40200f +#define MASK_CBO_ZERO 0xfff07fff +#define MATCH_CLMUL 0xa001033 +#define MASK_CLMUL 0xfe00707f +#define MATCH_CLMULH 0xa003033 +#define MASK_CLMULH 0xfe00707f +#define MATCH_CLMULR 0xa002033 +#define MASK_CLMULR 0xfe00707f +#define MATCH_CLRS16 0xae800077 +#define MASK_CLRS16 0xfff0707f +#define MATCH_CLRS32 0xaf800077 +#define MASK_CLRS32 0xfff0707f +#define MATCH_CLRS8 0xae000077 +#define MASK_CLRS8 0xfff0707f +#define MATCH_CLZ 0x60001013 +#define MASK_CLZ 0xfff0707f +#define MATCH_CLZ16 0xae900077 +#define MASK_CLZ16 0xfff0707f +#define MATCH_CLZ32 0xaf900077 +#define MASK_CLZ32 0xfff0707f +#define MATCH_CLZ8 0xae100077 +#define MASK_CLZ8 0xfff0707f +#define MATCH_CLZW 0x6000101b +#define MASK_CLZW 0xfff0707f +#define MATCH_CM_JALT 0xa002 +#define MASK_CM_JALT 0xfc03 +#define MATCH_CM_MVA01S 0xac62 +#define MASK_CM_MVA01S 0xfc63 +#define MATCH_CM_MVSA01 0xac22 +#define MASK_CM_MVSA01 0xfc63 +#define MATCH_CM_POP 0xba02 +#define MASK_CM_POP 0xff03 +#define MATCH_CM_POPRET 0xbe02 +#define MASK_CM_POPRET 0xff03 +#define MATCH_CM_POPRETZ 0xbc02 +#define MASK_CM_POPRETZ 0xff03 +#define MATCH_CM_PUSH 0xb802 +#define MASK_CM_PUSH 0xff03 +#define MATCH_CMIX 0x6001033 +#define MASK_CMIX 0x600707f +#define MATCH_CMOV 0x6005033 +#define MASK_CMOV 0x600707f +#define MATCH_CMPEQ16 0x4c000077 +#define MASK_CMPEQ16 0xfe00707f +#define MATCH_CMPEQ8 0x4e000077 +#define MASK_CMPEQ8 0xfe00707f +#define MATCH_CPOP 0x60201013 +#define MASK_CPOP 0xfff0707f +#define MATCH_CPOPW 0x6020101b +#define MASK_CPOPW 0xfff0707f +#define MATCH_CRAS16 0x44000077 +#define MASK_CRAS16 0xfe00707f +#define MATCH_CRAS32 0x44002077 +#define MASK_CRAS32 0xfe00707f +#define MATCH_CRC32_B 0x61001013 +#define MASK_CRC32_B 0xfff0707f +#define MATCH_CRC32_D 0x61301013 +#define MASK_CRC32_D 0xfff0707f +#define MATCH_CRC32_H 0x61101013 +#define MASK_CRC32_H 0xfff0707f +#define MATCH_CRC32_W 0x61201013 +#define MASK_CRC32_W 0xfff0707f +#define MATCH_CRC32C_B 0x61801013 +#define MASK_CRC32C_B 0xfff0707f +#define MATCH_CRC32C_D 0x61b01013 +#define MASK_CRC32C_D 0xfff0707f +#define MATCH_CRC32C_H 0x61901013 +#define MASK_CRC32C_H 0xfff0707f +#define MATCH_CRC32C_W 0x61a01013 +#define MASK_CRC32C_W 0xfff0707f +#define MATCH_CRSA16 0x46000077 +#define MASK_CRSA16 0xfe00707f +#define MATCH_CRSA32 0x46002077 +#define MASK_CRSA32 0xfe00707f +#define MATCH_CSRRC 0x3073 +#define MASK_CSRRC 0x707f +#define MATCH_CSRRCI 0x7073 +#define MASK_CSRRCI 0x707f +#define MATCH_CSRRS 0x2073 +#define MASK_CSRRS 0x707f +#define MATCH_CSRRSI 0x6073 +#define MASK_CSRRSI 0x707f +#define MATCH_CSRRW 0x1073 +#define MASK_CSRRW 0x707f +#define MATCH_CSRRWI 0x5073 +#define MASK_CSRRWI 0x707f +#define MATCH_CTZ 0x60101013 +#define MASK_CTZ 0xfff0707f +#define MATCH_CTZW 0x6010101b +#define MASK_CTZW 0xfff0707f +#define MATCH_CZERO_EQZ 0xe005033 +#define MASK_CZERO_EQZ 0xfe00707f +#define MATCH_CZERO_NEZ 0xe007033 +#define MASK_CZERO_NEZ 0xfe00707f +#define MATCH_DIV 0x2004033 +#define MASK_DIV 0xfe00707f +#define MATCH_DIVU 0x2005033 +#define MASK_DIVU 0xfe00707f +#define MATCH_DIVUW 0x200503b +#define MASK_DIVUW 0xfe00707f +#define MATCH_DIVW 0x200403b +#define MASK_DIVW 0xfe00707f +#define MATCH_DRET 0x7b200073 +#define MASK_DRET 0xffffffff +#define MATCH_EBREAK 0x100073 +#define MASK_EBREAK 0xffffffff +#define MATCH_ECALL 0x73 +#define MASK_ECALL 0xffffffff +#define MATCH_FADD_D 0x2000053 +#define MASK_FADD_D 0xfe00007f +#define MATCH_FADD_H 0x4000053 +#define MASK_FADD_H 0xfe00007f +#define MATCH_FADD_Q 0x6000053 +#define MASK_FADD_Q 0xfe00007f +#define MATCH_FADD_S 0x53 +#define MASK_FADD_S 0xfe00007f +#define MATCH_FCLASS_D 0xe2001053 +#define MASK_FCLASS_D 0xfff0707f +#define MATCH_FCLASS_H 0xe4001053 +#define MASK_FCLASS_H 0xfff0707f +#define MATCH_FCLASS_Q 0xe6001053 +#define MASK_FCLASS_Q 0xfff0707f +#define MATCH_FCLASS_S 0xe0001053 +#define MASK_FCLASS_S 0xfff0707f +#define MATCH_FCVT_D_H 0x42200053 +#define MASK_FCVT_D_H 0xfff0007f +#define MATCH_FCVT_D_L 0xd2200053 +#define MASK_FCVT_D_L 0xfff0007f +#define MATCH_FCVT_D_LU 0xd2300053 +#define MASK_FCVT_D_LU 0xfff0007f +#define MATCH_FCVT_D_Q 0x42300053 +#define MASK_FCVT_D_Q 0xfff0007f +#define MATCH_FCVT_D_S 0x42000053 +#define MASK_FCVT_D_S 0xfff0007f +#define MATCH_FCVT_D_W 0xd2000053 +#define MASK_FCVT_D_W 0xfff0007f +#define MATCH_FCVT_D_WU 0xd2100053 +#define MASK_FCVT_D_WU 0xfff0007f +#define MATCH_FCVT_H_D 0x44100053 +#define MASK_FCVT_H_D 0xfff0007f +#define MATCH_FCVT_H_L 0xd4200053 +#define MASK_FCVT_H_L 0xfff0007f +#define MATCH_FCVT_H_LU 0xd4300053 +#define MASK_FCVT_H_LU 0xfff0007f +#define MATCH_FCVT_H_Q 0x44300053 +#define MASK_FCVT_H_Q 0xfff0007f +#define MATCH_FCVT_H_S 0x44000053 +#define MASK_FCVT_H_S 0xfff0007f +#define MATCH_FCVT_H_W 0xd4000053 +#define MASK_FCVT_H_W 0xfff0007f +#define MATCH_FCVT_H_WU 0xd4100053 +#define MASK_FCVT_H_WU 0xfff0007f +#define MATCH_FCVT_L_D 0xc2200053 +#define MASK_FCVT_L_D 0xfff0007f +#define MATCH_FCVT_L_H 0xc4200053 +#define MASK_FCVT_L_H 0xfff0007f +#define MATCH_FCVT_L_Q 0xc6200053 +#define MASK_FCVT_L_Q 0xfff0007f +#define MATCH_FCVT_L_S 0xc0200053 +#define MASK_FCVT_L_S 0xfff0007f +#define MATCH_FCVT_LU_D 0xc2300053 +#define MASK_FCVT_LU_D 0xfff0007f +#define MATCH_FCVT_LU_H 0xc4300053 +#define MASK_FCVT_LU_H 0xfff0007f +#define MATCH_FCVT_LU_Q 0xc6300053 +#define MASK_FCVT_LU_Q 0xfff0007f +#define MATCH_FCVT_LU_S 0xc0300053 +#define MASK_FCVT_LU_S 0xfff0007f +#define MATCH_FCVT_Q_D 0x46100053 +#define MASK_FCVT_Q_D 0xfff0007f +#define MATCH_FCVT_Q_H 0x46200053 +#define MASK_FCVT_Q_H 0xfff0007f +#define MATCH_FCVT_Q_L 0xd6200053 +#define MASK_FCVT_Q_L 0xfff0007f +#define MATCH_FCVT_Q_LU 0xd6300053 +#define MASK_FCVT_Q_LU 0xfff0007f +#define MATCH_FCVT_Q_S 0x46000053 +#define MASK_FCVT_Q_S 0xfff0007f +#define MATCH_FCVT_Q_W 0xd6000053 +#define MASK_FCVT_Q_W 0xfff0007f +#define MATCH_FCVT_Q_WU 0xd6100053 +#define MASK_FCVT_Q_WU 0xfff0007f +#define MATCH_FCVT_S_D 0x40100053 +#define MASK_FCVT_S_D 0xfff0007f +#define MATCH_FCVT_S_H 0x40200053 +#define MASK_FCVT_S_H 0xfff0007f +#define MATCH_FCVT_S_L 0xd0200053 +#define MASK_FCVT_S_L 0xfff0007f +#define MATCH_FCVT_S_LU 0xd0300053 +#define MASK_FCVT_S_LU 0xfff0007f +#define MATCH_FCVT_S_Q 0x40300053 +#define MASK_FCVT_S_Q 0xfff0007f +#define MATCH_FCVT_S_W 0xd0000053 +#define MASK_FCVT_S_W 0xfff0007f +#define MATCH_FCVT_S_WU 0xd0100053 +#define MASK_FCVT_S_WU 0xfff0007f +#define MATCH_FCVT_W_D 0xc2000053 +#define MASK_FCVT_W_D 0xfff0007f +#define MATCH_FCVT_W_H 0xc4000053 +#define MASK_FCVT_W_H 0xfff0007f +#define MATCH_FCVT_W_Q 0xc6000053 +#define MASK_FCVT_W_Q 0xfff0007f +#define MATCH_FCVT_W_S 0xc0000053 +#define MASK_FCVT_W_S 0xfff0007f +#define MATCH_FCVT_WU_D 0xc2100053 +#define MASK_FCVT_WU_D 0xfff0007f +#define MATCH_FCVT_WU_H 0xc4100053 +#define MASK_FCVT_WU_H 0xfff0007f +#define MATCH_FCVT_WU_Q 0xc6100053 +#define MASK_FCVT_WU_Q 0xfff0007f +#define MATCH_FCVT_WU_S 0xc0100053 +#define MASK_FCVT_WU_S 0xfff0007f +#define MATCH_FCVTMOD_W_D 0xc2801053 +#define MASK_FCVTMOD_W_D 0xfff0707f +#define MATCH_FDIV_D 0x1a000053 +#define MASK_FDIV_D 0xfe00007f +#define MATCH_FDIV_H 0x1c000053 +#define MASK_FDIV_H 0xfe00007f +#define MATCH_FDIV_Q 0x1e000053 +#define MASK_FDIV_Q 0xfe00007f +#define MATCH_FDIV_S 0x18000053 +#define MASK_FDIV_S 0xfe00007f +#define MATCH_FENCE 0xf +#define MASK_FENCE 0x707f +#define MATCH_FENCE_I 0x100f +#define MASK_FENCE_I 0x707f +#define MATCH_FEQ_D 0xa2002053 +#define MASK_FEQ_D 0xfe00707f +#define MATCH_FEQ_H 0xa4002053 +#define MASK_FEQ_H 0xfe00707f +#define MATCH_FEQ_Q 0xa6002053 +#define MASK_FEQ_Q 0xfe00707f +#define MATCH_FEQ_S 0xa0002053 +#define MASK_FEQ_S 0xfe00707f +#define MATCH_FLD 0x3007 +#define MASK_FLD 0x707f +#define MATCH_FLE_D 0xa2000053 +#define MASK_FLE_D 0xfe00707f +#define MATCH_FLE_H 0xa4000053 +#define MASK_FLE_H 0xfe00707f +#define MATCH_FLE_Q 0xa6000053 +#define MASK_FLE_Q 0xfe00707f +#define MATCH_FLE_S 0xa0000053 +#define MASK_FLE_S 0xfe00707f +#define MATCH_FLEQ_D 0xa2004053 +#define MASK_FLEQ_D 0xfe00707f +#define MATCH_FLEQ_H 0xa4004053 +#define MASK_FLEQ_H 0xfe00707f +#define MATCH_FLEQ_Q 0xa6004053 +#define MASK_FLEQ_Q 0xfe00707f +#define MATCH_FLEQ_S 0xa0004053 +#define MASK_FLEQ_S 0xfe00707f +#define MATCH_FLH 0x1007 +#define MASK_FLH 0x707f +#define MATCH_FLI_D 0xf2100053 +#define MASK_FLI_D 0xfff0707f +#define MATCH_FLI_H 0xf4100053 +#define MASK_FLI_H 0xfff0707f +#define MATCH_FLI_Q 0xf6100053 +#define MASK_FLI_Q 0xfff0707f +#define MATCH_FLI_S 0xf0100053 +#define MASK_FLI_S 0xfff0707f +#define MATCH_FLQ 0x4007 +#define MASK_FLQ 0x707f +#define MATCH_FLT_D 0xa2001053 +#define MASK_FLT_D 0xfe00707f +#define MATCH_FLT_H 0xa4001053 +#define MASK_FLT_H 0xfe00707f +#define MATCH_FLT_Q 0xa6001053 +#define MASK_FLT_Q 0xfe00707f +#define MATCH_FLT_S 0xa0001053 +#define MASK_FLT_S 0xfe00707f +#define MATCH_FLTQ_D 0xa2005053 +#define MASK_FLTQ_D 0xfe00707f +#define MATCH_FLTQ_H 0xa4005053 +#define MASK_FLTQ_H 0xfe00707f +#define MATCH_FLTQ_Q 0xa6005053 +#define MASK_FLTQ_Q 0xfe00707f +#define MATCH_FLTQ_S 0xa0005053 +#define MASK_FLTQ_S 0xfe00707f +#define MATCH_FLW 0x2007 +#define MASK_FLW 0x707f +#define MATCH_FMADD_D 0x2000043 +#define MASK_FMADD_D 0x600007f +#define MATCH_FMADD_H 0x4000043 +#define MASK_FMADD_H 0x600007f +#define MATCH_FMADD_Q 0x6000043 +#define MASK_FMADD_Q 0x600007f +#define MATCH_FMADD_S 0x43 +#define MASK_FMADD_S 0x600007f +#define MATCH_FMAX_D 0x2a001053 +#define MASK_FMAX_D 0xfe00707f +#define MATCH_FMAX_H 0x2c001053 +#define MASK_FMAX_H 0xfe00707f +#define MATCH_FMAX_Q 0x2e001053 +#define MASK_FMAX_Q 0xfe00707f +#define MATCH_FMAX_S 0x28001053 +#define MASK_FMAX_S 0xfe00707f +#define MATCH_FMAXM_D 0x2a003053 +#define MASK_FMAXM_D 0xfe00707f +#define MATCH_FMAXM_H 0x2c003053 +#define MASK_FMAXM_H 0xfe00707f +#define MATCH_FMAXM_Q 0x2e003053 +#define MASK_FMAXM_Q 0xfe00707f +#define MATCH_FMAXM_S 0x28003053 +#define MASK_FMAXM_S 0xfe00707f +#define MATCH_FMIN_D 0x2a000053 +#define MASK_FMIN_D 0xfe00707f +#define MATCH_FMIN_H 0x2c000053 +#define MASK_FMIN_H 0xfe00707f +#define MATCH_FMIN_Q 0x2e000053 +#define MASK_FMIN_Q 0xfe00707f +#define MATCH_FMIN_S 0x28000053 +#define MASK_FMIN_S 0xfe00707f +#define MATCH_FMINM_D 0x2a002053 +#define MASK_FMINM_D 0xfe00707f +#define MATCH_FMINM_H 0x2c002053 +#define MASK_FMINM_H 0xfe00707f +#define MATCH_FMINM_Q 0x2e002053 +#define MASK_FMINM_Q 0xfe00707f +#define MATCH_FMINM_S 0x28002053 +#define MASK_FMINM_S 0xfe00707f +#define MATCH_FMSUB_D 0x2000047 +#define MASK_FMSUB_D 0x600007f +#define MATCH_FMSUB_H 0x4000047 +#define MASK_FMSUB_H 0x600007f +#define MATCH_FMSUB_Q 0x6000047 +#define MASK_FMSUB_Q 0x600007f +#define MATCH_FMSUB_S 0x47 +#define MASK_FMSUB_S 0x600007f +#define MATCH_FMUL_D 0x12000053 +#define MASK_FMUL_D 0xfe00007f +#define MATCH_FMUL_H 0x14000053 +#define MASK_FMUL_H 0xfe00007f +#define MATCH_FMUL_Q 0x16000053 +#define MASK_FMUL_Q 0xfe00007f +#define MATCH_FMUL_S 0x10000053 +#define MASK_FMUL_S 0xfe00007f +#define MATCH_FMV_D_X 0xf2000053 +#define MASK_FMV_D_X 0xfff0707f +#define MATCH_FMV_H_X 0xf4000053 +#define MASK_FMV_H_X 0xfff0707f +#define MATCH_FMV_W_X 0xf0000053 +#define MASK_FMV_W_X 0xfff0707f +#define MATCH_FMV_X_D 0xe2000053 +#define MASK_FMV_X_D 0xfff0707f +#define MATCH_FMV_X_H 0xe4000053 +#define MASK_FMV_X_H 0xfff0707f +#define MATCH_FMV_X_W 0xe0000053 +#define MASK_FMV_X_W 0xfff0707f +#define MATCH_FMVH_X_D 0xe2100053 +#define MASK_FMVH_X_D 0xfff0707f +#define MATCH_FMVH_X_Q 0xe6100053 +#define MASK_FMVH_X_Q 0xfff0707f +#define MATCH_FMVP_D_X 0xb2100053 +#define MASK_FMVP_D_X 0xfff0707f +#define MATCH_FMVP_Q_X 0xb6100053 +#define MASK_FMVP_Q_X 0xfff0707f +#define MATCH_FNMADD_D 0x200004f +#define MASK_FNMADD_D 0x600007f +#define MATCH_FNMADD_H 0x400004f +#define MASK_FNMADD_H 0x600007f +#define MATCH_FNMADD_Q 0x600004f +#define MASK_FNMADD_Q 0x600007f +#define MATCH_FNMADD_S 0x4f +#define MASK_FNMADD_S 0x600007f +#define MATCH_FNMSUB_D 0x200004b +#define MASK_FNMSUB_D 0x600007f +#define MATCH_FNMSUB_H 0x400004b +#define MASK_FNMSUB_H 0x600007f +#define MATCH_FNMSUB_Q 0x600004b +#define MASK_FNMSUB_Q 0x600007f +#define MATCH_FNMSUB_S 0x4b +#define MASK_FNMSUB_S 0x600007f +#define MATCH_FROUND_D 0x42400053 +#define MASK_FROUND_D 0xfff0007f +#define MATCH_FROUND_H 0x44400053 +#define MASK_FROUND_H 0xfff0007f +#define MATCH_FROUND_Q 0x46400053 +#define MASK_FROUND_Q 0xfff0007f +#define MATCH_FROUND_S 0x40400053 +#define MASK_FROUND_S 0xfff0007f +#define MATCH_FROUNDNX_D 0x42500053 +#define MASK_FROUNDNX_D 0xfff0007f +#define MATCH_FROUNDNX_H 0x44500053 +#define MASK_FROUNDNX_H 0xfff0007f +#define MATCH_FROUNDNX_Q 0x46500053 +#define MASK_FROUNDNX_Q 0xfff0007f +#define MATCH_FROUNDNX_S 0x40500053 +#define MASK_FROUNDNX_S 0xfff0007f +#define MATCH_FSD 0x3027 +#define MASK_FSD 0x707f +#define MATCH_FSGNJ_D 0x22000053 +#define MASK_FSGNJ_D 0xfe00707f +#define MATCH_FSGNJ_H 0x24000053 +#define MASK_FSGNJ_H 0xfe00707f +#define MATCH_FSGNJ_Q 0x26000053 +#define MASK_FSGNJ_Q 0xfe00707f +#define MATCH_FSGNJ_S 0x20000053 +#define MASK_FSGNJ_S 0xfe00707f +#define MATCH_FSGNJN_D 0x22001053 +#define MASK_FSGNJN_D 0xfe00707f +#define MATCH_FSGNJN_H 0x24001053 +#define MASK_FSGNJN_H 0xfe00707f +#define MATCH_FSGNJN_Q 0x26001053 +#define MASK_FSGNJN_Q 0xfe00707f +#define MATCH_FSGNJN_S 0x20001053 +#define MASK_FSGNJN_S 0xfe00707f +#define MATCH_FSGNJX_D 0x22002053 +#define MASK_FSGNJX_D 0xfe00707f +#define MATCH_FSGNJX_H 0x24002053 +#define MASK_FSGNJX_H 0xfe00707f +#define MATCH_FSGNJX_Q 0x26002053 +#define MASK_FSGNJX_Q 0xfe00707f +#define MATCH_FSGNJX_S 0x20002053 +#define MASK_FSGNJX_S 0xfe00707f +#define MATCH_FSH 0x1027 +#define MASK_FSH 0x707f +#define MATCH_FSL 0x4001033 +#define MASK_FSL 0x600707f +#define MATCH_FSLW 0x400103b +#define MASK_FSLW 0x600707f +#define MATCH_FSQ 0x4027 +#define MASK_FSQ 0x707f +#define MATCH_FSQRT_D 0x5a000053 +#define MASK_FSQRT_D 0xfff0007f +#define MATCH_FSQRT_H 0x5c000053 +#define MASK_FSQRT_H 0xfff0007f +#define MATCH_FSQRT_Q 0x5e000053 +#define MASK_FSQRT_Q 0xfff0007f +#define MATCH_FSQRT_S 0x58000053 +#define MASK_FSQRT_S 0xfff0007f +#define MATCH_FSR 0x4005033 +#define MASK_FSR 0x600707f +#define MATCH_FSRI 0x4005013 +#define MASK_FSRI 0x400707f +#define MATCH_FSRIW 0x400501b +#define MASK_FSRIW 0x600707f +#define MATCH_FSRW 0x400503b +#define MASK_FSRW 0x600707f +#define MATCH_FSUB_D 0xa000053 +#define MASK_FSUB_D 0xfe00007f +#define MATCH_FSUB_H 0xc000053 +#define MASK_FSUB_H 0xfe00007f +#define MATCH_FSUB_Q 0xe000053 +#define MASK_FSUB_Q 0xfe00007f +#define MATCH_FSUB_S 0x8000053 +#define MASK_FSUB_S 0xfe00007f +#define MATCH_FSW 0x2027 +#define MASK_FSW 0x707f +#define MATCH_GORC 0x28005033 +#define MASK_GORC 0xfe00707f +#define MATCH_GORCI 0x28005013 +#define MASK_GORCI 0xfc00707f +#define MATCH_GORCIW 0x2800501b +#define MASK_GORCIW 0xfe00707f +#define MATCH_GORCW 0x2800503b +#define MASK_GORCW 0xfe00707f +#define MATCH_GREV 0x68005033 +#define MASK_GREV 0xfe00707f +#define MATCH_GREVI 0x68005013 +#define MASK_GREVI 0xfc00707f +#define MATCH_GREVIW 0x6800501b +#define MASK_GREVIW 0xfe00707f +#define MATCH_GREVW 0x6800503b +#define MASK_GREVW 0xfe00707f +#define MATCH_HFENCE_GVMA 0x62000073 +#define MASK_HFENCE_GVMA 0xfe007fff +#define MATCH_HFENCE_VVMA 0x22000073 +#define MASK_HFENCE_VVMA 0xfe007fff +#define MATCH_HINVAL_GVMA 0x66000073 +#define MASK_HINVAL_GVMA 0xfe007fff +#define MATCH_HINVAL_VVMA 0x26000073 +#define MASK_HINVAL_VVMA 0xfe007fff +#define MATCH_HLV_B 0x60004073 +#define MASK_HLV_B 0xfff0707f +#define MATCH_HLV_BU 0x60104073 +#define MASK_HLV_BU 0xfff0707f +#define MATCH_HLV_D 0x6c004073 +#define MASK_HLV_D 0xfff0707f +#define MATCH_HLV_H 0x64004073 +#define MASK_HLV_H 0xfff0707f +#define MATCH_HLV_HU 0x64104073 +#define MASK_HLV_HU 0xfff0707f +#define MATCH_HLV_W 0x68004073 +#define MASK_HLV_W 0xfff0707f +#define MATCH_HLV_WU 0x68104073 +#define MASK_HLV_WU 0xfff0707f +#define MATCH_HLVX_HU 0x64304073 +#define MASK_HLVX_HU 0xfff0707f +#define MATCH_HLVX_WU 0x68304073 +#define MASK_HLVX_WU 0xfff0707f +#define MATCH_HSV_B 0x62004073 +#define MASK_HSV_B 0xfe007fff +#define MATCH_HSV_D 0x6e004073 +#define MASK_HSV_D 0xfe007fff +#define MATCH_HSV_H 0x66004073 +#define MASK_HSV_H 0xfe007fff +#define MATCH_HSV_W 0x6a004073 +#define MASK_HSV_W 0xfe007fff +#define MATCH_INSB 0xac000077 +#define MASK_INSB 0xff80707f +#define MATCH_JAL 0x6f +#define MASK_JAL 0x7f +#define MATCH_JALR 0x67 +#define MASK_JALR 0x707f +#define MATCH_KABS16 0xad100077 +#define MASK_KABS16 0xfff0707f +#define MATCH_KABS32 0xad200077 +#define MASK_KABS32 0xfff0707f +#define MATCH_KABS8 0xad000077 +#define MASK_KABS8 0xfff0707f +#define MATCH_KABSW 0xad400077 +#define MASK_KABSW 0xfff0707f +#define MATCH_KADD16 0x10000077 +#define MASK_KADD16 0xfe00707f +#define MATCH_KADD32 0x10002077 +#define MASK_KADD32 0xfe00707f +#define MATCH_KADD64 0x90001077 +#define MASK_KADD64 0xfe00707f +#define MATCH_KADD8 0x18000077 +#define MASK_KADD8 0xfe00707f +#define MATCH_KADDH 0x4001077 +#define MASK_KADDH 0xfe00707f +#define MATCH_KADDW 0x1077 +#define MASK_KADDW 0xfe00707f +#define MATCH_KCRAS16 0x14000077 +#define MASK_KCRAS16 0xfe00707f +#define MATCH_KCRAS32 0x14002077 +#define MASK_KCRAS32 0xfe00707f +#define MATCH_KCRSA16 0x16000077 +#define MASK_KCRSA16 0xfe00707f +#define MATCH_KCRSA32 0x16002077 +#define MASK_KCRSA32 0xfe00707f +#define MATCH_KDMABB 0xd2001077 +#define MASK_KDMABB 0xfe00707f +#define MATCH_KDMABB16 0xd8001077 +#define MASK_KDMABB16 0xfe00707f +#define MATCH_KDMABT 0xe2001077 +#define MASK_KDMABT 0xfe00707f +#define MATCH_KDMABT16 0xe8001077 +#define MASK_KDMABT16 0xfe00707f +#define MATCH_KDMATT 0xf2001077 +#define MASK_KDMATT 0xfe00707f +#define MATCH_KDMATT16 0xf8001077 +#define MASK_KDMATT16 0xfe00707f +#define MATCH_KDMBB 0xa001077 +#define MASK_KDMBB 0xfe00707f +#define MATCH_KDMBB16 0xda001077 +#define MASK_KDMBB16 0xfe00707f +#define MATCH_KDMBT 0x1a001077 +#define MASK_KDMBT 0xfe00707f +#define MATCH_KDMBT16 0xea001077 +#define MASK_KDMBT16 0xfe00707f +#define MATCH_KDMTT 0x2a001077 +#define MASK_KDMTT 0xfe00707f +#define MATCH_KDMTT16 0xfa001077 +#define MASK_KDMTT16 0xfe00707f +#define MATCH_KHM16 0x86000077 +#define MASK_KHM16 0xfe00707f +#define MATCH_KHM8 0x8e000077 +#define MASK_KHM8 0xfe00707f +#define MATCH_KHMBB 0xc001077 +#define MASK_KHMBB 0xfe00707f +#define MATCH_KHMBB16 0xdc001077 +#define MASK_KHMBB16 0xfe00707f +#define MATCH_KHMBT 0x1c001077 +#define MASK_KHMBT 0xfe00707f +#define MATCH_KHMBT16 0xec001077 +#define MASK_KHMBT16 0xfe00707f +#define MATCH_KHMTT 0x2c001077 +#define MASK_KHMTT 0xfe00707f +#define MATCH_KHMTT16 0xfc001077 +#define MASK_KHMTT16 0xfe00707f +#define MATCH_KHMX16 0x96000077 +#define MASK_KHMX16 0xfe00707f +#define MATCH_KHMX8 0x9e000077 +#define MASK_KHMX8 0xfe00707f +#define MATCH_KMABB 0x5a001077 +#define MASK_KMABB 0xfe00707f +#define MATCH_KMABB32 0x5a002077 +#define MASK_KMABB32 0xfe00707f +#define MATCH_KMABT 0x6a001077 +#define MASK_KMABT 0xfe00707f +#define MATCH_KMABT32 0x6a002077 +#define MASK_KMABT32 0xfe00707f +#define MATCH_KMADA 0x48001077 +#define MASK_KMADA 0xfe00707f +#define MATCH_KMADRS 0x6c001077 +#define MASK_KMADRS 0xfe00707f +#define MATCH_KMADRS32 0x6c002077 +#define MASK_KMADRS32 0xfe00707f +#define MATCH_KMADS 0x5c001077 +#define MASK_KMADS 0xfe00707f +#define MATCH_KMADS32 0x5c002077 +#define MASK_KMADS32 0xfe00707f +#define MATCH_KMAR64 0x94001077 +#define MASK_KMAR64 0xfe00707f +#define MATCH_KMATT 0x7a001077 +#define MASK_KMATT 0xfe00707f +#define MATCH_KMATT32 0x7a002077 +#define MASK_KMATT32 0xfe00707f +#define MATCH_KMAXDA 0x4a001077 +#define MASK_KMAXDA 0xfe00707f +#define MATCH_KMAXDA32 0x4a002077 +#define MASK_KMAXDA32 0xfe00707f +#define MATCH_KMAXDS 0x7c001077 +#define MASK_KMAXDS 0xfe00707f +#define MATCH_KMAXDS32 0x7c002077 +#define MASK_KMAXDS32 0xfe00707f +#define MATCH_KMDA 0x38001077 +#define MASK_KMDA 0xfe00707f +#define MATCH_KMDA32 0x38002077 +#define MASK_KMDA32 0xfe00707f +#define MATCH_KMMAC 0x60001077 +#define MASK_KMMAC 0xfe00707f +#define MATCH_KMMAC_U 0x70001077 +#define MASK_KMMAC_U 0xfe00707f +#define MATCH_KMMAWB 0x46001077 +#define MASK_KMMAWB 0xfe00707f +#define MATCH_KMMAWB2 0xce001077 +#define MASK_KMMAWB2 0xfe00707f +#define MATCH_KMMAWB2_U 0xde001077 +#define MASK_KMMAWB2_U 0xfe00707f +#define MATCH_KMMAWB_U 0x56001077 +#define MASK_KMMAWB_U 0xfe00707f +#define MATCH_KMMAWT 0x66001077 +#define MASK_KMMAWT 0xfe00707f +#define MATCH_KMMAWT2 0xee001077 +#define MASK_KMMAWT2 0xfe00707f +#define MATCH_KMMAWT2_U 0xfe001077 +#define MASK_KMMAWT2_U 0xfe00707f +#define MATCH_KMMAWT_U 0x76001077 +#define MASK_KMMAWT_U 0xfe00707f +#define MATCH_KMMSB 0x42001077 +#define MASK_KMMSB 0xfe00707f +#define MATCH_KMMSB_U 0x52001077 +#define MASK_KMMSB_U 0xfe00707f +#define MATCH_KMMWB2 0x8e001077 +#define MASK_KMMWB2 0xfe00707f +#define MATCH_KMMWB2_U 0x9e001077 +#define MASK_KMMWB2_U 0xfe00707f +#define MATCH_KMMWT2 0xae001077 +#define MASK_KMMWT2 0xfe00707f +#define MATCH_KMMWT2_U 0xbe001077 +#define MASK_KMMWT2_U 0xfe00707f +#define MATCH_KMSDA 0x4c001077 +#define MASK_KMSDA 0xfe00707f +#define MATCH_KMSDA32 0x4c002077 +#define MASK_KMSDA32 0xfe00707f +#define MATCH_KMSR64 0x96001077 +#define MASK_KMSR64 0xfe00707f +#define MATCH_KMSXDA 0x4e001077 +#define MASK_KMSXDA 0xfe00707f +#define MATCH_KMSXDA32 0x4e002077 +#define MASK_KMSXDA32 0xfe00707f +#define MATCH_KMXDA 0x3a001077 +#define MASK_KMXDA 0xfe00707f +#define MATCH_KMXDA32 0x3a002077 +#define MASK_KMXDA32 0xfe00707f +#define MATCH_KSLL16 0x64000077 +#define MASK_KSLL16 0xfe00707f +#define MATCH_KSLL32 0x64002077 +#define MASK_KSLL32 0xfe00707f +#define MATCH_KSLL8 0x6c000077 +#define MASK_KSLL8 0xfe00707f +#define MATCH_KSLLI16 0x75000077 +#define MASK_KSLLI16 0xff00707f +#define MATCH_KSLLI32 0x84002077 +#define MASK_KSLLI32 0xfe00707f +#define MATCH_KSLLI8 0x7c800077 +#define MASK_KSLLI8 0xff80707f +#define MATCH_KSLLIW 0x36001077 +#define MASK_KSLLIW 0xfe00707f +#define MATCH_KSLLW 0x26001077 +#define MASK_KSLLW 0xfe00707f +#define MATCH_KSLRA16 0x56000077 +#define MASK_KSLRA16 0xfe00707f +#define MATCH_KSLRA16_U 0x66000077 +#define MASK_KSLRA16_U 0xfe00707f +#define MATCH_KSLRA32 0x56002077 +#define MASK_KSLRA32 0xfe00707f +#define MATCH_KSLRA32_U 0x66002077 +#define MASK_KSLRA32_U 0xfe00707f +#define MATCH_KSLRA8 0x5e000077 +#define MASK_KSLRA8 0xfe00707f +#define MATCH_KSLRA8_U 0x6e000077 +#define MASK_KSLRA8_U 0xfe00707f +#define MATCH_KSLRAW 0x6e001077 +#define MASK_KSLRAW 0xfe00707f +#define MATCH_KSLRAW_U 0x7e001077 +#define MASK_KSLRAW_U 0xfe00707f +#define MATCH_KSTAS16 0xc4002077 +#define MASK_KSTAS16 0xfe00707f +#define MATCH_KSTAS32 0xc0002077 +#define MASK_KSTAS32 0xfe00707f +#define MATCH_KSTSA16 0xc6002077 +#define MASK_KSTSA16 0xfe00707f +#define MATCH_KSTSA32 0xc2002077 +#define MASK_KSTSA32 0xfe00707f +#define MATCH_KSUB16 0x12000077 +#define MASK_KSUB16 0xfe00707f +#define MATCH_KSUB32 0x12002077 +#define MASK_KSUB32 0xfe00707f +#define MATCH_KSUB64 0x92001077 +#define MASK_KSUB64 0xfe00707f +#define MATCH_KSUB8 0x1a000077 +#define MASK_KSUB8 0xfe00707f +#define MATCH_KSUBH 0x6001077 +#define MASK_KSUBH 0xfe00707f +#define MATCH_KSUBW 0x2001077 +#define MASK_KSUBW 0xfe00707f +#define MATCH_KWMMUL 0x62001077 +#define MASK_KWMMUL 0xfe00707f +#define MATCH_KWMMUL_U 0x72001077 +#define MASK_KWMMUL_U 0xfe00707f +#define MATCH_LB 0x3 +#define MASK_LB 0x707f +#define MATCH_LBU 0x4003 +#define MASK_LBU 0x707f +#define MATCH_LD 0x3003 +#define MASK_LD 0x707f +#define MATCH_LDU 0x7003 +#define MASK_LDU 0x707f +#define MATCH_LH 0x1003 +#define MASK_LH 0x707f +#define MATCH_LHU 0x5003 +#define MASK_LHU 0x707f +#define MATCH_LQ 0x300f +#define MASK_LQ 0x707f +#define MATCH_LR_D 0x1000302f +#define MASK_LR_D 0xf9f0707f +#define MATCH_LR_W 0x1000202f +#define MASK_LR_W 0xf9f0707f +#define MATCH_LUI 0x37 +#define MASK_LUI 0x7f +#define MATCH_LW 0x2003 +#define MASK_LW 0x707f +#define MATCH_LWU 0x6003 +#define MASK_LWU 0x707f +#define MATCH_MADDR32 0xc4001077 +#define MASK_MADDR32 0xfe00707f +#define MATCH_MAX 0xa006033 +#define MASK_MAX 0xfe00707f +#define MATCH_MAXU 0xa007033 +#define MASK_MAXU 0xfe00707f +#define MATCH_MIN 0xa004033 +#define MASK_MIN 0xfe00707f +#define MATCH_MINU 0xa005033 +#define MASK_MINU 0xfe00707f +#define MATCH_MNRET 0x70200073 +#define MASK_MNRET 0xffffffff +#define MATCH_MRET 0x30200073 +#define MASK_MRET 0xffffffff +#define MATCH_MSUBR32 0xc6001077 +#define MASK_MSUBR32 0xfe00707f +#define MATCH_MUL 0x2000033 +#define MASK_MUL 0xfe00707f +#define MATCH_MULH 0x2001033 +#define MASK_MULH 0xfe00707f +#define MATCH_MULHSU 0x2002033 +#define MASK_MULHSU 0xfe00707f +#define MATCH_MULHU 0x2003033 +#define MASK_MULHU 0xfe00707f +#define MATCH_MULR64 0xf0001077 +#define MASK_MULR64 0xfe00707f +#define MATCH_MULSR64 0xe0001077 +#define MASK_MULSR64 0xfe00707f +#define MATCH_MULW 0x200003b +#define MASK_MULW 0xfe00707f +#define MATCH_OR 0x6033 +#define MASK_OR 0xfe00707f +#define MATCH_ORI 0x6013 +#define MASK_ORI 0x707f +#define MATCH_ORN 0x40006033 +#define MASK_ORN 0xfe00707f +#define MATCH_PACK 0x8004033 +#define MASK_PACK 0xfe00707f +#define MATCH_PACKH 0x8007033 +#define MASK_PACKH 0xfe00707f +#define MATCH_PACKU 0x48004033 +#define MASK_PACKU 0xfe00707f +#define MATCH_PACKUW 0x4800403b +#define MASK_PACKUW 0xfe00707f +#define MATCH_PACKW 0x800403b +#define MASK_PACKW 0xfe00707f +#define MATCH_PAUSE 0x100000f +#define MASK_PAUSE 0xffffffff +#define MATCH_PBSAD 0xfc000077 +#define MASK_PBSAD 0xfe00707f +#define MATCH_PBSADA 0xfe000077 +#define MASK_PBSADA 0xfe00707f +#define MATCH_PKBB16 0xe001077 +#define MASK_PKBB16 0xfe00707f +#define MATCH_PKBT16 0x1e001077 +#define MASK_PKBT16 0xfe00707f +#define MATCH_PKBT32 0x1e002077 +#define MASK_PKBT32 0xfe00707f +#define MATCH_PKTB16 0x3e001077 +#define MASK_PKTB16 0xfe00707f +#define MATCH_PKTB32 0x3e002077 +#define MASK_PKTB32 0xfe00707f +#define MATCH_PKTT16 0x2e001077 +#define MASK_PKTT16 0xfe00707f +#define MATCH_PREFETCH_I 0x6013 +#define MASK_PREFETCH_I 0x1f07fff +#define MATCH_PREFETCH_R 0x106013 +#define MASK_PREFETCH_R 0x1f07fff +#define MATCH_PREFETCH_W 0x306013 +#define MASK_PREFETCH_W 0x1f07fff +#define MATCH_RADD16 0x77 +#define MASK_RADD16 0xfe00707f +#define MATCH_RADD32 0x2077 +#define MASK_RADD32 0xfe00707f +#define MATCH_RADD64 0x80001077 +#define MASK_RADD64 0xfe00707f +#define MATCH_RADD8 0x8000077 +#define MASK_RADD8 0xfe00707f +#define MATCH_RADDW 0x20001077 +#define MASK_RADDW 0xfe00707f +#define MATCH_RCRAS16 0x4000077 +#define MASK_RCRAS16 0xfe00707f +#define MATCH_RCRAS32 0x4002077 +#define MASK_RCRAS32 0xfe00707f +#define MATCH_RCRSA16 0x6000077 +#define MASK_RCRSA16 0xfe00707f +#define MATCH_RCRSA32 0x6002077 +#define MASK_RCRSA32 0xfe00707f +#define MATCH_REM 0x2006033 +#define MASK_REM 0xfe00707f +#define MATCH_REMU 0x2007033 +#define MASK_REMU 0xfe00707f +#define MATCH_REMUW 0x200703b +#define MASK_REMUW 0xfe00707f +#define MATCH_REMW 0x200603b +#define MASK_REMW 0xfe00707f +#define MATCH_ROL 0x60001033 +#define MASK_ROL 0xfe00707f +#define MATCH_ROLW 0x6000103b +#define MASK_ROLW 0xfe00707f +#define MATCH_ROR 0x60005033 +#define MASK_ROR 0xfe00707f +#define MATCH_RORI 0x60005013 +#define MASK_RORI 0xfc00707f +#define MATCH_RORIW 0x6000501b +#define MASK_RORIW 0xfe00707f +#define MATCH_RORW 0x6000503b +#define MASK_RORW 0xfe00707f +#define MATCH_RSTAS16 0xb4002077 +#define MASK_RSTAS16 0xfe00707f +#define MATCH_RSTAS32 0xb0002077 +#define MASK_RSTAS32 0xfe00707f +#define MATCH_RSTSA16 0xb6002077 +#define MASK_RSTSA16 0xfe00707f +#define MATCH_RSTSA32 0xb2002077 +#define MASK_RSTSA32 0xfe00707f +#define MATCH_RSUB16 0x2000077 +#define MASK_RSUB16 0xfe00707f +#define MATCH_RSUB32 0x2002077 +#define MASK_RSUB32 0xfe00707f +#define MATCH_RSUB64 0x82001077 +#define MASK_RSUB64 0xfe00707f +#define MATCH_RSUB8 0xa000077 +#define MASK_RSUB8 0xfe00707f +#define MATCH_RSUBW 0x22001077 +#define MASK_RSUBW 0xfe00707f +#define MATCH_SB 0x23 +#define MASK_SB 0x707f +#define MATCH_SC_D 0x1800302f +#define MASK_SC_D 0xf800707f +#define MATCH_SC_W 0x1800202f +#define MASK_SC_W 0xf800707f +#define MATCH_SCLIP16 0x84000077 +#define MASK_SCLIP16 0xff00707f +#define MATCH_SCLIP32 0xe4000077 +#define MASK_SCLIP32 0xfe00707f +#define MATCH_SCLIP8 0x8c000077 +#define MASK_SCLIP8 0xff80707f +#define MATCH_SCMPLE16 0x1c000077 +#define MASK_SCMPLE16 0xfe00707f +#define MATCH_SCMPLE8 0x1e000077 +#define MASK_SCMPLE8 0xfe00707f +#define MATCH_SCMPLT16 0xc000077 +#define MASK_SCMPLT16 0xfe00707f +#define MATCH_SCMPLT8 0xe000077 +#define MASK_SCMPLT8 0xfe00707f +#define MATCH_SD 0x3023 +#define MASK_SD 0x707f +#define MATCH_SEXT_B 0x60401013 +#define MASK_SEXT_B 0xfff0707f +#define MATCH_SEXT_H 0x60501013 +#define MASK_SEXT_H 0xfff0707f +#define MATCH_SFENCE_INVAL_IR 0x18100073 +#define MASK_SFENCE_INVAL_IR 0xffffffff +#define MATCH_SFENCE_VMA 0x12000073 +#define MASK_SFENCE_VMA 0xfe007fff +#define MATCH_SFENCE_W_INVAL 0x18000073 +#define MASK_SFENCE_W_INVAL 0xffffffff +#define MATCH_SH 0x1023 +#define MASK_SH 0x707f +#define MATCH_SH1ADD 0x20002033 +#define MASK_SH1ADD 0xfe00707f +#define MATCH_SH1ADD_UW 0x2000203b +#define MASK_SH1ADD_UW 0xfe00707f +#define MATCH_SH2ADD 0x20004033 +#define MASK_SH2ADD 0xfe00707f +#define MATCH_SH2ADD_UW 0x2000403b +#define MASK_SH2ADD_UW 0xfe00707f +#define MATCH_SH3ADD 0x20006033 +#define MASK_SH3ADD 0xfe00707f +#define MATCH_SH3ADD_UW 0x2000603b +#define MASK_SH3ADD_UW 0xfe00707f +#define MATCH_SHA256SIG0 0x10201013 +#define MASK_SHA256SIG0 0xfff0707f +#define MATCH_SHA256SIG1 0x10301013 +#define MASK_SHA256SIG1 0xfff0707f +#define MATCH_SHA256SUM0 0x10001013 +#define MASK_SHA256SUM0 0xfff0707f +#define MATCH_SHA256SUM1 0x10101013 +#define MASK_SHA256SUM1 0xfff0707f +#define MATCH_SHA512SIG0 0x10601013 +#define MASK_SHA512SIG0 0xfff0707f +#define MATCH_SHA512SIG0H 0x5c000033 +#define MASK_SHA512SIG0H 0xfe00707f +#define MATCH_SHA512SIG0L 0x54000033 +#define MASK_SHA512SIG0L 0xfe00707f +#define MATCH_SHA512SIG1 0x10701013 +#define MASK_SHA512SIG1 0xfff0707f +#define MATCH_SHA512SIG1H 0x5e000033 +#define MASK_SHA512SIG1H 0xfe00707f +#define MATCH_SHA512SIG1L 0x56000033 +#define MASK_SHA512SIG1L 0xfe00707f +#define MATCH_SHA512SUM0 0x10401013 +#define MASK_SHA512SUM0 0xfff0707f +#define MATCH_SHA512SUM0R 0x50000033 +#define MASK_SHA512SUM0R 0xfe00707f +#define MATCH_SHA512SUM1 0x10501013 +#define MASK_SHA512SUM1 0xfff0707f +#define MATCH_SHA512SUM1R 0x52000033 +#define MASK_SHA512SUM1R 0xfe00707f +#define MATCH_SHFL 0x8001033 +#define MASK_SHFL 0xfe00707f +#define MATCH_SHFLI 0x8001013 +#define MASK_SHFLI 0xfe00707f +#define MATCH_SHFLW 0x800103b +#define MASK_SHFLW 0xfe00707f +#define MATCH_SINVAL_VMA 0x16000073 +#define MASK_SINVAL_VMA 0xfe007fff +#define MATCH_SLL 0x1033 +#define MASK_SLL 0xfe00707f +#define MATCH_SLL16 0x54000077 +#define MASK_SLL16 0xfe00707f +#define MATCH_SLL32 0x54002077 +#define MASK_SLL32 0xfe00707f +#define MATCH_SLL8 0x5c000077 +#define MASK_SLL8 0xfe00707f +#define MATCH_SLLD 0x107b +#define MASK_SLLD 0xfe00707f +#define MATCH_SLLI 0x1013 +#define MASK_SLLI 0xfc00707f +#define MATCH_SLLI16 0x74000077 +#define MASK_SLLI16 0xff00707f +#define MATCH_SLLI32 0x74002077 +#define MASK_SLLI32 0xfe00707f +#define MATCH_SLLI8 0x7c000077 +#define MASK_SLLI8 0xff80707f +#define MATCH_SLLI_RV128 0x1013 +#define MASK_SLLI_RV128 0xf800707f +#define MATCH_SLLI_RV32 0x1013 +#define MASK_SLLI_RV32 0xfe00707f +#define MATCH_SLLI_UW 0x800101b +#define MASK_SLLI_UW 0xfc00707f +#define MATCH_SLLID 0x105b +#define MASK_SLLID 0xfc00707f +#define MATCH_SLLIW 0x101b +#define MASK_SLLIW 0xfe00707f +#define MATCH_SLLW 0x103b +#define MASK_SLLW 0xfe00707f +#define MATCH_SLO 0x20001033 +#define MASK_SLO 0xfe00707f +#define MATCH_SLOI 0x20001013 +#define MASK_SLOI 0xfc00707f +#define MATCH_SLOIW 0x2000101b +#define MASK_SLOIW 0xfe00707f +#define MATCH_SLOW 0x2000103b +#define MASK_SLOW 0xfe00707f +#define MATCH_SLT 0x2033 +#define MASK_SLT 0xfe00707f +#define MATCH_SLTI 0x2013 +#define MASK_SLTI 0x707f +#define MATCH_SLTIU 0x3013 +#define MASK_SLTIU 0x707f +#define MATCH_SLTU 0x3033 +#define MASK_SLTU 0xfe00707f +#define MATCH_SM3P0 0x10801013 +#define MASK_SM3P0 0xfff0707f +#define MATCH_SM3P1 0x10901013 +#define MASK_SM3P1 0xfff0707f +#define MATCH_SM4ED 0x30000033 +#define MASK_SM4ED 0x3e00707f +#define MATCH_SM4KS 0x34000033 +#define MASK_SM4KS 0x3e00707f +#define MATCH_SMAL 0x5e001077 +#define MASK_SMAL 0xfe00707f +#define MATCH_SMALBB 0x88001077 +#define MASK_SMALBB 0xfe00707f +#define MATCH_SMALBT 0x98001077 +#define MASK_SMALBT 0xfe00707f +#define MATCH_SMALDA 0x8c001077 +#define MASK_SMALDA 0xfe00707f +#define MATCH_SMALDRS 0x9a001077 +#define MASK_SMALDRS 0xfe00707f +#define MATCH_SMALDS 0x8a001077 +#define MASK_SMALDS 0xfe00707f +#define MATCH_SMALTT 0xa8001077 +#define MASK_SMALTT 0xfe00707f +#define MATCH_SMALXDA 0x9c001077 +#define MASK_SMALXDA 0xfe00707f +#define MATCH_SMALXDS 0xaa001077 +#define MASK_SMALXDS 0xfe00707f +#define MATCH_SMAQA 0xc8000077 +#define MASK_SMAQA 0xfe00707f +#define MATCH_SMAQA_SU 0xca000077 +#define MASK_SMAQA_SU 0xfe00707f +#define MATCH_SMAR64 0x84001077 +#define MASK_SMAR64 0xfe00707f +#define MATCH_SMAX16 0x82000077 +#define MASK_SMAX16 0xfe00707f +#define MATCH_SMAX32 0x92002077 +#define MASK_SMAX32 0xfe00707f +#define MATCH_SMAX8 0x8a000077 +#define MASK_SMAX8 0xfe00707f +#define MATCH_SMBB16 0x8001077 +#define MASK_SMBB16 0xfe00707f +#define MATCH_SMBT16 0x18001077 +#define MASK_SMBT16 0xfe00707f +#define MATCH_SMBT32 0x18002077 +#define MASK_SMBT32 0xfe00707f +#define MATCH_SMDRS 0x68001077 +#define MASK_SMDRS 0xfe00707f +#define MATCH_SMDRS32 0x68002077 +#define MASK_SMDRS32 0xfe00707f +#define MATCH_SMDS 0x58001077 +#define MASK_SMDS 0xfe00707f +#define MATCH_SMDS32 0x58002077 +#define MASK_SMDS32 0xfe00707f +#define MATCH_SMIN16 0x80000077 +#define MASK_SMIN16 0xfe00707f +#define MATCH_SMIN32 0x90002077 +#define MASK_SMIN32 0xfe00707f +#define MATCH_SMIN8 0x88000077 +#define MASK_SMIN8 0xfe00707f +#define MATCH_SMMUL 0x40001077 +#define MASK_SMMUL 0xfe00707f +#define MATCH_SMMUL_U 0x50001077 +#define MASK_SMMUL_U 0xfe00707f +#define MATCH_SMMWB 0x44001077 +#define MASK_SMMWB 0xfe00707f +#define MATCH_SMMWB_U 0x54001077 +#define MASK_SMMWB_U 0xfe00707f +#define MATCH_SMMWT 0x64001077 +#define MASK_SMMWT 0xfe00707f +#define MATCH_SMMWT_U 0x74001077 +#define MASK_SMMWT_U 0xfe00707f +#define MATCH_SMSLDA 0xac001077 +#define MASK_SMSLDA 0xfe00707f +#define MATCH_SMSLXDA 0xbc001077 +#define MASK_SMSLXDA 0xfe00707f +#define MATCH_SMSR64 0x86001077 +#define MASK_SMSR64 0xfe00707f +#define MATCH_SMTT16 0x28001077 +#define MASK_SMTT16 0xfe00707f +#define MATCH_SMTT32 0x28002077 +#define MASK_SMTT32 0xfe00707f +#define MATCH_SMUL16 0xa0000077 +#define MASK_SMUL16 0xfe00707f +#define MATCH_SMUL8 0xa8000077 +#define MASK_SMUL8 0xfe00707f +#define MATCH_SMULX16 0xa2000077 +#define MASK_SMULX16 0xfe00707f +#define MATCH_SMULX8 0xaa000077 +#define MASK_SMULX8 0xfe00707f +#define MATCH_SMXDS 0x78001077 +#define MASK_SMXDS 0xfe00707f +#define MATCH_SMXDS32 0x78002077 +#define MASK_SMXDS32 0xfe00707f +#define MATCH_SQ 0x4023 +#define MASK_SQ 0x707f +#define MATCH_SRA 0x40005033 +#define MASK_SRA 0xfe00707f +#define MATCH_SRA16 0x50000077 +#define MASK_SRA16 0xfe00707f +#define MATCH_SRA16_U 0x60000077 +#define MASK_SRA16_U 0xfe00707f +#define MATCH_SRA32 0x50002077 +#define MASK_SRA32 0xfe00707f +#define MATCH_SRA32_U 0x60002077 +#define MASK_SRA32_U 0xfe00707f +#define MATCH_SRA8 0x58000077 +#define MASK_SRA8 0xfe00707f +#define MATCH_SRA8_U 0x68000077 +#define MASK_SRA8_U 0xfe00707f +#define MATCH_SRA_U 0x24001077 +#define MASK_SRA_U 0xfe00707f +#define MATCH_SRAD 0x4000507b +#define MASK_SRAD 0xfe00707f +#define MATCH_SRAI 0x40005013 +#define MASK_SRAI 0xfc00707f +#define MATCH_SRAI16 0x70000077 +#define MASK_SRAI16 0xff00707f +#define MATCH_SRAI16_U 0x71000077 +#define MASK_SRAI16_U 0xff00707f +#define MATCH_SRAI32 0x70002077 +#define MASK_SRAI32 0xfe00707f +#define MATCH_SRAI32_U 0x80002077 +#define MASK_SRAI32_U 0xfe00707f +#define MATCH_SRAI8 0x78000077 +#define MASK_SRAI8 0xff80707f +#define MATCH_SRAI8_U 0x78800077 +#define MASK_SRAI8_U 0xff80707f +#define MATCH_SRAI_RV128 0x40005013 +#define MASK_SRAI_RV128 0xf800707f +#define MATCH_SRAI_RV32 0x40005013 +#define MASK_SRAI_RV32 0xfe00707f +#define MATCH_SRAI_U 0xd4001077 +#define MASK_SRAI_U 0xfc00707f +#define MATCH_SRAID 0x4000505b +#define MASK_SRAID 0xfc00707f +#define MATCH_SRAIW 0x4000501b +#define MASK_SRAIW 0xfe00707f +#define MATCH_SRAIW_U 0x34001077 +#define MASK_SRAIW_U 0xfe00707f +#define MATCH_SRAW 0x4000503b +#define MASK_SRAW 0xfe00707f +#define MATCH_SRET 0x10200073 +#define MASK_SRET 0xffffffff +#define MATCH_SRL 0x5033 +#define MASK_SRL 0xfe00707f +#define MATCH_SRL16 0x52000077 +#define MASK_SRL16 0xfe00707f +#define MATCH_SRL16_U 0x62000077 +#define MASK_SRL16_U 0xfe00707f +#define MATCH_SRL32 0x52002077 +#define MASK_SRL32 0xfe00707f +#define MATCH_SRL32_U 0x62002077 +#define MASK_SRL32_U 0xfe00707f +#define MATCH_SRL8 0x5a000077 +#define MASK_SRL8 0xfe00707f +#define MATCH_SRL8_U 0x6a000077 +#define MASK_SRL8_U 0xfe00707f +#define MATCH_SRLD 0x507b +#define MASK_SRLD 0xfe00707f +#define MATCH_SRLI 0x5013 +#define MASK_SRLI 0xfc00707f +#define MATCH_SRLI16 0x72000077 +#define MASK_SRLI16 0xff00707f +#define MATCH_SRLI16_U 0x73000077 +#define MASK_SRLI16_U 0xff00707f +#define MATCH_SRLI32 0x72002077 +#define MASK_SRLI32 0xfe00707f +#define MATCH_SRLI32_U 0x82002077 +#define MASK_SRLI32_U 0xfe00707f +#define MATCH_SRLI8 0x7a000077 +#define MASK_SRLI8 0xff80707f +#define MATCH_SRLI8_U 0x7a800077 +#define MASK_SRLI8_U 0xff80707f +#define MATCH_SRLI_RV128 0x5013 +#define MASK_SRLI_RV128 0xf800707f +#define MATCH_SRLI_RV32 0x5013 +#define MASK_SRLI_RV32 0xfe00707f +#define MATCH_SRLID 0x505b +#define MASK_SRLID 0xfc00707f +#define MATCH_SRLIW 0x501b +#define MASK_SRLIW 0xfe00707f +#define MATCH_SRLW 0x503b +#define MASK_SRLW 0xfe00707f +#define MATCH_SRO 0x20005033 +#define MASK_SRO 0xfe00707f +#define MATCH_SROI 0x20005013 +#define MASK_SROI 0xfc00707f +#define MATCH_SROIW 0x2000501b +#define MASK_SROIW 0xfe00707f +#define MATCH_SROW 0x2000503b +#define MASK_SROW 0xfe00707f +#define MATCH_STAS16 0xf4002077 +#define MASK_STAS16 0xfe00707f +#define MATCH_STAS32 0xf0002077 +#define MASK_STAS32 0xfe00707f +#define MATCH_STSA16 0xf6002077 +#define MASK_STSA16 0xfe00707f +#define MATCH_STSA32 0xf2002077 +#define MASK_STSA32 0xfe00707f +#define MATCH_SUB 0x40000033 +#define MASK_SUB 0xfe00707f +#define MATCH_SUB16 0x42000077 +#define MASK_SUB16 0xfe00707f +#define MATCH_SUB32 0x42002077 +#define MASK_SUB32 0xfe00707f +#define MATCH_SUB64 0xc2001077 +#define MASK_SUB64 0xfe00707f +#define MATCH_SUB8 0x4a000077 +#define MASK_SUB8 0xfe00707f +#define MATCH_SUBD 0x4000007b +#define MASK_SUBD 0xfe00707f +#define MATCH_SUBW 0x4000003b +#define MASK_SUBW 0xfe00707f +#define MATCH_SUNPKD810 0xac800077 +#define MASK_SUNPKD810 0xfff0707f +#define MATCH_SUNPKD820 0xac900077 +#define MASK_SUNPKD820 0xfff0707f +#define MATCH_SUNPKD830 0xaca00077 +#define MASK_SUNPKD830 0xfff0707f +#define MATCH_SUNPKD831 0xacb00077 +#define MASK_SUNPKD831 0xfff0707f +#define MATCH_SUNPKD832 0xad300077 +#define MASK_SUNPKD832 0xfff0707f +#define MATCH_SW 0x2023 +#define MASK_SW 0x707f +#define MATCH_UCLIP16 0x85000077 +#define MASK_UCLIP16 0xff00707f +#define MATCH_UCLIP32 0xf4000077 +#define MASK_UCLIP32 0xfe00707f +#define MATCH_UCLIP8 0x8d000077 +#define MASK_UCLIP8 0xff80707f +#define MATCH_UCMPLE16 0x3c000077 +#define MASK_UCMPLE16 0xfe00707f +#define MATCH_UCMPLE8 0x3e000077 +#define MASK_UCMPLE8 0xfe00707f +#define MATCH_UCMPLT16 0x2c000077 +#define MASK_UCMPLT16 0xfe00707f +#define MATCH_UCMPLT8 0x2e000077 +#define MASK_UCMPLT8 0xfe00707f +#define MATCH_UKADD16 0x30000077 +#define MASK_UKADD16 0xfe00707f +#define MATCH_UKADD32 0x30002077 +#define MASK_UKADD32 0xfe00707f +#define MATCH_UKADD64 0xb0001077 +#define MASK_UKADD64 0xfe00707f +#define MATCH_UKADD8 0x38000077 +#define MASK_UKADD8 0xfe00707f +#define MATCH_UKADDH 0x14001077 +#define MASK_UKADDH 0xfe00707f +#define MATCH_UKADDW 0x10001077 +#define MASK_UKADDW 0xfe00707f +#define MATCH_UKCRAS16 0x34000077 +#define MASK_UKCRAS16 0xfe00707f +#define MATCH_UKCRAS32 0x34002077 +#define MASK_UKCRAS32 0xfe00707f +#define MATCH_UKCRSA16 0x36000077 +#define MASK_UKCRSA16 0xfe00707f +#define MATCH_UKCRSA32 0x36002077 +#define MASK_UKCRSA32 0xfe00707f +#define MATCH_UKMAR64 0xb4001077 +#define MASK_UKMAR64 0xfe00707f +#define MATCH_UKMSR64 0xb6001077 +#define MASK_UKMSR64 0xfe00707f +#define MATCH_UKSTAS16 0xe4002077 +#define MASK_UKSTAS16 0xfe00707f +#define MATCH_UKSTAS32 0xe0002077 +#define MASK_UKSTAS32 0xfe00707f +#define MATCH_UKSTSA16 0xe6002077 +#define MASK_UKSTSA16 0xfe00707f +#define MATCH_UKSTSA32 0xe2002077 +#define MASK_UKSTSA32 0xfe00707f +#define MATCH_UKSUB16 0x32000077 +#define MASK_UKSUB16 0xfe00707f +#define MATCH_UKSUB32 0x32002077 +#define MASK_UKSUB32 0xfe00707f +#define MATCH_UKSUB64 0xb2001077 +#define MASK_UKSUB64 0xfe00707f +#define MATCH_UKSUB8 0x3a000077 +#define MASK_UKSUB8 0xfe00707f +#define MATCH_UKSUBH 0x16001077 +#define MASK_UKSUBH 0xfe00707f +#define MATCH_UKSUBW 0x12001077 +#define MASK_UKSUBW 0xfe00707f +#define MATCH_UMAQA 0xcc000077 +#define MASK_UMAQA 0xfe00707f +#define MATCH_UMAR64 0xa4001077 +#define MASK_UMAR64 0xfe00707f +#define MATCH_UMAX16 0x92000077 +#define MASK_UMAX16 0xfe00707f +#define MATCH_UMAX32 0xa2002077 +#define MASK_UMAX32 0xfe00707f +#define MATCH_UMAX8 0x9a000077 +#define MASK_UMAX8 0xfe00707f +#define MATCH_UMIN16 0x90000077 +#define MASK_UMIN16 0xfe00707f +#define MATCH_UMIN32 0xa0002077 +#define MASK_UMIN32 0xfe00707f +#define MATCH_UMIN8 0x98000077 +#define MASK_UMIN8 0xfe00707f +#define MATCH_UMSR64 0xa6001077 +#define MASK_UMSR64 0xfe00707f +#define MATCH_UMUL16 0xb0000077 +#define MASK_UMUL16 0xfe00707f +#define MATCH_UMUL8 0xb8000077 +#define MASK_UMUL8 0xfe00707f +#define MATCH_UMULX16 0xb2000077 +#define MASK_UMULX16 0xfe00707f +#define MATCH_UMULX8 0xba000077 +#define MASK_UMULX8 0xfe00707f +#define MATCH_UNSHFL 0x8005033 +#define MASK_UNSHFL 0xfe00707f +#define MATCH_UNSHFLI 0x8005013 +#define MASK_UNSHFLI 0xfe00707f +#define MATCH_UNSHFLW 0x800503b +#define MASK_UNSHFLW 0xfe00707f +#define MATCH_URADD16 0x20000077 +#define MASK_URADD16 0xfe00707f +#define MATCH_URADD32 0x20002077 +#define MASK_URADD32 0xfe00707f +#define MATCH_URADD64 0xa0001077 +#define MASK_URADD64 0xfe00707f +#define MATCH_URADD8 0x28000077 +#define MASK_URADD8 0xfe00707f +#define MATCH_URADDW 0x30001077 +#define MASK_URADDW 0xfe00707f +#define MATCH_URCRAS16 0x24000077 +#define MASK_URCRAS16 0xfe00707f +#define MATCH_URCRAS32 0x24002077 +#define MASK_URCRAS32 0xfe00707f +#define MATCH_URCRSA16 0x26000077 +#define MASK_URCRSA16 0xfe00707f +#define MATCH_URCRSA32 0x26002077 +#define MASK_URCRSA32 0xfe00707f +#define MATCH_URSTAS16 0xd4002077 +#define MASK_URSTAS16 0xfe00707f +#define MATCH_URSTAS32 0xd0002077 +#define MASK_URSTAS32 0xfe00707f +#define MATCH_URSTSA16 0xd6002077 +#define MASK_URSTSA16 0xfe00707f +#define MATCH_URSTSA32 0xd2002077 +#define MASK_URSTSA32 0xfe00707f +#define MATCH_URSUB16 0x22000077 +#define MASK_URSUB16 0xfe00707f +#define MATCH_URSUB32 0x22002077 +#define MASK_URSUB32 0xfe00707f +#define MATCH_URSUB64 0xa2001077 +#define MASK_URSUB64 0xfe00707f +#define MATCH_URSUB8 0x2a000077 +#define MASK_URSUB8 0xfe00707f +#define MATCH_URSUBW 0x32001077 +#define MASK_URSUBW 0xfe00707f +#define MATCH_VAADD_VV 0x24002057 +#define MASK_VAADD_VV 0xfc00707f +#define MATCH_VAADD_VX 0x24006057 +#define MASK_VAADD_VX 0xfc00707f +#define MATCH_VAADDU_VV 0x20002057 +#define MASK_VAADDU_VV 0xfc00707f +#define MATCH_VAADDU_VX 0x20006057 +#define MASK_VAADDU_VX 0xfc00707f +#define MATCH_VADC_VIM 0x40003057 +#define MASK_VADC_VIM 0xfe00707f +#define MATCH_VADC_VVM 0x40000057 +#define MASK_VADC_VVM 0xfe00707f +#define MATCH_VADC_VXM 0x40004057 +#define MASK_VADC_VXM 0xfe00707f +#define MATCH_VADD_VI 0x3057 +#define MASK_VADD_VI 0xfc00707f +#define MATCH_VADD_VV 0x57 +#define MASK_VADD_VV 0xfc00707f +#define MATCH_VADD_VX 0x4057 +#define MASK_VADD_VX 0xfc00707f +#define MATCH_VAMOADDEI16_V 0x502f +#define MASK_VAMOADDEI16_V 0xf800707f +#define MATCH_VAMOADDEI32_V 0x602f +#define MASK_VAMOADDEI32_V 0xf800707f +#define MATCH_VAMOADDEI64_V 0x702f +#define MASK_VAMOADDEI64_V 0xf800707f +#define MATCH_VAMOADDEI8_V 0x2f +#define MASK_VAMOADDEI8_V 0xf800707f +#define MATCH_VAMOANDEI16_V 0x6000502f +#define MASK_VAMOANDEI16_V 0xf800707f +#define MATCH_VAMOANDEI32_V 0x6000602f +#define MASK_VAMOANDEI32_V 0xf800707f +#define MATCH_VAMOANDEI64_V 0x6000702f +#define MASK_VAMOANDEI64_V 0xf800707f +#define MATCH_VAMOANDEI8_V 0x6000002f +#define MASK_VAMOANDEI8_V 0xf800707f +#define MATCH_VAMOMAXEI16_V 0xa000502f +#define MASK_VAMOMAXEI16_V 0xf800707f +#define MATCH_VAMOMAXEI32_V 0xa000602f +#define MASK_VAMOMAXEI32_V 0xf800707f +#define MATCH_VAMOMAXEI64_V 0xa000702f +#define MASK_VAMOMAXEI64_V 0xf800707f +#define MATCH_VAMOMAXEI8_V 0xa000002f +#define MASK_VAMOMAXEI8_V 0xf800707f +#define MATCH_VAMOMAXUEI16_V 0xe000502f +#define MASK_VAMOMAXUEI16_V 0xf800707f +#define MATCH_VAMOMAXUEI32_V 0xe000602f +#define MASK_VAMOMAXUEI32_V 0xf800707f +#define MATCH_VAMOMAXUEI64_V 0xe000702f +#define MASK_VAMOMAXUEI64_V 0xf800707f +#define MATCH_VAMOMAXUEI8_V 0xe000002f +#define MASK_VAMOMAXUEI8_V 0xf800707f +#define MATCH_VAMOMINEI16_V 0x8000502f +#define MASK_VAMOMINEI16_V 0xf800707f +#define MATCH_VAMOMINEI32_V 0x8000602f +#define MASK_VAMOMINEI32_V 0xf800707f +#define MATCH_VAMOMINEI64_V 0x8000702f +#define MASK_VAMOMINEI64_V 0xf800707f +#define MATCH_VAMOMINEI8_V 0x8000002f +#define MASK_VAMOMINEI8_V 0xf800707f +#define MATCH_VAMOMINUEI16_V 0xc000502f +#define MASK_VAMOMINUEI16_V 0xf800707f +#define MATCH_VAMOMINUEI32_V 0xc000602f +#define MASK_VAMOMINUEI32_V 0xf800707f +#define MATCH_VAMOMINUEI64_V 0xc000702f +#define MASK_VAMOMINUEI64_V 0xf800707f +#define MATCH_VAMOMINUEI8_V 0xc000002f +#define MASK_VAMOMINUEI8_V 0xf800707f +#define MATCH_VAMOOREI16_V 0x4000502f +#define MASK_VAMOOREI16_V 0xf800707f +#define MATCH_VAMOOREI32_V 0x4000602f +#define MASK_VAMOOREI32_V 0xf800707f +#define MATCH_VAMOOREI64_V 0x4000702f +#define MASK_VAMOOREI64_V 0xf800707f +#define MATCH_VAMOOREI8_V 0x4000002f +#define MASK_VAMOOREI8_V 0xf800707f +#define MATCH_VAMOSWAPEI16_V 0x800502f +#define MASK_VAMOSWAPEI16_V 0xf800707f +#define MATCH_VAMOSWAPEI32_V 0x800602f +#define MASK_VAMOSWAPEI32_V 0xf800707f +#define MATCH_VAMOSWAPEI64_V 0x800702f +#define MASK_VAMOSWAPEI64_V 0xf800707f +#define MATCH_VAMOSWAPEI8_V 0x800002f +#define MASK_VAMOSWAPEI8_V 0xf800707f +#define MATCH_VAMOXOREI16_V 0x2000502f +#define MASK_VAMOXOREI16_V 0xf800707f +#define MATCH_VAMOXOREI32_V 0x2000602f +#define MASK_VAMOXOREI32_V 0xf800707f +#define MATCH_VAMOXOREI64_V 0x2000702f +#define MASK_VAMOXOREI64_V 0xf800707f +#define MATCH_VAMOXOREI8_V 0x2000002f +#define MASK_VAMOXOREI8_V 0xf800707f +#define MATCH_VAND_VI 0x24003057 +#define MASK_VAND_VI 0xfc00707f +#define MATCH_VAND_VV 0x24000057 +#define MASK_VAND_VV 0xfc00707f +#define MATCH_VAND_VX 0x24004057 +#define MASK_VAND_VX 0xfc00707f +#define MATCH_VASUB_VV 0x2c002057 +#define MASK_VASUB_VV 0xfc00707f +#define MATCH_VASUB_VX 0x2c006057 +#define MASK_VASUB_VX 0xfc00707f +#define MATCH_VASUBU_VV 0x28002057 +#define MASK_VASUBU_VV 0xfc00707f +#define MATCH_VASUBU_VX 0x28006057 +#define MASK_VASUBU_VX 0xfc00707f +#define MATCH_VCOMPRESS_VM 0x5e002057 +#define MASK_VCOMPRESS_VM 0xfe00707f +#define MATCH_VCPOP_M 0x40082057 +#define MASK_VCPOP_M 0xfc0ff07f +#define MATCH_VDIV_VV 0x84002057 +#define MASK_VDIV_VV 0xfc00707f +#define MATCH_VDIV_VX 0x84006057 +#define MASK_VDIV_VX 0xfc00707f +#define MATCH_VDIVU_VV 0x80002057 +#define MASK_VDIVU_VV 0xfc00707f +#define MATCH_VDIVU_VX 0x80006057 +#define MASK_VDIVU_VX 0xfc00707f +#define MATCH_VFADD_VF 0x5057 +#define MASK_VFADD_VF 0xfc00707f +#define MATCH_VFADD_VV 0x1057 +#define MASK_VFADD_VV 0xfc00707f +#define MATCH_VFCLASS_V 0x4c081057 +#define MASK_VFCLASS_V 0xfc0ff07f +#define MATCH_VFCVT_F_X_V 0x48019057 +#define MASK_VFCVT_F_X_V 0xfc0ff07f +#define MATCH_VFCVT_F_XU_V 0x48011057 +#define MASK_VFCVT_F_XU_V 0xfc0ff07f +#define MATCH_VFCVT_RTZ_X_F_V 0x48039057 +#define MASK_VFCVT_RTZ_X_F_V 0xfc0ff07f +#define MATCH_VFCVT_RTZ_XU_F_V 0x48031057 +#define MASK_VFCVT_RTZ_XU_F_V 0xfc0ff07f +#define MATCH_VFCVT_X_F_V 0x48009057 +#define MASK_VFCVT_X_F_V 0xfc0ff07f +#define MATCH_VFCVT_XU_F_V 0x48001057 +#define MASK_VFCVT_XU_F_V 0xfc0ff07f +#define MATCH_VFDIV_VF 0x80005057 +#define MASK_VFDIV_VF 0xfc00707f +#define MATCH_VFDIV_VV 0x80001057 +#define MASK_VFDIV_VV 0xfc00707f +#define MATCH_VFIRST_M 0x4008a057 +#define MASK_VFIRST_M 0xfc0ff07f +#define MATCH_VFMACC_VF 0xb0005057 +#define MASK_VFMACC_VF 0xfc00707f +#define MATCH_VFMACC_VV 0xb0001057 +#define MASK_VFMACC_VV 0xfc00707f +#define MATCH_VFMADD_VF 0xa0005057 +#define MASK_VFMADD_VF 0xfc00707f +#define MATCH_VFMADD_VV 0xa0001057 +#define MASK_VFMADD_VV 0xfc00707f +#define MATCH_VFMAX_VF 0x18005057 +#define MASK_VFMAX_VF 0xfc00707f +#define MATCH_VFMAX_VV 0x18001057 +#define MASK_VFMAX_VV 0xfc00707f +#define MATCH_VFMERGE_VFM 0x5c005057 +#define MASK_VFMERGE_VFM 0xfe00707f +#define MATCH_VFMIN_VF 0x10005057 +#define MASK_VFMIN_VF 0xfc00707f +#define MATCH_VFMIN_VV 0x10001057 +#define MASK_VFMIN_VV 0xfc00707f +#define MATCH_VFMSAC_VF 0xb8005057 +#define MASK_VFMSAC_VF 0xfc00707f +#define MATCH_VFMSAC_VV 0xb8001057 +#define MASK_VFMSAC_VV 0xfc00707f +#define MATCH_VFMSUB_VF 0xa8005057 +#define MASK_VFMSUB_VF 0xfc00707f +#define MATCH_VFMSUB_VV 0xa8001057 +#define MASK_VFMSUB_VV 0xfc00707f +#define MATCH_VFMUL_VF 0x90005057 +#define MASK_VFMUL_VF 0xfc00707f +#define MATCH_VFMUL_VV 0x90001057 +#define MASK_VFMUL_VV 0xfc00707f +#define MATCH_VFMV_F_S 0x42001057 +#define MASK_VFMV_F_S 0xfe0ff07f +#define MATCH_VFMV_S_F 0x42005057 +#define MASK_VFMV_S_F 0xfff0707f +#define MATCH_VFMV_V_F 0x5e005057 +#define MASK_VFMV_V_F 0xfff0707f +#define MATCH_VFNCVT_F_F_W 0x480a1057 +#define MASK_VFNCVT_F_F_W 0xfc0ff07f +#define MATCH_VFNCVT_F_X_W 0x48099057 +#define MASK_VFNCVT_F_X_W 0xfc0ff07f +#define MATCH_VFNCVT_F_XU_W 0x48091057 +#define MASK_VFNCVT_F_XU_W 0xfc0ff07f +#define MATCH_VFNCVT_ROD_F_F_W 0x480a9057 +#define MASK_VFNCVT_ROD_F_F_W 0xfc0ff07f +#define MATCH_VFNCVT_RTZ_X_F_W 0x480b9057 +#define MASK_VFNCVT_RTZ_X_F_W 0xfc0ff07f +#define MATCH_VFNCVT_RTZ_XU_F_W 0x480b1057 +#define MASK_VFNCVT_RTZ_XU_F_W 0xfc0ff07f +#define MATCH_VFNCVT_X_F_W 0x48089057 +#define MASK_VFNCVT_X_F_W 0xfc0ff07f +#define MATCH_VFNCVT_XU_F_W 0x48081057 +#define MASK_VFNCVT_XU_F_W 0xfc0ff07f +#define MATCH_VFNMACC_VF 0xb4005057 +#define MASK_VFNMACC_VF 0xfc00707f +#define MATCH_VFNMACC_VV 0xb4001057 +#define MASK_VFNMACC_VV 0xfc00707f +#define MATCH_VFNMADD_VF 0xa4005057 +#define MASK_VFNMADD_VF 0xfc00707f +#define MATCH_VFNMADD_VV 0xa4001057 +#define MASK_VFNMADD_VV 0xfc00707f +#define MATCH_VFNMSAC_VF 0xbc005057 +#define MASK_VFNMSAC_VF 0xfc00707f +#define MATCH_VFNMSAC_VV 0xbc001057 +#define MASK_VFNMSAC_VV 0xfc00707f +#define MATCH_VFNMSUB_VF 0xac005057 +#define MASK_VFNMSUB_VF 0xfc00707f +#define MATCH_VFNMSUB_VV 0xac001057 +#define MASK_VFNMSUB_VV 0xfc00707f +#define MATCH_VFRDIV_VF 0x84005057 +#define MASK_VFRDIV_VF 0xfc00707f +#define MATCH_VFREC7_V 0x4c029057 +#define MASK_VFREC7_V 0xfc0ff07f +#define MATCH_VFREDMAX_VS 0x1c001057 +#define MASK_VFREDMAX_VS 0xfc00707f +#define MATCH_VFREDMIN_VS 0x14001057 +#define MASK_VFREDMIN_VS 0xfc00707f +#define MATCH_VFREDOSUM_VS 0xc001057 +#define MASK_VFREDOSUM_VS 0xfc00707f +#define MATCH_VFREDUSUM_VS 0x4001057 +#define MASK_VFREDUSUM_VS 0xfc00707f +#define MATCH_VFRSQRT7_V 0x4c021057 +#define MASK_VFRSQRT7_V 0xfc0ff07f +#define MATCH_VFRSUB_VF 0x9c005057 +#define MASK_VFRSUB_VF 0xfc00707f +#define MATCH_VFSGNJ_VF 0x20005057 +#define MASK_VFSGNJ_VF 0xfc00707f +#define MATCH_VFSGNJ_VV 0x20001057 +#define MASK_VFSGNJ_VV 0xfc00707f +#define MATCH_VFSGNJN_VF 0x24005057 +#define MASK_VFSGNJN_VF 0xfc00707f +#define MATCH_VFSGNJN_VV 0x24001057 +#define MASK_VFSGNJN_VV 0xfc00707f +#define MATCH_VFSGNJX_VF 0x28005057 +#define MASK_VFSGNJX_VF 0xfc00707f +#define MATCH_VFSGNJX_VV 0x28001057 +#define MASK_VFSGNJX_VV 0xfc00707f +#define MATCH_VFSLIDE1DOWN_VF 0x3c005057 +#define MASK_VFSLIDE1DOWN_VF 0xfc00707f +#define MATCH_VFSLIDE1UP_VF 0x38005057 +#define MASK_VFSLIDE1UP_VF 0xfc00707f +#define MATCH_VFSQRT_V 0x4c001057 +#define MASK_VFSQRT_V 0xfc0ff07f +#define MATCH_VFSUB_VF 0x8005057 +#define MASK_VFSUB_VF 0xfc00707f +#define MATCH_VFSUB_VV 0x8001057 +#define MASK_VFSUB_VV 0xfc00707f +#define MATCH_VFWADD_VF 0xc0005057 +#define MASK_VFWADD_VF 0xfc00707f +#define MATCH_VFWADD_VV 0xc0001057 +#define MASK_VFWADD_VV 0xfc00707f +#define MATCH_VFWADD_WF 0xd0005057 +#define MASK_VFWADD_WF 0xfc00707f +#define MATCH_VFWADD_WV 0xd0001057 +#define MASK_VFWADD_WV 0xfc00707f +#define MATCH_VFWCVT_F_F_V 0x48061057 +#define MASK_VFWCVT_F_F_V 0xfc0ff07f +#define MATCH_VFWCVT_F_X_V 0x48059057 +#define MASK_VFWCVT_F_X_V 0xfc0ff07f +#define MATCH_VFWCVT_F_XU_V 0x48051057 +#define MASK_VFWCVT_F_XU_V 0xfc0ff07f +#define MATCH_VFWCVT_RTZ_X_F_V 0x48079057 +#define MASK_VFWCVT_RTZ_X_F_V 0xfc0ff07f +#define MATCH_VFWCVT_RTZ_XU_F_V 0x48071057 +#define MASK_VFWCVT_RTZ_XU_F_V 0xfc0ff07f +#define MATCH_VFWCVT_X_F_V 0x48049057 +#define MASK_VFWCVT_X_F_V 0xfc0ff07f +#define MATCH_VFWCVT_XU_F_V 0x48041057 +#define MASK_VFWCVT_XU_F_V 0xfc0ff07f +#define MATCH_VFWMACC_VF 0xf0005057 +#define MASK_VFWMACC_VF 0xfc00707f +#define MATCH_VFWMACC_VV 0xf0001057 +#define MASK_VFWMACC_VV 0xfc00707f +#define MATCH_VFWMSAC_VF 0xf8005057 +#define MASK_VFWMSAC_VF 0xfc00707f +#define MATCH_VFWMSAC_VV 0xf8001057 +#define MASK_VFWMSAC_VV 0xfc00707f +#define MATCH_VFWMUL_VF 0xe0005057 +#define MASK_VFWMUL_VF 0xfc00707f +#define MATCH_VFWMUL_VV 0xe0001057 +#define MASK_VFWMUL_VV 0xfc00707f +#define MATCH_VFWNMACC_VF 0xf4005057 +#define MASK_VFWNMACC_VF 0xfc00707f +#define MATCH_VFWNMACC_VV 0xf4001057 +#define MASK_VFWNMACC_VV 0xfc00707f +#define MATCH_VFWNMSAC_VF 0xfc005057 +#define MASK_VFWNMSAC_VF 0xfc00707f +#define MATCH_VFWNMSAC_VV 0xfc001057 +#define MASK_VFWNMSAC_VV 0xfc00707f +#define MATCH_VFWREDOSUM_VS 0xcc001057 +#define MASK_VFWREDOSUM_VS 0xfc00707f +#define MATCH_VFWREDUSUM_VS 0xc4001057 +#define MASK_VFWREDUSUM_VS 0xfc00707f +#define MATCH_VFWSUB_VF 0xc8005057 +#define MASK_VFWSUB_VF 0xfc00707f +#define MATCH_VFWSUB_VV 0xc8001057 +#define MASK_VFWSUB_VV 0xfc00707f +#define MATCH_VFWSUB_WF 0xd8005057 +#define MASK_VFWSUB_WF 0xfc00707f +#define MATCH_VFWSUB_WV 0xd8001057 +#define MASK_VFWSUB_WV 0xfc00707f +#define MATCH_VID_V 0x5008a057 +#define MASK_VID_V 0xfdfff07f +#define MATCH_VIOTA_M 0x50082057 +#define MASK_VIOTA_M 0xfc0ff07f +#define MATCH_VL1RE16_V 0x2805007 +#define MASK_VL1RE16_V 0xfff0707f +#define MATCH_VL1RE32_V 0x2806007 +#define MASK_VL1RE32_V 0xfff0707f +#define MATCH_VL1RE64_V 0x2807007 +#define MASK_VL1RE64_V 0xfff0707f +#define MATCH_VL1RE8_V 0x2800007 +#define MASK_VL1RE8_V 0xfff0707f +#define MATCH_VL2RE16_V 0x22805007 +#define MASK_VL2RE16_V 0xfff0707f +#define MATCH_VL2RE32_V 0x22806007 +#define MASK_VL2RE32_V 0xfff0707f +#define MATCH_VL2RE64_V 0x22807007 +#define MASK_VL2RE64_V 0xfff0707f +#define MATCH_VL2RE8_V 0x22800007 +#define MASK_VL2RE8_V 0xfff0707f +#define MATCH_VL4RE16_V 0x62805007 +#define MASK_VL4RE16_V 0xfff0707f +#define MATCH_VL4RE32_V 0x62806007 +#define MASK_VL4RE32_V 0xfff0707f +#define MATCH_VL4RE64_V 0x62807007 +#define MASK_VL4RE64_V 0xfff0707f +#define MATCH_VL4RE8_V 0x62800007 +#define MASK_VL4RE8_V 0xfff0707f +#define MATCH_VL8RE16_V 0xe2805007 +#define MASK_VL8RE16_V 0xfff0707f +#define MATCH_VL8RE32_V 0xe2806007 +#define MASK_VL8RE32_V 0xfff0707f +#define MATCH_VL8RE64_V 0xe2807007 +#define MASK_VL8RE64_V 0xfff0707f +#define MATCH_VL8RE8_V 0xe2800007 +#define MASK_VL8RE8_V 0xfff0707f +#define MATCH_VLE1024_V 0x10007007 +#define MASK_VLE1024_V 0x1df0707f +#define MATCH_VLE1024FF_V 0x11007007 +#define MASK_VLE1024FF_V 0x1df0707f +#define MATCH_VLE128_V 0x10000007 +#define MASK_VLE128_V 0x1df0707f +#define MATCH_VLE128FF_V 0x11000007 +#define MASK_VLE128FF_V 0x1df0707f +#define MATCH_VLE16_V 0x5007 +#define MASK_VLE16_V 0x1df0707f +#define MATCH_VLE16FF_V 0x1005007 +#define MASK_VLE16FF_V 0x1df0707f +#define MATCH_VLE256_V 0x10005007 +#define MASK_VLE256_V 0x1df0707f +#define MATCH_VLE256FF_V 0x11005007 +#define MASK_VLE256FF_V 0x1df0707f +#define MATCH_VLE32_V 0x6007 +#define MASK_VLE32_V 0x1df0707f +#define MATCH_VLE32FF_V 0x1006007 +#define MASK_VLE32FF_V 0x1df0707f +#define MATCH_VLE512_V 0x10006007 +#define MASK_VLE512_V 0x1df0707f +#define MATCH_VLE512FF_V 0x11006007 +#define MASK_VLE512FF_V 0x1df0707f +#define MATCH_VLE64_V 0x7007 +#define MASK_VLE64_V 0x1df0707f +#define MATCH_VLE64FF_V 0x1007007 +#define MASK_VLE64FF_V 0x1df0707f +#define MATCH_VLE8_V 0x7 +#define MASK_VLE8_V 0x1df0707f +#define MATCH_VLE8FF_V 0x1000007 +#define MASK_VLE8FF_V 0x1df0707f +#define MATCH_VLM_V 0x2b00007 +#define MASK_VLM_V 0xfff0707f +#define MATCH_VLOXEI1024_V 0x1c007007 +#define MASK_VLOXEI1024_V 0x1c00707f +#define MATCH_VLOXEI128_V 0x1c000007 +#define MASK_VLOXEI128_V 0x1c00707f +#define MATCH_VLOXEI16_V 0xc005007 +#define MASK_VLOXEI16_V 0x1c00707f +#define MATCH_VLOXEI256_V 0x1c005007 +#define MASK_VLOXEI256_V 0x1c00707f +#define MATCH_VLOXEI32_V 0xc006007 +#define MASK_VLOXEI32_V 0x1c00707f +#define MATCH_VLOXEI512_V 0x1c006007 +#define MASK_VLOXEI512_V 0x1c00707f +#define MATCH_VLOXEI64_V 0xc007007 +#define MASK_VLOXEI64_V 0x1c00707f +#define MATCH_VLOXEI8_V 0xc000007 +#define MASK_VLOXEI8_V 0x1c00707f +#define MATCH_VLSE1024_V 0x18007007 +#define MASK_VLSE1024_V 0x1c00707f +#define MATCH_VLSE128_V 0x18000007 +#define MASK_VLSE128_V 0x1c00707f +#define MATCH_VLSE16_V 0x8005007 +#define MASK_VLSE16_V 0x1c00707f +#define MATCH_VLSE256_V 0x18005007 +#define MASK_VLSE256_V 0x1c00707f +#define MATCH_VLSE32_V 0x8006007 +#define MASK_VLSE32_V 0x1c00707f +#define MATCH_VLSE512_V 0x18006007 +#define MASK_VLSE512_V 0x1c00707f +#define MATCH_VLSE64_V 0x8007007 +#define MASK_VLSE64_V 0x1c00707f +#define MATCH_VLSE8_V 0x8000007 +#define MASK_VLSE8_V 0x1c00707f +#define MATCH_VLUXEI1024_V 0x14007007 +#define MASK_VLUXEI1024_V 0x1c00707f +#define MATCH_VLUXEI128_V 0x14000007 +#define MASK_VLUXEI128_V 0x1c00707f +#define MATCH_VLUXEI16_V 0x4005007 +#define MASK_VLUXEI16_V 0x1c00707f +#define MATCH_VLUXEI256_V 0x14005007 +#define MASK_VLUXEI256_V 0x1c00707f +#define MATCH_VLUXEI32_V 0x4006007 +#define MASK_VLUXEI32_V 0x1c00707f +#define MATCH_VLUXEI512_V 0x14006007 +#define MASK_VLUXEI512_V 0x1c00707f +#define MATCH_VLUXEI64_V 0x4007007 +#define MASK_VLUXEI64_V 0x1c00707f +#define MATCH_VLUXEI8_V 0x4000007 +#define MASK_VLUXEI8_V 0x1c00707f +#define MATCH_VMACC_VV 0xb4002057 +#define MASK_VMACC_VV 0xfc00707f +#define MATCH_VMACC_VX 0xb4006057 +#define MASK_VMACC_VX 0xfc00707f +#define MATCH_VMADC_VI 0x46003057 +#define MASK_VMADC_VI 0xfe00707f +#define MATCH_VMADC_VIM 0x44003057 +#define MASK_VMADC_VIM 0xfe00707f +#define MATCH_VMADC_VV 0x46000057 +#define MASK_VMADC_VV 0xfe00707f +#define MATCH_VMADC_VVM 0x44000057 +#define MASK_VMADC_VVM 0xfe00707f +#define MATCH_VMADC_VX 0x46004057 +#define MASK_VMADC_VX 0xfe00707f +#define MATCH_VMADC_VXM 0x44004057 +#define MASK_VMADC_VXM 0xfe00707f +#define MATCH_VMADD_VV 0xa4002057 +#define MASK_VMADD_VV 0xfc00707f +#define MATCH_VMADD_VX 0xa4006057 +#define MASK_VMADD_VX 0xfc00707f +#define MATCH_VMAND_MM 0x64002057 +#define MASK_VMAND_MM 0xfc00707f +#define MATCH_VMANDN_MM 0x60002057 +#define MASK_VMANDN_MM 0xfc00707f +#define MATCH_VMAX_VV 0x1c000057 +#define MASK_VMAX_VV 0xfc00707f +#define MATCH_VMAX_VX 0x1c004057 +#define MASK_VMAX_VX 0xfc00707f +#define MATCH_VMAXU_VV 0x18000057 +#define MASK_VMAXU_VV 0xfc00707f +#define MATCH_VMAXU_VX 0x18004057 +#define MASK_VMAXU_VX 0xfc00707f +#define MATCH_VMERGE_VIM 0x5c003057 +#define MASK_VMERGE_VIM 0xfe00707f +#define MATCH_VMERGE_VVM 0x5c000057 +#define MASK_VMERGE_VVM 0xfe00707f +#define MATCH_VMERGE_VXM 0x5c004057 +#define MASK_VMERGE_VXM 0xfe00707f +#define MATCH_VMFEQ_VF 0x60005057 +#define MASK_VMFEQ_VF 0xfc00707f +#define MATCH_VMFEQ_VV 0x60001057 +#define MASK_VMFEQ_VV 0xfc00707f +#define MATCH_VMFGE_VF 0x7c005057 +#define MASK_VMFGE_VF 0xfc00707f +#define MATCH_VMFGT_VF 0x74005057 +#define MASK_VMFGT_VF 0xfc00707f +#define MATCH_VMFLE_VF 0x64005057 +#define MASK_VMFLE_VF 0xfc00707f +#define MATCH_VMFLE_VV 0x64001057 +#define MASK_VMFLE_VV 0xfc00707f +#define MATCH_VMFLT_VF 0x6c005057 +#define MASK_VMFLT_VF 0xfc00707f +#define MATCH_VMFLT_VV 0x6c001057 +#define MASK_VMFLT_VV 0xfc00707f +#define MATCH_VMFNE_VF 0x70005057 +#define MASK_VMFNE_VF 0xfc00707f +#define MATCH_VMFNE_VV 0x70001057 +#define MASK_VMFNE_VV 0xfc00707f +#define MATCH_VMIN_VV 0x14000057 +#define MASK_VMIN_VV 0xfc00707f +#define MATCH_VMIN_VX 0x14004057 +#define MASK_VMIN_VX 0xfc00707f +#define MATCH_VMINU_VV 0x10000057 +#define MASK_VMINU_VV 0xfc00707f +#define MATCH_VMINU_VX 0x10004057 +#define MASK_VMINU_VX 0xfc00707f +#define MATCH_VMNAND_MM 0x74002057 +#define MASK_VMNAND_MM 0xfc00707f +#define MATCH_VMNOR_MM 0x78002057 +#define MASK_VMNOR_MM 0xfc00707f +#define MATCH_VMOR_MM 0x68002057 +#define MASK_VMOR_MM 0xfc00707f +#define MATCH_VMORN_MM 0x70002057 +#define MASK_VMORN_MM 0xfc00707f +#define MATCH_VMSBC_VV 0x4e000057 +#define MASK_VMSBC_VV 0xfe00707f +#define MATCH_VMSBC_VVM 0x4c000057 +#define MASK_VMSBC_VVM 0xfe00707f +#define MATCH_VMSBC_VX 0x4e004057 +#define MASK_VMSBC_VX 0xfe00707f +#define MATCH_VMSBC_VXM 0x4c004057 +#define MASK_VMSBC_VXM 0xfe00707f +#define MATCH_VMSBF_M 0x5000a057 +#define MASK_VMSBF_M 0xfc0ff07f +#define MATCH_VMSEQ_VI 0x60003057 +#define MASK_VMSEQ_VI 0xfc00707f +#define MATCH_VMSEQ_VV 0x60000057 +#define MASK_VMSEQ_VV 0xfc00707f +#define MATCH_VMSEQ_VX 0x60004057 +#define MASK_VMSEQ_VX 0xfc00707f +#define MATCH_VMSGT_VI 0x7c003057 +#define MASK_VMSGT_VI 0xfc00707f +#define MATCH_VMSGT_VX 0x7c004057 +#define MASK_VMSGT_VX 0xfc00707f +#define MATCH_VMSGTU_VI 0x78003057 +#define MASK_VMSGTU_VI 0xfc00707f +#define MATCH_VMSGTU_VX 0x78004057 +#define MASK_VMSGTU_VX 0xfc00707f +#define MATCH_VMSIF_M 0x5001a057 +#define MASK_VMSIF_M 0xfc0ff07f +#define MATCH_VMSLE_VI 0x74003057 +#define MASK_VMSLE_VI 0xfc00707f +#define MATCH_VMSLE_VV 0x74000057 +#define MASK_VMSLE_VV 0xfc00707f +#define MATCH_VMSLE_VX 0x74004057 +#define MASK_VMSLE_VX 0xfc00707f +#define MATCH_VMSLEU_VI 0x70003057 +#define MASK_VMSLEU_VI 0xfc00707f +#define MATCH_VMSLEU_VV 0x70000057 +#define MASK_VMSLEU_VV 0xfc00707f +#define MATCH_VMSLEU_VX 0x70004057 +#define MASK_VMSLEU_VX 0xfc00707f +#define MATCH_VMSLT_VV 0x6c000057 +#define MASK_VMSLT_VV 0xfc00707f +#define MATCH_VMSLT_VX 0x6c004057 +#define MASK_VMSLT_VX 0xfc00707f +#define MATCH_VMSLTU_VV 0x68000057 +#define MASK_VMSLTU_VV 0xfc00707f +#define MATCH_VMSLTU_VX 0x68004057 +#define MASK_VMSLTU_VX 0xfc00707f +#define MATCH_VMSNE_VI 0x64003057 +#define MASK_VMSNE_VI 0xfc00707f +#define MATCH_VMSNE_VV 0x64000057 +#define MASK_VMSNE_VV 0xfc00707f +#define MATCH_VMSNE_VX 0x64004057 +#define MASK_VMSNE_VX 0xfc00707f +#define MATCH_VMSOF_M 0x50012057 +#define MASK_VMSOF_M 0xfc0ff07f +#define MATCH_VMUL_VV 0x94002057 +#define MASK_VMUL_VV 0xfc00707f +#define MATCH_VMUL_VX 0x94006057 +#define MASK_VMUL_VX 0xfc00707f +#define MATCH_VMULH_VV 0x9c002057 +#define MASK_VMULH_VV 0xfc00707f +#define MATCH_VMULH_VX 0x9c006057 +#define MASK_VMULH_VX 0xfc00707f +#define MATCH_VMULHSU_VV 0x98002057 +#define MASK_VMULHSU_VV 0xfc00707f +#define MATCH_VMULHSU_VX 0x98006057 +#define MASK_VMULHSU_VX 0xfc00707f +#define MATCH_VMULHU_VV 0x90002057 +#define MASK_VMULHU_VV 0xfc00707f +#define MATCH_VMULHU_VX 0x90006057 +#define MASK_VMULHU_VX 0xfc00707f +#define MATCH_VMV1R_V 0x9e003057 +#define MASK_VMV1R_V 0xfe0ff07f +#define MATCH_VMV2R_V 0x9e00b057 +#define MASK_VMV2R_V 0xfe0ff07f +#define MATCH_VMV4R_V 0x9e01b057 +#define MASK_VMV4R_V 0xfe0ff07f +#define MATCH_VMV8R_V 0x9e03b057 +#define MASK_VMV8R_V 0xfe0ff07f +#define MATCH_VMV_S_X 0x42006057 +#define MASK_VMV_S_X 0xfff0707f +#define MATCH_VMV_V_I 0x5e003057 +#define MASK_VMV_V_I 0xfff0707f +#define MATCH_VMV_V_V 0x5e000057 +#define MASK_VMV_V_V 0xfff0707f +#define MATCH_VMV_V_X 0x5e004057 +#define MASK_VMV_V_X 0xfff0707f +#define MATCH_VMV_X_S 0x42002057 +#define MASK_VMV_X_S 0xfe0ff07f +#define MATCH_VMXNOR_MM 0x7c002057 +#define MASK_VMXNOR_MM 0xfc00707f +#define MATCH_VMXOR_MM 0x6c002057 +#define MASK_VMXOR_MM 0xfc00707f +#define MATCH_VNCLIP_WI 0xbc003057 +#define MASK_VNCLIP_WI 0xfc00707f +#define MATCH_VNCLIP_WV 0xbc000057 +#define MASK_VNCLIP_WV 0xfc00707f +#define MATCH_VNCLIP_WX 0xbc004057 +#define MASK_VNCLIP_WX 0xfc00707f +#define MATCH_VNCLIPU_WI 0xb8003057 +#define MASK_VNCLIPU_WI 0xfc00707f +#define MATCH_VNCLIPU_WV 0xb8000057 +#define MASK_VNCLIPU_WV 0xfc00707f +#define MATCH_VNCLIPU_WX 0xb8004057 +#define MASK_VNCLIPU_WX 0xfc00707f +#define MATCH_VNMSAC_VV 0xbc002057 +#define MASK_VNMSAC_VV 0xfc00707f +#define MATCH_VNMSAC_VX 0xbc006057 +#define MASK_VNMSAC_VX 0xfc00707f +#define MATCH_VNMSUB_VV 0xac002057 +#define MASK_VNMSUB_VV 0xfc00707f +#define MATCH_VNMSUB_VX 0xac006057 +#define MASK_VNMSUB_VX 0xfc00707f +#define MATCH_VNSRA_WI 0xb4003057 +#define MASK_VNSRA_WI 0xfc00707f +#define MATCH_VNSRA_WV 0xb4000057 +#define MASK_VNSRA_WV 0xfc00707f +#define MATCH_VNSRA_WX 0xb4004057 +#define MASK_VNSRA_WX 0xfc00707f +#define MATCH_VNSRL_WI 0xb0003057 +#define MASK_VNSRL_WI 0xfc00707f +#define MATCH_VNSRL_WV 0xb0000057 +#define MASK_VNSRL_WV 0xfc00707f +#define MATCH_VNSRL_WX 0xb0004057 +#define MASK_VNSRL_WX 0xfc00707f +#define MATCH_VOR_VI 0x28003057 +#define MASK_VOR_VI 0xfc00707f +#define MATCH_VOR_VV 0x28000057 +#define MASK_VOR_VV 0xfc00707f +#define MATCH_VOR_VX 0x28004057 +#define MASK_VOR_VX 0xfc00707f +#define MATCH_VREDAND_VS 0x4002057 +#define MASK_VREDAND_VS 0xfc00707f +#define MATCH_VREDMAX_VS 0x1c002057 +#define MASK_VREDMAX_VS 0xfc00707f +#define MATCH_VREDMAXU_VS 0x18002057 +#define MASK_VREDMAXU_VS 0xfc00707f +#define MATCH_VREDMIN_VS 0x14002057 +#define MASK_VREDMIN_VS 0xfc00707f +#define MATCH_VREDMINU_VS 0x10002057 +#define MASK_VREDMINU_VS 0xfc00707f +#define MATCH_VREDOR_VS 0x8002057 +#define MASK_VREDOR_VS 0xfc00707f +#define MATCH_VREDSUM_VS 0x2057 +#define MASK_VREDSUM_VS 0xfc00707f +#define MATCH_VREDXOR_VS 0xc002057 +#define MASK_VREDXOR_VS 0xfc00707f +#define MATCH_VREM_VV 0x8c002057 +#define MASK_VREM_VV 0xfc00707f +#define MATCH_VREM_VX 0x8c006057 +#define MASK_VREM_VX 0xfc00707f +#define MATCH_VREMU_VV 0x88002057 +#define MASK_VREMU_VV 0xfc00707f +#define MATCH_VREMU_VX 0x88006057 +#define MASK_VREMU_VX 0xfc00707f +#define MATCH_VRGATHER_VI 0x30003057 +#define MASK_VRGATHER_VI 0xfc00707f +#define MATCH_VRGATHER_VV 0x30000057 +#define MASK_VRGATHER_VV 0xfc00707f +#define MATCH_VRGATHER_VX 0x30004057 +#define MASK_VRGATHER_VX 0xfc00707f +#define MATCH_VRGATHEREI16_VV 0x38000057 +#define MASK_VRGATHEREI16_VV 0xfc00707f +#define MATCH_VRSUB_VI 0xc003057 +#define MASK_VRSUB_VI 0xfc00707f +#define MATCH_VRSUB_VX 0xc004057 +#define MASK_VRSUB_VX 0xfc00707f +#define MATCH_VS1R_V 0x2800027 +#define MASK_VS1R_V 0xfff0707f +#define MATCH_VS2R_V 0x22800027 +#define MASK_VS2R_V 0xfff0707f +#define MATCH_VS4R_V 0x62800027 +#define MASK_VS4R_V 0xfff0707f +#define MATCH_VS8R_V 0xe2800027 +#define MASK_VS8R_V 0xfff0707f +#define MATCH_VSADD_VI 0x84003057 +#define MASK_VSADD_VI 0xfc00707f +#define MATCH_VSADD_VV 0x84000057 +#define MASK_VSADD_VV 0xfc00707f +#define MATCH_VSADD_VX 0x84004057 +#define MASK_VSADD_VX 0xfc00707f +#define MATCH_VSADDU_VI 0x80003057 +#define MASK_VSADDU_VI 0xfc00707f +#define MATCH_VSADDU_VV 0x80000057 +#define MASK_VSADDU_VV 0xfc00707f +#define MATCH_VSADDU_VX 0x80004057 +#define MASK_VSADDU_VX 0xfc00707f +#define MATCH_VSBC_VVM 0x48000057 +#define MASK_VSBC_VVM 0xfe00707f +#define MATCH_VSBC_VXM 0x48004057 +#define MASK_VSBC_VXM 0xfe00707f +#define MATCH_VSE1024_V 0x10007027 +#define MASK_VSE1024_V 0x1df0707f +#define MATCH_VSE128_V 0x10000027 +#define MASK_VSE128_V 0x1df0707f +#define MATCH_VSE16_V 0x5027 +#define MASK_VSE16_V 0x1df0707f +#define MATCH_VSE256_V 0x10005027 +#define MASK_VSE256_V 0x1df0707f +#define MATCH_VSE32_V 0x6027 +#define MASK_VSE32_V 0x1df0707f +#define MATCH_VSE512_V 0x10006027 +#define MASK_VSE512_V 0x1df0707f +#define MATCH_VSE64_V 0x7027 +#define MASK_VSE64_V 0x1df0707f +#define MATCH_VSE8_V 0x27 +#define MASK_VSE8_V 0x1df0707f +#define MATCH_VSETIVLI 0xc0007057 +#define MASK_VSETIVLI 0xc000707f +#define MATCH_VSETVL 0x80007057 +#define MASK_VSETVL 0xfe00707f +#define MATCH_VSETVLI 0x7057 +#define MASK_VSETVLI 0x8000707f +#define MATCH_VSEXT_VF2 0x4803a057 +#define MASK_VSEXT_VF2 0xfc0ff07f +#define MATCH_VSEXT_VF4 0x4802a057 +#define MASK_VSEXT_VF4 0xfc0ff07f +#define MATCH_VSEXT_VF8 0x4801a057 +#define MASK_VSEXT_VF8 0xfc0ff07f +#define MATCH_VSLIDE1DOWN_VX 0x3c006057 +#define MASK_VSLIDE1DOWN_VX 0xfc00707f +#define MATCH_VSLIDE1UP_VX 0x38006057 +#define MASK_VSLIDE1UP_VX 0xfc00707f +#define MATCH_VSLIDEDOWN_VI 0x3c003057 +#define MASK_VSLIDEDOWN_VI 0xfc00707f +#define MATCH_VSLIDEDOWN_VX 0x3c004057 +#define MASK_VSLIDEDOWN_VX 0xfc00707f +#define MATCH_VSLIDEUP_VI 0x38003057 +#define MASK_VSLIDEUP_VI 0xfc00707f +#define MATCH_VSLIDEUP_VX 0x38004057 +#define MASK_VSLIDEUP_VX 0xfc00707f +#define MATCH_VSLL_VI 0x94003057 +#define MASK_VSLL_VI 0xfc00707f +#define MATCH_VSLL_VV 0x94000057 +#define MASK_VSLL_VV 0xfc00707f +#define MATCH_VSLL_VX 0x94004057 +#define MASK_VSLL_VX 0xfc00707f +#define MATCH_VSM_V 0x2b00027 +#define MASK_VSM_V 0xfff0707f +#define MATCH_VSMUL_VV 0x9c000057 +#define MASK_VSMUL_VV 0xfc00707f +#define MATCH_VSMUL_VX 0x9c004057 +#define MASK_VSMUL_VX 0xfc00707f +#define MATCH_VSOXEI1024_V 0x1c007027 +#define MASK_VSOXEI1024_V 0x1c00707f +#define MATCH_VSOXEI128_V 0x1c000027 +#define MASK_VSOXEI128_V 0x1c00707f +#define MATCH_VSOXEI16_V 0xc005027 +#define MASK_VSOXEI16_V 0x1c00707f +#define MATCH_VSOXEI256_V 0x1c005027 +#define MASK_VSOXEI256_V 0x1c00707f +#define MATCH_VSOXEI32_V 0xc006027 +#define MASK_VSOXEI32_V 0x1c00707f +#define MATCH_VSOXEI512_V 0x1c006027 +#define MASK_VSOXEI512_V 0x1c00707f +#define MATCH_VSOXEI64_V 0xc007027 +#define MASK_VSOXEI64_V 0x1c00707f +#define MATCH_VSOXEI8_V 0xc000027 +#define MASK_VSOXEI8_V 0x1c00707f +#define MATCH_VSRA_VI 0xa4003057 +#define MASK_VSRA_VI 0xfc00707f +#define MATCH_VSRA_VV 0xa4000057 +#define MASK_VSRA_VV 0xfc00707f +#define MATCH_VSRA_VX 0xa4004057 +#define MASK_VSRA_VX 0xfc00707f +#define MATCH_VSRL_VI 0xa0003057 +#define MASK_VSRL_VI 0xfc00707f +#define MATCH_VSRL_VV 0xa0000057 +#define MASK_VSRL_VV 0xfc00707f +#define MATCH_VSRL_VX 0xa0004057 +#define MASK_VSRL_VX 0xfc00707f +#define MATCH_VSSE1024_V 0x18007027 +#define MASK_VSSE1024_V 0x1c00707f +#define MATCH_VSSE128_V 0x18000027 +#define MASK_VSSE128_V 0x1c00707f +#define MATCH_VSSE16_V 0x8005027 +#define MASK_VSSE16_V 0x1c00707f +#define MATCH_VSSE256_V 0x18005027 +#define MASK_VSSE256_V 0x1c00707f +#define MATCH_VSSE32_V 0x8006027 +#define MASK_VSSE32_V 0x1c00707f +#define MATCH_VSSE512_V 0x18006027 +#define MASK_VSSE512_V 0x1c00707f +#define MATCH_VSSE64_V 0x8007027 +#define MASK_VSSE64_V 0x1c00707f +#define MATCH_VSSE8_V 0x8000027 +#define MASK_VSSE8_V 0x1c00707f +#define MATCH_VSSRA_VI 0xac003057 +#define MASK_VSSRA_VI 0xfc00707f +#define MATCH_VSSRA_VV 0xac000057 +#define MASK_VSSRA_VV 0xfc00707f +#define MATCH_VSSRA_VX 0xac004057 +#define MASK_VSSRA_VX 0xfc00707f +#define MATCH_VSSRL_VI 0xa8003057 +#define MASK_VSSRL_VI 0xfc00707f +#define MATCH_VSSRL_VV 0xa8000057 +#define MASK_VSSRL_VV 0xfc00707f +#define MATCH_VSSRL_VX 0xa8004057 +#define MASK_VSSRL_VX 0xfc00707f +#define MATCH_VSSUB_VV 0x8c000057 +#define MASK_VSSUB_VV 0xfc00707f +#define MATCH_VSSUB_VX 0x8c004057 +#define MASK_VSSUB_VX 0xfc00707f +#define MATCH_VSSUBU_VV 0x88000057 +#define MASK_VSSUBU_VV 0xfc00707f +#define MATCH_VSSUBU_VX 0x88004057 +#define MASK_VSSUBU_VX 0xfc00707f +#define MATCH_VSUB_VV 0x8000057 +#define MASK_VSUB_VV 0xfc00707f +#define MATCH_VSUB_VX 0x8004057 +#define MASK_VSUB_VX 0xfc00707f +#define MATCH_VSUXEI1024_V 0x14007027 +#define MASK_VSUXEI1024_V 0x1c00707f +#define MATCH_VSUXEI128_V 0x14000027 +#define MASK_VSUXEI128_V 0x1c00707f +#define MATCH_VSUXEI16_V 0x4005027 +#define MASK_VSUXEI16_V 0x1c00707f +#define MATCH_VSUXEI256_V 0x14005027 +#define MASK_VSUXEI256_V 0x1c00707f +#define MATCH_VSUXEI32_V 0x4006027 +#define MASK_VSUXEI32_V 0x1c00707f +#define MATCH_VSUXEI512_V 0x14006027 +#define MASK_VSUXEI512_V 0x1c00707f +#define MATCH_VSUXEI64_V 0x4007027 +#define MASK_VSUXEI64_V 0x1c00707f +#define MATCH_VSUXEI8_V 0x4000027 +#define MASK_VSUXEI8_V 0x1c00707f +#define MATCH_VWADD_VV 0xc4002057 +#define MASK_VWADD_VV 0xfc00707f +#define MATCH_VWADD_VX 0xc4006057 +#define MASK_VWADD_VX 0xfc00707f +#define MATCH_VWADD_WV 0xd4002057 +#define MASK_VWADD_WV 0xfc00707f +#define MATCH_VWADD_WX 0xd4006057 +#define MASK_VWADD_WX 0xfc00707f +#define MATCH_VWADDU_VV 0xc0002057 +#define MASK_VWADDU_VV 0xfc00707f +#define MATCH_VWADDU_VX 0xc0006057 +#define MASK_VWADDU_VX 0xfc00707f +#define MATCH_VWADDU_WV 0xd0002057 +#define MASK_VWADDU_WV 0xfc00707f +#define MATCH_VWADDU_WX 0xd0006057 +#define MASK_VWADDU_WX 0xfc00707f +#define MATCH_VWMACC_VV 0xf4002057 +#define MASK_VWMACC_VV 0xfc00707f +#define MATCH_VWMACC_VX 0xf4006057 +#define MASK_VWMACC_VX 0xfc00707f +#define MATCH_VWMACCSU_VV 0xfc002057 +#define MASK_VWMACCSU_VV 0xfc00707f +#define MATCH_VWMACCSU_VX 0xfc006057 +#define MASK_VWMACCSU_VX 0xfc00707f +#define MATCH_VWMACCU_VV 0xf0002057 +#define MASK_VWMACCU_VV 0xfc00707f +#define MATCH_VWMACCU_VX 0xf0006057 +#define MASK_VWMACCU_VX 0xfc00707f +#define MATCH_VWMACCUS_VX 0xf8006057 +#define MASK_VWMACCUS_VX 0xfc00707f +#define MATCH_VWMUL_VV 0xec002057 +#define MASK_VWMUL_VV 0xfc00707f +#define MATCH_VWMUL_VX 0xec006057 +#define MASK_VWMUL_VX 0xfc00707f +#define MATCH_VWMULSU_VV 0xe8002057 +#define MASK_VWMULSU_VV 0xfc00707f +#define MATCH_VWMULSU_VX 0xe8006057 +#define MASK_VWMULSU_VX 0xfc00707f +#define MATCH_VWMULU_VV 0xe0002057 +#define MASK_VWMULU_VV 0xfc00707f +#define MATCH_VWMULU_VX 0xe0006057 +#define MASK_VWMULU_VX 0xfc00707f +#define MATCH_VWREDSUM_VS 0xc4000057 +#define MASK_VWREDSUM_VS 0xfc00707f +#define MATCH_VWREDSUMU_VS 0xc0000057 +#define MASK_VWREDSUMU_VS 0xfc00707f +#define MATCH_VWSUB_VV 0xcc002057 +#define MASK_VWSUB_VV 0xfc00707f +#define MATCH_VWSUB_VX 0xcc006057 +#define MASK_VWSUB_VX 0xfc00707f +#define MATCH_VWSUB_WV 0xdc002057 +#define MASK_VWSUB_WV 0xfc00707f +#define MATCH_VWSUB_WX 0xdc006057 +#define MASK_VWSUB_WX 0xfc00707f +#define MATCH_VWSUBU_VV 0xc8002057 +#define MASK_VWSUBU_VV 0xfc00707f +#define MATCH_VWSUBU_VX 0xc8006057 +#define MASK_VWSUBU_VX 0xfc00707f +#define MATCH_VWSUBU_WV 0xd8002057 +#define MASK_VWSUBU_WV 0xfc00707f +#define MATCH_VWSUBU_WX 0xd8006057 +#define MASK_VWSUBU_WX 0xfc00707f +#define MATCH_VXOR_VI 0x2c003057 +#define MASK_VXOR_VI 0xfc00707f +#define MATCH_VXOR_VV 0x2c000057 +#define MASK_VXOR_VV 0xfc00707f +#define MATCH_VXOR_VX 0x2c004057 +#define MASK_VXOR_VX 0xfc00707f +#define MATCH_VZEXT_VF2 0x48032057 +#define MASK_VZEXT_VF2 0xfc0ff07f +#define MATCH_VZEXT_VF4 0x48022057 +#define MASK_VZEXT_VF4 0xfc0ff07f +#define MATCH_VZEXT_VF8 0x48012057 +#define MASK_VZEXT_VF8 0xfc0ff07f +#define MATCH_WFI 0x10500073 +#define MASK_WFI 0xffffffff +#define MATCH_WRS_NTO 0xd00073 +#define MASK_WRS_NTO 0xffffffff +#define MATCH_WRS_STO 0x1d00073 +#define MASK_WRS_STO 0xffffffff +#define MATCH_XNOR 0x40004033 +#define MASK_XNOR 0xfe00707f +#define MATCH_XOR 0x4033 +#define MASK_XOR 0xfe00707f +#define MATCH_XORI 0x4013 +#define MASK_XORI 0x707f +#define MATCH_XPERM16 0x28006033 +#define MASK_XPERM16 0xfe00707f +#define MATCH_XPERM32 0x28000033 +#define MASK_XPERM32 0xfe00707f +#define MATCH_XPERM4 0x28002033 +#define MASK_XPERM4 0xfe00707f +#define MATCH_XPERM8 0x28004033 +#define MASK_XPERM8 0xfe00707f +#define MATCH_ZUNPKD810 0xacc00077 +#define MASK_ZUNPKD810 0xfff0707f +#define MATCH_ZUNPKD820 0xacd00077 +#define MASK_ZUNPKD820 0xfff0707f +#define MATCH_ZUNPKD830 0xace00077 +#define MASK_ZUNPKD830 0xfff0707f +#define MATCH_ZUNPKD831 0xacf00077 +#define MASK_ZUNPKD831 0xfff0707f +#define MATCH_ZUNPKD832 0xad700077 +#define MASK_ZUNPKD832 0xfff0707f + +#define CSR_FFLAGS 0x1 +#define CSR_FRM 0x2 +#define CSR_FCSR 0x3 +#define CSR_VSTART 0x8 +#define CSR_VXSAT 0x9 +#define CSR_VXRM 0xa +#define CSR_VCSR 0xf +#define CSR_SEED 0x15 +#define CSR_JVT 0x17 +#define CSR_CYCLE 0xc00 +#define CSR_TIME 0xc01 +#define CSR_INSTRET 0xc02 +#define CSR_HPMCOUNTER3 0xc03 +#define CSR_HPMCOUNTER4 0xc04 +#define CSR_HPMCOUNTER5 0xc05 +#define CSR_HPMCOUNTER6 0xc06 +#define CSR_HPMCOUNTER7 0xc07 +#define CSR_HPMCOUNTER8 0xc08 +#define CSR_HPMCOUNTER9 0xc09 +#define CSR_HPMCOUNTER10 0xc0a +#define CSR_HPMCOUNTER11 0xc0b +#define CSR_HPMCOUNTER12 0xc0c +#define CSR_HPMCOUNTER13 0xc0d +#define CSR_HPMCOUNTER14 0xc0e +#define CSR_HPMCOUNTER15 0xc0f +#define CSR_HPMCOUNTER16 0xc10 +#define CSR_HPMCOUNTER17 0xc11 +#define CSR_HPMCOUNTER18 0xc12 +#define CSR_HPMCOUNTER19 0xc13 +#define CSR_HPMCOUNTER20 0xc14 +#define CSR_HPMCOUNTER21 0xc15 +#define CSR_HPMCOUNTER22 0xc16 +#define CSR_HPMCOUNTER23 0xc17 +#define CSR_HPMCOUNTER24 0xc18 +#define CSR_HPMCOUNTER25 0xc19 +#define CSR_HPMCOUNTER26 0xc1a +#define CSR_HPMCOUNTER27 0xc1b +#define CSR_HPMCOUNTER28 0xc1c +#define CSR_HPMCOUNTER29 0xc1d +#define CSR_HPMCOUNTER30 0xc1e +#define CSR_HPMCOUNTER31 0xc1f +#define CSR_VL 0xc20 +#define CSR_VTYPE 0xc21 +#define CSR_VLENB 0xc22 +#define CSR_SSTATUS 0x100 +#define CSR_SEDELEG 0x102 +#define CSR_SIDELEG 0x103 +#define CSR_SIE 0x104 +#define CSR_STVEC 0x105 +#define CSR_SCOUNTEREN 0x106 +#define CSR_SENVCFG 0x10a +#define CSR_SSTATEEN0 0x10c +#define CSR_SSTATEEN1 0x10d +#define CSR_SSTATEEN2 0x10e +#define CSR_SSTATEEN3 0x10f +#define CSR_SSCRATCH 0x140 +#define CSR_SEPC 0x141 +#define CSR_SCAUSE 0x142 +#define CSR_STVAL 0x143 +#define CSR_SIP 0x144 +#define CSR_STIMECMP 0x14d +#define CSR_SISELECT 0x150 +#define CSR_SIREG 0x151 +#define CSR_STOPEI 0x15c +#define CSR_SATP 0x180 +#define CSR_SCONTEXT 0x5a8 +#define CSR_VSSTATUS 0x200 +#define CSR_VSIE 0x204 +#define CSR_VSTVEC 0x205 +#define CSR_VSSCRATCH 0x240 +#define CSR_VSEPC 0x241 +#define CSR_VSCAUSE 0x242 +#define CSR_VSTVAL 0x243 +#define CSR_VSIP 0x244 +#define CSR_VSTIMECMP 0x24d +#define CSR_VSISELECT 0x250 +#define CSR_VSIREG 0x251 +#define CSR_VSTOPEI 0x25c +#define CSR_VSATP 0x280 +#define CSR_HSTATUS 0x600 +#define CSR_HEDELEG 0x602 +#define CSR_HIDELEG 0x603 +#define CSR_HIE 0x604 +#define CSR_HTIMEDELTA 0x605 +#define CSR_HCOUNTEREN 0x606 +#define CSR_HGEIE 0x607 +#define CSR_HVIEN 0x608 +#define CSR_HVICTL 0x609 +#define CSR_HENVCFG 0x60a +#define CSR_HSTATEEN0 0x60c +#define CSR_HSTATEEN1 0x60d +#define CSR_HSTATEEN2 0x60e +#define CSR_HSTATEEN3 0x60f +#define CSR_HTVAL 0x643 +#define CSR_HIP 0x644 +#define CSR_HVIP 0x645 +#define CSR_HVIPRIO1 0x646 +#define CSR_HVIPRIO2 0x647 +#define CSR_HTINST 0x64a +#define CSR_HGATP 0x680 +#define CSR_HCONTEXT 0x6a8 +#define CSR_HGEIP 0xe12 +#define CSR_VSTOPI 0xeb0 +#define CSR_SCOUNTOVF 0xda0 +#define CSR_STOPI 0xdb0 +#define CSR_UTVT 0x7 +#define CSR_UNXTI 0x45 +#define CSR_UINTSTATUS 0x46 +#define CSR_USCRATCHCSW 0x48 +#define CSR_USCRATCHCSWL 0x49 +#define CSR_STVT 0x107 +#define CSR_SNXTI 0x145 +#define CSR_SINTSTATUS 0x146 +#define CSR_SSCRATCHCSW 0x148 +#define CSR_SSCRATCHCSWL 0x149 +#define CSR_MTVT 0x307 +#define CSR_MNXTI 0x345 +#define CSR_MINTSTATUS 0x346 +#define CSR_MSCRATCHCSW 0x348 +#define CSR_MSCRATCHCSWL 0x349 +#define CSR_MSTATUS 0x300 +#define CSR_MISA 0x301 +#define CSR_MEDELEG 0x302 +#define CSR_MIDELEG 0x303 +#define CSR_MIE 0x304 +#define CSR_MTVEC 0x305 +#define CSR_MCOUNTEREN 0x306 +#define CSR_MVIEN 0x308 +#define CSR_MVIP 0x309 +#define CSR_MENVCFG 0x30a +#define CSR_MSTATEEN0 0x30c +#define CSR_MSTATEEN1 0x30d +#define CSR_MSTATEEN2 0x30e +#define CSR_MSTATEEN3 0x30f +#define CSR_MCOUNTINHIBIT 0x320 +#define CSR_MSCRATCH 0x340 +#define CSR_MEPC 0x341 +#define CSR_MCAUSE 0x342 +#define CSR_MTVAL 0x343 +#define CSR_MIP 0x344 +#define CSR_MTINST 0x34a +#define CSR_MTVAL2 0x34b +#define CSR_MISELECT 0x350 +#define CSR_MIREG 0x351 +#define CSR_MTOPEI 0x35c +#define CSR_PMPCFG0 0x3a0 +#define CSR_PMPCFG1 0x3a1 +#define CSR_PMPCFG2 0x3a2 +#define CSR_PMPCFG3 0x3a3 +#define CSR_PMPCFG4 0x3a4 +#define CSR_PMPCFG5 0x3a5 +#define CSR_PMPCFG6 0x3a6 +#define CSR_PMPCFG7 0x3a7 +#define CSR_PMPCFG8 0x3a8 +#define CSR_PMPCFG9 0x3a9 +#define CSR_PMPCFG10 0x3aa +#define CSR_PMPCFG11 0x3ab +#define CSR_PMPCFG12 0x3ac +#define CSR_PMPCFG13 0x3ad +#define CSR_PMPCFG14 0x3ae +#define CSR_PMPCFG15 0x3af +#define CSR_PMPADDR0 0x3b0 +#define CSR_PMPADDR1 0x3b1 +#define CSR_PMPADDR2 0x3b2 +#define CSR_PMPADDR3 0x3b3 +#define CSR_PMPADDR4 0x3b4 +#define CSR_PMPADDR5 0x3b5 +#define CSR_PMPADDR6 0x3b6 +#define CSR_PMPADDR7 0x3b7 +#define CSR_PMPADDR8 0x3b8 +#define CSR_PMPADDR9 0x3b9 +#define CSR_PMPADDR10 0x3ba +#define CSR_PMPADDR11 0x3bb +#define CSR_PMPADDR12 0x3bc +#define CSR_PMPADDR13 0x3bd +#define CSR_PMPADDR14 0x3be +#define CSR_PMPADDR15 0x3bf +#define CSR_PMPADDR16 0x3c0 +#define CSR_PMPADDR17 0x3c1 +#define CSR_PMPADDR18 0x3c2 +#define CSR_PMPADDR19 0x3c3 +#define CSR_PMPADDR20 0x3c4 +#define CSR_PMPADDR21 0x3c5 +#define CSR_PMPADDR22 0x3c6 +#define CSR_PMPADDR23 0x3c7 +#define CSR_PMPADDR24 0x3c8 +#define CSR_PMPADDR25 0x3c9 +#define CSR_PMPADDR26 0x3ca +#define CSR_PMPADDR27 0x3cb +#define CSR_PMPADDR28 0x3cc +#define CSR_PMPADDR29 0x3cd +#define CSR_PMPADDR30 0x3ce +#define CSR_PMPADDR31 0x3cf +#define CSR_PMPADDR32 0x3d0 +#define CSR_PMPADDR33 0x3d1 +#define CSR_PMPADDR34 0x3d2 +#define CSR_PMPADDR35 0x3d3 +#define CSR_PMPADDR36 0x3d4 +#define CSR_PMPADDR37 0x3d5 +#define CSR_PMPADDR38 0x3d6 +#define CSR_PMPADDR39 0x3d7 +#define CSR_PMPADDR40 0x3d8 +#define CSR_PMPADDR41 0x3d9 +#define CSR_PMPADDR42 0x3da +#define CSR_PMPADDR43 0x3db +#define CSR_PMPADDR44 0x3dc +#define CSR_PMPADDR45 0x3dd +#define CSR_PMPADDR46 0x3de +#define CSR_PMPADDR47 0x3df +#define CSR_PMPADDR48 0x3e0 +#define CSR_PMPADDR49 0x3e1 +#define CSR_PMPADDR50 0x3e2 +#define CSR_PMPADDR51 0x3e3 +#define CSR_PMPADDR52 0x3e4 +#define CSR_PMPADDR53 0x3e5 +#define CSR_PMPADDR54 0x3e6 +#define CSR_PMPADDR55 0x3e7 +#define CSR_PMPADDR56 0x3e8 +#define CSR_PMPADDR57 0x3e9 +#define CSR_PMPADDR58 0x3ea +#define CSR_PMPADDR59 0x3eb +#define CSR_PMPADDR60 0x3ec +#define CSR_PMPADDR61 0x3ed +#define CSR_PMPADDR62 0x3ee +#define CSR_PMPADDR63 0x3ef +#define CSR_MSECCFG 0x747 +#define CSR_TSELECT 0x7a0 +#define CSR_TDATA1 0x7a1 +#define CSR_TDATA2 0x7a2 +#define CSR_TDATA3 0x7a3 +#define CSR_TINFO 0x7a4 +#define CSR_TCONTROL 0x7a5 +#define CSR_MCONTEXT 0x7a8 +#define CSR_MSCONTEXT 0x7aa +#define CSR_DCSR 0x7b0 +#define CSR_DPC 0x7b1 +#define CSR_DSCRATCH0 0x7b2 +#define CSR_DSCRATCH1 0x7b3 +#define CSR_MCYCLE 0xb00 +#define CSR_MINSTRET 0xb02 +#define CSR_MHPMCOUNTER3 0xb03 +#define CSR_MHPMCOUNTER4 0xb04 +#define CSR_MHPMCOUNTER5 0xb05 +#define CSR_MHPMCOUNTER6 0xb06 +#define CSR_MHPMCOUNTER7 0xb07 +#define CSR_MHPMCOUNTER8 0xb08 +#define CSR_MHPMCOUNTER9 0xb09 +#define CSR_MHPMCOUNTER10 0xb0a +#define CSR_MHPMCOUNTER11 0xb0b +#define CSR_MHPMCOUNTER12 0xb0c +#define CSR_MHPMCOUNTER13 0xb0d +#define CSR_MHPMCOUNTER14 0xb0e +#define CSR_MHPMCOUNTER15 0xb0f +#define CSR_MHPMCOUNTER16 0xb10 +#define CSR_MHPMCOUNTER17 0xb11 +#define CSR_MHPMCOUNTER18 0xb12 +#define CSR_MHPMCOUNTER19 0xb13 +#define CSR_MHPMCOUNTER20 0xb14 +#define CSR_MHPMCOUNTER21 0xb15 +#define CSR_MHPMCOUNTER22 0xb16 +#define CSR_MHPMCOUNTER23 0xb17 +#define CSR_MHPMCOUNTER24 0xb18 +#define CSR_MHPMCOUNTER25 0xb19 +#define CSR_MHPMCOUNTER26 0xb1a +#define CSR_MHPMCOUNTER27 0xb1b +#define CSR_MHPMCOUNTER28 0xb1c +#define CSR_MHPMCOUNTER29 0xb1d +#define CSR_MHPMCOUNTER30 0xb1e +#define CSR_MHPMCOUNTER31 0xb1f +#define CSR_MHPMEVENT3 0x323 +#define CSR_MHPMEVENT4 0x324 +#define CSR_MHPMEVENT5 0x325 +#define CSR_MHPMEVENT6 0x326 +#define CSR_MHPMEVENT7 0x327 +#define CSR_MHPMEVENT8 0x328 +#define CSR_MHPMEVENT9 0x329 +#define CSR_MHPMEVENT10 0x32a +#define CSR_MHPMEVENT11 0x32b +#define CSR_MHPMEVENT12 0x32c +#define CSR_MHPMEVENT13 0x32d +#define CSR_MHPMEVENT14 0x32e +#define CSR_MHPMEVENT15 0x32f +#define CSR_MHPMEVENT16 0x330 +#define CSR_MHPMEVENT17 0x331 +#define CSR_MHPMEVENT18 0x332 +#define CSR_MHPMEVENT19 0x333 +#define CSR_MHPMEVENT20 0x334 +#define CSR_MHPMEVENT21 0x335 +#define CSR_MHPMEVENT22 0x336 +#define CSR_MHPMEVENT23 0x337 +#define CSR_MHPMEVENT24 0x338 +#define CSR_MHPMEVENT25 0x339 +#define CSR_MHPMEVENT26 0x33a +#define CSR_MHPMEVENT27 0x33b +#define CSR_MHPMEVENT28 0x33c +#define CSR_MHPMEVENT29 0x33d +#define CSR_MHPMEVENT30 0x33e +#define CSR_MHPMEVENT31 0x33f +#define CSR_MVENDORID 0xf11 +#define CSR_MARCHID 0xf12 +#define CSR_MIMPID 0xf13 +#define CSR_MHARTID 0xf14 +#define CSR_MCONFIGPTR 0xf15 +#define CSR_MTOPI 0xfb0 +#define CSR_SIEH 0x114 +#define CSR_SIPH 0x154 +#define CSR_STIMECMPH 0x15d +#define CSR_VSIEH 0x214 +#define CSR_VSIPH 0x254 +#define CSR_VSTIMECMPH 0x25d +#define CSR_HTIMEDELTAH 0x615 +#define CSR_HIDELEGH 0x613 +#define CSR_HVIENH 0x618 +#define CSR_HENVCFGH 0x61a +#define CSR_HVIPH 0x655 +#define CSR_HVIPRIO1H 0x656 +#define CSR_HVIPRIO2H 0x657 +#define CSR_HSTATEEN0H 0x61c +#define CSR_HSTATEEN1H 0x61d +#define CSR_HSTATEEN2H 0x61e +#define CSR_HSTATEEN3H 0x61f +#define CSR_CYCLEH 0xc80 +#define CSR_TIMEH 0xc81 +#define CSR_INSTRETH 0xc82 +#define CSR_HPMCOUNTER3H 0xc83 +#define CSR_HPMCOUNTER4H 0xc84 +#define CSR_HPMCOUNTER5H 0xc85 +#define CSR_HPMCOUNTER6H 0xc86 +#define CSR_HPMCOUNTER7H 0xc87 +#define CSR_HPMCOUNTER8H 0xc88 +#define CSR_HPMCOUNTER9H 0xc89 +#define CSR_HPMCOUNTER10H 0xc8a +#define CSR_HPMCOUNTER11H 0xc8b +#define CSR_HPMCOUNTER12H 0xc8c +#define CSR_HPMCOUNTER13H 0xc8d +#define CSR_HPMCOUNTER14H 0xc8e +#define CSR_HPMCOUNTER15H 0xc8f +#define CSR_HPMCOUNTER16H 0xc90 +#define CSR_HPMCOUNTER17H 0xc91 +#define CSR_HPMCOUNTER18H 0xc92 +#define CSR_HPMCOUNTER19H 0xc93 +#define CSR_HPMCOUNTER20H 0xc94 +#define CSR_HPMCOUNTER21H 0xc95 +#define CSR_HPMCOUNTER22H 0xc96 +#define CSR_HPMCOUNTER23H 0xc97 +#define CSR_HPMCOUNTER24H 0xc98 +#define CSR_HPMCOUNTER25H 0xc99 +#define CSR_HPMCOUNTER26H 0xc9a +#define CSR_HPMCOUNTER27H 0xc9b +#define CSR_HPMCOUNTER28H 0xc9c +#define CSR_HPMCOUNTER29H 0xc9d +#define CSR_HPMCOUNTER30H 0xc9e +#define CSR_HPMCOUNTER31H 0xc9f +#define CSR_MSTATUSH 0x310 +#define CSR_MIDELEGH 0x313 +#define CSR_MIEH 0x314 +#define CSR_MVIENH 0x318 +#define CSR_MVIPH 0x319 +#define CSR_MENVCFGH 0x31a +#define CSR_MSTATEEN0H 0x31c +#define CSR_MSTATEEN1H 0x31d +#define CSR_MSTATEEN2H 0x31e +#define CSR_MSTATEEN3H 0x31f +#define CSR_MIPH 0x354 +#define CSR_MHPMEVENT3H 0x723 +#define CSR_MHPMEVENT4H 0x724 +#define CSR_MHPMEVENT5H 0x725 +#define CSR_MHPMEVENT6H 0x726 +#define CSR_MHPMEVENT7H 0x727 +#define CSR_MHPMEVENT8H 0x728 +#define CSR_MHPMEVENT9H 0x729 +#define CSR_MHPMEVENT10H 0x72a +#define CSR_MHPMEVENT11H 0x72b +#define CSR_MHPMEVENT12H 0x72c +#define CSR_MHPMEVENT13H 0x72d +#define CSR_MHPMEVENT14H 0x72e +#define CSR_MHPMEVENT15H 0x72f +#define CSR_MHPMEVENT16H 0x730 +#define CSR_MHPMEVENT17H 0x731 +#define CSR_MHPMEVENT18H 0x732 +#define CSR_MHPMEVENT19H 0x733 +#define CSR_MHPMEVENT20H 0x734 +#define CSR_MHPMEVENT21H 0x735 +#define CSR_MHPMEVENT22H 0x736 +#define CSR_MHPMEVENT23H 0x737 +#define CSR_MHPMEVENT24H 0x738 +#define CSR_MHPMEVENT25H 0x739 +#define CSR_MHPMEVENT26H 0x73a +#define CSR_MHPMEVENT27H 0x73b +#define CSR_MHPMEVENT28H 0x73c +#define CSR_MHPMEVENT29H 0x73d +#define CSR_MHPMEVENT30H 0x73e +#define CSR_MHPMEVENT31H 0x73f +#define CSR_MNSCRATCH 0x740 +#define CSR_MNEPC 0x741 +#define CSR_MNCAUSE 0x742 +#define CSR_MNSTATUS 0x744 +#define CSR_MSECCFGH 0x757 +#define CSR_MCYCLEH 0xb80 +#define CSR_MINSTRETH 0xb82 +#define CSR_MHPMCOUNTER3H 0xb83 +#define CSR_MHPMCOUNTER4H 0xb84 +#define CSR_MHPMCOUNTER5H 0xb85 +#define CSR_MHPMCOUNTER6H 0xb86 +#define CSR_MHPMCOUNTER7H 0xb87 +#define CSR_MHPMCOUNTER8H 0xb88 +#define CSR_MHPMCOUNTER9H 0xb89 +#define CSR_MHPMCOUNTER10H 0xb8a +#define CSR_MHPMCOUNTER11H 0xb8b +#define CSR_MHPMCOUNTER12H 0xb8c +#define CSR_MHPMCOUNTER13H 0xb8d +#define CSR_MHPMCOUNTER14H 0xb8e +#define CSR_MHPMCOUNTER15H 0xb8f +#define CSR_MHPMCOUNTER16H 0xb90 +#define CSR_MHPMCOUNTER17H 0xb91 +#define CSR_MHPMCOUNTER18H 0xb92 +#define CSR_MHPMCOUNTER19H 0xb93 +#define CSR_MHPMCOUNTER20H 0xb94 +#define CSR_MHPMCOUNTER21H 0xb95 +#define CSR_MHPMCOUNTER22H 0xb96 +#define CSR_MHPMCOUNTER23H 0xb97 +#define CSR_MHPMCOUNTER24H 0xb98 +#define CSR_MHPMCOUNTER25H 0xb99 +#define CSR_MHPMCOUNTER26H 0xb9a +#define CSR_MHPMCOUNTER27H 0xb9b +#define CSR_MHPMCOUNTER28H 0xb9c +#define CSR_MHPMCOUNTER29H 0xb9d +#define CSR_MHPMCOUNTER30H 0xb9e +#define CSR_MHPMCOUNTER31H 0xb9f + +#define CAUSE_MISALIGNED_FETCH 0x0 +#define CAUSE_FETCH_ACCESS 0x1 +#define CAUSE_ILLEGAL_INSTRUCTION 0x2 +#define CAUSE_BREAKPOINT 0x3 +#define CAUSE_MISALIGNED_LOAD 0x4 +#define CAUSE_LOAD_ACCESS 0x5 +#define CAUSE_MISALIGNED_STORE 0x6 +#define CAUSE_STORE_ACCESS 0x7 +#define CAUSE_USER_ECALL 0x8 +#define CAUSE_SUPERVISOR_ECALL 0x9 +#define CAUSE_VIRTUAL_SUPERVISOR_ECALL 0xa +#define CAUSE_MACHINE_ECALL 0xb +#define CAUSE_FETCH_PAGE_FAULT 0xc +#define CAUSE_LOAD_PAGE_FAULT 0xd +#define CAUSE_STORE_PAGE_FAULT 0xf +#define CAUSE_FETCH_GUEST_PAGE_FAULT 0x14 +#define CAUSE_LOAD_GUEST_PAGE_FAULT 0x15 +#define CAUSE_VIRTUAL_INSTRUCTION 0x16 +#define CAUSE_STORE_GUEST_PAGE_FAULT 0x17 + +#define INSN_FIELD_RD 0xf80 +#define INSN_FIELD_RT 0xf8000 +#define INSN_FIELD_RS1 0xf8000 +#define INSN_FIELD_RS2 0x1f00000 +#define INSN_FIELD_RS3 0xf8000000 +#define INSN_FIELD_AQRL 0x6000000 +#define INSN_FIELD_AQ 0x4000000 +#define INSN_FIELD_RL 0x2000000 +#define INSN_FIELD_FM 0xf0000000 +#define INSN_FIELD_PRED 0xf000000 +#define INSN_FIELD_SUCC 0xf00000 +#define INSN_FIELD_RM 0x7000 +#define INSN_FIELD_FUNCT3 0x7000 +#define INSN_FIELD_FUNCT2 0x6000000 +#define INSN_FIELD_IMM20 0xfffff000 +#define INSN_FIELD_JIMM20 0xfffff000 +#define INSN_FIELD_IMM12 0xfff00000 +#define INSN_FIELD_CSR 0xfff00000 +#define INSN_FIELD_IMM12HI 0xfe000000 +#define INSN_FIELD_BIMM12HI 0xfe000000 +#define INSN_FIELD_IMM12LO 0xf80 +#define INSN_FIELD_BIMM12LO 0xf80 +#define INSN_FIELD_ZIMM 0xf8000 +#define INSN_FIELD_SHAMTQ 0x7f00000 +#define INSN_FIELD_SHAMTW 0x1f00000 +#define INSN_FIELD_SHAMTW4 0xf00000 +#define INSN_FIELD_SHAMTD 0x3f00000 +#define INSN_FIELD_BS 0xc0000000 +#define INSN_FIELD_RNUM 0xf00000 +#define INSN_FIELD_RC 0x3e000000 +#define INSN_FIELD_IMM2 0x300000 +#define INSN_FIELD_IMM3 0x700000 +#define INSN_FIELD_IMM4 0xf00000 +#define INSN_FIELD_IMM5 0x1f00000 +#define INSN_FIELD_IMM6 0x3f00000 +#define INSN_FIELD_OPCODE 0x7f +#define INSN_FIELD_FUNCT7 0xfe000000 +#define INSN_FIELD_VD 0xf80 +#define INSN_FIELD_VS3 0xf80 +#define INSN_FIELD_VS1 0xf8000 +#define INSN_FIELD_VS2 0x1f00000 +#define INSN_FIELD_VM 0x2000000 +#define INSN_FIELD_WD 0x4000000 +#define INSN_FIELD_AMOOP 0xf8000000 +#define INSN_FIELD_NF 0xe0000000 +#define INSN_FIELD_SIMM5 0xf8000 +#define INSN_FIELD_ZIMM10 0x3ff00000 +#define INSN_FIELD_ZIMM11 0x7ff00000 +#define INSN_FIELD_C_NZUIMM10 0x1fe0 +#define INSN_FIELD_C_UIMM7LO 0x60 +#define INSN_FIELD_C_UIMM7HI 0x1c00 +#define INSN_FIELD_C_UIMM8LO 0x60 +#define INSN_FIELD_C_UIMM8HI 0x1c00 +#define INSN_FIELD_C_UIMM9LO 0x60 +#define INSN_FIELD_C_UIMM9HI 0x1c00 +#define INSN_FIELD_C_NZIMM6LO 0x7c +#define INSN_FIELD_C_NZIMM6HI 0x1000 +#define INSN_FIELD_C_IMM6LO 0x7c +#define INSN_FIELD_C_IMM6HI 0x1000 +#define INSN_FIELD_C_NZIMM10HI 0x1000 +#define INSN_FIELD_C_NZIMM10LO 0x7c +#define INSN_FIELD_C_NZIMM18HI 0x1000 +#define INSN_FIELD_C_NZIMM18LO 0x7c +#define INSN_FIELD_C_IMM12 0x1ffc +#define INSN_FIELD_C_BIMM9LO 0x7c +#define INSN_FIELD_C_BIMM9HI 0x1c00 +#define INSN_FIELD_C_NZUIMM5 0x7c +#define INSN_FIELD_C_NZUIMM6LO 0x7c +#define INSN_FIELD_C_NZUIMM6HI 0x1000 +#define INSN_FIELD_C_UIMM8SPLO 0x7c +#define INSN_FIELD_C_UIMM8SPHI 0x1000 +#define INSN_FIELD_C_UIMM8SP_S 0x1f80 +#define INSN_FIELD_C_UIMM10SPLO 0x7c +#define INSN_FIELD_C_UIMM10SPHI 0x1000 +#define INSN_FIELD_C_UIMM9SPLO 0x7c +#define INSN_FIELD_C_UIMM9SPHI 0x1000 +#define INSN_FIELD_C_UIMM10SP_S 0x1f80 +#define INSN_FIELD_C_UIMM9SP_S 0x1f80 +#define INSN_FIELD_C_UIMM2 0x60 +#define INSN_FIELD_C_UIMM1 0x20 +#define INSN_FIELD_C_RLIST 0xf0 +#define INSN_FIELD_C_SPIMM 0xc +#define INSN_FIELD_C_INDEX 0x3fc +#define INSN_FIELD_RS1_P 0x380 +#define INSN_FIELD_RS2_P 0x1c +#define INSN_FIELD_RD_P 0x1c +#define INSN_FIELD_RD_RS1_N0 0xf80 +#define INSN_FIELD_RD_RS1_P 0x380 +#define INSN_FIELD_RD_RS1 0xf80 +#define INSN_FIELD_RD_N2 0xf80 +#define INSN_FIELD_RD_N0 0xf80 +#define INSN_FIELD_RS1_N0 0xf80 +#define INSN_FIELD_C_RS2_N0 0x7c +#define INSN_FIELD_C_RS1_N0 0xf80 +#define INSN_FIELD_C_RS2 0x7c +#define INSN_FIELD_C_SREG1 0x380 +#define INSN_FIELD_C_SREG2 0x1c +#endif +#ifdef DECLARE_INSN +DECLARE_INSN(add, MATCH_ADD, MASK_ADD) +DECLARE_INSN(add16, MATCH_ADD16, MASK_ADD16) +DECLARE_INSN(add32, MATCH_ADD32, MASK_ADD32) +DECLARE_INSN(add64, MATCH_ADD64, MASK_ADD64) +DECLARE_INSN(add8, MATCH_ADD8, MASK_ADD8) +DECLARE_INSN(add_uw, MATCH_ADD_UW, MASK_ADD_UW) +DECLARE_INSN(addd, MATCH_ADDD, MASK_ADDD) +DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI) +DECLARE_INSN(addid, MATCH_ADDID, MASK_ADDID) +DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW) +DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW) +DECLARE_INSN(aes32dsi, MATCH_AES32DSI, MASK_AES32DSI) +DECLARE_INSN(aes32dsmi, MATCH_AES32DSMI, MASK_AES32DSMI) +DECLARE_INSN(aes32esi, MATCH_AES32ESI, MASK_AES32ESI) +DECLARE_INSN(aes32esmi, MATCH_AES32ESMI, MASK_AES32ESMI) +DECLARE_INSN(aes64ds, MATCH_AES64DS, MASK_AES64DS) +DECLARE_INSN(aes64dsm, MATCH_AES64DSM, MASK_AES64DSM) +DECLARE_INSN(aes64es, MATCH_AES64ES, MASK_AES64ES) +DECLARE_INSN(aes64esm, MATCH_AES64ESM, MASK_AES64ESM) +DECLARE_INSN(aes64im, MATCH_AES64IM, MASK_AES64IM) +DECLARE_INSN(aes64ks1i, MATCH_AES64KS1I, MASK_AES64KS1I) +DECLARE_INSN(aes64ks2, MATCH_AES64KS2, MASK_AES64KS2) +DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D) +DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W) +DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D) +DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W) +DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D) +DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W) +DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D) +DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W) +DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D) +DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W) +DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D) +DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W) +DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D) +DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W) +DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D) +DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W) +DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D) +DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W) +DECLARE_INSN(and, MATCH_AND, MASK_AND) +DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI) +DECLARE_INSN(andn, MATCH_ANDN, MASK_ANDN) +DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC) +DECLARE_INSN(ave, MATCH_AVE, MASK_AVE) +DECLARE_INSN(bclr, MATCH_BCLR, MASK_BCLR) +DECLARE_INSN(bclri, MATCH_BCLRI, MASK_BCLRI) +DECLARE_INSN(bcompress, MATCH_BCOMPRESS, MASK_BCOMPRESS) +DECLARE_INSN(bcompressw, MATCH_BCOMPRESSW, MASK_BCOMPRESSW) +DECLARE_INSN(bdecompress, MATCH_BDECOMPRESS, MASK_BDECOMPRESS) +DECLARE_INSN(bdecompressw, MATCH_BDECOMPRESSW, MASK_BDECOMPRESSW) +DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ) +DECLARE_INSN(bext, MATCH_BEXT, MASK_BEXT) +DECLARE_INSN(bexti, MATCH_BEXTI, MASK_BEXTI) +DECLARE_INSN(bfp, MATCH_BFP, MASK_BFP) +DECLARE_INSN(bfpw, MATCH_BFPW, MASK_BFPW) +DECLARE_INSN(bge, MATCH_BGE, MASK_BGE) +DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU) +DECLARE_INSN(binv, MATCH_BINV, MASK_BINV) +DECLARE_INSN(binvi, MATCH_BINVI, MASK_BINVI) +DECLARE_INSN(blt, MATCH_BLT, MASK_BLT) +DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU) +DECLARE_INSN(bmatflip, MATCH_BMATFLIP, MASK_BMATFLIP) +DECLARE_INSN(bmator, MATCH_BMATOR, MASK_BMATOR) +DECLARE_INSN(bmatxor, MATCH_BMATXOR, MASK_BMATXOR) +DECLARE_INSN(bne, MATCH_BNE, MASK_BNE) +DECLARE_INSN(bset, MATCH_BSET, MASK_BSET) +DECLARE_INSN(bseti, MATCH_BSETI, MASK_BSETI) +DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD) +DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI) +DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP) +DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN) +DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW) +DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW) +DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND) +DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI) +DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ) +DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ) +DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK) +DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD) +DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP) +DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW) +DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP) +DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD) +DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP) +DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW) +DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP) +DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J) +DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL) +DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR) +DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR) +DECLARE_INSN(c_lbu, MATCH_C_LBU, MASK_C_LBU) +DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD) +DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP) +DECLARE_INSN(c_lh, MATCH_C_LH, MASK_C_LH) +DECLARE_INSN(c_lhu, MATCH_C_LHU, MASK_C_LHU) +DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI) +DECLARE_INSN(c_lq, MATCH_C_LQ, MASK_C_LQ) +DECLARE_INSN(c_lqsp, MATCH_C_LQSP, MASK_C_LQSP) +DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI) +DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW) +DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP) +DECLARE_INSN(c_mul, MATCH_C_MUL, MASK_C_MUL) +DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV) +DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP) +DECLARE_INSN(c_not, MATCH_C_NOT, MASK_C_NOT) +DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR) +DECLARE_INSN(c_sb, MATCH_C_SB, MASK_C_SB) +DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD) +DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) +DECLARE_INSN(c_sext_b, MATCH_C_SEXT_B, MASK_C_SEXT_B) +DECLARE_INSN(c_sext_h, MATCH_C_SEXT_H, MASK_C_SEXT_H) +DECLARE_INSN(c_sh, MATCH_C_SH, MASK_C_SH) +DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI) +DECLARE_INSN(c_sq, MATCH_C_SQ, MASK_C_SQ) +DECLARE_INSN(c_sqsp, MATCH_C_SQSP, MASK_C_SQSP) +DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI) +DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI) +DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB) +DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW) +DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW) +DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP) +DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR) +DECLARE_INSN(c_zext_b, MATCH_C_ZEXT_B, MASK_C_ZEXT_B) +DECLARE_INSN(c_zext_h, MATCH_C_ZEXT_H, MASK_C_ZEXT_H) +DECLARE_INSN(c_zext_w, MATCH_C_ZEXT_W, MASK_C_ZEXT_W) +DECLARE_INSN(cbo_clean, MATCH_CBO_CLEAN, MASK_CBO_CLEAN) +DECLARE_INSN(cbo_flush, MATCH_CBO_FLUSH, MASK_CBO_FLUSH) +DECLARE_INSN(cbo_inval, MATCH_CBO_INVAL, MASK_CBO_INVAL) +DECLARE_INSN(cbo_zero, MATCH_CBO_ZERO, MASK_CBO_ZERO) +DECLARE_INSN(clmul, MATCH_CLMUL, MASK_CLMUL) +DECLARE_INSN(clmulh, MATCH_CLMULH, MASK_CLMULH) +DECLARE_INSN(clmulr, MATCH_CLMULR, MASK_CLMULR) +DECLARE_INSN(clrs16, MATCH_CLRS16, MASK_CLRS16) +DECLARE_INSN(clrs32, MATCH_CLRS32, MASK_CLRS32) +DECLARE_INSN(clrs8, MATCH_CLRS8, MASK_CLRS8) +DECLARE_INSN(clz, MATCH_CLZ, MASK_CLZ) +DECLARE_INSN(clz16, MATCH_CLZ16, MASK_CLZ16) +DECLARE_INSN(clz32, MATCH_CLZ32, MASK_CLZ32) +DECLARE_INSN(clz8, MATCH_CLZ8, MASK_CLZ8) +DECLARE_INSN(clzw, MATCH_CLZW, MASK_CLZW) +DECLARE_INSN(cm_jalt, MATCH_CM_JALT, MASK_CM_JALT) +DECLARE_INSN(cm_mva01s, MATCH_CM_MVA01S, MASK_CM_MVA01S) +DECLARE_INSN(cm_mvsa01, MATCH_CM_MVSA01, MASK_CM_MVSA01) +DECLARE_INSN(cm_pop, MATCH_CM_POP, MASK_CM_POP) +DECLARE_INSN(cm_popret, MATCH_CM_POPRET, MASK_CM_POPRET) +DECLARE_INSN(cm_popretz, MATCH_CM_POPRETZ, MASK_CM_POPRETZ) +DECLARE_INSN(cm_push, MATCH_CM_PUSH, MASK_CM_PUSH) +DECLARE_INSN(cmix, MATCH_CMIX, MASK_CMIX) +DECLARE_INSN(cmov, MATCH_CMOV, MASK_CMOV) +DECLARE_INSN(cmpeq16, MATCH_CMPEQ16, MASK_CMPEQ16) +DECLARE_INSN(cmpeq8, MATCH_CMPEQ8, MASK_CMPEQ8) +DECLARE_INSN(cpop, MATCH_CPOP, MASK_CPOP) +DECLARE_INSN(cpopw, MATCH_CPOPW, MASK_CPOPW) +DECLARE_INSN(cras16, MATCH_CRAS16, MASK_CRAS16) +DECLARE_INSN(cras32, MATCH_CRAS32, MASK_CRAS32) +DECLARE_INSN(crc32_b, MATCH_CRC32_B, MASK_CRC32_B) +DECLARE_INSN(crc32_d, MATCH_CRC32_D, MASK_CRC32_D) +DECLARE_INSN(crc32_h, MATCH_CRC32_H, MASK_CRC32_H) +DECLARE_INSN(crc32_w, MATCH_CRC32_W, MASK_CRC32_W) +DECLARE_INSN(crc32c_b, MATCH_CRC32C_B, MASK_CRC32C_B) +DECLARE_INSN(crc32c_d, MATCH_CRC32C_D, MASK_CRC32C_D) +DECLARE_INSN(crc32c_h, MATCH_CRC32C_H, MASK_CRC32C_H) +DECLARE_INSN(crc32c_w, MATCH_CRC32C_W, MASK_CRC32C_W) +DECLARE_INSN(crsa16, MATCH_CRSA16, MASK_CRSA16) +DECLARE_INSN(crsa32, MATCH_CRSA32, MASK_CRSA32) +DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC) +DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI) +DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS) +DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI) +DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) +DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI) +DECLARE_INSN(ctz, MATCH_CTZ, MASK_CTZ) +DECLARE_INSN(ctzw, MATCH_CTZW, MASK_CTZW) +DECLARE_INSN(czero_eqz, MATCH_CZERO_EQZ, MASK_CZERO_EQZ) +DECLARE_INSN(czero_nez, MATCH_CZERO_NEZ, MASK_CZERO_NEZ) +DECLARE_INSN(div, MATCH_DIV, MASK_DIV) +DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU) +DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW) +DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW) +DECLARE_INSN(dret, MATCH_DRET, MASK_DRET) +DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK) +DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL) +DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D) +DECLARE_INSN(fadd_h, MATCH_FADD_H, MASK_FADD_H) +DECLARE_INSN(fadd_q, MATCH_FADD_Q, MASK_FADD_Q) +DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S) +DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D) +DECLARE_INSN(fclass_h, MATCH_FCLASS_H, MASK_FCLASS_H) +DECLARE_INSN(fclass_q, MATCH_FCLASS_Q, MASK_FCLASS_Q) +DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S) +DECLARE_INSN(fcvt_d_h, MATCH_FCVT_D_H, MASK_FCVT_D_H) +DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L) +DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU) +DECLARE_INSN(fcvt_d_q, MATCH_FCVT_D_Q, MASK_FCVT_D_Q) +DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S) +DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W) +DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU) +DECLARE_INSN(fcvt_h_d, MATCH_FCVT_H_D, MASK_FCVT_H_D) +DECLARE_INSN(fcvt_h_l, MATCH_FCVT_H_L, MASK_FCVT_H_L) +DECLARE_INSN(fcvt_h_lu, MATCH_FCVT_H_LU, MASK_FCVT_H_LU) +DECLARE_INSN(fcvt_h_q, MATCH_FCVT_H_Q, MASK_FCVT_H_Q) +DECLARE_INSN(fcvt_h_s, MATCH_FCVT_H_S, MASK_FCVT_H_S) +DECLARE_INSN(fcvt_h_w, MATCH_FCVT_H_W, MASK_FCVT_H_W) +DECLARE_INSN(fcvt_h_wu, MATCH_FCVT_H_WU, MASK_FCVT_H_WU) +DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D) +DECLARE_INSN(fcvt_l_h, MATCH_FCVT_L_H, MASK_FCVT_L_H) +DECLARE_INSN(fcvt_l_q, MATCH_FCVT_L_Q, MASK_FCVT_L_Q) +DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S) +DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D) +DECLARE_INSN(fcvt_lu_h, MATCH_FCVT_LU_H, MASK_FCVT_LU_H) +DECLARE_INSN(fcvt_lu_q, MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q) +DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S) +DECLARE_INSN(fcvt_q_d, MATCH_FCVT_Q_D, MASK_FCVT_Q_D) +DECLARE_INSN(fcvt_q_h, MATCH_FCVT_Q_H, MASK_FCVT_Q_H) +DECLARE_INSN(fcvt_q_l, MATCH_FCVT_Q_L, MASK_FCVT_Q_L) +DECLARE_INSN(fcvt_q_lu, MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU) +DECLARE_INSN(fcvt_q_s, MATCH_FCVT_Q_S, MASK_FCVT_Q_S) +DECLARE_INSN(fcvt_q_w, MATCH_FCVT_Q_W, MASK_FCVT_Q_W) +DECLARE_INSN(fcvt_q_wu, MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU) +DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D) +DECLARE_INSN(fcvt_s_h, MATCH_FCVT_S_H, MASK_FCVT_S_H) +DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L) +DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU) +DECLARE_INSN(fcvt_s_q, MATCH_FCVT_S_Q, MASK_FCVT_S_Q) +DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) +DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU) +DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D) +DECLARE_INSN(fcvt_w_h, MATCH_FCVT_W_H, MASK_FCVT_W_H) +DECLARE_INSN(fcvt_w_q, MATCH_FCVT_W_Q, MASK_FCVT_W_Q) +DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S) +DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D) +DECLARE_INSN(fcvt_wu_h, MATCH_FCVT_WU_H, MASK_FCVT_WU_H) +DECLARE_INSN(fcvt_wu_q, MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q) +DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S) +DECLARE_INSN(fcvtmod_w_d, MATCH_FCVTMOD_W_D, MASK_FCVTMOD_W_D) +DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D) +DECLARE_INSN(fdiv_h, MATCH_FDIV_H, MASK_FDIV_H) +DECLARE_INSN(fdiv_q, MATCH_FDIV_Q, MASK_FDIV_Q) +DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S) +DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE) +DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I) +DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D) +DECLARE_INSN(feq_h, MATCH_FEQ_H, MASK_FEQ_H) +DECLARE_INSN(feq_q, MATCH_FEQ_Q, MASK_FEQ_Q) +DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S) +DECLARE_INSN(fld, MATCH_FLD, MASK_FLD) +DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D) +DECLARE_INSN(fle_h, MATCH_FLE_H, MASK_FLE_H) +DECLARE_INSN(fle_q, MATCH_FLE_Q, MASK_FLE_Q) +DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S) +DECLARE_INSN(fleq_d, MATCH_FLEQ_D, MASK_FLEQ_D) +DECLARE_INSN(fleq_h, MATCH_FLEQ_H, MASK_FLEQ_H) +DECLARE_INSN(fleq_q, MATCH_FLEQ_Q, MASK_FLEQ_Q) +DECLARE_INSN(fleq_s, MATCH_FLEQ_S, MASK_FLEQ_S) +DECLARE_INSN(flh, MATCH_FLH, MASK_FLH) +DECLARE_INSN(fli_d, MATCH_FLI_D, MASK_FLI_D) +DECLARE_INSN(fli_h, MATCH_FLI_H, MASK_FLI_H) +DECLARE_INSN(fli_q, MATCH_FLI_Q, MASK_FLI_Q) +DECLARE_INSN(fli_s, MATCH_FLI_S, MASK_FLI_S) +DECLARE_INSN(flq, MATCH_FLQ, MASK_FLQ) +DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D) +DECLARE_INSN(flt_h, MATCH_FLT_H, MASK_FLT_H) +DECLARE_INSN(flt_q, MATCH_FLT_Q, MASK_FLT_Q) +DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S) +DECLARE_INSN(fltq_d, MATCH_FLTQ_D, MASK_FLTQ_D) +DECLARE_INSN(fltq_h, MATCH_FLTQ_H, MASK_FLTQ_H) +DECLARE_INSN(fltq_q, MATCH_FLTQ_Q, MASK_FLTQ_Q) +DECLARE_INSN(fltq_s, MATCH_FLTQ_S, MASK_FLTQ_S) +DECLARE_INSN(flw, MATCH_FLW, MASK_FLW) +DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D) +DECLARE_INSN(fmadd_h, MATCH_FMADD_H, MASK_FMADD_H) +DECLARE_INSN(fmadd_q, MATCH_FMADD_Q, MASK_FMADD_Q) +DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S) +DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D) +DECLARE_INSN(fmax_h, MATCH_FMAX_H, MASK_FMAX_H) +DECLARE_INSN(fmax_q, MATCH_FMAX_Q, MASK_FMAX_Q) +DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S) +DECLARE_INSN(fmaxm_d, MATCH_FMAXM_D, MASK_FMAXM_D) +DECLARE_INSN(fmaxm_h, MATCH_FMAXM_H, MASK_FMAXM_H) +DECLARE_INSN(fmaxm_q, MATCH_FMAXM_Q, MASK_FMAXM_Q) +DECLARE_INSN(fmaxm_s, MATCH_FMAXM_S, MASK_FMAXM_S) +DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D) +DECLARE_INSN(fmin_h, MATCH_FMIN_H, MASK_FMIN_H) +DECLARE_INSN(fmin_q, MATCH_FMIN_Q, MASK_FMIN_Q) +DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S) +DECLARE_INSN(fminm_d, MATCH_FMINM_D, MASK_FMINM_D) +DECLARE_INSN(fminm_h, MATCH_FMINM_H, MASK_FMINM_H) +DECLARE_INSN(fminm_q, MATCH_FMINM_Q, MASK_FMINM_Q) +DECLARE_INSN(fminm_s, MATCH_FMINM_S, MASK_FMINM_S) +DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D) +DECLARE_INSN(fmsub_h, MATCH_FMSUB_H, MASK_FMSUB_H) +DECLARE_INSN(fmsub_q, MATCH_FMSUB_Q, MASK_FMSUB_Q) +DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S) +DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D) +DECLARE_INSN(fmul_h, MATCH_FMUL_H, MASK_FMUL_H) +DECLARE_INSN(fmul_q, MATCH_FMUL_Q, MASK_FMUL_Q) +DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S) +DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X) +DECLARE_INSN(fmv_h_x, MATCH_FMV_H_X, MASK_FMV_H_X) +DECLARE_INSN(fmv_w_x, MATCH_FMV_W_X, MASK_FMV_W_X) +DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D) +DECLARE_INSN(fmv_x_h, MATCH_FMV_X_H, MASK_FMV_X_H) +DECLARE_INSN(fmv_x_w, MATCH_FMV_X_W, MASK_FMV_X_W) +DECLARE_INSN(fmvh_x_d, MATCH_FMVH_X_D, MASK_FMVH_X_D) +DECLARE_INSN(fmvh_x_q, MATCH_FMVH_X_Q, MASK_FMVH_X_Q) +DECLARE_INSN(fmvp_d_x, MATCH_FMVP_D_X, MASK_FMVP_D_X) +DECLARE_INSN(fmvp_q_x, MATCH_FMVP_Q_X, MASK_FMVP_Q_X) +DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D) +DECLARE_INSN(fnmadd_h, MATCH_FNMADD_H, MASK_FNMADD_H) +DECLARE_INSN(fnmadd_q, MATCH_FNMADD_Q, MASK_FNMADD_Q) +DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S) +DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D) +DECLARE_INSN(fnmsub_h, MATCH_FNMSUB_H, MASK_FNMSUB_H) +DECLARE_INSN(fnmsub_q, MATCH_FNMSUB_Q, MASK_FNMSUB_Q) +DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S) +DECLARE_INSN(fround_d, MATCH_FROUND_D, MASK_FROUND_D) +DECLARE_INSN(fround_h, MATCH_FROUND_H, MASK_FROUND_H) +DECLARE_INSN(fround_q, MATCH_FROUND_Q, MASK_FROUND_Q) +DECLARE_INSN(fround_s, MATCH_FROUND_S, MASK_FROUND_S) +DECLARE_INSN(froundnx_d, MATCH_FROUNDNX_D, MASK_FROUNDNX_D) +DECLARE_INSN(froundnx_h, MATCH_FROUNDNX_H, MASK_FROUNDNX_H) +DECLARE_INSN(froundnx_q, MATCH_FROUNDNX_Q, MASK_FROUNDNX_Q) +DECLARE_INSN(froundnx_s, MATCH_FROUNDNX_S, MASK_FROUNDNX_S) +DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD) +DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D) +DECLARE_INSN(fsgnj_h, MATCH_FSGNJ_H, MASK_FSGNJ_H) +DECLARE_INSN(fsgnj_q, MATCH_FSGNJ_Q, MASK_FSGNJ_Q) +DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S) +DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D) +DECLARE_INSN(fsgnjn_h, MATCH_FSGNJN_H, MASK_FSGNJN_H) +DECLARE_INSN(fsgnjn_q, MATCH_FSGNJN_Q, MASK_FSGNJN_Q) +DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S) +DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D) +DECLARE_INSN(fsgnjx_h, MATCH_FSGNJX_H, MASK_FSGNJX_H) +DECLARE_INSN(fsgnjx_q, MATCH_FSGNJX_Q, MASK_FSGNJX_Q) +DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S) +DECLARE_INSN(fsh, MATCH_FSH, MASK_FSH) +DECLARE_INSN(fsl, MATCH_FSL, MASK_FSL) +DECLARE_INSN(fslw, MATCH_FSLW, MASK_FSLW) +DECLARE_INSN(fsq, MATCH_FSQ, MASK_FSQ) +DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D) +DECLARE_INSN(fsqrt_h, MATCH_FSQRT_H, MASK_FSQRT_H) +DECLARE_INSN(fsqrt_q, MATCH_FSQRT_Q, MASK_FSQRT_Q) +DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S) +DECLARE_INSN(fsr, MATCH_FSR, MASK_FSR) +DECLARE_INSN(fsri, MATCH_FSRI, MASK_FSRI) +DECLARE_INSN(fsriw, MATCH_FSRIW, MASK_FSRIW) +DECLARE_INSN(fsrw, MATCH_FSRW, MASK_FSRW) +DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D) +DECLARE_INSN(fsub_h, MATCH_FSUB_H, MASK_FSUB_H) +DECLARE_INSN(fsub_q, MATCH_FSUB_Q, MASK_FSUB_Q) +DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S) +DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW) +DECLARE_INSN(gorc, MATCH_GORC, MASK_GORC) +DECLARE_INSN(gorci, MATCH_GORCI, MASK_GORCI) +DECLARE_INSN(gorciw, MATCH_GORCIW, MASK_GORCIW) +DECLARE_INSN(gorcw, MATCH_GORCW, MASK_GORCW) +DECLARE_INSN(grev, MATCH_GREV, MASK_GREV) +DECLARE_INSN(grevi, MATCH_GREVI, MASK_GREVI) +DECLARE_INSN(greviw, MATCH_GREVIW, MASK_GREVIW) +DECLARE_INSN(grevw, MATCH_GREVW, MASK_GREVW) +DECLARE_INSN(hfence_gvma, MATCH_HFENCE_GVMA, MASK_HFENCE_GVMA) +DECLARE_INSN(hfence_vvma, MATCH_HFENCE_VVMA, MASK_HFENCE_VVMA) +DECLARE_INSN(hinval_gvma, MATCH_HINVAL_GVMA, MASK_HINVAL_GVMA) +DECLARE_INSN(hinval_vvma, MATCH_HINVAL_VVMA, MASK_HINVAL_VVMA) +DECLARE_INSN(hlv_b, MATCH_HLV_B, MASK_HLV_B) +DECLARE_INSN(hlv_bu, MATCH_HLV_BU, MASK_HLV_BU) +DECLARE_INSN(hlv_d, MATCH_HLV_D, MASK_HLV_D) +DECLARE_INSN(hlv_h, MATCH_HLV_H, MASK_HLV_H) +DECLARE_INSN(hlv_hu, MATCH_HLV_HU, MASK_HLV_HU) +DECLARE_INSN(hlv_w, MATCH_HLV_W, MASK_HLV_W) +DECLARE_INSN(hlv_wu, MATCH_HLV_WU, MASK_HLV_WU) +DECLARE_INSN(hlvx_hu, MATCH_HLVX_HU, MASK_HLVX_HU) +DECLARE_INSN(hlvx_wu, MATCH_HLVX_WU, MASK_HLVX_WU) +DECLARE_INSN(hsv_b, MATCH_HSV_B, MASK_HSV_B) +DECLARE_INSN(hsv_d, MATCH_HSV_D, MASK_HSV_D) +DECLARE_INSN(hsv_h, MATCH_HSV_H, MASK_HSV_H) +DECLARE_INSN(hsv_w, MATCH_HSV_W, MASK_HSV_W) +DECLARE_INSN(insb, MATCH_INSB, MASK_INSB) +DECLARE_INSN(jal, MATCH_JAL, MASK_JAL) +DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR) +DECLARE_INSN(kabs16, MATCH_KABS16, MASK_KABS16) +DECLARE_INSN(kabs32, MATCH_KABS32, MASK_KABS32) +DECLARE_INSN(kabs8, MATCH_KABS8, MASK_KABS8) +DECLARE_INSN(kabsw, MATCH_KABSW, MASK_KABSW) +DECLARE_INSN(kadd16, MATCH_KADD16, MASK_KADD16) +DECLARE_INSN(kadd32, MATCH_KADD32, MASK_KADD32) +DECLARE_INSN(kadd64, MATCH_KADD64, MASK_KADD64) +DECLARE_INSN(kadd8, MATCH_KADD8, MASK_KADD8) +DECLARE_INSN(kaddh, MATCH_KADDH, MASK_KADDH) +DECLARE_INSN(kaddw, MATCH_KADDW, MASK_KADDW) +DECLARE_INSN(kcras16, MATCH_KCRAS16, MASK_KCRAS16) +DECLARE_INSN(kcras32, MATCH_KCRAS32, MASK_KCRAS32) +DECLARE_INSN(kcrsa16, MATCH_KCRSA16, MASK_KCRSA16) +DECLARE_INSN(kcrsa32, MATCH_KCRSA32, MASK_KCRSA32) +DECLARE_INSN(kdmabb, MATCH_KDMABB, MASK_KDMABB) +DECLARE_INSN(kdmabb16, MATCH_KDMABB16, MASK_KDMABB16) +DECLARE_INSN(kdmabt, MATCH_KDMABT, MASK_KDMABT) +DECLARE_INSN(kdmabt16, MATCH_KDMABT16, MASK_KDMABT16) +DECLARE_INSN(kdmatt, MATCH_KDMATT, MASK_KDMATT) +DECLARE_INSN(kdmatt16, MATCH_KDMATT16, MASK_KDMATT16) +DECLARE_INSN(kdmbb, MATCH_KDMBB, MASK_KDMBB) +DECLARE_INSN(kdmbb16, MATCH_KDMBB16, MASK_KDMBB16) +DECLARE_INSN(kdmbt, MATCH_KDMBT, MASK_KDMBT) +DECLARE_INSN(kdmbt16, MATCH_KDMBT16, MASK_KDMBT16) +DECLARE_INSN(kdmtt, MATCH_KDMTT, MASK_KDMTT) +DECLARE_INSN(kdmtt16, MATCH_KDMTT16, MASK_KDMTT16) +DECLARE_INSN(khm16, MATCH_KHM16, MASK_KHM16) +DECLARE_INSN(khm8, MATCH_KHM8, MASK_KHM8) +DECLARE_INSN(khmbb, MATCH_KHMBB, MASK_KHMBB) +DECLARE_INSN(khmbb16, MATCH_KHMBB16, MASK_KHMBB16) +DECLARE_INSN(khmbt, MATCH_KHMBT, MASK_KHMBT) +DECLARE_INSN(khmbt16, MATCH_KHMBT16, MASK_KHMBT16) +DECLARE_INSN(khmtt, MATCH_KHMTT, MASK_KHMTT) +DECLARE_INSN(khmtt16, MATCH_KHMTT16, MASK_KHMTT16) +DECLARE_INSN(khmx16, MATCH_KHMX16, MASK_KHMX16) +DECLARE_INSN(khmx8, MATCH_KHMX8, MASK_KHMX8) +DECLARE_INSN(kmabb, MATCH_KMABB, MASK_KMABB) +DECLARE_INSN(kmabb32, MATCH_KMABB32, MASK_KMABB32) +DECLARE_INSN(kmabt, MATCH_KMABT, MASK_KMABT) +DECLARE_INSN(kmabt32, MATCH_KMABT32, MASK_KMABT32) +DECLARE_INSN(kmada, MATCH_KMADA, MASK_KMADA) +DECLARE_INSN(kmadrs, MATCH_KMADRS, MASK_KMADRS) +DECLARE_INSN(kmadrs32, MATCH_KMADRS32, MASK_KMADRS32) +DECLARE_INSN(kmads, MATCH_KMADS, MASK_KMADS) +DECLARE_INSN(kmads32, MATCH_KMADS32, MASK_KMADS32) +DECLARE_INSN(kmar64, MATCH_KMAR64, MASK_KMAR64) +DECLARE_INSN(kmatt, MATCH_KMATT, MASK_KMATT) +DECLARE_INSN(kmatt32, MATCH_KMATT32, MASK_KMATT32) +DECLARE_INSN(kmaxda, MATCH_KMAXDA, MASK_KMAXDA) +DECLARE_INSN(kmaxda32, MATCH_KMAXDA32, MASK_KMAXDA32) +DECLARE_INSN(kmaxds, MATCH_KMAXDS, MASK_KMAXDS) +DECLARE_INSN(kmaxds32, MATCH_KMAXDS32, MASK_KMAXDS32) +DECLARE_INSN(kmda, MATCH_KMDA, MASK_KMDA) +DECLARE_INSN(kmda32, MATCH_KMDA32, MASK_KMDA32) +DECLARE_INSN(kmmac, MATCH_KMMAC, MASK_KMMAC) +DECLARE_INSN(kmmac_u, MATCH_KMMAC_U, MASK_KMMAC_U) +DECLARE_INSN(kmmawb, MATCH_KMMAWB, MASK_KMMAWB) +DECLARE_INSN(kmmawb2, MATCH_KMMAWB2, MASK_KMMAWB2) +DECLARE_INSN(kmmawb2_u, MATCH_KMMAWB2_U, MASK_KMMAWB2_U) +DECLARE_INSN(kmmawb_u, MATCH_KMMAWB_U, MASK_KMMAWB_U) +DECLARE_INSN(kmmawt, MATCH_KMMAWT, MASK_KMMAWT) +DECLARE_INSN(kmmawt2, MATCH_KMMAWT2, MASK_KMMAWT2) +DECLARE_INSN(kmmawt2_u, MATCH_KMMAWT2_U, MASK_KMMAWT2_U) +DECLARE_INSN(kmmawt_u, MATCH_KMMAWT_U, MASK_KMMAWT_U) +DECLARE_INSN(kmmsb, MATCH_KMMSB, MASK_KMMSB) +DECLARE_INSN(kmmsb_u, MATCH_KMMSB_U, MASK_KMMSB_U) +DECLARE_INSN(kmmwb2, MATCH_KMMWB2, MASK_KMMWB2) +DECLARE_INSN(kmmwb2_u, MATCH_KMMWB2_U, MASK_KMMWB2_U) +DECLARE_INSN(kmmwt2, MATCH_KMMWT2, MASK_KMMWT2) +DECLARE_INSN(kmmwt2_u, MATCH_KMMWT2_U, MASK_KMMWT2_U) +DECLARE_INSN(kmsda, MATCH_KMSDA, MASK_KMSDA) +DECLARE_INSN(kmsda32, MATCH_KMSDA32, MASK_KMSDA32) +DECLARE_INSN(kmsr64, MATCH_KMSR64, MASK_KMSR64) +DECLARE_INSN(kmsxda, MATCH_KMSXDA, MASK_KMSXDA) +DECLARE_INSN(kmsxda32, MATCH_KMSXDA32, MASK_KMSXDA32) +DECLARE_INSN(kmxda, MATCH_KMXDA, MASK_KMXDA) +DECLARE_INSN(kmxda32, MATCH_KMXDA32, MASK_KMXDA32) +DECLARE_INSN(ksll16, MATCH_KSLL16, MASK_KSLL16) +DECLARE_INSN(ksll32, MATCH_KSLL32, MASK_KSLL32) +DECLARE_INSN(ksll8, MATCH_KSLL8, MASK_KSLL8) +DECLARE_INSN(kslli16, MATCH_KSLLI16, MASK_KSLLI16) +DECLARE_INSN(kslli32, MATCH_KSLLI32, MASK_KSLLI32) +DECLARE_INSN(kslli8, MATCH_KSLLI8, MASK_KSLLI8) +DECLARE_INSN(kslliw, MATCH_KSLLIW, MASK_KSLLIW) +DECLARE_INSN(ksllw, MATCH_KSLLW, MASK_KSLLW) +DECLARE_INSN(kslra16, MATCH_KSLRA16, MASK_KSLRA16) +DECLARE_INSN(kslra16_u, MATCH_KSLRA16_U, MASK_KSLRA16_U) +DECLARE_INSN(kslra32, MATCH_KSLRA32, MASK_KSLRA32) +DECLARE_INSN(kslra32_u, MATCH_KSLRA32_U, MASK_KSLRA32_U) +DECLARE_INSN(kslra8, MATCH_KSLRA8, MASK_KSLRA8) +DECLARE_INSN(kslra8_u, MATCH_KSLRA8_U, MASK_KSLRA8_U) +DECLARE_INSN(kslraw, MATCH_KSLRAW, MASK_KSLRAW) +DECLARE_INSN(kslraw_u, MATCH_KSLRAW_U, MASK_KSLRAW_U) +DECLARE_INSN(kstas16, MATCH_KSTAS16, MASK_KSTAS16) +DECLARE_INSN(kstas32, MATCH_KSTAS32, MASK_KSTAS32) +DECLARE_INSN(kstsa16, MATCH_KSTSA16, MASK_KSTSA16) +DECLARE_INSN(kstsa32, MATCH_KSTSA32, MASK_KSTSA32) +DECLARE_INSN(ksub16, MATCH_KSUB16, MASK_KSUB16) +DECLARE_INSN(ksub32, MATCH_KSUB32, MASK_KSUB32) +DECLARE_INSN(ksub64, MATCH_KSUB64, MASK_KSUB64) +DECLARE_INSN(ksub8, MATCH_KSUB8, MASK_KSUB8) +DECLARE_INSN(ksubh, MATCH_KSUBH, MASK_KSUBH) +DECLARE_INSN(ksubw, MATCH_KSUBW, MASK_KSUBW) +DECLARE_INSN(kwmmul, MATCH_KWMMUL, MASK_KWMMUL) +DECLARE_INSN(kwmmul_u, MATCH_KWMMUL_U, MASK_KWMMUL_U) +DECLARE_INSN(lb, MATCH_LB, MASK_LB) +DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU) +DECLARE_INSN(ld, MATCH_LD, MASK_LD) +DECLARE_INSN(ldu, MATCH_LDU, MASK_LDU) +DECLARE_INSN(lh, MATCH_LH, MASK_LH) +DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU) +DECLARE_INSN(lq, MATCH_LQ, MASK_LQ) +DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D) +DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W) +DECLARE_INSN(lui, MATCH_LUI, MASK_LUI) +DECLARE_INSN(lw, MATCH_LW, MASK_LW) +DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU) +DECLARE_INSN(maddr32, MATCH_MADDR32, MASK_MADDR32) +DECLARE_INSN(max, MATCH_MAX, MASK_MAX) +DECLARE_INSN(maxu, MATCH_MAXU, MASK_MAXU) +DECLARE_INSN(min, MATCH_MIN, MASK_MIN) +DECLARE_INSN(minu, MATCH_MINU, MASK_MINU) +DECLARE_INSN(mnret, MATCH_MNRET, MASK_MNRET) +DECLARE_INSN(mret, MATCH_MRET, MASK_MRET) +DECLARE_INSN(msubr32, MATCH_MSUBR32, MASK_MSUBR32) +DECLARE_INSN(mul, MATCH_MUL, MASK_MUL) +DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH) +DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU) +DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU) +DECLARE_INSN(mulr64, MATCH_MULR64, MASK_MULR64) +DECLARE_INSN(mulsr64, MATCH_MULSR64, MASK_MULSR64) +DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW) +DECLARE_INSN(or, MATCH_OR, MASK_OR) +DECLARE_INSN(ori, MATCH_ORI, MASK_ORI) +DECLARE_INSN(orn, MATCH_ORN, MASK_ORN) +DECLARE_INSN(pack, MATCH_PACK, MASK_PACK) +DECLARE_INSN(packh, MATCH_PACKH, MASK_PACKH) +DECLARE_INSN(packu, MATCH_PACKU, MASK_PACKU) +DECLARE_INSN(packuw, MATCH_PACKUW, MASK_PACKUW) +DECLARE_INSN(packw, MATCH_PACKW, MASK_PACKW) +DECLARE_INSN(pause, MATCH_PAUSE, MASK_PAUSE) +DECLARE_INSN(pbsad, MATCH_PBSAD, MASK_PBSAD) +DECLARE_INSN(pbsada, MATCH_PBSADA, MASK_PBSADA) +DECLARE_INSN(pkbb16, MATCH_PKBB16, MASK_PKBB16) +DECLARE_INSN(pkbt16, MATCH_PKBT16, MASK_PKBT16) +DECLARE_INSN(pkbt32, MATCH_PKBT32, MASK_PKBT32) +DECLARE_INSN(pktb16, MATCH_PKTB16, MASK_PKTB16) +DECLARE_INSN(pktb32, MATCH_PKTB32, MASK_PKTB32) +DECLARE_INSN(pktt16, MATCH_PKTT16, MASK_PKTT16) +DECLARE_INSN(prefetch_i, MATCH_PREFETCH_I, MASK_PREFETCH_I) +DECLARE_INSN(prefetch_r, MATCH_PREFETCH_R, MASK_PREFETCH_R) +DECLARE_INSN(prefetch_w, MATCH_PREFETCH_W, MASK_PREFETCH_W) +DECLARE_INSN(radd16, MATCH_RADD16, MASK_RADD16) +DECLARE_INSN(radd32, MATCH_RADD32, MASK_RADD32) +DECLARE_INSN(radd64, MATCH_RADD64, MASK_RADD64) +DECLARE_INSN(radd8, MATCH_RADD8, MASK_RADD8) +DECLARE_INSN(raddw, MATCH_RADDW, MASK_RADDW) +DECLARE_INSN(rcras16, MATCH_RCRAS16, MASK_RCRAS16) +DECLARE_INSN(rcras32, MATCH_RCRAS32, MASK_RCRAS32) +DECLARE_INSN(rcrsa16, MATCH_RCRSA16, MASK_RCRSA16) +DECLARE_INSN(rcrsa32, MATCH_RCRSA32, MASK_RCRSA32) +DECLARE_INSN(rem, MATCH_REM, MASK_REM) +DECLARE_INSN(remu, MATCH_REMU, MASK_REMU) +DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW) +DECLARE_INSN(remw, MATCH_REMW, MASK_REMW) +DECLARE_INSN(rol, MATCH_ROL, MASK_ROL) +DECLARE_INSN(rolw, MATCH_ROLW, MASK_ROLW) +DECLARE_INSN(ror, MATCH_ROR, MASK_ROR) +DECLARE_INSN(rori, MATCH_RORI, MASK_RORI) +DECLARE_INSN(roriw, MATCH_RORIW, MASK_RORIW) +DECLARE_INSN(rorw, MATCH_RORW, MASK_RORW) +DECLARE_INSN(rstas16, MATCH_RSTAS16, MASK_RSTAS16) +DECLARE_INSN(rstas32, MATCH_RSTAS32, MASK_RSTAS32) +DECLARE_INSN(rstsa16, MATCH_RSTSA16, MASK_RSTSA16) +DECLARE_INSN(rstsa32, MATCH_RSTSA32, MASK_RSTSA32) +DECLARE_INSN(rsub16, MATCH_RSUB16, MASK_RSUB16) +DECLARE_INSN(rsub32, MATCH_RSUB32, MASK_RSUB32) +DECLARE_INSN(rsub64, MATCH_RSUB64, MASK_RSUB64) +DECLARE_INSN(rsub8, MATCH_RSUB8, MASK_RSUB8) +DECLARE_INSN(rsubw, MATCH_RSUBW, MASK_RSUBW) +DECLARE_INSN(sb, MATCH_SB, MASK_SB) +DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D) +DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W) +DECLARE_INSN(sclip16, MATCH_SCLIP16, MASK_SCLIP16) +DECLARE_INSN(sclip32, MATCH_SCLIP32, MASK_SCLIP32) +DECLARE_INSN(sclip8, MATCH_SCLIP8, MASK_SCLIP8) +DECLARE_INSN(scmple16, MATCH_SCMPLE16, MASK_SCMPLE16) +DECLARE_INSN(scmple8, MATCH_SCMPLE8, MASK_SCMPLE8) +DECLARE_INSN(scmplt16, MATCH_SCMPLT16, MASK_SCMPLT16) +DECLARE_INSN(scmplt8, MATCH_SCMPLT8, MASK_SCMPLT8) +DECLARE_INSN(sd, MATCH_SD, MASK_SD) +DECLARE_INSN(sext_b, MATCH_SEXT_B, MASK_SEXT_B) +DECLARE_INSN(sext_h, MATCH_SEXT_H, MASK_SEXT_H) +DECLARE_INSN(sfence_inval_ir, MATCH_SFENCE_INVAL_IR, MASK_SFENCE_INVAL_IR) +DECLARE_INSN(sfence_vma, MATCH_SFENCE_VMA, MASK_SFENCE_VMA) +DECLARE_INSN(sfence_w_inval, MATCH_SFENCE_W_INVAL, MASK_SFENCE_W_INVAL) +DECLARE_INSN(sh, MATCH_SH, MASK_SH) +DECLARE_INSN(sh1add, MATCH_SH1ADD, MASK_SH1ADD) +DECLARE_INSN(sh1add_uw, MATCH_SH1ADD_UW, MASK_SH1ADD_UW) +DECLARE_INSN(sh2add, MATCH_SH2ADD, MASK_SH2ADD) +DECLARE_INSN(sh2add_uw, MATCH_SH2ADD_UW, MASK_SH2ADD_UW) +DECLARE_INSN(sh3add, MATCH_SH3ADD, MASK_SH3ADD) +DECLARE_INSN(sh3add_uw, MATCH_SH3ADD_UW, MASK_SH3ADD_UW) +DECLARE_INSN(sha256sig0, MATCH_SHA256SIG0, MASK_SHA256SIG0) +DECLARE_INSN(sha256sig1, MATCH_SHA256SIG1, MASK_SHA256SIG1) +DECLARE_INSN(sha256sum0, MATCH_SHA256SUM0, MASK_SHA256SUM0) +DECLARE_INSN(sha256sum1, MATCH_SHA256SUM1, MASK_SHA256SUM1) +DECLARE_INSN(sha512sig0, MATCH_SHA512SIG0, MASK_SHA512SIG0) +DECLARE_INSN(sha512sig0h, MATCH_SHA512SIG0H, MASK_SHA512SIG0H) +DECLARE_INSN(sha512sig0l, MATCH_SHA512SIG0L, MASK_SHA512SIG0L) +DECLARE_INSN(sha512sig1, MATCH_SHA512SIG1, MASK_SHA512SIG1) +DECLARE_INSN(sha512sig1h, MATCH_SHA512SIG1H, MASK_SHA512SIG1H) +DECLARE_INSN(sha512sig1l, MATCH_SHA512SIG1L, MASK_SHA512SIG1L) +DECLARE_INSN(sha512sum0, MATCH_SHA512SUM0, MASK_SHA512SUM0) +DECLARE_INSN(sha512sum0r, MATCH_SHA512SUM0R, MASK_SHA512SUM0R) +DECLARE_INSN(sha512sum1, MATCH_SHA512SUM1, MASK_SHA512SUM1) +DECLARE_INSN(sha512sum1r, MATCH_SHA512SUM1R, MASK_SHA512SUM1R) +DECLARE_INSN(shfl, MATCH_SHFL, MASK_SHFL) +DECLARE_INSN(shfli, MATCH_SHFLI, MASK_SHFLI) +DECLARE_INSN(shflw, MATCH_SHFLW, MASK_SHFLW) +DECLARE_INSN(sinval_vma, MATCH_SINVAL_VMA, MASK_SINVAL_VMA) +DECLARE_INSN(sll, MATCH_SLL, MASK_SLL) +DECLARE_INSN(sll16, MATCH_SLL16, MASK_SLL16) +DECLARE_INSN(sll32, MATCH_SLL32, MASK_SLL32) +DECLARE_INSN(sll8, MATCH_SLL8, MASK_SLL8) +DECLARE_INSN(slld, MATCH_SLLD, MASK_SLLD) +DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI) +DECLARE_INSN(slli16, MATCH_SLLI16, MASK_SLLI16) +DECLARE_INSN(slli32, MATCH_SLLI32, MASK_SLLI32) +DECLARE_INSN(slli8, MATCH_SLLI8, MASK_SLLI8) +DECLARE_INSN(slli_rv128, MATCH_SLLI_RV128, MASK_SLLI_RV128) +DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32) +DECLARE_INSN(slli_uw, MATCH_SLLI_UW, MASK_SLLI_UW) +DECLARE_INSN(sllid, MATCH_SLLID, MASK_SLLID) +DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW) +DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW) +DECLARE_INSN(slo, MATCH_SLO, MASK_SLO) +DECLARE_INSN(sloi, MATCH_SLOI, MASK_SLOI) +DECLARE_INSN(sloiw, MATCH_SLOIW, MASK_SLOIW) +DECLARE_INSN(slow, MATCH_SLOW, MASK_SLOW) +DECLARE_INSN(slt, MATCH_SLT, MASK_SLT) +DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI) +DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU) +DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU) +DECLARE_INSN(sm3p0, MATCH_SM3P0, MASK_SM3P0) +DECLARE_INSN(sm3p1, MATCH_SM3P1, MASK_SM3P1) +DECLARE_INSN(sm4ed, MATCH_SM4ED, MASK_SM4ED) +DECLARE_INSN(sm4ks, MATCH_SM4KS, MASK_SM4KS) +DECLARE_INSN(smal, MATCH_SMAL, MASK_SMAL) +DECLARE_INSN(smalbb, MATCH_SMALBB, MASK_SMALBB) +DECLARE_INSN(smalbt, MATCH_SMALBT, MASK_SMALBT) +DECLARE_INSN(smalda, MATCH_SMALDA, MASK_SMALDA) +DECLARE_INSN(smaldrs, MATCH_SMALDRS, MASK_SMALDRS) +DECLARE_INSN(smalds, MATCH_SMALDS, MASK_SMALDS) +DECLARE_INSN(smaltt, MATCH_SMALTT, MASK_SMALTT) +DECLARE_INSN(smalxda, MATCH_SMALXDA, MASK_SMALXDA) +DECLARE_INSN(smalxds, MATCH_SMALXDS, MASK_SMALXDS) +DECLARE_INSN(smaqa, MATCH_SMAQA, MASK_SMAQA) +DECLARE_INSN(smaqa_su, MATCH_SMAQA_SU, MASK_SMAQA_SU) +DECLARE_INSN(smar64, MATCH_SMAR64, MASK_SMAR64) +DECLARE_INSN(smax16, MATCH_SMAX16, MASK_SMAX16) +DECLARE_INSN(smax32, MATCH_SMAX32, MASK_SMAX32) +DECLARE_INSN(smax8, MATCH_SMAX8, MASK_SMAX8) +DECLARE_INSN(smbb16, MATCH_SMBB16, MASK_SMBB16) +DECLARE_INSN(smbt16, MATCH_SMBT16, MASK_SMBT16) +DECLARE_INSN(smbt32, MATCH_SMBT32, MASK_SMBT32) +DECLARE_INSN(smdrs, MATCH_SMDRS, MASK_SMDRS) +DECLARE_INSN(smdrs32, MATCH_SMDRS32, MASK_SMDRS32) +DECLARE_INSN(smds, MATCH_SMDS, MASK_SMDS) +DECLARE_INSN(smds32, MATCH_SMDS32, MASK_SMDS32) +DECLARE_INSN(smin16, MATCH_SMIN16, MASK_SMIN16) +DECLARE_INSN(smin32, MATCH_SMIN32, MASK_SMIN32) +DECLARE_INSN(smin8, MATCH_SMIN8, MASK_SMIN8) +DECLARE_INSN(smmul, MATCH_SMMUL, MASK_SMMUL) +DECLARE_INSN(smmul_u, MATCH_SMMUL_U, MASK_SMMUL_U) +DECLARE_INSN(smmwb, MATCH_SMMWB, MASK_SMMWB) +DECLARE_INSN(smmwb_u, MATCH_SMMWB_U, MASK_SMMWB_U) +DECLARE_INSN(smmwt, MATCH_SMMWT, MASK_SMMWT) +DECLARE_INSN(smmwt_u, MATCH_SMMWT_U, MASK_SMMWT_U) +DECLARE_INSN(smslda, MATCH_SMSLDA, MASK_SMSLDA) +DECLARE_INSN(smslxda, MATCH_SMSLXDA, MASK_SMSLXDA) +DECLARE_INSN(smsr64, MATCH_SMSR64, MASK_SMSR64) +DECLARE_INSN(smtt16, MATCH_SMTT16, MASK_SMTT16) +DECLARE_INSN(smtt32, MATCH_SMTT32, MASK_SMTT32) +DECLARE_INSN(smul16, MATCH_SMUL16, MASK_SMUL16) +DECLARE_INSN(smul8, MATCH_SMUL8, MASK_SMUL8) +DECLARE_INSN(smulx16, MATCH_SMULX16, MASK_SMULX16) +DECLARE_INSN(smulx8, MATCH_SMULX8, MASK_SMULX8) +DECLARE_INSN(smxds, MATCH_SMXDS, MASK_SMXDS) +DECLARE_INSN(smxds32, MATCH_SMXDS32, MASK_SMXDS32) +DECLARE_INSN(sq, MATCH_SQ, MASK_SQ) +DECLARE_INSN(sra, MATCH_SRA, MASK_SRA) +DECLARE_INSN(sra16, MATCH_SRA16, MASK_SRA16) +DECLARE_INSN(sra16_u, MATCH_SRA16_U, MASK_SRA16_U) +DECLARE_INSN(sra32, MATCH_SRA32, MASK_SRA32) +DECLARE_INSN(sra32_u, MATCH_SRA32_U, MASK_SRA32_U) +DECLARE_INSN(sra8, MATCH_SRA8, MASK_SRA8) +DECLARE_INSN(sra8_u, MATCH_SRA8_U, MASK_SRA8_U) +DECLARE_INSN(sra_u, MATCH_SRA_U, MASK_SRA_U) +DECLARE_INSN(srad, MATCH_SRAD, MASK_SRAD) +DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI) +DECLARE_INSN(srai16, MATCH_SRAI16, MASK_SRAI16) +DECLARE_INSN(srai16_u, MATCH_SRAI16_U, MASK_SRAI16_U) +DECLARE_INSN(srai32, MATCH_SRAI32, MASK_SRAI32) +DECLARE_INSN(srai32_u, MATCH_SRAI32_U, MASK_SRAI32_U) +DECLARE_INSN(srai8, MATCH_SRAI8, MASK_SRAI8) +DECLARE_INSN(srai8_u, MATCH_SRAI8_U, MASK_SRAI8_U) +DECLARE_INSN(srai_rv128, MATCH_SRAI_RV128, MASK_SRAI_RV128) +DECLARE_INSN(srai_rv32, MATCH_SRAI_RV32, MASK_SRAI_RV32) +DECLARE_INSN(srai_u, MATCH_SRAI_U, MASK_SRAI_U) +DECLARE_INSN(sraid, MATCH_SRAID, MASK_SRAID) +DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW) +DECLARE_INSN(sraiw_u, MATCH_SRAIW_U, MASK_SRAIW_U) +DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW) +DECLARE_INSN(sret, MATCH_SRET, MASK_SRET) +DECLARE_INSN(srl, MATCH_SRL, MASK_SRL) +DECLARE_INSN(srl16, MATCH_SRL16, MASK_SRL16) +DECLARE_INSN(srl16_u, MATCH_SRL16_U, MASK_SRL16_U) +DECLARE_INSN(srl32, MATCH_SRL32, MASK_SRL32) +DECLARE_INSN(srl32_u, MATCH_SRL32_U, MASK_SRL32_U) +DECLARE_INSN(srl8, MATCH_SRL8, MASK_SRL8) +DECLARE_INSN(srl8_u, MATCH_SRL8_U, MASK_SRL8_U) +DECLARE_INSN(srld, MATCH_SRLD, MASK_SRLD) +DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI) +DECLARE_INSN(srli16, MATCH_SRLI16, MASK_SRLI16) +DECLARE_INSN(srli16_u, MATCH_SRLI16_U, MASK_SRLI16_U) +DECLARE_INSN(srli32, MATCH_SRLI32, MASK_SRLI32) +DECLARE_INSN(srli32_u, MATCH_SRLI32_U, MASK_SRLI32_U) +DECLARE_INSN(srli8, MATCH_SRLI8, MASK_SRLI8) +DECLARE_INSN(srli8_u, MATCH_SRLI8_U, MASK_SRLI8_U) +DECLARE_INSN(srli_rv128, MATCH_SRLI_RV128, MASK_SRLI_RV128) +DECLARE_INSN(srli_rv32, MATCH_SRLI_RV32, MASK_SRLI_RV32) +DECLARE_INSN(srlid, MATCH_SRLID, MASK_SRLID) +DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW) +DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW) +DECLARE_INSN(sro, MATCH_SRO, MASK_SRO) +DECLARE_INSN(sroi, MATCH_SROI, MASK_SROI) +DECLARE_INSN(sroiw, MATCH_SROIW, MASK_SROIW) +DECLARE_INSN(srow, MATCH_SROW, MASK_SROW) +DECLARE_INSN(stas16, MATCH_STAS16, MASK_STAS16) +DECLARE_INSN(stas32, MATCH_STAS32, MASK_STAS32) +DECLARE_INSN(stsa16, MATCH_STSA16, MASK_STSA16) +DECLARE_INSN(stsa32, MATCH_STSA32, MASK_STSA32) +DECLARE_INSN(sub, MATCH_SUB, MASK_SUB) +DECLARE_INSN(sub16, MATCH_SUB16, MASK_SUB16) +DECLARE_INSN(sub32, MATCH_SUB32, MASK_SUB32) +DECLARE_INSN(sub64, MATCH_SUB64, MASK_SUB64) +DECLARE_INSN(sub8, MATCH_SUB8, MASK_SUB8) +DECLARE_INSN(subd, MATCH_SUBD, MASK_SUBD) +DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW) +DECLARE_INSN(sunpkd810, MATCH_SUNPKD810, MASK_SUNPKD810) +DECLARE_INSN(sunpkd820, MATCH_SUNPKD820, MASK_SUNPKD820) +DECLARE_INSN(sunpkd830, MATCH_SUNPKD830, MASK_SUNPKD830) +DECLARE_INSN(sunpkd831, MATCH_SUNPKD831, MASK_SUNPKD831) +DECLARE_INSN(sunpkd832, MATCH_SUNPKD832, MASK_SUNPKD832) +DECLARE_INSN(sw, MATCH_SW, MASK_SW) +DECLARE_INSN(uclip16, MATCH_UCLIP16, MASK_UCLIP16) +DECLARE_INSN(uclip32, MATCH_UCLIP32, MASK_UCLIP32) +DECLARE_INSN(uclip8, MATCH_UCLIP8, MASK_UCLIP8) +DECLARE_INSN(ucmple16, MATCH_UCMPLE16, MASK_UCMPLE16) +DECLARE_INSN(ucmple8, MATCH_UCMPLE8, MASK_UCMPLE8) +DECLARE_INSN(ucmplt16, MATCH_UCMPLT16, MASK_UCMPLT16) +DECLARE_INSN(ucmplt8, MATCH_UCMPLT8, MASK_UCMPLT8) +DECLARE_INSN(ukadd16, MATCH_UKADD16, MASK_UKADD16) +DECLARE_INSN(ukadd32, MATCH_UKADD32, MASK_UKADD32) +DECLARE_INSN(ukadd64, MATCH_UKADD64, MASK_UKADD64) +DECLARE_INSN(ukadd8, MATCH_UKADD8, MASK_UKADD8) +DECLARE_INSN(ukaddh, MATCH_UKADDH, MASK_UKADDH) +DECLARE_INSN(ukaddw, MATCH_UKADDW, MASK_UKADDW) +DECLARE_INSN(ukcras16, MATCH_UKCRAS16, MASK_UKCRAS16) +DECLARE_INSN(ukcras32, MATCH_UKCRAS32, MASK_UKCRAS32) +DECLARE_INSN(ukcrsa16, MATCH_UKCRSA16, MASK_UKCRSA16) +DECLARE_INSN(ukcrsa32, MATCH_UKCRSA32, MASK_UKCRSA32) +DECLARE_INSN(ukmar64, MATCH_UKMAR64, MASK_UKMAR64) +DECLARE_INSN(ukmsr64, MATCH_UKMSR64, MASK_UKMSR64) +DECLARE_INSN(ukstas16, MATCH_UKSTAS16, MASK_UKSTAS16) +DECLARE_INSN(ukstas32, MATCH_UKSTAS32, MASK_UKSTAS32) +DECLARE_INSN(ukstsa16, MATCH_UKSTSA16, MASK_UKSTSA16) +DECLARE_INSN(ukstsa32, MATCH_UKSTSA32, MASK_UKSTSA32) +DECLARE_INSN(uksub16, MATCH_UKSUB16, MASK_UKSUB16) +DECLARE_INSN(uksub32, MATCH_UKSUB32, MASK_UKSUB32) +DECLARE_INSN(uksub64, MATCH_UKSUB64, MASK_UKSUB64) +DECLARE_INSN(uksub8, MATCH_UKSUB8, MASK_UKSUB8) +DECLARE_INSN(uksubh, MATCH_UKSUBH, MASK_UKSUBH) +DECLARE_INSN(uksubw, MATCH_UKSUBW, MASK_UKSUBW) +DECLARE_INSN(umaqa, MATCH_UMAQA, MASK_UMAQA) +DECLARE_INSN(umar64, MATCH_UMAR64, MASK_UMAR64) +DECLARE_INSN(umax16, MATCH_UMAX16, MASK_UMAX16) +DECLARE_INSN(umax32, MATCH_UMAX32, MASK_UMAX32) +DECLARE_INSN(umax8, MATCH_UMAX8, MASK_UMAX8) +DECLARE_INSN(umin16, MATCH_UMIN16, MASK_UMIN16) +DECLARE_INSN(umin32, MATCH_UMIN32, MASK_UMIN32) +DECLARE_INSN(umin8, MATCH_UMIN8, MASK_UMIN8) +DECLARE_INSN(umsr64, MATCH_UMSR64, MASK_UMSR64) +DECLARE_INSN(umul16, MATCH_UMUL16, MASK_UMUL16) +DECLARE_INSN(umul8, MATCH_UMUL8, MASK_UMUL8) +DECLARE_INSN(umulx16, MATCH_UMULX16, MASK_UMULX16) +DECLARE_INSN(umulx8, MATCH_UMULX8, MASK_UMULX8) +DECLARE_INSN(unshfl, MATCH_UNSHFL, MASK_UNSHFL) +DECLARE_INSN(unshfli, MATCH_UNSHFLI, MASK_UNSHFLI) +DECLARE_INSN(unshflw, MATCH_UNSHFLW, MASK_UNSHFLW) +DECLARE_INSN(uradd16, MATCH_URADD16, MASK_URADD16) +DECLARE_INSN(uradd32, MATCH_URADD32, MASK_URADD32) +DECLARE_INSN(uradd64, MATCH_URADD64, MASK_URADD64) +DECLARE_INSN(uradd8, MATCH_URADD8, MASK_URADD8) +DECLARE_INSN(uraddw, MATCH_URADDW, MASK_URADDW) +DECLARE_INSN(urcras16, MATCH_URCRAS16, MASK_URCRAS16) +DECLARE_INSN(urcras32, MATCH_URCRAS32, MASK_URCRAS32) +DECLARE_INSN(urcrsa16, MATCH_URCRSA16, MASK_URCRSA16) +DECLARE_INSN(urcrsa32, MATCH_URCRSA32, MASK_URCRSA32) +DECLARE_INSN(urstas16, MATCH_URSTAS16, MASK_URSTAS16) +DECLARE_INSN(urstas32, MATCH_URSTAS32, MASK_URSTAS32) +DECLARE_INSN(urstsa16, MATCH_URSTSA16, MASK_URSTSA16) +DECLARE_INSN(urstsa32, MATCH_URSTSA32, MASK_URSTSA32) +DECLARE_INSN(ursub16, MATCH_URSUB16, MASK_URSUB16) +DECLARE_INSN(ursub32, MATCH_URSUB32, MASK_URSUB32) +DECLARE_INSN(ursub64, MATCH_URSUB64, MASK_URSUB64) +DECLARE_INSN(ursub8, MATCH_URSUB8, MASK_URSUB8) +DECLARE_INSN(ursubw, MATCH_URSUBW, MASK_URSUBW) +DECLARE_INSN(vaadd_vv, MATCH_VAADD_VV, MASK_VAADD_VV) +DECLARE_INSN(vaadd_vx, MATCH_VAADD_VX, MASK_VAADD_VX) +DECLARE_INSN(vaaddu_vv, MATCH_VAADDU_VV, MASK_VAADDU_VV) +DECLARE_INSN(vaaddu_vx, MATCH_VAADDU_VX, MASK_VAADDU_VX) +DECLARE_INSN(vadc_vim, MATCH_VADC_VIM, MASK_VADC_VIM) +DECLARE_INSN(vadc_vvm, MATCH_VADC_VVM, MASK_VADC_VVM) +DECLARE_INSN(vadc_vxm, MATCH_VADC_VXM, MASK_VADC_VXM) +DECLARE_INSN(vadd_vi, MATCH_VADD_VI, MASK_VADD_VI) +DECLARE_INSN(vadd_vv, MATCH_VADD_VV, MASK_VADD_VV) +DECLARE_INSN(vadd_vx, MATCH_VADD_VX, MASK_VADD_VX) +DECLARE_INSN(vamoaddei16_v, MATCH_VAMOADDEI16_V, MASK_VAMOADDEI16_V) +DECLARE_INSN(vamoaddei32_v, MATCH_VAMOADDEI32_V, MASK_VAMOADDEI32_V) +DECLARE_INSN(vamoaddei64_v, MATCH_VAMOADDEI64_V, MASK_VAMOADDEI64_V) +DECLARE_INSN(vamoaddei8_v, MATCH_VAMOADDEI8_V, MASK_VAMOADDEI8_V) +DECLARE_INSN(vamoandei16_v, MATCH_VAMOANDEI16_V, MASK_VAMOANDEI16_V) +DECLARE_INSN(vamoandei32_v, MATCH_VAMOANDEI32_V, MASK_VAMOANDEI32_V) +DECLARE_INSN(vamoandei64_v, MATCH_VAMOANDEI64_V, MASK_VAMOANDEI64_V) +DECLARE_INSN(vamoandei8_v, MATCH_VAMOANDEI8_V, MASK_VAMOANDEI8_V) +DECLARE_INSN(vamomaxei16_v, MATCH_VAMOMAXEI16_V, MASK_VAMOMAXEI16_V) +DECLARE_INSN(vamomaxei32_v, MATCH_VAMOMAXEI32_V, MASK_VAMOMAXEI32_V) +DECLARE_INSN(vamomaxei64_v, MATCH_VAMOMAXEI64_V, MASK_VAMOMAXEI64_V) +DECLARE_INSN(vamomaxei8_v, MATCH_VAMOMAXEI8_V, MASK_VAMOMAXEI8_V) +DECLARE_INSN(vamomaxuei16_v, MATCH_VAMOMAXUEI16_V, MASK_VAMOMAXUEI16_V) +DECLARE_INSN(vamomaxuei32_v, MATCH_VAMOMAXUEI32_V, MASK_VAMOMAXUEI32_V) +DECLARE_INSN(vamomaxuei64_v, MATCH_VAMOMAXUEI64_V, MASK_VAMOMAXUEI64_V) +DECLARE_INSN(vamomaxuei8_v, MATCH_VAMOMAXUEI8_V, MASK_VAMOMAXUEI8_V) +DECLARE_INSN(vamominei16_v, MATCH_VAMOMINEI16_V, MASK_VAMOMINEI16_V) +DECLARE_INSN(vamominei32_v, MATCH_VAMOMINEI32_V, MASK_VAMOMINEI32_V) +DECLARE_INSN(vamominei64_v, MATCH_VAMOMINEI64_V, MASK_VAMOMINEI64_V) +DECLARE_INSN(vamominei8_v, MATCH_VAMOMINEI8_V, MASK_VAMOMINEI8_V) +DECLARE_INSN(vamominuei16_v, MATCH_VAMOMINUEI16_V, MASK_VAMOMINUEI16_V) +DECLARE_INSN(vamominuei32_v, MATCH_VAMOMINUEI32_V, MASK_VAMOMINUEI32_V) +DECLARE_INSN(vamominuei64_v, MATCH_VAMOMINUEI64_V, MASK_VAMOMINUEI64_V) +DECLARE_INSN(vamominuei8_v, MATCH_VAMOMINUEI8_V, MASK_VAMOMINUEI8_V) +DECLARE_INSN(vamoorei16_v, MATCH_VAMOOREI16_V, MASK_VAMOOREI16_V) +DECLARE_INSN(vamoorei32_v, MATCH_VAMOOREI32_V, MASK_VAMOOREI32_V) +DECLARE_INSN(vamoorei64_v, MATCH_VAMOOREI64_V, MASK_VAMOOREI64_V) +DECLARE_INSN(vamoorei8_v, MATCH_VAMOOREI8_V, MASK_VAMOOREI8_V) +DECLARE_INSN(vamoswapei16_v, MATCH_VAMOSWAPEI16_V, MASK_VAMOSWAPEI16_V) +DECLARE_INSN(vamoswapei32_v, MATCH_VAMOSWAPEI32_V, MASK_VAMOSWAPEI32_V) +DECLARE_INSN(vamoswapei64_v, MATCH_VAMOSWAPEI64_V, MASK_VAMOSWAPEI64_V) +DECLARE_INSN(vamoswapei8_v, MATCH_VAMOSWAPEI8_V, MASK_VAMOSWAPEI8_V) +DECLARE_INSN(vamoxorei16_v, MATCH_VAMOXOREI16_V, MASK_VAMOXOREI16_V) +DECLARE_INSN(vamoxorei32_v, MATCH_VAMOXOREI32_V, MASK_VAMOXOREI32_V) +DECLARE_INSN(vamoxorei64_v, MATCH_VAMOXOREI64_V, MASK_VAMOXOREI64_V) +DECLARE_INSN(vamoxorei8_v, MATCH_VAMOXOREI8_V, MASK_VAMOXOREI8_V) +DECLARE_INSN(vand_vi, MATCH_VAND_VI, MASK_VAND_VI) +DECLARE_INSN(vand_vv, MATCH_VAND_VV, MASK_VAND_VV) +DECLARE_INSN(vand_vx, MATCH_VAND_VX, MASK_VAND_VX) +DECLARE_INSN(vasub_vv, MATCH_VASUB_VV, MASK_VASUB_VV) +DECLARE_INSN(vasub_vx, MATCH_VASUB_VX, MASK_VASUB_VX) +DECLARE_INSN(vasubu_vv, MATCH_VASUBU_VV, MASK_VASUBU_VV) +DECLARE_INSN(vasubu_vx, MATCH_VASUBU_VX, MASK_VASUBU_VX) +DECLARE_INSN(vcompress_vm, MATCH_VCOMPRESS_VM, MASK_VCOMPRESS_VM) +DECLARE_INSN(vcpop_m, MATCH_VCPOP_M, MASK_VCPOP_M) +DECLARE_INSN(vdiv_vv, MATCH_VDIV_VV, MASK_VDIV_VV) +DECLARE_INSN(vdiv_vx, MATCH_VDIV_VX, MASK_VDIV_VX) +DECLARE_INSN(vdivu_vv, MATCH_VDIVU_VV, MASK_VDIVU_VV) +DECLARE_INSN(vdivu_vx, MATCH_VDIVU_VX, MASK_VDIVU_VX) +DECLARE_INSN(vfadd_vf, MATCH_VFADD_VF, MASK_VFADD_VF) +DECLARE_INSN(vfadd_vv, MATCH_VFADD_VV, MASK_VFADD_VV) +DECLARE_INSN(vfclass_v, MATCH_VFCLASS_V, MASK_VFCLASS_V) +DECLARE_INSN(vfcvt_f_x_v, MATCH_VFCVT_F_X_V, MASK_VFCVT_F_X_V) +DECLARE_INSN(vfcvt_f_xu_v, MATCH_VFCVT_F_XU_V, MASK_VFCVT_F_XU_V) +DECLARE_INSN(vfcvt_rtz_x_f_v, MATCH_VFCVT_RTZ_X_F_V, MASK_VFCVT_RTZ_X_F_V) +DECLARE_INSN(vfcvt_rtz_xu_f_v, MATCH_VFCVT_RTZ_XU_F_V, MASK_VFCVT_RTZ_XU_F_V) +DECLARE_INSN(vfcvt_x_f_v, MATCH_VFCVT_X_F_V, MASK_VFCVT_X_F_V) +DECLARE_INSN(vfcvt_xu_f_v, MATCH_VFCVT_XU_F_V, MASK_VFCVT_XU_F_V) +DECLARE_INSN(vfdiv_vf, MATCH_VFDIV_VF, MASK_VFDIV_VF) +DECLARE_INSN(vfdiv_vv, MATCH_VFDIV_VV, MASK_VFDIV_VV) +DECLARE_INSN(vfirst_m, MATCH_VFIRST_M, MASK_VFIRST_M) +DECLARE_INSN(vfmacc_vf, MATCH_VFMACC_VF, MASK_VFMACC_VF) +DECLARE_INSN(vfmacc_vv, MATCH_VFMACC_VV, MASK_VFMACC_VV) +DECLARE_INSN(vfmadd_vf, MATCH_VFMADD_VF, MASK_VFMADD_VF) +DECLARE_INSN(vfmadd_vv, MATCH_VFMADD_VV, MASK_VFMADD_VV) +DECLARE_INSN(vfmax_vf, MATCH_VFMAX_VF, MASK_VFMAX_VF) +DECLARE_INSN(vfmax_vv, MATCH_VFMAX_VV, MASK_VFMAX_VV) +DECLARE_INSN(vfmerge_vfm, MATCH_VFMERGE_VFM, MASK_VFMERGE_VFM) +DECLARE_INSN(vfmin_vf, MATCH_VFMIN_VF, MASK_VFMIN_VF) +DECLARE_INSN(vfmin_vv, MATCH_VFMIN_VV, MASK_VFMIN_VV) +DECLARE_INSN(vfmsac_vf, MATCH_VFMSAC_VF, MASK_VFMSAC_VF) +DECLARE_INSN(vfmsac_vv, MATCH_VFMSAC_VV, MASK_VFMSAC_VV) +DECLARE_INSN(vfmsub_vf, MATCH_VFMSUB_VF, MASK_VFMSUB_VF) +DECLARE_INSN(vfmsub_vv, MATCH_VFMSUB_VV, MASK_VFMSUB_VV) +DECLARE_INSN(vfmul_vf, MATCH_VFMUL_VF, MASK_VFMUL_VF) +DECLARE_INSN(vfmul_vv, MATCH_VFMUL_VV, MASK_VFMUL_VV) +DECLARE_INSN(vfmv_f_s, MATCH_VFMV_F_S, MASK_VFMV_F_S) +DECLARE_INSN(vfmv_s_f, MATCH_VFMV_S_F, MASK_VFMV_S_F) +DECLARE_INSN(vfmv_v_f, MATCH_VFMV_V_F, MASK_VFMV_V_F) +DECLARE_INSN(vfncvt_f_f_w, MATCH_VFNCVT_F_F_W, MASK_VFNCVT_F_F_W) +DECLARE_INSN(vfncvt_f_x_w, MATCH_VFNCVT_F_X_W, MASK_VFNCVT_F_X_W) +DECLARE_INSN(vfncvt_f_xu_w, MATCH_VFNCVT_F_XU_W, MASK_VFNCVT_F_XU_W) +DECLARE_INSN(vfncvt_rod_f_f_w, MATCH_VFNCVT_ROD_F_F_W, MASK_VFNCVT_ROD_F_F_W) +DECLARE_INSN(vfncvt_rtz_x_f_w, MATCH_VFNCVT_RTZ_X_F_W, MASK_VFNCVT_RTZ_X_F_W) +DECLARE_INSN(vfncvt_rtz_xu_f_w, MATCH_VFNCVT_RTZ_XU_F_W, MASK_VFNCVT_RTZ_XU_F_W) +DECLARE_INSN(vfncvt_x_f_w, MATCH_VFNCVT_X_F_W, MASK_VFNCVT_X_F_W) +DECLARE_INSN(vfncvt_xu_f_w, MATCH_VFNCVT_XU_F_W, MASK_VFNCVT_XU_F_W) +DECLARE_INSN(vfnmacc_vf, MATCH_VFNMACC_VF, MASK_VFNMACC_VF) +DECLARE_INSN(vfnmacc_vv, MATCH_VFNMACC_VV, MASK_VFNMACC_VV) +DECLARE_INSN(vfnmadd_vf, MATCH_VFNMADD_VF, MASK_VFNMADD_VF) +DECLARE_INSN(vfnmadd_vv, MATCH_VFNMADD_VV, MASK_VFNMADD_VV) +DECLARE_INSN(vfnmsac_vf, MATCH_VFNMSAC_VF, MASK_VFNMSAC_VF) +DECLARE_INSN(vfnmsac_vv, MATCH_VFNMSAC_VV, MASK_VFNMSAC_VV) +DECLARE_INSN(vfnmsub_vf, MATCH_VFNMSUB_VF, MASK_VFNMSUB_VF) +DECLARE_INSN(vfnmsub_vv, MATCH_VFNMSUB_VV, MASK_VFNMSUB_VV) +DECLARE_INSN(vfrdiv_vf, MATCH_VFRDIV_VF, MASK_VFRDIV_VF) +DECLARE_INSN(vfrec7_v, MATCH_VFREC7_V, MASK_VFREC7_V) +DECLARE_INSN(vfredmax_vs, MATCH_VFREDMAX_VS, MASK_VFREDMAX_VS) +DECLARE_INSN(vfredmin_vs, MATCH_VFREDMIN_VS, MASK_VFREDMIN_VS) +DECLARE_INSN(vfredosum_vs, MATCH_VFREDOSUM_VS, MASK_VFREDOSUM_VS) +DECLARE_INSN(vfredusum_vs, MATCH_VFREDUSUM_VS, MASK_VFREDUSUM_VS) +DECLARE_INSN(vfrsqrt7_v, MATCH_VFRSQRT7_V, MASK_VFRSQRT7_V) +DECLARE_INSN(vfrsub_vf, MATCH_VFRSUB_VF, MASK_VFRSUB_VF) +DECLARE_INSN(vfsgnj_vf, MATCH_VFSGNJ_VF, MASK_VFSGNJ_VF) +DECLARE_INSN(vfsgnj_vv, MATCH_VFSGNJ_VV, MASK_VFSGNJ_VV) +DECLARE_INSN(vfsgnjn_vf, MATCH_VFSGNJN_VF, MASK_VFSGNJN_VF) +DECLARE_INSN(vfsgnjn_vv, MATCH_VFSGNJN_VV, MASK_VFSGNJN_VV) +DECLARE_INSN(vfsgnjx_vf, MATCH_VFSGNJX_VF, MASK_VFSGNJX_VF) +DECLARE_INSN(vfsgnjx_vv, MATCH_VFSGNJX_VV, MASK_VFSGNJX_VV) +DECLARE_INSN(vfslide1down_vf, MATCH_VFSLIDE1DOWN_VF, MASK_VFSLIDE1DOWN_VF) +DECLARE_INSN(vfslide1up_vf, MATCH_VFSLIDE1UP_VF, MASK_VFSLIDE1UP_VF) +DECLARE_INSN(vfsqrt_v, MATCH_VFSQRT_V, MASK_VFSQRT_V) +DECLARE_INSN(vfsub_vf, MATCH_VFSUB_VF, MASK_VFSUB_VF) +DECLARE_INSN(vfsub_vv, MATCH_VFSUB_VV, MASK_VFSUB_VV) +DECLARE_INSN(vfwadd_vf, MATCH_VFWADD_VF, MASK_VFWADD_VF) +DECLARE_INSN(vfwadd_vv, MATCH_VFWADD_VV, MASK_VFWADD_VV) +DECLARE_INSN(vfwadd_wf, MATCH_VFWADD_WF, MASK_VFWADD_WF) +DECLARE_INSN(vfwadd_wv, MATCH_VFWADD_WV, MASK_VFWADD_WV) +DECLARE_INSN(vfwcvt_f_f_v, MATCH_VFWCVT_F_F_V, MASK_VFWCVT_F_F_V) +DECLARE_INSN(vfwcvt_f_x_v, MATCH_VFWCVT_F_X_V, MASK_VFWCVT_F_X_V) +DECLARE_INSN(vfwcvt_f_xu_v, MATCH_VFWCVT_F_XU_V, MASK_VFWCVT_F_XU_V) +DECLARE_INSN(vfwcvt_rtz_x_f_v, MATCH_VFWCVT_RTZ_X_F_V, MASK_VFWCVT_RTZ_X_F_V) +DECLARE_INSN(vfwcvt_rtz_xu_f_v, MATCH_VFWCVT_RTZ_XU_F_V, MASK_VFWCVT_RTZ_XU_F_V) +DECLARE_INSN(vfwcvt_x_f_v, MATCH_VFWCVT_X_F_V, MASK_VFWCVT_X_F_V) +DECLARE_INSN(vfwcvt_xu_f_v, MATCH_VFWCVT_XU_F_V, MASK_VFWCVT_XU_F_V) +DECLARE_INSN(vfwmacc_vf, MATCH_VFWMACC_VF, MASK_VFWMACC_VF) +DECLARE_INSN(vfwmacc_vv, MATCH_VFWMACC_VV, MASK_VFWMACC_VV) +DECLARE_INSN(vfwmsac_vf, MATCH_VFWMSAC_VF, MASK_VFWMSAC_VF) +DECLARE_INSN(vfwmsac_vv, MATCH_VFWMSAC_VV, MASK_VFWMSAC_VV) +DECLARE_INSN(vfwmul_vf, MATCH_VFWMUL_VF, MASK_VFWMUL_VF) +DECLARE_INSN(vfwmul_vv, MATCH_VFWMUL_VV, MASK_VFWMUL_VV) +DECLARE_INSN(vfwnmacc_vf, MATCH_VFWNMACC_VF, MASK_VFWNMACC_VF) +DECLARE_INSN(vfwnmacc_vv, MATCH_VFWNMACC_VV, MASK_VFWNMACC_VV) +DECLARE_INSN(vfwnmsac_vf, MATCH_VFWNMSAC_VF, MASK_VFWNMSAC_VF) +DECLARE_INSN(vfwnmsac_vv, MATCH_VFWNMSAC_VV, MASK_VFWNMSAC_VV) +DECLARE_INSN(vfwredosum_vs, MATCH_VFWREDOSUM_VS, MASK_VFWREDOSUM_VS) +DECLARE_INSN(vfwredusum_vs, MATCH_VFWREDUSUM_VS, MASK_VFWREDUSUM_VS) +DECLARE_INSN(vfwsub_vf, MATCH_VFWSUB_VF, MASK_VFWSUB_VF) +DECLARE_INSN(vfwsub_vv, MATCH_VFWSUB_VV, MASK_VFWSUB_VV) +DECLARE_INSN(vfwsub_wf, MATCH_VFWSUB_WF, MASK_VFWSUB_WF) +DECLARE_INSN(vfwsub_wv, MATCH_VFWSUB_WV, MASK_VFWSUB_WV) +DECLARE_INSN(vid_v, MATCH_VID_V, MASK_VID_V) +DECLARE_INSN(viota_m, MATCH_VIOTA_M, MASK_VIOTA_M) +DECLARE_INSN(vl1re16_v, MATCH_VL1RE16_V, MASK_VL1RE16_V) +DECLARE_INSN(vl1re32_v, MATCH_VL1RE32_V, MASK_VL1RE32_V) +DECLARE_INSN(vl1re64_v, MATCH_VL1RE64_V, MASK_VL1RE64_V) +DECLARE_INSN(vl1re8_v, MATCH_VL1RE8_V, MASK_VL1RE8_V) +DECLARE_INSN(vl2re16_v, MATCH_VL2RE16_V, MASK_VL2RE16_V) +DECLARE_INSN(vl2re32_v, MATCH_VL2RE32_V, MASK_VL2RE32_V) +DECLARE_INSN(vl2re64_v, MATCH_VL2RE64_V, MASK_VL2RE64_V) +DECLARE_INSN(vl2re8_v, MATCH_VL2RE8_V, MASK_VL2RE8_V) +DECLARE_INSN(vl4re16_v, MATCH_VL4RE16_V, MASK_VL4RE16_V) +DECLARE_INSN(vl4re32_v, MATCH_VL4RE32_V, MASK_VL4RE32_V) +DECLARE_INSN(vl4re64_v, MATCH_VL4RE64_V, MASK_VL4RE64_V) +DECLARE_INSN(vl4re8_v, MATCH_VL4RE8_V, MASK_VL4RE8_V) +DECLARE_INSN(vl8re16_v, MATCH_VL8RE16_V, MASK_VL8RE16_V) +DECLARE_INSN(vl8re32_v, MATCH_VL8RE32_V, MASK_VL8RE32_V) +DECLARE_INSN(vl8re64_v, MATCH_VL8RE64_V, MASK_VL8RE64_V) +DECLARE_INSN(vl8re8_v, MATCH_VL8RE8_V, MASK_VL8RE8_V) +DECLARE_INSN(vle1024_v, MATCH_VLE1024_V, MASK_VLE1024_V) +DECLARE_INSN(vle1024ff_v, MATCH_VLE1024FF_V, MASK_VLE1024FF_V) +DECLARE_INSN(vle128_v, MATCH_VLE128_V, MASK_VLE128_V) +DECLARE_INSN(vle128ff_v, MATCH_VLE128FF_V, MASK_VLE128FF_V) +DECLARE_INSN(vle16_v, MATCH_VLE16_V, MASK_VLE16_V) +DECLARE_INSN(vle16ff_v, MATCH_VLE16FF_V, MASK_VLE16FF_V) +DECLARE_INSN(vle256_v, MATCH_VLE256_V, MASK_VLE256_V) +DECLARE_INSN(vle256ff_v, MATCH_VLE256FF_V, MASK_VLE256FF_V) +DECLARE_INSN(vle32_v, MATCH_VLE32_V, MASK_VLE32_V) +DECLARE_INSN(vle32ff_v, MATCH_VLE32FF_V, MASK_VLE32FF_V) +DECLARE_INSN(vle512_v, MATCH_VLE512_V, MASK_VLE512_V) +DECLARE_INSN(vle512ff_v, MATCH_VLE512FF_V, MASK_VLE512FF_V) +DECLARE_INSN(vle64_v, MATCH_VLE64_V, MASK_VLE64_V) +DECLARE_INSN(vle64ff_v, MATCH_VLE64FF_V, MASK_VLE64FF_V) +DECLARE_INSN(vle8_v, MATCH_VLE8_V, MASK_VLE8_V) +DECLARE_INSN(vle8ff_v, MATCH_VLE8FF_V, MASK_VLE8FF_V) +DECLARE_INSN(vlm_v, MATCH_VLM_V, MASK_VLM_V) +DECLARE_INSN(vloxei1024_v, MATCH_VLOXEI1024_V, MASK_VLOXEI1024_V) +DECLARE_INSN(vloxei128_v, MATCH_VLOXEI128_V, MASK_VLOXEI128_V) +DECLARE_INSN(vloxei16_v, MATCH_VLOXEI16_V, MASK_VLOXEI16_V) +DECLARE_INSN(vloxei256_v, MATCH_VLOXEI256_V, MASK_VLOXEI256_V) +DECLARE_INSN(vloxei32_v, MATCH_VLOXEI32_V, MASK_VLOXEI32_V) +DECLARE_INSN(vloxei512_v, MATCH_VLOXEI512_V, MASK_VLOXEI512_V) +DECLARE_INSN(vloxei64_v, MATCH_VLOXEI64_V, MASK_VLOXEI64_V) +DECLARE_INSN(vloxei8_v, MATCH_VLOXEI8_V, MASK_VLOXEI8_V) +DECLARE_INSN(vlse1024_v, MATCH_VLSE1024_V, MASK_VLSE1024_V) +DECLARE_INSN(vlse128_v, MATCH_VLSE128_V, MASK_VLSE128_V) +DECLARE_INSN(vlse16_v, MATCH_VLSE16_V, MASK_VLSE16_V) +DECLARE_INSN(vlse256_v, MATCH_VLSE256_V, MASK_VLSE256_V) +DECLARE_INSN(vlse32_v, MATCH_VLSE32_V, MASK_VLSE32_V) +DECLARE_INSN(vlse512_v, MATCH_VLSE512_V, MASK_VLSE512_V) +DECLARE_INSN(vlse64_v, MATCH_VLSE64_V, MASK_VLSE64_V) +DECLARE_INSN(vlse8_v, MATCH_VLSE8_V, MASK_VLSE8_V) +DECLARE_INSN(vluxei1024_v, MATCH_VLUXEI1024_V, MASK_VLUXEI1024_V) +DECLARE_INSN(vluxei128_v, MATCH_VLUXEI128_V, MASK_VLUXEI128_V) +DECLARE_INSN(vluxei16_v, MATCH_VLUXEI16_V, MASK_VLUXEI16_V) +DECLARE_INSN(vluxei256_v, MATCH_VLUXEI256_V, MASK_VLUXEI256_V) +DECLARE_INSN(vluxei32_v, MATCH_VLUXEI32_V, MASK_VLUXEI32_V) +DECLARE_INSN(vluxei512_v, MATCH_VLUXEI512_V, MASK_VLUXEI512_V) +DECLARE_INSN(vluxei64_v, MATCH_VLUXEI64_V, MASK_VLUXEI64_V) +DECLARE_INSN(vluxei8_v, MATCH_VLUXEI8_V, MASK_VLUXEI8_V) +DECLARE_INSN(vmacc_vv, MATCH_VMACC_VV, MASK_VMACC_VV) +DECLARE_INSN(vmacc_vx, MATCH_VMACC_VX, MASK_VMACC_VX) +DECLARE_INSN(vmadc_vi, MATCH_VMADC_VI, MASK_VMADC_VI) +DECLARE_INSN(vmadc_vim, MATCH_VMADC_VIM, MASK_VMADC_VIM) +DECLARE_INSN(vmadc_vv, MATCH_VMADC_VV, MASK_VMADC_VV) +DECLARE_INSN(vmadc_vvm, MATCH_VMADC_VVM, MASK_VMADC_VVM) +DECLARE_INSN(vmadc_vx, MATCH_VMADC_VX, MASK_VMADC_VX) +DECLARE_INSN(vmadc_vxm, MATCH_VMADC_VXM, MASK_VMADC_VXM) +DECLARE_INSN(vmadd_vv, MATCH_VMADD_VV, MASK_VMADD_VV) +DECLARE_INSN(vmadd_vx, MATCH_VMADD_VX, MASK_VMADD_VX) +DECLARE_INSN(vmand_mm, MATCH_VMAND_MM, MASK_VMAND_MM) +DECLARE_INSN(vmandn_mm, MATCH_VMANDN_MM, MASK_VMANDN_MM) +DECLARE_INSN(vmax_vv, MATCH_VMAX_VV, MASK_VMAX_VV) +DECLARE_INSN(vmax_vx, MATCH_VMAX_VX, MASK_VMAX_VX) +DECLARE_INSN(vmaxu_vv, MATCH_VMAXU_VV, MASK_VMAXU_VV) +DECLARE_INSN(vmaxu_vx, MATCH_VMAXU_VX, MASK_VMAXU_VX) +DECLARE_INSN(vmerge_vim, MATCH_VMERGE_VIM, MASK_VMERGE_VIM) +DECLARE_INSN(vmerge_vvm, MATCH_VMERGE_VVM, MASK_VMERGE_VVM) +DECLARE_INSN(vmerge_vxm, MATCH_VMERGE_VXM, MASK_VMERGE_VXM) +DECLARE_INSN(vmfeq_vf, MATCH_VMFEQ_VF, MASK_VMFEQ_VF) +DECLARE_INSN(vmfeq_vv, MATCH_VMFEQ_VV, MASK_VMFEQ_VV) +DECLARE_INSN(vmfge_vf, MATCH_VMFGE_VF, MASK_VMFGE_VF) +DECLARE_INSN(vmfgt_vf, MATCH_VMFGT_VF, MASK_VMFGT_VF) +DECLARE_INSN(vmfle_vf, MATCH_VMFLE_VF, MASK_VMFLE_VF) +DECLARE_INSN(vmfle_vv, MATCH_VMFLE_VV, MASK_VMFLE_VV) +DECLARE_INSN(vmflt_vf, MATCH_VMFLT_VF, MASK_VMFLT_VF) +DECLARE_INSN(vmflt_vv, MATCH_VMFLT_VV, MASK_VMFLT_VV) +DECLARE_INSN(vmfne_vf, MATCH_VMFNE_VF, MASK_VMFNE_VF) +DECLARE_INSN(vmfne_vv, MATCH_VMFNE_VV, MASK_VMFNE_VV) +DECLARE_INSN(vmin_vv, MATCH_VMIN_VV, MASK_VMIN_VV) +DECLARE_INSN(vmin_vx, MATCH_VMIN_VX, MASK_VMIN_VX) +DECLARE_INSN(vminu_vv, MATCH_VMINU_VV, MASK_VMINU_VV) +DECLARE_INSN(vminu_vx, MATCH_VMINU_VX, MASK_VMINU_VX) +DECLARE_INSN(vmnand_mm, MATCH_VMNAND_MM, MASK_VMNAND_MM) +DECLARE_INSN(vmnor_mm, MATCH_VMNOR_MM, MASK_VMNOR_MM) +DECLARE_INSN(vmor_mm, MATCH_VMOR_MM, MASK_VMOR_MM) +DECLARE_INSN(vmorn_mm, MATCH_VMORN_MM, MASK_VMORN_MM) +DECLARE_INSN(vmsbc_vv, MATCH_VMSBC_VV, MASK_VMSBC_VV) +DECLARE_INSN(vmsbc_vvm, MATCH_VMSBC_VVM, MASK_VMSBC_VVM) +DECLARE_INSN(vmsbc_vx, MATCH_VMSBC_VX, MASK_VMSBC_VX) +DECLARE_INSN(vmsbc_vxm, MATCH_VMSBC_VXM, MASK_VMSBC_VXM) +DECLARE_INSN(vmsbf_m, MATCH_VMSBF_M, MASK_VMSBF_M) +DECLARE_INSN(vmseq_vi, MATCH_VMSEQ_VI, MASK_VMSEQ_VI) +DECLARE_INSN(vmseq_vv, MATCH_VMSEQ_VV, MASK_VMSEQ_VV) +DECLARE_INSN(vmseq_vx, MATCH_VMSEQ_VX, MASK_VMSEQ_VX) +DECLARE_INSN(vmsgt_vi, MATCH_VMSGT_VI, MASK_VMSGT_VI) +DECLARE_INSN(vmsgt_vx, MATCH_VMSGT_VX, MASK_VMSGT_VX) +DECLARE_INSN(vmsgtu_vi, MATCH_VMSGTU_VI, MASK_VMSGTU_VI) +DECLARE_INSN(vmsgtu_vx, MATCH_VMSGTU_VX, MASK_VMSGTU_VX) +DECLARE_INSN(vmsif_m, MATCH_VMSIF_M, MASK_VMSIF_M) +DECLARE_INSN(vmsle_vi, MATCH_VMSLE_VI, MASK_VMSLE_VI) +DECLARE_INSN(vmsle_vv, MATCH_VMSLE_VV, MASK_VMSLE_VV) +DECLARE_INSN(vmsle_vx, MATCH_VMSLE_VX, MASK_VMSLE_VX) +DECLARE_INSN(vmsleu_vi, MATCH_VMSLEU_VI, MASK_VMSLEU_VI) +DECLARE_INSN(vmsleu_vv, MATCH_VMSLEU_VV, MASK_VMSLEU_VV) +DECLARE_INSN(vmsleu_vx, MATCH_VMSLEU_VX, MASK_VMSLEU_VX) +DECLARE_INSN(vmslt_vv, MATCH_VMSLT_VV, MASK_VMSLT_VV) +DECLARE_INSN(vmslt_vx, MATCH_VMSLT_VX, MASK_VMSLT_VX) +DECLARE_INSN(vmsltu_vv, MATCH_VMSLTU_VV, MASK_VMSLTU_VV) +DECLARE_INSN(vmsltu_vx, MATCH_VMSLTU_VX, MASK_VMSLTU_VX) +DECLARE_INSN(vmsne_vi, MATCH_VMSNE_VI, MASK_VMSNE_VI) +DECLARE_INSN(vmsne_vv, MATCH_VMSNE_VV, MASK_VMSNE_VV) +DECLARE_INSN(vmsne_vx, MATCH_VMSNE_VX, MASK_VMSNE_VX) +DECLARE_INSN(vmsof_m, MATCH_VMSOF_M, MASK_VMSOF_M) +DECLARE_INSN(vmul_vv, MATCH_VMUL_VV, MASK_VMUL_VV) +DECLARE_INSN(vmul_vx, MATCH_VMUL_VX, MASK_VMUL_VX) +DECLARE_INSN(vmulh_vv, MATCH_VMULH_VV, MASK_VMULH_VV) +DECLARE_INSN(vmulh_vx, MATCH_VMULH_VX, MASK_VMULH_VX) +DECLARE_INSN(vmulhsu_vv, MATCH_VMULHSU_VV, MASK_VMULHSU_VV) +DECLARE_INSN(vmulhsu_vx, MATCH_VMULHSU_VX, MASK_VMULHSU_VX) +DECLARE_INSN(vmulhu_vv, MATCH_VMULHU_VV, MASK_VMULHU_VV) +DECLARE_INSN(vmulhu_vx, MATCH_VMULHU_VX, MASK_VMULHU_VX) +DECLARE_INSN(vmv1r_v, MATCH_VMV1R_V, MASK_VMV1R_V) +DECLARE_INSN(vmv2r_v, MATCH_VMV2R_V, MASK_VMV2R_V) +DECLARE_INSN(vmv4r_v, MATCH_VMV4R_V, MASK_VMV4R_V) +DECLARE_INSN(vmv8r_v, MATCH_VMV8R_V, MASK_VMV8R_V) +DECLARE_INSN(vmv_s_x, MATCH_VMV_S_X, MASK_VMV_S_X) +DECLARE_INSN(vmv_v_i, MATCH_VMV_V_I, MASK_VMV_V_I) +DECLARE_INSN(vmv_v_v, MATCH_VMV_V_V, MASK_VMV_V_V) +DECLARE_INSN(vmv_v_x, MATCH_VMV_V_X, MASK_VMV_V_X) +DECLARE_INSN(vmv_x_s, MATCH_VMV_X_S, MASK_VMV_X_S) +DECLARE_INSN(vmxnor_mm, MATCH_VMXNOR_MM, MASK_VMXNOR_MM) +DECLARE_INSN(vmxor_mm, MATCH_VMXOR_MM, MASK_VMXOR_MM) +DECLARE_INSN(vnclip_wi, MATCH_VNCLIP_WI, MASK_VNCLIP_WI) +DECLARE_INSN(vnclip_wv, MATCH_VNCLIP_WV, MASK_VNCLIP_WV) +DECLARE_INSN(vnclip_wx, MATCH_VNCLIP_WX, MASK_VNCLIP_WX) +DECLARE_INSN(vnclipu_wi, MATCH_VNCLIPU_WI, MASK_VNCLIPU_WI) +DECLARE_INSN(vnclipu_wv, MATCH_VNCLIPU_WV, MASK_VNCLIPU_WV) +DECLARE_INSN(vnclipu_wx, MATCH_VNCLIPU_WX, MASK_VNCLIPU_WX) +DECLARE_INSN(vnmsac_vv, MATCH_VNMSAC_VV, MASK_VNMSAC_VV) +DECLARE_INSN(vnmsac_vx, MATCH_VNMSAC_VX, MASK_VNMSAC_VX) +DECLARE_INSN(vnmsub_vv, MATCH_VNMSUB_VV, MASK_VNMSUB_VV) +DECLARE_INSN(vnmsub_vx, MATCH_VNMSUB_VX, MASK_VNMSUB_VX) +DECLARE_INSN(vnsra_wi, MATCH_VNSRA_WI, MASK_VNSRA_WI) +DECLARE_INSN(vnsra_wv, MATCH_VNSRA_WV, MASK_VNSRA_WV) +DECLARE_INSN(vnsra_wx, MATCH_VNSRA_WX, MASK_VNSRA_WX) +DECLARE_INSN(vnsrl_wi, MATCH_VNSRL_WI, MASK_VNSRL_WI) +DECLARE_INSN(vnsrl_wv, MATCH_VNSRL_WV, MASK_VNSRL_WV) +DECLARE_INSN(vnsrl_wx, MATCH_VNSRL_WX, MASK_VNSRL_WX) +DECLARE_INSN(vor_vi, MATCH_VOR_VI, MASK_VOR_VI) +DECLARE_INSN(vor_vv, MATCH_VOR_VV, MASK_VOR_VV) +DECLARE_INSN(vor_vx, MATCH_VOR_VX, MASK_VOR_VX) +DECLARE_INSN(vredand_vs, MATCH_VREDAND_VS, MASK_VREDAND_VS) +DECLARE_INSN(vredmax_vs, MATCH_VREDMAX_VS, MASK_VREDMAX_VS) +DECLARE_INSN(vredmaxu_vs, MATCH_VREDMAXU_VS, MASK_VREDMAXU_VS) +DECLARE_INSN(vredmin_vs, MATCH_VREDMIN_VS, MASK_VREDMIN_VS) +DECLARE_INSN(vredminu_vs, MATCH_VREDMINU_VS, MASK_VREDMINU_VS) +DECLARE_INSN(vredor_vs, MATCH_VREDOR_VS, MASK_VREDOR_VS) +DECLARE_INSN(vredsum_vs, MATCH_VREDSUM_VS, MASK_VREDSUM_VS) +DECLARE_INSN(vredxor_vs, MATCH_VREDXOR_VS, MASK_VREDXOR_VS) +DECLARE_INSN(vrem_vv, MATCH_VREM_VV, MASK_VREM_VV) +DECLARE_INSN(vrem_vx, MATCH_VREM_VX, MASK_VREM_VX) +DECLARE_INSN(vremu_vv, MATCH_VREMU_VV, MASK_VREMU_VV) +DECLARE_INSN(vremu_vx, MATCH_VREMU_VX, MASK_VREMU_VX) +DECLARE_INSN(vrgather_vi, MATCH_VRGATHER_VI, MASK_VRGATHER_VI) +DECLARE_INSN(vrgather_vv, MATCH_VRGATHER_VV, MASK_VRGATHER_VV) +DECLARE_INSN(vrgather_vx, MATCH_VRGATHER_VX, MASK_VRGATHER_VX) +DECLARE_INSN(vrgatherei16_vv, MATCH_VRGATHEREI16_VV, MASK_VRGATHEREI16_VV) +DECLARE_INSN(vrsub_vi, MATCH_VRSUB_VI, MASK_VRSUB_VI) +DECLARE_INSN(vrsub_vx, MATCH_VRSUB_VX, MASK_VRSUB_VX) +DECLARE_INSN(vs1r_v, MATCH_VS1R_V, MASK_VS1R_V) +DECLARE_INSN(vs2r_v, MATCH_VS2R_V, MASK_VS2R_V) +DECLARE_INSN(vs4r_v, MATCH_VS4R_V, MASK_VS4R_V) +DECLARE_INSN(vs8r_v, MATCH_VS8R_V, MASK_VS8R_V) +DECLARE_INSN(vsadd_vi, MATCH_VSADD_VI, MASK_VSADD_VI) +DECLARE_INSN(vsadd_vv, MATCH_VSADD_VV, MASK_VSADD_VV) +DECLARE_INSN(vsadd_vx, MATCH_VSADD_VX, MASK_VSADD_VX) +DECLARE_INSN(vsaddu_vi, MATCH_VSADDU_VI, MASK_VSADDU_VI) +DECLARE_INSN(vsaddu_vv, MATCH_VSADDU_VV, MASK_VSADDU_VV) +DECLARE_INSN(vsaddu_vx, MATCH_VSADDU_VX, MASK_VSADDU_VX) +DECLARE_INSN(vsbc_vvm, MATCH_VSBC_VVM, MASK_VSBC_VVM) +DECLARE_INSN(vsbc_vxm, MATCH_VSBC_VXM, MASK_VSBC_VXM) +DECLARE_INSN(vse1024_v, MATCH_VSE1024_V, MASK_VSE1024_V) +DECLARE_INSN(vse128_v, MATCH_VSE128_V, MASK_VSE128_V) +DECLARE_INSN(vse16_v, MATCH_VSE16_V, MASK_VSE16_V) +DECLARE_INSN(vse256_v, MATCH_VSE256_V, MASK_VSE256_V) +DECLARE_INSN(vse32_v, MATCH_VSE32_V, MASK_VSE32_V) +DECLARE_INSN(vse512_v, MATCH_VSE512_V, MASK_VSE512_V) +DECLARE_INSN(vse64_v, MATCH_VSE64_V, MASK_VSE64_V) +DECLARE_INSN(vse8_v, MATCH_VSE8_V, MASK_VSE8_V) +DECLARE_INSN(vsetivli, MATCH_VSETIVLI, MASK_VSETIVLI) +DECLARE_INSN(vsetvl, MATCH_VSETVL, MASK_VSETVL) +DECLARE_INSN(vsetvli, MATCH_VSETVLI, MASK_VSETVLI) +DECLARE_INSN(vsext_vf2, MATCH_VSEXT_VF2, MASK_VSEXT_VF2) +DECLARE_INSN(vsext_vf4, MATCH_VSEXT_VF4, MASK_VSEXT_VF4) +DECLARE_INSN(vsext_vf8, MATCH_VSEXT_VF8, MASK_VSEXT_VF8) +DECLARE_INSN(vslide1down_vx, MATCH_VSLIDE1DOWN_VX, MASK_VSLIDE1DOWN_VX) +DECLARE_INSN(vslide1up_vx, MATCH_VSLIDE1UP_VX, MASK_VSLIDE1UP_VX) +DECLARE_INSN(vslidedown_vi, MATCH_VSLIDEDOWN_VI, MASK_VSLIDEDOWN_VI) +DECLARE_INSN(vslidedown_vx, MATCH_VSLIDEDOWN_VX, MASK_VSLIDEDOWN_VX) +DECLARE_INSN(vslideup_vi, MATCH_VSLIDEUP_VI, MASK_VSLIDEUP_VI) +DECLARE_INSN(vslideup_vx, MATCH_VSLIDEUP_VX, MASK_VSLIDEUP_VX) +DECLARE_INSN(vsll_vi, MATCH_VSLL_VI, MASK_VSLL_VI) +DECLARE_INSN(vsll_vv, MATCH_VSLL_VV, MASK_VSLL_VV) +DECLARE_INSN(vsll_vx, MATCH_VSLL_VX, MASK_VSLL_VX) +DECLARE_INSN(vsm_v, MATCH_VSM_V, MASK_VSM_V) +DECLARE_INSN(vsmul_vv, MATCH_VSMUL_VV, MASK_VSMUL_VV) +DECLARE_INSN(vsmul_vx, MATCH_VSMUL_VX, MASK_VSMUL_VX) +DECLARE_INSN(vsoxei1024_v, MATCH_VSOXEI1024_V, MASK_VSOXEI1024_V) +DECLARE_INSN(vsoxei128_v, MATCH_VSOXEI128_V, MASK_VSOXEI128_V) +DECLARE_INSN(vsoxei16_v, MATCH_VSOXEI16_V, MASK_VSOXEI16_V) +DECLARE_INSN(vsoxei256_v, MATCH_VSOXEI256_V, MASK_VSOXEI256_V) +DECLARE_INSN(vsoxei32_v, MATCH_VSOXEI32_V, MASK_VSOXEI32_V) +DECLARE_INSN(vsoxei512_v, MATCH_VSOXEI512_V, MASK_VSOXEI512_V) +DECLARE_INSN(vsoxei64_v, MATCH_VSOXEI64_V, MASK_VSOXEI64_V) +DECLARE_INSN(vsoxei8_v, MATCH_VSOXEI8_V, MASK_VSOXEI8_V) +DECLARE_INSN(vsra_vi, MATCH_VSRA_VI, MASK_VSRA_VI) +DECLARE_INSN(vsra_vv, MATCH_VSRA_VV, MASK_VSRA_VV) +DECLARE_INSN(vsra_vx, MATCH_VSRA_VX, MASK_VSRA_VX) +DECLARE_INSN(vsrl_vi, MATCH_VSRL_VI, MASK_VSRL_VI) +DECLARE_INSN(vsrl_vv, MATCH_VSRL_VV, MASK_VSRL_VV) +DECLARE_INSN(vsrl_vx, MATCH_VSRL_VX, MASK_VSRL_VX) +DECLARE_INSN(vsse1024_v, MATCH_VSSE1024_V, MASK_VSSE1024_V) +DECLARE_INSN(vsse128_v, MATCH_VSSE128_V, MASK_VSSE128_V) +DECLARE_INSN(vsse16_v, MATCH_VSSE16_V, MASK_VSSE16_V) +DECLARE_INSN(vsse256_v, MATCH_VSSE256_V, MASK_VSSE256_V) +DECLARE_INSN(vsse32_v, MATCH_VSSE32_V, MASK_VSSE32_V) +DECLARE_INSN(vsse512_v, MATCH_VSSE512_V, MASK_VSSE512_V) +DECLARE_INSN(vsse64_v, MATCH_VSSE64_V, MASK_VSSE64_V) +DECLARE_INSN(vsse8_v, MATCH_VSSE8_V, MASK_VSSE8_V) +DECLARE_INSN(vssra_vi, MATCH_VSSRA_VI, MASK_VSSRA_VI) +DECLARE_INSN(vssra_vv, MATCH_VSSRA_VV, MASK_VSSRA_VV) +DECLARE_INSN(vssra_vx, MATCH_VSSRA_VX, MASK_VSSRA_VX) +DECLARE_INSN(vssrl_vi, MATCH_VSSRL_VI, MASK_VSSRL_VI) +DECLARE_INSN(vssrl_vv, MATCH_VSSRL_VV, MASK_VSSRL_VV) +DECLARE_INSN(vssrl_vx, MATCH_VSSRL_VX, MASK_VSSRL_VX) +DECLARE_INSN(vssub_vv, MATCH_VSSUB_VV, MASK_VSSUB_VV) +DECLARE_INSN(vssub_vx, MATCH_VSSUB_VX, MASK_VSSUB_VX) +DECLARE_INSN(vssubu_vv, MATCH_VSSUBU_VV, MASK_VSSUBU_VV) +DECLARE_INSN(vssubu_vx, MATCH_VSSUBU_VX, MASK_VSSUBU_VX) +DECLARE_INSN(vsub_vv, MATCH_VSUB_VV, MASK_VSUB_VV) +DECLARE_INSN(vsub_vx, MATCH_VSUB_VX, MASK_VSUB_VX) +DECLARE_INSN(vsuxei1024_v, MATCH_VSUXEI1024_V, MASK_VSUXEI1024_V) +DECLARE_INSN(vsuxei128_v, MATCH_VSUXEI128_V, MASK_VSUXEI128_V) +DECLARE_INSN(vsuxei16_v, MATCH_VSUXEI16_V, MASK_VSUXEI16_V) +DECLARE_INSN(vsuxei256_v, MATCH_VSUXEI256_V, MASK_VSUXEI256_V) +DECLARE_INSN(vsuxei32_v, MATCH_VSUXEI32_V, MASK_VSUXEI32_V) +DECLARE_INSN(vsuxei512_v, MATCH_VSUXEI512_V, MASK_VSUXEI512_V) +DECLARE_INSN(vsuxei64_v, MATCH_VSUXEI64_V, MASK_VSUXEI64_V) +DECLARE_INSN(vsuxei8_v, MATCH_VSUXEI8_V, MASK_VSUXEI8_V) +DECLARE_INSN(vwadd_vv, MATCH_VWADD_VV, MASK_VWADD_VV) +DECLARE_INSN(vwadd_vx, MATCH_VWADD_VX, MASK_VWADD_VX) +DECLARE_INSN(vwadd_wv, MATCH_VWADD_WV, MASK_VWADD_WV) +DECLARE_INSN(vwadd_wx, MATCH_VWADD_WX, MASK_VWADD_WX) +DECLARE_INSN(vwaddu_vv, MATCH_VWADDU_VV, MASK_VWADDU_VV) +DECLARE_INSN(vwaddu_vx, MATCH_VWADDU_VX, MASK_VWADDU_VX) +DECLARE_INSN(vwaddu_wv, MATCH_VWADDU_WV, MASK_VWADDU_WV) +DECLARE_INSN(vwaddu_wx, MATCH_VWADDU_WX, MASK_VWADDU_WX) +DECLARE_INSN(vwmacc_vv, MATCH_VWMACC_VV, MASK_VWMACC_VV) +DECLARE_INSN(vwmacc_vx, MATCH_VWMACC_VX, MASK_VWMACC_VX) +DECLARE_INSN(vwmaccsu_vv, MATCH_VWMACCSU_VV, MASK_VWMACCSU_VV) +DECLARE_INSN(vwmaccsu_vx, MATCH_VWMACCSU_VX, MASK_VWMACCSU_VX) +DECLARE_INSN(vwmaccu_vv, MATCH_VWMACCU_VV, MASK_VWMACCU_VV) +DECLARE_INSN(vwmaccu_vx, MATCH_VWMACCU_VX, MASK_VWMACCU_VX) +DECLARE_INSN(vwmaccus_vx, MATCH_VWMACCUS_VX, MASK_VWMACCUS_VX) +DECLARE_INSN(vwmul_vv, MATCH_VWMUL_VV, MASK_VWMUL_VV) +DECLARE_INSN(vwmul_vx, MATCH_VWMUL_VX, MASK_VWMUL_VX) +DECLARE_INSN(vwmulsu_vv, MATCH_VWMULSU_VV, MASK_VWMULSU_VV) +DECLARE_INSN(vwmulsu_vx, MATCH_VWMULSU_VX, MASK_VWMULSU_VX) +DECLARE_INSN(vwmulu_vv, MATCH_VWMULU_VV, MASK_VWMULU_VV) +DECLARE_INSN(vwmulu_vx, MATCH_VWMULU_VX, MASK_VWMULU_VX) +DECLARE_INSN(vwredsum_vs, MATCH_VWREDSUM_VS, MASK_VWREDSUM_VS) +DECLARE_INSN(vwredsumu_vs, MATCH_VWREDSUMU_VS, MASK_VWREDSUMU_VS) +DECLARE_INSN(vwsub_vv, MATCH_VWSUB_VV, MASK_VWSUB_VV) +DECLARE_INSN(vwsub_vx, MATCH_VWSUB_VX, MASK_VWSUB_VX) +DECLARE_INSN(vwsub_wv, MATCH_VWSUB_WV, MASK_VWSUB_WV) +DECLARE_INSN(vwsub_wx, MATCH_VWSUB_WX, MASK_VWSUB_WX) +DECLARE_INSN(vwsubu_vv, MATCH_VWSUBU_VV, MASK_VWSUBU_VV) +DECLARE_INSN(vwsubu_vx, MATCH_VWSUBU_VX, MASK_VWSUBU_VX) +DECLARE_INSN(vwsubu_wv, MATCH_VWSUBU_WV, MASK_VWSUBU_WV) +DECLARE_INSN(vwsubu_wx, MATCH_VWSUBU_WX, MASK_VWSUBU_WX) +DECLARE_INSN(vxor_vi, MATCH_VXOR_VI, MASK_VXOR_VI) +DECLARE_INSN(vxor_vv, MATCH_VXOR_VV, MASK_VXOR_VV) +DECLARE_INSN(vxor_vx, MATCH_VXOR_VX, MASK_VXOR_VX) +DECLARE_INSN(vzext_vf2, MATCH_VZEXT_VF2, MASK_VZEXT_VF2) +DECLARE_INSN(vzext_vf4, MATCH_VZEXT_VF4, MASK_VZEXT_VF4) +DECLARE_INSN(vzext_vf8, MATCH_VZEXT_VF8, MASK_VZEXT_VF8) +DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) +DECLARE_INSN(wrs_nto, MATCH_WRS_NTO, MASK_WRS_NTO) +DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO) +DECLARE_INSN(xnor, MATCH_XNOR, MASK_XNOR) +DECLARE_INSN(xor, MATCH_XOR, MASK_XOR) +DECLARE_INSN(xori, MATCH_XORI, MASK_XORI) +DECLARE_INSN(xperm16, MATCH_XPERM16, MASK_XPERM16) +DECLARE_INSN(xperm32, MATCH_XPERM32, MASK_XPERM32) +DECLARE_INSN(xperm4, MATCH_XPERM4, MASK_XPERM4) +DECLARE_INSN(xperm8, MATCH_XPERM8, MASK_XPERM8) +DECLARE_INSN(zunpkd810, MATCH_ZUNPKD810, MASK_ZUNPKD810) +DECLARE_INSN(zunpkd820, MATCH_ZUNPKD820, MASK_ZUNPKD820) +DECLARE_INSN(zunpkd830, MATCH_ZUNPKD830, MASK_ZUNPKD830) +DECLARE_INSN(zunpkd831, MATCH_ZUNPKD831, MASK_ZUNPKD831) +DECLARE_INSN(zunpkd832, MATCH_ZUNPKD832, MASK_ZUNPKD832) +#endif +#ifdef DECLARE_CSR +DECLARE_CSR(fflags, CSR_FFLAGS) +DECLARE_CSR(frm, CSR_FRM) +DECLARE_CSR(fcsr, CSR_FCSR) +DECLARE_CSR(vstart, CSR_VSTART) +DECLARE_CSR(vxsat, CSR_VXSAT) +DECLARE_CSR(vxrm, CSR_VXRM) +DECLARE_CSR(vcsr, CSR_VCSR) +DECLARE_CSR(seed, CSR_SEED) +DECLARE_CSR(jvt, CSR_JVT) +DECLARE_CSR(cycle, CSR_CYCLE) +DECLARE_CSR(time, CSR_TIME) +DECLARE_CSR(instret, CSR_INSTRET) +DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3) +DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4) +DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5) +DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6) +DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7) +DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8) +DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9) +DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10) +DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11) +DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12) +DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13) +DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14) +DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15) +DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16) +DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17) +DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18) +DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19) +DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20) +DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21) +DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22) +DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23) +DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24) +DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25) +DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26) +DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27) +DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28) +DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29) +DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30) +DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31) +DECLARE_CSR(vl, CSR_VL) +DECLARE_CSR(vtype, CSR_VTYPE) +DECLARE_CSR(vlenb, CSR_VLENB) +DECLARE_CSR(sstatus, CSR_SSTATUS) +DECLARE_CSR(sedeleg, CSR_SEDELEG) +DECLARE_CSR(sideleg, CSR_SIDELEG) +DECLARE_CSR(sie, CSR_SIE) +DECLARE_CSR(stvec, CSR_STVEC) +DECLARE_CSR(scounteren, CSR_SCOUNTEREN) +DECLARE_CSR(senvcfg, CSR_SENVCFG) +DECLARE_CSR(sstateen0, CSR_SSTATEEN0) +DECLARE_CSR(sstateen1, CSR_SSTATEEN1) +DECLARE_CSR(sstateen2, CSR_SSTATEEN2) +DECLARE_CSR(sstateen3, CSR_SSTATEEN3) +DECLARE_CSR(sscratch, CSR_SSCRATCH) +DECLARE_CSR(sepc, CSR_SEPC) +DECLARE_CSR(scause, CSR_SCAUSE) +DECLARE_CSR(stval, CSR_STVAL) +DECLARE_CSR(sip, CSR_SIP) +DECLARE_CSR(stimecmp, CSR_STIMECMP) +DECLARE_CSR(siselect, CSR_SISELECT) +DECLARE_CSR(sireg, CSR_SIREG) +DECLARE_CSR(stopei, CSR_STOPEI) +DECLARE_CSR(satp, CSR_SATP) +DECLARE_CSR(scontext, CSR_SCONTEXT) +DECLARE_CSR(vsstatus, CSR_VSSTATUS) +DECLARE_CSR(vsie, CSR_VSIE) +DECLARE_CSR(vstvec, CSR_VSTVEC) +DECLARE_CSR(vsscratch, CSR_VSSCRATCH) +DECLARE_CSR(vsepc, CSR_VSEPC) +DECLARE_CSR(vscause, CSR_VSCAUSE) +DECLARE_CSR(vstval, CSR_VSTVAL) +DECLARE_CSR(vsip, CSR_VSIP) +DECLARE_CSR(vstimecmp, CSR_VSTIMECMP) +DECLARE_CSR(vsiselect, CSR_VSISELECT) +DECLARE_CSR(vsireg, CSR_VSIREG) +DECLARE_CSR(vstopei, CSR_VSTOPEI) +DECLARE_CSR(vsatp, CSR_VSATP) +DECLARE_CSR(hstatus, CSR_HSTATUS) +DECLARE_CSR(hedeleg, CSR_HEDELEG) +DECLARE_CSR(hideleg, CSR_HIDELEG) +DECLARE_CSR(hie, CSR_HIE) +DECLARE_CSR(htimedelta, CSR_HTIMEDELTA) +DECLARE_CSR(hcounteren, CSR_HCOUNTEREN) +DECLARE_CSR(hgeie, CSR_HGEIE) +DECLARE_CSR(hvien, CSR_HVIEN) +DECLARE_CSR(hvictl, CSR_HVICTL) +DECLARE_CSR(henvcfg, CSR_HENVCFG) +DECLARE_CSR(hstateen0, CSR_HSTATEEN0) +DECLARE_CSR(hstateen1, CSR_HSTATEEN1) +DECLARE_CSR(hstateen2, CSR_HSTATEEN2) +DECLARE_CSR(hstateen3, CSR_HSTATEEN3) +DECLARE_CSR(htval, CSR_HTVAL) +DECLARE_CSR(hip, CSR_HIP) +DECLARE_CSR(hvip, CSR_HVIP) +DECLARE_CSR(hviprio1, CSR_HVIPRIO1) +DECLARE_CSR(hviprio2, CSR_HVIPRIO2) +DECLARE_CSR(htinst, CSR_HTINST) +DECLARE_CSR(hgatp, CSR_HGATP) +DECLARE_CSR(hcontext, CSR_HCONTEXT) +DECLARE_CSR(hgeip, CSR_HGEIP) +DECLARE_CSR(vstopi, CSR_VSTOPI) +DECLARE_CSR(scountovf, CSR_SCOUNTOVF) +DECLARE_CSR(stopi, CSR_STOPI) +DECLARE_CSR(utvt, CSR_UTVT) +DECLARE_CSR(unxti, CSR_UNXTI) +DECLARE_CSR(uintstatus, CSR_UINTSTATUS) +DECLARE_CSR(uscratchcsw, CSR_USCRATCHCSW) +DECLARE_CSR(uscratchcswl, CSR_USCRATCHCSWL) +DECLARE_CSR(stvt, CSR_STVT) +DECLARE_CSR(snxti, CSR_SNXTI) +DECLARE_CSR(sintstatus, CSR_SINTSTATUS) +DECLARE_CSR(sscratchcsw, CSR_SSCRATCHCSW) +DECLARE_CSR(sscratchcswl, CSR_SSCRATCHCSWL) +DECLARE_CSR(mtvt, CSR_MTVT) +DECLARE_CSR(mnxti, CSR_MNXTI) +DECLARE_CSR(mintstatus, CSR_MINTSTATUS) +DECLARE_CSR(mscratchcsw, CSR_MSCRATCHCSW) +DECLARE_CSR(mscratchcswl, CSR_MSCRATCHCSWL) +DECLARE_CSR(mstatus, CSR_MSTATUS) +DECLARE_CSR(misa, CSR_MISA) +DECLARE_CSR(medeleg, CSR_MEDELEG) +DECLARE_CSR(mideleg, CSR_MIDELEG) +DECLARE_CSR(mie, CSR_MIE) +DECLARE_CSR(mtvec, CSR_MTVEC) +DECLARE_CSR(mcounteren, CSR_MCOUNTEREN) +DECLARE_CSR(mvien, CSR_MVIEN) +DECLARE_CSR(mvip, CSR_MVIP) +DECLARE_CSR(menvcfg, CSR_MENVCFG) +DECLARE_CSR(mstateen0, CSR_MSTATEEN0) +DECLARE_CSR(mstateen1, CSR_MSTATEEN1) +DECLARE_CSR(mstateen2, CSR_MSTATEEN2) +DECLARE_CSR(mstateen3, CSR_MSTATEEN3) +DECLARE_CSR(mcountinhibit, CSR_MCOUNTINHIBIT) +DECLARE_CSR(mscratch, CSR_MSCRATCH) +DECLARE_CSR(mepc, CSR_MEPC) +DECLARE_CSR(mcause, CSR_MCAUSE) +DECLARE_CSR(mtval, CSR_MTVAL) +DECLARE_CSR(mip, CSR_MIP) +DECLARE_CSR(mtinst, CSR_MTINST) +DECLARE_CSR(mtval2, CSR_MTVAL2) +DECLARE_CSR(miselect, CSR_MISELECT) +DECLARE_CSR(mireg, CSR_MIREG) +DECLARE_CSR(mtopei, CSR_MTOPEI) +DECLARE_CSR(pmpcfg0, CSR_PMPCFG0) +DECLARE_CSR(pmpcfg1, CSR_PMPCFG1) +DECLARE_CSR(pmpcfg2, CSR_PMPCFG2) +DECLARE_CSR(pmpcfg3, CSR_PMPCFG3) +DECLARE_CSR(pmpcfg4, CSR_PMPCFG4) +DECLARE_CSR(pmpcfg5, CSR_PMPCFG5) +DECLARE_CSR(pmpcfg6, CSR_PMPCFG6) +DECLARE_CSR(pmpcfg7, CSR_PMPCFG7) +DECLARE_CSR(pmpcfg8, CSR_PMPCFG8) +DECLARE_CSR(pmpcfg9, CSR_PMPCFG9) +DECLARE_CSR(pmpcfg10, CSR_PMPCFG10) +DECLARE_CSR(pmpcfg11, CSR_PMPCFG11) +DECLARE_CSR(pmpcfg12, CSR_PMPCFG12) +DECLARE_CSR(pmpcfg13, CSR_PMPCFG13) +DECLARE_CSR(pmpcfg14, CSR_PMPCFG14) +DECLARE_CSR(pmpcfg15, CSR_PMPCFG15) +DECLARE_CSR(pmpaddr0, CSR_PMPADDR0) +DECLARE_CSR(pmpaddr1, CSR_PMPADDR1) +DECLARE_CSR(pmpaddr2, CSR_PMPADDR2) +DECLARE_CSR(pmpaddr3, CSR_PMPADDR3) +DECLARE_CSR(pmpaddr4, CSR_PMPADDR4) +DECLARE_CSR(pmpaddr5, CSR_PMPADDR5) +DECLARE_CSR(pmpaddr6, CSR_PMPADDR6) +DECLARE_CSR(pmpaddr7, CSR_PMPADDR7) +DECLARE_CSR(pmpaddr8, CSR_PMPADDR8) +DECLARE_CSR(pmpaddr9, CSR_PMPADDR9) +DECLARE_CSR(pmpaddr10, CSR_PMPADDR10) +DECLARE_CSR(pmpaddr11, CSR_PMPADDR11) +DECLARE_CSR(pmpaddr12, CSR_PMPADDR12) +DECLARE_CSR(pmpaddr13, CSR_PMPADDR13) +DECLARE_CSR(pmpaddr14, CSR_PMPADDR14) +DECLARE_CSR(pmpaddr15, CSR_PMPADDR15) +DECLARE_CSR(pmpaddr16, CSR_PMPADDR16) +DECLARE_CSR(pmpaddr17, CSR_PMPADDR17) +DECLARE_CSR(pmpaddr18, CSR_PMPADDR18) +DECLARE_CSR(pmpaddr19, CSR_PMPADDR19) +DECLARE_CSR(pmpaddr20, CSR_PMPADDR20) +DECLARE_CSR(pmpaddr21, CSR_PMPADDR21) +DECLARE_CSR(pmpaddr22, CSR_PMPADDR22) +DECLARE_CSR(pmpaddr23, CSR_PMPADDR23) +DECLARE_CSR(pmpaddr24, CSR_PMPADDR24) +DECLARE_CSR(pmpaddr25, CSR_PMPADDR25) +DECLARE_CSR(pmpaddr26, CSR_PMPADDR26) +DECLARE_CSR(pmpaddr27, CSR_PMPADDR27) +DECLARE_CSR(pmpaddr28, CSR_PMPADDR28) +DECLARE_CSR(pmpaddr29, CSR_PMPADDR29) +DECLARE_CSR(pmpaddr30, CSR_PMPADDR30) +DECLARE_CSR(pmpaddr31, CSR_PMPADDR31) +DECLARE_CSR(pmpaddr32, CSR_PMPADDR32) +DECLARE_CSR(pmpaddr33, CSR_PMPADDR33) +DECLARE_CSR(pmpaddr34, CSR_PMPADDR34) +DECLARE_CSR(pmpaddr35, CSR_PMPADDR35) +DECLARE_CSR(pmpaddr36, CSR_PMPADDR36) +DECLARE_CSR(pmpaddr37, CSR_PMPADDR37) +DECLARE_CSR(pmpaddr38, CSR_PMPADDR38) +DECLARE_CSR(pmpaddr39, CSR_PMPADDR39) +DECLARE_CSR(pmpaddr40, CSR_PMPADDR40) +DECLARE_CSR(pmpaddr41, CSR_PMPADDR41) +DECLARE_CSR(pmpaddr42, CSR_PMPADDR42) +DECLARE_CSR(pmpaddr43, CSR_PMPADDR43) +DECLARE_CSR(pmpaddr44, CSR_PMPADDR44) +DECLARE_CSR(pmpaddr45, CSR_PMPADDR45) +DECLARE_CSR(pmpaddr46, CSR_PMPADDR46) +DECLARE_CSR(pmpaddr47, CSR_PMPADDR47) +DECLARE_CSR(pmpaddr48, CSR_PMPADDR48) +DECLARE_CSR(pmpaddr49, CSR_PMPADDR49) +DECLARE_CSR(pmpaddr50, CSR_PMPADDR50) +DECLARE_CSR(pmpaddr51, CSR_PMPADDR51) +DECLARE_CSR(pmpaddr52, CSR_PMPADDR52) +DECLARE_CSR(pmpaddr53, CSR_PMPADDR53) +DECLARE_CSR(pmpaddr54, CSR_PMPADDR54) +DECLARE_CSR(pmpaddr55, CSR_PMPADDR55) +DECLARE_CSR(pmpaddr56, CSR_PMPADDR56) +DECLARE_CSR(pmpaddr57, CSR_PMPADDR57) +DECLARE_CSR(pmpaddr58, CSR_PMPADDR58) +DECLARE_CSR(pmpaddr59, CSR_PMPADDR59) +DECLARE_CSR(pmpaddr60, CSR_PMPADDR60) +DECLARE_CSR(pmpaddr61, CSR_PMPADDR61) +DECLARE_CSR(pmpaddr62, CSR_PMPADDR62) +DECLARE_CSR(pmpaddr63, CSR_PMPADDR63) +DECLARE_CSR(mseccfg, CSR_MSECCFG) +DECLARE_CSR(tselect, CSR_TSELECT) +DECLARE_CSR(tdata1, CSR_TDATA1) +DECLARE_CSR(tdata2, CSR_TDATA2) +DECLARE_CSR(tdata3, CSR_TDATA3) +DECLARE_CSR(tinfo, CSR_TINFO) +DECLARE_CSR(tcontrol, CSR_TCONTROL) +DECLARE_CSR(mcontext, CSR_MCONTEXT) +DECLARE_CSR(mscontext, CSR_MSCONTEXT) +DECLARE_CSR(dcsr, CSR_DCSR) +DECLARE_CSR(dpc, CSR_DPC) +DECLARE_CSR(dscratch0, CSR_DSCRATCH0) +DECLARE_CSR(dscratch1, CSR_DSCRATCH1) +DECLARE_CSR(mcycle, CSR_MCYCLE) +DECLARE_CSR(minstret, CSR_MINSTRET) +DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3) +DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4) +DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5) +DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6) +DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7) +DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8) +DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9) +DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10) +DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11) +DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12) +DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13) +DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14) +DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15) +DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16) +DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17) +DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18) +DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19) +DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20) +DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21) +DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22) +DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23) +DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24) +DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25) +DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26) +DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27) +DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28) +DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29) +DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30) +DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31) +DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3) +DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4) +DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5) +DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6) +DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7) +DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8) +DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9) +DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10) +DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11) +DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12) +DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13) +DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14) +DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15) +DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16) +DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17) +DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18) +DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19) +DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20) +DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21) +DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22) +DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23) +DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24) +DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25) +DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26) +DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27) +DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28) +DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29) +DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30) +DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31) +DECLARE_CSR(mvendorid, CSR_MVENDORID) +DECLARE_CSR(marchid, CSR_MARCHID) +DECLARE_CSR(mimpid, CSR_MIMPID) +DECLARE_CSR(mhartid, CSR_MHARTID) +DECLARE_CSR(mconfigptr, CSR_MCONFIGPTR) +DECLARE_CSR(mtopi, CSR_MTOPI) +DECLARE_CSR(sieh, CSR_SIEH) +DECLARE_CSR(siph, CSR_SIPH) +DECLARE_CSR(stimecmph, CSR_STIMECMPH) +DECLARE_CSR(vsieh, CSR_VSIEH) +DECLARE_CSR(vsiph, CSR_VSIPH) +DECLARE_CSR(vstimecmph, CSR_VSTIMECMPH) +DECLARE_CSR(htimedeltah, CSR_HTIMEDELTAH) +DECLARE_CSR(hidelegh, CSR_HIDELEGH) +DECLARE_CSR(hvienh, CSR_HVIENH) +DECLARE_CSR(henvcfgh, CSR_HENVCFGH) +DECLARE_CSR(hviph, CSR_HVIPH) +DECLARE_CSR(hviprio1h, CSR_HVIPRIO1H) +DECLARE_CSR(hviprio2h, CSR_HVIPRIO2H) +DECLARE_CSR(hstateen0h, CSR_HSTATEEN0H) +DECLARE_CSR(hstateen1h, CSR_HSTATEEN1H) +DECLARE_CSR(hstateen2h, CSR_HSTATEEN2H) +DECLARE_CSR(hstateen3h, CSR_HSTATEEN3H) +DECLARE_CSR(cycleh, CSR_CYCLEH) +DECLARE_CSR(timeh, CSR_TIMEH) +DECLARE_CSR(instreth, CSR_INSTRETH) +DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H) +DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H) +DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H) +DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H) +DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H) +DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H) +DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H) +DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H) +DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H) +DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H) +DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H) +DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H) +DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H) +DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H) +DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H) +DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H) +DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H) +DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H) +DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H) +DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H) +DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H) +DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H) +DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H) +DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H) +DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H) +DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H) +DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H) +DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H) +DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H) +DECLARE_CSR(mstatush, CSR_MSTATUSH) +DECLARE_CSR(midelegh, CSR_MIDELEGH) +DECLARE_CSR(mieh, CSR_MIEH) +DECLARE_CSR(mvienh, CSR_MVIENH) +DECLARE_CSR(mviph, CSR_MVIPH) +DECLARE_CSR(menvcfgh, CSR_MENVCFGH) +DECLARE_CSR(mstateen0h, CSR_MSTATEEN0H) +DECLARE_CSR(mstateen1h, CSR_MSTATEEN1H) +DECLARE_CSR(mstateen2h, CSR_MSTATEEN2H) +DECLARE_CSR(mstateen3h, CSR_MSTATEEN3H) +DECLARE_CSR(miph, CSR_MIPH) +DECLARE_CSR(mhpmevent3h, CSR_MHPMEVENT3H) +DECLARE_CSR(mhpmevent4h, CSR_MHPMEVENT4H) +DECLARE_CSR(mhpmevent5h, CSR_MHPMEVENT5H) +DECLARE_CSR(mhpmevent6h, CSR_MHPMEVENT6H) +DECLARE_CSR(mhpmevent7h, CSR_MHPMEVENT7H) +DECLARE_CSR(mhpmevent8h, CSR_MHPMEVENT8H) +DECLARE_CSR(mhpmevent9h, CSR_MHPMEVENT9H) +DECLARE_CSR(mhpmevent10h, CSR_MHPMEVENT10H) +DECLARE_CSR(mhpmevent11h, CSR_MHPMEVENT11H) +DECLARE_CSR(mhpmevent12h, CSR_MHPMEVENT12H) +DECLARE_CSR(mhpmevent13h, CSR_MHPMEVENT13H) +DECLARE_CSR(mhpmevent14h, CSR_MHPMEVENT14H) +DECLARE_CSR(mhpmevent15h, CSR_MHPMEVENT15H) +DECLARE_CSR(mhpmevent16h, CSR_MHPMEVENT16H) +DECLARE_CSR(mhpmevent17h, CSR_MHPMEVENT17H) +DECLARE_CSR(mhpmevent18h, CSR_MHPMEVENT18H) +DECLARE_CSR(mhpmevent19h, CSR_MHPMEVENT19H) +DECLARE_CSR(mhpmevent20h, CSR_MHPMEVENT20H) +DECLARE_CSR(mhpmevent21h, CSR_MHPMEVENT21H) +DECLARE_CSR(mhpmevent22h, CSR_MHPMEVENT22H) +DECLARE_CSR(mhpmevent23h, CSR_MHPMEVENT23H) +DECLARE_CSR(mhpmevent24h, CSR_MHPMEVENT24H) +DECLARE_CSR(mhpmevent25h, CSR_MHPMEVENT25H) +DECLARE_CSR(mhpmevent26h, CSR_MHPMEVENT26H) +DECLARE_CSR(mhpmevent27h, CSR_MHPMEVENT27H) +DECLARE_CSR(mhpmevent28h, CSR_MHPMEVENT28H) +DECLARE_CSR(mhpmevent29h, CSR_MHPMEVENT29H) +DECLARE_CSR(mhpmevent30h, CSR_MHPMEVENT30H) +DECLARE_CSR(mhpmevent31h, CSR_MHPMEVENT31H) +DECLARE_CSR(mnscratch, CSR_MNSCRATCH) +DECLARE_CSR(mnepc, CSR_MNEPC) +DECLARE_CSR(mncause, CSR_MNCAUSE) +DECLARE_CSR(mnstatus, CSR_MNSTATUS) +DECLARE_CSR(mseccfgh, CSR_MSECCFGH) +DECLARE_CSR(mcycleh, CSR_MCYCLEH) +DECLARE_CSR(minstreth, CSR_MINSTRETH) +DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H) +DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H) +DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H) +DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H) +DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H) +DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H) +DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H) +DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H) +DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H) +DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H) +DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H) +DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H) +DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H) +DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H) +DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H) +DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H) +DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H) +DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H) +DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H) +DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H) +DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H) +DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H) +DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H) +DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H) +DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H) +DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H) +DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H) +DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H) +DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H) +#endif +#ifdef DECLARE_CAUSE +DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH) +DECLARE_CAUSE("fetch access", CAUSE_FETCH_ACCESS) +DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION) +DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT) +DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD) +DECLARE_CAUSE("load access", CAUSE_LOAD_ACCESS) +DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE) +DECLARE_CAUSE("store access", CAUSE_STORE_ACCESS) +DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL) +DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL) +DECLARE_CAUSE("virtual_supervisor_ecall", CAUSE_VIRTUAL_SUPERVISOR_ECALL) +DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL) +DECLARE_CAUSE("fetch page fault", CAUSE_FETCH_PAGE_FAULT) +DECLARE_CAUSE("load page fault", CAUSE_LOAD_PAGE_FAULT) +DECLARE_CAUSE("store page fault", CAUSE_STORE_PAGE_FAULT) +DECLARE_CAUSE("fetch guest page fault", CAUSE_FETCH_GUEST_PAGE_FAULT) +DECLARE_CAUSE("load guest page fault", CAUSE_LOAD_GUEST_PAGE_FAULT) +DECLARE_CAUSE("virtual instruction", CAUSE_VIRTUAL_INSTRUCTION) +DECLARE_CAUSE("store guest page fault", CAUSE_STORE_GUEST_PAGE_FAULT) +#endif diff --git a/vendor/riscv/riscv-isa-sim/riscv/entropy_source.h b/vendor/riscv/riscv-isa-sim/riscv/entropy_source.h new file mode 100644 index 0000000000..148e6b0529 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/entropy_source.h @@ -0,0 +1,118 @@ + +#include <fstream> +#include <iostream> + +#include "common.h" + +// +// Used to model the cryptography extension entropy source. +// See Section 4 of the Scalar Cryptography Extension specificaiton. +class entropy_source { + +public: + + // Valid return codes for OPST bits [31:30] when reading seed. + static const uint32_t OPST_BIST = 0x0 << 30; + static const uint32_t OPST_WAIT = 0x1 << 30; + static const uint32_t OPST_ES16 = 0x2 << 30; + static const uint32_t OPST_DEAD = 0x3 << 30; + + // + // Other system events + // ------------------------------------------------------------ + + void reset() { + // Does nothing for now. In the future, can be used to model things + // like initial BIST states. + } + + // + // seed register + // ------------------------------------------------------------ + + void set_seed(reg_t UNUSED val) { + // Always ignore writes to seed. + // This CSR is strictly read only. It occupies a RW CSR address + // to handle the side-effect of the changing seed value on a read. + } + + // + // The format of seed is described in Section 4.1 of + // the scalar cryptography specification. + reg_t get_seed() { + + uint32_t result = 0; + + // Currently, always return ES16 (i.e. good randomness) In the future, we + // can more realistically model things like WAIT states, BIST warm up and + // maybe scriptable entry into the DEAD state, but until then, this is + // the bare minimum. + uint32_t return_status = OPST_ES16; + + if (return_status == OPST_ES16) { + + // Add some sampled entropy into the low 16 bits + uint16_t entropy = this -> get_two_random_bytes(); + result |= entropy; + + } else if (return_status == OPST_BIST) { + + // Do nothing. + + } else if (return_status == OPST_WAIT) { + + // Do nothing. + + } else if (return_status == OPST_DEAD) { + + // Do nothing. Stay dead. + + } else { + + // Unreachable. + + } + + // Note that if we get here any return_status is anything other than + // OPST_ES16, then the low 16-bits of the return value must be zero. + + result |= return_status; + + // Result is zero-extended on RV64. + return (reg_t)result; + } + + // + // Utility / support variables and functions. + // ------------------------------------------------------------ + + // The file to read entropy from. + std::string randomness_source = "/dev/urandom"; + + // Read two random bytes from the entropy source file. + uint16_t get_two_random_bytes() { + + std::ifstream fh(this -> randomness_source, std::ios::binary); + + if (fh.is_open()) { + + uint16_t random_bytes; + + fh.read((char*)(&random_bytes), 2); + + fh.close(); + + return random_bytes; + + } else { + + fprintf(stderr, "Could not open randomness source file:\n\t"); + fprintf(stderr, "%s", randomness_source.c_str()); + abort(); + + } + + } + +}; + diff --git a/vendor/riscv/riscv-isa-sim/riscv/execute.cc b/vendor/riscv/riscv-isa-sim/riscv/execute.cc new file mode 100644 index 0000000000..acf0e908c6 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/execute.cc @@ -0,0 +1,350 @@ +// See LICENSE for license details. + +#include "config.h" +#include "processor.h" +#include "mmu.h" +#include "disasm.h" +#include "decode_macros.h" +#include <cassert> + +static void commit_log_reset(processor_t* p) +{ + p->get_state()->log_reg_write.clear(); + p->get_state()->log_mem_read.clear(); + p->get_state()->log_mem_write.clear(); +} + +static void commit_log_stash_privilege(processor_t* p) +{ + state_t* state = p->get_state(); + state->last_inst_priv = state->prv; + state->last_inst_xlen = p->get_xlen(); + state->last_inst_flen = p->get_flen(); +} + +static void commit_log_print_value(FILE *log_file, int width, const void *data) +{ + assert(log_file); + + switch (width) { + case 8: + fprintf(log_file, "0x%02" PRIx8, *(const uint8_t *)data); + break; + case 16: + fprintf(log_file, "0x%04" PRIx16, *(const uint16_t *)data); + break; + case 32: + fprintf(log_file, "0x%08" PRIx32, *(const uint32_t *)data); + break; + case 64: + fprintf(log_file, "0x%016" PRIx64, *(const uint64_t *)data); + break; + default: + // max lengh of vector + if (((width - 1) & width) == 0) { + const uint64_t *arr = (const uint64_t *)data; + + fprintf(log_file, "0x"); + for (int idx = width / 64 - 1; idx >= 0; --idx) { + fprintf(log_file, "%016" PRIx64, arr[idx]); + } + } else { + abort(); + } + break; + } +} + +static void commit_log_print_value(FILE *log_file, int width, uint64_t val) +{ + commit_log_print_value(log_file, width, &val); +} + +static void commit_log_print_insn(processor_t *p, reg_t pc, insn_t insn) +{ + FILE *log_file = p->get_log_file(); + + auto& reg = p->get_state()->log_reg_write; + auto& load = p->get_state()->log_mem_read; + auto& store = p->get_state()->log_mem_write; + int priv = p->get_state()->last_inst_priv; + int xlen = p->get_state()->last_inst_xlen; + int flen = p->get_state()->last_inst_flen; + + // print core id on all lines so it is easy to grep + fprintf(log_file, "core%4" PRId32 ": ", p->get_id()); + + fprintf(log_file, "%1d ", priv); + commit_log_print_value(log_file, xlen, pc); + fprintf(log_file, " ("); + commit_log_print_value(log_file, insn.length() * 8, insn.bits()); + fprintf(log_file, ")"); + bool show_vec = false; + + for (auto item : reg) { + if (item.first == 0) + continue; + + char prefix; + int size; + int rd = item.first >> 4; + bool is_vec = false; + bool is_vreg = false; + switch (item.first & 0xf) { + case 0: + size = xlen; + prefix = 'x'; + break; + case 1: + size = flen; + prefix = 'f'; + break; + case 2: + size = p->VU.VLEN; + prefix = 'v'; + is_vreg = true; + break; + case 3: + is_vec = true; + break; + case 4: + size = xlen; + prefix = 'c'; + break; + default: + assert("can't been here" && 0); + break; + } + + if (!show_vec && (is_vreg || is_vec)) { + fprintf(log_file, " e%ld %s%ld l%ld", + (long)p->VU.vsew, + p->VU.vflmul < 1 ? "mf" : "m", + p->VU.vflmul < 1 ? (long)(1 / p->VU.vflmul) : (long)p->VU.vflmul, + (long)p->VU.vl->read()); + show_vec = true; + } + + if (!is_vec) { + if (prefix == 'c') + fprintf(log_file, " c%d_%s ", rd, csr_name(rd)); + else + fprintf(log_file, " %c%-2d ", prefix, rd); + if (is_vreg) + commit_log_print_value(log_file, size, &p->VU.elt<uint8_t>(rd, 0)); + else + commit_log_print_value(log_file, size, item.second.v); + } + } + + for (auto item : load) { + fprintf(log_file, " mem "); + commit_log_print_value(log_file, xlen, std::get<0>(item)); + } + + for (auto item : store) { + fprintf(log_file, " mem "); + commit_log_print_value(log_file, xlen, std::get<0>(item)); + fprintf(log_file, " "); + commit_log_print_value(log_file, std::get<2>(item) << 3, std::get<1>(item)); + } + fprintf(log_file, "\n"); +} + +inline void processor_t::update_histogram(reg_t pc) +{ + if (histogram_enabled) + pc_histogram[pc]++; +} + +// These two functions are expected to be inlined by the compiler separately in +// the processor_t::step() loop. The logged variant is used in the slow path +static inline reg_t execute_insn_fast(processor_t* p, reg_t pc, insn_fetch_t fetch) { + return fetch.func(p, fetch.insn, pc); +} +static inline reg_t execute_insn_logged(processor_t* p, reg_t pc, insn_fetch_t fetch) +{ + if (p->get_log_commits_enabled()) { + commit_log_reset(p); + commit_log_stash_privilege(p); + } + + reg_t npc; + + try { + npc = fetch.func(p, fetch.insn, pc); + if (npc != PC_SERIALIZE_BEFORE) { + if (p->get_log_commits_enabled()) { + commit_log_print_insn(p, pc, fetch.insn); + } + } + } catch (wait_for_interrupt_t &t) { + if (p->get_log_commits_enabled()) { + commit_log_print_insn(p, pc, fetch.insn); + } + throw; + } catch(mem_trap_t& t) { + //handle segfault in midlle of vector load/store + if (p->get_log_commits_enabled()) { + for (auto item : p->get_state()->log_reg_write) { + if ((item.first & 3) == 3) { + commit_log_print_insn(p, pc, fetch.insn); + break; + } + } + } + throw; + } catch(...) { + throw; + } + p->update_histogram(pc); + + return npc; +} + +bool processor_t::slow_path() +{ + return debug || state.single_step != state.STEP_NONE || state.debug_mode || + log_commits_enabled || histogram_enabled || in_wfi || check_triggers_icount; +} + +// fetch/decode/execute loop +void processor_t::step(size_t n) +{ + if (!state.debug_mode) { + if (halt_request == HR_REGULAR) { + enter_debug_mode(DCSR_CAUSE_DEBUGINT); + } else if (halt_request == HR_GROUP) { + enter_debug_mode(DCSR_CAUSE_GROUP); + } // !!!The halt bit in DCSR is deprecated. + else if (state.dcsr->halt) { + enter_debug_mode(DCSR_CAUSE_HALT); + } + } + + while (n > 0) { + size_t instret = 0; + reg_t pc = state.pc; + mmu_t* _mmu = mmu; + + #define advance_pc() \ + if (unlikely(invalid_pc(pc))) { \ + switch (pc) { \ + case PC_SERIALIZE_BEFORE: state.serialized = true; break; \ + case PC_SERIALIZE_AFTER: ++instret; break; \ + default: abort(); \ + } \ + pc = state.pc; \ + break; \ + } else { \ + state.pc = pc; \ + instret++; \ + } + + try + { + take_pending_interrupt(); + + if (unlikely(slow_path())) + { + // Main simulation loop, slow path. + while (instret < n) + { + if (unlikely(!state.serialized && state.single_step == state.STEP_STEPPED)) { + state.single_step = state.STEP_NONE; + if (!state.debug_mode) { + enter_debug_mode(DCSR_CAUSE_STEP); + // enter_debug_mode changed state.pc, so we can't just continue. + break; + } + } + + if (unlikely(state.single_step == state.STEP_STEPPING)) { + state.single_step = state.STEP_STEPPED; + } + + if (!state.serialized && check_triggers_icount) { + auto match = TM.detect_icount_match(); + if (match.has_value()) { + assert(match->timing == triggers::TIMING_BEFORE); + throw triggers::matched_t((triggers::operation_t)0, 0, match->action); + } + } + + // debug mode wfis must nop + if (unlikely(in_wfi && !state.debug_mode)) { + throw wait_for_interrupt_t(); + } + + in_wfi = false; + insn_fetch_t fetch = mmu->load_insn(pc); + if (debug && !state.serialized) + disasm(fetch.insn); + pc = execute_insn_logged(this, pc, fetch); + advance_pc(); + } + } + else while (instret < n) + { + // Main simulation loop, fast path. + for (auto ic_entry = _mmu->access_icache(pc); ; ) { + auto fetch = ic_entry->data; + pc = execute_insn_fast(this, pc, fetch); + ic_entry = ic_entry->next; + if (unlikely(ic_entry->tag != pc)) + break; + if (unlikely(instret + 1 == n)) + break; + instret++; + state.pc = pc; + } + + advance_pc(); + } + } + catch(trap_t& t) + { + take_trap(t, pc); + n = instret; + + // Trigger action takes priority over single step + auto match = TM.detect_trap_match(t); + if (match.has_value()) + take_trigger_action(match->action, 0, state.pc); + else if (unlikely(state.single_step == state.STEP_STEPPED)) { + state.single_step = state.STEP_NONE; + enter_debug_mode(DCSR_CAUSE_STEP); + } + } + catch (triggers::matched_t& t) + { + if (mmu->matched_trigger) { + delete mmu->matched_trigger; + mmu->matched_trigger = NULL; + } + take_trigger_action(t.action, t.address, pc); + } + catch(trap_debug_mode&) + { + enter_debug_mode(DCSR_CAUSE_SWBP); + } + catch (wait_for_interrupt_t &t) + { + // Return to the outer simulation loop, which gives other devices/harts a + // chance to generate interrupts. + // + // In the debug ROM this prevents us from wasting time looping, but also + // allows us to switch to other threads only once per idle loop in case + // there is activity. + n = ++instret; + in_wfi = true; + } + + state.minstret->bump(instret); + + // Model a hart whose CPI is 1. + state.mcycle->bump(instret); + + n -= instret; + } +} diff --git a/vendor/riscv/riscv-isa-sim/riscv/extension.cc b/vendor/riscv/riscv-isa-sim/riscv/extension.cc new file mode 100644 index 0000000000..520c2ed578 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/extension.cc @@ -0,0 +1,23 @@ +// See LICENSE for license details. + +#include "extension.h" +#include "trap.h" + +extension_t::~extension_t() +{ +} + +void extension_t::illegal_instruction() +{ + throw trap_illegal_instruction(0); +} + +void extension_t::raise_interrupt() +{ + p->take_interrupt((reg_t)1 << IRQ_COP); // must not return + throw std::logic_error("a COP exception was posted, but interrupts are disabled!"); +} + +void extension_t::clear_interrupt() +{ +} diff --git a/vendor/riscv/riscv-isa-sim/riscv/extension.h b/vendor/riscv/riscv-isa-sim/riscv/extension.h new file mode 100644 index 0000000000..de6ece3e63 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/extension.h @@ -0,0 +1,38 @@ +// See LICENSE for license details. + +#ifndef _RISCV_COPROCESSOR_H +#define _RISCV_COPROCESSOR_H + +#include "processor.h" +#include "disasm.h" +#include <vector> +#include <functional> + +class extension_t +{ + public: + virtual std::vector<insn_desc_t> get_instructions() = 0; + virtual std::vector<disasm_insn_t*> get_disasms() = 0; + virtual const char* name() = 0; + virtual void reset() {}; + virtual void set_debug(bool UNUSED value) {} + virtual ~extension_t(); + + void set_processor(processor_t* _p) { p = _p; } + protected: + processor_t* p; + + void illegal_instruction(); + void raise_interrupt(); + void clear_interrupt(); +}; + +std::function<extension_t*()> find_extension(const char* name); +void register_extension(const char* name, std::function<extension_t*()> f); + +#define REGISTER_EXTENSION(name, constructor) \ + class register_##name { \ + public: register_##name() { register_extension(#name, constructor); } \ + }; static register_##name dummy_##name; + +#endif diff --git a/vendor/riscv/riscv-isa-sim/riscv/extensions.cc b/vendor/riscv/riscv-isa-sim/riscv/extensions.cc new file mode 100644 index 0000000000..b488aad159 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/extensions.cc @@ -0,0 +1,46 @@ +// See LICENSE for license details. + +#include "extension.h" +#include <string> +#include <map> +#include <dlfcn.h> + +static std::map<std::string, std::function<extension_t*()>>& extensions() +{ + static std::map<std::string, std::function<extension_t*()>> v; + return v; +} + +void register_extension(const char* name, std::function<extension_t*()> f) +{ + extensions()[name] = f; +} + +std::function<extension_t*()> find_extension(const char* name) +{ + if (!extensions().count(name)) { + // try to find extension xyz by loading libxyz.so + std::string libname = std::string("lib") + name + ".so"; + std::string libdefault = "libcustomext.so"; + bool is_default = false; + auto dlh = dlopen(libname.c_str(), RTLD_LAZY); + if (!dlh) { + dlh = dlopen(libdefault.c_str(), RTLD_LAZY); + if (!dlh) { + fprintf(stderr, "couldn't load shared library (either '%s' or '%s'), reason: %s\n", + libname.c_str(), libdefault.c_str(), dlerror()); + exit(-1); + } + + is_default = true; + } + + if (!extensions().count(name)) { + fprintf(stderr, "couldn't find extension '%s' in shared library '%s'\n", + name, is_default ? libdefault.c_str() : libname.c_str()); + exit(-1); + } + } + + return extensions()[name]; +} diff --git a/vendor/riscv/riscv-isa-sim/riscv/insn_macros.h b/vendor/riscv/riscv-isa-sim/riscv/insn_macros.h new file mode 100644 index 0000000000..8ec8f763e8 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insn_macros.h @@ -0,0 +1,9 @@ +#ifndef _RISCV_INSN_MACROS_H +#define _RISCV_INSN_MACROS_H + +// These conflict with Boost headers so can't be included from insn_template.h +#define P (*p) + +#define require(x) (unlikely(!(x)) ? throw trap_illegal_instruction(insn.bits()) : (void) 0) + +#endif diff --git a/vendor/riscv/riscv-isa-sim/riscv/insn_template.cc b/vendor/riscv/riscv-isa-sim/riscv/insn_template.cc new file mode 100644 index 0000000000..9194d19f46 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insn_template.cc @@ -0,0 +1,98 @@ +// See LICENSE for license details. + +#include "insn_template.h" +#include "insn_macros.h" + +#define DECODE_MACRO_USAGE_LOGGED 0 + +reg_t fast_rv32i_NAME(processor_t* p, insn_t insn, reg_t pc) +{ + #define xlen 32 + reg_t npc = sext_xlen(pc + insn_length(OPCODE)); + #include "insns/NAME.h" + trace_opcode(p, OPCODE, insn); + #undef xlen + return npc; +} + +reg_t fast_rv64i_NAME(processor_t* p, insn_t insn, reg_t pc) +{ + #define xlen 64 + reg_t npc = sext_xlen(pc + insn_length(OPCODE)); + #include "insns/NAME.h" + trace_opcode(p, OPCODE, insn); + #undef xlen + return npc; +} + +#undef DECODE_MACRO_USAGE_LOGGED +#define DECODE_MACRO_USAGE_LOGGED 1 + +reg_t logged_rv32i_NAME(processor_t* p, insn_t insn, reg_t pc) +{ + #define xlen 32 + reg_t npc = sext_xlen(pc + insn_length(OPCODE)); + #include "insns/NAME.h" + trace_opcode(p, OPCODE, insn); + #undef xlen + return npc; +} + +reg_t logged_rv64i_NAME(processor_t* p, insn_t insn, reg_t pc) +{ + #define xlen 64 + reg_t npc = sext_xlen(pc + insn_length(OPCODE)); + #include "insns/NAME.h" + trace_opcode(p, OPCODE, insn); + #undef xlen + return npc; +} + +#undef CHECK_REG +#define CHECK_REG(reg) require((reg) < 16) + +#undef DECODE_MACRO_USAGE_LOGGED +#define DECODE_MACRO_USAGE_LOGGED 0 + +reg_t fast_rv32e_NAME(processor_t* p, insn_t insn, reg_t pc) +{ + #define xlen 32 + reg_t npc = sext_xlen(pc + insn_length(OPCODE)); + #include "insns/NAME.h" + trace_opcode(p, OPCODE, insn); + #undef xlen + return npc; +} + +reg_t fast_rv64e_NAME(processor_t* p, insn_t insn, reg_t pc) +{ + #define xlen 64 + reg_t npc = sext_xlen(pc + insn_length(OPCODE)); + #include "insns/NAME.h" + trace_opcode(p, OPCODE, insn); + #undef xlen + return npc; +} + +#undef DECODE_MACRO_USAGE_LOGGED +#define DECODE_MACRO_USAGE_LOGGED 1 + +reg_t logged_rv32e_NAME(processor_t* p, insn_t insn, reg_t pc) +{ + #define xlen 32 + reg_t npc = sext_xlen(pc + insn_length(OPCODE)); + #include "insns/NAME.h" + trace_opcode(p, OPCODE, insn); + #undef xlen + return npc; +} + +reg_t logged_rv64e_NAME(processor_t* p, insn_t insn, reg_t pc) +{ + #define xlen 64 + reg_t npc = sext_xlen(pc + insn_length(OPCODE)); + #include "insns/NAME.h" + trace_opcode(p, OPCODE, insn); + #undef xlen + return npc; +} diff --git a/vendor/riscv/riscv-isa-sim/riscv/insn_template.h b/vendor/riscv/riscv-isa-sim/riscv/insn_template.h new file mode 100644 index 0000000000..cead6d7dc8 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insn_template.h @@ -0,0 +1,12 @@ +// See LICENSE for license details. + +#include "decode_macros.h" +#include "arith.h" +#include "mmu.h" +#include "softfloat.h" +#include "internals.h" +#include "specialize.h" +#include "tracer.h" +#include "p_ext_macros.h" +#include "v_ext_macros.h" +#include <assert.h> diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/add.h b/vendor/riscv/riscv-isa-sim/riscv/insns/add.h new file mode 100644 index 0000000000..895e2b1867 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/add.h @@ -0,0 +1 @@ +WRITE_RD(sext_xlen(RS1 + RS2)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/add16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/add16.h new file mode 100644 index 0000000000..fae43165fc --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/add16.h @@ -0,0 +1,3 @@ +P_LOOP(16, { + pd = ps1 + ps2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/add32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/add32.h new file mode 100644 index 0000000000..ca544cef3e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/add32.h @@ -0,0 +1,4 @@ +require_rv64; +P_LOOP(32, { + pd = ps1 + ps2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/add64.h b/vendor/riscv/riscv-isa-sim/riscv/insns/add64.h new file mode 100644 index 0000000000..0968656f96 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/add64.h @@ -0,0 +1,3 @@ +P_64_PROFILE({ + rd = rs1 + rs2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/add8.h b/vendor/riscv/riscv-isa-sim/riscv/insns/add8.h new file mode 100644 index 0000000000..bb54a7b6bf --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/add8.h @@ -0,0 +1,3 @@ +P_LOOP(8, { + pd = ps1 + ps2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/add_uw.h b/vendor/riscv/riscv-isa-sim/riscv/insns/add_uw.h new file mode 100644 index 0000000000..5b25a36762 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/add_uw.h @@ -0,0 +1,3 @@ +require_rv64; +require_extension(EXT_ZBA); +WRITE_RD(sext_xlen(zext32(RS1) + RS2)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/addi.h b/vendor/riscv/riscv-isa-sim/riscv/insns/addi.h new file mode 100644 index 0000000000..1bb5dcedfa --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/addi.h @@ -0,0 +1 @@ +WRITE_RD(sext_xlen(RS1 + insn.i_imm())); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/addiw.h b/vendor/riscv/riscv-isa-sim/riscv/insns/addiw.h new file mode 100644 index 0000000000..4263eada24 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/addiw.h @@ -0,0 +1,2 @@ +require_rv64; +WRITE_RD(sext32(insn.i_imm() + RS1)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/addw.h b/vendor/riscv/riscv-isa-sim/riscv/insns/addw.h new file mode 100644 index 0000000000..706dc9c8f9 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/addw.h @@ -0,0 +1,2 @@ +require_rv64; +WRITE_RD(sext32(RS1 + RS2)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/aes32dsi.h b/vendor/riscv/riscv-isa-sim/riscv/insns/aes32dsi.h new file mode 100644 index 0000000000..b2680b019e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/aes32dsi.h @@ -0,0 +1,16 @@ + +#include "aes_common.h" + +require_rv32; +require_extension(EXT_ZKND); + +uint8_t bs = insn.bs(); + +uint8_t t0 = RS2 >> (8*bs); +uint8_t x = AES_DEC_SBOX[t0]; +uint32_t u = x; + +u = (u << (8*bs)) | (u >> (32-8*bs)); + +WRITE_RD(sext_xlen(u ^ RS1)); + diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/aes32dsmi.h b/vendor/riscv/riscv-isa-sim/riscv/insns/aes32dsmi.h new file mode 100644 index 0000000000..d76abc089e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/aes32dsmi.h @@ -0,0 +1,21 @@ + +#include "aes_common.h" + +require_rv32; +require_extension(EXT_ZKND); + +uint8_t bs = insn.bs(); + +uint8_t t0 = RS2 >> (8*bs); +uint8_t x = AES_DEC_SBOX[t0]; +uint32_t u ; + +u = (AES_GFMUL(x,0xb) << 24) | + (AES_GFMUL(x,0xd) << 16) | + (AES_GFMUL(x,0x9) << 8) | + (AES_GFMUL(x,0xe) << 0) ; + +u = (u << (8*bs)) | (u >> (32-8*bs)); + +WRITE_RD(sext_xlen(u ^ RS1)); + diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/aes32esi.h b/vendor/riscv/riscv-isa-sim/riscv/insns/aes32esi.h new file mode 100644 index 0000000000..d0c0a63baa --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/aes32esi.h @@ -0,0 +1,16 @@ + +#include "aes_common.h" + +require_rv32; +require_extension(EXT_ZKNE); + +uint8_t bs = insn.bs(); + +uint8_t t0 = RS2 >> (8*bs); +uint8_t x = AES_ENC_SBOX[t0]; +uint32_t u = x; + +u = (u << (8*bs)) | (u >> (32-8*bs)); + +WRITE_RD(sext_xlen(u ^ RS1)); + diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/aes32esmi.h b/vendor/riscv/riscv-isa-sim/riscv/insns/aes32esmi.h new file mode 100644 index 0000000000..069718d97c --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/aes32esmi.h @@ -0,0 +1,21 @@ + +#include "aes_common.h" + +require_rv32; +require_extension(EXT_ZKNE); + +uint8_t bs = insn.bs(); + +uint8_t t0 = RS2 >> (8*bs); +uint8_t x = AES_ENC_SBOX[t0]; +uint32_t u ; + +u = (AES_GFMUL(x,3) << 24) | + ( x << 16) | + ( x << 8) | + (AES_GFMUL(x,2) << 0) ; + +u = (u << (8*bs)) | (u >> (32-8*bs)); + +WRITE_RD(sext_xlen(u ^ RS1)); + diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/aes64ds.h b/vendor/riscv/riscv-isa-sim/riscv/insns/aes64ds.h new file mode 100644 index 0000000000..64baf87a82 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/aes64ds.h @@ -0,0 +1,21 @@ + +#include "aes_common.h" + +require_rv64; +require_extension(EXT_ZKND); + +uint64_t temp = AES_INVSHIFROWS_LO(RS1,RS2); + + temp = ( + ((uint64_t)AES_DEC_SBOX[(temp >> 0) & 0xFF] << 0) | + ((uint64_t)AES_DEC_SBOX[(temp >> 8) & 0xFF] << 8) | + ((uint64_t)AES_DEC_SBOX[(temp >> 16) & 0xFF] << 16) | + ((uint64_t)AES_DEC_SBOX[(temp >> 24) & 0xFF] << 24) | + ((uint64_t)AES_DEC_SBOX[(temp >> 32) & 0xFF] << 32) | + ((uint64_t)AES_DEC_SBOX[(temp >> 40) & 0xFF] << 40) | + ((uint64_t)AES_DEC_SBOX[(temp >> 48) & 0xFF] << 48) | + ((uint64_t)AES_DEC_SBOX[(temp >> 56) & 0xFF] << 56) +); + +WRITE_RD(temp); + diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/aes64dsm.h b/vendor/riscv/riscv-isa-sim/riscv/insns/aes64dsm.h new file mode 100644 index 0000000000..eccf02fca2 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/aes64dsm.h @@ -0,0 +1,29 @@ + +#include "aes_common.h" + +require_rv64; +require_extension(EXT_ZKND); + +uint64_t temp = AES_INVSHIFROWS_LO(RS1,RS2); + + temp = ( + ((uint64_t)AES_DEC_SBOX[(temp >> 0) & 0xFF] << 0) | + ((uint64_t)AES_DEC_SBOX[(temp >> 8) & 0xFF] << 8) | + ((uint64_t)AES_DEC_SBOX[(temp >> 16) & 0xFF] << 16) | + ((uint64_t)AES_DEC_SBOX[(temp >> 24) & 0xFF] << 24) | + ((uint64_t)AES_DEC_SBOX[(temp >> 32) & 0xFF] << 32) | + ((uint64_t)AES_DEC_SBOX[(temp >> 40) & 0xFF] << 40) | + ((uint64_t)AES_DEC_SBOX[(temp >> 48) & 0xFF] << 48) | + ((uint64_t)AES_DEC_SBOX[(temp >> 56) & 0xFF] << 56) +); + +uint32_t col_0 = temp & 0xFFFFFFFF; +uint32_t col_1 = temp >> 32 ; + + col_0 = AES_INVMIXCOLUMN(col_0); + col_1 = AES_INVMIXCOLUMN(col_1); + +uint64_t result= ((uint64_t)col_1 << 32) | col_0; + +WRITE_RD(result); + diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/aes64es.h b/vendor/riscv/riscv-isa-sim/riscv/insns/aes64es.h new file mode 100644 index 0000000000..6bbc4efe83 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/aes64es.h @@ -0,0 +1,21 @@ + +#include "aes_common.h" + +require_rv64; +require_extension(EXT_ZKNE); + +uint64_t temp = AES_SHIFROWS_LO(RS1,RS2); + + temp = ( + ((uint64_t)AES_ENC_SBOX[(temp >> 0) & 0xFF] << 0) | + ((uint64_t)AES_ENC_SBOX[(temp >> 8) & 0xFF] << 8) | + ((uint64_t)AES_ENC_SBOX[(temp >> 16) & 0xFF] << 16) | + ((uint64_t)AES_ENC_SBOX[(temp >> 24) & 0xFF] << 24) | + ((uint64_t)AES_ENC_SBOX[(temp >> 32) & 0xFF] << 32) | + ((uint64_t)AES_ENC_SBOX[(temp >> 40) & 0xFF] << 40) | + ((uint64_t)AES_ENC_SBOX[(temp >> 48) & 0xFF] << 48) | + ((uint64_t)AES_ENC_SBOX[(temp >> 56) & 0xFF] << 56) +); + +WRITE_RD(temp); + diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/aes64esm.h b/vendor/riscv/riscv-isa-sim/riscv/insns/aes64esm.h new file mode 100644 index 0000000000..0351c11b3b --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/aes64esm.h @@ -0,0 +1,29 @@ + +#include "aes_common.h" + +require_rv64; +require_extension(EXT_ZKNE); + +uint64_t temp = AES_SHIFROWS_LO(RS1,RS2); + + temp = ( + ((uint64_t)AES_ENC_SBOX[(temp >> 0) & 0xFF] << 0) | + ((uint64_t)AES_ENC_SBOX[(temp >> 8) & 0xFF] << 8) | + ((uint64_t)AES_ENC_SBOX[(temp >> 16) & 0xFF] << 16) | + ((uint64_t)AES_ENC_SBOX[(temp >> 24) & 0xFF] << 24) | + ((uint64_t)AES_ENC_SBOX[(temp >> 32) & 0xFF] << 32) | + ((uint64_t)AES_ENC_SBOX[(temp >> 40) & 0xFF] << 40) | + ((uint64_t)AES_ENC_SBOX[(temp >> 48) & 0xFF] << 48) | + ((uint64_t)AES_ENC_SBOX[(temp >> 56) & 0xFF] << 56) +); + +uint32_t col_0 = temp & 0xFFFFFFFF; +uint32_t col_1 = temp >> 32 ; + + col_0 = AES_MIXCOLUMN(col_0); + col_1 = AES_MIXCOLUMN(col_1); + +uint64_t result= ((uint64_t)col_1 << 32) | col_0; + +WRITE_RD(result); + diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/aes64im.h b/vendor/riscv/riscv-isa-sim/riscv/insns/aes64im.h new file mode 100644 index 0000000000..9dd9b021cc --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/aes64im.h @@ -0,0 +1,16 @@ + +#include "aes_common.h" + +require_rv64; +require_extension(EXT_ZKND); + +uint32_t col_0 = RS1 & 0xFFFFFFFF; +uint32_t col_1 = RS1 >> 32 ; + + col_0 = AES_INVMIXCOLUMN(col_0); + col_1 = AES_INVMIXCOLUMN(col_1); + +uint64_t result= ((uint64_t)col_1 << 32) | col_0; + +WRITE_RD(result); + diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/aes64ks1i.h b/vendor/riscv/riscv-isa-sim/riscv/insns/aes64ks1i.h new file mode 100644 index 0000000000..c7354d6cba --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/aes64ks1i.h @@ -0,0 +1,35 @@ + +#include "aes_common.h" + +require_rv64; +require_either_extension(EXT_ZKND, EXT_ZKNE); + +uint8_t round_consts [10] = { + 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1b, 0x36 +}; + +uint8_t enc_rcon = insn.rcon() ; + +require(enc_rcon <= 0xA); + +uint32_t temp = (RS1 >> 32) & 0xFFFFFFFF ; +uint8_t rcon = 0 ; +uint64_t result ; + +if (enc_rcon != 0xA) { + temp = (temp >> 8) | (temp << 24); // Rotate right by 8 + rcon = round_consts[enc_rcon]; +} + +temp = + ((uint32_t)AES_ENC_SBOX[(temp >> 24) & 0xFF] << 24) | + ((uint32_t)AES_ENC_SBOX[(temp >> 16) & 0xFF] << 16) | + ((uint32_t)AES_ENC_SBOX[(temp >> 8) & 0xFF] << 8) | + ((uint32_t)AES_ENC_SBOX[(temp >> 0) & 0xFF] << 0) ; + +temp ^= rcon; + +result = ((uint64_t)temp << 32) | temp; + +WRITE_RD(result); + diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/aes64ks2.h b/vendor/riscv/riscv-isa-sim/riscv/insns/aes64ks2.h new file mode 100644 index 0000000000..65d5a77c33 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/aes64ks2.h @@ -0,0 +1,16 @@ + +#include "aes_common.h" + +require_rv64; +require_either_extension(EXT_ZKND, EXT_ZKNE); + +uint32_t rs1_hi = RS1 >> 32; +uint32_t rs2_lo = RS2 ; +uint32_t rs2_hi = RS2 >> 32; + +uint32_t r_lo = (rs1_hi ^ rs2_lo ) ; +uint32_t r_hi = (rs1_hi ^ rs2_lo ^ rs2_hi) ; +uint64_t result = ((uint64_t)r_hi << 32) | r_lo ; + +WRITE_RD(result); + diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/aes_common.h b/vendor/riscv/riscv-isa-sim/riscv/insns/aes_common.h new file mode 100644 index 0000000000..4f3f618db0 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/aes_common.h @@ -0,0 +1,156 @@ + +static uint8_t UNUSED AES_ENC_SBOX[]= { + 0x63, 0x7C, 0x77, 0x7B, 0xF2, 0x6B, 0x6F, 0xC5, + 0x30, 0x01, 0x67, 0x2B, 0xFE, 0xD7, 0xAB, 0x76, + 0xCA, 0x82, 0xC9, 0x7D, 0xFA, 0x59, 0x47, 0xF0, + 0xAD, 0xD4, 0xA2, 0xAF, 0x9C, 0xA4, 0x72, 0xC0, + 0xB7, 0xFD, 0x93, 0x26, 0x36, 0x3F, 0xF7, 0xCC, + 0x34, 0xA5, 0xE5, 0xF1, 0x71, 0xD8, 0x31, 0x15, + 0x04, 0xC7, 0x23, 0xC3, 0x18, 0x96, 0x05, 0x9A, + 0x07, 0x12, 0x80, 0xE2, 0xEB, 0x27, 0xB2, 0x75, + 0x09, 0x83, 0x2C, 0x1A, 0x1B, 0x6E, 0x5A, 0xA0, + 0x52, 0x3B, 0xD6, 0xB3, 0x29, 0xE3, 0x2F, 0x84, + 0x53, 0xD1, 0x00, 0xED, 0x20, 0xFC, 0xB1, 0x5B, + 0x6A, 0xCB, 0xBE, 0x39, 0x4A, 0x4C, 0x58, 0xCF, + 0xD0, 0xEF, 0xAA, 0xFB, 0x43, 0x4D, 0x33, 0x85, + 0x45, 0xF9, 0x02, 0x7F, 0x50, 0x3C, 0x9F, 0xA8, + 0x51, 0xA3, 0x40, 0x8F, 0x92, 0x9D, 0x38, 0xF5, + 0xBC, 0xB6, 0xDA, 0x21, 0x10, 0xFF, 0xF3, 0xD2, + 0xCD, 0x0C, 0x13, 0xEC, 0x5F, 0x97, 0x44, 0x17, + 0xC4, 0xA7, 0x7E, 0x3D, 0x64, 0x5D, 0x19, 0x73, + 0x60, 0x81, 0x4F, 0xDC, 0x22, 0x2A, 0x90, 0x88, + 0x46, 0xEE, 0xB8, 0x14, 0xDE, 0x5E, 0x0B, 0xDB, + 0xE0, 0x32, 0x3A, 0x0A, 0x49, 0x06, 0x24, 0x5C, + 0xC2, 0xD3, 0xAC, 0x62, 0x91, 0x95, 0xE4, 0x79, + 0xE7, 0xC8, 0x37, 0x6D, 0x8D, 0xD5, 0x4E, 0xA9, + 0x6C, 0x56, 0xF4, 0xEA, 0x65, 0x7A, 0xAE, 0x08, + 0xBA, 0x78, 0x25, 0x2E, 0x1C, 0xA6, 0xB4, 0xC6, + 0xE8, 0xDD, 0x74, 0x1F, 0x4B, 0xBD, 0x8B, 0x8A, + 0x70, 0x3E, 0xB5, 0x66, 0x48, 0x03, 0xF6, 0x0E, + 0x61, 0x35, 0x57, 0xB9, 0x86, 0xC1, 0x1D, 0x9E, + 0xE1, 0xF8, 0x98, 0x11, 0x69, 0xD9, 0x8E, 0x94, + 0x9B, 0x1E, 0x87, 0xE9, 0xCE, 0x55, 0x28, 0xDF, + 0x8C, 0xA1, 0x89, 0x0D, 0xBF, 0xE6, 0x42, 0x68, + 0x41, 0x99, 0x2D, 0x0F, 0xB0, 0x54, 0xBB, 0x16 +}; + +static uint8_t UNUSED AES_DEC_SBOX[] = { + 0x52, 0x09, 0x6A, 0xD5, 0x30, 0x36, 0xA5, 0x38, + 0xBF, 0x40, 0xA3, 0x9E, 0x81, 0xF3, 0xD7, 0xFB, + 0x7C, 0xE3, 0x39, 0x82, 0x9B, 0x2F, 0xFF, 0x87, + 0x34, 0x8E, 0x43, 0x44, 0xC4, 0xDE, 0xE9, 0xCB, + 0x54, 0x7B, 0x94, 0x32, 0xA6, 0xC2, 0x23, 0x3D, + 0xEE, 0x4C, 0x95, 0x0B, 0x42, 0xFA, 0xC3, 0x4E, + 0x08, 0x2E, 0xA1, 0x66, 0x28, 0xD9, 0x24, 0xB2, + 0x76, 0x5B, 0xA2, 0x49, 0x6D, 0x8B, 0xD1, 0x25, + 0x72, 0xF8, 0xF6, 0x64, 0x86, 0x68, 0x98, 0x16, + 0xD4, 0xA4, 0x5C, 0xCC, 0x5D, 0x65, 0xB6, 0x92, + 0x6C, 0x70, 0x48, 0x50, 0xFD, 0xED, 0xB9, 0xDA, + 0x5E, 0x15, 0x46, 0x57, 0xA7, 0x8D, 0x9D, 0x84, + 0x90, 0xD8, 0xAB, 0x00, 0x8C, 0xBC, 0xD3, 0x0A, + 0xF7, 0xE4, 0x58, 0x05, 0xB8, 0xB3, 0x45, 0x06, + 0xD0, 0x2C, 0x1E, 0x8F, 0xCA, 0x3F, 0x0F, 0x02, + 0xC1, 0xAF, 0xBD, 0x03, 0x01, 0x13, 0x8A, 0x6B, + 0x3A, 0x91, 0x11, 0x41, 0x4F, 0x67, 0xDC, 0xEA, + 0x97, 0xF2, 0xCF, 0xCE, 0xF0, 0xB4, 0xE6, 0x73, + 0x96, 0xAC, 0x74, 0x22, 0xE7, 0xAD, 0x35, 0x85, + 0xE2, 0xF9, 0x37, 0xE8, 0x1C, 0x75, 0xDF, 0x6E, + 0x47, 0xF1, 0x1A, 0x71, 0x1D, 0x29, 0xC5, 0x89, + 0x6F, 0xB7, 0x62, 0x0E, 0xAA, 0x18, 0xBE, 0x1B, + 0xFC, 0x56, 0x3E, 0x4B, 0xC6, 0xD2, 0x79, 0x20, + 0x9A, 0xDB, 0xC0, 0xFE, 0x78, 0xCD, 0x5A, 0xF4, + 0x1F, 0xDD, 0xA8, 0x33, 0x88, 0x07, 0xC7, 0x31, + 0xB1, 0x12, 0x10, 0x59, 0x27, 0x80, 0xEC, 0x5F, + 0x60, 0x51, 0x7F, 0xA9, 0x19, 0xB5, 0x4A, 0x0D, + 0x2D, 0xE5, 0x7A, 0x9F, 0x93, 0xC9, 0x9C, 0xEF, + 0xA0, 0xE0, 0x3B, 0x4D, 0xAE, 0x2A, 0xF5, 0xB0, + 0xC8, 0xEB, 0xBB, 0x3C, 0x83, 0x53, 0x99, 0x61, + 0x17, 0x2B, 0x04, 0x7E, 0xBA, 0x77, 0xD6, 0x26, + 0xE1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0C, 0x7D +}; + +#define AES_UNPACK_BYTES(b0,b1,b2,b3) \ + uint8_t b0 = (RS1 >> 0) & 0xFF; \ + uint8_t b1 = (RS2 >> 8) & 0xFF; \ + uint8_t b2 = (RS1 >> 16) & 0xFF; \ + uint8_t b3 = (RS2 >> 24) & 0xFF; \ + +#define AES_PACK_BYTES(b0,b1,b2,b3) ( \ + (uint32_t)b0 << 0 | \ + (uint32_t)b1 << 8 | \ + (uint32_t)b2 << 16 | \ + (uint32_t)b3 << 24 ) + +#define AES_SBOX(b0, b1, b2, b3) \ + b0 = AES_ENC_SBOX[b0]; \ + b1 = AES_ENC_SBOX[b1]; \ + b2 = AES_ENC_SBOX[b2]; \ + b3 = AES_ENC_SBOX[b3]; \ + +#define AES_RSBOX(b0, b1, b2, b3) \ + b0 = AES_DEC_SBOX[b0]; \ + b1 = AES_DEC_SBOX[b1]; \ + b2 = AES_DEC_SBOX[b2]; \ + b3 = AES_DEC_SBOX[b3]; \ + +#define AES_XTIME(a) \ + ((a << 1) ^ ((a&0x80) ? 0x1b : 0)) + +#define AES_GFMUL(a,b) (( \ + ( ( (b) & 0x1 ) ? (a) : 0 ) ^ \ + ( ( (b) & 0x2 ) ? AES_XTIME(a) : 0 ) ^ \ + ( ( (b) & 0x4 ) ? AES_XTIME(AES_XTIME(a)) : 0 ) ^ \ + ( ( (b) & 0x8 ) ? AES_XTIME(AES_XTIME(AES_XTIME(a))) : 0 ) )&0xFF) + +#define BY(X,I) ((X >> (8*I)) & 0xFF) + +#define AES_SHIFROWS_LO(RS1,RS2) ( \ + (((RS1 >> 24) & 0xFF) << 56) | \ + (((RS2 >> 48) & 0xFF) << 48) | \ + (((RS2 >> 8) & 0xFF) << 40) | \ + (((RS1 >> 32) & 0xFF) << 32) | \ + (((RS2 >> 56) & 0xFF) << 24) | \ + (((RS2 >> 16) & 0xFF) << 16) | \ + (((RS1 >> 40) & 0xFF) << 8) | \ + (((RS1 >> 0) & 0xFF) << 0) ) + +#define AES_INVSHIFROWS_LO(RS1,RS2) ( \ + (((RS2 >> 24) & 0xFF) << 56) | \ + (((RS2 >> 48) & 0xFF) << 48) | \ + (((RS1 >> 8) & 0xFF) << 40) | \ + (((RS1 >> 32) & 0xFF) << 32) | \ + (((RS1 >> 56) & 0xFF) << 24) | \ + (((RS2 >> 16) & 0xFF) << 16) | \ + (((RS2 >> 40) & 0xFF) << 8) | \ + (((RS1 >> 0) & 0xFF) << 0) ) + + +#define AES_MIXBYTE(COL,B0,B1,B2,B3) ( \ + BY(COL,B3) ^ \ + BY(COL,B2) ^ \ + AES_GFMUL(BY(COL,B1), 3) ^ \ + AES_GFMUL(BY(COL,B0), 2) \ +) + +#define AES_MIXCOLUMN(COL) ( \ + AES_MIXBYTE(COL,3,0,1,2) << 24 | \ + AES_MIXBYTE(COL,2,3,0,1) << 16 | \ + AES_MIXBYTE(COL,1,2,3,0) << 8 | \ + AES_MIXBYTE(COL,0,1,2,3) << 0 \ +) + + +#define AES_INVMIXBYTE(COL,B0,B1,B2,B3) ( \ + AES_GFMUL(BY(COL,B3),0x9) ^ \ + AES_GFMUL(BY(COL,B2),0xd) ^ \ + AES_GFMUL(BY(COL,B1),0xb) ^ \ + AES_GFMUL(BY(COL,B0),0xe) \ +) + +#define AES_INVMIXCOLUMN(COL) ( \ + AES_INVMIXBYTE(COL,3,0,1,2) << 24 | \ + AES_INVMIXBYTE(COL,2,3,0,1) << 16 | \ + AES_INVMIXBYTE(COL,1,2,3,0) << 8 | \ + AES_INVMIXBYTE(COL,0,1,2,3) << 0 \ +) + diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/amoadd_d.h b/vendor/riscv/riscv-isa-sim/riscv/insns/amoadd_d.h new file mode 100644 index 0000000000..8573aa50e8 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/amoadd_d.h @@ -0,0 +1,3 @@ +require_extension('A'); +require_rv64; +WRITE_RD(MMU.amo<uint64_t>(RS1, [&](uint64_t lhs) { return lhs + RS2; })); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/amoadd_w.h b/vendor/riscv/riscv-isa-sim/riscv/insns/amoadd_w.h new file mode 100644 index 0000000000..c288b3bc4d --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/amoadd_w.h @@ -0,0 +1,2 @@ +require_extension('A'); +WRITE_RD(sext32(MMU.amo<uint32_t>(RS1, [&](uint32_t lhs) { return lhs + RS2; }))); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/amoand_d.h b/vendor/riscv/riscv-isa-sim/riscv/insns/amoand_d.h new file mode 100644 index 0000000000..2df7ce2afc --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/amoand_d.h @@ -0,0 +1,3 @@ +require_extension('A'); +require_rv64; +WRITE_RD(MMU.amo<uint64_t>(RS1, [&](uint64_t lhs) { return lhs & RS2; })); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/amoand_w.h b/vendor/riscv/riscv-isa-sim/riscv/insns/amoand_w.h new file mode 100644 index 0000000000..962165f152 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/amoand_w.h @@ -0,0 +1,2 @@ +require_extension('A'); +WRITE_RD(sext32(MMU.amo<uint32_t>(RS1, [&](uint32_t lhs) { return lhs & RS2; }))); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/amomax_d.h b/vendor/riscv/riscv-isa-sim/riscv/insns/amomax_d.h new file mode 100644 index 0000000000..ab95da09e4 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/amomax_d.h @@ -0,0 +1,3 @@ +require_extension('A'); +require_rv64; +WRITE_RD(MMU.amo<uint64_t>(RS1, [&](int64_t lhs) { return std::max(lhs, int64_t(RS2)); })); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/amomax_w.h b/vendor/riscv/riscv-isa-sim/riscv/insns/amomax_w.h new file mode 100644 index 0000000000..132c2e041d --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/amomax_w.h @@ -0,0 +1,2 @@ +require_extension('A'); +WRITE_RD(sext32(MMU.amo<uint32_t>(RS1, [&](int32_t lhs) { return std::max(lhs, int32_t(RS2)); }))); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/amomaxu_d.h b/vendor/riscv/riscv-isa-sim/riscv/insns/amomaxu_d.h new file mode 100644 index 0000000000..e2371aa056 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/amomaxu_d.h @@ -0,0 +1,3 @@ +require_extension('A'); +require_rv64; +WRITE_RD(MMU.amo<uint64_t>(RS1, [&](uint64_t lhs) { return std::max(lhs, RS2); })); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/amomaxu_w.h b/vendor/riscv/riscv-isa-sim/riscv/insns/amomaxu_w.h new file mode 100644 index 0000000000..ebbdd415c8 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/amomaxu_w.h @@ -0,0 +1,2 @@ +require_extension('A'); +WRITE_RD(sext32(MMU.amo<uint32_t>(RS1, [&](uint32_t lhs) { return std::max(lhs, uint32_t(RS2)); }))); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/amomin_d.h b/vendor/riscv/riscv-isa-sim/riscv/insns/amomin_d.h new file mode 100644 index 0000000000..419e42e683 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/amomin_d.h @@ -0,0 +1,3 @@ +require_extension('A'); +require_rv64; +WRITE_RD(MMU.amo<uint64_t>(RS1, [&](int64_t lhs) { return std::min(lhs, int64_t(RS2)); })); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/amomin_w.h b/vendor/riscv/riscv-isa-sim/riscv/insns/amomin_w.h new file mode 100644 index 0000000000..749149c714 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/amomin_w.h @@ -0,0 +1,2 @@ +require_extension('A'); +WRITE_RD(sext32(MMU.amo<uint32_t>(RS1, [&](int32_t lhs) { return std::min(lhs, int32_t(RS2)); }))); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/amominu_d.h b/vendor/riscv/riscv-isa-sim/riscv/insns/amominu_d.h new file mode 100644 index 0000000000..b4bab47532 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/amominu_d.h @@ -0,0 +1,3 @@ +require_extension('A'); +require_rv64; +WRITE_RD(MMU.amo<uint64_t>(RS1, [&](uint64_t lhs) { return std::min(lhs, RS2); })); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/amominu_w.h b/vendor/riscv/riscv-isa-sim/riscv/insns/amominu_w.h new file mode 100644 index 0000000000..680eef2710 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/amominu_w.h @@ -0,0 +1,2 @@ +require_extension('A'); +WRITE_RD(sext32(MMU.amo<uint32_t>(RS1, [&](uint32_t lhs) { return std::min(lhs, uint32_t(RS2)); }))); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/amoor_d.h b/vendor/riscv/riscv-isa-sim/riscv/insns/amoor_d.h new file mode 100644 index 0000000000..c201d88a44 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/amoor_d.h @@ -0,0 +1,3 @@ +require_extension('A'); +require_rv64; +WRITE_RD(MMU.amo<uint64_t>(RS1, [&](uint64_t lhs) { return lhs | RS2; })); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/amoor_w.h b/vendor/riscv/riscv-isa-sim/riscv/insns/amoor_w.h new file mode 100644 index 0000000000..0adac5b72a --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/amoor_w.h @@ -0,0 +1,2 @@ +require_extension('A'); +WRITE_RD(sext32(MMU.amo<uint32_t>(RS1, [&](uint32_t lhs) { return lhs | RS2; }))); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/amoswap_d.h b/vendor/riscv/riscv-isa-sim/riscv/insns/amoswap_d.h new file mode 100644 index 0000000000..62a95b0a09 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/amoswap_d.h @@ -0,0 +1,3 @@ +require_extension('A'); +require_rv64; +WRITE_RD(MMU.amo<uint64_t>(RS1, [&](uint64_t UNUSED lhs) { return RS2; })); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/amoswap_w.h b/vendor/riscv/riscv-isa-sim/riscv/insns/amoswap_w.h new file mode 100644 index 0000000000..819579cddc --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/amoswap_w.h @@ -0,0 +1,2 @@ +require_extension('A'); +WRITE_RD(sext32(MMU.amo<uint32_t>(RS1, [&](uint32_t UNUSED lhs) { return RS2; }))); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/amoxor_d.h b/vendor/riscv/riscv-isa-sim/riscv/insns/amoxor_d.h new file mode 100644 index 0000000000..a40050fd07 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/amoxor_d.h @@ -0,0 +1,3 @@ +require_extension('A'); +require_rv64; +WRITE_RD(MMU.amo<uint64_t>(RS1, [&](uint64_t lhs) { return lhs ^ RS2; })); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/amoxor_w.h b/vendor/riscv/riscv-isa-sim/riscv/insns/amoxor_w.h new file mode 100644 index 0000000000..af025d6891 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/amoxor_w.h @@ -0,0 +1,2 @@ +require_extension('A'); +WRITE_RD(sext32(MMU.amo<uint32_t>(RS1, [&](uint32_t lhs) { return lhs ^ RS2; }))); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/and.h b/vendor/riscv/riscv-isa-sim/riscv/insns/and.h new file mode 100644 index 0000000000..86b488314f --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/and.h @@ -0,0 +1 @@ +WRITE_RD(RS1 & RS2); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/andi.h b/vendor/riscv/riscv-isa-sim/riscv/insns/andi.h new file mode 100644 index 0000000000..bcc51e4407 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/andi.h @@ -0,0 +1 @@ +WRITE_RD(insn.i_imm() & RS1); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/andn.h b/vendor/riscv/riscv-isa-sim/riscv/insns/andn.h new file mode 100644 index 0000000000..8add191954 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/andn.h @@ -0,0 +1,2 @@ +require_either_extension(EXT_ZBB, EXT_ZBKB); +WRITE_RD(RS1 & ~RS2); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/auipc.h b/vendor/riscv/riscv-isa-sim/riscv/insns/auipc.h new file mode 100644 index 0000000000..1a2b169b59 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/auipc.h @@ -0,0 +1 @@ +WRITE_RD(sext_xlen(insn.u_imm() + pc)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/ave.h b/vendor/riscv/riscv-isa-sim/riscv/insns/ave.h new file mode 100644 index 0000000000..599790027e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/ave.h @@ -0,0 +1,5 @@ +require_extension(EXT_ZPN); +sreg_t rs1 = RS1; +sreg_t rs2 = RS2; +sreg_t carry = (rs1 & 1) | (rs2 & 1); +WRITE_RD(sext_xlen((rs1 >> 1) + (rs2 >> 1) + carry)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/bclr.h b/vendor/riscv/riscv-isa-sim/riscv/insns/bclr.h new file mode 100644 index 0000000000..589273e640 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/bclr.h @@ -0,0 +1,3 @@ +require_extension(EXT_ZBS); +int shamt = RS2 & (xlen-1); +WRITE_RD(sext_xlen(RS1 & ~(1LL << shamt))); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/bclri.h b/vendor/riscv/riscv-isa-sim/riscv/insns/bclri.h new file mode 100644 index 0000000000..8df6a5f4e5 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/bclri.h @@ -0,0 +1,3 @@ +require_extension(EXT_ZBS); +int shamt = SHAMT & (xlen-1); +WRITE_RD(sext_xlen(RS1 & ~(1LL << shamt))); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/bcompress.h b/vendor/riscv/riscv-isa-sim/riscv/insns/bcompress.h new file mode 100644 index 0000000000..579346f463 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/bcompress.h @@ -0,0 +1,9 @@ +require_extension(EXT_XZBE); +uint64_t c = 0, i = 0, data = zext_xlen(RS1), mask = zext_xlen(RS2); +while (mask) { + uint64_t b = mask & ~((mask | (mask-1)) + 1); + c |= (data & b) >> (ctz(b) - i); + i += popcount(b); + mask -= b; +} +WRITE_RD(sext_xlen(c)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/bcompressw.h b/vendor/riscv/riscv-isa-sim/riscv/insns/bcompressw.h new file mode 100644 index 0000000000..2c1017cd17 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/bcompressw.h @@ -0,0 +1,10 @@ +require_rv64; +require_extension(EXT_XZBE); +uint64_t c = 0, i = 0, data = zext32(RS1), mask = zext32(RS2); +while (mask) { + uint64_t b = mask & ~((mask | (mask-1)) + 1); + c |= (data & b) >> (ctz(b) - i); + i += popcount(b); + mask -= b; +} +WRITE_RD(sext32(c)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/bdecompress.h b/vendor/riscv/riscv-isa-sim/riscv/insns/bdecompress.h new file mode 100644 index 0000000000..2894be0143 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/bdecompress.h @@ -0,0 +1,9 @@ +require_extension(EXT_XZBE); +uint64_t c = 0, i = 0, data = zext_xlen(RS1), mask = zext_xlen(RS2); +while (mask) { + uint64_t b = mask & ~((mask | (mask-1)) + 1); + c |= (data << (ctz(b) - i)) & b; + i += popcount(b); + mask -= b; +} +WRITE_RD(sext_xlen(c)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/bdecompressw.h b/vendor/riscv/riscv-isa-sim/riscv/insns/bdecompressw.h new file mode 100644 index 0000000000..468a7260ae --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/bdecompressw.h @@ -0,0 +1,10 @@ +require_rv64; +require_extension(EXT_XZBE); +uint64_t c = 0, i = 0, data = zext32(RS1), mask = zext32(RS2); +while (mask) { + uint64_t b = mask & ~((mask | (mask-1)) + 1); + c |= (data << (ctz(b) - i)) & b; + i += popcount(b); + mask -= b; +} +WRITE_RD(sext32(c)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/beq.h b/vendor/riscv/riscv-isa-sim/riscv/insns/beq.h new file mode 100644 index 0000000000..3d2c9758d3 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/beq.h @@ -0,0 +1,2 @@ +if (RS1 == RS2) + set_pc(BRANCH_TARGET); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/bext.h b/vendor/riscv/riscv-isa-sim/riscv/insns/bext.h new file mode 100644 index 0000000000..24c80b07df --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/bext.h @@ -0,0 +1,3 @@ +require_extension(EXT_ZBS); +int shamt = RS2 & (xlen-1); +WRITE_RD(sext_xlen(1 & (RS1 >> shamt))); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/bexti.h b/vendor/riscv/riscv-isa-sim/riscv/insns/bexti.h new file mode 100644 index 0000000000..31d2316685 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/bexti.h @@ -0,0 +1,3 @@ +require_extension(EXT_ZBS); +int shamt = SHAMT & (xlen-1); +WRITE_RD(sext_xlen(1 & (RS1 >> shamt))); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/bfp.h b/vendor/riscv/riscv-isa-sim/riscv/insns/bfp.h new file mode 100644 index 0000000000..886d840531 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/bfp.h @@ -0,0 +1,10 @@ +require_extension(EXT_XZBF); +reg_t cfg = RS2 >> (xlen/2); +if ((cfg >> 30) == 2) + cfg = cfg >> 16; +int len = (cfg >> 8) & (xlen/2-1); +int off = cfg & (xlen-1); +len = len ? len : xlen/2; +reg_t mask = ~(~reg_t(0) << len) << off; +reg_t data = RS2 << off; +WRITE_RD(sext_xlen((data & mask) | (RS1 & ~mask))); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/bfpw.h b/vendor/riscv/riscv-isa-sim/riscv/insns/bfpw.h new file mode 100644 index 0000000000..42479e72f4 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/bfpw.h @@ -0,0 +1,9 @@ +require_rv64; +require_extension(EXT_XZBF); +reg_t cfg = RS2 >> 16; +int len = (cfg >> 8) & 15; +int off = cfg & 31; +len = len ? len : 16; +reg_t mask = ~(~reg_t(0) << len) << off; +reg_t data = RS2 << off; +WRITE_RD(sext32((data & mask) | (RS1 & ~mask))); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/bge.h b/vendor/riscv/riscv-isa-sim/riscv/insns/bge.h new file mode 100644 index 0000000000..b2421c229e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/bge.h @@ -0,0 +1,2 @@ +if (sreg_t(RS1) >= sreg_t(RS2)) + set_pc(BRANCH_TARGET); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/bgeu.h b/vendor/riscv/riscv-isa-sim/riscv/insns/bgeu.h new file mode 100644 index 0000000000..f09b7f4d0d --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/bgeu.h @@ -0,0 +1,2 @@ +if (RS1 >= RS2) + set_pc(BRANCH_TARGET); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/binv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/binv.h new file mode 100644 index 0000000000..cef5b780dd --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/binv.h @@ -0,0 +1,3 @@ +require_extension(EXT_ZBS); +int shamt = RS2 & (xlen-1); +WRITE_RD(sext_xlen(RS1 ^ (1LL << shamt))); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/binvi.h b/vendor/riscv/riscv-isa-sim/riscv/insns/binvi.h new file mode 100644 index 0000000000..3272d39316 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/binvi.h @@ -0,0 +1,3 @@ +require_extension(EXT_ZBS); +int shamt = SHAMT & (xlen-1); +WRITE_RD(sext_xlen(RS1 ^ (1LL << shamt))); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/blt.h b/vendor/riscv/riscv-isa-sim/riscv/insns/blt.h new file mode 100644 index 0000000000..cad064be33 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/blt.h @@ -0,0 +1,2 @@ +if (sreg_t(RS1) < sreg_t(RS2)) + set_pc(BRANCH_TARGET); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/bltu.h b/vendor/riscv/riscv-isa-sim/riscv/insns/bltu.h new file mode 100644 index 0000000000..b7c3300b3e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/bltu.h @@ -0,0 +1,2 @@ +if (RS1 < RS2) + set_pc(BRANCH_TARGET); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/bmatflip.h b/vendor/riscv/riscv-isa-sim/riscv/insns/bmatflip.h new file mode 100644 index 0000000000..c10df8f9a1 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/bmatflip.h @@ -0,0 +1,11 @@ +require_rv64; +require_extension(EXT_XZBM); +reg_t x = RS1; +for (int i = 0; i < 3; i++) { + x = (x & 0xFFFF00000000FFFFLL) | ((x & 0x0000FFFF00000000LL) >> 16) | ((x & 0x00000000FFFF0000LL) << 16); + x = (x & 0xFF0000FFFF0000FFLL) | ((x & 0x00FF000000FF0000LL) >> 8) | ((x & 0x0000FF000000FF00LL) << 8); + x = (x & 0xF00FF00FF00FF00FLL) | ((x & 0x0F000F000F000F00LL) >> 4) | ((x & 0x00F000F000F000F0LL) << 4); + x = (x & 0xC3C3C3C3C3C3C3C3LL) | ((x & 0x3030303030303030LL) >> 2) | ((x & 0x0C0C0C0C0C0C0C0CLL) << 2); + x = (x & 0x9999999999999999LL) | ((x & 0x4444444444444444LL) >> 1) | ((x & 0x2222222222222222LL) << 1); +} +WRITE_RD(sext_xlen(x)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/bmator.h b/vendor/riscv/riscv-isa-sim/riscv/insns/bmator.h new file mode 100644 index 0000000000..33057ca04e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/bmator.h @@ -0,0 +1,29 @@ +require_rv64; +require_extension(EXT_XZBM); + +// transpose of rs2 +int64_t rs2t = RS2; +for (int i = 0; i < 3; i++) { + rs2t = (rs2t & 0xFFFF00000000FFFFLL) | ((rs2t & 0x0000FFFF00000000LL) >> 16) | ((rs2t & 0x00000000FFFF0000LL) << 16); + rs2t = (rs2t & 0xFF0000FFFF0000FFLL) | ((rs2t & 0x00FF000000FF0000LL) >> 8) | ((rs2t & 0x0000FF000000FF00LL) << 8); + rs2t = (rs2t & 0xF00FF00FF00FF00FLL) | ((rs2t & 0x0F000F000F000F00LL) >> 4) | ((rs2t & 0x00F000F000F000F0LL) << 4); + rs2t = (rs2t & 0xC3C3C3C3C3C3C3C3LL) | ((rs2t & 0x3030303030303030LL) >> 2) | ((rs2t & 0x0C0C0C0C0C0C0C0CLL) << 2); + rs2t = (rs2t & 0x9999999999999999LL) | ((rs2t & 0x4444444444444444LL) >> 1) | ((rs2t & 0x2222222222222222LL) << 1); +} + +int64_t rs1 = RS1; +uint8_t u[8]; // rows of rs1 +uint8_t v[8]; // cols of rs2 + +for (int i = 0; i < 8; i++) { + u[i] = rs1 >> (i*8); + v[i] = rs2t >> (i*8); +} + +uint64_t x = 0; +for (int i = 0; i < 64; i++) { + if ((u[i / 8] & v[i % 8]) != 0) + x |= 1LL << i; +} + +WRITE_RD(sext_xlen(x)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/bmatxor.h b/vendor/riscv/riscv-isa-sim/riscv/insns/bmatxor.h new file mode 100644 index 0000000000..ca2d096715 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/bmatxor.h @@ -0,0 +1,29 @@ +require_rv64; +require_extension(EXT_XZBM); + +// transpose of rs2 +int64_t rs2t = RS2; +for (int i = 0; i < 3; i++) { + rs2t = (rs2t & 0xFFFF00000000FFFFLL) | ((rs2t & 0x0000FFFF00000000LL) >> 16) | ((rs2t & 0x00000000FFFF0000LL) << 16); + rs2t = (rs2t & 0xFF0000FFFF0000FFLL) | ((rs2t & 0x00FF000000FF0000LL) >> 8) | ((rs2t & 0x0000FF000000FF00LL) << 8); + rs2t = (rs2t & 0xF00FF00FF00FF00FLL) | ((rs2t & 0x0F000F000F000F00LL) >> 4) | ((rs2t & 0x00F000F000F000F0LL) << 4); + rs2t = (rs2t & 0xC3C3C3C3C3C3C3C3LL) | ((rs2t & 0x3030303030303030LL) >> 2) | ((rs2t & 0x0C0C0C0C0C0C0C0CLL) << 2); + rs2t = (rs2t & 0x9999999999999999LL) | ((rs2t & 0x4444444444444444LL) >> 1) | ((rs2t & 0x2222222222222222LL) << 1); +} + +int64_t rs1 = RS1; +uint8_t u[8]; // rows of rs1 +uint8_t v[8]; // cols of rs2 + +for (int i = 0; i < 8; i++) { + u[i] = rs1 >> (i*8); + v[i] = rs2t >> (i*8); +} + +uint64_t x = 0; +for (int i = 0; i < 64; i++) { + if (popcount(u[i / 8] & v[i % 8]) & 1) + x |= 1LL << i; +} + +WRITE_RD(sext_xlen(x)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/bne.h b/vendor/riscv/riscv-isa-sim/riscv/insns/bne.h new file mode 100644 index 0000000000..e832fa14e9 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/bne.h @@ -0,0 +1,2 @@ +if (RS1 != RS2) + set_pc(BRANCH_TARGET); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/bset.h b/vendor/riscv/riscv-isa-sim/riscv/insns/bset.h new file mode 100644 index 0000000000..9009fb328a --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/bset.h @@ -0,0 +1,3 @@ +require_extension(EXT_ZBS); +int shamt = RS2 & (xlen-1); +WRITE_RD(sext_xlen(RS1 | (1LL << shamt))); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/bseti.h b/vendor/riscv/riscv-isa-sim/riscv/insns/bseti.h new file mode 100644 index 0000000000..495237863c --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/bseti.h @@ -0,0 +1,3 @@ +require_extension(EXT_ZBS); +int shamt = SHAMT & (xlen-1); +WRITE_RD(sext_xlen(RS1 | (1LL << shamt))); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/c_add.h b/vendor/riscv/riscv-isa-sim/riscv/insns/c_add.h new file mode 100644 index 0000000000..796e634a47 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/c_add.h @@ -0,0 +1,3 @@ +require_extension(EXT_ZCA); +require(insn.rvc_rs2() != 0); +WRITE_RD(sext_xlen(RVC_RS1 + RVC_RS2)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/c_addi.h b/vendor/riscv/riscv-isa-sim/riscv/insns/c_addi.h new file mode 100644 index 0000000000..62d0639927 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/c_addi.h @@ -0,0 +1,2 @@ +require_extension(EXT_ZCA); +WRITE_RD(sext_xlen(RVC_RS1 + insn.rvc_imm())); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/c_addi4spn.h b/vendor/riscv/riscv-isa-sim/riscv/insns/c_addi4spn.h new file mode 100644 index 0000000000..a1d5425ebe --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/c_addi4spn.h @@ -0,0 +1,3 @@ +require_extension(EXT_ZCA); +require(insn.rvc_addi4spn_imm() != 0); +WRITE_RVC_RS2S(sext_xlen(RVC_SP + insn.rvc_addi4spn_imm())); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/c_addw.h b/vendor/riscv/riscv-isa-sim/riscv/insns/c_addw.h new file mode 100644 index 0000000000..bd64b1e7a4 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/c_addw.h @@ -0,0 +1,3 @@ +require_extension(EXT_ZCA); +require_rv64; +WRITE_RVC_RS1S(sext32(RVC_RS1S + RVC_RS2S)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/c_and.h b/vendor/riscv/riscv-isa-sim/riscv/insns/c_and.h new file mode 100644 index 0000000000..9054e05dfe --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/c_and.h @@ -0,0 +1,2 @@ +require_extension(EXT_ZCA); +WRITE_RVC_RS1S(RVC_RS1S & RVC_RS2S); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/c_andi.h b/vendor/riscv/riscv-isa-sim/riscv/insns/c_andi.h new file mode 100644 index 0000000000..156e4405cc --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/c_andi.h @@ -0,0 +1,2 @@ +require_extension(EXT_ZCA); +WRITE_RVC_RS1S(RVC_RS1S & insn.rvc_imm()); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/c_beqz.h b/vendor/riscv/riscv-isa-sim/riscv/insns/c_beqz.h new file mode 100644 index 0000000000..65bdcf6ab9 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/c_beqz.h @@ -0,0 +1,3 @@ +require_extension(EXT_ZCA); +if (RVC_RS1S == 0) + set_pc(pc + insn.rvc_b_imm()); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/c_bnez.h b/vendor/riscv/riscv-isa-sim/riscv/insns/c_bnez.h new file mode 100644 index 0000000000..2a2e9a9ac3 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/c_bnez.h @@ -0,0 +1,3 @@ +require_extension(EXT_ZCA); +if (RVC_RS1S != 0) + set_pc(pc + insn.rvc_b_imm()); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/c_ebreak.h b/vendor/riscv/riscv-isa-sim/riscv/insns/c_ebreak.h new file mode 100644 index 0000000000..14b5136310 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/c_ebreak.h @@ -0,0 +1,9 @@ +require_extension(EXT_ZCA); +if (!STATE.debug_mode && + ((STATE.prv == PRV_M && STATE.dcsr->ebreakm) || + (STATE.prv == PRV_S && STATE.dcsr->ebreaks) || + (STATE.prv == PRV_U && STATE.dcsr->ebreaku))) { + throw trap_debug_mode(); +} else { + throw trap_breakpoint(STATE.v, pc); +} diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/c_fld.h b/vendor/riscv/riscv-isa-sim/riscv/insns/c_fld.h new file mode 100644 index 0000000000..dac173826f --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/c_fld.h @@ -0,0 +1,3 @@ +require_extension(EXT_ZCD); +require_fp; +WRITE_RVC_FRS2S(f64(MMU.load<uint64_t>(RVC_RS1S + insn.rvc_ld_imm()))); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/c_fldsp.h b/vendor/riscv/riscv-isa-sim/riscv/insns/c_fldsp.h new file mode 100644 index 0000000000..b49a88a6ef --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/c_fldsp.h @@ -0,0 +1,3 @@ +require_extension(EXT_ZCD); +require_fp; +WRITE_FRD(f64(MMU.load<uint64_t>(RVC_SP + insn.rvc_ldsp_imm()))); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/c_flw.h b/vendor/riscv/riscv-isa-sim/riscv/insns/c_flw.h new file mode 100644 index 0000000000..95ae260282 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/c_flw.h @@ -0,0 +1,8 @@ +if (xlen == 32) { + require_extension(EXT_ZCF); + require_fp; + WRITE_RVC_FRS2S(f32(MMU.load<uint32_t>(RVC_RS1S + insn.rvc_lw_imm()))); +} else { // c.ld + require_extension(EXT_ZCA); + WRITE_RVC_RS2S(MMU.load<int64_t>(RVC_RS1S + insn.rvc_ld_imm())); +} diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/c_flwsp.h b/vendor/riscv/riscv-isa-sim/riscv/insns/c_flwsp.h new file mode 100644 index 0000000000..eea0ec53ca --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/c_flwsp.h @@ -0,0 +1,9 @@ +if (xlen == 32) { + require_extension(EXT_ZCF); + require_fp; + WRITE_FRD(f32(MMU.load<uint32_t>(RVC_SP + insn.rvc_lwsp_imm()))); +} else { // c.ldsp + require_extension(EXT_ZCA); + require(insn.rvc_rd() != 0); + WRITE_RD(MMU.load<int64_t>(RVC_SP + insn.rvc_ldsp_imm())); +} diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/c_fsd.h b/vendor/riscv/riscv-isa-sim/riscv/insns/c_fsd.h new file mode 100644 index 0000000000..d86b47e4cf --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/c_fsd.h @@ -0,0 +1,3 @@ +require_extension(EXT_ZCD); +require_fp; +MMU.store<uint64_t>(RVC_RS1S + insn.rvc_ld_imm(), RVC_FRS2S.v[0]); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/c_fsdsp.h b/vendor/riscv/riscv-isa-sim/riscv/insns/c_fsdsp.h new file mode 100644 index 0000000000..980dbc4c54 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/c_fsdsp.h @@ -0,0 +1,3 @@ +require_extension(EXT_ZCD); +require_fp; +MMU.store<uint64_t>(RVC_SP + insn.rvc_sdsp_imm(), RVC_FRS2.v[0]); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/c_fsw.h b/vendor/riscv/riscv-isa-sim/riscv/insns/c_fsw.h new file mode 100644 index 0000000000..d7d6fed365 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/c_fsw.h @@ -0,0 +1,8 @@ +if (xlen == 32) { + require_extension(EXT_ZCF); + require_fp; + MMU.store<uint32_t>(RVC_RS1S + insn.rvc_lw_imm(), RVC_FRS2S.v[0]); +} else { // c.sd + require_extension(EXT_ZCA); + MMU.store<uint64_t>(RVC_RS1S + insn.rvc_ld_imm(), RVC_RS2S); +} diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/c_fswsp.h b/vendor/riscv/riscv-isa-sim/riscv/insns/c_fswsp.h new file mode 100644 index 0000000000..5952251074 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/c_fswsp.h @@ -0,0 +1,8 @@ +if (xlen == 32) { + require_extension(EXT_ZCF); + require_fp; + MMU.store<uint32_t>(RVC_SP + insn.rvc_swsp_imm(), RVC_FRS2.v[0]); +} else { // c.sdsp + require_extension(EXT_ZCA); + MMU.store<uint64_t>(RVC_SP + insn.rvc_sdsp_imm(), RVC_RS2); +} diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/c_j.h b/vendor/riscv/riscv-isa-sim/riscv/insns/c_j.h new file mode 100644 index 0000000000..a2712c322d --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/c_j.h @@ -0,0 +1,2 @@ +require_extension(EXT_ZCA); +set_pc(pc + insn.rvc_j_imm()); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/c_jal.h b/vendor/riscv/riscv-isa-sim/riscv/insns/c_jal.h new file mode 100644 index 0000000000..49e20f4b67 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/c_jal.h @@ -0,0 +1,9 @@ +require_extension(EXT_ZCA); +if (xlen == 32) { + reg_t tmp = npc; + set_pc(pc + insn.rvc_j_imm()); + WRITE_REG(X_RA, tmp); +} else { // c.addiw + require(insn.rvc_rd() != 0); + WRITE_RD(sext32(RVC_RS1 + insn.rvc_imm())); +} diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/c_jalr.h b/vendor/riscv/riscv-isa-sim/riscv/insns/c_jalr.h new file mode 100644 index 0000000000..0a00f1cc03 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/c_jalr.h @@ -0,0 +1,5 @@ +require_extension(EXT_ZCA); +require(insn.rvc_rs1() != 0); +reg_t tmp = npc; +set_pc(RVC_RS1 & ~reg_t(1)); +WRITE_REG(X_RA, tmp); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/c_jr.h b/vendor/riscv/riscv-isa-sim/riscv/insns/c_jr.h new file mode 100644 index 0000000000..020cafd817 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/c_jr.h @@ -0,0 +1,3 @@ +require_extension(EXT_ZCA); +require(insn.rvc_rs1() != 0); +set_pc(RVC_RS1 & ~reg_t(1)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/c_lbu.h b/vendor/riscv/riscv-isa-sim/riscv/insns/c_lbu.h new file mode 100644 index 0000000000..e8fb380c9c --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/c_lbu.h @@ -0,0 +1,2 @@ +require_extension(EXT_ZCB); +WRITE_RVC_RS2S(MMU.load<uint8_t>(RVC_RS1S + insn.rvc_lbimm())); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/c_lh.h b/vendor/riscv/riscv-isa-sim/riscv/insns/c_lh.h new file mode 100644 index 0000000000..6a00146cf9 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/c_lh.h @@ -0,0 +1,2 @@ +require_extension(EXT_ZCB); +WRITE_RVC_RS2S(MMU.load<int16_t>(RVC_RS1S + insn.rvc_lhimm())); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/c_lhu.h b/vendor/riscv/riscv-isa-sim/riscv/insns/c_lhu.h new file mode 100644 index 0000000000..fb190c5506 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/c_lhu.h @@ -0,0 +1,2 @@ +require_extension(EXT_ZCB); +WRITE_RVC_RS2S(MMU.load<uint16_t>(RVC_RS1S + insn.rvc_lhimm())); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/c_li.h b/vendor/riscv/riscv-isa-sim/riscv/insns/c_li.h new file mode 100644 index 0000000000..bfe16a2b09 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/c_li.h @@ -0,0 +1,2 @@ +require_extension(EXT_ZCA); +WRITE_RD(insn.rvc_imm()); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/c_lui.h b/vendor/riscv/riscv-isa-sim/riscv/insns/c_lui.h new file mode 100644 index 0000000000..956fa448bc --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/c_lui.h @@ -0,0 +1,8 @@ +require_extension(EXT_ZCA); +if (insn.rvc_rd() == 2) { // c.addi16sp + require(insn.rvc_addi16sp_imm() != 0); + WRITE_REG(X_SP, sext_xlen(RVC_SP + insn.rvc_addi16sp_imm())); +} else { + require(insn.rvc_imm() != 0); + WRITE_RD(insn.rvc_imm() << 12); +} diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/c_lw.h b/vendor/riscv/riscv-isa-sim/riscv/insns/c_lw.h new file mode 100644 index 0000000000..63b708c9ad --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/c_lw.h @@ -0,0 +1,2 @@ +require_extension(EXT_ZCA); +WRITE_RVC_RS2S(MMU.load<int32_t>(RVC_RS1S + insn.rvc_lw_imm())); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/c_lwsp.h b/vendor/riscv/riscv-isa-sim/riscv/insns/c_lwsp.h new file mode 100644 index 0000000000..de23cd9701 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/c_lwsp.h @@ -0,0 +1,3 @@ +require_extension(EXT_ZCA); +require(insn.rvc_rd() != 0); +WRITE_RD(MMU.load<int32_t>(RVC_SP + insn.rvc_lwsp_imm())); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/c_mul.h b/vendor/riscv/riscv-isa-sim/riscv/insns/c_mul.h new file mode 100644 index 0000000000..3ac0b01b32 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/c_mul.h @@ -0,0 +1,3 @@ +require_extension(EXT_ZCB); +require_either_extension('M', EXT_ZMMUL); +WRITE_RVC_RS1S(sext_xlen(RVC_RS1S * RVC_RS2S)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/c_mv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/c_mv.h new file mode 100644 index 0000000000..b227005e40 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/c_mv.h @@ -0,0 +1,3 @@ +require_extension(EXT_ZCA); +require(insn.rvc_rs2() != 0); +WRITE_RD(RVC_RS2); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/c_not.h b/vendor/riscv/riscv-isa-sim/riscv/insns/c_not.h new file mode 100644 index 0000000000..26c1626d24 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/c_not.h @@ -0,0 +1,2 @@ +require_extension(EXT_ZCB); +WRITE_RVC_RS1S(sext_xlen(~RVC_RS1S)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/c_or.h b/vendor/riscv/riscv-isa-sim/riscv/insns/c_or.h new file mode 100644 index 0000000000..736ec997c6 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/c_or.h @@ -0,0 +1,2 @@ +require_extension(EXT_ZCA); +WRITE_RVC_RS1S(RVC_RS1S | RVC_RS2S); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/c_sb.h b/vendor/riscv/riscv-isa-sim/riscv/insns/c_sb.h new file mode 100644 index 0000000000..5badc28c99 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/c_sb.h @@ -0,0 +1,2 @@ +require_extension(EXT_ZCB); +MMU.store<uint8_t>(RVC_RS1S + insn.rvc_lbimm(), RVC_RS2S); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/c_sext_b.h b/vendor/riscv/riscv-isa-sim/riscv/insns/c_sext_b.h new file mode 100644 index 0000000000..dca6af1a2b --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/c_sext_b.h @@ -0,0 +1,3 @@ +require_extension(EXT_ZCB); +require_extension(EXT_ZBB); +WRITE_RVC_RS1S((sreg_t)(int8_t)(RVC_RS1S)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/c_sext_h.h b/vendor/riscv/riscv-isa-sim/riscv/insns/c_sext_h.h new file mode 100644 index 0000000000..b286d07695 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/c_sext_h.h @@ -0,0 +1,3 @@ +require_extension(EXT_ZCB); +require_extension(EXT_ZBB); +WRITE_RVC_RS1S((sreg_t)(int16_t)(RVC_RS1S)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/c_sh.h b/vendor/riscv/riscv-isa-sim/riscv/insns/c_sh.h new file mode 100644 index 0000000000..271ca09db6 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/c_sh.h @@ -0,0 +1,2 @@ +require_extension(EXT_ZCB); +MMU.store<uint16_t>(RVC_RS1S + insn.rvc_lhimm(), RVC_RS2S); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/c_slli.h b/vendor/riscv/riscv-isa-sim/riscv/insns/c_slli.h new file mode 100644 index 0000000000..1358d4d21d --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/c_slli.h @@ -0,0 +1,3 @@ +require_extension(EXT_ZCA); +require(insn.rvc_zimm() < xlen); +WRITE_RD(sext_xlen(RVC_RS1 << insn.rvc_zimm())); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/c_srai.h b/vendor/riscv/riscv-isa-sim/riscv/insns/c_srai.h new file mode 100644 index 0000000000..8f25e39c8d --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/c_srai.h @@ -0,0 +1,3 @@ +require_extension(EXT_ZCA); +require(insn.rvc_zimm() < xlen); +WRITE_RVC_RS1S(sext_xlen(sext_xlen(RVC_RS1S) >> insn.rvc_zimm())); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/c_srli.h b/vendor/riscv/riscv-isa-sim/riscv/insns/c_srli.h new file mode 100644 index 0000000000..de08031215 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/c_srli.h @@ -0,0 +1,3 @@ +require_extension(EXT_ZCA); +require(insn.rvc_zimm() < xlen); +WRITE_RVC_RS1S(sext_xlen(zext_xlen(RVC_RS1S) >> insn.rvc_zimm())); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/c_sub.h b/vendor/riscv/riscv-isa-sim/riscv/insns/c_sub.h new file mode 100644 index 0000000000..2a9d51b6e1 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/c_sub.h @@ -0,0 +1,2 @@ +require_extension(EXT_ZCA); +WRITE_RVC_RS1S(sext_xlen(RVC_RS1S - RVC_RS2S)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/c_subw.h b/vendor/riscv/riscv-isa-sim/riscv/insns/c_subw.h new file mode 100644 index 0000000000..80999735b6 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/c_subw.h @@ -0,0 +1,3 @@ +require_extension(EXT_ZCA); +require_rv64; +WRITE_RVC_RS1S(sext32(RVC_RS1S - RVC_RS2S)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/c_sw.h b/vendor/riscv/riscv-isa-sim/riscv/insns/c_sw.h new file mode 100644 index 0000000000..5fdf4a166f --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/c_sw.h @@ -0,0 +1,2 @@ +require_extension(EXT_ZCA); +MMU.store<uint32_t>(RVC_RS1S + insn.rvc_lw_imm(), RVC_RS2S); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/c_swsp.h b/vendor/riscv/riscv-isa-sim/riscv/insns/c_swsp.h new file mode 100644 index 0000000000..d6684fda13 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/c_swsp.h @@ -0,0 +1,2 @@ +require_extension(EXT_ZCA); +MMU.store<uint32_t>(RVC_SP + insn.rvc_swsp_imm(), RVC_RS2); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/c_xor.h b/vendor/riscv/riscv-isa-sim/riscv/insns/c_xor.h new file mode 100644 index 0000000000..7fd72ec9cc --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/c_xor.h @@ -0,0 +1,2 @@ +require_extension(EXT_ZCA); +WRITE_RVC_RS1S(RVC_RS1S ^ RVC_RS2S); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/c_zext_b.h b/vendor/riscv/riscv-isa-sim/riscv/insns/c_zext_b.h new file mode 100644 index 0000000000..71c518e660 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/c_zext_b.h @@ -0,0 +1,2 @@ +require_extension(EXT_ZCB); +WRITE_RVC_RS1S((reg_t)(uint8_t)(RVC_RS1S)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/c_zext_h.h b/vendor/riscv/riscv-isa-sim/riscv/insns/c_zext_h.h new file mode 100644 index 0000000000..6b8fd8fb01 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/c_zext_h.h @@ -0,0 +1,3 @@ +require_extension(EXT_ZCB); +require_extension(EXT_ZBB); +WRITE_RVC_RS1S((reg_t)(uint16_t)(RVC_RS1S)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/c_zext_w.h b/vendor/riscv/riscv-isa-sim/riscv/insns/c_zext_w.h new file mode 100644 index 0000000000..1ad12a4a47 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/c_zext_w.h @@ -0,0 +1,4 @@ +require_extension(EXT_ZCB); +require_extension(EXT_ZBA); +require_rv64; +WRITE_RVC_RS1S((reg_t)(uint32_t)(RVC_RS1S)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/cbo_clean.h b/vendor/riscv/riscv-isa-sim/riscv/insns/cbo_clean.h new file mode 100644 index 0000000000..201fa4476a --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/cbo_clean.h @@ -0,0 +1,4 @@ +require_extension(EXT_ZICBOM); +DECLARE_XENVCFG_VARS(CBCFE); +require_envcfg(CBCFE); +MMU.clean_inval(RS1, true, false); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/cbo_flush.h b/vendor/riscv/riscv-isa-sim/riscv/insns/cbo_flush.h new file mode 100644 index 0000000000..b17f5cf1aa --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/cbo_flush.h @@ -0,0 +1,4 @@ +require_extension(EXT_ZICBOM); +DECLARE_XENVCFG_VARS(CBCFE); +require_envcfg(CBCFE); +MMU.clean_inval(RS1, true, true); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/cbo_inval.h b/vendor/riscv/riscv-isa-sim/riscv/insns/cbo_inval.h new file mode 100644 index 0000000000..bd80a6fd2b --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/cbo_inval.h @@ -0,0 +1,9 @@ +require_extension(EXT_ZICBOM); +DECLARE_XENVCFG_VARS(CBIE); +require_envcfg(CBIE); +if (((STATE.prv != PRV_M) && (mCBIE == 1)) || + ((!STATE.v && (STATE.prv == PRV_U)) && (sCBIE = 1)) || + (STATE.v && ((hCBIE == 1) || ((STATE.prv == PRV_U) && (sCBIE== 0))))) + MMU.clean_inval(RS1, true, true); +else + MMU.clean_inval(RS1, false, true); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/cbo_zero.h b/vendor/riscv/riscv-isa-sim/riscv/insns/cbo_zero.h new file mode 100644 index 0000000000..4bbe28d3e6 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/cbo_zero.h @@ -0,0 +1,4 @@ +require_extension(EXT_ZICBOZ); +DECLARE_XENVCFG_VARS(CBZE); +require_envcfg(CBZE); +MMU.cbo_zero(RS1); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/clmul.h b/vendor/riscv/riscv-isa-sim/riscv/insns/clmul.h new file mode 100644 index 0000000000..b8e6d6d4c0 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/clmul.h @@ -0,0 +1,6 @@ +require_either_extension(EXT_ZBC, EXT_ZBKC); +reg_t a = zext_xlen(RS1), b = zext_xlen(RS2), x = 0; +for (int i = 0; i < xlen; i++) + if ((b >> i) & 1) + x ^= a << i; +WRITE_RD(sext_xlen(x)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/clmulh.h b/vendor/riscv/riscv-isa-sim/riscv/insns/clmulh.h new file mode 100644 index 0000000000..dfee94e29b --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/clmulh.h @@ -0,0 +1,6 @@ +require_either_extension(EXT_ZBC, EXT_ZBKC); +reg_t a = zext_xlen(RS1), b = zext_xlen(RS2), x = 0; +for (int i = 1; i < xlen; i++) + if ((b >> i) & 1) + x ^= a >> (xlen-i); +WRITE_RD(sext_xlen(x)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/clmulhw.h b/vendor/riscv/riscv-isa-sim/riscv/insns/clmulhw.h new file mode 100644 index 0000000000..f41acb0e83 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/clmulhw.h @@ -0,0 +1,6 @@ +require_extension(EXT_XZBC); +reg_t a = zext32(RS1), b = zext32(RS2), x = 0; +for (int i = 1; i < 32; i++) + if ((b >> i) & 1) + x ^= a >> (32-i); +WRITE_RD(sext32(x)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/clmulr.h b/vendor/riscv/riscv-isa-sim/riscv/insns/clmulr.h new file mode 100644 index 0000000000..ffa046d258 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/clmulr.h @@ -0,0 +1,6 @@ +require_extension(EXT_ZBC); +reg_t a = zext_xlen(RS1), b = zext_xlen(RS2), x = 0; +for (int i = 0; i < xlen; i++) + if ((b >> i) & 1) + x ^= a >> (xlen-i-1); +WRITE_RD(sext_xlen(x)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/clmulrw.h b/vendor/riscv/riscv-isa-sim/riscv/insns/clmulrw.h new file mode 100644 index 0000000000..784859ae74 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/clmulrw.h @@ -0,0 +1,6 @@ +require_extension(EXT_XZBC); +reg_t a = zext32(RS1), b = zext32(RS2), x = 0; +for (int i = 0; i < 32; i++) + if ((b >> i) & 1) + x ^= a >> (31-i); +WRITE_RD(sext32(x)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/clmulw.h b/vendor/riscv/riscv-isa-sim/riscv/insns/clmulw.h new file mode 100644 index 0000000000..5bb753fe3d --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/clmulw.h @@ -0,0 +1,6 @@ +require_extension(EXT_XZBC); +reg_t a = zext32(RS1), b = zext32(RS2), x = 0; +for (int i = 0; i < 32; i++) + if ((b >> i) & 1) + x ^= a << i; +WRITE_RD(sext32(x)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/clo16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/clo16.h new file mode 100644 index 0000000000..9da659930e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/clo16.h @@ -0,0 +1,11 @@ +P_ONE_LOOP(16, { + pd = 0; + ps1 = ~ps1; + if (!ps1) pd = 16; + else { + if ((ps1 & 0xFF00) == 0) { pd += 8; ps1 <<= 8; } + if ((ps1 & 0xF000) == 0) { pd += 4; ps1 <<= 4; } + if ((ps1 & 0xC000) == 0) { pd += 2; ps1 <<= 2; } + if ((ps1 & 0x8000) == 0) { pd += 1; } + } +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/clo32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/clo32.h new file mode 100644 index 0000000000..431bb0e9c3 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/clo32.h @@ -0,0 +1,12 @@ +P_ONE_LOOP(32, { + pd = 0; + ps1 = ~ps1; + if (!ps1) pd = 32; + else { + if ((ps1 & 0xFFFF0000) == 0) { pd += 16; ps1 <<= 16; } + if ((ps1 & 0xFF000000) == 0) { pd += 8; ps1 <<= 8; } + if ((ps1 & 0xF0000000) == 0) { pd += 4; ps1 <<= 4; } + if ((ps1 & 0xC0000000) == 0) { pd += 2; ps1 <<= 2; } + if ((ps1 & 0x80000000) == 0) { pd += 1; } + } +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/clo8.h b/vendor/riscv/riscv-isa-sim/riscv/insns/clo8.h new file mode 100644 index 0000000000..2581adec8a --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/clo8.h @@ -0,0 +1,10 @@ +P_ONE_LOOP(8, { + pd = 0; + ps1 = ~ps1; + if (!ps1) pd = 8; + else { + if ((ps1 & 0xF0) == 0) { pd += 4; ps1 <<= 4; } + if ((ps1 & 0xC0) == 0) { pd += 2; ps1 <<= 2; } + if ((ps1 & 0x80) == 0) { pd += 1; } + } +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/clrs16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/clrs16.h new file mode 100644 index 0000000000..65412629da --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/clrs16.h @@ -0,0 +1,12 @@ +P_ONE_LOOP(16, { + pd = 0; + if (ps1 < 0) ps1 = ~ps1; + if (!ps1) pd = 16; + else { + if ((ps1 & 0xFF00) == 0) { pd += 8; ps1 <<= 8; } + if ((ps1 & 0xF000) == 0) { pd += 4; ps1 <<= 4; } + if ((ps1 & 0xC000) == 0) { pd += 2; ps1 <<= 2; } + if ((ps1 & 0x8000) == 0) { pd += 1; } + } + pd -= 1; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/clrs32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/clrs32.h new file mode 100644 index 0000000000..c75db18098 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/clrs32.h @@ -0,0 +1,13 @@ +P_ONE_LOOP(32, { + pd = 0; + if (ps1 < 0) ps1 = ~ps1; + if (!ps1) pd = 32; + else { + if ((ps1 & 0xFFFF0000) == 0) { pd += 16; ps1 <<= 16; } + if ((ps1 & 0xFF000000) == 0) { pd += 8; ps1 <<= 8; } + if ((ps1 & 0xF0000000) == 0) { pd += 4; ps1 <<= 4; } + if ((ps1 & 0xC0000000) == 0) { pd += 2; ps1 <<= 2; } + if ((ps1 & 0x80000000) == 0) { pd += 1; } + } + pd -= 1; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/clrs8.h b/vendor/riscv/riscv-isa-sim/riscv/insns/clrs8.h new file mode 100644 index 0000000000..f6f8298799 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/clrs8.h @@ -0,0 +1,11 @@ +P_ONE_LOOP(8, { + pd = 0; + if (ps1 < 0) ps1 = ~ps1; + if (!ps1) pd = 8; + else { + if ((ps1 & 0xF0) == 0) { pd += 4; ps1 <<= 4; } + if ((ps1 & 0xC0) == 0) { pd += 2; ps1 <<= 2; } + if ((ps1 & 0x80) == 0) { pd += 1; } + } + pd -= 1; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/clz.h b/vendor/riscv/riscv-isa-sim/riscv/insns/clz.h new file mode 100644 index 0000000000..e10e4d2d84 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/clz.h @@ -0,0 +1,5 @@ +require_either_extension(xlen == 32 ? EXT_ZBPBO : EXT_ZBB, EXT_ZBB); +reg_t x = xlen; +for (int i = 0; i < xlen; i++) + if (1 & (RS1 >> (xlen-i-1))) { x = i; break; } +WRITE_RD(sext_xlen(x)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/clz16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/clz16.h new file mode 100644 index 0000000000..a129d59ac6 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/clz16.h @@ -0,0 +1,10 @@ +P_ONE_LOOP(16, { + pd = 0; + if (ps1 == 0) pd = 16; + else { + if ((ps1 & 0xFF00) == 0) { pd += 8; ps1 <<= 8; } + if ((ps1 & 0xF000) == 0) { pd += 4; ps1 <<= 4; } + if ((ps1 & 0xC000) == 0) { pd += 2; ps1 <<= 2; } + if ((ps1 & 0x8000) == 0) { pd += 1; } + } +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/clz32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/clz32.h new file mode 100644 index 0000000000..a38dda76e6 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/clz32.h @@ -0,0 +1,12 @@ +require_rv64; +P_ONE_LOOP(32, { + pd = 0; + if (ps1 == 0) pd = 32; + else { + if ((ps1 & 0xFFFF0000) == 0) { pd += 16; ps1 <<= 16; } + if ((ps1 & 0xFF000000) == 0) { pd += 8; ps1 <<= 8; } + if ((ps1 & 0xF0000000) == 0) { pd += 4; ps1 <<= 4; } + if ((ps1 & 0xC0000000) == 0) { pd += 2; ps1 <<= 2; } + if ((ps1 & 0x80000000) == 0) { pd += 1; } + } +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/clz8.h b/vendor/riscv/riscv-isa-sim/riscv/insns/clz8.h new file mode 100644 index 0000000000..78ff6b7bfb --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/clz8.h @@ -0,0 +1,9 @@ +P_ONE_LOOP(8, { + pd = 0; + if (ps1 == 0) pd = 8; + else { + if ((ps1 & 0xF0) == 0) { pd += 4; ps1 <<= 4; } + if ((ps1 & 0xC0) == 0) { pd += 2; ps1 <<= 2; } + if ((ps1 & 0x80) == 0) { pd += 1; } + } +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/clzw.h b/vendor/riscv/riscv-isa-sim/riscv/insns/clzw.h new file mode 100644 index 0000000000..46816e77b2 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/clzw.h @@ -0,0 +1,6 @@ +require_rv64; +require_extension(EXT_ZBB); +reg_t x = 32; +for (int i = 0; i < 32; i++) + if (1 & (RS1 >> (31-i))) { x = i; break; } +WRITE_RD(sext32(x)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/cm_jalt.h b/vendor/riscv/riscv-isa-sim/riscv/insns/cm_jalt.h new file mode 100644 index 0000000000..be88dc401f --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/cm_jalt.h @@ -0,0 +1,23 @@ +require_extension(EXT_ZCMT); +STATE.jvt->verify_permissions(insn, false); +reg_t jvt = STATE.jvt->read(); +uint8_t mode = get_field(jvt, JVT_MODE); +reg_t base = jvt & JVT_BASE; +reg_t index = insn.rvc_index(); +reg_t target; +switch (mode) { +case 0: // jump table mode + if (xlen == 32) + target = MMU.fetch_jump_table<int32_t>(base + (index << 2)); + else // xlen = 64 + target = MMU.fetch_jump_table<int64_t>(base + (index << 3)); + + if (index >= 32) // cm.jalt + WRITE_REG(1, npc); + + set_pc(target & ~reg_t(1)); + break; +default: + require(0); + break; +} diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/cm_mva01s.h b/vendor/riscv/riscv-isa-sim/riscv/insns/cm_mva01s.h new file mode 100644 index 0000000000..6504caef7f --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/cm_mva01s.h @@ -0,0 +1,3 @@ +require_extension(EXT_ZCMP); +WRITE_REG(X_A0, READ_REG(RVC_R1S)); +WRITE_REG(X_A1, READ_REG(RVC_R2S)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/cm_mvsa01.h b/vendor/riscv/riscv-isa-sim/riscv/insns/cm_mvsa01.h new file mode 100644 index 0000000000..221489705c --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/cm_mvsa01.h @@ -0,0 +1,4 @@ +require_extension(EXT_ZCMP); +require(insn.rvc_r1sc() != insn.rvc_r2sc()); +WRITE_REG(RVC_R1S, READ_REG(X_A0)); +WRITE_REG(RVC_R2S, READ_REG(X_A1)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/cm_pop.h b/vendor/riscv/riscv-isa-sim/riscv/insns/cm_pop.h new file mode 100644 index 0000000000..0563bf53d4 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/cm_pop.h @@ -0,0 +1,17 @@ +require_zcmp_pushpop; + +const auto new_sp = SP + insn.zcmp_stack_adjustment(xlen); +auto addr = new_sp; + +for (int i = Sn(11); i >= 0; i--) { + if (insn.zcmp_regmask() & (1 << i)) { + addr -= xlen / 8; + + if (xlen == 32) + WRITE_REG(i, MMU.load<int32_t>(addr)); + else + WRITE_REG(i, MMU.load<int64_t>(addr)); + } +} + +WRITE_REG(X_SP, new_sp); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/cm_popret.h b/vendor/riscv/riscv-isa-sim/riscv/insns/cm_popret.h new file mode 100644 index 0000000000..4873c029dc --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/cm_popret.h @@ -0,0 +1,2 @@ +#include "cm_pop.h" +set_pc(RA); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/cm_popretz.h b/vendor/riscv/riscv-isa-sim/riscv/insns/cm_popretz.h new file mode 100644 index 0000000000..1042351610 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/cm_popretz.h @@ -0,0 +1,2 @@ +#include "cm_popret.h" +WRITE_REG(X_A0, 0); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/cm_push.h b/vendor/riscv/riscv-isa-sim/riscv/insns/cm_push.h new file mode 100644 index 0000000000..64accd4b5f --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/cm_push.h @@ -0,0 +1,17 @@ +require_zcmp_pushpop; + +const auto new_sp = SP - insn.zcmp_stack_adjustment(xlen); +auto addr = SP; + +for (int i = Sn(11); i >= 0; i--) { + if (insn.zcmp_regmask() & (1 << i)) { + addr -= xlen / 8; + + if (xlen == 32) + MMU.store<uint32_t>(addr, READ_REG(i)); + else + MMU.store<uint64_t>(addr, READ_REG(i)); + } +} + +WRITE_REG(X_SP, new_sp); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/cmix.h b/vendor/riscv/riscv-isa-sim/riscv/insns/cmix.h new file mode 100644 index 0000000000..98eb0bca21 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/cmix.h @@ -0,0 +1,2 @@ +require_either_extension(EXT_ZBPBO, EXT_XZBT); +WRITE_RD((RS1 & RS2) | (RS3 & ~RS2)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/cmov.h b/vendor/riscv/riscv-isa-sim/riscv/insns/cmov.h new file mode 100644 index 0000000000..c7551bc645 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/cmov.h @@ -0,0 +1,2 @@ +require_extension(EXT_XZBT); +WRITE_RD(RS2 ? RS1 : RS3); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/cmpeq16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/cmpeq16.h new file mode 100644 index 0000000000..4fb6faab3e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/cmpeq16.h @@ -0,0 +1,3 @@ +P_LOOP(16, { + pd = (ps1 == ps2) ? -1 : 0; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/cmpeq8.h b/vendor/riscv/riscv-isa-sim/riscv/insns/cmpeq8.h new file mode 100644 index 0000000000..fba1bf6d95 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/cmpeq8.h @@ -0,0 +1,3 @@ +P_LOOP(8, { + pd = (ps1 == ps2) ? -1 : 0; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/cpop.h b/vendor/riscv/riscv-isa-sim/riscv/insns/cpop.h new file mode 100644 index 0000000000..1f5c3ef86c --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/cpop.h @@ -0,0 +1,5 @@ +require_extension(EXT_ZBB); +reg_t x = 0; +for (int i = 0; i < xlen; i++) + if (1 & (RS1 >> i)) x++; +WRITE_RD(sext_xlen(x)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/cpopw.h b/vendor/riscv/riscv-isa-sim/riscv/insns/cpopw.h new file mode 100644 index 0000000000..4138398505 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/cpopw.h @@ -0,0 +1,6 @@ +require_rv64; +require_extension(EXT_ZBB); +reg_t x = 0; +for (int i = 0; i < 32; i++) + if (1 & (RS1 >> i)) x++; +WRITE_RD(sext32(x)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/cras16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/cras16.h new file mode 100644 index 0000000000..6717e099ed --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/cras16.h @@ -0,0 +1,5 @@ +P_CROSS_LOOP(16, { + pd = ps1 + ps2; +}, { + pd = ps1 - ps2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/cras32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/cras32.h new file mode 100644 index 0000000000..8f53e98b44 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/cras32.h @@ -0,0 +1,6 @@ +require_rv64; +P_CROSS_LOOP(32, { + pd = ps1 + ps2; +}, { + pd = ps1 - ps2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/crc32_b.h b/vendor/riscv/riscv-isa-sim/riscv/insns/crc32_b.h new file mode 100644 index 0000000000..3111fe5728 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/crc32_b.h @@ -0,0 +1,5 @@ +require_extension(EXT_XZBR); +reg_t x = zext_xlen(RS1); +for (int i = 0; i < 8; i++) + x = (x >> 1) ^ (0xEDB88320 & ~((x&1)-1)); +WRITE_RD(sext_xlen(x)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/crc32_d.h b/vendor/riscv/riscv-isa-sim/riscv/insns/crc32_d.h new file mode 100644 index 0000000000..7fd7a38f2b --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/crc32_d.h @@ -0,0 +1,6 @@ +require_rv64; +require_extension(EXT_XZBR); +reg_t x = zext_xlen(RS1); +for (int i = 0; i < 64; i++) + x = (x >> 1) ^ (0xEDB88320 & ~((x&1)-1)); +WRITE_RD(sext_xlen(x)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/crc32_h.h b/vendor/riscv/riscv-isa-sim/riscv/insns/crc32_h.h new file mode 100644 index 0000000000..5063fefd6d --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/crc32_h.h @@ -0,0 +1,5 @@ +require_extension(EXT_XZBR); +reg_t x = zext_xlen(RS1); +for (int i = 0; i < 16; i++) + x = (x >> 1) ^ (0xEDB88320 & ~((x&1)-1)); +WRITE_RD(sext_xlen(x)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/crc32_w.h b/vendor/riscv/riscv-isa-sim/riscv/insns/crc32_w.h new file mode 100644 index 0000000000..6e425ab8d9 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/crc32_w.h @@ -0,0 +1,5 @@ +require_extension(EXT_XZBR); +reg_t x = zext_xlen(RS1); +for (int i = 0; i < 32; i++) + x = (x >> 1) ^ (0xEDB88320 & ~((x&1)-1)); +WRITE_RD(sext_xlen(x)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/crc32c_b.h b/vendor/riscv/riscv-isa-sim/riscv/insns/crc32c_b.h new file mode 100644 index 0000000000..d11b0dda87 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/crc32c_b.h @@ -0,0 +1,5 @@ +require_extension(EXT_XZBR); +reg_t x = zext_xlen(RS1); +for (int i = 0; i < 8; i++) + x = (x >> 1) ^ (0x82F63B78 & ~((x&1)-1)); +WRITE_RD(sext_xlen(x)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/crc32c_d.h b/vendor/riscv/riscv-isa-sim/riscv/insns/crc32c_d.h new file mode 100644 index 0000000000..81175fd9c1 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/crc32c_d.h @@ -0,0 +1,6 @@ +require_rv64; +require_extension(EXT_XZBR); +reg_t x = zext_xlen(RS1); +for (int i = 0; i < 64; i++) + x = (x >> 1) ^ (0x82F63B78 & ~((x&1)-1)); +WRITE_RD(sext_xlen(x)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/crc32c_h.h b/vendor/riscv/riscv-isa-sim/riscv/insns/crc32c_h.h new file mode 100644 index 0000000000..ef5817d99e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/crc32c_h.h @@ -0,0 +1,5 @@ +require_extension(EXT_XZBR); +reg_t x = zext_xlen(RS1); +for (int i = 0; i < 16; i++) + x = (x >> 1) ^ (0x82F63B78 & ~((x&1)-1)); +WRITE_RD(sext_xlen(x)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/crc32c_w.h b/vendor/riscv/riscv-isa-sim/riscv/insns/crc32c_w.h new file mode 100644 index 0000000000..8793540297 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/crc32c_w.h @@ -0,0 +1,5 @@ +require_extension(EXT_XZBR); +reg_t x = zext_xlen(RS1); +for (int i = 0; i < 32; i++) + x = (x >> 1) ^ (0x82F63B78 & ~((x&1)-1)); +WRITE_RD(sext_xlen(x)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/crsa16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/crsa16.h new file mode 100644 index 0000000000..2c1997ac98 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/crsa16.h @@ -0,0 +1,5 @@ +P_CROSS_LOOP(16, { + pd = ps1 - ps2; +}, { + pd = ps1 + ps2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/crsa32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/crsa32.h new file mode 100644 index 0000000000..4290e9ed8c --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/crsa32.h @@ -0,0 +1,6 @@ +require_rv64; +P_CROSS_LOOP(32, { + pd = (int64_t)ps1 - ps2; +}, { + pd = (int64_t)ps1 + ps2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/csrrc.h b/vendor/riscv/riscv-isa-sim/riscv/insns/csrrc.h new file mode 100644 index 0000000000..019a9ce4eb --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/csrrc.h @@ -0,0 +1,8 @@ +bool write = insn.rs1() != 0; +int csr = validate_csr(insn.csr(), write); +reg_t old = p->get_csr(csr, insn, write); +if (write) { + p->put_csr(csr, old & ~RS1); +} +WRITE_RD(sext_xlen(old)); +serialize(); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/csrrci.h b/vendor/riscv/riscv-isa-sim/riscv/insns/csrrci.h new file mode 100644 index 0000000000..f02d326886 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/csrrci.h @@ -0,0 +1,8 @@ +bool write = insn.rs1() != 0; +int csr = validate_csr(insn.csr(), write); +reg_t old = p->get_csr(csr, insn, write); +if (write) { + p->put_csr(csr, old & ~(reg_t)insn.rs1()); +} +WRITE_RD(sext_xlen(old)); +serialize(); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/csrrs.h b/vendor/riscv/riscv-isa-sim/riscv/insns/csrrs.h new file mode 100644 index 0000000000..7632d1f40c --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/csrrs.h @@ -0,0 +1,8 @@ +bool write = insn.rs1() != 0; +int csr = validate_csr(insn.csr(), write); +reg_t old = p->get_csr(csr, insn, write); +if (write) { + p->put_csr(csr, old | RS1); +} +WRITE_RD(sext_xlen(old)); +serialize(); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/csrrsi.h b/vendor/riscv/riscv-isa-sim/riscv/insns/csrrsi.h new file mode 100644 index 0000000000..9acfcfcf74 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/csrrsi.h @@ -0,0 +1,8 @@ +bool write = insn.rs1() != 0; +int csr = validate_csr(insn.csr(), write); +reg_t old = p->get_csr(csr, insn, write); +if (write) { + p->put_csr(csr, old | insn.rs1()); +} +WRITE_RD(sext_xlen(old)); +serialize(); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/csrrw.h b/vendor/riscv/riscv-isa-sim/riscv/insns/csrrw.h new file mode 100644 index 0000000000..e4c605bd81 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/csrrw.h @@ -0,0 +1,5 @@ +int csr = validate_csr(insn.csr(), true); +reg_t old = p->get_csr(csr, insn, true); +p->put_csr(csr, RS1); +WRITE_RD(sext_xlen(old)); +serialize(); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/csrrwi.h b/vendor/riscv/riscv-isa-sim/riscv/insns/csrrwi.h new file mode 100644 index 0000000000..77fec1543e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/csrrwi.h @@ -0,0 +1,5 @@ +int csr = validate_csr(insn.csr(), true); +reg_t old = p->get_csr(csr, insn, true); +p->put_csr(csr, insn.rs1()); +WRITE_RD(sext_xlen(old)); +serialize(); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/ctz.h b/vendor/riscv/riscv-isa-sim/riscv/insns/ctz.h new file mode 100644 index 0000000000..25d37239fd --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/ctz.h @@ -0,0 +1,5 @@ +require_extension(EXT_ZBB); +reg_t x = xlen; +for (int i = 0; i < xlen; i++) + if (1 & (RS1 >> i)) { x = i; break; } +WRITE_RD(sext_xlen(x)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/ctzw.h b/vendor/riscv/riscv-isa-sim/riscv/insns/ctzw.h new file mode 100644 index 0000000000..aca46e9d16 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/ctzw.h @@ -0,0 +1,6 @@ +require_rv64; +require_extension(EXT_ZBB); +reg_t x = 32; +for (int i = 0; i < 32; i++) + if (1 & (RS1 >> i)) { x = i; break; } +WRITE_RD(sext32(x)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/czero_eqz.h b/vendor/riscv/riscv-isa-sim/riscv/insns/czero_eqz.h new file mode 100644 index 0000000000..24062af9eb --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/czero_eqz.h @@ -0,0 +1,2 @@ +require_extension(EXT_ZICOND); +WRITE_RD(RS2 == 0 ? 0 : RS1); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/czero_nez.h b/vendor/riscv/riscv-isa-sim/riscv/insns/czero_nez.h new file mode 100644 index 0000000000..cd6c8af7c5 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/czero_nez.h @@ -0,0 +1,2 @@ +require_extension(EXT_ZICOND); +WRITE_RD(RS2 != 0 ? 0 : RS1); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/div.h b/vendor/riscv/riscv-isa-sim/riscv/insns/div.h new file mode 100644 index 0000000000..fb62437bb4 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/div.h @@ -0,0 +1,9 @@ +require_extension('M'); +sreg_t lhs = sext_xlen(RS1); +sreg_t rhs = sext_xlen(RS2); +if (rhs == 0) + WRITE_RD(UINT64_MAX); +else if (lhs == INT64_MIN && rhs == -1) + WRITE_RD(lhs); +else + WRITE_RD(sext_xlen(lhs / rhs)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/divu.h b/vendor/riscv/riscv-isa-sim/riscv/insns/divu.h new file mode 100644 index 0000000000..ed05818620 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/divu.h @@ -0,0 +1,7 @@ +require_extension('M'); +reg_t lhs = zext_xlen(RS1); +reg_t rhs = zext_xlen(RS2); +if (rhs == 0) + WRITE_RD(UINT64_MAX); +else + WRITE_RD(sext_xlen(lhs / rhs)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/divuw.h b/vendor/riscv/riscv-isa-sim/riscv/insns/divuw.h new file mode 100644 index 0000000000..bc7e9d2d3f --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/divuw.h @@ -0,0 +1,8 @@ +require_extension('M'); +require_rv64; +reg_t lhs = zext32(RS1); +reg_t rhs = zext32(RS2); +if (rhs == 0) + WRITE_RD(UINT64_MAX); +else + WRITE_RD(sext32(lhs / rhs)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/divw.h b/vendor/riscv/riscv-isa-sim/riscv/insns/divw.h new file mode 100644 index 0000000000..54409b07a1 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/divw.h @@ -0,0 +1,8 @@ +require_extension('M'); +require_rv64; +sreg_t lhs = sext32(RS1); +sreg_t rhs = sext32(RS2); +if (rhs == 0) + WRITE_RD(UINT64_MAX); +else + WRITE_RD(sext32(lhs / rhs)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/dret.h b/vendor/riscv/riscv-isa-sim/riscv/insns/dret.h new file mode 100644 index 0000000000..56ce25bce6 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/dret.h @@ -0,0 +1,11 @@ +require(STATE.debug_mode); +set_pc_and_serialize(STATE.dpc->read()); +p->set_privilege(STATE.dcsr->prv); +if (STATE.prv < PRV_M) + STATE.mstatus->write(STATE.mstatus->read() & ~MSTATUS_MPRV); + +/* We're not in Debug Mode anymore. */ +STATE.debug_mode = false; + +if (STATE.dcsr->step) + STATE.single_step = STATE.STEP_STEPPING; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/ebreak.h b/vendor/riscv/riscv-isa-sim/riscv/insns/ebreak.h new file mode 100644 index 0000000000..227ab93527 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/ebreak.h @@ -0,0 +1,8 @@ +if (!STATE.debug_mode && + ((STATE.prv == PRV_M && STATE.dcsr->ebreakm) || + (STATE.prv == PRV_S && STATE.dcsr->ebreaks) || + (STATE.prv == PRV_U && STATE.dcsr->ebreaku))) { + throw trap_debug_mode(); +} else { + throw trap_breakpoint(STATE.v, pc); +} diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/ecall.h b/vendor/riscv/riscv-isa-sim/riscv/insns/ecall.h new file mode 100644 index 0000000000..e6c723f4e3 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/ecall.h @@ -0,0 +1,11 @@ +switch (STATE.prv) +{ + case PRV_U: throw trap_user_ecall(); + case PRV_S: + if (STATE.v) + throw trap_virtual_supervisor_ecall(); + else + throw trap_supervisor_ecall(); + case PRV_M: throw trap_machine_ecall(); + default: abort(); +} diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fadd_d.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fadd_d.h new file mode 100644 index 0000000000..9bfff5fb9a --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fadd_d.h @@ -0,0 +1,5 @@ +require_either_extension('D', EXT_ZDINX); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD_D(f64_add(FRS1_D, FRS2_D)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fadd_h.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fadd_h.h new file mode 100644 index 0000000000..f57e5fa795 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fadd_h.h @@ -0,0 +1,5 @@ +require_either_extension(EXT_ZFH, EXT_ZHINX); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD_H(f16_add(FRS1_H, FRS2_H)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fadd_q.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fadd_q.h new file mode 100644 index 0000000000..1139a74dc7 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fadd_q.h @@ -0,0 +1,5 @@ +require_extension('Q'); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD(f128_add(f128(FRS1), f128(FRS2))); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fadd_s.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fadd_s.h new file mode 100644 index 0000000000..7a40b1bf18 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fadd_s.h @@ -0,0 +1,5 @@ +require_either_extension('F', EXT_ZFINX); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD_F(f32_add(FRS1_F, FRS2_F)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fclass_d.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fclass_d.h new file mode 100644 index 0000000000..a355062981 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fclass_d.h @@ -0,0 +1,3 @@ +require_either_extension('D', EXT_ZDINX); +require_fp; +WRITE_RD(f64_classify(FRS1_D)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fclass_h.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fclass_h.h new file mode 100644 index 0000000000..2638ac8d3e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fclass_h.h @@ -0,0 +1,3 @@ +require_either_extension(EXT_ZFH, EXT_ZHINX); +require_fp; +WRITE_RD(f16_classify(FRS1_H)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fclass_q.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fclass_q.h new file mode 100644 index 0000000000..533075821c --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fclass_q.h @@ -0,0 +1,3 @@ +require_extension('Q'); +require_fp; +WRITE_RD(f128_classify(f128(FRS1))); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fclass_s.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fclass_s.h new file mode 100644 index 0000000000..3d529adc8a --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fclass_s.h @@ -0,0 +1,3 @@ +require_either_extension('F', EXT_ZFINX); +require_fp; +WRITE_RD(f32_classify(FRS1_F)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_d_h.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_d_h.h new file mode 100644 index 0000000000..061a2710d0 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_d_h.h @@ -0,0 +1,6 @@ +require_either_extension(EXT_ZFHMIN, EXT_ZHINXMIN); +require_either_extension('D', EXT_ZDINX); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD_D(f16_to_f64(FRS1_H)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_d_l.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_d_l.h new file mode 100644 index 0000000000..7788f1f0b8 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_d_l.h @@ -0,0 +1,6 @@ +require_either_extension('D', EXT_ZDINX); +require_rv64; +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD_D(i64_to_f64(RS1)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_d_lu.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_d_lu.h new file mode 100644 index 0000000000..edb694f7ad --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_d_lu.h @@ -0,0 +1,6 @@ +require_either_extension('D', EXT_ZDINX); +require_rv64; +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD_D(ui64_to_f64(RS1)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_d_q.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_d_q.h new file mode 100644 index 0000000000..b50a43d07d --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_d_q.h @@ -0,0 +1,5 @@ +require_extension('Q'); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD(f128_to_f64(f128(FRS1))); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_d_s.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_d_s.h new file mode 100644 index 0000000000..8039e9465a --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_d_s.h @@ -0,0 +1,5 @@ +require_either_extension('D', EXT_ZDINX); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD_D(f32_to_f64(FRS1_F)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_d_w.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_d_w.h new file mode 100644 index 0000000000..e3375faf60 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_d_w.h @@ -0,0 +1,5 @@ +require_either_extension('D', EXT_ZDINX); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD_D(i32_to_f64((int32_t)RS1)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_d_wu.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_d_wu.h new file mode 100644 index 0000000000..d903561ffb --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_d_wu.h @@ -0,0 +1,5 @@ +require_either_extension('D', EXT_ZDINX); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD_D(ui32_to_f64((uint32_t)RS1)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_h_d.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_h_d.h new file mode 100644 index 0000000000..e06b1a5550 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_h_d.h @@ -0,0 +1,6 @@ +require_either_extension(EXT_ZFHMIN, EXT_ZHINXMIN); +require_either_extension('D', EXT_ZDINX); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD_H(f64_to_f16(FRS1_D)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_h_l.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_h_l.h new file mode 100644 index 0000000000..31e8a1e4f1 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_h_l.h @@ -0,0 +1,6 @@ +require_either_extension(EXT_ZFH, EXT_ZHINX); +require_rv64; +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD_H(i64_to_f16(RS1)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_h_lu.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_h_lu.h new file mode 100644 index 0000000000..189b1601ae --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_h_lu.h @@ -0,0 +1,6 @@ +require_either_extension(EXT_ZFH, EXT_ZHINX); +require_rv64; +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD_H(ui64_to_f16(RS1)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_h_q.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_h_q.h new file mode 100644 index 0000000000..4dfdd53642 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_h_q.h @@ -0,0 +1,6 @@ +require_extension(EXT_ZFHMIN); +require_extension('Q'); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD(f128_to_f16(f128(FRS1))); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_h_s.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_h_s.h new file mode 100644 index 0000000000..57ba0059dd --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_h_s.h @@ -0,0 +1,5 @@ +require_either_extension(EXT_ZFHMIN, EXT_ZHINXMIN); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD_H(f32_to_f16(FRS1_F)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_h_w.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_h_w.h new file mode 100644 index 0000000000..de4cbe56c3 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_h_w.h @@ -0,0 +1,5 @@ +require_either_extension(EXT_ZFH, EXT_ZHINX); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD_H(i32_to_f16((int32_t)RS1)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_h_wu.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_h_wu.h new file mode 100644 index 0000000000..230c354fe6 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_h_wu.h @@ -0,0 +1,5 @@ +require_either_extension(EXT_ZFH, EXT_ZHINX); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD_H(ui32_to_f16((uint32_t)RS1)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_l_d.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_l_d.h new file mode 100644 index 0000000000..f2374d269b --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_l_d.h @@ -0,0 +1,6 @@ +require_either_extension('D', EXT_ZDINX); +require_rv64; +require_fp; +softfloat_roundingMode = RM; +WRITE_RD(f64_to_i64(FRS1_D, RM, true)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_l_h.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_l_h.h new file mode 100644 index 0000000000..3b630276ef --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_l_h.h @@ -0,0 +1,6 @@ +require_either_extension(EXT_ZFH, EXT_ZHINX); +require_rv64; +require_fp; +softfloat_roundingMode = RM; +WRITE_RD(f16_to_i64(FRS1_H, RM, true)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_l_q.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_l_q.h new file mode 100644 index 0000000000..b28bca239b --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_l_q.h @@ -0,0 +1,6 @@ +require_extension('Q'); +require_rv64; +require_fp; +softfloat_roundingMode = RM; +WRITE_RD(f128_to_i64(f128(FRS1), RM, true)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_l_s.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_l_s.h new file mode 100644 index 0000000000..d121a65c3b --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_l_s.h @@ -0,0 +1,6 @@ +require_either_extension('F', EXT_ZFINX); +require_rv64; +require_fp; +softfloat_roundingMode = RM; +WRITE_RD(f32_to_i64(FRS1_F, RM, true)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_lu_d.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_lu_d.h new file mode 100644 index 0000000000..939bc0e184 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_lu_d.h @@ -0,0 +1,6 @@ +require_either_extension('D', EXT_ZDINX); +require_rv64; +require_fp; +softfloat_roundingMode = RM; +WRITE_RD(f64_to_ui64(FRS1_D, RM, true)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_lu_h.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_lu_h.h new file mode 100644 index 0000000000..d27f175e20 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_lu_h.h @@ -0,0 +1,6 @@ +require_either_extension(EXT_ZFH, EXT_ZHINX); +require_rv64; +require_fp; +softfloat_roundingMode = RM; +WRITE_RD(f16_to_ui64(FRS1_H, RM, true)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_lu_q.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_lu_q.h new file mode 100644 index 0000000000..8c5be7c6c8 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_lu_q.h @@ -0,0 +1,6 @@ +require_extension('Q'); +require_rv64; +require_fp; +softfloat_roundingMode = RM; +WRITE_RD(f128_to_ui64(f128(FRS1), RM, true)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_lu_s.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_lu_s.h new file mode 100644 index 0000000000..69c95ef059 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_lu_s.h @@ -0,0 +1,6 @@ +require_either_extension('F', EXT_ZFINX); +require_rv64; +require_fp; +softfloat_roundingMode = RM; +WRITE_RD(f32_to_ui64(FRS1_F, RM, true)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_q_d.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_q_d.h new file mode 100644 index 0000000000..c2437b12fc --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_q_d.h @@ -0,0 +1,5 @@ +require_extension('Q'); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD(f64_to_f128(f64(FRS1))); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_q_h.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_q_h.h new file mode 100644 index 0000000000..8bf16ce45b --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_q_h.h @@ -0,0 +1,6 @@ +require_extension(EXT_ZFHMIN); +require_extension('Q'); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD(f16_to_f128(f16(FRS1))); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_q_l.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_q_l.h new file mode 100644 index 0000000000..f1f45ca3e6 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_q_l.h @@ -0,0 +1,6 @@ +require_extension('Q'); +require_rv64; +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD(i64_to_f128(RS1)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_q_lu.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_q_lu.h new file mode 100644 index 0000000000..850212e9bc --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_q_lu.h @@ -0,0 +1,6 @@ +require_extension('Q'); +require_rv64; +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD(ui64_to_f128(RS1)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_q_s.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_q_s.h new file mode 100644 index 0000000000..79e6bb6fc1 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_q_s.h @@ -0,0 +1,5 @@ +require_extension('Q'); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD(f32_to_f128(f32(FRS1))); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_q_w.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_q_w.h new file mode 100644 index 0000000000..fb83f15d99 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_q_w.h @@ -0,0 +1,5 @@ +require_extension('Q'); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD(i32_to_f128((int32_t)RS1)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_q_wu.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_q_wu.h new file mode 100644 index 0000000000..7c2ae97ec8 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_q_wu.h @@ -0,0 +1,5 @@ +require_extension('Q'); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD(ui32_to_f128((uint32_t)RS1)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_s_d.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_s_d.h new file mode 100644 index 0000000000..f3cd26e9a1 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_s_d.h @@ -0,0 +1,5 @@ +require_either_extension('D', EXT_ZDINX); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD_F(f64_to_f32(FRS1_D)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_s_h.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_s_h.h new file mode 100644 index 0000000000..346440a972 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_s_h.h @@ -0,0 +1,5 @@ +require_either_extension(EXT_ZFHMIN, EXT_ZHINXMIN); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD_F(f16_to_f32(FRS1_H)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_s_l.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_s_l.h new file mode 100644 index 0000000000..1d096d2ca7 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_s_l.h @@ -0,0 +1,6 @@ +require_either_extension('F', EXT_ZFINX); +require_rv64; +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD_F(i64_to_f32(RS1)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_s_lu.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_s_lu.h new file mode 100644 index 0000000000..e4e84cf426 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_s_lu.h @@ -0,0 +1,6 @@ +require_either_extension('F', EXT_ZFINX); +require_rv64; +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD_F(ui64_to_f32(RS1)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_s_q.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_s_q.h new file mode 100644 index 0000000000..b0f118ec59 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_s_q.h @@ -0,0 +1,5 @@ +require_extension('Q'); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD(f128_to_f32(f128(FRS1))); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_s_w.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_s_w.h new file mode 100644 index 0000000000..75c87db502 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_s_w.h @@ -0,0 +1,5 @@ +require_either_extension('F', EXT_ZFINX); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD_F(i32_to_f32((int32_t)RS1)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_s_wu.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_s_wu.h new file mode 100644 index 0000000000..ec90fad93d --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_s_wu.h @@ -0,0 +1,5 @@ +require_either_extension('F', EXT_ZFINX); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD_F(ui32_to_f32((uint32_t)RS1)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_w_d.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_w_d.h new file mode 100644 index 0000000000..a839f4ba88 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_w_d.h @@ -0,0 +1,5 @@ +require_either_extension('D', EXT_ZDINX); +require_fp; +softfloat_roundingMode = RM; +WRITE_RD(sext32(f64_to_i32(FRS1_D, RM, true))); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_w_h.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_w_h.h new file mode 100644 index 0000000000..97e49a554e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_w_h.h @@ -0,0 +1,5 @@ +require_either_extension(EXT_ZFH, EXT_ZHINX); +require_fp; +softfloat_roundingMode = RM; +WRITE_RD(sext32(f16_to_i32(FRS1_H, RM, true))); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_w_q.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_w_q.h new file mode 100644 index 0000000000..e10bafc978 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_w_q.h @@ -0,0 +1,5 @@ +require_extension('Q'); +require_fp; +softfloat_roundingMode = RM; +WRITE_RD(sext32(f128_to_i32(f128(FRS1), RM, true))); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_w_s.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_w_s.h new file mode 100644 index 0000000000..6aeb5101a9 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_w_s.h @@ -0,0 +1,5 @@ +require_either_extension('F', EXT_ZFINX); +require_fp; +softfloat_roundingMode = RM; +WRITE_RD(sext32(f32_to_i32(FRS1_F, RM, true))); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_wu_d.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_wu_d.h new file mode 100644 index 0000000000..906f003fbf --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_wu_d.h @@ -0,0 +1,5 @@ +require_either_extension('D', EXT_ZDINX); +require_fp; +softfloat_roundingMode = RM; +WRITE_RD(sext32(f64_to_ui32(FRS1_D, RM, true))); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_wu_h.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_wu_h.h new file mode 100644 index 0000000000..ce111438ba --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_wu_h.h @@ -0,0 +1,5 @@ +require_either_extension(EXT_ZFH, EXT_ZHINX); +require_fp; +softfloat_roundingMode = RM; +WRITE_RD(sext32(f16_to_ui32(FRS1_H, RM, true))); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_wu_q.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_wu_q.h new file mode 100644 index 0000000000..c391dc8759 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_wu_q.h @@ -0,0 +1,5 @@ +require_extension('Q'); +require_fp; +softfloat_roundingMode = RM; +WRITE_RD(sext32(f128_to_ui32(f128(FRS1), RM, true))); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_wu_s.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_wu_s.h new file mode 100644 index 0000000000..a8b8455775 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvt_wu_s.h @@ -0,0 +1,5 @@ +require_either_extension('F', EXT_ZFINX); +require_fp; +softfloat_roundingMode = RM; +WRITE_RD(sext32(f32_to_ui32(FRS1_F, RM, true))); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fcvtmod_w_d.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvtmod_w_d.h new file mode 100644 index 0000000000..89b9b9522b --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fcvtmod_w_d.h @@ -0,0 +1,58 @@ +require_extension('D'); +require_extension(EXT_ZFA); +require_fp; +uint64_t a = FRS1_D.v; + +uint32_t sign = signF64UI(a); +uint32_t exp = expF64UI(a); +uint64_t frac = fracF64UI(a); + +bool inexact = false; +bool invalid = false; + +if (exp == 0) { + inexact = (frac != 0); + frac = 0; +} else if (exp == 0x7ff) { + /* inf or NaN */ + invalid = true; + frac = 0; +} else { + int true_exp = exp - 1023; + int shift = true_exp - 52; + + /* Restore implicit bit. */ + frac |= 1ull << 52; + + /* Shift the fraction into place. */ + if (shift >= 64) { + /* The fraction is shifted out entirely. */ + frac = 0; + } else if ((shift >= 0) && (shift < 64)) { + /* The number is so large we must shift the fraction left. */ + frac <<= shift; + } else if ((shift > -64) && (shift < 0)) { + /* Normal case -- shift right and notice if bits shift out. */ + inexact = (frac << (64 + shift)) != 0; + frac >>= -shift; + } else { + /* The fraction is shifted out entirely. */ + frac = 0; + } + + /* Notice overflow or inexact exceptions. */ + if (true_exp > 31 || frac > (sign ? 0x80000000ull : 0x7fffffff)) { + /* Overflow, for which this operation raises invalid. */ + invalid = true; + } + + /* Honor the sign. */ + if (sign) { + frac = -frac; + } +} + +WRITE_RD(sext32(frac)); +STATE.fflags->write(STATE.fflags->read() | + (inexact ? softfloat_flag_inexact : 0) | + (invalid ? softfloat_flag_invalid : 0)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fdiv_d.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fdiv_d.h new file mode 100644 index 0000000000..990afca028 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fdiv_d.h @@ -0,0 +1,5 @@ +require_either_extension('D', EXT_ZDINX); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD_D(f64_div(FRS1_D, FRS2_D)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fdiv_h.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fdiv_h.h new file mode 100644 index 0000000000..91c518b4e1 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fdiv_h.h @@ -0,0 +1,5 @@ +require_either_extension(EXT_ZFH, EXT_ZHINX); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD_H(f16_div(FRS1_H, FRS2_H)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fdiv_q.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fdiv_q.h new file mode 100644 index 0000000000..2204831773 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fdiv_q.h @@ -0,0 +1,5 @@ +require_extension('Q'); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD(f128_div(f128(FRS1), f128(FRS2))); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fdiv_s.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fdiv_s.h new file mode 100644 index 0000000000..180b41dd28 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fdiv_s.h @@ -0,0 +1,5 @@ +require_either_extension('F', EXT_ZFINX); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD_F(f32_div(FRS1_F, FRS2_F)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fence.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fence.h new file mode 100644 index 0000000000..e69de29bb2 diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fence_i.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fence_i.h new file mode 100644 index 0000000000..38dcaf3fce --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fence_i.h @@ -0,0 +1 @@ +MMU.flush_icache(); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/feq_d.h b/vendor/riscv/riscv-isa-sim/riscv/insns/feq_d.h new file mode 100644 index 0000000000..9585bad707 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/feq_d.h @@ -0,0 +1,4 @@ +require_either_extension('D', EXT_ZDINX); +require_fp; +WRITE_RD(f64_eq(FRS1_D, FRS2_D)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/feq_h.h b/vendor/riscv/riscv-isa-sim/riscv/insns/feq_h.h new file mode 100644 index 0000000000..5988db900a --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/feq_h.h @@ -0,0 +1,4 @@ +require_either_extension(EXT_ZFH, EXT_ZHINX); +require_fp; +WRITE_RD(f16_eq(FRS1_H, FRS2_H)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/feq_q.h b/vendor/riscv/riscv-isa-sim/riscv/insns/feq_q.h new file mode 100644 index 0000000000..cee2da95a7 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/feq_q.h @@ -0,0 +1,4 @@ +require_extension('Q'); +require_fp; +WRITE_RD(f128_eq(f128(FRS1), f128(FRS2))); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/feq_s.h b/vendor/riscv/riscv-isa-sim/riscv/insns/feq_s.h new file mode 100644 index 0000000000..97b57c2ed2 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/feq_s.h @@ -0,0 +1,4 @@ +require_either_extension('F', EXT_ZFINX); +require_fp; +WRITE_RD(f32_eq(FRS1_F, FRS2_F)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fld.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fld.h new file mode 100644 index 0000000000..bbe859fe99 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fld.h @@ -0,0 +1,3 @@ +require_extension('D'); +require_fp; +WRITE_FRD(f64(MMU.load<uint64_t>(RS1 + insn.i_imm()))); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fle_d.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fle_d.h new file mode 100644 index 0000000000..17b49320e7 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fle_d.h @@ -0,0 +1,4 @@ +require_either_extension('D', EXT_ZDINX); +require_fp; +WRITE_RD(f64_le(FRS1_D, FRS2_D)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fle_h.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fle_h.h new file mode 100644 index 0000000000..31ed8a750d --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fle_h.h @@ -0,0 +1,4 @@ +require_either_extension(EXT_ZFH, EXT_ZHINX); +require_fp; +WRITE_RD(f16_le(FRS1_H, FRS2_H)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fle_q.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fle_q.h new file mode 100644 index 0000000000..8368af9dfd --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fle_q.h @@ -0,0 +1,4 @@ +require_extension('Q'); +require_fp; +WRITE_RD(f128_le(f128(FRS1), f128(FRS2))); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fle_s.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fle_s.h new file mode 100644 index 0000000000..e26f055632 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fle_s.h @@ -0,0 +1,4 @@ +require_either_extension('F', EXT_ZFINX); +require_fp; +WRITE_RD(f32_le(FRS1_F, FRS2_F)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fleq_d.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fleq_d.h new file mode 100644 index 0000000000..762e147039 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fleq_d.h @@ -0,0 +1,4 @@ +require_extension('D'); +require_extension(EXT_ZFA); +require_fp; +WRITE_RD(f64_le_quiet(FRS1_D, FRS2_D)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fleq_h.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fleq_h.h new file mode 100644 index 0000000000..7e6db59ae5 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fleq_h.h @@ -0,0 +1,4 @@ +require_extension(EXT_ZFH); +require_extension(EXT_ZFA); +require_fp; +WRITE_RD(f16_le_quiet(FRS1_H, FRS2_H)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fleq_q.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fleq_q.h new file mode 100644 index 0000000000..8533d11d16 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fleq_q.h @@ -0,0 +1,4 @@ +require_extension('Q'); +require_extension(EXT_ZFA); +require_fp; +WRITE_RD(f128_le_quiet(f128(FRS1), f128(FRS2))); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fleq_s.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fleq_s.h new file mode 100644 index 0000000000..8c0a909446 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fleq_s.h @@ -0,0 +1,4 @@ +require_extension('F'); +require_extension(EXT_ZFA); +require_fp; +WRITE_RD(f32_le_quiet(FRS1_F, FRS2_F)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/flh.h b/vendor/riscv/riscv-isa-sim/riscv/insns/flh.h new file mode 100644 index 0000000000..befff2cd3a --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/flh.h @@ -0,0 +1,3 @@ +require_extension(EXT_ZFHMIN); +require_fp; +WRITE_FRD(f16(MMU.load<uint16_t>(RS1 + insn.i_imm()))); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fli_d.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fli_d.h new file mode 100644 index 0000000000..090e88c724 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fli_d.h @@ -0,0 +1,40 @@ +require_extension('D'); +require_extension(EXT_ZFA); +require_fp; +{ + const uint64_t bits[32] = { + [0b00000] = 0xbff0000000000000ull, /* -1.0 */ + [0b00001] = 0x0010000000000000ull, /* minimum positive normal */ + [0b00010] = 0x3ef0000000000000ull, /* 1.0 * 2^-16 */ + [0b00011] = 0x3f00000000000000ull, /* 1.0 * 2^-15 */ + [0b00100] = 0x3f70000000000000ull, /* 1.0 * 2^-8 */ + [0b00101] = 0x3f80000000000000ull, /* 1.0 * 2^-7 */ + [0b00110] = 0x3fb0000000000000ull, /* 1.0 * 2^-4 */ + [0b00111] = 0x3fc0000000000000ull, /* 1.0 * 2^-3 */ + [0b01000] = 0x3fd0000000000000ull, /* 0.25 */ + [0b01001] = 0x3fd4000000000000ull, /* 0.3125 */ + [0b01010] = 0x3fd8000000000000ull, /* 0.375 */ + [0b01011] = 0x3fdc000000000000ull, /* 0.4375 */ + [0b01100] = 0x3fe0000000000000ull, /* 0.5 */ + [0b01101] = 0x3fe4000000000000ull, /* 0.625 */ + [0b01110] = 0x3fe8000000000000ull, /* 0.75 */ + [0b01111] = 0x3fec000000000000ull, /* 0.875 */ + [0b10000] = 0x3ff0000000000000ull, /* 1.0 */ + [0b10001] = 0x3ff4000000000000ull, /* 1.25 */ + [0b10010] = 0x3ff8000000000000ull, /* 1.5 */ + [0b10011] = 0x3ffc000000000000ull, /* 1.75 */ + [0b10100] = 0x4000000000000000ull, /* 2.0 */ + [0b10101] = 0x4004000000000000ull, /* 2.5 */ + [0b10110] = 0x4008000000000000ull, /* 3 */ + [0b10111] = 0x4010000000000000ull, /* 4 */ + [0b11000] = 0x4020000000000000ull, /* 8 */ + [0b11001] = 0x4030000000000000ull, /* 16 */ + [0b11010] = 0x4060000000000000ull, /* 2^7 */ + [0b11011] = 0x4070000000000000ull, /* 2^8 */ + [0b11100] = 0x40e0000000000000ull, /* 2^15 */ + [0b11101] = 0x40f0000000000000ull, /* 2^16 */ + [0b11110] = 0x7ff0000000000000ull, /* +inf */ + [0b11111] = defaultNaNF64UI + }; + WRITE_FRD_D(f64(bits[insn.rs1()])); +} diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fli_h.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fli_h.h new file mode 100644 index 0000000000..ddf41a9d32 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fli_h.h @@ -0,0 +1,40 @@ +require_extension(EXT_ZFH); +require_extension(EXT_ZFA); +require_fp; +{ + static const uint16_t bits[32] = { + [0b00000] = 0xbc00, /* -1.0 */ + [0b00001] = 0x0400, /* minimum positive normal */ + [0b00010] = 0x0100, /* 1.0 * 2^-16 */ + [0b00011] = 0x0200, /* 1.0 * 2^-15 */ + [0b00100] = 0x1c00, /* 1.0 * 2^-8 */ + [0b00101] = 0x2000, /* 1.0 * 2^-7 */ + [0b00110] = 0x2c00, /* 1.0 * 2^-4 */ + [0b00111] = 0x3000, /* 1.0 * 2^-3 */ + [0b01000] = 0x3400, /* 0.25 */ + [0b01001] = 0x3500, /* 0.3125 */ + [0b01010] = 0x3600, /* 0.375 */ + [0b01011] = 0x3700, /* 0.4375 */ + [0b01100] = 0x3800, /* 0.5 */ + [0b01101] = 0x3900, /* 0.625 */ + [0b01110] = 0x3a00, /* 0.75 */ + [0b01111] = 0x3b00, /* 0.875 */ + [0b10000] = 0x3c00, /* 1.0 */ + [0b10001] = 0x3d00, /* 1.25 */ + [0b10010] = 0x3e00, /* 1.5 */ + [0b10011] = 0x3f00, /* 1.75 */ + [0b10100] = 0x4000, /* 2.0 */ + [0b10101] = 0x4100, /* 2.5 */ + [0b10110] = 0x4200, /* 3 */ + [0b10111] = 0x4400, /* 4 */ + [0b11000] = 0x4800, /* 8 */ + [0b11001] = 0x4c00, /* 16 */ + [0b11010] = 0x5800, /* 2^7 */ + [0b11011] = 0x5c00, /* 2^8 */ + [0b11100] = 0x7800, /* 2^15 */ + [0b11101] = 0x7c00, /* +inf (2^16 is not expressible) */ + [0b11110] = 0x7c00, /* +inf */ + [0b11111] = defaultNaNF16UI + }; + WRITE_FRD_H(f16(bits[insn.rs1()])); +} diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fli_q.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fli_q.h new file mode 100644 index 0000000000..7ba569bf07 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fli_q.h @@ -0,0 +1,46 @@ +require_extension('D'); +require_extension(EXT_ZFA); +require_fp; +{ + const uint64_t bits[32] = { + [0b00000] = 0xBFFF000000000000ull, /* -1.0 */ + [0b00001] = 0x0001000000000000ull, /* minimum positive normal */ + [0b00010] = 0x3FEF000000000000ull, /* 1.0 * 2^-16 */ + [0b00011] = 0x3FF0000000000000ull, /* 1.0 * 2^-15 */ + [0b00100] = 0x3FF7000000000000ull, /* 1.0 * 2^-8 */ + [0b00101] = 0x3FF8000000000000ull, /* 1.0 * 2^-7 */ + [0b00110] = 0x3FFB000000000000ull, /* 1.0 * 2^-4 */ + [0b00111] = 0x3FF9000000000000ull, /* 1.0 * 2^-3 */ + [0b01000] = 0x3FFD000000000000ull, /* 0.25 */ + [0b01001] = 0x3FFD400000000000ull, /* 0.3125 */ + [0b01010] = 0x3FFD800000000000ull, /* 0.375 */ + [0b01011] = 0x3FFDC00000000000ull, /* 0.4375 */ + [0b01100] = 0x3FFE000000000000ull, /* 0.5 */ + [0b01101] = 0x3FFE400000000000ull, /* 0.625 */ + [0b01110] = 0x3FFE800000000000ull, /* 0.75 */ + [0b01111] = 0x3FFEC00000000000ull, /* 0.875 */ + [0b10000] = 0x3FFF000000000000ull, /* 1.0 */ + [0b10001] = 0x3FFF400000000000ull, /* 1.25 */ + [0b10010] = 0x3FFFC00000000000ull, /* 1.5 */ + [0b10011] = 0x4000000000000000ull, /* 1.75 */ + [0b10100] = 0x4000400000000000ull, /* 2.0 */ + [0b10101] = 0x4000800000000000ull, /* 2.5 */ + [0b10110] = 0x4001000000000000ull, /* 3 */ + [0b10111] = 0x4002000000000000ull, /* 4 */ + [0b11000] = 0x4003000000000000ull, /* 8 */ + [0b11001] = 0x400D000000000000ull, /* 16 */ + [0b11010] = 0x4006000000000000ull, /* 2^7 */ + [0b11011] = 0x4007000000000000ull, /* 2^8 */ + [0b11100] = 0x400E000000000000ull, /* 2^15 */ + [0b11101] = 0x400F000000000000ull, /* 2^16 */ + [0b11110] = 0x7FFF000000000000ull, /* +inf */ + [0b11111] = defaultNaNF128UI64 + }; + + static_assert(defaultNaNF128UI0 == 0, "LSBs of quad-precision NaN must be zero"); + + ui128_f128 ui; + ui.ui.v64 = bits[insn.rs1()]; + ui.ui.v0 = 0; + WRITE_FRD(f128(ui.f)); +} diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fli_s.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fli_s.h new file mode 100644 index 0000000000..e03b3b7f11 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fli_s.h @@ -0,0 +1,40 @@ +require_extension('F'); +require_extension(EXT_ZFA); +require_fp; +{ + const uint32_t bits[32] = { + [0b00000] = 0xbf800000, /* -1.0 */ + [0b00001] = 0x00800000, /* minimum positive normal */ + [0b00010] = 0x37800000, /* 1.0 * 2^-16 */ + [0b00011] = 0x38000000, /* 1.0 * 2^-15 */ + [0b00100] = 0x3b800000, /* 1.0 * 2^-8 */ + [0b00101] = 0x3c000000, /* 1.0 * 2^-7 */ + [0b00110] = 0x3d800000, /* 1.0 * 2^-4 */ + [0b00111] = 0x3e000000, /* 1.0 * 2^-3 */ + [0b01000] = 0x3e800000, /* 0.25 */ + [0b01001] = 0x3ea00000, /* 0.3125 */ + [0b01010] = 0x3ec00000, /* 0.375 */ + [0b01011] = 0x3ee00000, /* 0.4375 */ + [0b01100] = 0x3f000000, /* 0.5 */ + [0b01101] = 0x3f200000, /* 0.625 */ + [0b01110] = 0x3f400000, /* 0.75 */ + [0b01111] = 0x3f600000, /* 0.875 */ + [0b10000] = 0x3f800000, /* 1.0 */ + [0b10001] = 0x3fa00000, /* 1.25 */ + [0b10010] = 0x3fc00000, /* 1.5 */ + [0b10011] = 0x3fe00000, /* 1.75 */ + [0b10100] = 0x40000000, /* 2.0 */ + [0b10101] = 0x40200000, /* 2.5 */ + [0b10110] = 0x40400000, /* 3 */ + [0b10111] = 0x40800000, /* 4 */ + [0b11000] = 0x41000000, /* 8 */ + [0b11001] = 0x41800000, /* 16 */ + [0b11010] = 0x43000000, /* 2^7 */ + [0b11011] = 0x43800000, /* 2^8 */ + [0b11100] = 0x47000000, /* 2^15 */ + [0b11101] = 0x47800000, /* 2^16 */ + [0b11110] = 0x7f800000, /* +inf */ + [0b11111] = defaultNaNF32UI + }; + WRITE_FRD_F(f32(bits[insn.rs1()])); +} diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/flq.h b/vendor/riscv/riscv-isa-sim/riscv/insns/flq.h new file mode 100644 index 0000000000..81d225cd22 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/flq.h @@ -0,0 +1,3 @@ +require_extension('Q'); +require_fp; +WRITE_FRD(MMU.load_float128(RS1 + insn.i_imm())); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/flt_d.h b/vendor/riscv/riscv-isa-sim/riscv/insns/flt_d.h new file mode 100644 index 0000000000..5fb0572425 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/flt_d.h @@ -0,0 +1,4 @@ +require_either_extension('D', EXT_ZDINX); +require_fp; +WRITE_RD(f64_lt(FRS1_D, FRS2_D)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/flt_h.h b/vendor/riscv/riscv-isa-sim/riscv/insns/flt_h.h new file mode 100644 index 0000000000..dd6bc79fdc --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/flt_h.h @@ -0,0 +1,4 @@ +require_either_extension(EXT_ZFH, EXT_ZHINX); +require_fp; +WRITE_RD(f16_lt(FRS1_H, FRS2_H)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/flt_q.h b/vendor/riscv/riscv-isa-sim/riscv/insns/flt_q.h new file mode 100644 index 0000000000..c452141885 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/flt_q.h @@ -0,0 +1,4 @@ +require_extension('Q'); +require_fp; +WRITE_RD(f128_lt(f128(FRS1), f128(FRS2))); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/flt_s.h b/vendor/riscv/riscv-isa-sim/riscv/insns/flt_s.h new file mode 100644 index 0000000000..2f50ed6c3e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/flt_s.h @@ -0,0 +1,4 @@ +require_either_extension('F', EXT_ZFINX); +require_fp; +WRITE_RD(f32_lt(FRS1_F, FRS2_F)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fltq_d.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fltq_d.h new file mode 100644 index 0000000000..c7ec9f112e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fltq_d.h @@ -0,0 +1,4 @@ +require_extension('D'); +require_extension(EXT_ZFA); +require_fp; +WRITE_RD(f64_lt_quiet(FRS1_D, FRS2_D)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fltq_h.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fltq_h.h new file mode 100644 index 0000000000..84d880a63c --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fltq_h.h @@ -0,0 +1,4 @@ +require_extension(EXT_ZFH); +require_extension(EXT_ZFA); +require_fp; +WRITE_RD(f16_lt_quiet(FRS1_H, FRS2_H)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fltq_q.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fltq_q.h new file mode 100644 index 0000000000..a65ca769b7 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fltq_q.h @@ -0,0 +1,4 @@ +require_extension('Q'); +require_extension(EXT_ZFA); +require_fp; +WRITE_RD(f128_lt_quiet(f128(FRS1), f128(FRS2))); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fltq_s.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fltq_s.h new file mode 100644 index 0000000000..1ee09837b2 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fltq_s.h @@ -0,0 +1,4 @@ +require_extension('F'); +require_extension(EXT_ZFA); +require_fp; +WRITE_RD(f32_lt_quiet(FRS1_F, FRS2_F)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/flw.h b/vendor/riscv/riscv-isa-sim/riscv/insns/flw.h new file mode 100644 index 0000000000..c57306a4f6 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/flw.h @@ -0,0 +1,3 @@ +require_extension('F'); +require_fp; +WRITE_FRD(f32(MMU.load<uint32_t>(RS1 + insn.i_imm()))); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fmadd_d.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fmadd_d.h new file mode 100644 index 0000000000..07a8b255b0 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fmadd_d.h @@ -0,0 +1,5 @@ +require_either_extension('D', EXT_ZDINX); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD_D(f64_mulAdd(FRS1_D, FRS2_D, FRS3_D)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fmadd_h.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fmadd_h.h new file mode 100644 index 0000000000..5428897a94 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fmadd_h.h @@ -0,0 +1,5 @@ +require_either_extension(EXT_ZFH, EXT_ZHINX); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD_H(f16_mulAdd(FRS1_H, FRS2_H, FRS3_H)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fmadd_q.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fmadd_q.h new file mode 100644 index 0000000000..882dfc1dce --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fmadd_q.h @@ -0,0 +1,5 @@ +require_extension('Q'); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD(f128_mulAdd(f128(FRS1), f128(FRS2), f128(FRS3))); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fmadd_s.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fmadd_s.h new file mode 100644 index 0000000000..5a72cf81be --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fmadd_s.h @@ -0,0 +1,5 @@ +require_either_extension('F', EXT_ZFINX); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD_F(f32_mulAdd(FRS1_F, FRS2_F, FRS3_F)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fmax_d.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fmax_d.h new file mode 100644 index 0000000000..3e05b7e600 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fmax_d.h @@ -0,0 +1,9 @@ +require_either_extension('D', EXT_ZDINX); +require_fp; +bool greater = f64_lt_quiet(FRS2_D, FRS1_D) || + (f64_eq(FRS2_D, FRS1_D) && (FRS2_D.v & F64_SIGN)); +if (isNaNF64UI(FRS1_D.v) && isNaNF64UI(FRS2_D.v)) + WRITE_FRD_D(f64(defaultNaNF64UI)); +else + WRITE_FRD_D((greater || isNaNF64UI(FRS2_D.v) ? FRS1_D : FRS2_D)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fmax_h.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fmax_h.h new file mode 100644 index 0000000000..c86425841d --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fmax_h.h @@ -0,0 +1,4 @@ +require_either_extension(EXT_ZFH, EXT_ZHINX); +require_fp; +WRITE_FRD_H(f16_max(FRS1_H, FRS2_H)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fmax_q.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fmax_q.h new file mode 100644 index 0000000000..7dd7884a67 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fmax_q.h @@ -0,0 +1,9 @@ +require_extension('Q'); +require_fp; +bool greater = f128_lt_quiet(f128(FRS2), f128(FRS1)) || + (f128_eq(f128(FRS2), f128(FRS1)) && (f128(FRS2).v[1] & F64_SIGN)); +if (isNaNF128(f128(FRS1)) && isNaNF128(f128(FRS2))) + WRITE_FRD(f128(defaultNaNF128())); +else + WRITE_FRD(greater || isNaNF128(f128(FRS2)) ? FRS1 : FRS2); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fmax_s.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fmax_s.h new file mode 100644 index 0000000000..17d8b3c8de --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fmax_s.h @@ -0,0 +1,9 @@ +require_either_extension('F', EXT_ZFINX); +require_fp; +bool greater = f32_lt_quiet(FRS2_F, FRS1_F) || + (f32_eq(FRS2_F, FRS1_F) && (FRS2_F.v & F32_SIGN)); +if (isNaNF32UI(FRS1_F.v) && isNaNF32UI(FRS2_F.v)) + WRITE_FRD_F(f32(defaultNaNF32UI)); +else + WRITE_FRD_F((greater || isNaNF32UI(FRS2_F.v) ? FRS1_F : FRS2_F)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fmaxm_d.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fmaxm_d.h new file mode 100644 index 0000000000..0cecd640ee --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fmaxm_d.h @@ -0,0 +1,10 @@ +require_extension('D'); +require_extension(EXT_ZFA); +require_fp; +bool greater = f64_lt_quiet(FRS2_D, FRS1_D) || + (f64_eq(FRS2_D, FRS1_D) && (FRS2_D.v & F64_SIGN)); +if (isNaNF64UI(FRS1_D.v) || isNaNF64UI(FRS2_D.v)) + WRITE_FRD_D(f64(defaultNaNF64UI)); +else + WRITE_FRD_D(greater ? FRS1_D : FRS2_D); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fmaxm_h.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fmaxm_h.h new file mode 100644 index 0000000000..0eb00eaf99 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fmaxm_h.h @@ -0,0 +1,10 @@ +require_extension(EXT_ZFH); +require_extension(EXT_ZFA); +require_fp; +bool greater = f16_lt_quiet(FRS2_H, FRS1_H) || + (f16_eq(FRS2_H, FRS1_H) && (FRS2_H.v & F16_SIGN)); +if (isNaNF16UI(FRS1_H.v) || isNaNF16UI(FRS2_H.v)) + WRITE_FRD_H(f16(defaultNaNF16UI)); +else + WRITE_FRD_H(greater ? FRS1_H : FRS2_H); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fmaxm_q.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fmaxm_q.h new file mode 100644 index 0000000000..a48031e22b --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fmaxm_q.h @@ -0,0 +1,17 @@ +require_extension('D'); +require_extension(EXT_ZFA); +require_fp; +ui128_f128 ui1; +ui1.f = f128(FRS1); +ui128_f128 ui2; +ui2.f = f128(FRS2); +bool greater = f128_lt_quiet(f128(FRS2), f128(FRS1)) || + (f128_eq(f128(FRS1), f128(FRS2)) && (signF128UI64(ui2.ui.v64))); +if (isNaNF128UI(ui1.ui.v64, ui1.ui.v0) || isNaNF128UI(ui2.ui.v64, ui2.ui.v0)) { + ui128_f128 ui; + ui.ui.v64 = defaultNaNF128UI64; + ui.ui.v0 = defaultNaNF128UI0; + WRITE_FRD(f128(ui.f)); + } else + WRITE_FRD(greater ? f128(FRS1) : f128(FRS2)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fmaxm_s.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fmaxm_s.h new file mode 100644 index 0000000000..ebf195a153 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fmaxm_s.h @@ -0,0 +1,10 @@ +require_extension('F'); +require_extension(EXT_ZFA); +require_fp; +bool greater = f32_lt_quiet(FRS2_F, FRS1_F) || + (f32_eq(FRS2_F, FRS1_F) && (FRS2_F.v & F32_SIGN)); +if (isNaNF32UI(FRS1_F.v) || isNaNF32UI(FRS2_F.v)) + WRITE_FRD_F(f32(defaultNaNF32UI)); +else + WRITE_FRD_F(greater ? FRS1_F : FRS2_F); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fmin_d.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fmin_d.h new file mode 100644 index 0000000000..f60a73e796 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fmin_d.h @@ -0,0 +1,9 @@ +require_either_extension('D', EXT_ZDINX); +require_fp; +bool less = f64_lt_quiet(FRS1_D, FRS2_D) || + (f64_eq(FRS1_D, FRS2_D) && (FRS1_D.v & F64_SIGN)); +if (isNaNF64UI(FRS1_D.v) && isNaNF64UI(FRS2_D.v)) + WRITE_FRD_D(f64(defaultNaNF64UI)); +else + WRITE_FRD_D((less || isNaNF64UI(FRS2_D.v) ? FRS1_D : FRS2_D)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fmin_h.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fmin_h.h new file mode 100644 index 0000000000..cd02f20e11 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fmin_h.h @@ -0,0 +1,4 @@ +require_either_extension(EXT_ZFH, EXT_ZHINX); +require_fp; +WRITE_FRD_H(f16_min(FRS1_H, FRS2_H)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fmin_q.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fmin_q.h new file mode 100644 index 0000000000..fcb9526efd --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fmin_q.h @@ -0,0 +1,9 @@ +require_extension('Q'); +require_fp; +bool less = f128_lt_quiet(f128(FRS1), f128(FRS2)) || + (f128_eq(f128(FRS1), f128(FRS2)) && (f128(FRS1).v[1] & F64_SIGN)); +if (isNaNF128(f128(FRS1)) && isNaNF128(f128(FRS2))) + WRITE_FRD(f128(defaultNaNF128())); +else + WRITE_FRD(less || isNaNF128(f128(FRS2)) ? FRS1 : FRS2); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fmin_s.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fmin_s.h new file mode 100644 index 0000000000..476a586092 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fmin_s.h @@ -0,0 +1,9 @@ +require_either_extension('F', EXT_ZFINX); +require_fp; +bool less = f32_lt_quiet(FRS1_F, FRS2_F) || + (f32_eq(FRS1_F, FRS2_F) && (FRS1_F.v & F32_SIGN)); +if (isNaNF32UI(FRS1_F.v) && isNaNF32UI(FRS2_F.v)) + WRITE_FRD_F(f32(defaultNaNF32UI)); +else + WRITE_FRD_F((less || isNaNF32UI(FRS2_F.v) ? FRS1_F : FRS2_F)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fminm_d.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fminm_d.h new file mode 100644 index 0000000000..a60d3e88c6 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fminm_d.h @@ -0,0 +1,10 @@ +require_extension('D'); +require_extension(EXT_ZFA); +require_fp; +bool less = f64_lt_quiet(FRS1_D, FRS2_D) || + (f64_eq(FRS2_D, FRS1_D) && (FRS1_D.v & F64_SIGN)); +if (isNaNF64UI(FRS1_D.v) || isNaNF64UI(FRS2_D.v)) + WRITE_FRD_D(f64(defaultNaNF64UI)); +else + WRITE_FRD_D(less ? FRS1_D : FRS2_D); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fminm_h.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fminm_h.h new file mode 100644 index 0000000000..0f207e8063 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fminm_h.h @@ -0,0 +1,10 @@ +require_extension(EXT_ZFH); +require_extension(EXT_ZFA); +require_fp; +bool less = f16_lt_quiet(FRS1_H, FRS2_H) || + (f16_eq(FRS2_H, FRS1_H) && (FRS1_H.v & F16_SIGN)); +if (isNaNF16UI(FRS1_H.v) || isNaNF16UI(FRS2_H.v)) + WRITE_FRD_H(f16(defaultNaNF16UI)); +else + WRITE_FRD_H(less ? FRS1_H : FRS2_H); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fminm_q.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fminm_q.h new file mode 100644 index 0000000000..bccd7ed634 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fminm_q.h @@ -0,0 +1,17 @@ +require_extension('Q'); +require_extension(EXT_ZFA); +require_fp; +ui128_f128 ui1; +ui1.f = f128(FRS1); +ui128_f128 ui2; +ui2.f = f128(FRS2); +bool less = f128_lt_quiet(f128(FRS1), f128(FRS2)) || + (f128_eq(f128(FRS1), f128(FRS2)) && (signF128UI64(ui1.ui.v64))); +if (isNaNF128UI(ui1.ui.v64, ui1.ui.v0) || isNaNF128UI(ui2.ui.v64, ui2.ui.v0)) { + ui128_f128 ui; + ui.ui.v64 = defaultNaNF128UI64; + ui.ui.v0 = defaultNaNF128UI0; + WRITE_FRD(f128(ui.f)); + } else + WRITE_FRD(less ? f128(FRS1) : f128(FRS2)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fminm_s.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fminm_s.h new file mode 100644 index 0000000000..b1c60f84d6 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fminm_s.h @@ -0,0 +1,10 @@ +require_extension('F'); +require_extension(EXT_ZFA); +require_fp; +bool less = f32_lt_quiet(FRS1_F, FRS2_F) || + (f32_eq(FRS2_F, FRS1_F) && (FRS1_F.v & F32_SIGN)); +if (isNaNF32UI(FRS1_F.v) || isNaNF32UI(FRS2_F.v)) + WRITE_FRD_F(f32(defaultNaNF32UI)); +else + WRITE_FRD_F(less ? FRS1_F : FRS2_F); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fmsub_d.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fmsub_d.h new file mode 100644 index 0000000000..1a7d7847cc --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fmsub_d.h @@ -0,0 +1,5 @@ +require_either_extension('D', EXT_ZDINX); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD_D(f64_mulAdd(FRS1_D, FRS2_D, f64(FRS3_D.v ^ F64_SIGN))); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fmsub_h.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fmsub_h.h new file mode 100644 index 0000000000..dc6a8e6c84 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fmsub_h.h @@ -0,0 +1,5 @@ +require_either_extension(EXT_ZFH, EXT_ZHINX); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD_H(f16_mulAdd(FRS1_H, FRS2_H, f16(FRS3_H.v ^ F16_SIGN))); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fmsub_q.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fmsub_q.h new file mode 100644 index 0000000000..1bb96c2704 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fmsub_q.h @@ -0,0 +1,5 @@ +require_extension('Q'); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD(f128_mulAdd(f128(FRS1), f128(FRS2), f128_negate(f128(FRS3)))); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fmsub_s.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fmsub_s.h new file mode 100644 index 0000000000..179cc2f651 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fmsub_s.h @@ -0,0 +1,5 @@ +require_either_extension('F', EXT_ZFINX); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD_F(f32_mulAdd(FRS1_F, FRS2_F, f32(FRS3_F.v ^ F32_SIGN))); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fmul_d.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fmul_d.h new file mode 100644 index 0000000000..e5caa34c99 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fmul_d.h @@ -0,0 +1,5 @@ +require_either_extension('D', EXT_ZDINX); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD_D(f64_mul(FRS1_D, FRS2_D)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fmul_h.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fmul_h.h new file mode 100644 index 0000000000..dc7f9c47b5 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fmul_h.h @@ -0,0 +1,5 @@ +require_either_extension(EXT_ZFH, EXT_ZHINX); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD_H(f16_mul(FRS1_H, FRS2_H)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fmul_q.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fmul_q.h new file mode 100644 index 0000000000..66f5a05cef --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fmul_q.h @@ -0,0 +1,5 @@ +require_extension('Q'); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD(f128_mul(f128(FRS1), f128(FRS2))); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fmul_s.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fmul_s.h new file mode 100644 index 0000000000..9cf30b4bdd --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fmul_s.h @@ -0,0 +1,5 @@ +require_either_extension('F', EXT_ZFINX); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD_F(f32_mul(FRS1_F, FRS2_F)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fmv_d_x.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fmv_d_x.h new file mode 100644 index 0000000000..0bff5fb754 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fmv_d_x.h @@ -0,0 +1,4 @@ +require_extension('D'); +require_rv64; +require_fp; +WRITE_FRD(f64(RS1)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fmv_h_x.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fmv_h_x.h new file mode 100644 index 0000000000..e55d607b17 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fmv_h_x.h @@ -0,0 +1,3 @@ +require_extension(EXT_ZFHMIN); +require_fp; +WRITE_FRD(f16(RS1)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fmv_w_x.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fmv_w_x.h new file mode 100644 index 0000000000..5f713231cb --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fmv_w_x.h @@ -0,0 +1,3 @@ +require_extension('F'); +require_fp; +WRITE_FRD(f32(RS1)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fmv_x_d.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fmv_x_d.h new file mode 100644 index 0000000000..e1a23f4827 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fmv_x_d.h @@ -0,0 +1,4 @@ +require_extension('D'); +require_rv64; +require_fp; +WRITE_RD(FRS1.v[0]); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fmv_x_h.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fmv_x_h.h new file mode 100644 index 0000000000..7a2e5ff6bf --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fmv_x_h.h @@ -0,0 +1,3 @@ +require_extension(EXT_ZFHMIN); +require_fp; +WRITE_RD(sext32((int16_t)(FRS1.v[0]))); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fmv_x_w.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fmv_x_w.h new file mode 100644 index 0000000000..6754f8693f --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fmv_x_w.h @@ -0,0 +1,3 @@ +require_extension('F'); +require_fp; +WRITE_RD(sext32(FRS1.v[0])); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fmvh_x_d.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fmvh_x_d.h new file mode 100644 index 0000000000..961ad765d9 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fmvh_x_d.h @@ -0,0 +1,7 @@ +require_rv32; +require_extension('D'); +require_extension(EXT_ZFA); +require_fp; +ui64_f64 ui; +ui.f = FRS1_D; +WRITE_RD(ui.ui >> 32); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fmvh_x_q.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fmvh_x_q.h new file mode 100644 index 0000000000..12a3923ba3 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fmvh_x_q.h @@ -0,0 +1,7 @@ +require_rv64; +require_extension('Q'); +require_extension(EXT_ZFA); +require_fp; +ui128_f128 ui; +ui.f = f128(FRS1); +WRITE_RD(ui.ui.v64); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fmvp_d_x.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fmvp_d_x.h new file mode 100644 index 0000000000..f95cfe9684 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fmvp_d_x.h @@ -0,0 +1,8 @@ +require_rv32; +require_extension('D'); +require_extension(EXT_ZFA); +require_fp; +ui64_f64 ui; +ui.ui = ((uint64_t)RS2) << 32; +ui.ui |= RS1; +WRITE_FRD_D(f64(ui.ui)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fmvp_q_x.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fmvp_q_x.h new file mode 100644 index 0000000000..99c7bfd625 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fmvp_q_x.h @@ -0,0 +1,8 @@ +require_rv64; +require_extension('Q'); +require_extension(EXT_ZFA); +require_fp; +ui128_f128 ui; +ui.ui.v64 = RS2; +ui.ui.v0 = RS1; +WRITE_FRD(f128(ui.f)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fnmadd_d.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fnmadd_d.h new file mode 100644 index 0000000000..a2a14e9cd6 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fnmadd_d.h @@ -0,0 +1,5 @@ +require_either_extension('D', EXT_ZDINX); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD_D(f64_mulAdd(f64(FRS1_D.v ^ F64_SIGN), FRS2_D, f64(FRS3_D.v ^ F64_SIGN))); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fnmadd_h.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fnmadd_h.h new file mode 100644 index 0000000000..b1ca28328c --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fnmadd_h.h @@ -0,0 +1,5 @@ +require_either_extension(EXT_ZFH, EXT_ZHINX); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD_H(f16_mulAdd(f16(FRS1_H.v ^ F16_SIGN), FRS2_H, f16(FRS3_H.v ^ F16_SIGN))); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fnmadd_q.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fnmadd_q.h new file mode 100644 index 0000000000..a36ce188bb --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fnmadd_q.h @@ -0,0 +1,5 @@ +require_extension('Q'); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD(f128_mulAdd(f128_negate(f128(FRS1)), f128(FRS2), f128_negate(f128(FRS3)))); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fnmadd_s.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fnmadd_s.h new file mode 100644 index 0000000000..683257ad83 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fnmadd_s.h @@ -0,0 +1,5 @@ +require_either_extension('F', EXT_ZFINX); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD_F(f32_mulAdd(f32(FRS1_F.v ^ F32_SIGN), FRS2_F, f32(FRS3_F.v ^ F32_SIGN))); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fnmsub_d.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fnmsub_d.h new file mode 100644 index 0000000000..9352c3fd2c --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fnmsub_d.h @@ -0,0 +1,5 @@ +require_either_extension('D', EXT_ZDINX); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD_D(f64_mulAdd(f64(FRS1_D.v ^ F64_SIGN), FRS2_D, FRS3_D)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fnmsub_h.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fnmsub_h.h new file mode 100644 index 0000000000..e05fcd1fbf --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fnmsub_h.h @@ -0,0 +1,5 @@ +require_either_extension(EXT_ZFH, EXT_ZHINX); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD_H(f16_mulAdd(f16(FRS1_H.v ^ F16_SIGN), FRS2_H, FRS3_H)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fnmsub_q.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fnmsub_q.h new file mode 100644 index 0000000000..130b4ce3f5 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fnmsub_q.h @@ -0,0 +1,5 @@ +require_extension('Q'); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD(f128_mulAdd(f128_negate(f128(FRS1)), f128(FRS2), f128(FRS3))); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fnmsub_s.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fnmsub_s.h new file mode 100644 index 0000000000..b22b3db6dc --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fnmsub_s.h @@ -0,0 +1,5 @@ +require_either_extension('F', EXT_ZFINX); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD_F(f32_mulAdd(f32(FRS1_F.v ^ F32_SIGN), FRS2_F, FRS3_F)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fround_d.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fround_d.h new file mode 100644 index 0000000000..1127135093 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fround_d.h @@ -0,0 +1,5 @@ +require_extension('D'); +require_extension(EXT_ZFA); +require_fp; +WRITE_FRD_D(f64_roundToInt(FRS1_D, RM, true)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fround_h.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fround_h.h new file mode 100644 index 0000000000..6417a39c6a --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fround_h.h @@ -0,0 +1,5 @@ +require_extension(EXT_ZFH); +require_extension(EXT_ZFA); +require_fp; +WRITE_FRD_H(f16_roundToInt(FRS1_H, RM, true)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fround_q.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fround_q.h new file mode 100644 index 0000000000..51ebce2378 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fround_q.h @@ -0,0 +1,5 @@ +require_extension('Q'); +require_extension(EXT_ZFA); +require_fp; +WRITE_FRD(f128_roundToInt(f128(FRS1), RM, true)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fround_s.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fround_s.h new file mode 100644 index 0000000000..272897ed13 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fround_s.h @@ -0,0 +1,5 @@ +require_extension('F'); +require_extension(EXT_ZFA); +require_fp; +WRITE_FRD_F(f32_roundToInt(FRS1_F, RM, true)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/froundnx_d.h b/vendor/riscv/riscv-isa-sim/riscv/insns/froundnx_d.h new file mode 100644 index 0000000000..0e8a1ba6d2 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/froundnx_d.h @@ -0,0 +1,5 @@ +require_extension('D'); +require_extension(EXT_ZFA); +require_fp; +WRITE_FRD_D(f64_roundToInt(FRS1_D, RM, false)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/froundnx_h.h b/vendor/riscv/riscv-isa-sim/riscv/insns/froundnx_h.h new file mode 100644 index 0000000000..0c6cdae4c3 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/froundnx_h.h @@ -0,0 +1,5 @@ +require_extension(EXT_ZFH); +require_extension(EXT_ZFA); +require_fp; +WRITE_FRD_H(f16_roundToInt(FRS1_H, RM, false)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/froundnx_q.h b/vendor/riscv/riscv-isa-sim/riscv/insns/froundnx_q.h new file mode 100644 index 0000000000..91bab77e27 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/froundnx_q.h @@ -0,0 +1,5 @@ +require_extension('Q'); +require_extension(EXT_ZFA); +require_fp; +WRITE_FRD(f128_roundToInt(f128(FRS1), RM, false)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/froundnx_s.h b/vendor/riscv/riscv-isa-sim/riscv/insns/froundnx_s.h new file mode 100644 index 0000000000..f6e75f5d3e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/froundnx_s.h @@ -0,0 +1,5 @@ +require_extension('F'); +require_extension(EXT_ZFA); +require_fp; +WRITE_FRD_F(f32_roundToInt(FRS1_F, RM, false)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fsd.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fsd.h new file mode 100644 index 0000000000..babc9e58f8 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fsd.h @@ -0,0 +1,3 @@ +require_extension('D'); +require_fp; +MMU.store<uint64_t>(RS1 + insn.s_imm(), FRS2.v[0]); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fsgnj_d.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fsgnj_d.h new file mode 100644 index 0000000000..8f02fd11f2 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fsgnj_d.h @@ -0,0 +1,3 @@ +require_either_extension('D', EXT_ZDINX); +require_fp; +WRITE_FRD_D(fsgnj64(freg(FRS1_D), freg(FRS2_D), false, false)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fsgnj_h.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fsgnj_h.h new file mode 100644 index 0000000000..080f27d8c1 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fsgnj_h.h @@ -0,0 +1,3 @@ +require_either_extension(EXT_ZFH, EXT_ZHINX); +require_fp; +WRITE_FRD_H(fsgnj16(freg(FRS1_H), freg(FRS2_H), false, false)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fsgnj_q.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fsgnj_q.h new file mode 100644 index 0000000000..0b9a27083d --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fsgnj_q.h @@ -0,0 +1,3 @@ +require_extension('Q'); +require_fp; +WRITE_FRD(fsgnj128(FRS1, FRS2, false, false)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fsgnj_s.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fsgnj_s.h new file mode 100644 index 0000000000..ea511b89e1 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fsgnj_s.h @@ -0,0 +1,3 @@ +require_either_extension('F', EXT_ZFINX); +require_fp; +WRITE_FRD_F(fsgnj32(freg(FRS1_F), freg(FRS2_F), false, false)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fsgnjn_d.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fsgnjn_d.h new file mode 100644 index 0000000000..870a9793f0 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fsgnjn_d.h @@ -0,0 +1,3 @@ +require_either_extension('D', EXT_ZDINX); +require_fp; +WRITE_FRD_D(fsgnj64(freg(FRS1_D), freg(FRS2_D), true, false)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fsgnjn_h.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fsgnjn_h.h new file mode 100644 index 0000000000..1d7bf03b96 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fsgnjn_h.h @@ -0,0 +1,3 @@ +require_either_extension(EXT_ZFH, EXT_ZHINX); +require_fp; +WRITE_FRD_H(fsgnj16(freg(FRS1_H), freg(FRS2_H), true, false)); \ No newline at end of file diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fsgnjn_q.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fsgnjn_q.h new file mode 100644 index 0000000000..dcf7235508 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fsgnjn_q.h @@ -0,0 +1,3 @@ +require_extension('Q'); +require_fp; +WRITE_FRD(fsgnj128(FRS1, FRS2, true, false)); \ No newline at end of file diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fsgnjn_s.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fsgnjn_s.h new file mode 100644 index 0000000000..a0994b4997 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fsgnjn_s.h @@ -0,0 +1,3 @@ +require_either_extension('F', EXT_ZFINX); +require_fp; +WRITE_FRD_F(fsgnj32(freg(FRS1_F), freg(FRS2_F), true, false)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fsgnjx_d.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fsgnjx_d.h new file mode 100644 index 0000000000..25906f0890 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fsgnjx_d.h @@ -0,0 +1,3 @@ +require_either_extension('D', EXT_ZDINX); +require_fp; +WRITE_FRD_D(fsgnj64(freg(FRS1_D), freg(FRS2_D), false, true)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fsgnjx_h.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fsgnjx_h.h new file mode 100644 index 0000000000..1d29bb1fc5 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fsgnjx_h.h @@ -0,0 +1,3 @@ +require_either_extension(EXT_ZFH, EXT_ZHINX); +require_fp; +WRITE_FRD_H(fsgnj16(freg(FRS1_H), freg(FRS2_H), false, true)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fsgnjx_q.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fsgnjx_q.h new file mode 100644 index 0000000000..fc86d26d9a --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fsgnjx_q.h @@ -0,0 +1,3 @@ +require_extension('Q'); +require_fp; +WRITE_FRD(fsgnj128(FRS1, FRS2, false, true)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fsgnjx_s.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fsgnjx_s.h new file mode 100644 index 0000000000..9bc0798887 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fsgnjx_s.h @@ -0,0 +1,3 @@ +require_either_extension('F', EXT_ZFINX); +require_fp; +WRITE_FRD_F(fsgnj32(freg(FRS1_F), freg(FRS2_F), false, true)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fsh.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fsh.h new file mode 100644 index 0000000000..dfd6bc5ca9 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fsh.h @@ -0,0 +1,3 @@ +require_extension(EXT_ZFHMIN); +require_fp; +MMU.store<uint16_t>(RS1 + insn.s_imm(), FRS2.v[0]); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fsl.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fsl.h new file mode 100644 index 0000000000..53a21608d9 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fsl.h @@ -0,0 +1,9 @@ +require_extension(EXT_XZBT); +int shamt = RS2 & (2*xlen-1); +reg_t a = RS1, b = RS3; +if (shamt >= xlen) { + a = RS3, b = RS1; + shamt -= xlen; +} +int rshamt = -shamt & (xlen-1); +WRITE_RD(sext_xlen(shamt ? (a << shamt) | (zext_xlen(b) >> rshamt) : a)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fslw.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fslw.h new file mode 100644 index 0000000000..83940105b8 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fslw.h @@ -0,0 +1,10 @@ +require_rv64; +require_extension(EXT_XZBT); +int shamt = RS2 & 63; +reg_t a = RS1, b = RS3; +if (shamt >= 32) { + a = RS3, b = RS1; + shamt -= 32; +} +int rshamt = -shamt & 31; +WRITE_RD(sext32(shamt ? (a << shamt) | (zext32(b) >> rshamt) : a)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fsq.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fsq.h new file mode 100644 index 0000000000..610960e599 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fsq.h @@ -0,0 +1,3 @@ +require_extension('Q'); +require_fp; +MMU.store_float128(RS1 + insn.s_imm(), FRS2); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fsqrt_d.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fsqrt_d.h new file mode 100644 index 0000000000..363b457f42 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fsqrt_d.h @@ -0,0 +1,5 @@ +require_either_extension('D', EXT_ZDINX); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD_D(f64_sqrt(FRS1_D)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fsqrt_h.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fsqrt_h.h new file mode 100644 index 0000000000..fea429bd0c --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fsqrt_h.h @@ -0,0 +1,5 @@ +require_either_extension(EXT_ZFH, EXT_ZHINX); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD_H(f16_sqrt(FRS1_H)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fsqrt_q.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fsqrt_q.h new file mode 100644 index 0000000000..6cb6ba3117 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fsqrt_q.h @@ -0,0 +1,5 @@ +require_extension('Q'); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD(f128_sqrt(f128(FRS1))); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fsqrt_s.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fsqrt_s.h new file mode 100644 index 0000000000..d44503a76d --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fsqrt_s.h @@ -0,0 +1,5 @@ +require_either_extension('F', EXT_ZFINX); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD_F(f32_sqrt(FRS1_F)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fsr.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fsr.h new file mode 100644 index 0000000000..dfb26f11e1 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fsr.h @@ -0,0 +1,9 @@ +require_either_extension(xlen == 32 ? EXT_ZBPBO : EXT_XZBT, EXT_XZBT); +int shamt = RS2 & (2*xlen-1); +reg_t a = RS1, b = RS3; +if (shamt >= xlen) { + a = RS3, b = RS1; + shamt -= xlen; +} +int rshamt = -shamt & (xlen-1); +WRITE_RD(sext_xlen(shamt ? (b << rshamt) | (zext_xlen(a) >> shamt) : a)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fsri.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fsri.h new file mode 100644 index 0000000000..f7186f1b6a --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fsri.h @@ -0,0 +1,9 @@ +require_either_extension(xlen == 32 ? EXT_ZBPBO : EXT_XZBT, EXT_XZBT); +int shamt = SHAMT & (2*xlen-1); +reg_t a = RS1, b = RS3; +if (shamt >= xlen) { + a = RS3, b = RS1; + shamt -= xlen; +} +int rshamt = -shamt & (xlen-1); +WRITE_RD(sext_xlen(shamt ? (b << rshamt) | (zext_xlen(a) >> shamt) : a)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fsriw.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fsriw.h new file mode 100644 index 0000000000..7956de7ce7 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fsriw.h @@ -0,0 +1,10 @@ +require_rv64; +require_extension(EXT_XZBT); +int shamt = SHAMT & 63; +reg_t a = RS1, b = RS3; +if (shamt >= 32) { + a = RS3, b = RS1; + shamt -= 32; +} +int rshamt = -shamt & 31; +WRITE_RD(sext32(shamt ? (b << rshamt) | (zext32(a) >> shamt) : a)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fsrw.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fsrw.h new file mode 100644 index 0000000000..494fe260cc --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fsrw.h @@ -0,0 +1,10 @@ +require_rv64; +require_either_extension(EXT_ZBPBO, EXT_XZBT); +int shamt = RS2 & 63; +reg_t a = RS1, b = RS3; +if (shamt >= 32) { + a = RS3, b = RS1; + shamt -= 32; +} +int rshamt = -shamt & 31; +WRITE_RD(sext32(shamt ? (b << rshamt) | (zext32(a) >> shamt) : a)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fsub_d.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fsub_d.h new file mode 100644 index 0000000000..4f8bf509b8 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fsub_d.h @@ -0,0 +1,5 @@ +require_either_extension('D', EXT_ZDINX); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD_D(f64_sub(FRS1_D, FRS2_D)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fsub_h.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fsub_h.h new file mode 100644 index 0000000000..f7006fb08f --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fsub_h.h @@ -0,0 +1,5 @@ +require_either_extension(EXT_ZFH, EXT_ZHINX); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD_H(f16_sub(FRS1_H, FRS2_H)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fsub_q.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fsub_q.h new file mode 100644 index 0000000000..e050e3aa98 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fsub_q.h @@ -0,0 +1,5 @@ +require_extension('Q'); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD(f128_sub(f128(FRS1), f128(FRS2))); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fsub_s.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fsub_s.h new file mode 100644 index 0000000000..1a33ffdbf3 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fsub_s.h @@ -0,0 +1,5 @@ +require_either_extension('F', EXT_ZFINX); +require_fp; +softfloat_roundingMode = RM; +WRITE_FRD_F(f32_sub(FRS1_F, FRS2_F)); +set_fp_exceptions; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/fsw.h b/vendor/riscv/riscv-isa-sim/riscv/insns/fsw.h new file mode 100644 index 0000000000..887f03ea81 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/fsw.h @@ -0,0 +1,3 @@ +require_extension('F'); +require_fp; +MMU.store<uint32_t>(RS1 + insn.s_imm(), FRS2.v[0]); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/gorc.h b/vendor/riscv/riscv-isa-sim/riscv/insns/gorc.h new file mode 100644 index 0000000000..ffe441347d --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/gorc.h @@ -0,0 +1,10 @@ +require_extension(EXT_XZBP); +reg_t x = RS1; +int shamt = RS2 & (xlen-1); +if (shamt & 1) x |= ((x & 0x5555555555555555LL) << 1) | ((x & 0xAAAAAAAAAAAAAAAALL) >> 1); +if (shamt & 2) x |= ((x & 0x3333333333333333LL) << 2) | ((x & 0xCCCCCCCCCCCCCCCCLL) >> 2); +if (shamt & 4) x |= ((x & 0x0F0F0F0F0F0F0F0FLL) << 4) | ((x & 0xF0F0F0F0F0F0F0F0LL) >> 4); +if (shamt & 8) x |= ((x & 0x00FF00FF00FF00FFLL) << 8) | ((x & 0xFF00FF00FF00FF00LL) >> 8); +if (shamt & 16) x |= ((x & 0x0000FFFF0000FFFFLL) << 16) | ((x & 0xFFFF0000FFFF0000LL) >> 16); +if (shamt & 32) x |= ((x & 0x00000000FFFFFFFFLL) << 32) | ((x & 0xFFFFFFFF00000000LL) >> 32); +WRITE_RD(sext_xlen(x)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/gorci.h b/vendor/riscv/riscv-isa-sim/riscv/insns/gorci.h new file mode 100644 index 0000000000..d3017f499e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/gorci.h @@ -0,0 +1,13 @@ +// Zbb contains orc.b but not general gorci +require(((SHAMT == 7) && p->extension_enabled(EXT_ZBB)) + || p->extension_enabled(EXT_XZBP)); +require(SHAMT < xlen); +reg_t x = RS1; +int shamt = SHAMT; +if (shamt & 1) x |= ((x & 0x5555555555555555LL) << 1) | ((x & 0xAAAAAAAAAAAAAAAALL) >> 1); +if (shamt & 2) x |= ((x & 0x3333333333333333LL) << 2) | ((x & 0xCCCCCCCCCCCCCCCCLL) >> 2); +if (shamt & 4) x |= ((x & 0x0F0F0F0F0F0F0F0FLL) << 4) | ((x & 0xF0F0F0F0F0F0F0F0LL) >> 4); +if (shamt & 8) x |= ((x & 0x00FF00FF00FF00FFLL) << 8) | ((x & 0xFF00FF00FF00FF00LL) >> 8); +if (shamt & 16) x |= ((x & 0x0000FFFF0000FFFFLL) << 16) | ((x & 0xFFFF0000FFFF0000LL) >> 16); +if (shamt & 32) x |= ((x & 0x00000000FFFFFFFFLL) << 32) | ((x & 0xFFFFFFFF00000000LL) >> 32); +WRITE_RD(sext_xlen(x)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/gorciw.h b/vendor/riscv/riscv-isa-sim/riscv/insns/gorciw.h new file mode 100644 index 0000000000..44ade807ea --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/gorciw.h @@ -0,0 +1,11 @@ +require_rv64; +require_extension(EXT_XZBP); +require(SHAMT < 32); +reg_t x = RS1; +int shamt = SHAMT; +if (shamt & 1) x |= ((x & 0x5555555555555555LL) << 1) | ((x & 0xAAAAAAAAAAAAAAAALL) >> 1); +if (shamt & 2) x |= ((x & 0x3333333333333333LL) << 2) | ((x & 0xCCCCCCCCCCCCCCCCLL) >> 2); +if (shamt & 4) x |= ((x & 0x0F0F0F0F0F0F0F0FLL) << 4) | ((x & 0xF0F0F0F0F0F0F0F0LL) >> 4); +if (shamt & 8) x |= ((x & 0x00FF00FF00FF00FFLL) << 8) | ((x & 0xFF00FF00FF00FF00LL) >> 8); +if (shamt & 16) x |= ((x & 0x0000FFFF0000FFFFLL) << 16) | ((x & 0xFFFF0000FFFF0000LL) >> 16); +WRITE_RD(sext32(x)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/gorcw.h b/vendor/riscv/riscv-isa-sim/riscv/insns/gorcw.h new file mode 100644 index 0000000000..611b3caa43 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/gorcw.h @@ -0,0 +1,10 @@ +require_rv64; +require_extension(EXT_XZBP); +reg_t x = RS1; +int shamt = RS2 & 31; +if (shamt & 1) x |= ((x & 0x5555555555555555LL) << 1) | ((x & 0xAAAAAAAAAAAAAAAALL) >> 1); +if (shamt & 2) x |= ((x & 0x3333333333333333LL) << 2) | ((x & 0xCCCCCCCCCCCCCCCCLL) >> 2); +if (shamt & 4) x |= ((x & 0x0F0F0F0F0F0F0F0FLL) << 4) | ((x & 0xF0F0F0F0F0F0F0F0LL) >> 4); +if (shamt & 8) x |= ((x & 0x00FF00FF00FF00FFLL) << 8) | ((x & 0xFF00FF00FF00FF00LL) >> 8); +if (shamt & 16) x |= ((x & 0x0000FFFF0000FFFFLL) << 16) | ((x & 0xFFFF0000FFFF0000LL) >> 16); +WRITE_RD(sext32(x)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/grev.h b/vendor/riscv/riscv-isa-sim/riscv/insns/grev.h new file mode 100644 index 0000000000..7181b3cda8 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/grev.h @@ -0,0 +1,10 @@ +require_extension(EXT_XZBP); +reg_t x = RS1; +int shamt = RS2 & (xlen-1); +if (shamt & 1) x = ((x & 0x5555555555555555LL) << 1) | ((x & 0xAAAAAAAAAAAAAAAALL) >> 1); +if (shamt & 2) x = ((x & 0x3333333333333333LL) << 2) | ((x & 0xCCCCCCCCCCCCCCCCLL) >> 2); +if (shamt & 4) x = ((x & 0x0F0F0F0F0F0F0F0FLL) << 4) | ((x & 0xF0F0F0F0F0F0F0F0LL) >> 4); +if (shamt & 8) x = ((x & 0x00FF00FF00FF00FFLL) << 8) | ((x & 0xFF00FF00FF00FF00LL) >> 8); +if (shamt & 16) x = ((x & 0x0000FFFF0000FFFFLL) << 16) | ((x & 0xFFFF0000FFFF0000LL) >> 16); +if (shamt & 32) x = ((x & 0x00000000FFFFFFFFLL) << 32) | ((x & 0xFFFFFFFF00000000LL) >> 32); +WRITE_RD(sext_xlen(x)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/grevi.h b/vendor/riscv/riscv-isa-sim/riscv/insns/grevi.h new file mode 100644 index 0000000000..d4718145b4 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/grevi.h @@ -0,0 +1,17 @@ +// Zbb contains rev8 but not general grevi +// Zbkb contains rev8 and brev8 (a.k.a. rev.b) but not general grevi +int shamt = SHAMT; +require(((shamt == xlen - 8) && (p->extension_enabled(EXT_ZBB) || p->extension_enabled(EXT_ZBKB))) //rev8 + || ((shamt == 7) && p->extension_enabled(EXT_ZBKB)) // rev8.b + || ((shamt == 8) && p->extension_enabled(EXT_ZPN)) // rev8.h + || ((shamt == xlen - 1) && p->extension_enabled(EXT_ZPN)) // rev + || p->extension_enabled(EXT_XZBP)); +require(shamt < xlen); +reg_t x = RS1; +if (shamt & 1) x = ((x & 0x5555555555555555LL) << 1) | ((x & 0xAAAAAAAAAAAAAAAALL) >> 1); +if (shamt & 2) x = ((x & 0x3333333333333333LL) << 2) | ((x & 0xCCCCCCCCCCCCCCCCLL) >> 2); +if (shamt & 4) x = ((x & 0x0F0F0F0F0F0F0F0FLL) << 4) | ((x & 0xF0F0F0F0F0F0F0F0LL) >> 4); +if (shamt & 8) x = ((x & 0x00FF00FF00FF00FFLL) << 8) | ((x & 0xFF00FF00FF00FF00LL) >> 8); +if (shamt & 16) x = ((x & 0x0000FFFF0000FFFFLL) << 16) | ((x & 0xFFFF0000FFFF0000LL) >> 16); +if (shamt & 32) x = ((x & 0x00000000FFFFFFFFLL) << 32) | ((x & 0xFFFFFFFF00000000LL) >> 32); +WRITE_RD(sext_xlen(x)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/greviw.h b/vendor/riscv/riscv-isa-sim/riscv/insns/greviw.h new file mode 100644 index 0000000000..004ecf347c --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/greviw.h @@ -0,0 +1,11 @@ +require_rv64; +require_extension(EXT_XZBP); +require(SHAMT < 32); +reg_t x = RS1; +int shamt = SHAMT; +if (shamt & 1) x = ((x & 0x5555555555555555LL) << 1) | ((x & 0xAAAAAAAAAAAAAAAALL) >> 1); +if (shamt & 2) x = ((x & 0x3333333333333333LL) << 2) | ((x & 0xCCCCCCCCCCCCCCCCLL) >> 2); +if (shamt & 4) x = ((x & 0x0F0F0F0F0F0F0F0FLL) << 4) | ((x & 0xF0F0F0F0F0F0F0F0LL) >> 4); +if (shamt & 8) x = ((x & 0x00FF00FF00FF00FFLL) << 8) | ((x & 0xFF00FF00FF00FF00LL) >> 8); +if (shamt & 16) x = ((x & 0x0000FFFF0000FFFFLL) << 16) | ((x & 0xFFFF0000FFFF0000LL) >> 16); +WRITE_RD(sext32(x)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/grevw.h b/vendor/riscv/riscv-isa-sim/riscv/insns/grevw.h new file mode 100644 index 0000000000..3fbcf228d2 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/grevw.h @@ -0,0 +1,10 @@ +require_rv64; +require_extension(EXT_XZBP); +reg_t x = RS1; +int shamt = RS2 & 31; +if (shamt & 1) x = ((x & 0x5555555555555555LL) << 1) | ((x & 0xAAAAAAAAAAAAAAAALL) >> 1); +if (shamt & 2) x = ((x & 0x3333333333333333LL) << 2) | ((x & 0xCCCCCCCCCCCCCCCCLL) >> 2); +if (shamt & 4) x = ((x & 0x0F0F0F0F0F0F0F0FLL) << 4) | ((x & 0xF0F0F0F0F0F0F0F0LL) >> 4); +if (shamt & 8) x = ((x & 0x00FF00FF00FF00FFLL) << 8) | ((x & 0xFF00FF00FF00FF00LL) >> 8); +if (shamt & 16) x = ((x & 0x0000FFFF0000FFFFLL) << 16) | ((x & 0xFFFF0000FFFF0000LL) >> 16); +WRITE_RD(sext32(x)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/hfence_gvma.h b/vendor/riscv/riscv-isa-sim/riscv/insns/hfence_gvma.h new file mode 100644 index 0000000000..b3ddf1e81c --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/hfence_gvma.h @@ -0,0 +1,4 @@ +require_extension('H'); +require_novirt(); +require_privilege(get_field(STATE.mstatus->read(), MSTATUS_TVM) ? PRV_M : PRV_S); +MMU.flush_tlb(); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/hfence_vvma.h b/vendor/riscv/riscv-isa-sim/riscv/insns/hfence_vvma.h new file mode 100644 index 0000000000..ecd42c198c --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/hfence_vvma.h @@ -0,0 +1,4 @@ +require_extension('H'); +require_novirt(); +require_privilege(PRV_S); +MMU.flush_tlb(); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/hinval_gvma.h b/vendor/riscv/riscv-isa-sim/riscv/insns/hinval_gvma.h new file mode 100644 index 0000000000..6be5cd9418 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/hinval_gvma.h @@ -0,0 +1,2 @@ +require_extension(EXT_SVINVAL); +#include "hfence_gvma.h" diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/hinval_vvma.h b/vendor/riscv/riscv-isa-sim/riscv/insns/hinval_vvma.h new file mode 100644 index 0000000000..c50707c240 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/hinval_vvma.h @@ -0,0 +1,2 @@ +require_extension(EXT_SVINVAL); +#include "hfence_vvma.h" diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/hlv_b.h b/vendor/riscv/riscv-isa-sim/riscv/insns/hlv_b.h new file mode 100644 index 0000000000..308d038f45 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/hlv_b.h @@ -0,0 +1,4 @@ +require_extension('H'); +require_novirt(); +require_privilege(get_field(STATE.hstatus->read(), HSTATUS_HU) ? PRV_U : PRV_S); +WRITE_RD(MMU.guest_load<int8_t>(RS1)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/hlv_bu.h b/vendor/riscv/riscv-isa-sim/riscv/insns/hlv_bu.h new file mode 100644 index 0000000000..1fe4d6a937 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/hlv_bu.h @@ -0,0 +1,4 @@ +require_extension('H'); +require_novirt(); +require_privilege(get_field(STATE.hstatus->read(), HSTATUS_HU) ? PRV_U : PRV_S); +WRITE_RD(MMU.guest_load<uint8_t>(RS1)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/hlv_d.h b/vendor/riscv/riscv-isa-sim/riscv/insns/hlv_d.h new file mode 100644 index 0000000000..8e92ce3e02 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/hlv_d.h @@ -0,0 +1,5 @@ +require_extension('H'); +require_rv64; +require_novirt(); +require_privilege(get_field(STATE.hstatus->read(), HSTATUS_HU) ? PRV_U : PRV_S); +WRITE_RD(MMU.guest_load<int64_t>(RS1)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/hlv_h.h b/vendor/riscv/riscv-isa-sim/riscv/insns/hlv_h.h new file mode 100644 index 0000000000..f2e14c4b00 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/hlv_h.h @@ -0,0 +1,4 @@ +require_extension('H'); +require_novirt(); +require_privilege(get_field(STATE.hstatus->read(), HSTATUS_HU) ? PRV_U : PRV_S); +WRITE_RD(MMU.guest_load<int16_t>(RS1)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/hlv_hu.h b/vendor/riscv/riscv-isa-sim/riscv/insns/hlv_hu.h new file mode 100644 index 0000000000..f7f12ef0ef --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/hlv_hu.h @@ -0,0 +1,4 @@ +require_extension('H'); +require_novirt(); +require_privilege(get_field(STATE.hstatus->read(), HSTATUS_HU) ? PRV_U : PRV_S); +WRITE_RD(MMU.guest_load<uint16_t>(RS1)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/hlv_w.h b/vendor/riscv/riscv-isa-sim/riscv/insns/hlv_w.h new file mode 100644 index 0000000000..72f69eaaf2 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/hlv_w.h @@ -0,0 +1,4 @@ +require_extension('H'); +require_novirt(); +require_privilege(get_field(STATE.hstatus->read(), HSTATUS_HU) ? PRV_U : PRV_S); +WRITE_RD(MMU.guest_load<int32_t>(RS1)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/hlv_wu.h b/vendor/riscv/riscv-isa-sim/riscv/insns/hlv_wu.h new file mode 100644 index 0000000000..854269fe20 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/hlv_wu.h @@ -0,0 +1,5 @@ +require_extension('H'); +require_rv64; +require_novirt(); +require_privilege(get_field(STATE.hstatus->read(), HSTATUS_HU) ? PRV_U : PRV_S); +WRITE_RD(MMU.guest_load<uint32_t>(RS1)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/hlvx_hu.h b/vendor/riscv/riscv-isa-sim/riscv/insns/hlvx_hu.h new file mode 100644 index 0000000000..95dcb2042c --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/hlvx_hu.h @@ -0,0 +1,4 @@ +require_extension('H'); +require_novirt(); +require_privilege(get_field(STATE.hstatus->read(), HSTATUS_HU) ? PRV_U : PRV_S); +WRITE_RD(MMU.guest_load_x<uint16_t>(RS1)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/hlvx_wu.h b/vendor/riscv/riscv-isa-sim/riscv/insns/hlvx_wu.h new file mode 100644 index 0000000000..c751ba588d --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/hlvx_wu.h @@ -0,0 +1,4 @@ +require_extension('H'); +require_novirt(); +require_privilege(get_field(STATE.hstatus->read(), HSTATUS_HU) ? PRV_U : PRV_S); +WRITE_RD(sext_xlen(MMU.guest_load_x<uint32_t>(RS1))); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/hsv_b.h b/vendor/riscv/riscv-isa-sim/riscv/insns/hsv_b.h new file mode 100644 index 0000000000..d56483fb27 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/hsv_b.h @@ -0,0 +1,4 @@ +require_extension('H'); +require_novirt(); +require_privilege(get_field(STATE.hstatus->read(), HSTATUS_HU) ? PRV_U : PRV_S); +MMU.guest_store<uint8_t>(RS1, RS2); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/hsv_d.h b/vendor/riscv/riscv-isa-sim/riscv/insns/hsv_d.h new file mode 100644 index 0000000000..ed7f5bb921 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/hsv_d.h @@ -0,0 +1,5 @@ +require_extension('H'); +require_rv64; +require_novirt(); +require_privilege(get_field(STATE.hstatus->read(), HSTATUS_HU) ? PRV_U : PRV_S); +MMU.guest_store<uint64_t>(RS1, RS2); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/hsv_h.h b/vendor/riscv/riscv-isa-sim/riscv/insns/hsv_h.h new file mode 100644 index 0000000000..596f1684c6 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/hsv_h.h @@ -0,0 +1,4 @@ +require_extension('H'); +require_novirt(); +require_privilege(get_field(STATE.hstatus->read(), HSTATUS_HU) ? PRV_U : PRV_S); +MMU.guest_store<uint16_t>(RS1, RS2); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/hsv_w.h b/vendor/riscv/riscv-isa-sim/riscv/insns/hsv_w.h new file mode 100644 index 0000000000..f011e2dfac --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/hsv_w.h @@ -0,0 +1,4 @@ +require_extension('H'); +require_novirt(); +require_privilege(get_field(STATE.hstatus->read(), HSTATUS_HU) ? PRV_U : PRV_S); +MMU.guest_store<uint32_t>(RS1, RS2); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/insb.h b/vendor/riscv/riscv-isa-sim/riscv/insns/insb.h new file mode 100644 index 0000000000..020e90513e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/insb.h @@ -0,0 +1,4 @@ +require_extension(EXT_ZPN); +reg_t bpos = insn.p_imm3(); +require(bpos < (unsigned long)xlen/8); // imm[2] == 1 is illegal on rv32 +WRITE_RD(sext_xlen(set_field(RD, make_mask64(bpos * 8, 8), P_B(RS1, 0)))); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/jal.h b/vendor/riscv/riscv-isa-sim/riscv/insns/jal.h new file mode 100644 index 0000000000..cd599641e2 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/jal.h @@ -0,0 +1,3 @@ +reg_t tmp = npc; +set_pc(JUMP_TARGET); +WRITE_RD(tmp); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/jalr.h b/vendor/riscv/riscv-isa-sim/riscv/insns/jalr.h new file mode 100644 index 0000000000..386e8db1f5 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/jalr.h @@ -0,0 +1,3 @@ +reg_t tmp = npc; +set_pc((RS1 + insn.i_imm()) & ~reg_t(1)); +WRITE_RD(tmp); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kabs16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kabs16.h new file mode 100644 index 0000000000..8d1d9b83fb --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kabs16.h @@ -0,0 +1,10 @@ +require_vector_vs; +P_ONE_LOOP(16, { + pd = ps1; + if (ps1 == INT16_MIN) { + pd = INT16_MAX; + P_SET_OV(1); + } else if (ps1 < 0) { + pd = - ps1; + } +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kabs32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kabs32.h new file mode 100644 index 0000000000..0536aaca61 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kabs32.h @@ -0,0 +1,11 @@ +require_vector_vs; +require_rv64; +P_ONE_LOOP(32, { + pd = ps1; + if (ps1 == INT32_MIN) { + pd = INT32_MAX; + P_SET_OV(1); + } else if (ps1 < 0) { + pd = - ps1; + } +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kabs8.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kabs8.h new file mode 100644 index 0000000000..2e6e1f1629 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kabs8.h @@ -0,0 +1,10 @@ +require_vector_vs; +P_ONE_LOOP(8, { + pd = ps1; + if (ps1 == INT8_MIN) { + pd = INT8_MAX; + P_SET_OV(1); + } else if (ps1 < 0) { + pd = - ps1; + } +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kabsw.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kabsw.h new file mode 100644 index 0000000000..5e83b759d3 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kabsw.h @@ -0,0 +1,10 @@ +require_vector_vs; +require_extension(EXT_ZPN); +int32_t rs1 = P_W(RS1, 0); + +if (rs1 == INT32_MIN) { + rs1 = INT32_MAX; + P_SET_OV(1); +} + +WRITE_RD(sext_xlen(rs1 >= 0 ? rs1 : -rs1)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kadd16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kadd16.h new file mode 100644 index 0000000000..b6defe1fab --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kadd16.h @@ -0,0 +1,6 @@ +require_vector_vs; +P_LOOP(16, { + bool sat = false; + pd = (sat_add<int16_t, uint16_t>(ps1, ps2, sat)); + P_SET_OV(sat); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kadd32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kadd32.h new file mode 100644 index 0000000000..1728847aea --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kadd32.h @@ -0,0 +1,7 @@ +require_vector_vs; +require_rv64; +P_LOOP(32, { + bool sat = false; + pd = (sat_add<int32_t, uint32_t>(ps1, ps2, sat)); + P_SET_OV(sat); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kadd64.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kadd64.h new file mode 100644 index 0000000000..c58fff09de --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kadd64.h @@ -0,0 +1,6 @@ +require_vector_vs; +P_64_PROFILE({ + bool sat = false; + rd = (sat_add<int64_t, uint64_t>(rs1, rs2, sat)); + P_SET_OV(sat); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kadd8.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kadd8.h new file mode 100644 index 0000000000..98864c705d --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kadd8.h @@ -0,0 +1,6 @@ +require_vector_vs; +P_LOOP(8, { + bool sat = false; + pd = (sat_add<int8_t, uint8_t>(ps1, ps2, sat)); + P_SET_OV(sat); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kaddh.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kaddh.h new file mode 100644 index 0000000000..43aedb2d2d --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kaddh.h @@ -0,0 +1,5 @@ +require_vector_vs; +require_extension(EXT_ZPN); +sreg_t res = (sreg_t)P_SH(RS1, 0) + (sreg_t)P_SH(RS2, 0); +P_SAT(res, 16); +WRITE_RD(sext_xlen((int16_t)res)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kaddw.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kaddw.h new file mode 100644 index 0000000000..3298d57e86 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kaddw.h @@ -0,0 +1,5 @@ +require_vector_vs; +require_extension(EXT_ZPN); +sreg_t res = (sreg_t)P_SW(RS1, 0) + (sreg_t)P_SW(RS2, 0); +P_SAT(res, 32); +WRITE_RD(sext32(res)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kcras16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kcras16.h new file mode 100644 index 0000000000..d74642535c --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kcras16.h @@ -0,0 +1,10 @@ +require_vector_vs; +P_CROSS_ULOOP(16, { + bool sat = false; + pd = (sat_add<int16_t, uint16_t>(ps1, ps2, sat)); + P_SET_OV(sat); +}, { + bool sat = false; + pd = (sat_sub<int16_t, uint16_t>(ps1, ps2, sat)); + P_SET_OV(sat); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kcras32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kcras32.h new file mode 100644 index 0000000000..ead31f8aec --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kcras32.h @@ -0,0 +1,11 @@ +require_vector_vs; +require_rv64; +P_CROSS_ULOOP(32, { + bool sat = false; + pd = (sat_add<int32_t, uint32_t>(ps1, ps2, sat)); + P_SET_OV(sat); +}, { + bool sat = false; + pd = (sat_sub<int32_t, uint32_t>(ps1, ps2, sat)); + P_SET_OV(sat); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kcrsa16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kcrsa16.h new file mode 100644 index 0000000000..2a7ca4d229 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kcrsa16.h @@ -0,0 +1,10 @@ +require_vector_vs; +P_CROSS_ULOOP(16, { + bool sat = false; + pd = (sat_sub<int16_t, uint16_t>(ps1, ps2, sat)); + P_SET_OV(sat); +}, { + bool sat = false; + pd = (sat_add<int16_t, uint16_t>(ps1, ps2, sat)); + P_SET_OV(sat); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kcrsa32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kcrsa32.h new file mode 100644 index 0000000000..b688fd3c1a --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kcrsa32.h @@ -0,0 +1,11 @@ +require_vector_vs; +require_rv64; +P_CROSS_ULOOP(32, { + bool sat = false; + pd = (sat_sub<int32_t, uint32_t>(ps1, ps2, sat)); + P_SET_OV(sat); +}, { + bool sat = false; + pd = (sat_add<int32_t, uint32_t>(ps1, ps2, sat)); + P_SET_OV(sat); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kdmabb.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kdmabb.h new file mode 100644 index 0000000000..7ca056399e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kdmabb.h @@ -0,0 +1,17 @@ +require_vector_vs; +require_extension(EXT_ZPN); +sreg_t res; +sreg_t aop = P_SH(RS1, 0); +sreg_t bop = P_SH(RS2, 0); + +if ((INT16_MIN != aop) | (INT16_MIN != bop)) { + res = aop * bop; + res <<= 1; +} else { + res = INT32_MAX; + P_SET_OV(1); +} + +res += sext32(RD); +P_SAT(res, 32); +WRITE_RD(sext32(res)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kdmabb16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kdmabb16.h new file mode 100644 index 0000000000..2ccd40b1ca --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kdmabb16.h @@ -0,0 +1,18 @@ +require_vector_vs; +require_rv64; +P_LOOP(32, { + int32_t aop = P_SH(ps1, 0); + int32_t bop = P_SH(ps2, 0); + int32_t mres; + bool sat; + + if ((INT16_MIN != aop) | (INT16_MIN != bop)) { + mres = aop * bop; + mres <<= 1; + } else { + mres = INT32_MAX; + P_SET_OV(1); + } + pd = (sat_add<int32_t, uint32_t>(pd, mres, sat)); + P_SET_OV(sat); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kdmabt.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kdmabt.h new file mode 100644 index 0000000000..d50a6dfa0f --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kdmabt.h @@ -0,0 +1,17 @@ +require_vector_vs; +require_extension(EXT_ZPN); +sreg_t res; +sreg_t aop = P_SH(RS1, 0); +sreg_t bop = P_SH(RS2, 1); + +if ((INT16_MIN != aop) | (INT16_MIN != bop)) { + res = aop * bop; + res <<= 1; +} else { + res = INT32_MAX; + P_SET_OV(1); +} + +res += sext32(RD); +P_SAT(res, 32); +WRITE_RD(sext32(res)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kdmabt16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kdmabt16.h new file mode 100644 index 0000000000..49538b38dc --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kdmabt16.h @@ -0,0 +1,18 @@ +require_vector_vs; +require_rv64; +P_LOOP(32, { + int32_t aop = P_SH(ps1, 0); + int32_t bop = P_SH(ps2, 1); + int32_t mres; + bool sat; + + if ((INT16_MIN != aop) | (INT16_MIN != bop)) { + mres = aop * bop; + mres <<= 1; + } else { + mres = INT32_MAX; + P_SET_OV(1); + } + pd = (sat_add<int32_t, uint32_t>(pd, mres, sat)); + P_SET_OV(sat); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kdmatt.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kdmatt.h new file mode 100644 index 0000000000..e917d41446 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kdmatt.h @@ -0,0 +1,17 @@ +require_vector_vs; +require_extension(EXT_ZPN); +sreg_t res; +sreg_t aop = P_SH(RS1, 1); +sreg_t bop = P_SH(RS2, 1); + +if ((INT16_MIN != aop) | (INT16_MIN != bop)) { + res = aop * bop; + res <<= 1; +} else { + res = INT32_MAX; + P_SET_OV(1); +} + +res += sext32(RD); +P_SAT(res, 32); +WRITE_RD(sext32(res)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kdmatt16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kdmatt16.h new file mode 100644 index 0000000000..ebce13f477 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kdmatt16.h @@ -0,0 +1,18 @@ +require_vector_vs; +require_rv64; +P_LOOP(32, { + int32_t aop = P_SH(ps1, 1); + int32_t bop = P_SH(ps2, 1); + int32_t mres; + bool sat; + + if ((INT16_MIN != aop) | (INT16_MIN != bop)) { + mres = aop * bop; + mres <<= 1; + } else { + mres = INT32_MAX; + P_SET_OV(1); + } + pd = (sat_add<int32_t, uint32_t>(pd, mres, sat)); + P_SET_OV(sat); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kdmbb.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kdmbb.h new file mode 100644 index 0000000000..2f7a3f95bf --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kdmbb.h @@ -0,0 +1,13 @@ +require_vector_vs; +require_extension(EXT_ZPN); +sreg_t res; +sreg_t aop = P_SH(RS1, 0); +sreg_t bop = P_SH(RS2, 0); +if ((INT16_MIN != aop) | (INT16_MIN != bop)) { + res = aop * bop; + res <<= 1; +} else { + res = INT32_MAX; + P_SET_OV(1); +} +WRITE_RD(sext32(res)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kdmbb16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kdmbb16.h new file mode 100644 index 0000000000..a84877d2de --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kdmbb16.h @@ -0,0 +1,13 @@ +require_vector_vs; +require_rv64; +P_LOOP(32, { + int32_t aop = P_SH(ps1, 0); + int32_t bop = P_SH(ps2, 0); + if ((INT16_MIN != aop) | (INT16_MIN != bop)) { + pd = aop * bop; + pd <<= 1; + } else { + pd = INT32_MAX; + P_SET_OV(1); + } +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kdmbt.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kdmbt.h new file mode 100644 index 0000000000..7f093e3ae8 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kdmbt.h @@ -0,0 +1,13 @@ +require_vector_vs; +require_extension(EXT_ZPN); +sreg_t res; +sreg_t aop = P_SH(RS1, 0); +sreg_t bop = P_SH(RS2, 1); +if ((INT16_MIN != aop) | (INT16_MIN != bop)) { + res = aop * bop; + res <<= 1; +} else { + res = INT32_MAX; + P_SET_OV(1); +} +WRITE_RD(sext32(res)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kdmbt16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kdmbt16.h new file mode 100644 index 0000000000..85e9d0e6c4 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kdmbt16.h @@ -0,0 +1,13 @@ +require_vector_vs; +require_rv64; +P_LOOP(32, { + int32_t aop = P_SH(ps1, 0); + int32_t bop = P_SH(ps2, 1); + if ((INT16_MIN != aop) | (INT16_MIN != bop)) { + pd = aop * bop; + pd <<= 1; + } else { + pd = INT32_MAX; + P_SET_OV(1); + } +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kdmtt.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kdmtt.h new file mode 100644 index 0000000000..05a4c8c20e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kdmtt.h @@ -0,0 +1,13 @@ +require_vector_vs; +require_extension(EXT_ZPN); +sreg_t res; +sreg_t aop = P_SH(RS1, 1); +sreg_t bop = P_SH(RS2, 1); +if ((INT16_MIN != aop) | (INT16_MIN != bop)) { + res = aop * bop; + res <<= 1; +} else { + res = INT32_MAX; + P_SET_OV(1); +} +WRITE_RD(sext32(res)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kdmtt16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kdmtt16.h new file mode 100644 index 0000000000..2190710a90 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kdmtt16.h @@ -0,0 +1,13 @@ +require_vector_vs; +require_rv64; +P_LOOP(32, { + int32_t aop = P_SH(ps1, 1); + int32_t bop = P_SH(ps2, 1); + if ((INT16_MIN != aop) | (INT16_MIN != bop)) { + pd = aop * bop; + pd <<= 1; + } else { + pd = INT32_MAX; + P_SET_OV(1); + } +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/khm16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/khm16.h new file mode 100644 index 0000000000..9c2e28c3dc --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/khm16.h @@ -0,0 +1,9 @@ +require_vector_vs; +P_LOOP(16, { + if ((ps1 != INT16_MIN) | (ps2 != INT16_MIN)) { + pd = (ps1 * ps2) >> 15; + } else { + pd = INT16_MAX; + P_SET_OV(1); + } +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/khm8.h b/vendor/riscv/riscv-isa-sim/riscv/insns/khm8.h new file mode 100644 index 0000000000..ac21d68c69 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/khm8.h @@ -0,0 +1,9 @@ +require_vector_vs; +P_LOOP(8, { + if ((ps1 != INT8_MIN) | (ps2 != INT8_MIN)) { + pd = (ps1 * ps2) >> 7; + } else { + pd = INT8_MAX; + P_SET_OV(1); + } +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/khmbb.h b/vendor/riscv/riscv-isa-sim/riscv/insns/khmbb.h new file mode 100644 index 0000000000..e08eddca2a --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/khmbb.h @@ -0,0 +1,13 @@ +require_vector_vs; +require_extension(EXT_ZPN); +sreg_t res; +sreg_t aop = P_SH(RS1, 0); +sreg_t bop = P_SH(RS2, 0); +if ((INT16_MIN != aop) | (INT16_MIN != bop)) { + res = aop * bop; + res >>= 15; +} else { + res = INT16_MAX; + P_SET_OV(1); +} +WRITE_RD(sext_xlen((int16_t)res)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/khmbb16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/khmbb16.h new file mode 100644 index 0000000000..efbd7eb6e0 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/khmbb16.h @@ -0,0 +1,14 @@ +require_vector_vs; +require_rv64; +P_LOOP(32, { + int32_t aop = P_SH(ps1, 0); + int32_t bop = P_SH(ps2, 0); + if ((INT16_MIN != aop) | (INT16_MIN != bop)) { + pd = aop * bop; + pd >>= 15; + } else { + pd = INT16_MAX; + P_SET_OV(1); + } + pd = (int16_t)pd; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/khmbt.h b/vendor/riscv/riscv-isa-sim/riscv/insns/khmbt.h new file mode 100644 index 0000000000..0c19cd1696 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/khmbt.h @@ -0,0 +1,13 @@ +require_vector_vs; +require_extension(EXT_ZPN); +sreg_t res; +sreg_t aop = P_SH(RS1, 0); +sreg_t bop = P_SH(RS2, 1); +if ((INT16_MIN != aop) | (INT16_MIN != bop)) { + res = aop * bop; + res >>= 15; +} else { + res = INT16_MAX; + P_SET_OV(1); +} +WRITE_RD(sext_xlen((int16_t)res)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/khmbt16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/khmbt16.h new file mode 100644 index 0000000000..4bb1f48c8c --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/khmbt16.h @@ -0,0 +1,14 @@ +require_vector_vs; +require_rv64; +P_LOOP(32, { + int32_t aop = P_SH(ps1, 0); + int32_t bop = P_SH(ps2, 1); + if ((INT16_MIN != aop) | (INT16_MIN != bop)) { + pd = aop * bop; + pd >>= 15; + } else { + pd = INT16_MAX; + P_SET_OV(1); + } + pd = (int16_t)pd; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/khmtt.h b/vendor/riscv/riscv-isa-sim/riscv/insns/khmtt.h new file mode 100644 index 0000000000..dcd450304f --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/khmtt.h @@ -0,0 +1,13 @@ +require_vector_vs; +require_extension(EXT_ZPN); +sreg_t res; +sreg_t aop = P_SH(RS1, 1); +sreg_t bop = P_SH(RS2, 1); +if ((INT16_MIN != aop) | (INT16_MIN != bop)) { + res = aop * bop; + res >>= 15; +} else { + res = INT16_MAX; + P_SET_OV(1); +} +WRITE_RD(sext_xlen((int16_t)res)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/khmtt16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/khmtt16.h new file mode 100644 index 0000000000..d3c0b4cf9c --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/khmtt16.h @@ -0,0 +1,14 @@ +require_vector_vs; +require_rv64; +P_LOOP(32, { + int32_t aop = P_SH(ps1, 1); + int32_t bop = P_SH(ps2, 1); + if ((INT16_MIN != aop) | (INT16_MIN != bop)) { + pd = aop * bop; + pd >>= 15; + } else { + pd = INT16_MAX; + P_SET_OV(1); + } + pd = (int16_t)pd; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/khmx16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/khmx16.h new file mode 100644 index 0000000000..bf93462755 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/khmx16.h @@ -0,0 +1,9 @@ +require_vector_vs; +P_CROSS_LOOP(16, { + if ((ps1 != INT16_MIN) | (ps2 != INT16_MIN)) { + pd = (ps1 * ps2) >> 15; + } else { + pd = INT16_MAX; + P_SET_OV(1); + } +},) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/khmx8.h b/vendor/riscv/riscv-isa-sim/riscv/insns/khmx8.h new file mode 100644 index 0000000000..0d6a5d5ad8 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/khmx8.h @@ -0,0 +1,9 @@ +require_vector_vs; +P_CROSS_LOOP(8, { + if ((ps1 != INT8_MIN) | (ps2 != INT8_MIN)) { + pd = (ps1 * ps2) >> 7; + } else { + pd = INT8_MAX; + P_SET_OV(1); + } +},) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kmabb.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kmabb.h new file mode 100644 index 0000000000..f2d7715eb4 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kmabb.h @@ -0,0 +1,7 @@ +require_vector_vs; +P_LOOP(32, { + int32_t mres = P_SH(ps1, 0) * P_SH(ps2, 0); + bool sat = false; + pd = (sat_add<int32_t, uint32_t>(pd, mres, sat)); + P_SET_OV(sat); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kmabb32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kmabb32.h new file mode 100644 index 0000000000..752bf8b557 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kmabb32.h @@ -0,0 +1,8 @@ +require_vector_vs; +require_rv64; +require_extension(EXT_ZPN); + +bool sat = false; +sreg_t mres = (sreg_t)P_SW(RS1, 0) * P_SW(RS2, 0); +WRITE_RD((sat_add<int64_t, uint64_t>(RD, mres, sat))); +P_SET_OV(sat); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kmabt.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kmabt.h new file mode 100644 index 0000000000..4ead23bcc8 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kmabt.h @@ -0,0 +1,7 @@ +require_vector_vs; +P_LOOP(32, { + int32_t mres = P_SH(ps1, 0) * P_SH(ps2, 1); + bool sat = false; + pd = (sat_add<int32_t, uint32_t>(pd, mres, sat)); + P_SET_OV(sat); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kmabt32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kmabt32.h new file mode 100644 index 0000000000..ee7511bdf6 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kmabt32.h @@ -0,0 +1,8 @@ +require_vector_vs; +require_rv64; +require_extension(EXT_ZPN); + +bool sat = false; +sreg_t mres = (sreg_t)P_SW(RS1, 0) * P_SW(RS2, 1); +WRITE_RD((sat_add<int64_t, uint64_t>(RD, mres, sat))); +P_SET_OV(sat); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kmada.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kmada.h new file mode 100644 index 0000000000..3c082c7ba5 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kmada.h @@ -0,0 +1,4 @@ +require_vector_vs; +P_REDUCTION_LOOP(32, 16, true, true, { + pd_res += ps1 * ps2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kmadrs.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kmadrs.h new file mode 100644 index 0000000000..a4503517f4 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kmadrs.h @@ -0,0 +1,7 @@ +require_vector_vs; +P_REDUCTION_LOOP(32, 16, true, true, { + if (j & 1) + pd_res -= ps1 * ps2; + else + pd_res += ps1 * ps2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kmadrs32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kmadrs32.h new file mode 100644 index 0000000000..0f71e90ffd --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kmadrs32.h @@ -0,0 +1,10 @@ +require_vector_vs; +require_rv64; +require_extension(EXT_ZPN); + +bool sat; +sreg_t mres0 = (sreg_t)P_SW(RS1, 0) * P_SW(RS2, 0); +sreg_t mres1 = (sreg_t)P_SW(RS1, 1) * P_SW(RS2, 1); + +WRITE_RD((sat_add<sreg_t, reg_t>(RD, mres0, -mres1, sat))); +P_SET_OV(sat); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kmads.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kmads.h new file mode 100644 index 0000000000..89aabe0583 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kmads.h @@ -0,0 +1,7 @@ +require_vector_vs; +P_REDUCTION_LOOP(32, 16, true, true, { + if (j & 1) + pd_res += ps1 * ps2; + else + pd_res -= ps1 * ps2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kmads32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kmads32.h new file mode 100644 index 0000000000..0a3b590520 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kmads32.h @@ -0,0 +1,10 @@ +require_vector_vs; +require_rv64; +require_extension(EXT_ZPN); + +bool sat; +sreg_t mres0 = (sreg_t)P_SW(RS1, 0) * P_SW(RS2, 0); +sreg_t mres1 = (sreg_t)P_SW(RS1, 1) * P_SW(RS2, 1); + +WRITE_RD((sat_add<sreg_t, reg_t>(RD, -mres0, mres1, sat))); +P_SET_OV(sat); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kmar64.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kmar64.h new file mode 100644 index 0000000000..a4d332b0d8 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kmar64.h @@ -0,0 +1,15 @@ +require_vector_vs; +P_64_PROFILE_BASE() +P_64_PROFILE_PARAM(true, false) + +bool sat = false; +sreg_t mres0 = (sreg_t)P_SW(rs1, 0) * P_SW(rs2, 0); +sreg_t mres1 = (sreg_t)P_SW(rs1, 1) * P_SW(rs2, 1); + +if (xlen == 32) { + rd = (sat_add<int64_t, uint64_t>(rd, mres0, sat)); +} else { + rd = (sat_add<int64_t, uint64_t>(rd, mres0, mres1, sat)); +} +P_SET_OV(sat); +P_64_PROFILE_END() diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kmatt.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kmatt.h new file mode 100644 index 0000000000..4be2f3d935 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kmatt.h @@ -0,0 +1,7 @@ +require_vector_vs; +P_LOOP(32, { + int32_t mres = P_SH(ps1, 1) * P_SH(ps2, 1); + bool sat = false; + pd = (sat_add<int32_t, uint32_t>(pd, mres, sat)); + P_SET_OV(sat); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kmatt32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kmatt32.h new file mode 100644 index 0000000000..4fe9ed2b8b --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kmatt32.h @@ -0,0 +1,8 @@ +require_vector_vs; +require_rv64; +require_extension(EXT_ZPN); + +bool sat = false; +sreg_t mres = (sreg_t)P_SW(RS1, 1) * P_SW(RS2, 1); +WRITE_RD((sat_add<int64_t, uint64_t>(RD, mres, sat))); +P_SET_OV(sat); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kmaxda.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kmaxda.h new file mode 100644 index 0000000000..393f0472e4 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kmaxda.h @@ -0,0 +1,4 @@ +require_vector_vs; +P_REDUCTION_CROSS_LOOP(32, 16, true, true, { + pd_res += ps1 * ps2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kmaxda32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kmaxda32.h new file mode 100644 index 0000000000..b9346b96c4 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kmaxda32.h @@ -0,0 +1,10 @@ +require_vector_vs; +require_rv64; +require_extension(EXT_ZPN); + +bool sat; +sreg_t mres0 = (sreg_t)P_SW(RS1, 0) * P_SW(RS2, 1); +sreg_t mres1 = (sreg_t)P_SW(RS1, 1) * P_SW(RS2, 0); + +WRITE_RD((sat_add<sreg_t, reg_t>(RD, mres0, mres1, sat))); +P_SET_OV(sat); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kmaxds.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kmaxds.h new file mode 100644 index 0000000000..c2f0e59178 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kmaxds.h @@ -0,0 +1,7 @@ +require_vector_vs; +P_REDUCTION_CROSS_LOOP(32, 16, true, true, { + if (j & 1) + pd_res += ps1 * ps2; + else + pd_res -= ps1 * ps2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kmaxds32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kmaxds32.h new file mode 100644 index 0000000000..6a7d64e419 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kmaxds32.h @@ -0,0 +1,10 @@ +require_vector_vs; +require_rv64; +require_extension(EXT_ZPN); + +bool sat; +sreg_t mres0 = (sreg_t)P_SW(RS1, 0) * P_SW(RS2, 1); +sreg_t mres1 = (sreg_t)P_SW(RS1, 1) * P_SW(RS2, 0); + +WRITE_RD((sat_add<sreg_t, reg_t>(RD, -mres0, mres1, sat))); +P_SET_OV(sat); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kmda.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kmda.h new file mode 100644 index 0000000000..68b6c9a723 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kmda.h @@ -0,0 +1,4 @@ +require_vector_vs; +P_REDUCTION_LOOP(32, 16, false, true, { + pd_res += ps1 * ps2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kmda32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kmda32.h new file mode 100644 index 0000000000..646021f122 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kmda32.h @@ -0,0 +1,10 @@ +require_vector_vs; +require_rv64; +require_extension(EXT_ZPN); + +bool sat; +sreg_t mres0 = (sreg_t)P_SW(RS1, 0) * P_SW(RS2, 0); +sreg_t mres1 = (sreg_t)P_SW(RS1, 1) * P_SW(RS2, 1); + +WRITE_RD((sat_add<sreg_t, reg_t>(mres0, mres1, sat))); +P_SET_OV(sat); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kmmac.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kmmac.h new file mode 100644 index 0000000000..946f0fe554 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kmmac.h @@ -0,0 +1,7 @@ +require_vector_vs; +P_LOOP(32, { + int64_t mres = (int64_t) ps1 * (int64_t) ps2; + bool sat = false; + pd = (sat_add<int32_t, uint32_t>(pd, (mres >> 32), sat)); + P_SET_OV(sat); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kmmac_u.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kmmac_u.h new file mode 100644 index 0000000000..5a06a4db1e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kmmac_u.h @@ -0,0 +1,8 @@ +require_vector_vs; +P_LOOP(32, { + int64_t mres = (int64_t) ps1 * (int64_t) ps2; + int32_t round = (((mres >> 31) + 1) >> 1); + bool sat = false; + pd = (sat_add<int32_t, uint32_t>(pd, round, sat)); + P_SET_OV(sat); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kmmawb.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kmmawb.h new file mode 100644 index 0000000000..0e3a6944d5 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kmmawb.h @@ -0,0 +1,7 @@ +require_vector_vs; +P_LOOP(32, { + int64_t mres = (int64_t)ps1 * P_SH(ps2, 0); + bool sat = false; + pd = (sat_add<int32_t, uint32_t>(pd, (mres >> 16), sat)); + P_SET_OV(sat); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kmmawb2.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kmmawb2.h new file mode 100644 index 0000000000..274f9dd83a --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kmmawb2.h @@ -0,0 +1,15 @@ +require_vector_vs; +P_LOOP(32, { + int64_t addop = 0; + int64_t mres = 0; + bool sat = false; + if ((INT32_MIN != ps1) | (INT16_MIN != P_SH(ps2, 0))) { + mres = ((int64_t) ps1 * P_SH(ps2, 0)) << 1; + addop = mres >> 16; + } else { + addop = INT32_MAX; + P_SET_OV(1); + } + pd = (sat_add<int32_t, uint32_t>(pd, addop, sat)); + P_SET_OV(sat); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kmmawb2_u.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kmmawb2_u.h new file mode 100644 index 0000000000..447a3f455b --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kmmawb2_u.h @@ -0,0 +1,15 @@ +require_vector_vs; +P_LOOP(32, { + int64_t addop = 0; + int64_t mres = 0; + bool sat = false; + if ((INT32_MIN != ps1) | (INT16_MIN != P_SH(ps2, 0))) { + mres = ((int64_t) ps1 * P_SH(ps2, 0)) << 1; + addop = ((mres >> 15) + 1) >> 1; + } else { + addop = INT32_MAX; + P_SET_OV(1); + } + pd = (sat_add<int32_t, uint32_t>(pd, addop, sat)); + P_SET_OV(sat); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kmmawb_u.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kmmawb_u.h new file mode 100644 index 0000000000..766dd71605 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kmmawb_u.h @@ -0,0 +1,8 @@ +require_vector_vs; +P_LOOP(32, { + int64_t mres = (int64_t)ps1 * P_SH(ps2, 0); + int32_t round = (((mres >> 15) + 1) >> 1); + bool sat = false; + pd = (sat_add<int32_t, uint32_t>(pd, round, sat)); + P_SET_OV(sat); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kmmawt.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kmmawt.h new file mode 100644 index 0000000000..514ee48459 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kmmawt.h @@ -0,0 +1,7 @@ +require_vector_vs; +P_LOOP(32, { + int64_t mres = (int64_t)ps1 * P_SH(ps2, 1); + bool sat = false; + pd = (sat_add<int32_t, uint32_t>(pd, (mres >> 16), sat)); + P_SET_OV(sat); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kmmawt2.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kmmawt2.h new file mode 100644 index 0000000000..6eb22ac08a --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kmmawt2.h @@ -0,0 +1,15 @@ +require_vector_vs; +P_LOOP(32, { + int64_t addop = 0; + int64_t mres = 0; + bool sat = false; + if ((INT32_MIN != ps1) | (INT16_MIN != P_SH(ps2, 1))) { + mres = ((int64_t) ps1 * P_SH(ps2, 1)) << 1; + addop = mres >> 16; + } else { + addop = INT32_MAX; + P_SET_OV(1); + } + pd = (sat_add<int32_t, uint32_t>(pd, addop, sat)); + P_SET_OV(sat); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kmmawt2_u.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kmmawt2_u.h new file mode 100644 index 0000000000..b82e0909c6 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kmmawt2_u.h @@ -0,0 +1,15 @@ +require_vector_vs; +P_LOOP(32, { + int64_t addop = 0; + int64_t mres = 0; + bool sat = false; + if ((INT32_MIN != ps1) | (INT16_MIN != P_SH(ps2, 1))) { + mres = ((int64_t) ps1 * P_SH(ps2, 1)) << 1; + addop = ((mres >> 15) + 1) >> 1; + } else { + addop = INT32_MAX; + P_SET_OV(1); + } + pd = (sat_add<int32_t, uint32_t>(pd, addop, sat)); + P_SET_OV(sat); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kmmawt_u.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kmmawt_u.h new file mode 100644 index 0000000000..74d8fd011c --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kmmawt_u.h @@ -0,0 +1,8 @@ +require_vector_vs; +P_LOOP(32, { + int64_t mres = (int64_t)ps1 * P_SH(ps2, 1); + int32_t round = (((mres >> 15) + 1) >> 1); + bool sat = false; + pd = (sat_add<int32_t, uint32_t>(pd, round, sat)); + P_SET_OV(sat); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kmmsb.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kmmsb.h new file mode 100644 index 0000000000..29ad1bfa7a --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kmmsb.h @@ -0,0 +1,7 @@ +require_vector_vs; +P_LOOP(32, { + int64_t mres = (int64_t) ps1 * (int64_t) ps2; + bool sat = false; + pd = (sat_sub<int32_t, uint32_t>(pd, (mres >> 32), sat)); + P_SET_OV(sat); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kmmsb_u.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kmmsb_u.h new file mode 100644 index 0000000000..c7b283eaa8 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kmmsb_u.h @@ -0,0 +1,8 @@ +require_vector_vs; +P_LOOP(32, { + int64_t mres = (int64_t) ps1 * (int64_t) ps2; + int32_t round = (((mres >> 31) + 1) >> 1); + bool sat = false; + pd = (sat_sub<int32_t, uint32_t>(pd, round, sat)); + P_SET_OV(sat); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kmmwb2.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kmmwb2.h new file mode 100644 index 0000000000..d08b0ef5a8 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kmmwb2.h @@ -0,0 +1,10 @@ +require_vector_vs; +P_LOOP(32, { + if ((INT32_MIN != ps1) | (INT16_MIN != P_SH(ps2, 0))) { + int64_t mres = ((int64_t) ps1 * P_SH(ps2, 0)) << 1; + pd = mres >> 16; + } else { + pd = INT32_MAX; + P_SET_OV(1); + } +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kmmwb2_u.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kmmwb2_u.h new file mode 100644 index 0000000000..d308bf3a32 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kmmwb2_u.h @@ -0,0 +1,10 @@ +require_vector_vs; +P_LOOP(32, { + if ((INT32_MIN != ps1) | (INT16_MIN != P_SH(ps2, 0))) { + int64_t mres = ((int64_t) ps1 * P_SH(ps2, 0)) << 1; + pd = ((mres >> 15) + 1) >> 1; + } else { + pd = INT32_MAX; + P_SET_OV(1); + } +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kmmwt2.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kmmwt2.h new file mode 100644 index 0000000000..38ba9b18fd --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kmmwt2.h @@ -0,0 +1,10 @@ +require_vector_vs; +P_LOOP(32, { + if ((INT32_MIN != ps1) | (INT16_MIN != P_SH(ps2, 1))) { + int64_t mres = ((int64_t) ps1 * P_SH(ps2, 1)) << 1; + pd = mres >> 16; + } else { + pd = INT32_MAX; + P_SET_OV(1); + } +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kmmwt2_u.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kmmwt2_u.h new file mode 100644 index 0000000000..e85578630c --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kmmwt2_u.h @@ -0,0 +1,10 @@ +require_vector_vs; +P_LOOP(32, { + if ((INT32_MIN != ps1) | (INT16_MIN != P_SH(ps2, 1))) { + int64_t mres = ((int64_t) ps1 * P_SH(ps2, 1)) << 1; + pd = ((mres >> 15) + 1) >> 1; + } else { + pd = INT32_MAX; + P_SET_OV(1); + } +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kmsda.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kmsda.h new file mode 100644 index 0000000000..94b118a270 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kmsda.h @@ -0,0 +1,4 @@ +require_vector_vs; +P_REDUCTION_LOOP(32, 16, true, true, { + pd_res -= ps1 * ps2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kmsda32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kmsda32.h new file mode 100644 index 0000000000..d54d42c2b1 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kmsda32.h @@ -0,0 +1,10 @@ +require_vector_vs; +require_rv64; +require_extension(EXT_ZPN); + +bool sat; +sreg_t mres0 = (sreg_t)P_SW(RS1, 0) * P_SW(RS2, 0); +sreg_t mres1 = (sreg_t)P_SW(RS1, 1) * P_SW(RS2, 1); + +WRITE_RD((sat_add<sreg_t, reg_t>(RD, -mres0, -mres1, sat))); +P_SET_OV(sat); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kmsr64.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kmsr64.h new file mode 100644 index 0000000000..bfef50331b --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kmsr64.h @@ -0,0 +1,26 @@ +require_vector_vs; +P_64_PROFILE_BASE() +P_64_PROFILE_PARAM(true, false) + +bool sat = false; +sreg_t mres0 = -(sreg_t)P_SW(rs1, 0) * P_SW(rs2, 0); +sreg_t mres1 = -(sreg_t)P_SW(rs1, 1) * P_SW(rs2, 1); +sreg_t res; + +if (xlen == 32) { + rd = (sat_add<int64_t, uint64_t>(rd, mres0, sat)); +} else { + if ((rd ^ mres0) < 0) { + res = rd + mres0; + rd = (sat_add<int64_t, uint64_t>(res, mres1, sat)); + } else if ((rd ^ mres1) < 0) { + res = rd + mres1; + rd = (sat_add<int64_t, uint64_t>(res, mres0, sat)); + } else { + rd = (sat_add<int64_t, uint64_t>(rd, mres0, sat)); + P_SET_OV(sat); + rd = (sat_add<int64_t, uint64_t>(rd, mres1, sat)); + } +} +P_SET_OV(sat); +P_64_PROFILE_END() diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kmsxda.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kmsxda.h new file mode 100644 index 0000000000..2d0faa361c --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kmsxda.h @@ -0,0 +1,4 @@ +require_vector_vs; +P_REDUCTION_CROSS_LOOP(32, 16, true, true, { + pd_res -= ps1 * ps2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kmsxda32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kmsxda32.h new file mode 100644 index 0000000000..3006b54204 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kmsxda32.h @@ -0,0 +1,10 @@ +require_vector_vs; +require_rv64; +require_extension(EXT_ZPN); + +bool sat; +sreg_t mres0 = (sreg_t)P_SW(RS1, 0) * P_SW(RS2, 1); +sreg_t mres1 = (sreg_t)P_SW(RS1, 1) * P_SW(RS2, 0); + +WRITE_RD((sat_add<sreg_t, reg_t>(RD, -mres0, -mres1, sat))); +P_SET_OV(sat); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kmxda.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kmxda.h new file mode 100644 index 0000000000..4addd8a5c7 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kmxda.h @@ -0,0 +1,4 @@ +require_vector_vs; +P_REDUCTION_CROSS_LOOP(32, 16, false, true, { + pd_res += ps1 * ps2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kmxda32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kmxda32.h new file mode 100644 index 0000000000..99a8204eb6 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kmxda32.h @@ -0,0 +1,10 @@ +require_vector_vs; +require_rv64; +require_extension(EXT_ZPN); + +bool sat; +sreg_t mres0 = (sreg_t)P_SW(RS1, 0) * P_SW(RS2, 1); +sreg_t mres1 = (sreg_t)P_SW(RS1, 1) * P_SW(RS2, 0); + +WRITE_RD((sat_add<sreg_t, reg_t>(mres0, mres1, sat))); +P_SET_OV(sat); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/ksll16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/ksll16.h new file mode 100644 index 0000000000..9e03b34756 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/ksll16.h @@ -0,0 +1,6 @@ +require_vector_vs; +P_X_LOOP(16, 4, { + auto res = (sreg_t)ps1 << sa; + P_SAT(res, 16); + pd = res; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/ksll32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/ksll32.h new file mode 100644 index 0000000000..35888986fb --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/ksll32.h @@ -0,0 +1,7 @@ +require_vector_vs; +require_rv64; +P_X_LOOP(32, 5, { + auto res = (sreg_t)ps1 << sa; + P_SAT(res, 32); + pd = res; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/ksll8.h b/vendor/riscv/riscv-isa-sim/riscv/insns/ksll8.h new file mode 100644 index 0000000000..930ea03bce --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/ksll8.h @@ -0,0 +1,6 @@ +require_vector_vs; +P_X_LOOP(8, 3, { + auto res = (sreg_t)ps1 << sa; + P_SAT(res, 8); + pd = res; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kslli16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kslli16.h new file mode 100644 index 0000000000..edc7c671d3 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kslli16.h @@ -0,0 +1,6 @@ +require_vector_vs; +P_I_LOOP(16, 4, { + auto res = (sreg_t)ps1 << imm4u; + P_SAT(res, 16); + pd = res; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kslli32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kslli32.h new file mode 100644 index 0000000000..4fd506b2d2 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kslli32.h @@ -0,0 +1,7 @@ +require_vector_vs; +require_rv64; +P_I_LOOP(32, 5, { + auto res = (sreg_t)ps1 << imm5u; + P_SAT(res, 32); + pd = res; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kslli8.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kslli8.h new file mode 100644 index 0000000000..18d714f93c --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kslli8.h @@ -0,0 +1,6 @@ +require_vector_vs; +P_I_LOOP(8, 3, { + auto res = (sreg_t)ps1 << imm3u; + P_SAT(res, 8); + pd = res; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kslliw.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kslliw.h new file mode 100644 index 0000000000..8902d3a375 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kslliw.h @@ -0,0 +1,8 @@ +require_vector_vs; +require_extension(EXT_ZPN); +sreg_t rs1 = sext32(RS1); +sreg_t sa = insn.p_imm5(); +sreg_t res = rs1 << sa; + +P_SAT(res, 32); +WRITE_RD(sext32(res)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/ksllw.h b/vendor/riscv/riscv-isa-sim/riscv/insns/ksllw.h new file mode 100644 index 0000000000..7e8452f8dd --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/ksllw.h @@ -0,0 +1,8 @@ +require_vector_vs; +require_extension(EXT_ZPN); +sreg_t rs1 = sext32(RS1); +sreg_t sa = get_field(RS2, make_mask64(0, 5)); +sreg_t res = rs1 << sa; + +P_SAT(res, 32); +WRITE_RD(sext32(res)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kslra16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kslra16.h new file mode 100644 index 0000000000..ad1443a260 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kslra16.h @@ -0,0 +1,12 @@ +require_vector_vs; +P_X_LOOP(16, 5, { + if (ssa < 0) { + sa = -ssa; + sa = (sa == 16) ? 15 : sa; + pd = ps1 >> sa; + } else { + auto res = (sreg_t)ps1 << ssa; + P_SAT(res, 16); + pd = res; + } +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kslra16_u.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kslra16_u.h new file mode 100644 index 0000000000..27bb77c4bb --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kslra16_u.h @@ -0,0 +1,15 @@ +require_vector_vs; +P_X_LOOP(16, 5, { + if (ssa < 0) { + sa = -ssa; + sa = (sa == 16) ? 15 : sa; + if (sa != 0) + pd = ((ps1 >> (sa - 1)) + 1) >> 1; + else + pd = ps1; + } else { + auto res = (sreg_t)ps1 << ssa; + P_SAT(res, 16); + pd = res; + } +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kslra32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kslra32.h new file mode 100644 index 0000000000..871d60115e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kslra32.h @@ -0,0 +1,13 @@ +require_vector_vs; +require_rv64; +P_X_LOOP(32, 6, { + if (ssa < 0) { + sa = -ssa; + sa = (sa == 32) ? 31 : sa; + pd = ps1 >> sa; + } else { + auto res = (sreg_t)ps1 << ssa; + P_SAT(res, 32); + pd = res; + } +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kslra32_u.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kslra32_u.h new file mode 100644 index 0000000000..b9c06cfee8 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kslra32_u.h @@ -0,0 +1,16 @@ +require_vector_vs; +require_rv64; +P_X_LOOP(32, 6, { + if (ssa < 0) { + sa = -ssa; + sa = (sa == 32) ? 31 : sa; + if (sa != 0) + pd = ((ps1 >> (sa - 1)) + 1) >> 1; + else + pd = ps1; + } else { + auto res = (sreg_t)ps1 << ssa; + P_SAT(res, 32); + pd = res; + } +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kslra8.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kslra8.h new file mode 100644 index 0000000000..b3f3e6b875 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kslra8.h @@ -0,0 +1,12 @@ +require_vector_vs; +P_X_LOOP(8, 4, { + if (ssa < 0) { + sa = -ssa; + sa = (sa == 8) ? 7 : sa; + pd = ps1 >> sa; + } else { + auto res = (sreg_t)ps1 << ssa; + P_SAT(res, 8); + pd = res; + } +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kslra8_u.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kslra8_u.h new file mode 100644 index 0000000000..340283f648 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kslra8_u.h @@ -0,0 +1,15 @@ +require_vector_vs; +P_X_LOOP(8, 4, { + if (ssa < 0) { + sa = -ssa; + sa = (sa == 8) ? 7 : sa; + if (sa != 0) + pd = ((ps1 >> (sa - 1)) + 1) >> 1; + else + pd = ps1; + } else { + auto res = (sreg_t)ps1 << ssa; + P_SAT(res, 8); + pd = res; + } +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kslraw.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kslraw.h new file mode 100644 index 0000000000..fa4c844332 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kslraw.h @@ -0,0 +1,14 @@ +require_vector_vs; +require_extension(EXT_ZPN); +sreg_t rs1 = sext32(RS1); +sreg_t sa = int64_t(RS2) << (64 - 6) >> (64 - 6); + +if (sa < 0) { + sa = -sa; + sa = (sa == 32) ? 31 : sa; + WRITE_RD(sext32(rs1 >> sa)); +} else { + auto res = rs1 << sa; + P_SAT(res, 32); + WRITE_RD(sext32(res)); +} diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kslraw_u.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kslraw_u.h new file mode 100644 index 0000000000..ebecb61553 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kslraw_u.h @@ -0,0 +1,14 @@ +require_vector_vs; +require_extension(EXT_ZPN); +sreg_t rs1 = sext32(RS1); +sreg_t sa = int64_t(RS2) << (64 - 6) >> (64 - 6); + +if (sa < 0) { + sa = -sa; + sa = (sa == 32) ? 31 : sa; + WRITE_RD(sext32(((rs1 >> (sa - 1)) + 1)) >> 1); +} else { + auto res = rs1 << sa; + P_SAT(res, 32); + WRITE_RD(sext32(res)); +} diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kstas16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kstas16.h new file mode 100644 index 0000000000..ad180131ef --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kstas16.h @@ -0,0 +1,10 @@ +require_vector_vs; +P_STRAIGHT_ULOOP(16, { + bool sat = false; + pd = (sat_add<int16_t, uint16_t>(ps1, ps2, sat)); + P_SET_OV(sat); +}, { + bool sat = false; + pd = (sat_sub<int16_t, uint16_t>(ps1, ps2, sat)); + P_SET_OV(sat); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kstas32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kstas32.h new file mode 100644 index 0000000000..35f23e03d1 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kstas32.h @@ -0,0 +1,11 @@ +require_vector_vs; +require_rv64; +P_STRAIGHT_ULOOP(32, { + bool sat = false; + pd = (sat_add<int32_t, uint32_t>(ps1, ps2, sat)); + P_SET_OV(sat); +}, { + bool sat = false; + pd = (sat_sub<int32_t, uint32_t>(ps1, ps2, sat)); + P_SET_OV(sat); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kstsa16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kstsa16.h new file mode 100644 index 0000000000..47a8918b34 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kstsa16.h @@ -0,0 +1,10 @@ +require_vector_vs; +P_STRAIGHT_ULOOP(16, { + bool sat = false; + pd = (sat_sub<int16_t, uint16_t>(ps1, ps2, sat)); + P_SET_OV(sat); +}, { + bool sat = false; + pd = (sat_add<int16_t, uint16_t>(ps1, ps2, sat)); + P_SET_OV(sat); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kstsa32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kstsa32.h new file mode 100644 index 0000000000..aa9c372f3d --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kstsa32.h @@ -0,0 +1,11 @@ +require_vector_vs; +require_rv64; +P_STRAIGHT_ULOOP(32, { + bool sat = false; + pd = (sat_sub<int32_t, uint32_t>(ps1, ps2, sat)); + P_SET_OV(sat); +}, { + bool sat = false; + pd = (sat_add<int32_t, uint32_t>(ps1, ps2, sat)); + P_SET_OV(sat); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/ksub16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/ksub16.h new file mode 100644 index 0000000000..57562b5d24 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/ksub16.h @@ -0,0 +1,6 @@ +require_vector_vs; +P_LOOP(16, { + bool sat = false; + pd = (sat_sub<int16_t, uint16_t>(ps1, ps2, sat)); + P_SET_OV(sat); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/ksub32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/ksub32.h new file mode 100644 index 0000000000..3ef32e8736 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/ksub32.h @@ -0,0 +1,7 @@ +require_vector_vs; +require_rv64; +P_LOOP(32, { + bool sat = false; + pd = (sat_sub<int32_t, uint32_t>(ps1, ps2, sat)); + P_SET_OV(sat); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/ksub64.h b/vendor/riscv/riscv-isa-sim/riscv/insns/ksub64.h new file mode 100644 index 0000000000..c6f099489a --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/ksub64.h @@ -0,0 +1,6 @@ +require_vector_vs; +P_64_PROFILE({ + bool sat = false; + rd = (sat_sub<int64_t, uint64_t>(rs1, rs2, sat)); + P_SET_OV(sat); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/ksub8.h b/vendor/riscv/riscv-isa-sim/riscv/insns/ksub8.h new file mode 100644 index 0000000000..705f632914 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/ksub8.h @@ -0,0 +1,6 @@ +require_vector_vs; +P_LOOP(8, { + bool sat = false; + pd = (sat_sub<int8_t, uint8_t>(ps1, ps2, sat)); + P_SET_OV(sat); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/ksubh.h b/vendor/riscv/riscv-isa-sim/riscv/insns/ksubh.h new file mode 100644 index 0000000000..2455c16120 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/ksubh.h @@ -0,0 +1,5 @@ +require_vector_vs; +require_extension(EXT_ZPN); +sreg_t res = (sreg_t)P_SH(RS1, 0) - (sreg_t)P_SH(RS2, 0); +P_SAT(res, 16); +WRITE_RD(sext_xlen((int16_t)res)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/ksubw.h b/vendor/riscv/riscv-isa-sim/riscv/insns/ksubw.h new file mode 100644 index 0000000000..3a3d7806a9 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/ksubw.h @@ -0,0 +1,5 @@ +require_vector_vs; +require_extension(EXT_ZPN); +sreg_t res = (sreg_t)P_SW(RS1, 0) - (sreg_t)P_SW(RS2, 0); +P_SAT(res, 32); +WRITE_RD(sext32(res)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kwmmul.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kwmmul.h new file mode 100644 index 0000000000..ca654f2f71 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kwmmul.h @@ -0,0 +1,10 @@ +require_vector_vs; +P_LOOP(32, { + if ((INT32_MIN != ps1) | (INT32_MIN != ps2)) { + int64_t mres = ((int64_t) ps1 * (int64_t) ps2) << 1; + pd = mres >> 32; + } else { + pd = INT32_MAX; + P_SET_OV(1); + } +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/kwmmul_u.h b/vendor/riscv/riscv-isa-sim/riscv/insns/kwmmul_u.h new file mode 100644 index 0000000000..b435561cb0 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/kwmmul_u.h @@ -0,0 +1,10 @@ +require_vector_vs; +P_LOOP(32, { + if ((INT32_MIN != ps1) | (INT32_MIN != ps2)) { + int64_t mres = ((int64_t) ps1 * (int64_t) ps2) << 1; + pd = ((mres >> 31) + 1) >> 1; + } else { + pd = INT32_MAX; + P_SET_OV(1); + } +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/lb.h b/vendor/riscv/riscv-isa-sim/riscv/insns/lb.h new file mode 100644 index 0000000000..cd6b46125f --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/lb.h @@ -0,0 +1 @@ +WRITE_RD(MMU.load<int8_t>(RS1 + insn.i_imm())); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/lbu.h b/vendor/riscv/riscv-isa-sim/riscv/insns/lbu.h new file mode 100644 index 0000000000..bcdf7cad6a --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/lbu.h @@ -0,0 +1 @@ +WRITE_RD(MMU.load<uint8_t>(RS1 + insn.i_imm())); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/ld.h b/vendor/riscv/riscv-isa-sim/riscv/insns/ld.h new file mode 100644 index 0000000000..3dea301e2a --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/ld.h @@ -0,0 +1,2 @@ +require_rv64; +WRITE_RD(MMU.load<int64_t>(RS1 + insn.i_imm())); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/lh.h b/vendor/riscv/riscv-isa-sim/riscv/insns/lh.h new file mode 100644 index 0000000000..845451a78e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/lh.h @@ -0,0 +1 @@ +WRITE_RD(MMU.load<int16_t>(RS1 + insn.i_imm())); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/lhu.h b/vendor/riscv/riscv-isa-sim/riscv/insns/lhu.h new file mode 100644 index 0000000000..6eac0bb9a9 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/lhu.h @@ -0,0 +1 @@ +WRITE_RD(MMU.load<uint16_t>(RS1 + insn.i_imm())); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/lr_d.h b/vendor/riscv/riscv-isa-sim/riscv/insns/lr_d.h new file mode 100644 index 0000000000..214daff26a --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/lr_d.h @@ -0,0 +1,3 @@ +require_extension('A'); +require_rv64; +WRITE_RD(MMU.load_reserved<int64_t>(RS1)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/lr_w.h b/vendor/riscv/riscv-isa-sim/riscv/insns/lr_w.h new file mode 100644 index 0000000000..354590f26f --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/lr_w.h @@ -0,0 +1,2 @@ +require_extension('A'); +WRITE_RD(MMU.load_reserved<int32_t>(RS1)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/lui.h b/vendor/riscv/riscv-isa-sim/riscv/insns/lui.h new file mode 100644 index 0000000000..c7b5264e00 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/lui.h @@ -0,0 +1 @@ +WRITE_RD(insn.u_imm()); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/lw.h b/vendor/riscv/riscv-isa-sim/riscv/insns/lw.h new file mode 100644 index 0000000000..82d7044442 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/lw.h @@ -0,0 +1 @@ +WRITE_RD(MMU.load<int32_t>(RS1 + insn.i_imm())); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/lwu.h b/vendor/riscv/riscv-isa-sim/riscv/insns/lwu.h new file mode 100644 index 0000000000..cbc7e2abd2 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/lwu.h @@ -0,0 +1,2 @@ +require_rv64; +WRITE_RD(MMU.load<uint32_t>(RS1 + insn.i_imm())); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/maddr32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/maddr32.h new file mode 100644 index 0000000000..943aeac9a3 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/maddr32.h @@ -0,0 +1,5 @@ +require_extension(EXT_ZPN); +reg_t mres = (reg_t)P_W(RS1, 0) * P_W(RS2, 0); +reg_t rd = P_W(RD, 0); +rd += mres; +WRITE_RD(sext_xlen((int32_t)rd)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/max.h b/vendor/riscv/riscv-isa-sim/riscv/insns/max.h new file mode 100644 index 0000000000..073b8df2ee --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/max.h @@ -0,0 +1,2 @@ +require_either_extension(EXT_ZBPBO, EXT_ZBB); +WRITE_RD(sext_xlen(sreg_t(RS1) > sreg_t(RS2) ? RS1 : RS2)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/maxu.h b/vendor/riscv/riscv-isa-sim/riscv/insns/maxu.h new file mode 100644 index 0000000000..05af49258a --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/maxu.h @@ -0,0 +1,2 @@ +require_extension(EXT_ZBB); +WRITE_RD(sext_xlen(RS1 > RS2 ? RS1 : RS2)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/min.h b/vendor/riscv/riscv-isa-sim/riscv/insns/min.h new file mode 100644 index 0000000000..47bc993c57 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/min.h @@ -0,0 +1,2 @@ +require_either_extension(EXT_ZBPBO, EXT_ZBB); +WRITE_RD(sext_xlen(sreg_t(RS1) < sreg_t(RS2) ? RS1 : RS2)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/minu.h b/vendor/riscv/riscv-isa-sim/riscv/insns/minu.h new file mode 100644 index 0000000000..7582c0d178 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/minu.h @@ -0,0 +1,2 @@ +require_extension(EXT_ZBB); +WRITE_RD(sext_xlen(RS1 < RS2 ? RS1 : RS2)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/mnret.h b/vendor/riscv/riscv-isa-sim/riscv/insns/mnret.h new file mode 100644 index 0000000000..bc69510620 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/mnret.h @@ -0,0 +1,15 @@ +require_extension(EXT_SMRNMI); +require_privilege(PRV_M); +set_pc_and_serialize(p->get_state()->mnepc->read()); +reg_t s = STATE.mnstatus->read(); +reg_t prev_prv = get_field(s, MNSTATUS_MNPP); +reg_t prev_virt = get_field(s, MNSTATUS_MNPV); +if (prev_prv != PRV_M) { + reg_t mstatus = STATE.mstatus->read(); + mstatus = set_field(mstatus, MSTATUS_MPRV, 0); + STATE.mstatus->write(mstatus); +} +s = set_field(s, MNSTATUS_NMIE, 1); +STATE.mnstatus->write(s); +p->set_privilege(prev_prv); +p->set_virt(prev_virt); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/mret.h b/vendor/riscv/riscv-isa-sim/riscv/insns/mret.h new file mode 100644 index 0000000000..5198b8fc64 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/mret.h @@ -0,0 +1,14 @@ +require_privilege(PRV_M); +set_pc_and_serialize(p->get_state()->mepc->read()); +reg_t s = STATE.mstatus->read(); +reg_t prev_prv = get_field(s, MSTATUS_MPP); +reg_t prev_virt = get_field(s, MSTATUS_MPV); +if (prev_prv != PRV_M) + s = set_field(s, MSTATUS_MPRV, 0); +s = set_field(s, MSTATUS_MIE, get_field(s, MSTATUS_MPIE)); +s = set_field(s, MSTATUS_MPIE, 1); +s = set_field(s, MSTATUS_MPP, p->extension_enabled('U') ? PRV_U : PRV_M); +s = set_field(s, MSTATUS_MPV, 0); +p->put_csr(CSR_MSTATUS, s); +p->set_privilege(prev_prv); +p->set_virt(prev_virt); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/msubr32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/msubr32.h new file mode 100644 index 0000000000..2086bd198a --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/msubr32.h @@ -0,0 +1,5 @@ +require_extension(EXT_ZPN); +reg_t mres = (reg_t)P_W(RS1, 0) * P_W(RS2, 0); +reg_t rd = P_W(RD, 0); +rd -= mres; +WRITE_RD(sext_xlen((int32_t)rd)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/mul.h b/vendor/riscv/riscv-isa-sim/riscv/insns/mul.h new file mode 100644 index 0000000000..52d002259c --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/mul.h @@ -0,0 +1,2 @@ +require_either_extension('M', EXT_ZMMUL); +WRITE_RD(sext_xlen(RS1 * RS2)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/mulh.h b/vendor/riscv/riscv-isa-sim/riscv/insns/mulh.h new file mode 100644 index 0000000000..a8f67d1248 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/mulh.h @@ -0,0 +1,5 @@ +require_either_extension('M', EXT_ZMMUL); +if (xlen == 64) + WRITE_RD(mulh(RS1, RS2)); +else + WRITE_RD(sext32((sext32(RS1) * sext32(RS2)) >> 32)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/mulhsu.h b/vendor/riscv/riscv-isa-sim/riscv/insns/mulhsu.h new file mode 100644 index 0000000000..cb5caa4ef4 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/mulhsu.h @@ -0,0 +1,5 @@ +require_either_extension('M', EXT_ZMMUL); +if (xlen == 64) + WRITE_RD(mulhsu(RS1, RS2)); +else + WRITE_RD(sext32((sext32(RS1) * reg_t((uint32_t)RS2)) >> 32)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/mulhu.h b/vendor/riscv/riscv-isa-sim/riscv/insns/mulhu.h new file mode 100644 index 0000000000..9ce751e3a3 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/mulhu.h @@ -0,0 +1,5 @@ +require_either_extension('M', EXT_ZMMUL); +if (xlen == 64) + WRITE_RD(mulhu(RS1, RS2)); +else + WRITE_RD(sext32(((uint64_t)(uint32_t)RS1 * (uint64_t)(uint32_t)RS2) >> 32)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/mulr64.h b/vendor/riscv/riscv-isa-sim/riscv/insns/mulr64.h new file mode 100644 index 0000000000..4e2aad758d --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/mulr64.h @@ -0,0 +1,3 @@ +require_extension(EXT_ZPSFOPERAND); +reg_t rd = (reg_t)P_W(RS1, 0) * P_W(RS2, 0); +P_64_PROFILE_END(); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/mulsr64.h b/vendor/riscv/riscv-isa-sim/riscv/insns/mulsr64.h new file mode 100644 index 0000000000..a2a51156fb --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/mulsr64.h @@ -0,0 +1,3 @@ +require_extension(EXT_ZPSFOPERAND); +sreg_t rd = (sreg_t)P_SW(RS1, 0) * P_SW(RS2, 0); +P_64_PROFILE_END(); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/mulw.h b/vendor/riscv/riscv-isa-sim/riscv/insns/mulw.h new file mode 100644 index 0000000000..20108d840a --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/mulw.h @@ -0,0 +1,3 @@ +require_either_extension('M', EXT_ZMMUL); +require_rv64; +WRITE_RD(sext32(RS1 * RS2)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/or.h b/vendor/riscv/riscv-isa-sim/riscv/insns/or.h new file mode 100644 index 0000000000..3f2fffc22e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/or.h @@ -0,0 +1 @@ +WRITE_RD(RS1 | RS2); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/ori.h b/vendor/riscv/riscv-isa-sim/riscv/insns/ori.h new file mode 100644 index 0000000000..3aba1cb2d6 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/ori.h @@ -0,0 +1,2 @@ +// prefetch.i/r/w hint when rd = 0 and i_imm[4:0] = 0/1/3 +WRITE_RD(insn.i_imm() | RS1); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/orn.h b/vendor/riscv/riscv-isa-sim/riscv/insns/orn.h new file mode 100644 index 0000000000..c1c9fd4d4b --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/orn.h @@ -0,0 +1,2 @@ +require_either_extension(EXT_ZBB, EXT_ZBKB); +WRITE_RD(RS1 | ~RS2); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/pack.h b/vendor/riscv/riscv-isa-sim/riscv/insns/pack.h new file mode 100644 index 0000000000..2140f918d0 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/pack.h @@ -0,0 +1,11 @@ +// RV32Zbb contains zext.h but not general pack +require(((xlen == 32) && (insn.rs2() == 0) && p->extension_enabled(EXT_ZBB)) + || p->extension_enabled(EXT_ZPN) + || p->extension_enabled(EXT_ZBKB) + || p->extension_enabled(EXT_XZBP) + || p->extension_enabled(EXT_XZBE) + || p->extension_enabled(EXT_XZBF) + || ((xlen == 64) && p->extension_enabled(EXT_XZBM))); +reg_t lo = zext_xlen(RS1 << (xlen/2)) >> (xlen/2); +reg_t hi = zext_xlen(RS2 << (xlen/2)); +WRITE_RD(sext_xlen(lo | hi)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/packh.h b/vendor/riscv/riscv-isa-sim/riscv/insns/packh.h new file mode 100644 index 0000000000..82886e3293 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/packh.h @@ -0,0 +1,7 @@ +require(p->extension_enabled(EXT_ZBKB) || + p->extension_enabled(EXT_XZBP) || + p->extension_enabled(EXT_XZBE) || + p->extension_enabled(EXT_XZBF)); +reg_t lo = zext_xlen(RS1 << (xlen-8)) >> (xlen-8); +reg_t hi = zext_xlen(RS2 << (xlen-8)) >> (xlen-16); +WRITE_RD(sext_xlen(lo | hi)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/packu.h b/vendor/riscv/riscv-isa-sim/riscv/insns/packu.h new file mode 100644 index 0000000000..441207c32e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/packu.h @@ -0,0 +1,6 @@ +require(p->extension_enabled(EXT_ZPN) || + p->extension_enabled(EXT_XZBP) || + ((xlen == 64) && p->extension_enabled(EXT_XZBM))); +reg_t lo = zext_xlen(RS1) >> (xlen/2); +reg_t hi = zext_xlen(RS2) >> (xlen/2) << (xlen/2); +WRITE_RD(sext_xlen(lo | hi)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/packuw.h b/vendor/riscv/riscv-isa-sim/riscv/insns/packuw.h new file mode 100644 index 0000000000..1b3f7d5f54 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/packuw.h @@ -0,0 +1,5 @@ +require_rv64; +require_extension(EXT_XZBP); +reg_t lo = zext32(RS1) >> 16; +reg_t hi = zext32(RS2) >> 16 << 16; +WRITE_RD(sext32(lo | hi)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/packw.h b/vendor/riscv/riscv-isa-sim/riscv/insns/packw.h new file mode 100644 index 0000000000..084c190d0d --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/packw.h @@ -0,0 +1,10 @@ +// RV64Zbb contains zext.h but not general packw +require(((insn.rs2() == 0) && p->extension_enabled(EXT_ZBB)) + || p->extension_enabled(EXT_ZBKB) + || p->extension_enabled(EXT_XZBP) + || p->extension_enabled(EXT_XZBE) + || p->extension_enabled(EXT_XZBF)); +require_rv64; +reg_t lo = zext32(RS1 << 16) >> 16; +reg_t hi = zext32(RS2 << 16); +WRITE_RD(sext32(lo | hi)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/pbsad.h b/vendor/riscv/riscv-isa-sim/riscv/insns/pbsad.h new file mode 100644 index 0000000000..32789ef8a7 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/pbsad.h @@ -0,0 +1,3 @@ +P_REDUCTION_ULOOP(64, 8, false, false, { + pd_res += (ps1 > ps2 ? ps1 - ps2 : ps2 - ps1); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/pbsada.h b/vendor/riscv/riscv-isa-sim/riscv/insns/pbsada.h new file mode 100644 index 0000000000..cab988ed0c --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/pbsada.h @@ -0,0 +1,3 @@ +P_REDUCTION_ULOOP(64, 8, true, false, { + pd_res += (ps1 > ps2 ? ps1 - ps2 : ps2 - ps1); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/pkbb16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/pkbb16.h new file mode 100644 index 0000000000..20dcde611f --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/pkbb16.h @@ -0,0 +1,2 @@ +require_rv64; +P_PK(16, 0, 0); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/pkbt16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/pkbt16.h new file mode 100644 index 0000000000..8c51ab7dc3 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/pkbt16.h @@ -0,0 +1 @@ +P_PK(16, 0, 1); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/pkbt32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/pkbt32.h new file mode 100644 index 0000000000..2783d98053 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/pkbt32.h @@ -0,0 +1,2 @@ +require_rv64; +P_PK(32, 0, 1); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/pktb16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/pktb16.h new file mode 100644 index 0000000000..c49c1ed31e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/pktb16.h @@ -0,0 +1 @@ +P_PK(16, 1, 0); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/pktb32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/pktb32.h new file mode 100644 index 0000000000..0a7e17f4f4 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/pktb32.h @@ -0,0 +1,2 @@ +require_rv64; +P_PK(32, 1, 0); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/pktt16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/pktt16.h new file mode 100644 index 0000000000..b263ed400d --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/pktt16.h @@ -0,0 +1,2 @@ +require_rv64; +P_PK(16, 1, 1); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/radd16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/radd16.h new file mode 100644 index 0000000000..8f80050297 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/radd16.h @@ -0,0 +1,3 @@ +P_LOOP(16, { + pd = (ps1 + ps2) >> 1; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/radd32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/radd32.h new file mode 100644 index 0000000000..df50dd178d --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/radd32.h @@ -0,0 +1,4 @@ +require_rv64; +P_LOOP(32, { + pd = ((int64_t)ps1 + ps2) >> 1; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/radd64.h b/vendor/riscv/riscv-isa-sim/riscv/insns/radd64.h new file mode 100644 index 0000000000..110c472c32 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/radd64.h @@ -0,0 +1,8 @@ +P_64_PROFILE({ + rd = (rs1 + rs2) >> 1; + if (rs1 > 0 && rs2 > 0) { + rd &= ~((reg_t)1 << 63); + } else if (rs1 < 0 && rs2 < 0) { + rd |= ((reg_t)1 << 63); + } +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/radd8.h b/vendor/riscv/riscv-isa-sim/riscv/insns/radd8.h new file mode 100644 index 0000000000..ad0b6eced9 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/radd8.h @@ -0,0 +1,3 @@ +P_LOOP(8, { + pd = (ps1 + ps2) >> 1; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/raddw.h b/vendor/riscv/riscv-isa-sim/riscv/insns/raddw.h new file mode 100644 index 0000000000..ec04bb6d22 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/raddw.h @@ -0,0 +1,4 @@ +require_extension(EXT_ZPN); +sreg_t res = (sreg_t)P_SW(RS1, 0) + (sreg_t)P_SW(RS2, 0); +res >>= 1; +WRITE_RD(sext_xlen(res)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/rcras16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/rcras16.h new file mode 100644 index 0000000000..529c27fe47 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/rcras16.h @@ -0,0 +1,5 @@ +P_CROSS_LOOP(16, { + pd = (ps1 + ps2) >> 1; +}, { + pd = (ps1 - ps2) >> 1; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/rcras32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/rcras32.h new file mode 100644 index 0000000000..86a3f65e99 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/rcras32.h @@ -0,0 +1,6 @@ +require_rv64; +P_CROSS_LOOP(32, { + pd = ((int64_t)ps1 + ps2) >> 1; +}, { + pd = ((int64_t)ps1 - ps2) >> 1; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/rcrsa16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/rcrsa16.h new file mode 100644 index 0000000000..156e32c471 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/rcrsa16.h @@ -0,0 +1,5 @@ +P_CROSS_LOOP(16, { + pd = (ps1 - ps2) >> 1; +}, { + pd = (ps1 + ps2) >> 1; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/rcrsa32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/rcrsa32.h new file mode 100644 index 0000000000..b45f31fe44 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/rcrsa32.h @@ -0,0 +1,6 @@ +require_rv64; +P_CROSS_LOOP(32, { + pd = ((uint64_t)ps1 - ps2) >> 1; +}, { + pd = ((uint64_t)ps1 + ps2) >> 1; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/rem.h b/vendor/riscv/riscv-isa-sim/riscv/insns/rem.h new file mode 100644 index 0000000000..d2ee066844 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/rem.h @@ -0,0 +1,9 @@ +require_extension('M'); +sreg_t lhs = sext_xlen(RS1); +sreg_t rhs = sext_xlen(RS2); +if (rhs == 0) + WRITE_RD(lhs); +else if (lhs == INT64_MIN && rhs == -1) + WRITE_RD(0); +else + WRITE_RD(sext_xlen(lhs % rhs)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/remu.h b/vendor/riscv/riscv-isa-sim/riscv/insns/remu.h new file mode 100644 index 0000000000..676747ade9 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/remu.h @@ -0,0 +1,7 @@ +require_extension('M'); +reg_t lhs = zext_xlen(RS1); +reg_t rhs = zext_xlen(RS2); +if (rhs == 0) + WRITE_RD(sext_xlen(RS1)); +else + WRITE_RD(sext_xlen(lhs % rhs)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/remuw.h b/vendor/riscv/riscv-isa-sim/riscv/insns/remuw.h new file mode 100644 index 0000000000..caa1583ef6 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/remuw.h @@ -0,0 +1,8 @@ +require_extension('M'); +require_rv64; +reg_t lhs = zext32(RS1); +reg_t rhs = zext32(RS2); +if (rhs == 0) + WRITE_RD(sext32(lhs)); +else + WRITE_RD(sext32(lhs % rhs)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/remw.h b/vendor/riscv/riscv-isa-sim/riscv/insns/remw.h new file mode 100644 index 0000000000..076096c1f5 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/remw.h @@ -0,0 +1,8 @@ +require_extension('M'); +require_rv64; +sreg_t lhs = sext32(RS1); +sreg_t rhs = sext32(RS2); +if (rhs == 0) + WRITE_RD(lhs); +else + WRITE_RD(sext32(lhs % rhs)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/rol.h b/vendor/riscv/riscv-isa-sim/riscv/insns/rol.h new file mode 100644 index 0000000000..07735a1b32 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/rol.h @@ -0,0 +1,4 @@ +require_either_extension(EXT_ZBB, EXT_ZBKB); +int shamt = RS2 & (xlen-1); +int rshamt = -shamt & (xlen-1); +WRITE_RD(sext_xlen((RS1 << shamt) | (zext_xlen(RS1) >> rshamt))); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/rolw.h b/vendor/riscv/riscv-isa-sim/riscv/insns/rolw.h new file mode 100644 index 0000000000..4d5eeb193f --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/rolw.h @@ -0,0 +1,5 @@ +require_rv64; +require_either_extension(EXT_ZBB, EXT_ZBKB); +int shamt = RS2 & 31; +int rshamt = -shamt & 31; +WRITE_RD(sext32((RS1 << shamt) | (zext32(RS1) >> rshamt))); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/ror.h b/vendor/riscv/riscv-isa-sim/riscv/insns/ror.h new file mode 100644 index 0000000000..61b5ff8f7c --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/ror.h @@ -0,0 +1,4 @@ +require_either_extension(EXT_ZBB, EXT_ZBKB); +int shamt = RS2 & (xlen-1); +int rshamt = -shamt & (xlen-1); +WRITE_RD(sext_xlen((RS1 << rshamt) | (zext_xlen(RS1) >> shamt))); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/rori.h b/vendor/riscv/riscv-isa-sim/riscv/insns/rori.h new file mode 100644 index 0000000000..6585b60fa9 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/rori.h @@ -0,0 +1,5 @@ +require_either_extension(EXT_ZBB, EXT_ZBKB); +require(SHAMT < xlen); +int shamt = SHAMT & (xlen-1); +int rshamt = -shamt & (xlen-1); +WRITE_RD(sext_xlen((RS1 << rshamt) | (zext_xlen(RS1) >> shamt))); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/roriw.h b/vendor/riscv/riscv-isa-sim/riscv/insns/roriw.h new file mode 100644 index 0000000000..331d2264af --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/roriw.h @@ -0,0 +1,6 @@ +require_rv64; +require_either_extension(EXT_ZBB, EXT_ZBKB); +require(SHAMT < 32); +int shamt = SHAMT & 31; +int rshamt = -shamt & 31; +WRITE_RD(sext32((RS1 << rshamt) | (zext32(RS1) >> shamt))); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/rorw.h b/vendor/riscv/riscv-isa-sim/riscv/insns/rorw.h new file mode 100644 index 0000000000..65f0078cc8 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/rorw.h @@ -0,0 +1,5 @@ +require_rv64; +require_either_extension(EXT_ZBB, EXT_ZBKB); +int shamt = RS2 & 31; +int rshamt = -shamt & 31; +WRITE_RD(sext32((RS1 << rshamt) | (zext32(RS1) >> shamt))); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/rstas16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/rstas16.h new file mode 100644 index 0000000000..298b59174e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/rstas16.h @@ -0,0 +1,5 @@ +P_STRAIGHT_LOOP(16, { + pd = (ps1 + ps2) >> 1; +}, { + pd = (ps1 - ps2) >> 1; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/rstas32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/rstas32.h new file mode 100644 index 0000000000..9c8995a8f1 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/rstas32.h @@ -0,0 +1,6 @@ +require_rv64; +P_STRAIGHT_LOOP(32, { + pd = ((int64_t)ps1 + ps2) >> 1; +}, { + pd = ((int64_t)ps1 - ps2) >> 1; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/rstsa16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/rstsa16.h new file mode 100644 index 0000000000..443e4cef5f --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/rstsa16.h @@ -0,0 +1,5 @@ +P_STRAIGHT_LOOP(16, { + pd = (ps1 - ps2) >> 1; +}, { + pd = (ps1 + ps2) >> 1; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/rstsa32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/rstsa32.h new file mode 100644 index 0000000000..a89fc6eac4 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/rstsa32.h @@ -0,0 +1,6 @@ +require_rv64; +P_STRAIGHT_LOOP(32, { + pd = ((int64_t)ps1 - ps2) >> 1; +}, { + pd = ((int64_t)ps1 + ps2) >> 1; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/rsub16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/rsub16.h new file mode 100644 index 0000000000..768e067753 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/rsub16.h @@ -0,0 +1,3 @@ +P_LOOP(16, { + pd = (ps1 - ps2) >> 1; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/rsub32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/rsub32.h new file mode 100644 index 0000000000..22c31199a2 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/rsub32.h @@ -0,0 +1,4 @@ +require_rv64; +P_LOOP(32, { + pd = ((int64_t)ps1 - ps2) >> 1; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/rsub64.h b/vendor/riscv/riscv-isa-sim/riscv/insns/rsub64.h new file mode 100644 index 0000000000..2a5848519a --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/rsub64.h @@ -0,0 +1,8 @@ +P_64_PROFILE({ + rd = (rs1 - rs2) >> 1; + if (rs1 > 0 && rs2 < 0) { + rd &= ~((reg_t)1 << 63); + } else if (rs1 < 0 && rs2 > 0) { + rd |= ((reg_t)1 << 63); + } +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/rsub8.h b/vendor/riscv/riscv-isa-sim/riscv/insns/rsub8.h new file mode 100644 index 0000000000..9cf9c1a875 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/rsub8.h @@ -0,0 +1,3 @@ +P_LOOP(8, { + pd = (ps1 - ps2) >> 1; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/rsubw.h b/vendor/riscv/riscv-isa-sim/riscv/insns/rsubw.h new file mode 100644 index 0000000000..01dec51a7f --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/rsubw.h @@ -0,0 +1,4 @@ +require_extension(EXT_ZPN); +sreg_t res = (sreg_t)P_SW(RS1, 0) - (sreg_t)P_SW(RS2, 0); +res >>= 1; +WRITE_RD(sext_xlen(res)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sb.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sb.h new file mode 100644 index 0000000000..d9cc8f9f4a --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sb.h @@ -0,0 +1 @@ +MMU.store<uint8_t>(RS1 + insn.s_imm(), RS2); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sc_d.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sc_d.h new file mode 100644 index 0000000000..ac82c3ec60 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sc_d.h @@ -0,0 +1,6 @@ +require_extension('A'); +require_rv64; + +bool have_reservation = MMU.store_conditional<uint64_t>(RS1, RS2); + +WRITE_RD(!have_reservation); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sc_w.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sc_w.h new file mode 100644 index 0000000000..48fea4b5bf --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sc_w.h @@ -0,0 +1,5 @@ +require_extension('A'); + +bool have_reservation = MMU.store_conditional<uint32_t>(RS1, RS2); + +WRITE_RD(!have_reservation); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sclip16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sclip16.h new file mode 100644 index 0000000000..d90ce19c56 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sclip16.h @@ -0,0 +1,14 @@ +require_vector_vs; +P_I_LOOP(16, 4, { + int64_t int_max = INT64_MAX >> (64 - (imm4u + 1)); + int64_t int_min = INT64_MIN >> (64 - (imm4u + 1)); + pd = ps1; + + if (ps1 > int_max) { + pd = int_max; + P_SET_OV(1); + } else if (ps1 < int_min) { + pd = int_min; + P_SET_OV(1); + } +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sclip32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sclip32.h new file mode 100644 index 0000000000..ff1ba287bc --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sclip32.h @@ -0,0 +1,14 @@ +require_vector_vs; +P_I_LOOP(32, 5, { + int64_t int_max = INT64_MAX >> (64 - (imm5u + 1)); + int64_t int_min = INT64_MIN >> (64 - (imm5u + 1)); + pd = ps1; + + if (ps1 > int_max) { + pd = int_max; + P_SET_OV(1); + } else if (ps1 < int_min) { + pd = int_min; + P_SET_OV(1); + } +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sclip8.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sclip8.h new file mode 100644 index 0000000000..afd9c69292 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sclip8.h @@ -0,0 +1,14 @@ +require_vector_vs; +P_I_LOOP(8, 3, { + int64_t int_max = INT64_MAX >> (64 - (imm3u + 1)); + int64_t int_min = INT64_MIN >> (64 - (imm3u + 1)); + pd = ps1; + + if (ps1 > int_max) { + pd = int_max; + P_SET_OV(1); + } else if (ps1 < int_min) { + pd = int_min; + P_SET_OV(1); + } +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/scmple16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/scmple16.h new file mode 100644 index 0000000000..060c04c2e6 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/scmple16.h @@ -0,0 +1,3 @@ +P_LOOP(16, { + pd = (ps1 <= ps2) ? -1 : 0; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/scmple8.h b/vendor/riscv/riscv-isa-sim/riscv/insns/scmple8.h new file mode 100644 index 0000000000..8920c1f565 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/scmple8.h @@ -0,0 +1,3 @@ +P_LOOP(8, { + pd = (ps1 <= ps2) ? -1 : 0; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/scmplt16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/scmplt16.h new file mode 100644 index 0000000000..db62f6f7bc --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/scmplt16.h @@ -0,0 +1,3 @@ +P_LOOP(16, { + pd = (ps1 < ps2) ? -1 : 0; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/scmplt8.h b/vendor/riscv/riscv-isa-sim/riscv/insns/scmplt8.h new file mode 100644 index 0000000000..7d07209789 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/scmplt8.h @@ -0,0 +1,3 @@ +P_LOOP(8, { + pd = (ps1 < ps2) ? -1 : 0; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sd.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sd.h new file mode 100644 index 0000000000..5c9dd4e1b9 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sd.h @@ -0,0 +1,2 @@ +require_rv64; +MMU.store<uint64_t>(RS1 + insn.s_imm(), RS2); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sext_b.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sext_b.h new file mode 100644 index 0000000000..5acde617c8 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sext_b.h @@ -0,0 +1,2 @@ +require_extension(EXT_ZBB); +WRITE_RD((sreg_t)(int8_t)(RS1)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sext_h.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sext_h.h new file mode 100644 index 0000000000..e89a68d3a3 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sext_h.h @@ -0,0 +1,2 @@ +require_extension(EXT_ZBB); +WRITE_RD((sreg_t)(int16_t)(RS1)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sfence_inval_ir.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sfence_inval_ir.h new file mode 100644 index 0000000000..6f76a3ff45 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sfence_inval_ir.h @@ -0,0 +1,4 @@ +require_extension('S'); +require_extension(EXT_SVINVAL); +require_impl(IMPL_MMU); +require_privilege_hs_qualified(PRV_S); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sfence_vma.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sfence_vma.h new file mode 100644 index 0000000000..7d6c01a8be --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sfence_vma.h @@ -0,0 +1,9 @@ +require_extension('S'); +require_impl(IMPL_MMU); +if (STATE.v) { + if (STATE.prv == PRV_U || get_field(STATE.hstatus->read(), HSTATUS_VTVM)) + require_novirt(); +} else { + require_privilege(get_field(STATE.mstatus->read(), MSTATUS_TVM) ? PRV_M : PRV_S); +} +MMU.flush_tlb(); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sfence_w_inval.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sfence_w_inval.h new file mode 100644 index 0000000000..d1af529f95 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sfence_w_inval.h @@ -0,0 +1 @@ +#include "sfence_inval_ir.h" diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sh.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sh.h new file mode 100644 index 0000000000..8f780c3832 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sh.h @@ -0,0 +1 @@ +MMU.store<uint16_t>(RS1 + insn.s_imm(), RS2); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sh1add.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sh1add.h new file mode 100644 index 0000000000..6cbc36050c --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sh1add.h @@ -0,0 +1,2 @@ +require_extension(EXT_ZBA); +WRITE_RD(sext_xlen((RS1 << 1) + RS2)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sh1add_uw.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sh1add_uw.h new file mode 100644 index 0000000000..1177002642 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sh1add_uw.h @@ -0,0 +1,3 @@ +require_rv64; +require_extension(EXT_ZBA); +WRITE_RD(sext_xlen((zext32(RS1) << 1) + RS2)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sh2add.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sh2add.h new file mode 100644 index 0000000000..ea55e79a40 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sh2add.h @@ -0,0 +1,2 @@ +require_extension(EXT_ZBA); +WRITE_RD(sext_xlen((RS1 << 2) + RS2)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sh2add_uw.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sh2add_uw.h new file mode 100644 index 0000000000..b51250d963 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sh2add_uw.h @@ -0,0 +1,3 @@ +require_rv64; +require_extension(EXT_ZBA); +WRITE_RD(sext_xlen((zext32(RS1) << 2) + RS2)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sh3add.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sh3add.h new file mode 100644 index 0000000000..de71f0fae4 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sh3add.h @@ -0,0 +1,2 @@ +require_extension(EXT_ZBA); +WRITE_RD(sext_xlen((RS1 << 3) + RS2)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sh3add_uw.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sh3add_uw.h new file mode 100644 index 0000000000..b618b85186 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sh3add_uw.h @@ -0,0 +1,3 @@ +require_rv64; +require_extension(EXT_ZBA); +WRITE_RD(sext_xlen((zext32(RS1) << 3) + RS2)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sha256sig0.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sha256sig0.h new file mode 100644 index 0000000000..f86e42f7a0 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sha256sig0.h @@ -0,0 +1,13 @@ + +require_extension(EXT_ZKNH); + +#define ROR32(a,amt) ((a << (-amt & (32-1))) | (a >> (amt & (32-1)))) + +uint32_t a = RS1; + +WRITE_RD( + sext32(ROR32(a, 7) ^ ROR32(a,18) ^ (a >> 3)) +); + +#undef ROR32 + diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sha256sig1.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sha256sig1.h new file mode 100644 index 0000000000..72e586cb83 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sha256sig1.h @@ -0,0 +1,13 @@ + +require_extension(EXT_ZKNH); + +#define ROR32(a,amt) ((a << (-amt & (32-1))) | (a >> (amt & (32-1)))) + +uint32_t a = RS1; + +WRITE_RD( + sext32(ROR32(a, 17) ^ ROR32(a,19) ^ (a >> 10)) +); + +#undef ROR32 + diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sha256sum0.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sha256sum0.h new file mode 100644 index 0000000000..f0aed47fe1 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sha256sum0.h @@ -0,0 +1,13 @@ + +require_extension(EXT_ZKNH); + +#define ROR32(a,amt) ((a << (-amt & (32-1))) | (a >> (amt & (32-1)))) + +uint32_t a = RS1; + +WRITE_RD( + sext32(ROR32(a, 2) ^ ROR32(a,13) ^ ROR32(a, 22)) +); + +#undef ROR32 + diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sha256sum1.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sha256sum1.h new file mode 100644 index 0000000000..41de5afe2a --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sha256sum1.h @@ -0,0 +1,13 @@ + +require_extension(EXT_ZKNH); + +#define ROR32(a,amt) ((a << (-amt & (32-1))) | (a >> (amt & (32-1)))) + +uint32_t a = RS1; + +WRITE_RD( + sext32(ROR32(a, 6) ^ ROR32(a,11) ^ ROR32(a, 25)) +); + +#undef ROR32 + diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sha512sig0.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sha512sig0.h new file mode 100644 index 0000000000..2efd763d7b --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sha512sig0.h @@ -0,0 +1,13 @@ +require_rv64; +require_extension(EXT_ZKNH); + +#define ROR64(a,amt) ((a << (-amt & (64-1))) | (a >> (amt & (64-1)))) + +uint64_t a = RS1; + +WRITE_RD( + ROR64(a, 1) ^ ROR64(a, 8) ^ (a >> 7) +); + +#undef ROR64 + diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sha512sig0h.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sha512sig0h.h new file mode 100644 index 0000000000..eb6a2a25b6 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sha512sig0h.h @@ -0,0 +1,9 @@ + +require_rv32; +require_extension(EXT_ZKNH); + +reg_t result = + (zext32(RS1) >> 1) ^ (zext32(RS1) >> 7) ^ (zext32(RS1) >> 8) ^ + (zext32(RS2) << 31) ^ (zext32(RS2) << 24); + +WRITE_RD(sext_xlen(result)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sha512sig0l.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sha512sig0l.h new file mode 100644 index 0000000000..599a6a107e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sha512sig0l.h @@ -0,0 +1,9 @@ + +require_rv32; +require_extension(EXT_ZKNH); + +reg_t result = + (zext32(RS1) >> 1) ^ (zext32(RS1) >> 7) ^ (zext32(RS1) >> 8) ^ + (zext32(RS2) << 31) ^ (zext32(RS2) << 25) ^ (zext32(RS2) << 24); + +WRITE_RD(sext_xlen(result)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sha512sig1.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sha512sig1.h new file mode 100644 index 0000000000..2176654171 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sha512sig1.h @@ -0,0 +1,13 @@ +require_rv64; +require_extension(EXT_ZKNH); + +#define ROR64(a,amt) ((a << (-amt & (64-1))) | (a >> (amt & (64-1)))) + +uint64_t a = RS1; + +WRITE_RD( + ROR64(a, 19) ^ ROR64(a,61) ^ (a >> 6) +); + +#undef ROR64 + diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sha512sig1h.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sha512sig1h.h new file mode 100644 index 0000000000..271a1f908f --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sha512sig1h.h @@ -0,0 +1,9 @@ + +require_rv32; +require_extension(EXT_ZKNH); + +reg_t result = + (zext32(RS1) << 3) ^ (zext32(RS1) >> 6) ^ (zext32(RS1) >> 19) ^ + (zext32(RS2) >> 29) ^ (zext32(RS2) << 13); + +WRITE_RD(sext_xlen(result)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sha512sig1l.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sha512sig1l.h new file mode 100644 index 0000000000..491810d3a9 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sha512sig1l.h @@ -0,0 +1,9 @@ + +require_rv32; +require_extension(EXT_ZKNH); + +reg_t result = + (zext32(RS1) << 3) ^ (zext32(RS1) >> 6) ^ (zext32(RS1) >> 19) ^ + (zext32(RS2) >> 29) ^ (zext32(RS2) << 26) ^ (zext32(RS2) << 13); + +WRITE_RD(sext_xlen(result)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sha512sum0.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sha512sum0.h new file mode 100644 index 0000000000..01182e679a --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sha512sum0.h @@ -0,0 +1,13 @@ +require_rv64; +require_extension(EXT_ZKNH); + +#define ROR64(a,amt) ((a << (-amt & (64-1))) | (a >> (amt & (64-1)))) + +uint64_t a = RS1; + +WRITE_RD( + ROR64(a, 28) ^ ROR64(a,34) ^ ROR64(a,39) +); + +#undef ROR64 + diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sha512sum0r.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sha512sum0r.h new file mode 100644 index 0000000000..cb6c636f23 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sha512sum0r.h @@ -0,0 +1,9 @@ + +require_rv32; +require_extension(EXT_ZKNH); + +reg_t result = + (zext32(RS1) << 25) ^ (zext32(RS1) << 30) ^ (zext32(RS1) >> 28) ^ + (zext32(RS2) >> 7) ^ (zext32(RS2) >> 2) ^ (zext32(RS2) << 4); + +WRITE_RD(sext_xlen(result)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sha512sum1.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sha512sum1.h new file mode 100644 index 0000000000..267d7dd991 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sha512sum1.h @@ -0,0 +1,13 @@ +require_rv64; +require_extension(EXT_ZKNH); + +#define ROR64(a,amt) ((a << (-amt & (64-1))) | (a >> (amt & (64-1)))) + +uint64_t a = RS1; + +WRITE_RD( + ROR64(a, 14) ^ ROR64(a, 18) ^ ROR64(a, 41) +); + +#undef ROR64 + diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sha512sum1r.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sha512sum1r.h new file mode 100644 index 0000000000..8109d0dc84 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sha512sum1r.h @@ -0,0 +1,9 @@ + +require_rv32; +require_extension(EXT_ZKNH); + +reg_t result = + (zext32(RS1) << 23) ^ (zext32(RS1) >> 14) ^ (zext32(RS1) >> 18) ^ + (zext32(RS2) >> 9) ^ (zext32(RS2) << 18) ^ (zext32(RS2) << 14); + +WRITE_RD(sext_xlen(result)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/shfl.h b/vendor/riscv/riscv-isa-sim/riscv/insns/shfl.h new file mode 100644 index 0000000000..3004871e2c --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/shfl.h @@ -0,0 +1,9 @@ +require_extension(EXT_XZBP); +reg_t x = RS1; +int shamt = RS2 & ((xlen-1) >> 1); +if (shamt & 16) x = (x & 0xFFFF00000000FFFFLL) | ((x & 0x0000FFFF00000000LL) >> 16) | ((x & 0x00000000FFFF0000LL) << 16); +if (shamt & 8) x = (x & 0xFF0000FFFF0000FFLL) | ((x & 0x00FF000000FF0000LL) >> 8) | ((x & 0x0000FF000000FF00LL) << 8); +if (shamt & 4) x = (x & 0xF00FF00FF00FF00FLL) | ((x & 0x0F000F000F000F00LL) >> 4) | ((x & 0x00F000F000F000F0LL) << 4); +if (shamt & 2) x = (x & 0xC3C3C3C3C3C3C3C3LL) | ((x & 0x3030303030303030LL) >> 2) | ((x & 0x0C0C0C0C0C0C0C0CLL) << 2); +if (shamt & 1) x = (x & 0x9999999999999999LL) | ((x & 0x4444444444444444LL) >> 1) | ((x & 0x2222222222222222LL) << 1); +WRITE_RD(sext_xlen(x)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/shfli.h b/vendor/riscv/riscv-isa-sim/riscv/insns/shfli.h new file mode 100644 index 0000000000..f8636190f0 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/shfli.h @@ -0,0 +1,12 @@ +// Zbkb contains zip but not general shfli +require(((insn.rs2() == (xlen / 2 - 1)) && p->extension_enabled(EXT_ZBKB)) + || p->extension_enabled(EXT_XZBP)); +require(SHAMT < (xlen/2)); +reg_t x = RS1; +int shamt = SHAMT & ((xlen-1) >> 1); +if (shamt & 16) x = (x & 0xFFFF00000000FFFFLL) | ((x & 0x0000FFFF00000000LL) >> 16) | ((x & 0x00000000FFFF0000LL) << 16); +if (shamt & 8) x = (x & 0xFF0000FFFF0000FFLL) | ((x & 0x00FF000000FF0000LL) >> 8) | ((x & 0x0000FF000000FF00LL) << 8); +if (shamt & 4) x = (x & 0xF00FF00FF00FF00FLL) | ((x & 0x0F000F000F000F00LL) >> 4) | ((x & 0x00F000F000F000F0LL) << 4); +if (shamt & 2) x = (x & 0xC3C3C3C3C3C3C3C3LL) | ((x & 0x3030303030303030LL) >> 2) | ((x & 0x0C0C0C0C0C0C0C0CLL) << 2); +if (shamt & 1) x = (x & 0x9999999999999999LL) | ((x & 0x4444444444444444LL) >> 1) | ((x & 0x2222222222222222LL) << 1); +WRITE_RD(sext_xlen(x)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/shflw.h b/vendor/riscv/riscv-isa-sim/riscv/insns/shflw.h new file mode 100644 index 0000000000..06ee36045e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/shflw.h @@ -0,0 +1,9 @@ +require_rv64; +require_extension(EXT_XZBP); +reg_t x = RS1; +int shamt = RS2 & 15; +if (shamt & 8) x = (x & 0xFF0000FFFF0000FFLL) | ((x & 0x00FF000000FF0000LL) >> 8) | ((x & 0x0000FF000000FF00LL) << 8); +if (shamt & 4) x = (x & 0xF00FF00FF00FF00FLL) | ((x & 0x0F000F000F000F00LL) >> 4) | ((x & 0x00F000F000F000F0LL) << 4); +if (shamt & 2) x = (x & 0xC3C3C3C3C3C3C3C3LL) | ((x & 0x3030303030303030LL) >> 2) | ((x & 0x0C0C0C0C0C0C0C0CLL) << 2); +if (shamt & 1) x = (x & 0x9999999999999999LL) | ((x & 0x4444444444444444LL) >> 1) | ((x & 0x2222222222222222LL) << 1); +WRITE_RD(sext32(x)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sinval_vma.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sinval_vma.h new file mode 100644 index 0000000000..5e43149765 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sinval_vma.h @@ -0,0 +1,2 @@ +require_extension(EXT_SVINVAL); +#include "sfence_vma.h" diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sll.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sll.h new file mode 100644 index 0000000000..7db761318f --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sll.h @@ -0,0 +1 @@ +WRITE_RD(sext_xlen(RS1 << (RS2 & (xlen-1)))); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sll16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sll16.h new file mode 100644 index 0000000000..9659f53e93 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sll16.h @@ -0,0 +1,3 @@ +P_X_ULOOP(16, 4, { + pd = ps1 << sa; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sll32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sll32.h new file mode 100644 index 0000000000..8a05b39b3b --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sll32.h @@ -0,0 +1,4 @@ +require_rv64; +P_X_ULOOP(32, 5, { + pd = ps1 << sa; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sll8.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sll8.h new file mode 100644 index 0000000000..b7f069a3d8 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sll8.h @@ -0,0 +1,3 @@ +P_X_ULOOP(8, 3, { + pd = ps1 << sa; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/slli.h b/vendor/riscv/riscv-isa-sim/riscv/insns/slli.h new file mode 100644 index 0000000000..26782fda3d --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/slli.h @@ -0,0 +1,2 @@ +require(SHAMT < xlen); +WRITE_RD(sext_xlen(RS1 << SHAMT)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/slli16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/slli16.h new file mode 100644 index 0000000000..8d89a61f0f --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/slli16.h @@ -0,0 +1,3 @@ +P_I_ULOOP(16, 4, { + pd = ps1 << imm4u; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/slli32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/slli32.h new file mode 100644 index 0000000000..71d880af2d --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/slli32.h @@ -0,0 +1,4 @@ +require_rv64; +P_I_ULOOP(32, 5, { + pd = ps1 << imm5u; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/slli8.h b/vendor/riscv/riscv-isa-sim/riscv/insns/slli8.h new file mode 100644 index 0000000000..c997496f01 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/slli8.h @@ -0,0 +1,3 @@ +P_I_ULOOP(8, 3, { + pd = ps1 << imm3u; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/slli_uw.h b/vendor/riscv/riscv-isa-sim/riscv/insns/slli_uw.h new file mode 100644 index 0000000000..9cd48a912c --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/slli_uw.h @@ -0,0 +1,3 @@ +require_rv64; +require_extension(EXT_ZBA); +WRITE_RD(sext_xlen(zext32(RS1) << SHAMT)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/slliw.h b/vendor/riscv/riscv-isa-sim/riscv/insns/slliw.h new file mode 100644 index 0000000000..c1fda656c2 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/slliw.h @@ -0,0 +1,2 @@ +require_rv64; +WRITE_RD(sext32(RS1 << SHAMT)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sllw.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sllw.h new file mode 100644 index 0000000000..affe894441 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sllw.h @@ -0,0 +1,2 @@ +require_rv64; +WRITE_RD(sext32(RS1 << (RS2 & 0x1F))); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/slo.h b/vendor/riscv/riscv-isa-sim/riscv/insns/slo.h new file mode 100644 index 0000000000..a27ec37e2e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/slo.h @@ -0,0 +1,2 @@ +require_extension(EXT_XZBP); +WRITE_RD(sext_xlen(~((~RS1) << (RS2 & (xlen-1))))); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sloi.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sloi.h new file mode 100644 index 0000000000..62278b030b --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sloi.h @@ -0,0 +1,3 @@ +require(SHAMT < xlen); +require_extension(EXT_XZBP); +WRITE_RD(sext_xlen(~((~RS1) << SHAMT))); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sloiw.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sloiw.h new file mode 100644 index 0000000000..492c94a112 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sloiw.h @@ -0,0 +1,3 @@ +require_rv64; +require_extension(EXT_XZBP); +WRITE_RD(sext32(~((~RS1) << SHAMT))); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/slow.h b/vendor/riscv/riscv-isa-sim/riscv/insns/slow.h new file mode 100644 index 0000000000..04c90a45d4 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/slow.h @@ -0,0 +1,3 @@ +require_rv64; +require_extension(EXT_XZBP); +WRITE_RD(sext32(~((~RS1) << (RS2 & 0x1F)))); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/slt.h b/vendor/riscv/riscv-isa-sim/riscv/insns/slt.h new file mode 100644 index 0000000000..25ccd45ee8 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/slt.h @@ -0,0 +1 @@ +WRITE_RD(sreg_t(RS1) < sreg_t(RS2)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/slti.h b/vendor/riscv/riscv-isa-sim/riscv/insns/slti.h new file mode 100644 index 0000000000..3671d2418f --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/slti.h @@ -0,0 +1 @@ +WRITE_RD(sreg_t(RS1) < sreg_t(insn.i_imm())); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sltiu.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sltiu.h new file mode 100644 index 0000000000..f39845713f --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sltiu.h @@ -0,0 +1 @@ +WRITE_RD(RS1 < reg_t(insn.i_imm())); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sltu.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sltu.h new file mode 100644 index 0000000000..84d97a2a3d --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sltu.h @@ -0,0 +1 @@ +WRITE_RD(RS1 < RS2); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sm3p0.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sm3p0.h new file mode 100644 index 0000000000..0a72a930c8 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sm3p0.h @@ -0,0 +1,14 @@ + +require_extension(EXT_ZKSH); + +#define ROL32(a,amt) ((a >> (-amt & (32-1))) | (a << (amt & (32-1)))) + +uint32_t src = RS1; +uint32_t result = src ^ ROL32(src, 9) ^ ROL32(src, 17); + +WRITE_RD( + sext32(result) +); + +#undef ROL32 + diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sm3p1.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sm3p1.h new file mode 100644 index 0000000000..ce3e36c7d0 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sm3p1.h @@ -0,0 +1,14 @@ + +require_extension(EXT_ZKSH); + +#define ROL32(a,amt) ((a >> (-amt & (32-1))) | (a << (amt & (32-1)))) + +uint32_t src = RS1; +uint32_t result = src ^ ROL32(src, 15) ^ ROL32(src, 23); + +WRITE_RD( + sext32(result) +); + +#undef ROL32 + diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sm4_common.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sm4_common.h new file mode 100644 index 0000000000..17f129f0ad --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sm4_common.h @@ -0,0 +1,27 @@ + +// SM4 forward SBox. SM4 has no inverse sbox. +static const uint8_t sm4_sbox[256] = { + 0xD6, 0x90, 0xE9, 0xFE, 0xCC, 0xE1, 0x3D, 0xB7, 0x16, 0xB6, 0x14, 0xC2, + 0x28, 0xFB, 0x2C, 0x05, 0x2B, 0x67, 0x9A, 0x76, 0x2A, 0xBE, 0x04, 0xC3, + 0xAA, 0x44, 0x13, 0x26, 0x49, 0x86, 0x06, 0x99, 0x9C, 0x42, 0x50, 0xF4, + 0x91, 0xEF, 0x98, 0x7A, 0x33, 0x54, 0x0B, 0x43, 0xED, 0xCF, 0xAC, 0x62, + 0xE4, 0xB3, 0x1C, 0xA9, 0xC9, 0x08, 0xE8, 0x95, 0x80, 0xDF, 0x94, 0xFA, + 0x75, 0x8F, 0x3F, 0xA6, 0x47, 0x07, 0xA7, 0xFC, 0xF3, 0x73, 0x17, 0xBA, + 0x83, 0x59, 0x3C, 0x19, 0xE6, 0x85, 0x4F, 0xA8, 0x68, 0x6B, 0x81, 0xB2, + 0x71, 0x64, 0xDA, 0x8B, 0xF8, 0xEB, 0x0F, 0x4B, 0x70, 0x56, 0x9D, 0x35, + 0x1E, 0x24, 0x0E, 0x5E, 0x63, 0x58, 0xD1, 0xA2, 0x25, 0x22, 0x7C, 0x3B, + 0x01, 0x21, 0x78, 0x87, 0xD4, 0x00, 0x46, 0x57, 0x9F, 0xD3, 0x27, 0x52, + 0x4C, 0x36, 0x02, 0xE7, 0xA0, 0xC4, 0xC8, 0x9E, 0xEA, 0xBF, 0x8A, 0xD2, + 0x40, 0xC7, 0x38, 0xB5, 0xA3, 0xF7, 0xF2, 0xCE, 0xF9, 0x61, 0x15, 0xA1, + 0xE0, 0xAE, 0x5D, 0xA4, 0x9B, 0x34, 0x1A, 0x55, 0xAD, 0x93, 0x32, 0x30, + 0xF5, 0x8C, 0xB1, 0xE3, 0x1D, 0xF6, 0xE2, 0x2E, 0x82, 0x66, 0xCA, 0x60, + 0xC0, 0x29, 0x23, 0xAB, 0x0D, 0x53, 0x4E, 0x6F, 0xD5, 0xDB, 0x37, 0x45, + 0xDE, 0xFD, 0x8E, 0x2F, 0x03, 0xFF, 0x6A, 0x72, 0x6D, 0x6C, 0x5B, 0x51, + 0x8D, 0x1B, 0xAF, 0x92, 0xBB, 0xDD, 0xBC, 0x7F, 0x11, 0xD9, 0x5C, 0x41, + 0x1F, 0x10, 0x5A, 0xD8, 0x0A, 0xC1, 0x31, 0x88, 0xA5, 0xCD, 0x7B, 0xBD, + 0x2D, 0x74, 0xD0, 0x12, 0xB8, 0xE5, 0xB4, 0xB0, 0x89, 0x69, 0x97, 0x4A, + 0x0C, 0x96, 0x77, 0x7E, 0x65, 0xB9, 0xF1, 0x09, 0xC5, 0x6E, 0xC6, 0x84, + 0x18, 0xF0, 0x7D, 0xEC, 0x3A, 0xDC, 0x4D, 0x20, 0x79, 0xEE, 0x5F, 0x3E, + 0xD7, 0xCB, 0x39, 0x48 +}; + diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sm4ed.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sm4ed.h new file mode 100644 index 0000000000..a78c1a8767 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sm4ed.h @@ -0,0 +1,22 @@ + +require_extension(EXT_ZKSED); + +#include "sm4_common.h" + +uint8_t bs = insn.bs(); + +uint32_t sb_in = (RS2 >> (8*bs)) & 0xFF; +uint32_t sb_out = (uint32_t)sm4_sbox[sb_in]; + +uint32_t linear = sb_out ^ (sb_out << 8) ^ + (sb_out << 2) ^ + (sb_out << 18) ^ + ((sb_out & 0x3f) << 26) ^ + ((sb_out & 0xC0) << 10) ; + +uint32_t rotl = (linear << (8*bs)) | (linear >> (32-8*bs)); + +uint32_t result = rotl ^ RS1; + +WRITE_RD(sext32(result)); + diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sm4ks.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sm4ks.h new file mode 100644 index 0000000000..c93c97ed60 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sm4ks.h @@ -0,0 +1,20 @@ + +require_extension(EXT_ZKSED); + +#include "sm4_common.h" + +uint8_t bs = insn.bs(); + +uint32_t sb_in = (RS2 >> (8*bs)) & 0xFF; +uint32_t sb_out = sm4_sbox[sb_in]; + +uint32_t x = sb_out ^ + ((sb_out & 0x07) << 29) ^ ((sb_out & 0xFE) << 7) ^ + ((sb_out & 0x01) << 23) ^ ((sb_out & 0xF8) << 13) ; + +uint32_t rotl = (x << (8*bs)) | (x >> (32-8*bs)); + +uint32_t result = rotl ^ RS1; + +WRITE_RD(sext32(result)); + diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/smal.h b/vendor/riscv/riscv-isa-sim/riscv/insns/smal.h new file mode 100644 index 0000000000..09b818d72b --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/smal.h @@ -0,0 +1,11 @@ +require_extension(EXT_ZPSFOPERAND); +sreg_t res = 0; +if (xlen == 32) { + res = RS1_PAIR; + res += sext_xlen(P_SH(RS2, 0) * P_SH(RS2, 1)); + WRITE_RD_PAIR(res); +} else { + res = sext_xlen(P_SH(RS2, 0) * P_SH(RS2, 1)) + + sext_xlen(P_SH(RS2, 2) * P_SH(RS2, 3)) + RS1; + WRITE_RD(res); +} diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/smalbb.h b/vendor/riscv/riscv-isa-sim/riscv/insns/smalbb.h new file mode 100644 index 0000000000..9a2e799487 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/smalbb.h @@ -0,0 +1,3 @@ +P_64_PROFILE_REDUCTION(32, { + rd += (sreg_t)P_SH(ps1, 0) * (sreg_t)P_SH(ps2, 0); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/smalbt.h b/vendor/riscv/riscv-isa-sim/riscv/insns/smalbt.h new file mode 100644 index 0000000000..42cf71cc1f --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/smalbt.h @@ -0,0 +1,3 @@ +P_64_PROFILE_REDUCTION(32, { + rd += (sreg_t)P_SH(ps1, 0) * (sreg_t)P_SH(ps2, 1); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/smalda.h b/vendor/riscv/riscv-isa-sim/riscv/insns/smalda.h new file mode 100644 index 0000000000..8c06793938 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/smalda.h @@ -0,0 +1,3 @@ +P_64_PROFILE_REDUCTION(16, { + rd += ps1 * ps2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/smaldrs.h b/vendor/riscv/riscv-isa-sim/riscv/insns/smaldrs.h new file mode 100644 index 0000000000..84e176999c --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/smaldrs.h @@ -0,0 +1,7 @@ +P_64_PROFILE_REDUCTION(16, { + if (i & 1) { + rd -= ps1 * ps2; + } else { + rd += ps1 * ps2; + } +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/smalds.h b/vendor/riscv/riscv-isa-sim/riscv/insns/smalds.h new file mode 100644 index 0000000000..e3cfbd7cb0 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/smalds.h @@ -0,0 +1,7 @@ +P_64_PROFILE_REDUCTION(16, { + if (i & 1) { + rd += ps1 * ps2; + } else { + rd -= ps1 * ps2; + } +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/smaltt.h b/vendor/riscv/riscv-isa-sim/riscv/insns/smaltt.h new file mode 100644 index 0000000000..1e654a06e2 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/smaltt.h @@ -0,0 +1,3 @@ +P_64_PROFILE_REDUCTION(32, { + rd += P_SH(ps1, 1) * P_SH(ps2, 1); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/smalxda.h b/vendor/riscv/riscv-isa-sim/riscv/insns/smalxda.h new file mode 100644 index 0000000000..77675ee9c4 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/smalxda.h @@ -0,0 +1,4 @@ +P_64_PROFILE_REDUCTION(32, { + rd += (sreg_t)P_SH(ps1, 0) * (sreg_t)P_SH(ps2, 1); + rd += (sreg_t)P_SH(ps1, 1) * (sreg_t)P_SH(ps2, 0); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/smalxds.h b/vendor/riscv/riscv-isa-sim/riscv/insns/smalxds.h new file mode 100644 index 0000000000..2ae7eb53b2 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/smalxds.h @@ -0,0 +1,4 @@ +P_64_PROFILE_REDUCTION(32, { + rd += (sreg_t)P_SH(ps1, 1) * (sreg_t)P_SH(ps2, 0); + rd -= (sreg_t)P_SH(ps1, 0) * (sreg_t)P_SH(ps2, 1); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/smaqa.h b/vendor/riscv/riscv-isa-sim/riscv/insns/smaqa.h new file mode 100644 index 0000000000..83dda84f68 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/smaqa.h @@ -0,0 +1,3 @@ +P_REDUCTION_LOOP(32, 8, true, false, { + pd_res += ps1 * ps2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/smaqa_su.h b/vendor/riscv/riscv-isa-sim/riscv/insns/smaqa_su.h new file mode 100644 index 0000000000..4ee0eb7899 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/smaqa_su.h @@ -0,0 +1,3 @@ +P_REDUCTION_SULOOP(32, 8, true, false, { + pd_res += ps1 * ps2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/smar64.h b/vendor/riscv/riscv-isa-sim/riscv/insns/smar64.h new file mode 100644 index 0000000000..5c5da771c6 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/smar64.h @@ -0,0 +1,3 @@ +P_64_PROFILE_REDUCTION(32, { + rd += ps1 * ps2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/smax16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/smax16.h new file mode 100644 index 0000000000..083d63ce39 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/smax16.h @@ -0,0 +1,3 @@ +P_LOOP(16, { + pd = (ps1 > ps2) ? ps1 : ps2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/smax32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/smax32.h new file mode 100644 index 0000000000..6563cfc19e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/smax32.h @@ -0,0 +1,3 @@ +P_LOOP(32, { + pd = (ps1 > ps2) ? ps1 : ps2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/smax8.h b/vendor/riscv/riscv-isa-sim/riscv/insns/smax8.h new file mode 100644 index 0000000000..773039e3ee --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/smax8.h @@ -0,0 +1,3 @@ +P_LOOP(8, { + pd = (ps1 > ps2) ? ps1 : ps2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/smbb16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/smbb16.h new file mode 100644 index 0000000000..0813bfbfed --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/smbb16.h @@ -0,0 +1,3 @@ +P_LOOP(32, { + pd = P_SH(ps1, 0) * P_SH(ps2, 0); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/smbt16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/smbt16.h new file mode 100644 index 0000000000..953b3a624b --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/smbt16.h @@ -0,0 +1,3 @@ +P_LOOP(32, { + pd = P_SH(ps1, 0) * P_SH(ps2, 1); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/smbt32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/smbt32.h new file mode 100644 index 0000000000..35059ad38d --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/smbt32.h @@ -0,0 +1,3 @@ +require_rv64; +require_extension(EXT_ZPN); +WRITE_RD((sreg_t)P_SW(RS1, 0) * P_SW(RS2, 1)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/smdrs.h b/vendor/riscv/riscv-isa-sim/riscv/insns/smdrs.h new file mode 100644 index 0000000000..8f47f7d42f --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/smdrs.h @@ -0,0 +1,6 @@ +P_REDUCTION_LOOP(32, 16, false, false, { + if (j & 1) + pd_res -= ps1 * ps2; + else + pd_res += ps1 * ps2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/smdrs32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/smdrs32.h new file mode 100644 index 0000000000..c397013dce --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/smdrs32.h @@ -0,0 +1,7 @@ +require_rv64; +require_extension(EXT_ZPN); + +sreg_t mres0 = (sreg_t)P_SW(RS1, 0) * P_SW(RS2, 0); +sreg_t mres1 = (sreg_t)P_SW(RS1, 1) * P_SW(RS2, 1); + +WRITE_RD(mres0 - mres1); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/smds.h b/vendor/riscv/riscv-isa-sim/riscv/insns/smds.h new file mode 100644 index 0000000000..248679a523 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/smds.h @@ -0,0 +1,6 @@ +P_REDUCTION_LOOP(32, 16, false, false, { + if (j & 1) + pd_res += ps1 * ps2; + else + pd_res -= ps1 * ps2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/smds32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/smds32.h new file mode 100644 index 0000000000..e7fdeedd9b --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/smds32.h @@ -0,0 +1,7 @@ +require_rv64; +require_extension(EXT_ZPN); + +sreg_t mres0 = (sreg_t)P_SW(RS1, 0) * P_SW(RS2, 0); +sreg_t mres1 = (sreg_t)P_SW(RS1, 1) * P_SW(RS2, 1); + +WRITE_RD(mres1 - mres0); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/smin16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/smin16.h new file mode 100644 index 0000000000..afb1bb3b00 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/smin16.h @@ -0,0 +1,3 @@ +P_LOOP(16, { + pd = (ps1 < ps2) ? ps1 : ps2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/smin32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/smin32.h new file mode 100644 index 0000000000..22847cb415 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/smin32.h @@ -0,0 +1,3 @@ +P_LOOP(32, { + pd = (ps1 < ps2) ? ps1 : ps2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/smin8.h b/vendor/riscv/riscv-isa-sim/riscv/insns/smin8.h new file mode 100644 index 0000000000..084e0e6667 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/smin8.h @@ -0,0 +1,3 @@ +P_LOOP(8, { + pd = (ps1 < ps2) ? ps1 : ps2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/smmul.h b/vendor/riscv/riscv-isa-sim/riscv/insns/smmul.h new file mode 100644 index 0000000000..df0dd239b2 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/smmul.h @@ -0,0 +1,4 @@ +P_LOOP(32, { + int64_t mres = (int64_t) ps1 * (int64_t) ps2; + pd = mres >> 32; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/smmul_u.h b/vendor/riscv/riscv-isa-sim/riscv/insns/smmul_u.h new file mode 100644 index 0000000000..55fa617fa3 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/smmul_u.h @@ -0,0 +1,4 @@ +P_LOOP(32, { + int64_t mres = (int64_t) ps1 * (int64_t) ps2; + pd = ((mres >> 31) + 1) >> 1; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/smmwb.h b/vendor/riscv/riscv-isa-sim/riscv/insns/smmwb.h new file mode 100644 index 0000000000..f94aa9c00c --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/smmwb.h @@ -0,0 +1,4 @@ +P_LOOP(32, { + int64_t mres = (int64_t) ps1 * (int16_t) P_H(ps2, 0); + pd = mres >> 16; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/smmwb_u.h b/vendor/riscv/riscv-isa-sim/riscv/insns/smmwb_u.h new file mode 100644 index 0000000000..47c6e362c7 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/smmwb_u.h @@ -0,0 +1,4 @@ +P_LOOP(32, { + int64_t mres = (int64_t) ps1 * (int16_t) P_H(ps2, 0); + pd = ((mres >> 15) + 1) >> 1; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/smmwt.h b/vendor/riscv/riscv-isa-sim/riscv/insns/smmwt.h new file mode 100644 index 0000000000..d8cf439fb6 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/smmwt.h @@ -0,0 +1,4 @@ +P_LOOP(32, { + int64_t mres = (int64_t) ps1 * (int16_t) P_H(ps2, 1); + pd = mres >> 16; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/smmwt_u.h b/vendor/riscv/riscv-isa-sim/riscv/insns/smmwt_u.h new file mode 100644 index 0000000000..5c5a671f38 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/smmwt_u.h @@ -0,0 +1,4 @@ +P_LOOP(32, { + int64_t mres = (int64_t) ps1 * (int16_t) P_H(ps2, 1); + pd = ((mres >> 15) + 1) >> 1; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/smslda.h b/vendor/riscv/riscv-isa-sim/riscv/insns/smslda.h new file mode 100644 index 0000000000..f838960910 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/smslda.h @@ -0,0 +1,3 @@ +P_64_PROFILE_REDUCTION(16, { + rd -= ps1 * ps2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/smslxda.h b/vendor/riscv/riscv-isa-sim/riscv/insns/smslxda.h new file mode 100644 index 0000000000..7e25f9b839 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/smslxda.h @@ -0,0 +1,4 @@ +P_64_PROFILE_REDUCTION(32, { + rd -= (sreg_t)P_SH(ps1, 1) * (sreg_t)P_SH(ps2, 0); + rd -= (sreg_t)P_SH(ps1, 0) * (sreg_t)P_SH(ps2, 1); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/smsr64.h b/vendor/riscv/riscv-isa-sim/riscv/insns/smsr64.h new file mode 100644 index 0000000000..a43559fd6f --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/smsr64.h @@ -0,0 +1,3 @@ +P_64_PROFILE_REDUCTION(32, { + rd -= ps1 * ps2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/smtt16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/smtt16.h new file mode 100644 index 0000000000..e19c50a32f --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/smtt16.h @@ -0,0 +1,3 @@ +P_LOOP(32, { + pd = P_SH(ps1, 1) * P_SH(ps2, 1); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/smtt32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/smtt32.h new file mode 100644 index 0000000000..c7fd9e71df --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/smtt32.h @@ -0,0 +1,3 @@ +require_rv64; +require_extension(EXT_ZPN); +WRITE_RD((sreg_t)P_SW(RS1, 1) * P_SW(RS2, 1)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/smul16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/smul16.h new file mode 100644 index 0000000000..7e0f08abb6 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/smul16.h @@ -0,0 +1,3 @@ +P_MUL_LOOP(16, { + pd = (int32_t)ps1 * (int32_t)ps2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/smul8.h b/vendor/riscv/riscv-isa-sim/riscv/insns/smul8.h new file mode 100644 index 0000000000..a4a3ed93f9 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/smul8.h @@ -0,0 +1,3 @@ +P_MUL_LOOP(8, { + pd = (int16_t)ps1 * (int16_t)ps2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/smulx16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/smulx16.h new file mode 100644 index 0000000000..58e9a08d0e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/smulx16.h @@ -0,0 +1,3 @@ +P_MUL_CROSS_LOOP(16, { + pd = (int32_t)ps1 * (int32_t)ps2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/smulx8.h b/vendor/riscv/riscv-isa-sim/riscv/insns/smulx8.h new file mode 100644 index 0000000000..9270ce361c --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/smulx8.h @@ -0,0 +1,3 @@ +P_MUL_CROSS_LOOP(8, { + pd = (int16_t)ps1 * (int16_t)ps2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/smxds.h b/vendor/riscv/riscv-isa-sim/riscv/insns/smxds.h new file mode 100644 index 0000000000..845d01f655 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/smxds.h @@ -0,0 +1,6 @@ +P_REDUCTION_CROSS_LOOP(32, 16, false, false, { + if (j & 1) + pd_res += ps1 * ps2; + else + pd_res -= ps1 * ps2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/smxds32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/smxds32.h new file mode 100644 index 0000000000..8eeedcf95c --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/smxds32.h @@ -0,0 +1,7 @@ +require_rv64; +require_extension(EXT_ZPN); + +sreg_t mres0 = (sreg_t)P_SW(RS1, 0) * P_SW(RS2, 1); +sreg_t mres1 = (sreg_t)P_SW(RS1, 1) * P_SW(RS2, 0); + +WRITE_RD(mres1 - mres0); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sra.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sra.h new file mode 100644 index 0000000000..403b9b733a --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sra.h @@ -0,0 +1 @@ +WRITE_RD(sext_xlen(sext_xlen(RS1) >> (RS2 & (xlen-1)))); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sra16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sra16.h new file mode 100644 index 0000000000..84a40fb5d9 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sra16.h @@ -0,0 +1,3 @@ +P_X_LOOP(16, 4, { + pd = ps1 >> sa; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sra16_u.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sra16_u.h new file mode 100644 index 0000000000..6fcc398f16 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sra16_u.h @@ -0,0 +1,6 @@ +P_X_LOOP(16, 4, { + if (sa > 0) + pd = ((ps1 >> (sa - 1)) + 1) >> 1; + else + pd = ps1; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sra32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sra32.h new file mode 100644 index 0000000000..8b192e0c7e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sra32.h @@ -0,0 +1,4 @@ +require_rv64; +P_X_LOOP(32, 5, { + pd = ps1 >> sa; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sra32_u.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sra32_u.h new file mode 100644 index 0000000000..1a4488c58d --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sra32_u.h @@ -0,0 +1,7 @@ +require_rv64; +P_X_LOOP(32, 5, { + if (sa > 0) + pd = (((uint64_t)(ps1 >> (sa - 1))) + 1) >> 1; + else + pd = ps1; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sra8.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sra8.h new file mode 100644 index 0000000000..de1bd64ec8 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sra8.h @@ -0,0 +1,3 @@ +P_X_LOOP(8, 3, { + pd = ps1 >> sa; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sra8_u.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sra8_u.h new file mode 100644 index 0000000000..1f47623e83 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sra8_u.h @@ -0,0 +1,6 @@ +P_X_LOOP(8, 3, { + if (sa > 0) + pd = ((ps1 >> (sa - 1)) + 1) >> 1; + else + pd = ps1; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sra_u.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sra_u.h new file mode 100644 index 0000000000..d7c395b0c4 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sra_u.h @@ -0,0 +1,9 @@ +require_extension(EXT_ZPN); +sreg_t rs1 = sext_xlen(RS1); +reg_t sa = get_field(RS2, make_mask64(0, xlen == 32 ? 5 : 6)); + +if (sa > 0) { + WRITE_RD(sext_xlen(((rs1 >> (sa - 1)) + 1) >> 1)); +} else { + WRITE_RD(sext_xlen(rs1)); +} diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/srai.h b/vendor/riscv/riscv-isa-sim/riscv/insns/srai.h new file mode 100644 index 0000000000..7ae1d4e5af --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/srai.h @@ -0,0 +1,2 @@ +require(SHAMT < xlen); +WRITE_RD(sext_xlen(sext_xlen(RS1) >> SHAMT)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/srai16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/srai16.h new file mode 100644 index 0000000000..63f98073d0 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/srai16.h @@ -0,0 +1,3 @@ +P_I_LOOP(16, 4, { + pd = ps1 >> imm4u; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/srai16_u.h b/vendor/riscv/riscv-isa-sim/riscv/insns/srai16_u.h new file mode 100644 index 0000000000..d7835817bd --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/srai16_u.h @@ -0,0 +1,6 @@ +P_I_LOOP(16, 4, { + if (imm4u > 0) + pd = ((ps1 >> (imm4u - 1)) + 1) >> 1; + else + pd = ps1; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/srai32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/srai32.h new file mode 100644 index 0000000000..9058ba9d6b --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/srai32.h @@ -0,0 +1,4 @@ +require_rv64; +P_I_LOOP(32, 5, { + pd = ps1 >> imm5u; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/srai32_u.h b/vendor/riscv/riscv-isa-sim/riscv/insns/srai32_u.h new file mode 100644 index 0000000000..a5fe4d3ddf --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/srai32_u.h @@ -0,0 +1,7 @@ +require_rv64; +P_I_LOOP(32, 5, { + if (imm5u > 0) + pd = (((uint64_t)(ps1 >> (imm5u - 1))) + 1) >> 1; + else + pd = ps1; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/srai8.h b/vendor/riscv/riscv-isa-sim/riscv/insns/srai8.h new file mode 100644 index 0000000000..0141933ead --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/srai8.h @@ -0,0 +1,3 @@ +P_I_LOOP(8, 3, { + pd = ps1 >> imm3u; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/srai8_u.h b/vendor/riscv/riscv-isa-sim/riscv/insns/srai8_u.h new file mode 100644 index 0000000000..be7bfaf726 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/srai8_u.h @@ -0,0 +1,6 @@ +P_I_LOOP(8, 3, { + if (imm3u > 0) + pd = ((ps1 >> (imm3u - 1)) + 1) >> 1; + else + pd = ps1; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/srai_u.h b/vendor/riscv/riscv-isa-sim/riscv/insns/srai_u.h new file mode 100644 index 0000000000..f170083eef --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/srai_u.h @@ -0,0 +1,10 @@ +require_extension(EXT_ZPN); +sreg_t rs1 = sext_xlen(RS1); +reg_t sa = insn.p_imm6(); +require(sa < (unsigned long)xlen); // imm[5] == 1 is illegal on rv32 + +if (sa > 0) { + WRITE_RD(sext_xlen(((rs1 >> (sa - 1)) + 1) >> 1)); +} else { + WRITE_RD(sext_xlen(rs1)); +} diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sraiw.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sraiw.h new file mode 100644 index 0000000000..b344459bf4 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sraiw.h @@ -0,0 +1,2 @@ +require_rv64; +WRITE_RD(sext32(int32_t(RS1) >> SHAMT)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sraiw_u.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sraiw_u.h new file mode 100644 index 0000000000..3559d7fa14 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sraiw_u.h @@ -0,0 +1,9 @@ +require_rv64; +require_extension(EXT_ZPN); + +reg_t sa = insn.p_imm5(); +if (sa != 0) { + WRITE_RD(sext32(((P_SW(RS1, 0) >> (sa - 1)) + 1) >> 1)); +} else { + WRITE_RD(sext32(P_SW(RS1, 0))); +} diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sraw.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sraw.h new file mode 100644 index 0000000000..ca9c0c76ce --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sraw.h @@ -0,0 +1,2 @@ +require_rv64; +WRITE_RD(sext32(int32_t(RS1) >> (RS2 & 0x1F))); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sret.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sret.h new file mode 100644 index 0000000000..5102c15cc3 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sret.h @@ -0,0 +1,27 @@ +require_extension('S'); +reg_t prev_hstatus = STATE.hstatus->read(); +if (STATE.v) { + if (STATE.prv == PRV_U || get_field(prev_hstatus, HSTATUS_VTSR)) + require_novirt(); +} else { + require_privilege(get_field(STATE.mstatus->read(), MSTATUS_TSR) ? PRV_M : PRV_S); +} +reg_t next_pc = p->get_state()->sepc->read(); +set_pc_and_serialize(next_pc); +reg_t s = STATE.sstatus->read(); +reg_t prev_prv = get_field(s, MSTATUS_SPP); +s = set_field(s, MSTATUS_SIE, get_field(s, MSTATUS_SPIE)); +s = set_field(s, MSTATUS_SPIE, 1); +s = set_field(s, MSTATUS_SPP, PRV_U); +STATE.sstatus->write(s); +p->set_privilege(prev_prv); +if (!STATE.v) { + if (p->extension_enabled('H')) { + reg_t prev_virt = get_field(prev_hstatus, HSTATUS_SPV); + p->set_virt(prev_virt); + reg_t new_hstatus = set_field(prev_hstatus, HSTATUS_SPV, 0); + STATE.hstatus->write(new_hstatus); + } + + STATE.mstatus->write(set_field(STATE.mstatus->read(), MSTATUS_MPRV, 0)); +} diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/srl.h b/vendor/riscv/riscv-isa-sim/riscv/insns/srl.h new file mode 100644 index 0000000000..0dabe9ecde --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/srl.h @@ -0,0 +1 @@ +WRITE_RD(sext_xlen(zext_xlen(RS1) >> (RS2 & (xlen-1)))); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/srl16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/srl16.h new file mode 100644 index 0000000000..35f9cecb6d --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/srl16.h @@ -0,0 +1,3 @@ +P_X_ULOOP(16, 4, { + pd = ps1 >> sa; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/srl16_u.h b/vendor/riscv/riscv-isa-sim/riscv/insns/srl16_u.h new file mode 100644 index 0000000000..17d1bc0024 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/srl16_u.h @@ -0,0 +1,7 @@ +P_X_ULOOP(16, 4, { + if (sa > 0) { + pd = ((ps1 >> (sa - 1)) + 1) >> 1; + } else { + pd = ps1; + } +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/srl32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/srl32.h new file mode 100644 index 0000000000..2ad116ccf3 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/srl32.h @@ -0,0 +1,4 @@ +require_rv64; +P_X_ULOOP(32, 5, { + pd = ps1 >> sa; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/srl32_u.h b/vendor/riscv/riscv-isa-sim/riscv/insns/srl32_u.h new file mode 100644 index 0000000000..d6375469e2 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/srl32_u.h @@ -0,0 +1,8 @@ +require_rv64; +P_X_ULOOP(32, 5, { + if (sa > 0) { + pd = (((uint64_t)(ps1 >> (sa - 1))) + 1) >> 1; + } else { + pd = ps1; + } +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/srl8.h b/vendor/riscv/riscv-isa-sim/riscv/insns/srl8.h new file mode 100644 index 0000000000..f7d74a9430 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/srl8.h @@ -0,0 +1,3 @@ +P_X_ULOOP(8, 3, { + pd = ps1 >> sa; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/srl8_u.h b/vendor/riscv/riscv-isa-sim/riscv/insns/srl8_u.h new file mode 100644 index 0000000000..26415a56ac --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/srl8_u.h @@ -0,0 +1,7 @@ +P_X_ULOOP(8, 3, { + if (sa > 0) { + pd = ((ps1 >> (sa - 1)) + 1) >> 1; + } else { + pd = ps1; + } +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/srli.h b/vendor/riscv/riscv-isa-sim/riscv/insns/srli.h new file mode 100644 index 0000000000..ea0b40d654 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/srli.h @@ -0,0 +1,2 @@ +require(SHAMT < xlen); +WRITE_RD(sext_xlen(zext_xlen(RS1) >> SHAMT)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/srli16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/srli16.h new file mode 100644 index 0000000000..cbd685ff57 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/srli16.h @@ -0,0 +1,3 @@ +P_I_ULOOP(16, 4, { + pd = ps1 >> imm4u; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/srli16_u.h b/vendor/riscv/riscv-isa-sim/riscv/insns/srli16_u.h new file mode 100644 index 0000000000..2ba533a310 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/srli16_u.h @@ -0,0 +1,7 @@ +P_I_ULOOP(16, 4, { + if (imm4u > 0) { + pd = ((ps1 >> (imm4u - 1)) + 1) >> 1; + } else { + pd = ps1; + } +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/srli32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/srli32.h new file mode 100644 index 0000000000..f3d53af4e0 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/srli32.h @@ -0,0 +1,4 @@ +require_rv64; +P_I_ULOOP(32, 5, { + pd = ps1 >> imm5u; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/srli32_u.h b/vendor/riscv/riscv-isa-sim/riscv/insns/srli32_u.h new file mode 100644 index 0000000000..6d2327fc32 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/srli32_u.h @@ -0,0 +1,8 @@ +require_rv64; +P_I_ULOOP(32, 5, { + if (imm5u > 0) { + pd = (((uint64_t)(ps1 >> (imm5u - 1))) + 1) >> 1; + } else { + pd = ps1; + } +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/srli8.h b/vendor/riscv/riscv-isa-sim/riscv/insns/srli8.h new file mode 100644 index 0000000000..103f0ed291 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/srli8.h @@ -0,0 +1,3 @@ +P_I_ULOOP(8, 3, { + pd = ps1 >> imm3u; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/srli8_u.h b/vendor/riscv/riscv-isa-sim/riscv/insns/srli8_u.h new file mode 100644 index 0000000000..9fa7f8c300 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/srli8_u.h @@ -0,0 +1,7 @@ +P_I_ULOOP(8, 3, { + if (imm3u > 0) { + pd = ((ps1 >> (imm3u - 1)) + 1) >> 1; + } else { + pd = ps1; + } +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/srliw.h b/vendor/riscv/riscv-isa-sim/riscv/insns/srliw.h new file mode 100644 index 0000000000..c657d3da8b --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/srliw.h @@ -0,0 +1,2 @@ +require_rv64; +WRITE_RD(sext32((uint32_t)RS1 >> SHAMT)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/srlw.h b/vendor/riscv/riscv-isa-sim/riscv/insns/srlw.h new file mode 100644 index 0000000000..a8eb451985 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/srlw.h @@ -0,0 +1,2 @@ +require_rv64; +WRITE_RD(sext32((uint32_t)RS1 >> (RS2 & 0x1F))); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sro.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sro.h new file mode 100644 index 0000000000..3ac050daff --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sro.h @@ -0,0 +1,2 @@ +require_extension(EXT_XZBP); +WRITE_RD(sext_xlen(~((zext_xlen(~RS1)) >> (RS2 & (xlen-1))))); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sroi.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sroi.h new file mode 100644 index 0000000000..e878892800 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sroi.h @@ -0,0 +1,3 @@ +require(SHAMT < xlen); +require_extension(EXT_XZBP); +WRITE_RD(sext_xlen(~((zext_xlen(~RS1)) >> SHAMT))); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sroiw.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sroiw.h new file mode 100644 index 0000000000..83480705fa --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sroiw.h @@ -0,0 +1,3 @@ +require_rv64; +require_extension(EXT_XZBP); +WRITE_RD(sext32(~((~(uint32_t)RS1) >> SHAMT))); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/srow.h b/vendor/riscv/riscv-isa-sim/riscv/insns/srow.h new file mode 100644 index 0000000000..808af8dbbe --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/srow.h @@ -0,0 +1,3 @@ +require_rv64; +require_extension(EXT_XZBP); +WRITE_RD(sext32(~((~(uint32_t)RS1) >> (RS2 & 0x1F)))); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/stas16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/stas16.h new file mode 100644 index 0000000000..949e5c8513 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/stas16.h @@ -0,0 +1,5 @@ +P_STRAIGHT_LOOP(16, { + pd = ps1 + ps2; +}, { + pd = ps1 - ps2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/stas32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/stas32.h new file mode 100644 index 0000000000..2009a69394 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/stas32.h @@ -0,0 +1,6 @@ +require_rv64; +P_STRAIGHT_LOOP(32, { + pd = ps1 + ps2; +}, { + pd = ps1 - ps2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/stsa16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/stsa16.h new file mode 100644 index 0000000000..7e4371d2b2 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/stsa16.h @@ -0,0 +1,5 @@ +P_STRAIGHT_LOOP(16, { + pd = ps1 - ps2; +}, { + pd = ps1 + ps2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/stsa32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/stsa32.h new file mode 100644 index 0000000000..e2d81b709a --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/stsa32.h @@ -0,0 +1,6 @@ +require_rv64; +P_STRAIGHT_LOOP(32, { + pd = ps1 - ps2; +}, { + pd = ps1 + ps2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sub.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sub.h new file mode 100644 index 0000000000..9ed48f7449 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sub.h @@ -0,0 +1 @@ +WRITE_RD(sext_xlen(RS1 - RS2)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sub16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sub16.h new file mode 100644 index 0000000000..5d36aaf4b5 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sub16.h @@ -0,0 +1,3 @@ +P_LOOP(16, { + pd = ps1 - ps2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sub32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sub32.h new file mode 100644 index 0000000000..70bbc53c98 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sub32.h @@ -0,0 +1,4 @@ +require_rv64; +P_LOOP(32, { + pd = ps1 - ps2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sub64.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sub64.h new file mode 100644 index 0000000000..d9775264bc --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sub64.h @@ -0,0 +1,3 @@ +P_64_PROFILE({ + rd = rs1 - rs2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sub8.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sub8.h new file mode 100644 index 0000000000..7f13d6159c --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sub8.h @@ -0,0 +1,3 @@ +P_LOOP(8, { + pd = ps1 - ps2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/subw.h b/vendor/riscv/riscv-isa-sim/riscv/insns/subw.h new file mode 100644 index 0000000000..b4168efe82 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/subw.h @@ -0,0 +1,3 @@ +require_rv64; +WRITE_RD(sext32(RS1 - RS2)); + diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sunpkd810.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sunpkd810.h new file mode 100644 index 0000000000..2a2f7c323a --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sunpkd810.h @@ -0,0 +1 @@ +P_SUNPKD8(1, 0) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sunpkd820.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sunpkd820.h new file mode 100644 index 0000000000..84d5248be5 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sunpkd820.h @@ -0,0 +1 @@ +P_SUNPKD8(2, 0) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sunpkd830.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sunpkd830.h new file mode 100644 index 0000000000..88179075fe --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sunpkd830.h @@ -0,0 +1 @@ +P_SUNPKD8(3, 0) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sunpkd831.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sunpkd831.h new file mode 100644 index 0000000000..98ed748d64 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sunpkd831.h @@ -0,0 +1 @@ +P_SUNPKD8(3, 1) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sunpkd832.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sunpkd832.h new file mode 100644 index 0000000000..b0ac29f9df --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sunpkd832.h @@ -0,0 +1 @@ +P_SUNPKD8(3, 2) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/sw.h b/vendor/riscv/riscv-isa-sim/riscv/insns/sw.h new file mode 100644 index 0000000000..a9d726895e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/sw.h @@ -0,0 +1 @@ +MMU.store<uint32_t>(RS1 + insn.s_imm(), RS2); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/uclip16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/uclip16.h new file mode 100644 index 0000000000..4cc2519081 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/uclip16.h @@ -0,0 +1,13 @@ +require_vector_vs; +P_I_LOOP(16, 4, { + int64_t uint_max = imm4u ? UINT64_MAX >> (64 - imm4u) : 0; + pd = ps1; + + if (ps1 > uint_max) { + pd = uint_max; + P_SET_OV(1); + } else if (ps1 < 0) { + pd = 0; + P_SET_OV(1); + } +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/uclip32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/uclip32.h new file mode 100644 index 0000000000..d347650c36 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/uclip32.h @@ -0,0 +1,13 @@ +require_vector_vs; +P_I_LOOP(32, 5, { + int64_t uint_max = imm5u ? UINT64_MAX >> (64 - imm5u) : 0; + pd = ps1; + + if (ps1 > uint_max) { + pd = uint_max; + P_SET_OV(1); + } else if (ps1 < 0) { + pd = 0; + P_SET_OV(1); + } +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/uclip8.h b/vendor/riscv/riscv-isa-sim/riscv/insns/uclip8.h new file mode 100644 index 0000000000..b8a95c0758 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/uclip8.h @@ -0,0 +1,13 @@ +require_vector_vs; +P_I_LOOP(8, 3, { + int64_t uint_max = imm3u ? UINT64_MAX >> (64 - imm3u) : 0; + pd = ps1; + + if (ps1 > uint_max) { + pd = uint_max; + P_SET_OV(1); + } else if (ps1 < 0) { + pd = 0; + P_SET_OV(1); + } +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/ucmple16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/ucmple16.h new file mode 100644 index 0000000000..fe2b93fba3 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/ucmple16.h @@ -0,0 +1,3 @@ +P_ULOOP(16, { + pd = (ps1 <= ps2) ? -1 : 0; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/ucmple8.h b/vendor/riscv/riscv-isa-sim/riscv/insns/ucmple8.h new file mode 100644 index 0000000000..bd44cb0e00 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/ucmple8.h @@ -0,0 +1,3 @@ +P_ULOOP(8, { + pd = (ps1 <= ps2) ? -1 : 0; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/ucmplt16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/ucmplt16.h new file mode 100644 index 0000000000..fa7512c338 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/ucmplt16.h @@ -0,0 +1,3 @@ +P_ULOOP(16, { + pd = (ps1 < ps2) ? -1 : 0; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/ucmplt8.h b/vendor/riscv/riscv-isa-sim/riscv/insns/ucmplt8.h new file mode 100644 index 0000000000..6fa85b1a8e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/ucmplt8.h @@ -0,0 +1,3 @@ +P_ULOOP(8, { + pd = (ps1 < ps2) ? -1 : 0; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/ukadd16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/ukadd16.h new file mode 100644 index 0000000000..680b5b63e9 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/ukadd16.h @@ -0,0 +1,6 @@ +require_vector_vs; +P_ULOOP(16, { + bool sat = false; + pd = (sat_addu<uint16_t>(ps1, ps2, sat)); + P_SET_OV(sat); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/ukadd32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/ukadd32.h new file mode 100644 index 0000000000..dd836c1e37 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/ukadd32.h @@ -0,0 +1,7 @@ +require_vector_vs; +require_rv64; +P_ULOOP(32, { + bool sat = false; + pd = (sat_addu<uint32_t>(ps1, ps2, sat)); + P_SET_OV(sat); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/ukadd64.h b/vendor/riscv/riscv-isa-sim/riscv/insns/ukadd64.h new file mode 100644 index 0000000000..d7e98f3432 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/ukadd64.h @@ -0,0 +1,6 @@ +require_vector_vs; +P_64_UPROFILE({ + bool sat = false; + rd = (sat_addu<uint64_t>(rs1, rs2, sat)); + P_SET_OV(sat); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/ukadd8.h b/vendor/riscv/riscv-isa-sim/riscv/insns/ukadd8.h new file mode 100644 index 0000000000..4bcada20e3 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/ukadd8.h @@ -0,0 +1,6 @@ +require_vector_vs; +P_ULOOP(8, { + bool sat = false; + pd = (sat_addu<uint8_t>(ps1, ps2, sat)); + P_SET_OV(sat); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/ukaddh.h b/vendor/riscv/riscv-isa-sim/riscv/insns/ukaddh.h new file mode 100644 index 0000000000..30c970a3fd --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/ukaddh.h @@ -0,0 +1,5 @@ +require_vector_vs; +require_extension(EXT_ZPN); +sreg_t res = (sreg_t)P_H(RS1, 0) + (sreg_t)P_H(RS2, 0); +P_SATU(res, 16); +WRITE_RD(sext_xlen((int16_t)res)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/ukaddw.h b/vendor/riscv/riscv-isa-sim/riscv/insns/ukaddw.h new file mode 100644 index 0000000000..5d4d91efca --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/ukaddw.h @@ -0,0 +1,5 @@ +require_vector_vs; +require_extension(EXT_ZPN); +sreg_t res = (sreg_t)P_W(RS1, 0) + (sreg_t)P_W(RS2, 0); +P_SATU(res, 32); +WRITE_RD(sext32(res)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/ukcras16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/ukcras16.h new file mode 100644 index 0000000000..54b9a10433 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/ukcras16.h @@ -0,0 +1,10 @@ +require_vector_vs; +P_CROSS_ULOOP(16, { + bool sat = false; + pd = (sat_addu<uint16_t>(ps1, ps2, sat)); + P_SET_OV(sat); +}, { + bool sat = false; + pd = (sat_subu<uint16_t>(ps1, ps2, sat)); + P_SET_OV(sat); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/ukcras32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/ukcras32.h new file mode 100644 index 0000000000..001644c282 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/ukcras32.h @@ -0,0 +1,11 @@ +require_vector_vs; +require_rv64; +P_CROSS_ULOOP(32, { + bool sat = false; + pd = (sat_addu<uint32_t>(ps1, ps2, sat)); + P_SET_OV(sat); +}, { + bool sat = false; + pd = (sat_subu<uint32_t>(ps1, ps2, sat)); + P_SET_OV(sat); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/ukcrsa16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/ukcrsa16.h new file mode 100644 index 0000000000..343063ce72 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/ukcrsa16.h @@ -0,0 +1,10 @@ +require_vector_vs; +P_CROSS_ULOOP(16, { + bool sat = false; + pd = (sat_subu<uint16_t>(ps1, ps2, sat)); + P_SET_OV(sat); +}, { + bool sat = false; + pd = (sat_addu<uint16_t>(ps1, ps2, sat)); + P_SET_OV(sat); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/ukcrsa32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/ukcrsa32.h new file mode 100644 index 0000000000..260f181e65 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/ukcrsa32.h @@ -0,0 +1,11 @@ +require_vector_vs; +require_rv64; +P_CROSS_ULOOP(32, { + bool sat = false; + pd = (sat_subu<uint32_t>(ps1, ps2, sat)); + P_SET_OV(sat); +}, { + bool sat = false; + pd = (sat_addu<uint32_t>(ps1, ps2, sat)); + P_SET_OV(sat); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/ukmar64.h b/vendor/riscv/riscv-isa-sim/riscv/insns/ukmar64.h new file mode 100644 index 0000000000..e33ad7d8bd --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/ukmar64.h @@ -0,0 +1,6 @@ +require_vector_vs; +P_64_UPROFILE_REDUCTION(32, { + bool sat = false; + rd = (sat_addu<uint64_t>(rd, ps1 * ps2, sat)); + P_SET_OV(sat); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/ukmsr64.h b/vendor/riscv/riscv-isa-sim/riscv/insns/ukmsr64.h new file mode 100644 index 0000000000..9a38cb07bb --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/ukmsr64.h @@ -0,0 +1,6 @@ +require_vector_vs; +P_64_UPROFILE_REDUCTION(32, { + bool sat = false; + rd = (sat_subu<uint64_t>(rd, ps1 * ps2, sat)); + P_SET_OV(sat); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/ukstas16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/ukstas16.h new file mode 100644 index 0000000000..a8203e4314 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/ukstas16.h @@ -0,0 +1,10 @@ +require_vector_vs; +P_STRAIGHT_ULOOP(16, { + bool sat = false; + pd = (sat_addu<uint16_t>(ps1, ps2, sat)); + P_SET_OV(sat); +}, { + bool sat = false; + pd = (sat_subu<uint16_t>(ps1, ps2, sat)); + P_SET_OV(sat); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/ukstas32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/ukstas32.h new file mode 100644 index 0000000000..c734eb6c17 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/ukstas32.h @@ -0,0 +1,11 @@ +require_vector_vs; +require_rv64; +P_STRAIGHT_ULOOP(32, { + bool sat = false; + pd = (sat_addu<uint32_t>(ps1, ps2, sat)); + P_SET_OV(sat); +}, { + bool sat = false; + pd = (sat_subu<uint32_t>(ps1, ps2, sat)); + P_SET_OV(sat); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/ukstsa16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/ukstsa16.h new file mode 100644 index 0000000000..8145111209 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/ukstsa16.h @@ -0,0 +1,10 @@ +require_vector_vs; +P_STRAIGHT_ULOOP(16, { + bool sat = false; + pd = (sat_subu<uint16_t>(ps1, ps2, sat)); + P_SET_OV(sat); +}, { + bool sat = false; + pd = (sat_addu<uint16_t>(ps1, ps2, sat)); + P_SET_OV(sat); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/ukstsa32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/ukstsa32.h new file mode 100644 index 0000000000..9eb713ec21 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/ukstsa32.h @@ -0,0 +1,11 @@ +require_vector_vs; +require_rv64; +P_STRAIGHT_ULOOP(32, { + bool sat = false; + pd = (sat_subu<uint32_t>(ps1, ps2, sat)); + P_SET_OV(sat); +}, { + bool sat = false; + pd = (sat_addu<uint32_t>(ps1, ps2, sat)); + P_SET_OV(sat); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/uksub16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/uksub16.h new file mode 100644 index 0000000000..7fba16e974 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/uksub16.h @@ -0,0 +1,6 @@ +require_vector_vs; +P_ULOOP(16, { + bool sat = false; + pd = (sat_subu<uint16_t>(ps1, ps2, sat)); + P_SET_OV(sat); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/uksub32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/uksub32.h new file mode 100644 index 0000000000..3d4913bb43 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/uksub32.h @@ -0,0 +1,7 @@ +require_vector_vs; +require_rv64; +P_ULOOP(32, { + bool sat = false; + pd = (sat_subu<uint32_t>(ps1, ps2, sat)); + P_SET_OV(sat); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/uksub64.h b/vendor/riscv/riscv-isa-sim/riscv/insns/uksub64.h new file mode 100644 index 0000000000..0d2bb05052 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/uksub64.h @@ -0,0 +1,6 @@ +require_vector_vs; +P_64_UPROFILE({ + bool sat = false; + rd = (sat_subu<uint64_t>(rs1, rs2, sat)); + P_SET_OV(sat); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/uksub8.h b/vendor/riscv/riscv-isa-sim/riscv/insns/uksub8.h new file mode 100644 index 0000000000..f26621e7a8 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/uksub8.h @@ -0,0 +1,6 @@ +require_vector_vs; +P_ULOOP(8, { + bool sat = false; + pd = (sat_subu<uint8_t>(ps1, ps2, sat)); + P_SET_OV(sat); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/uksubh.h b/vendor/riscv/riscv-isa-sim/riscv/insns/uksubh.h new file mode 100644 index 0000000000..ac239895c6 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/uksubh.h @@ -0,0 +1,5 @@ +require_vector_vs; +require_extension(EXT_ZPN); +sreg_t res = (sreg_t)P_H(RS1, 0) - (sreg_t)P_H(RS2, 0); +P_SATU(res, 16); +WRITE_RD(sext_xlen((int16_t)res)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/uksubw.h b/vendor/riscv/riscv-isa-sim/riscv/insns/uksubw.h new file mode 100644 index 0000000000..41a32e7062 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/uksubw.h @@ -0,0 +1,5 @@ +require_vector_vs; +require_extension(EXT_ZPN); +sreg_t res = (sreg_t)P_W(RS1, 0) - (sreg_t)P_W(RS2, 0); +P_SATU(res, 32); +WRITE_RD(sext32(res)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/umaqa.h b/vendor/riscv/riscv-isa-sim/riscv/insns/umaqa.h new file mode 100644 index 0000000000..474b174aaf --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/umaqa.h @@ -0,0 +1,3 @@ +P_REDUCTION_ULOOP(32, 8, true, false, { + pd_res += ps1 * ps2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/umar64.h b/vendor/riscv/riscv-isa-sim/riscv/insns/umar64.h new file mode 100644 index 0000000000..0a8a352487 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/umar64.h @@ -0,0 +1,3 @@ +P_64_UPROFILE_REDUCTION(32, { + rd += ps1 * ps2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/umax16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/umax16.h new file mode 100644 index 0000000000..e60ed4ac18 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/umax16.h @@ -0,0 +1,3 @@ +P_ULOOP(16, { + pd = (ps1 > ps2) ? ps1 : ps2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/umax32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/umax32.h new file mode 100644 index 0000000000..6156345cd6 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/umax32.h @@ -0,0 +1,4 @@ +require_rv64; +P_ULOOP(32, { + pd = (ps1 > ps2) ? ps1 : ps2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/umax8.h b/vendor/riscv/riscv-isa-sim/riscv/insns/umax8.h new file mode 100644 index 0000000000..8a575a6893 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/umax8.h @@ -0,0 +1,3 @@ +P_ULOOP(8, { + pd = (ps1 > ps2) ? ps1 : ps2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/umin16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/umin16.h new file mode 100644 index 0000000000..d4142118f5 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/umin16.h @@ -0,0 +1,3 @@ +P_ULOOP(16, { + pd = (ps1 < ps2) ? ps1 : ps2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/umin32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/umin32.h new file mode 100644 index 0000000000..966994522e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/umin32.h @@ -0,0 +1,4 @@ +require_rv64; +P_ULOOP(32, { + pd = (ps1 < ps2) ? ps1 : ps2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/umin8.h b/vendor/riscv/riscv-isa-sim/riscv/insns/umin8.h new file mode 100644 index 0000000000..bea8ccd222 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/umin8.h @@ -0,0 +1,3 @@ +P_ULOOP(8, { + pd = (ps1 < ps2) ? ps1 : ps2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/umsr64.h b/vendor/riscv/riscv-isa-sim/riscv/insns/umsr64.h new file mode 100644 index 0000000000..0e186d96a1 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/umsr64.h @@ -0,0 +1,3 @@ +P_64_UPROFILE_REDUCTION(32, { + rd -= ps1 * ps2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/umul16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/umul16.h new file mode 100644 index 0000000000..09b839ca90 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/umul16.h @@ -0,0 +1,3 @@ +P_MUL_ULOOP(16, { + pd = (uint32_t)ps1 * (uint32_t)ps2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/umul8.h b/vendor/riscv/riscv-isa-sim/riscv/insns/umul8.h new file mode 100644 index 0000000000..29cae88500 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/umul8.h @@ -0,0 +1,3 @@ +P_MUL_ULOOP(8, { + pd = (uint16_t)ps1 * (uint16_t)ps2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/umulx16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/umulx16.h new file mode 100644 index 0000000000..3f0cce8ba7 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/umulx16.h @@ -0,0 +1,3 @@ +P_MUL_CROSS_ULOOP(16, { + pd = (uint32_t)ps1 * (uint32_t)ps2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/umulx8.h b/vendor/riscv/riscv-isa-sim/riscv/insns/umulx8.h new file mode 100644 index 0000000000..848b5d588d --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/umulx8.h @@ -0,0 +1,3 @@ +P_MUL_CROSS_ULOOP(8, { + pd = (uint16_t)ps1 * (uint16_t)ps2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/unshfl.h b/vendor/riscv/riscv-isa-sim/riscv/insns/unshfl.h new file mode 100644 index 0000000000..78990b876f --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/unshfl.h @@ -0,0 +1,9 @@ +require_extension(EXT_XZBP); +reg_t x = RS1; +int shamt = RS2 & ((xlen-1) >> 1); +if (shamt & 1) x = (x & 0x9999999999999999LL) | ((x & 0x4444444444444444LL) >> 1) | ((x & 0x2222222222222222LL) << 1); +if (shamt & 2) x = (x & 0xC3C3C3C3C3C3C3C3LL) | ((x & 0x3030303030303030LL) >> 2) | ((x & 0x0C0C0C0C0C0C0C0CLL) << 2); +if (shamt & 4) x = (x & 0xF00FF00FF00FF00FLL) | ((x & 0x0F000F000F000F00LL) >> 4) | ((x & 0x00F000F000F000F0LL) << 4); +if (shamt & 8) x = (x & 0xFF0000FFFF0000FFLL) | ((x & 0x00FF000000FF0000LL) >> 8) | ((x & 0x0000FF000000FF00LL) << 8); +if (shamt & 16) x = (x & 0xFFFF00000000FFFFLL) | ((x & 0x0000FFFF00000000LL) >> 16) | ((x & 0x00000000FFFF0000LL) << 16); +WRITE_RD(sext_xlen(x)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/unshfli.h b/vendor/riscv/riscv-isa-sim/riscv/insns/unshfli.h new file mode 100644 index 0000000000..26920f1403 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/unshfli.h @@ -0,0 +1,12 @@ +// Zbkb contains unzip but not general unshfli +require(((insn.rs2() == (xlen / 2 - 1)) && p->extension_enabled(EXT_ZBKB)) + || p->extension_enabled(EXT_XZBP)); +require(SHAMT < (xlen/2)); +reg_t x = RS1; +int shamt = SHAMT & ((xlen-1) >> 1); +if (shamt & 1) x = (x & 0x9999999999999999LL) | ((x & 0x4444444444444444LL) >> 1) | ((x & 0x2222222222222222LL) << 1); +if (shamt & 2) x = (x & 0xC3C3C3C3C3C3C3C3LL) | ((x & 0x3030303030303030LL) >> 2) | ((x & 0x0C0C0C0C0C0C0C0CLL) << 2); +if (shamt & 4) x = (x & 0xF00FF00FF00FF00FLL) | ((x & 0x0F000F000F000F00LL) >> 4) | ((x & 0x00F000F000F000F0LL) << 4); +if (shamt & 8) x = (x & 0xFF0000FFFF0000FFLL) | ((x & 0x00FF000000FF0000LL) >> 8) | ((x & 0x0000FF000000FF00LL) << 8); +if (shamt & 16) x = (x & 0xFFFF00000000FFFFLL) | ((x & 0x0000FFFF00000000LL) >> 16) | ((x & 0x00000000FFFF0000LL) << 16); +WRITE_RD(sext_xlen(x)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/unshflw.h b/vendor/riscv/riscv-isa-sim/riscv/insns/unshflw.h new file mode 100644 index 0000000000..776534e742 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/unshflw.h @@ -0,0 +1,9 @@ +require_rv64; +require_extension(EXT_XZBP); +reg_t x = RS1; +int shamt = RS2 & 15; +if (shamt & 1) x = (x & 0x9999999999999999LL) | ((x & 0x4444444444444444LL) >> 1) | ((x & 0x2222222222222222LL) << 1); +if (shamt & 2) x = (x & 0xC3C3C3C3C3C3C3C3LL) | ((x & 0x3030303030303030LL) >> 2) | ((x & 0x0C0C0C0C0C0C0C0CLL) << 2); +if (shamt & 4) x = (x & 0xF00FF00FF00FF00FLL) | ((x & 0x0F000F000F000F00LL) >> 4) | ((x & 0x00F000F000F000F0LL) << 4); +if (shamt & 8) x = (x & 0xFF0000FFFF0000FFLL) | ((x & 0x00FF000000FF0000LL) >> 8) | ((x & 0x0000FF000000FF00LL) << 8); +WRITE_RD(sext32(x)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/uradd16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/uradd16.h new file mode 100644 index 0000000000..29610bf475 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/uradd16.h @@ -0,0 +1,3 @@ +P_ULOOP(16, { + pd = (ps1 + ps2) >> 1; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/uradd32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/uradd32.h new file mode 100644 index 0000000000..4f791d9172 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/uradd32.h @@ -0,0 +1,4 @@ +require_rv64; +P_ULOOP(32, { + pd = ((uint64_t)ps1 + ps2) >> 1; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/uradd64.h b/vendor/riscv/riscv-isa-sim/riscv/insns/uradd64.h new file mode 100644 index 0000000000..f6787e16d4 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/uradd64.h @@ -0,0 +1,9 @@ +P_64_UPROFILE({ + rd = rs1 + rs2; + if (rd < rs1) { + rd >>= 1; + rd |= ((reg_t)1 << 63); + } else { + rd >>= 1; + } +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/uradd8.h b/vendor/riscv/riscv-isa-sim/riscv/insns/uradd8.h new file mode 100644 index 0000000000..412e3d59d4 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/uradd8.h @@ -0,0 +1,3 @@ +P_ULOOP(8, { + pd = (ps1 + ps2) >> 1; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/uraddw.h b/vendor/riscv/riscv-isa-sim/riscv/insns/uraddw.h new file mode 100644 index 0000000000..6a9455fcac --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/uraddw.h @@ -0,0 +1,4 @@ +require_extension(EXT_ZPN); +reg_t res = (reg_t)P_W(RS1, 0) + (reg_t)P_W(RS2, 0); +res >>= 1; +WRITE_RD(sext_xlen((int32_t)res)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/urcras16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/urcras16.h new file mode 100644 index 0000000000..2bac31561f --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/urcras16.h @@ -0,0 +1,5 @@ +P_CROSS_ULOOP(16, { + pd = (ps1 + ps2) >> 1; +}, { + pd = (ps1 - ps2) >> 1; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/urcras32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/urcras32.h new file mode 100644 index 0000000000..a08e8777be --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/urcras32.h @@ -0,0 +1,6 @@ +require_rv64; +P_CROSS_ULOOP(32, { + pd = ((uint64_t)ps1 + ps2) >> 1; +}, { + pd = ((uint64_t)ps1 - ps2) >> 1; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/urcrsa16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/urcrsa16.h new file mode 100644 index 0000000000..a890990a1f --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/urcrsa16.h @@ -0,0 +1,5 @@ +P_CROSS_ULOOP(16, { + pd = (ps1 - ps2) >> 1; +}, { + pd = (ps1 + ps2) >> 1; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/urcrsa32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/urcrsa32.h new file mode 100644 index 0000000000..7ddd4f9577 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/urcrsa32.h @@ -0,0 +1,6 @@ +require_rv64; +P_CROSS_ULOOP(32, { + pd = ((uint64_t)ps1 - ps2) >> 1; +}, { + pd = ((uint64_t)ps1 + ps2) >> 1; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/urstas16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/urstas16.h new file mode 100644 index 0000000000..3cc89d81ac --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/urstas16.h @@ -0,0 +1,5 @@ +P_STRAIGHT_ULOOP(16, { + pd = (ps1 + ps2) >> 1; +}, { + pd = (ps1 - ps2) >> 1; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/urstas32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/urstas32.h new file mode 100644 index 0000000000..668fa66a49 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/urstas32.h @@ -0,0 +1,6 @@ +require_rv64; +P_STRAIGHT_ULOOP(32, { + pd = ((uint64_t)ps1 + ps2) >> 1; +}, { + pd = ((uint64_t)ps1 - ps2) >> 1; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/urstsa16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/urstsa16.h new file mode 100644 index 0000000000..a88bcf13f8 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/urstsa16.h @@ -0,0 +1,5 @@ +P_STRAIGHT_ULOOP(16, { + pd = (ps1 - ps2) >> 1; +}, { + pd = (ps1 + ps2) >> 1; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/urstsa32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/urstsa32.h new file mode 100644 index 0000000000..097337ce33 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/urstsa32.h @@ -0,0 +1,6 @@ +require_rv64; +P_STRAIGHT_ULOOP(32, { + pd = ((uint64_t)ps1 - ps2) >> 1; +}, { + pd = ((uint64_t)ps1 + ps2) >> 1; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/ursub16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/ursub16.h new file mode 100644 index 0000000000..bcd09f0294 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/ursub16.h @@ -0,0 +1,3 @@ +P_ULOOP(16, { + pd = (ps1 - ps2) >> 1; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/ursub32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/ursub32.h new file mode 100644 index 0000000000..215436d013 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/ursub32.h @@ -0,0 +1,4 @@ +require_rv64; +P_ULOOP(32, { + pd = ((uint64_t)ps1 - ps2) >> 1; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/ursub64.h b/vendor/riscv/riscv-isa-sim/riscv/insns/ursub64.h new file mode 100644 index 0000000000..3d845a0c69 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/ursub64.h @@ -0,0 +1,9 @@ +P_64_UPROFILE({ + rd = rs1 - rs2; + if (rd > rs1) { + rd >>= 1; + rd |= ((reg_t)1 << 63); + } else { + rd >>= 1; + } +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/ursub8.h b/vendor/riscv/riscv-isa-sim/riscv/insns/ursub8.h new file mode 100644 index 0000000000..d66a9957ee --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/ursub8.h @@ -0,0 +1,3 @@ +P_ULOOP(8, { + pd = (ps1 - ps2) >> 1; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/ursubw.h b/vendor/riscv/riscv-isa-sim/riscv/insns/ursubw.h new file mode 100644 index 0000000000..5c90fde44f --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/ursubw.h @@ -0,0 +1,4 @@ +require_extension(EXT_ZPN); +reg_t res = (reg_t)P_W(RS1, 0) - (reg_t)P_W(RS2, 0); +res >>= 1; +WRITE_RD(sext_xlen((int32_t)res)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vaadd_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vaadd_vv.h new file mode 100644 index 0000000000..0e7e39b468 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vaadd_vv.h @@ -0,0 +1,2 @@ +// vaadd.vv vd, vs2, vs1 +VI_VV_LOOP_AVG(+); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vaadd_vx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vaadd_vx.h new file mode 100644 index 0000000000..120e63ebb3 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vaadd_vx.h @@ -0,0 +1,2 @@ +// vaadd.vx vd, vs2, rs1 +VI_VX_LOOP_AVG(+); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vaaddu_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vaaddu_vv.h new file mode 100644 index 0000000000..7eb7a895e9 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vaaddu_vv.h @@ -0,0 +1,2 @@ +// vaaddu.vv vd, vs2, vs1 +VI_VV_ULOOP_AVG(+); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vaaddu_vx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vaaddu_vx.h new file mode 100644 index 0000000000..325206f9d7 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vaaddu_vx.h @@ -0,0 +1,2 @@ +// vaaddu.vx vd, vs2, rs1 +VI_VX_ULOOP_AVG(+); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vadc_vim.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vadc_vim.h new file mode 100644 index 0000000000..4b0356f29c --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vadc_vim.h @@ -0,0 +1,5 @@ +// vadc.vim vd, vs2, simm5, v0 +VI_XI_LOOP_WITH_CARRY +({ + vd = (uint128_t)((op_mask & simm5) + (op_mask & vs2) + carry); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vadc_vvm.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vadc_vvm.h new file mode 100644 index 0000000000..7b41dd9f7b --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vadc_vvm.h @@ -0,0 +1,5 @@ +// vadc.vvm vd, vs2, rs1, v0 +VI_VV_LOOP_WITH_CARRY +({ + vd = (uint128_t)((op_mask & vs1) + (op_mask & vs2) + carry); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vadc_vxm.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vadc_vxm.h new file mode 100644 index 0000000000..b1f8886dcf --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vadc_vxm.h @@ -0,0 +1,5 @@ +// vadc.vxm vd, vs2, rs1, v0 +VI_XI_LOOP_WITH_CARRY +({ + vd = (uint128_t)((op_mask & rs1) + (op_mask & vs2) + carry); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vadd_vi.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vadd_vi.h new file mode 100644 index 0000000000..45fc6b74e7 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vadd_vi.h @@ -0,0 +1,5 @@ +// vadd.vi vd, simm5, vs2, vm +VI_VI_LOOP +({ + vd = simm5 + vs2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vadd_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vadd_vv.h new file mode 100644 index 0000000000..45c6bdcba7 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vadd_vv.h @@ -0,0 +1,5 @@ +// vadd.vv vd, vs1, vs2, vm +VI_VV_LOOP +({ + vd = vs1 + vs2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vadd_vx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vadd_vx.h new file mode 100644 index 0000000000..33e72ee495 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vadd_vx.h @@ -0,0 +1,5 @@ +// vadd.vx vd, rs1, vs2, vm +VI_VX_LOOP +({ + vd = rs1 + vs2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vamoaddei16_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vamoaddei16_v.h new file mode 100644 index 0000000000..3cb3db709d --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vamoaddei16_v.h @@ -0,0 +1,2 @@ +//vamoadde.v vd, (rs1), vs2, vd +VI_AMO({ return lhs + vs3; }, uint, e16); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vamoaddei32_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vamoaddei32_v.h new file mode 100644 index 0000000000..2bd77fcbd2 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vamoaddei32_v.h @@ -0,0 +1,2 @@ +//vamoadde.v vd, (rs1), vs2, vd +VI_AMO({ return lhs + vs3; }, uint, e32); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vamoaddei64_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vamoaddei64_v.h new file mode 100644 index 0000000000..79ca748205 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vamoaddei64_v.h @@ -0,0 +1,2 @@ +//vamoadde.v vd, (rs1), vs2, vd +VI_AMO({ return lhs + vs3; }, uint, e64); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vamoaddei8_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vamoaddei8_v.h new file mode 100644 index 0000000000..06b8c79302 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vamoaddei8_v.h @@ -0,0 +1,2 @@ +//vamoadde.v vd, (rs1), vs2, vd +VI_AMO({ return lhs + vs3; }, uint, e8); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vamoandei16_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vamoandei16_v.h new file mode 100644 index 0000000000..be119497f3 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vamoandei16_v.h @@ -0,0 +1,2 @@ +//vamoande.v vd, (rs1), vs2, vd +VI_AMO({ return lhs & vs3; }, uint, e16); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vamoandei32_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vamoandei32_v.h new file mode 100644 index 0000000000..71506704ff --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vamoandei32_v.h @@ -0,0 +1,2 @@ +//vamoande.v vd, (rs1), vs2, vd +VI_AMO({ return lhs & vs3; }, uint, e32); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vamoandei64_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vamoandei64_v.h new file mode 100644 index 0000000000..3efae3b59f --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vamoandei64_v.h @@ -0,0 +1,2 @@ +//vamoande.v vd, (rs1), vs2, vd +VI_AMO({ return lhs & vs3; }, uint, e64); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vamoandei8_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vamoandei8_v.h new file mode 100644 index 0000000000..c47645d3e0 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vamoandei8_v.h @@ -0,0 +1,2 @@ +//vamoande.v vd, (rs1), vs2, vd +VI_AMO({ return lhs & vs3; }, uint, e8); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vamomaxei16_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vamomaxei16_v.h new file mode 100644 index 0000000000..ca67893e99 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vamomaxei16_v.h @@ -0,0 +1,2 @@ +//vamomaxe.v vd, (rs1), vs2, vd +VI_AMO({ return lhs >= vs3 ? lhs : vs3; }, int, e16); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vamomaxei32_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vamomaxei32_v.h new file mode 100644 index 0000000000..b6823cd042 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vamomaxei32_v.h @@ -0,0 +1,2 @@ +//vamomaxe.v vd, (rs1), vs2, vd +VI_AMO({ return lhs >= vs3 ? lhs : vs3; }, int, e32); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vamomaxei64_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vamomaxei64_v.h new file mode 100644 index 0000000000..46e8a3bbd1 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vamomaxei64_v.h @@ -0,0 +1,2 @@ +//vamomaxe.v vd, (rs1), vs2, vd +VI_AMO({ return lhs >= vs3 ? lhs : vs3; }, int, e64); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vamomaxei8_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vamomaxei8_v.h new file mode 100644 index 0000000000..9697b3a4cb --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vamomaxei8_v.h @@ -0,0 +1,2 @@ +//vamomaxe.v vd, (rs1), vs2, vd +VI_AMO({ return lhs >= vs3 ? lhs : vs3; }, int, e8); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vamomaxuei16_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vamomaxuei16_v.h new file mode 100644 index 0000000000..e05971dfcf --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vamomaxuei16_v.h @@ -0,0 +1,2 @@ +//vamomaxue.v vd, (rs1), vs2, vd +VI_AMO({ return lhs >= vs3 ? lhs : vs3;; }, uint, e16); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vamomaxuei32_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vamomaxuei32_v.h new file mode 100644 index 0000000000..9b873543b9 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vamomaxuei32_v.h @@ -0,0 +1,2 @@ +//vamomaxue.v vd, (rs1), vs2, vd +VI_AMO({ return lhs >= vs3 ? lhs : vs3;; }, uint, e32); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vamomaxuei64_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vamomaxuei64_v.h new file mode 100644 index 0000000000..bbfbc9f2a3 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vamomaxuei64_v.h @@ -0,0 +1,2 @@ +//vamomaxue.v vd, (rs1), vs2, vd +VI_AMO({ return lhs >= vs3 ? lhs : vs3;; }, uint, e64); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vamomaxuei8_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vamomaxuei8_v.h new file mode 100644 index 0000000000..357ba2454a --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vamomaxuei8_v.h @@ -0,0 +1,2 @@ +//vamomaxue.v vd, (rs1), vs2, vd +VI_AMO({ return lhs >= vs3 ? lhs : vs3;; }, uint, e8); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vamominei16_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vamominei16_v.h new file mode 100644 index 0000000000..9d1ecac643 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vamominei16_v.h @@ -0,0 +1,2 @@ +//vamomine.v vd, (rs1), vs2, vd +VI_AMO({ return lhs < vs3 ? lhs : vs3; }, int, e16); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vamominei32_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vamominei32_v.h new file mode 100644 index 0000000000..6cb8475e39 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vamominei32_v.h @@ -0,0 +1,2 @@ +//vamomine.v vd, (rs1), vs2, vd +VI_AMO({ return lhs < vs3 ? lhs : vs3; }, int, e32); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vamominei64_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vamominei64_v.h new file mode 100644 index 0000000000..9ef3d4ee3b --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vamominei64_v.h @@ -0,0 +1,2 @@ +//vamomine.v vd, (rs1), vs2, vd +VI_AMO({ return lhs < vs3 ? lhs : vs3; }, int, e64); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vamominei8_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vamominei8_v.h new file mode 100644 index 0000000000..5c035ea47b --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vamominei8_v.h @@ -0,0 +1,2 @@ +//vamomine.v vd, (rs1), vs2, vd +VI_AMO({ return lhs < vs3 ? lhs : vs3; }, int, e8); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vamominuei16_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vamominuei16_v.h new file mode 100644 index 0000000000..d4a8f89292 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vamominuei16_v.h @@ -0,0 +1,2 @@ +//vamominue.v vd, (rs1), vs2, vd +VI_AMO({ return lhs < vs3 ? lhs : vs3;; }, uint, e16); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vamominuei32_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vamominuei32_v.h new file mode 100644 index 0000000000..16296c5beb --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vamominuei32_v.h @@ -0,0 +1,2 @@ +//vamominue.v vd, (rs1), vs2, vd +VI_AMO({ return lhs < vs3 ? lhs : vs3;; }, uint, e32); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vamominuei64_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vamominuei64_v.h new file mode 100644 index 0000000000..fd850fd063 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vamominuei64_v.h @@ -0,0 +1,2 @@ +//vamominue.v vd, (rs1), vs2, vd +VI_AMO({ return lhs < vs3 ? lhs : vs3;; }, uint, e64); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vamominuei8_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vamominuei8_v.h new file mode 100644 index 0000000000..3749d0525d --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vamominuei8_v.h @@ -0,0 +1,2 @@ +//vamominue.v vd, (rs1), vs2, vd +VI_AMO({ return lhs < vs3 ? lhs : vs3;; }, uint, e8); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vamoorei16_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vamoorei16_v.h new file mode 100644 index 0000000000..a5ba1caa74 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vamoorei16_v.h @@ -0,0 +1,2 @@ +//vamoore.v vd, (rs1), vs2, vd +VI_AMO({ return lhs | vs3; }, uint, e16); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vamoorei32_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vamoorei32_v.h new file mode 100644 index 0000000000..94e4458e49 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vamoorei32_v.h @@ -0,0 +1,2 @@ +//vamoore.v vd, (rs1), vs2, vd +VI_AMO({ return lhs | vs3; }, uint, e32); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vamoorei64_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vamoorei64_v.h new file mode 100644 index 0000000000..84e03944e5 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vamoorei64_v.h @@ -0,0 +1,2 @@ +//vamoore.v vd, (rs1), vs2, vd +VI_AMO({ return lhs | vs3; }, uint, e64); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vamoorei8_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vamoorei8_v.h new file mode 100644 index 0000000000..364035dbb2 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vamoorei8_v.h @@ -0,0 +1,2 @@ +//vamoore.v vd, (rs1), vs2, vd +VI_AMO({ return lhs | vs3; }, uint, e8); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vamoswapei16_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vamoswapei16_v.h new file mode 100644 index 0000000000..31ff021030 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vamoswapei16_v.h @@ -0,0 +1,2 @@ +//vamoswape.v vd, (rs1), vs2, vd +VI_AMO({ return vs3; }, uint, e16); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vamoswapei32_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vamoswapei32_v.h new file mode 100644 index 0000000000..a5741929ab --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vamoswapei32_v.h @@ -0,0 +1,2 @@ +//vamoswape.v vd, (rs1), vs2, vd +VI_AMO({ return vs3; }, uint, e32); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vamoswapei64_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vamoswapei64_v.h new file mode 100644 index 0000000000..58bd035217 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vamoswapei64_v.h @@ -0,0 +1,2 @@ +//vamoswape.v vd, (rs1), vs2, vd +VI_AMO({ return vs3; }, uint, e64); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vamoswapei8_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vamoswapei8_v.h new file mode 100644 index 0000000000..af37c8c3f8 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vamoswapei8_v.h @@ -0,0 +1,2 @@ +//vamoswape.v vd, (rs1), vs2, vd +VI_AMO({ return vs3; }, uint, e8); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vamoxorei16_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vamoxorei16_v.h new file mode 100644 index 0000000000..61e8c3272c --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vamoxorei16_v.h @@ -0,0 +1,2 @@ +//vamoore.v vd, (rs1), vs2, vd +VI_AMO({ return lhs ^ vs3; }, uint, e16); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vamoxorei32_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vamoxorei32_v.h new file mode 100644 index 0000000000..d48d951504 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vamoxorei32_v.h @@ -0,0 +1,2 @@ +//vamoore.v vd, (rs1), vs2, vd +VI_AMO({ return lhs ^ vs3; }, uint, e32); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vamoxorei64_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vamoxorei64_v.h new file mode 100644 index 0000000000..f7a3ca42e1 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vamoxorei64_v.h @@ -0,0 +1,2 @@ +//vamoore.v vd, (rs1), vs2, vd +VI_AMO({ return lhs ^ vs3; }, uint, e64); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vamoxorei8_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vamoxorei8_v.h new file mode 100644 index 0000000000..4b6c79824c --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vamoxorei8_v.h @@ -0,0 +1,2 @@ +//vamoore.v vd, (rs1), vs2, vd +VI_AMO({ return lhs ^ vs3; }, uint, e8); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vand_vi.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vand_vi.h new file mode 100644 index 0000000000..dd9618ba94 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vand_vi.h @@ -0,0 +1,5 @@ +// vand.vi vd, simm5, vs2, vm +VI_VI_LOOP +({ + vd = simm5 & vs2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vand_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vand_vv.h new file mode 100644 index 0000000000..65558e4b6a --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vand_vv.h @@ -0,0 +1,5 @@ +// vand.vv vd, vs1, vs2, vm +VI_VV_LOOP +({ + vd = vs1 & vs2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vand_vx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vand_vx.h new file mode 100644 index 0000000000..8eea1ed526 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vand_vx.h @@ -0,0 +1,5 @@ +// vand.vx vd, rs1, vs2, vm +VI_VX_LOOP +({ + vd = rs1 & vs2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vasub_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vasub_vv.h new file mode 100644 index 0000000000..7dfbdfcfaa --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vasub_vv.h @@ -0,0 +1,2 @@ +// vasub.vv vd, vs2, vs1 +VI_VV_LOOP_AVG(-); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vasub_vx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vasub_vx.h new file mode 100644 index 0000000000..185fa9c19f --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vasub_vx.h @@ -0,0 +1,2 @@ +// vasub.vx vd, vs2, rs1 +VI_VX_LOOP_AVG(-); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vasubu_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vasubu_vv.h new file mode 100644 index 0000000000..902fef998f --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vasubu_vv.h @@ -0,0 +1,2 @@ +// vasubu.vv vd, vs2, vs1 +VI_VV_ULOOP_AVG(-); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vasubu_vx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vasubu_vx.h new file mode 100644 index 0000000000..874dc59ee1 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vasubu_vx.h @@ -0,0 +1,2 @@ +// vasubu.vx vd, vs2, rs1 +VI_VX_ULOOP_AVG(-); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vcompress_vm.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vcompress_vm.h new file mode 100644 index 0000000000..719534596d --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vcompress_vm.h @@ -0,0 +1,33 @@ +// vcompress vd, vs2, vs1 +require(P.VU.vstart->read() == 0); +require_align(insn.rd(), P.VU.vflmul); +require_align(insn.rs2(), P.VU.vflmul); +require(insn.rd() != insn.rs2()); +require_noover(insn.rd(), P.VU.vflmul, insn.rs1(), 1); + +reg_t pos = 0; + +VI_GENERAL_LOOP_BASE + const int midx = i / 64; + const int mpos = i % 64; + + bool do_mask = (P.VU.elt<uint64_t>(rs1_num, midx) >> mpos) & 0x1; + if (do_mask) { + switch (sew) { + case e8: + P.VU.elt<uint8_t>(rd_num, pos, true) = P.VU.elt<uint8_t>(rs2_num, i); + break; + case e16: + P.VU.elt<uint16_t>(rd_num, pos, true) = P.VU.elt<uint16_t>(rs2_num, i); + break; + case e32: + P.VU.elt<uint32_t>(rd_num, pos, true) = P.VU.elt<uint32_t>(rs2_num, i); + break; + default: + P.VU.elt<uint64_t>(rd_num, pos, true) = P.VU.elt<uint64_t>(rs2_num, i); + break; + } + + ++pos; + } +VI_LOOP_END; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vcpop_m.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vcpop_m.h new file mode 100644 index 0000000000..671362f723 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vcpop_m.h @@ -0,0 +1,21 @@ +// vmpopc rd, vs2, vm +require(P.VU.vsew >= e8 && P.VU.vsew <= e64); +require_vector(true); +reg_t vl = P.VU.vl->read(); +reg_t rs2_num = insn.rs2(); +require(P.VU.vstart->read() == 0); +reg_t popcount = 0; +for (reg_t i=P.VU.vstart->read(); i<vl; ++i) { + const int midx = i / 32; + const int mpos = i % 32; + + bool vs2_lsb = ((P.VU.elt<uint32_t>(rs2_num, midx ) >> mpos) & 0x1) == 1; + if (insn.v_vm() == 1) { + popcount += vs2_lsb; + } else { + bool do_mask = (P.VU.elt<uint32_t>(0, midx) >> mpos) & 0x1; + popcount += (vs2_lsb && do_mask); + } +} +P.VU.vstart->write(0); +WRITE_RD(popcount); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vdiv_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vdiv_vv.h new file mode 100644 index 0000000000..0d4bd0d8e4 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vdiv_vv.h @@ -0,0 +1,10 @@ +// vdiv.vv vd, vs2, vs1 +VI_VV_LOOP +({ + if (vs1 == 0) + vd = -1; + else if (vs2 == (INT64_MIN >> (64 - sew)) && vs1 == -1) + vd = vs2; + else + vd = vs2 / vs1; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vdiv_vx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vdiv_vx.h new file mode 100644 index 0000000000..2b93eace59 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vdiv_vx.h @@ -0,0 +1,10 @@ +// vdiv.vx vd, vs2, rs1 +VI_VX_LOOP +({ + if (rs1 == 0) + vd = -1; + else if (vs2 == (INT64_MIN >> (64 - sew)) && rs1 == -1) + vd = vs2; + else + vd = vs2 / rs1; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vdivu_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vdivu_vv.h new file mode 100644 index 0000000000..89aeed625b --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vdivu_vv.h @@ -0,0 +1,8 @@ +// vdivu.vv vd, vs2, vs1 +VI_VV_ULOOP +({ + if (vs1 == 0) + vd = -1; + else + vd = vs2 / vs1; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vdivu_vx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vdivu_vx.h new file mode 100644 index 0000000000..ce3e9644c2 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vdivu_vx.h @@ -0,0 +1,8 @@ +// vdivu.vx vd, vs2, rs1 +VI_VX_ULOOP +({ + if (rs1 == 0) + vd = -1; + else + vd = vs2 / rs1; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfadd_vf.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfadd_vf.h new file mode 100644 index 0000000000..2b808e0ccd --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfadd_vf.h @@ -0,0 +1,11 @@ +// vfadd.vf vd, vs2, rs1 +VI_VFP_VF_LOOP +({ + vd = f16_add(rs1, vs2); +}, +{ + vd = f32_add(rs1, vs2); +}, +{ + vd = f64_add(rs1, vs2); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfadd_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfadd_vv.h new file mode 100644 index 0000000000..ce94921d56 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfadd_vv.h @@ -0,0 +1,11 @@ +// vfadd.vv vd, vs2, vs1 +VI_VFP_VV_LOOP +({ + vd = f16_add(vs1, vs2); +}, +{ + vd = f32_add(vs1, vs2); +}, +{ + vd = f64_add(vs1, vs2); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfclass_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfclass_v.h new file mode 100644 index 0000000000..a307d2d1ed --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfclass_v.h @@ -0,0 +1,11 @@ +// vfclass.v vd, vs2, vm +VI_VFP_V_LOOP +({ + vd = f16(f16_classify(vs2)); +}, +{ + vd = f32(f32_classify(vs2)); +}, +{ + vd = f64(f64_classify(vs2)); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfcvt_f_x_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfcvt_f_x_v.h new file mode 100644 index 0000000000..d094c14001 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfcvt_f_x_v.h @@ -0,0 +1,7 @@ +// vfcvt.f.x.v vd, vd2, vm +VI_VFP_CVT_INT_TO_FP( + { vd = i32_to_f16(vs2); }, // BODY16 + { vd = i32_to_f32(vs2); }, // BODY32 + { vd = i64_to_f64(vs2); }, // BODY64 + int // sign +) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfcvt_f_xu_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfcvt_f_xu_v.h new file mode 100644 index 0000000000..64dbb1c119 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfcvt_f_xu_v.h @@ -0,0 +1,7 @@ +// vfcvt.f.xu.v vd, vd2, vm +VI_VFP_CVT_INT_TO_FP( + { vd = ui32_to_f16(vs2); }, // BODY16 + { vd = ui32_to_f32(vs2); }, // BODY32 + { vd = ui64_to_f64(vs2); }, // BODY64 + uint // sign +) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfcvt_rtz_x_f_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfcvt_rtz_x_f_v.h new file mode 100644 index 0000000000..ecdfa22de9 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfcvt_rtz_x_f_v.h @@ -0,0 +1,7 @@ +// vfcvt.rtz.x.f.v vd, vd2, vm +VI_VFP_CVT_FP_TO_INT( + { vd = f16_to_i16(vs2, softfloat_round_minMag, true); }, // BODY16 + { vd = f32_to_i32(vs2, softfloat_round_minMag, true); }, // BODY32 + { vd = f64_to_i64(vs2, softfloat_round_minMag, true); }, // BODY64 + int // sign +) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfcvt_rtz_xu_f_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfcvt_rtz_xu_f_v.h new file mode 100644 index 0000000000..87585d24ca --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfcvt_rtz_xu_f_v.h @@ -0,0 +1,7 @@ +// vfcvt.rtz.xu.f.v vd, vd2, vm +VI_VFP_CVT_FP_TO_INT( + { vd = f16_to_ui16(vs2, softfloat_round_minMag, true); }, // BODY16 + { vd = f32_to_ui32(vs2, softfloat_round_minMag, true); }, // BODY32 + { vd = f64_to_ui64(vs2, softfloat_round_minMag, true); }, // BODY64 + uint // sign +) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfcvt_x_f_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfcvt_x_f_v.h new file mode 100644 index 0000000000..4f21b52ff9 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfcvt_x_f_v.h @@ -0,0 +1,7 @@ +// vfcvt.x.f.v vd, vd2, vm +VI_VFP_CVT_FP_TO_INT( + { vd = f16_to_i16(vs2, softfloat_roundingMode, true); }, // BODY16 + { vd = f32_to_i32(vs2, softfloat_roundingMode, true); }, // BODY32 + { vd = f64_to_i64(vs2, softfloat_roundingMode, true); }, // BODY64 + int // sign +) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfcvt_xu_f_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfcvt_xu_f_v.h new file mode 100644 index 0000000000..ba50fff6ac --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfcvt_xu_f_v.h @@ -0,0 +1,7 @@ +// vfcvt.xu.f.v vd, vd2, vm +VI_VFP_CVT_FP_TO_INT( + { vd = f16_to_ui16(vs2, softfloat_roundingMode, true); }, // BODY16 + { vd = f32_to_ui32(vs2, softfloat_roundingMode, true); }, // BODY32 + { vd = f64_to_ui64(vs2, softfloat_roundingMode, true); }, // BODY64 + uint // sign +) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfdiv_vf.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfdiv_vf.h new file mode 100644 index 0000000000..a703ef02bf --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfdiv_vf.h @@ -0,0 +1,11 @@ +// vfdiv.vf vd, vs2, rs1 +VI_VFP_VF_LOOP +({ + vd = f16_div(vs2, rs1); +}, +{ + vd = f32_div(vs2, rs1); +}, +{ + vd = f64_div(vs2, rs1); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfdiv_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfdiv_vv.h new file mode 100644 index 0000000000..c66d751659 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfdiv_vv.h @@ -0,0 +1,11 @@ +// vfdiv.vv vd, vs2, vs1 +VI_VFP_VV_LOOP +({ + vd = f16_div(vs2, vs1); +}, +{ + vd = f32_div(vs2, vs1); +}, +{ + vd = f64_div(vs2, vs1); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfirst_m.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfirst_m.h new file mode 100644 index 0000000000..9ddc82b40d --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfirst_m.h @@ -0,0 +1,18 @@ +// vmfirst rd, vs2 +require(P.VU.vsew >= e8 && P.VU.vsew <= e64); +require_vector(true); +reg_t vl = P.VU.vl->read(); +reg_t rs2_num = insn.rs2(); +require(P.VU.vstart->read() == 0); +reg_t pos = -1; +for (reg_t i=P.VU.vstart->read(); i < vl; ++i) { + VI_LOOP_ELEMENT_SKIP() + + bool vs2_lsb = ((P.VU.elt<uint64_t>(rs2_num, midx ) >> mpos) & 0x1) == 1; + if (vs2_lsb) { + pos = i; + break; + } +} +P.VU.vstart->write(0); +WRITE_RD(pos); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfmacc_vf.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfmacc_vf.h new file mode 100644 index 0000000000..61578d3318 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfmacc_vf.h @@ -0,0 +1,11 @@ +// vfmacc.vf vd, rs1, vs2, vm # vd[i] = +(vs2[i] * x[rs1]) + vd[i] +VI_VFP_VF_LOOP +({ + vd = f16_mulAdd(rs1, vs2, vd); +}, +{ + vd = f32_mulAdd(rs1, vs2, vd); +}, +{ + vd = f64_mulAdd(rs1, vs2, vd); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfmacc_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfmacc_vv.h new file mode 100644 index 0000000000..499b1d4d22 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfmacc_vv.h @@ -0,0 +1,11 @@ +// vfmacc.vv vd, rs1, vs2, vm # vd[i] = +(vs2[i] * vs1[i]) + vd[i] +VI_VFP_VV_LOOP +({ + vd = f16_mulAdd(vs1, vs2, vd); +}, +{ + vd = f32_mulAdd(vs1, vs2, vd); +}, +{ + vd = f64_mulAdd(vs1, vs2, vd); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfmadd_vf.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfmadd_vf.h new file mode 100644 index 0000000000..2a01429506 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfmadd_vf.h @@ -0,0 +1,11 @@ +// vfmadd: vd[i] = +(vd[i] * f[rs1]) + vs2[i] +VI_VFP_VF_LOOP +({ + vd = f16_mulAdd(vd, rs1, vs2); +}, +{ + vd = f32_mulAdd(vd, rs1, vs2); +}, +{ + vd = f64_mulAdd(vd, rs1, vs2); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfmadd_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfmadd_vv.h new file mode 100644 index 0000000000..7ef734f847 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfmadd_vv.h @@ -0,0 +1,11 @@ +// vfmadd: vd[i] = +(vd[i] * vs1[i]) + vs2[i] +VI_VFP_VV_LOOP +({ + vd = f16_mulAdd(vd, vs1, vs2); +}, +{ + vd = f32_mulAdd(vd, vs1, vs2); +}, +{ + vd = f64_mulAdd(vd, vs1, vs2); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfmax_vf.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfmax_vf.h new file mode 100644 index 0000000000..c4b74cbd54 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfmax_vf.h @@ -0,0 +1,11 @@ +// vfmax +VI_VFP_VF_LOOP +({ + vd = f16_max(vs2, rs1); +}, +{ + vd = f32_max(vs2, rs1); +}, +{ + vd = f64_max(vs2, rs1); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfmax_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfmax_vv.h new file mode 100644 index 0000000000..6439c8997f --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfmax_vv.h @@ -0,0 +1,11 @@ +// vfmax +VI_VFP_VV_LOOP +({ + vd = f16_max(vs2, vs1); +}, +{ + vd = f32_max(vs2, vs1); +}, +{ + vd = f64_max(vs2, vs1); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfmerge_vfm.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfmerge_vfm.h new file mode 100644 index 0000000000..d82dfef5de --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfmerge_vfm.h @@ -0,0 +1,4 @@ +// vfmerge_vf vd, vs2, vs1, vm +VI_VF_MERGE_LOOP({ + vd = use_first ? rs1 : vs2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfmin_vf.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfmin_vf.h new file mode 100644 index 0000000000..1560cdf7dc --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfmin_vf.h @@ -0,0 +1,11 @@ +// vfmin vd, vs2, rs1 +VI_VFP_VF_LOOP +({ + vd = f16_min(vs2, rs1); +}, +{ + vd = f32_min(vs2, rs1); +}, +{ + vd = f64_min(vs2, rs1); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfmin_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfmin_vv.h new file mode 100644 index 0000000000..882a774044 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfmin_vv.h @@ -0,0 +1,11 @@ +// vfmin vd, vs2, vs1 +VI_VFP_VV_LOOP +({ + vd = f16_min(vs2, vs1); +}, +{ + vd = f32_min(vs2, vs1); +}, +{ + vd = f64_min(vs2, vs1); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfmsac_vf.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfmsac_vf.h new file mode 100644 index 0000000000..8af397b999 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfmsac_vf.h @@ -0,0 +1,11 @@ +// vfmsac: vd[i] = +(f[rs1] * vs2[i]) - vd[i] +VI_VFP_VF_LOOP +({ + vd = f16_mulAdd(rs1, vs2, f16(vd.v ^ F16_SIGN)); +}, +{ + vd = f32_mulAdd(rs1, vs2, f32(vd.v ^ F32_SIGN)); +}, +{ + vd = f64_mulAdd(rs1, vs2, f64(vd.v ^ F64_SIGN)); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfmsac_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfmsac_vv.h new file mode 100644 index 0000000000..3bb50e50a9 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfmsac_vv.h @@ -0,0 +1,11 @@ +// vfmsac: vd[i] = +(vs1[i] * vs2[i]) - vd[i] +VI_VFP_VV_LOOP +({ + vd = f16_mulAdd(vs1, vs2, f16(vd.v ^ F16_SIGN)); +}, +{ + vd = f32_mulAdd(vs1, vs2, f32(vd.v ^ F32_SIGN)); +}, +{ + vd = f64_mulAdd(vs1, vs2, f64(vd.v ^ F64_SIGN)); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfmsub_vf.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfmsub_vf.h new file mode 100644 index 0000000000..ab77b4c6e1 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfmsub_vf.h @@ -0,0 +1,11 @@ +// vfmsub: vd[i] = +(vd[i] * f[rs1]) - vs2[i] +VI_VFP_VF_LOOP +({ + vd = f16_mulAdd(vd, rs1, f16(vs2.v ^ F16_SIGN)); +}, +{ + vd = f32_mulAdd(vd, rs1, f32(vs2.v ^ F32_SIGN)); +}, +{ + vd = f64_mulAdd(vd, rs1, f64(vs2.v ^ F64_SIGN)); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfmsub_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfmsub_vv.h new file mode 100644 index 0000000000..3cac937fd1 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfmsub_vv.h @@ -0,0 +1,11 @@ +// vfmsub: vd[i] = +(vd[i] * vs1[i]) - vs2[i] +VI_VFP_VV_LOOP +({ + vd = f16_mulAdd(vd, vs1, f16(vs2.v ^ F16_SIGN)); +}, +{ + vd = f32_mulAdd(vd, vs1, f32(vs2.v ^ F32_SIGN)); +}, +{ + vd = f64_mulAdd(vd, vs1, f64(vs2.v ^ F64_SIGN)); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfmul_vf.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfmul_vf.h new file mode 100644 index 0000000000..f5f63e497a --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfmul_vf.h @@ -0,0 +1,11 @@ +// vfmul.vf vd, vs2, rs1, vm +VI_VFP_VF_LOOP +({ + vd = f16_mul(vs2, rs1); +}, +{ + vd = f32_mul(vs2, rs1); +}, +{ + vd = f64_mul(vs2, rs1); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfmul_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfmul_vv.h new file mode 100644 index 0000000000..7930fd034e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfmul_vv.h @@ -0,0 +1,11 @@ +// vfmul.vv vd, vs1, vs2, vm +VI_VFP_VV_LOOP +({ + vd = f16_mul(vs1, vs2); +}, +{ + vd = f32_mul(vs1, vs2); +}, +{ + vd = f64_mul(vs1, vs2); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfmv_f_s.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfmv_f_s.h new file mode 100644 index 0000000000..1ad6bc693a --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfmv_f_s.h @@ -0,0 +1,38 @@ +// vfmv_f_s: rd = vs2[0] (rs1=0) +require_vector(true); +require_fp; +require((P.VU.vsew == e16 && p->extension_enabled(EXT_ZVFH)) || + (P.VU.vsew == e32 && p->extension_enabled('F')) || + (P.VU.vsew == e64 && p->extension_enabled('D'))); +require(STATE.frm->read() < 0x5); + +reg_t rs2_num = insn.rs2(); +uint64_t vs2_0 = 0; +const reg_t sew = P.VU.vsew; +switch (sew) { + case e16: + vs2_0 = P.VU.elt<uint16_t>(rs2_num, 0); + break; + case e32: + vs2_0 = P.VU.elt<uint32_t>(rs2_num, 0); + break; + case e64: + vs2_0 = P.VU.elt<uint64_t>(rs2_num, 0); + break; + default: + require(0); + break; +} + +// nan_extened +if (FLEN > sew) { + vs2_0 = vs2_0 | (UINT64_MAX << sew); +} + +if (FLEN == 64) { + WRITE_FRD(f64(vs2_0)); +} else { + WRITE_FRD(f32(vs2_0)); +} + +P.VU.vstart->write(0); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfmv_s_f.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfmv_s_f.h new file mode 100644 index 0000000000..4b1b955e56 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfmv_s_f.h @@ -0,0 +1,29 @@ +// vfmv_s_f: vd[0] = rs1 (vs2=0) +require_vector(true); +require_fp; +require((P.VU.vsew == e16 && p->extension_enabled(EXT_ZVFH)) || + (P.VU.vsew == e32 && p->extension_enabled('F')) || + (P.VU.vsew == e64 && p->extension_enabled('D'))); +require(STATE.frm->read() < 0x5); + +reg_t vl = P.VU.vl->read(); + +if (vl > 0 && P.VU.vstart->read() < vl) { + reg_t rd_num = insn.rd(); + + switch (P.VU.vsew) { + case e16: + P.VU.elt<uint16_t>(rd_num, 0, true) = f16(FRS1).v; + break; + case e32: + P.VU.elt<uint32_t>(rd_num, 0, true) = f32(FRS1).v; + break; + case e64: + if (FLEN == 64) + P.VU.elt<uint64_t>(rd_num, 0, true) = f64(FRS1).v; + else + P.VU.elt<uint64_t>(rd_num, 0, true) = f32(FRS1).v; + break; + } +} +P.VU.vstart->write(0); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfmv_v_f.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfmv_v_f.h new file mode 100644 index 0000000000..50b7513c65 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfmv_v_f.h @@ -0,0 +1,4 @@ +// vfmv_vf vd, vs1 +VI_VF_MERGE_LOOP({ + vd = rs1; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfncvt_f_f_w.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfncvt_f_f_w.h new file mode 100644 index 0000000000..97de40e275 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfncvt_f_f_w.h @@ -0,0 +1,7 @@ +// vfncvt.f.f.w vd, vs2, vm +VI_VFP_NCVT_FP_TO_FP( + { vd = f32_to_f16(vs2); }, // BODY32 + { vd = f64_to_f32(vs2); }, // BODY64 + { require_extension(EXT_ZVFHMIN); }, // CHECK32 + { require_extension('D'); } // CHECK64 +) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfncvt_f_x_w.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfncvt_f_x_w.h new file mode 100644 index 0000000000..46f2d92f71 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfncvt_f_x_w.h @@ -0,0 +1,8 @@ +// vfncvt.f.x.w vd, vs2, vm +VI_VFP_NCVT_INT_TO_FP( + { vd = i32_to_f16(vs2); }, // BODY32 + { vd = i64_to_f32(vs2); }, // BODY64 + { require_extension(EXT_ZVFH); }, // CHECK32 + { require_extension('F'); }, // CHECK64 + int // sign +) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfncvt_f_xu_w.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfncvt_f_xu_w.h new file mode 100644 index 0000000000..729fb528ee --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfncvt_f_xu_w.h @@ -0,0 +1,8 @@ +// vfncvt.f.xu.w vd, vs2, vm +VI_VFP_NCVT_INT_TO_FP( + { vd = ui32_to_f16(vs2); }, // BODY32 + { vd = ui64_to_f32(vs2); }, // BODY64 + { require_extension(EXT_ZVFH); }, // CHECK32 + { require_extension('F'); }, // CHECK64 + uint // sign +) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfncvt_rod_f_f_w.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfncvt_rod_f_f_w.h new file mode 100644 index 0000000000..93002dc0f5 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfncvt_rod_f_f_w.h @@ -0,0 +1,13 @@ +// vfncvt.rod.f.f.w vd, vs2, vm +VI_VFP_NCVT_FP_TO_FP( + { // BODY32 + softfloat_roundingMode = softfloat_round_odd; + vd = f32_to_f16(vs2); + }, + { // BODY64 + softfloat_roundingMode = softfloat_round_odd; + vd = f64_to_f32(vs2); + }, + { require_extension(EXT_ZVFH); }, // CHECK32 + { require_extension('F'); } // CHECK64 +) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfncvt_rtz_x_f_w.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfncvt_rtz_x_f_w.h new file mode 100644 index 0000000000..ee47e22361 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfncvt_rtz_x_f_w.h @@ -0,0 +1,10 @@ +// vfncvt.rtz.x.f.w vd, vs2, vm +VI_VFP_NCVT_FP_TO_INT( + { vd = f16_to_i8(vs2, softfloat_round_minMag, true); }, // BODY16 + { vd = f32_to_i16(vs2, softfloat_round_minMag, true); }, // BODY32 + { vd = f64_to_i32(vs2, softfloat_round_minMag, true); }, // BODY64 + { require_extension(EXT_ZVFH); }, // CHECK16 + { require(p->extension_enabled('F')); }, // CHECK32 + { require(p->extension_enabled('D')); }, // CHECK64 + int // sign +) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfncvt_rtz_xu_f_w.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfncvt_rtz_xu_f_w.h new file mode 100644 index 0000000000..3d029f3eb6 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfncvt_rtz_xu_f_w.h @@ -0,0 +1,10 @@ +// vfncvt.rtz.xu.f.w vd, vs2, vm +VI_VFP_NCVT_FP_TO_INT( + { vd = f16_to_ui8(vs2, softfloat_round_minMag, true); }, // BODY16 + { vd = f32_to_ui16(vs2, softfloat_round_minMag, true); }, // BODY32 + { vd = f64_to_ui32(vs2, softfloat_round_minMag, true); }, // BODY64 + { require_extension(EXT_ZVFH); }, // CHECK16 + { require(p->extension_enabled('F')); }, // CHECK32 + { require(p->extension_enabled('D')); }, // CHECK64 + uint // sign +) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfncvt_x_f_w.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfncvt_x_f_w.h new file mode 100644 index 0000000000..0da5a75f30 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfncvt_x_f_w.h @@ -0,0 +1,10 @@ +// vfncvt.x.f.w vd, vs2, vm +VI_VFP_NCVT_FP_TO_INT( + { vd = f16_to_i8(vs2, softfloat_roundingMode, true); }, // BODY16 + { vd = f32_to_i16(vs2, softfloat_roundingMode, true); }, // BODY32 + { vd = f64_to_i32(vs2, softfloat_roundingMode, true); }, // BODY64 + { require_extension(EXT_ZVFH); }, // CHECK16 + { require(p->extension_enabled('F')); }, // CHECK32 + { require(p->extension_enabled('D')); }, // CHECK64 + int // sign +) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfncvt_xu_f_w.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfncvt_xu_f_w.h new file mode 100644 index 0000000000..da5a52d3cb --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfncvt_xu_f_w.h @@ -0,0 +1,10 @@ +// vfncvt.xu.f.w vd, vs2, vm +VI_VFP_NCVT_FP_TO_INT( + { vd = f16_to_ui8(vs2, softfloat_roundingMode, true); }, // BODY16 + { vd = f32_to_ui16(vs2, softfloat_roundingMode, true); }, // BODY32 + { vd = f64_to_ui32(vs2, softfloat_roundingMode, true); }, // BODY64 + { require_extension(EXT_ZVFH); }, // CHECK16 + { require(p->extension_enabled('F')); }, // CHECK32 + { require(p->extension_enabled('D')); }, // CHECK64 + uint // sign +) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfnmacc_vf.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfnmacc_vf.h new file mode 100644 index 0000000000..1b99302c6c --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfnmacc_vf.h @@ -0,0 +1,11 @@ +// vfnmacc: vd[i] = -(f[rs1] * vs2[i]) - vd[i] +VI_VFP_VF_LOOP +({ + vd = f16_mulAdd(rs1, f16(vs2.v ^ F16_SIGN), f16(vd.v ^ F16_SIGN)); +}, +{ + vd = f32_mulAdd(rs1, f32(vs2.v ^ F32_SIGN), f32(vd.v ^ F32_SIGN)); +}, +{ + vd = f64_mulAdd(rs1, f64(vs2.v ^ F64_SIGN), f64(vd.v ^ F64_SIGN)); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfnmacc_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfnmacc_vv.h new file mode 100644 index 0000000000..7200e063ab --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfnmacc_vv.h @@ -0,0 +1,11 @@ +// vfnmacc: vd[i] = -(vs1[i] * vs2[i]) - vd[i] +VI_VFP_VV_LOOP +({ + vd = f16_mulAdd(f16(vs2.v ^ F16_SIGN), vs1, f16(vd.v ^ F16_SIGN)); +}, +{ + vd = f32_mulAdd(f32(vs2.v ^ F32_SIGN), vs1, f32(vd.v ^ F32_SIGN)); +}, +{ + vd = f64_mulAdd(f64(vs2.v ^ F64_SIGN), vs1, f64(vd.v ^ F64_SIGN)); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfnmadd_vf.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfnmadd_vf.h new file mode 100644 index 0000000000..cb9c217ff2 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfnmadd_vf.h @@ -0,0 +1,11 @@ +// vfnmadd: vd[i] = -(vd[i] * f[rs1]) - vs2[i] +VI_VFP_VF_LOOP +({ + vd = f16_mulAdd(f16(vd.v ^ F16_SIGN), rs1, f16(vs2.v ^ F16_SIGN)); +}, +{ + vd = f32_mulAdd(f32(vd.v ^ F32_SIGN), rs1, f32(vs2.v ^ F32_SIGN)); +}, +{ + vd = f64_mulAdd(f64(vd.v ^ F64_SIGN), rs1, f64(vs2.v ^ F64_SIGN)); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfnmadd_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfnmadd_vv.h new file mode 100644 index 0000000000..7160ed7d6f --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfnmadd_vv.h @@ -0,0 +1,11 @@ +// vfnmadd: vd[i] = -(vd[i] * vs1[i]) - vs2[i] +VI_VFP_VV_LOOP +({ + vd = f16_mulAdd(f16(vd.v ^ F16_SIGN), vs1, f16(vs2.v ^ F16_SIGN)); +}, +{ + vd = f32_mulAdd(f32(vd.v ^ F32_SIGN), vs1, f32(vs2.v ^ F32_SIGN)); +}, +{ + vd = f64_mulAdd(f64(vd.v ^ F64_SIGN), vs1, f64(vs2.v ^ F64_SIGN)); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfnmsac_vf.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfnmsac_vf.h new file mode 100644 index 0000000000..aa6baa30c6 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfnmsac_vf.h @@ -0,0 +1,11 @@ +// vfnmsac: vd[i] = -(f[rs1] * vs2[i]) + vd[i] +VI_VFP_VF_LOOP +({ + vd = f16_mulAdd(rs1, f16(vs2.v ^ F16_SIGN), vd); +}, +{ + vd = f32_mulAdd(rs1, f32(vs2.v ^ F32_SIGN), vd); +}, +{ + vd = f64_mulAdd(rs1, f64(vs2.v ^ F64_SIGN), vd); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfnmsac_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfnmsac_vv.h new file mode 100644 index 0000000000..47db61d2d0 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfnmsac_vv.h @@ -0,0 +1,11 @@ +// vfnmsac.vv vd, vs1, vs2, vm # vd[i] = -(vs2[i] * vs1[i]) + vd[i] +VI_VFP_VV_LOOP +({ + vd = f16_mulAdd(f16(vs1.v ^ F16_SIGN), vs2, vd); +}, +{ + vd = f32_mulAdd(f32(vs1.v ^ F32_SIGN), vs2, vd); +}, +{ + vd = f64_mulAdd(f64(vs1.v ^ F64_SIGN), vs2, vd); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfnmsub_vf.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfnmsub_vf.h new file mode 100644 index 0000000000..43aa9e2685 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfnmsub_vf.h @@ -0,0 +1,11 @@ +// vfnmsub: vd[i] = -(vd[i] * f[rs1]) + vs2[i] +VI_VFP_VF_LOOP +({ + vd = f16_mulAdd(f16(vd.v ^ F16_SIGN), rs1, vs2); +}, +{ + vd = f32_mulAdd(f32(vd.v ^ F32_SIGN), rs1, vs2); +}, +{ + vd = f64_mulAdd(f64(vd.v ^ F64_SIGN), rs1, vs2); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfnmsub_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfnmsub_vv.h new file mode 100644 index 0000000000..2a45c8fca0 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfnmsub_vv.h @@ -0,0 +1,11 @@ +// vfnmsub: vd[i] = -(vd[i] * vs1[i]) + vs2[i] +VI_VFP_VV_LOOP +({ + vd = f16_mulAdd(f16(vd.v ^ F16_SIGN), vs1, vs2); +}, +{ + vd = f32_mulAdd(f32(vd.v ^ F32_SIGN), vs1, vs2); +}, +{ + vd = f64_mulAdd(f64(vd.v ^ F64_SIGN), vs1, vs2); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfrdiv_vf.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfrdiv_vf.h new file mode 100644 index 0000000000..b283343cc2 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfrdiv_vf.h @@ -0,0 +1,11 @@ +// vfrdiv.vf vd, vs2, rs1, vm # scalar-vector, vd[i] = f[rs1]/vs2[i] +VI_VFP_VF_LOOP +({ + vd = f16_div(rs1, vs2); +}, +{ + vd = f32_div(rs1, vs2); +}, +{ + vd = f64_div(rs1, vs2); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfrec7_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfrec7_v.h new file mode 100644 index 0000000000..69c026b058 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfrec7_v.h @@ -0,0 +1,11 @@ +// vfclass.v vd, vs2, vm +VI_VFP_V_LOOP +({ + vd = f16_recip7(vs2); +}, +{ + vd = f32_recip7(vs2); +}, +{ + vd = f64_recip7(vs2); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfredmax_vs.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfredmax_vs.h new file mode 100644 index 0000000000..f19ec59791 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfredmax_vs.h @@ -0,0 +1,12 @@ +// vfredmax vd, vs2, vs1 +bool is_propagate = false; +VI_VFP_VV_LOOP_REDUCTION +({ + vd_0 = f16_max(vd_0, vs2); +}, +{ + vd_0 = f32_max(vd_0, vs2); +}, +{ + vd_0 = f64_max(vd_0, vs2); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfredmin_vs.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfredmin_vs.h new file mode 100644 index 0000000000..e3cf151324 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfredmin_vs.h @@ -0,0 +1,12 @@ +// vfredmin vd, vs2, vs1 +bool is_propagate = false; +VI_VFP_VV_LOOP_REDUCTION +({ + vd_0 = f16_min(vd_0, vs2); +}, +{ + vd_0 = f32_min(vd_0, vs2); +}, +{ + vd_0 = f64_min(vd_0, vs2); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfredosum_vs.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfredosum_vs.h new file mode 100644 index 0000000000..2438a7ba9c --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfredosum_vs.h @@ -0,0 +1,12 @@ +// vfredosum: vd[0] = sum( vs2[*] , vs1[0] ) +bool is_propagate = false; +VI_VFP_VV_LOOP_REDUCTION +({ + vd_0 = f16_add(vd_0, vs2); +}, +{ + vd_0 = f32_add(vd_0, vs2); +}, +{ + vd_0 = f64_add(vd_0, vs2); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfredusum_vs.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfredusum_vs.h new file mode 100644 index 0000000000..bad7308e54 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfredusum_vs.h @@ -0,0 +1,12 @@ +// vfredsum: vd[0] = sum( vs2[*] , vs1[0] ) +bool is_propagate = true; +VI_VFP_VV_LOOP_REDUCTION +({ + vd_0 = f16_add(vd_0, vs2); +}, +{ + vd_0 = f32_add(vd_0, vs2); +}, +{ + vd_0 = f64_add(vd_0, vs2); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfrsqrt7_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfrsqrt7_v.h new file mode 100644 index 0000000000..a073764127 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfrsqrt7_v.h @@ -0,0 +1,11 @@ +// vfclass.v vd, vs2, vm +VI_VFP_V_LOOP +({ + vd = f16_rsqrte7(vs2); +}, +{ + vd = f32_rsqrte7(vs2); +}, +{ + vd = f64_rsqrte7(vs2); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfrsub_vf.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfrsub_vf.h new file mode 100644 index 0000000000..7fb26a5b5d --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfrsub_vf.h @@ -0,0 +1,11 @@ +// vfsub.vf vd, vs2, rs1 +VI_VFP_VF_LOOP +({ + vd = f16_sub(rs1, vs2); +}, +{ + vd = f32_sub(rs1, vs2); +}, +{ + vd = f64_sub(rs1, vs2); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfsgnj_vf.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfsgnj_vf.h new file mode 100644 index 0000000000..ce06185ee9 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfsgnj_vf.h @@ -0,0 +1,11 @@ +// vfsgnj vd, vs2, vs1 +VI_VFP_VF_LOOP +({ + vd = fsgnj16(vs2.v, rs1.v, false, false); +}, +{ + vd = fsgnj32(vs2.v, rs1.v, false, false); +}, +{ + vd = fsgnj64(vs2.v, rs1.v, false, false); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfsgnj_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfsgnj_vv.h new file mode 100644 index 0000000000..722cb29cf0 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfsgnj_vv.h @@ -0,0 +1,11 @@ +// vfsgnj +VI_VFP_VV_LOOP +({ + vd = fsgnj16(vs2.v, vs1.v, false, false); +}, +{ + vd = fsgnj32(vs2.v, vs1.v, false, false); +}, +{ + vd = fsgnj64(vs2.v, vs1.v, false, false); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfsgnjn_vf.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfsgnjn_vf.h new file mode 100644 index 0000000000..e4894124aa --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfsgnjn_vf.h @@ -0,0 +1,11 @@ +// vfsgnn +VI_VFP_VF_LOOP +({ + vd = fsgnj16(vs2.v, rs1.v, true, false); +}, +{ + vd = fsgnj32(vs2.v, rs1.v, true, false); +}, +{ + vd = fsgnj64(vs2.v, rs1.v, true, false); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfsgnjn_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfsgnjn_vv.h new file mode 100644 index 0000000000..1d91f69199 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfsgnjn_vv.h @@ -0,0 +1,11 @@ +// vfsgnn +VI_VFP_VV_LOOP +({ + vd = fsgnj16(vs2.v, vs1.v, true, false); +}, +{ + vd = fsgnj32(vs2.v, vs1.v, true, false); +}, +{ + vd = fsgnj64(vs2.v, vs1.v, true, false); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfsgnjx_vf.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfsgnjx_vf.h new file mode 100644 index 0000000000..7be164c770 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfsgnjx_vf.h @@ -0,0 +1,11 @@ +// vfsgnx +VI_VFP_VF_LOOP +({ + vd = fsgnj16(vs2.v, rs1.v, false, true); +}, +{ + vd = fsgnj32(vs2.v, rs1.v, false, true); +}, +{ + vd = fsgnj64(vs2.v, rs1.v, false, true); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfsgnjx_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfsgnjx_vv.h new file mode 100644 index 0000000000..b04b8454ac --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfsgnjx_vv.h @@ -0,0 +1,11 @@ +// vfsgnx +VI_VFP_VV_LOOP +({ + vd = fsgnj16(vs2.v, vs1.v, false, true); +}, +{ + vd = fsgnj32(vs2.v, vs1.v, false, true); +}, +{ + vd = fsgnj64(vs2.v, vs1.v, false, true); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfslide1down_vf.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfslide1down_vf.h new file mode 100644 index 0000000000..40f3c18151 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfslide1down_vf.h @@ -0,0 +1,36 @@ +//vfslide1down.vf vd, vs2, rs1 +VI_CHECK_SLIDE(false); + +VI_VFP_LOOP_BASE +if (i != vl - 1) { + switch (P.VU.vsew) { + case e16: { + VI_XI_SLIDEDOWN_PARAMS(e16, 1); + vd = vs2; + } + break; + case e32: { + VI_XI_SLIDEDOWN_PARAMS(e32, 1); + vd = vs2; + } + break; + case e64: { + VI_XI_SLIDEDOWN_PARAMS(e64, 1); + vd = vs2; + } + break; + } +} else { + switch (P.VU.vsew) { + case e16: + P.VU.elt<float16_t>(rd_num, vl - 1, true) = FRS1_H; + break; + case e32: + P.VU.elt<float32_t>(rd_num, vl - 1, true) = FRS1_F; + break; + case e64: + P.VU.elt<float64_t>(rd_num, vl - 1, true) = FRS1_D; + break; + } +} +VI_VFP_LOOP_END diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfslide1up_vf.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfslide1up_vf.h new file mode 100644 index 0000000000..4e4e499abb --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfslide1up_vf.h @@ -0,0 +1,36 @@ +//vfslide1up.vf vd, vs2, rs1 +VI_CHECK_SLIDE(true); + +VI_VFP_LOOP_BASE +if (i != 0) { + switch (P.VU.vsew) { + case e16: { + VI_XI_SLIDEUP_PARAMS(e16, 1); + vd = vs2; + } + break; + case e32: { + VI_XI_SLIDEUP_PARAMS(e32, 1); + vd = vs2; + } + break; + case e64: { + VI_XI_SLIDEUP_PARAMS(e64, 1); + vd = vs2; + } + break; + } +} else { + switch (P.VU.vsew) { + case e16: + P.VU.elt<float16_t>(rd_num, 0, true) = FRS1_H; + break; + case e32: + P.VU.elt<float32_t>(rd_num, 0, true) = FRS1_F; + break; + case e64: + P.VU.elt<float64_t>(rd_num, 0, true) = FRS1_D; + break; + } +} +VI_VFP_LOOP_END diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfsqrt_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfsqrt_v.h new file mode 100644 index 0000000000..86f0148d4b --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfsqrt_v.h @@ -0,0 +1,11 @@ +// vsqrt.v vd, vd2, vm +VI_VFP_V_LOOP +({ + vd = f16_sqrt(vs2); +}, +{ + vd = f32_sqrt(vs2); +}, +{ + vd = f64_sqrt(vs2); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfsub_vf.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfsub_vf.h new file mode 100644 index 0000000000..fc6877ca5a --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfsub_vf.h @@ -0,0 +1,11 @@ +// vfsub.vf vd, vs2, rs1 +VI_VFP_VF_LOOP +({ + vd = f16_sub(vs2, rs1); +}, +{ + vd = f32_sub(vs2, rs1); +}, +{ + vd = f64_sub(vs2, rs1); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfsub_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfsub_vv.h new file mode 100644 index 0000000000..b0403f1180 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfsub_vv.h @@ -0,0 +1,11 @@ +// vfsub.vv vd, vs2, vs1 +VI_VFP_VV_LOOP +({ + vd = f16_sub(vs2, vs1); +}, +{ + vd = f32_sub(vs2, vs1); +}, +{ + vd = f64_sub(vs2, vs1); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfwadd_vf.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfwadd_vf.h new file mode 100644 index 0000000000..b8249001e0 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfwadd_vf.h @@ -0,0 +1,8 @@ +// vfwadd.vf vd, vs2, rs1 +VI_VFP_VF_LOOP_WIDE +({ + vd = f32_add(vs2, rs1); +}, +{ + vd = f64_add(vs2, rs1); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfwadd_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfwadd_vv.h new file mode 100644 index 0000000000..7255a50e13 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfwadd_vv.h @@ -0,0 +1,8 @@ +// vfwadd.vv vd, vs2, vs1 +VI_VFP_VV_LOOP_WIDE +({ + vd = f32_add(vs2, vs1); +}, +{ + vd = f64_add(vs2, vs1); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfwadd_wf.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfwadd_wf.h new file mode 100644 index 0000000000..021b17f049 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfwadd_wf.h @@ -0,0 +1,8 @@ +// vfwadd.wf vd, vs2, vs1 +VI_VFP_WF_LOOP_WIDE +({ + vd = f32_add(vs2, rs1); +}, +{ + vd = f64_add(vs2, rs1); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfwadd_wv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfwadd_wv.h new file mode 100644 index 0000000000..c1ed038925 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfwadd_wv.h @@ -0,0 +1,8 @@ +// vfwadd.wv vd, vs2, vs1 +VI_VFP_WV_LOOP_WIDE +({ + vd = f32_add(vs2, vs1); +}, +{ + vd = f64_add(vs2, vs1); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfwcvt_f_f_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfwcvt_f_f_v.h new file mode 100644 index 0000000000..111a231b7e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfwcvt_f_f_v.h @@ -0,0 +1,7 @@ +// vfwcvt.f.f.v vd, vs2, vm +VI_VFP_WCVT_FP_TO_FP( + { vd = f16_to_f32(vs2); }, // BODY16 + { vd = f32_to_f64(vs2); }, // BODY32 + { require_extension(EXT_ZVFHMIN); }, // CHECK16 + { require_extension('D'); } // CHECK32 +) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfwcvt_f_x_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfwcvt_f_x_v.h new file mode 100644 index 0000000000..c7678dcc95 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfwcvt_f_x_v.h @@ -0,0 +1,10 @@ +// vfwcvt.f.x.v vd, vs2, vm +VI_VFP_WCVT_INT_TO_FP( + { vd = i32_to_f16(vs2); }, // BODY8 + { vd = i32_to_f32(vs2); }, // BODY16 + { vd = i32_to_f64(vs2); }, // BODY32 + { require(p->extension_enabled(EXT_ZVFH)); }, // CHECK8 + { require_extension('F'); }, // CHECK16 + { require_extension('D'); }, // CHECK32 + int // sign +) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfwcvt_f_xu_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfwcvt_f_xu_v.h new file mode 100644 index 0000000000..e3b7e9f8b8 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfwcvt_f_xu_v.h @@ -0,0 +1,10 @@ +// vfwcvt.f.xu.v vd, vs2, vm +VI_VFP_WCVT_INT_TO_FP( + { vd = ui32_to_f16(vs2); }, // BODY8 + { vd = ui32_to_f32(vs2); }, // BODY16 + { vd = ui32_to_f64(vs2); }, // BODY32 + { require(p->extension_enabled(EXT_ZVFH)); }, // CHECK8 + { require_extension('F'); }, // CHECK16 + { require_extension('D'); }, // CHECK32 + uint // sign +) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfwcvt_rtz_x_f_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfwcvt_rtz_x_f_v.h new file mode 100644 index 0000000000..9caf617db3 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfwcvt_rtz_x_f_v.h @@ -0,0 +1,8 @@ +// vfwcvt.rtz.x.f.v vd, vs2, vm +VI_VFP_WCVT_FP_TO_INT( + { vd = f16_to_i32(vs2, softfloat_round_minMag, true); }, // BODY16 + { vd = f32_to_i64(vs2, softfloat_round_minMag, true); }, // BODY32 + { require_extension(EXT_ZVFH); }, // CHECK16 + { require_extension('F'); }, // CHECK32 + int // sign +) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfwcvt_rtz_xu_f_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfwcvt_rtz_xu_f_v.h new file mode 100644 index 0000000000..a25d847637 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfwcvt_rtz_xu_f_v.h @@ -0,0 +1,8 @@ +// vfwcvt.rtz,xu.f.v vd, vs2, vm +VI_VFP_WCVT_FP_TO_INT( + { vd = f16_to_ui32(vs2, softfloat_round_minMag, true); }, // BODY16 + { vd = f32_to_ui64(vs2, softfloat_round_minMag, true); }, // BODY32 + { require_extension(EXT_ZVFH); }, // CHECK16 + { require_extension('F'); }, // CHECK32 + uint // sign +) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfwcvt_x_f_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfwcvt_x_f_v.h new file mode 100644 index 0000000000..2d536adbad --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfwcvt_x_f_v.h @@ -0,0 +1,8 @@ +// vfwcvt.x.f.v vd, vs2, vm +VI_VFP_WCVT_FP_TO_INT( + { vd = f16_to_i32(vs2, softfloat_roundingMode, true); }, // BODY16 + { vd = f32_to_i64(vs2, softfloat_roundingMode, true); }, // BODY32 + { require_extension(EXT_ZVFH); }, // CHECK16 + { require_extension('F'); }, // CHECK32 + int // sign +) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfwcvt_xu_f_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfwcvt_xu_f_v.h new file mode 100644 index 0000000000..37201f5b2c --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfwcvt_xu_f_v.h @@ -0,0 +1,8 @@ +// vfwcvt.xu.f.v vd, vs2, vm +VI_VFP_WCVT_FP_TO_INT( + { vd = f16_to_ui32(vs2, softfloat_roundingMode, true); }, // BODY16 + { vd = f32_to_ui64(vs2, softfloat_roundingMode, true); }, // BODY32 + { require_extension(EXT_ZVFH); }, // CHECK16 + { require_extension('F'); }, // CHECK32 + uint // sign +) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfwmacc_vf.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfwmacc_vf.h new file mode 100644 index 0000000000..441fa0a791 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfwmacc_vf.h @@ -0,0 +1,8 @@ +// vfwmacc.vf vd, vs2, rs1 +VI_VFP_VF_LOOP_WIDE +({ + vd = f32_mulAdd(rs1, vs2, vd); +}, +{ + vd = f64_mulAdd(rs1, vs2, vd); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfwmacc_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfwmacc_vv.h new file mode 100644 index 0000000000..a654198bfd --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfwmacc_vv.h @@ -0,0 +1,8 @@ +// vfwmacc.vv vd, vs2, vs1 +VI_VFP_VV_LOOP_WIDE +({ + vd = f32_mulAdd(vs1, vs2, vd); +}, +{ + vd = f64_mulAdd(vs1, vs2, vd); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfwmsac_vf.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfwmsac_vf.h new file mode 100644 index 0000000000..18010ff490 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfwmsac_vf.h @@ -0,0 +1,8 @@ +// vfwmsac.vf vd, vs2, rs1 +VI_VFP_VF_LOOP_WIDE +({ + vd = f32_mulAdd(rs1, vs2, f32(vd.v ^ F32_SIGN)); +}, +{ + vd = f64_mulAdd(rs1, vs2, f64(vd.v ^ F64_SIGN)); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfwmsac_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfwmsac_vv.h new file mode 100644 index 0000000000..9dc4073fef --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfwmsac_vv.h @@ -0,0 +1,8 @@ +// vfwmsac.vv vd, vs2, vs1 +VI_VFP_VV_LOOP_WIDE +({ + vd = f32_mulAdd(vs1, vs2, f32(vd.v ^ F32_SIGN)); +}, +{ + vd = f64_mulAdd(vs1, vs2, f64(vd.v ^ F64_SIGN)); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfwmul_vf.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfwmul_vf.h new file mode 100644 index 0000000000..2bb543f63a --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfwmul_vf.h @@ -0,0 +1,8 @@ +// vfwmul.vf vd, vs2, rs1 +VI_VFP_VF_LOOP_WIDE +({ + vd = f32_mul(vs2, rs1); +}, +{ + vd = f64_mul(vs2, rs1); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfwmul_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfwmul_vv.h new file mode 100644 index 0000000000..2ce38e62c1 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfwmul_vv.h @@ -0,0 +1,8 @@ +// vfwmul.vv vd, vs2, vs1 +VI_VFP_VV_LOOP_WIDE +({ + vd = f32_mul(vs2, vs1); +}, +{ + vd = f64_mul(vs2, vs1); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfwnmacc_vf.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfwnmacc_vf.h new file mode 100644 index 0000000000..038bda08ca --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfwnmacc_vf.h @@ -0,0 +1,8 @@ +// vfwnmacc.vf vd, vs2, rs1 +VI_VFP_VF_LOOP_WIDE +({ + vd = f32_mulAdd(f32(rs1.v ^ F32_SIGN), vs2, f32(vd.v ^ F32_SIGN)); +}, +{ + vd = f64_mulAdd(f64(rs1.v ^ F64_SIGN), vs2, f64(vd.v ^ F64_SIGN)); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfwnmacc_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfwnmacc_vv.h new file mode 100644 index 0000000000..bf863e04c2 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfwnmacc_vv.h @@ -0,0 +1,8 @@ +// vfwnmacc.vv vd, vs2, vs1 +VI_VFP_VV_LOOP_WIDE +({ + vd = f32_mulAdd(f32(vs1.v ^ F32_SIGN), vs2, f32(vd.v ^ F32_SIGN)); +}, +{ + vd = f64_mulAdd(f64(vs1.v ^ F64_SIGN), vs2, f64(vd.v ^ F64_SIGN)); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfwnmsac_vf.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfwnmsac_vf.h new file mode 100644 index 0000000000..1e288e1b91 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfwnmsac_vf.h @@ -0,0 +1,8 @@ +// vfwnmacc.vf vd, vs2, rs1 +VI_VFP_VF_LOOP_WIDE +({ + vd = f32_mulAdd(f32(rs1.v ^ F32_SIGN), vs2, vd); +}, +{ + vd = f64_mulAdd(f64(rs1.v ^ F64_SIGN), vs2, vd); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfwnmsac_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfwnmsac_vv.h new file mode 100644 index 0000000000..ce97749e1c --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfwnmsac_vv.h @@ -0,0 +1,8 @@ +// vfwnmsac.vv vd, vs2, vs1 +VI_VFP_VV_LOOP_WIDE +({ + vd = f32_mulAdd(f32(vs1.v ^ F32_SIGN), vs2, vd); +}, +{ + vd = f64_mulAdd(f64(vs1.v ^ F64_SIGN), vs2, vd); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfwredosum_vs.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfwredosum_vs.h new file mode 100644 index 0000000000..1f42d8ff2f --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfwredosum_vs.h @@ -0,0 +1,9 @@ +// vfwredosum.vs vd, vs2, vs1 +bool is_propagate = false; +VI_VFP_VV_LOOP_WIDE_REDUCTION +({ + vd_0 = f32_add(vd_0, vs2); +}, +{ + vd_0 = f64_add(vd_0, vs2); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfwredusum_vs.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfwredusum_vs.h new file mode 100644 index 0000000000..4ef28969dc --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfwredusum_vs.h @@ -0,0 +1,9 @@ +// vfwredsum.vs vd, vs2, vs1 +bool is_propagate = true; +VI_VFP_VV_LOOP_WIDE_REDUCTION +({ + vd_0 = f32_add(vd_0, vs2); +}, +{ + vd_0 = f64_add(vd_0, vs2); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfwsub_vf.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfwsub_vf.h new file mode 100644 index 0000000000..8c37688419 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfwsub_vf.h @@ -0,0 +1,8 @@ +// vfwsub.vf vd, vs2, rs1 +VI_VFP_VF_LOOP_WIDE +({ + vd = f32_sub(vs2, rs1); +}, +{ + vd = f64_sub(vs2, rs1); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfwsub_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfwsub_vv.h new file mode 100644 index 0000000000..ce08e36af7 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfwsub_vv.h @@ -0,0 +1,8 @@ +// vfwsub.vv vd, vs2, vs1 +VI_VFP_VV_LOOP_WIDE +({ + vd = f32_sub(vs2, vs1); +}, +{ + vd = f64_sub(vs2, vs1); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfwsub_wf.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfwsub_wf.h new file mode 100644 index 0000000000..f6f47ca5cf --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfwsub_wf.h @@ -0,0 +1,8 @@ +// vfwsub.wf vd, vs2, rs1 +VI_VFP_WF_LOOP_WIDE +({ + vd = f32_sub(vs2, rs1); +}, +{ + vd = f64_sub(vs2, rs1); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vfwsub_wv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vfwsub_wv.h new file mode 100644 index 0000000000..eef904dcc2 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vfwsub_wv.h @@ -0,0 +1,8 @@ +// vfwsub.wv vd, vs2, vs1 +VI_VFP_WV_LOOP_WIDE +({ + vd = f32_sub(vs2, vs1); +}, +{ + vd = f64_sub(vs2, vs1); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vid_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vid_v.h new file mode 100644 index 0000000000..510132def7 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vid_v.h @@ -0,0 +1,28 @@ +// vmpopc rd, vs2, vm +require(P.VU.vsew >= e8 && P.VU.vsew <= e64); +require_vector(true); +reg_t sew = P.VU.vsew; +reg_t rd_num = insn.rd(); +require_align(rd_num, P.VU.vflmul); +require_vm; + +for (reg_t i = P.VU.vstart->read() ; i < P.VU.vl->read(); ++i) { + VI_LOOP_ELEMENT_SKIP(); + + switch (sew) { + case e8: + P.VU.elt<uint8_t>(rd_num, i, true) = i; + break; + case e16: + P.VU.elt<uint16_t>(rd_num, i, true) = i; + break; + case e32: + P.VU.elt<uint32_t>(rd_num, i, true) = i; + break; + default: + P.VU.elt<uint64_t>(rd_num, i, true) = i; + break; + } +} + +P.VU.vstart->write(0); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/viota_m.h b/vendor/riscv/riscv-isa-sim/riscv/insns/viota_m.h new file mode 100644 index 0000000000..1ee92295ac --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/viota_m.h @@ -0,0 +1,52 @@ +// vmpopc rd, vs2, vm +require(P.VU.vsew >= e8 && P.VU.vsew <= e64); +require_vector(true); +reg_t vl = P.VU.vl->read(); +reg_t sew = P.VU.vsew; +reg_t rd_num = insn.rd(); +reg_t rs2_num = insn.rs2(); +require(P.VU.vstart->read() == 0); +require_vm; +require_align(rd_num, P.VU.vflmul); +require_noover(rd_num, P.VU.vflmul, rs2_num, 1); + +int cnt = 0; +for (reg_t i = 0; i < vl; ++i) { + const int midx = i / 64; + const int mpos = i % 64; + + bool vs2_lsb = ((P.VU.elt<uint64_t>(rs2_num, midx) >> mpos) & 0x1) == 1; + bool do_mask = (P.VU.elt<uint64_t>(0, midx) >> mpos) & 0x1; + + bool has_one = false; + if (insn.v_vm() == 1 || (insn.v_vm() == 0 && do_mask)) { + if (vs2_lsb) { + has_one = true; + } + } + + bool use_ori = (insn.v_vm() == 0) && !do_mask; + switch (sew) { + case e8: + P.VU.elt<uint8_t>(rd_num, i, true) = use_ori ? + P.VU.elt<uint8_t>(rd_num, i) : cnt; + break; + case e16: + P.VU.elt<uint16_t>(rd_num, i, true) = use_ori ? + P.VU.elt<uint16_t>(rd_num, i) : cnt; + break; + case e32: + P.VU.elt<uint32_t>(rd_num, i, true) = use_ori ? + P.VU.elt<uint32_t>(rd_num, i) : cnt; + break; + default: + P.VU.elt<uint64_t>(rd_num, i, true) = use_ori ? + P.VU.elt<uint64_t>(rd_num, i) : cnt; + break; + } + + if (has_one) { + cnt++; + } +} + diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vl1re16_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vl1re16_v.h new file mode 100644 index 0000000000..220e83e6bb --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vl1re16_v.h @@ -0,0 +1,2 @@ +// vl1re16.v vd, (rs1) +VI_LD_WHOLE(uint16); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vl1re32_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vl1re32_v.h new file mode 100644 index 0000000000..e72ca02a3d --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vl1re32_v.h @@ -0,0 +1,2 @@ +// vl1re32.v vd, (rs1) +VI_LD_WHOLE(uint32); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vl1re64_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vl1re64_v.h new file mode 100644 index 0000000000..265701a06f --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vl1re64_v.h @@ -0,0 +1,2 @@ +// vl1re64.v vd, (rs1) +VI_LD_WHOLE(uint64); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vl1re8_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vl1re8_v.h new file mode 100644 index 0000000000..b4ce661688 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vl1re8_v.h @@ -0,0 +1,2 @@ +// vl1re8.v vd, (rs1) +VI_LD_WHOLE(uint8); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vl2re16_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vl2re16_v.h new file mode 100644 index 0000000000..2846edd980 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vl2re16_v.h @@ -0,0 +1,2 @@ +// vl2e16.v vd, (rs1) +VI_LD_WHOLE(uint16); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vl2re32_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vl2re32_v.h new file mode 100644 index 0000000000..5cea835524 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vl2re32_v.h @@ -0,0 +1,2 @@ +// vl2re32.v vd, (rs1) +VI_LD_WHOLE(uint32); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vl2re64_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vl2re64_v.h new file mode 100644 index 0000000000..efdf2ce2ac --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vl2re64_v.h @@ -0,0 +1,2 @@ +// vl2re64.v vd, (rs1) +VI_LD_WHOLE(uint64); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vl2re8_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vl2re8_v.h new file mode 100644 index 0000000000..fcc3c4c057 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vl2re8_v.h @@ -0,0 +1,2 @@ +// vl2re8.v vd, (rs1) +VI_LD_WHOLE(uint8); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vl4re16_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vl4re16_v.h new file mode 100644 index 0000000000..0363418319 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vl4re16_v.h @@ -0,0 +1,2 @@ +// vl4re16.v vd, (rs1) +VI_LD_WHOLE(uint16); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vl4re32_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vl4re32_v.h new file mode 100644 index 0000000000..e37cc1ab7b --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vl4re32_v.h @@ -0,0 +1,2 @@ +// vl4re32.v vd, (rs1) +VI_LD_WHOLE(uint32); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vl4re64_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vl4re64_v.h new file mode 100644 index 0000000000..11486f5d1e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vl4re64_v.h @@ -0,0 +1,2 @@ +// vl4re64.v vd, (rs1) +VI_LD_WHOLE(uint64); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vl4re8_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vl4re8_v.h new file mode 100644 index 0000000000..f9ce3ff7c7 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vl4re8_v.h @@ -0,0 +1,2 @@ +// vl4re8.v vd, (rs1) +VI_LD_WHOLE(uint8); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vl8re16_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vl8re16_v.h new file mode 100644 index 0000000000..0b3f1413ba --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vl8re16_v.h @@ -0,0 +1,2 @@ +// vl8re16.v vd, (rs1) +VI_LD_WHOLE(uint16); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vl8re32_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vl8re32_v.h new file mode 100644 index 0000000000..3372b89d05 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vl8re32_v.h @@ -0,0 +1,2 @@ +// vl8re32.v vd, (rs1) +VI_LD_WHOLE(uint32); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vl8re64_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vl8re64_v.h new file mode 100644 index 0000000000..f9a9ca981f --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vl8re64_v.h @@ -0,0 +1,2 @@ +// vl8re64.v vd, (rs1) +VI_LD_WHOLE(uint64); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vl8re8_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vl8re8_v.h new file mode 100644 index 0000000000..ee05e81a9d --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vl8re8_v.h @@ -0,0 +1,2 @@ +// vl8re8.v vd, (rs1) +VI_LD_WHOLE(uint8); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vle16_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vle16_v.h new file mode 100644 index 0000000000..70bf39fb06 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vle16_v.h @@ -0,0 +1,2 @@ +// vle16.v and vlseg[2-8]e16.v +VI_LD(0, (i * nf + fn), int16, false); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vle16ff_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vle16ff_v.h new file mode 100644 index 0000000000..53c8889137 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vle16ff_v.h @@ -0,0 +1,2 @@ +// vle16ff.v and vlseg[2-8]e16ff.v +VI_LDST_FF(int16); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vle32_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vle32_v.h new file mode 100644 index 0000000000..f1d0e73cd4 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vle32_v.h @@ -0,0 +1,2 @@ +// vle32.v and vlseg[2-8]e32.v +VI_LD(0, (i * nf + fn), int32, false); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vle32ff_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vle32ff_v.h new file mode 100644 index 0000000000..7d03d7ddd5 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vle32ff_v.h @@ -0,0 +1,2 @@ +// vle32ff.v and vlseg[2-8]e32ff.v +VI_LDST_FF(int32); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vle64_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vle64_v.h new file mode 100644 index 0000000000..86deb5cb6a --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vle64_v.h @@ -0,0 +1,2 @@ +// vle64.v and vlseg[2-8]e64.v +VI_LD(0, (i * nf + fn), int64, false); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vle64ff_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vle64ff_v.h new file mode 100644 index 0000000000..39996da6f1 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vle64ff_v.h @@ -0,0 +1,2 @@ +// vle64ff.v and vlseg[2-8]e64ff.v +VI_LDST_FF(int64); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vle8_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vle8_v.h new file mode 100644 index 0000000000..ffe17c3a22 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vle8_v.h @@ -0,0 +1,2 @@ +// vle8.v and vlseg[2-8]e8.v +VI_LD(0, (i * nf + fn), int8, false); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vle8ff_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vle8ff_v.h new file mode 100644 index 0000000000..b56d1d339c --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vle8ff_v.h @@ -0,0 +1,2 @@ +// vle8ff.v and vlseg[2-8]e8ff.v +VI_LDST_FF(int8); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vlm_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vlm_v.h new file mode 100644 index 0000000000..6d3f83aa8f --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vlm_v.h @@ -0,0 +1,2 @@ +// vle1.v and vlseg[2-8]e8.v +VI_LD(0, (i * nf + fn), int8, true); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vloxei16_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vloxei16_v.h new file mode 100644 index 0000000000..6e4ed49b57 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vloxei16_v.h @@ -0,0 +1,2 @@ +// vlxei16.v and vlxseg[2-8]e16.v +VI_LD_INDEX(e16, true); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vloxei32_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vloxei32_v.h new file mode 100644 index 0000000000..a7da8ff035 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vloxei32_v.h @@ -0,0 +1,2 @@ +// vlxe32.v and vlxseg[2-8]ei32.v +VI_LD_INDEX(e32, true); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vloxei64_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vloxei64_v.h new file mode 100644 index 0000000000..067224e4c5 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vloxei64_v.h @@ -0,0 +1,3 @@ +// vlxei64.v and vlxseg[2-8]ei64.v +VI_LD_INDEX(e64, true); + diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vloxei8_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vloxei8_v.h new file mode 100644 index 0000000000..d27304996b --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vloxei8_v.h @@ -0,0 +1,2 @@ +// vlxei8.v and vlxseg[2-8]ei8.v +VI_LD_INDEX(e8, true); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vlse16_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vlse16_v.h new file mode 100644 index 0000000000..5ac23a9894 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vlse16_v.h @@ -0,0 +1,2 @@ +// vlse16.v and vlsseg[2-8]e16.v +VI_LD(i * RS2, fn, int16, false); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vlse32_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vlse32_v.h new file mode 100644 index 0000000000..cfd74fb9b4 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vlse32_v.h @@ -0,0 +1,2 @@ +// vlse32.v and vlsseg[2-8]e32.v +VI_LD(i * RS2, fn, int32, false); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vlse64_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vlse64_v.h new file mode 100644 index 0000000000..2e33963803 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vlse64_v.h @@ -0,0 +1,2 @@ +// vlse64.v and vlsseg[2-8]e64.v +VI_LD(i * RS2, fn, int64, false); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vlse8_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vlse8_v.h new file mode 100644 index 0000000000..275f022414 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vlse8_v.h @@ -0,0 +1,2 @@ +// vlse8.v and vlsseg[2-8]e8.v +VI_LD(i * RS2, fn, int8, false); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vluxei16_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vluxei16_v.h new file mode 100644 index 0000000000..6e4ed49b57 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vluxei16_v.h @@ -0,0 +1,2 @@ +// vlxei16.v and vlxseg[2-8]e16.v +VI_LD_INDEX(e16, true); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vluxei32_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vluxei32_v.h new file mode 100644 index 0000000000..a7da8ff035 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vluxei32_v.h @@ -0,0 +1,2 @@ +// vlxe32.v and vlxseg[2-8]ei32.v +VI_LD_INDEX(e32, true); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vluxei64_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vluxei64_v.h new file mode 100644 index 0000000000..067224e4c5 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vluxei64_v.h @@ -0,0 +1,3 @@ +// vlxei64.v and vlxseg[2-8]ei64.v +VI_LD_INDEX(e64, true); + diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vluxei8_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vluxei8_v.h new file mode 100644 index 0000000000..d27304996b --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vluxei8_v.h @@ -0,0 +1,2 @@ +// vlxei8.v and vlxseg[2-8]ei8.v +VI_LD_INDEX(e8, true); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmacc_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmacc_vv.h new file mode 100644 index 0000000000..e6ec93ff71 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmacc_vv.h @@ -0,0 +1,5 @@ +// vmacc.vv: vd[i] = +(vs1[i] * vs2[i]) + vd[i] +VI_VV_LOOP +({ + vd = vs1 * vs2 + vd; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmacc_vx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmacc_vx.h new file mode 100644 index 0000000000..d40b264a05 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmacc_vx.h @@ -0,0 +1,5 @@ +// vmacc.vx: vd[i] = +(x[rs1] * vs2[i]) + vd[i] +VI_VX_LOOP +({ + vd = rs1 * vs2 + vd; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmadc_vi.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmadc_vi.h new file mode 100644 index 0000000000..37da8adf52 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmadc_vi.h @@ -0,0 +1,2 @@ +// vmadc.vi vd, vs2, simm5 +#include "vmadc_vim.h" diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmadc_vim.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmadc_vim.h new file mode 100644 index 0000000000..a1f78fff03 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmadc_vim.h @@ -0,0 +1,5 @@ +// vmadc.vim vd, vs2, simm5, v0 +VI_XI_LOOP_CARRY +({ + res = (((op_mask & simm5) + (op_mask & vs2) + carry) >> sew) & 0x1u; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmadc_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmadc_vv.h new file mode 100644 index 0000000000..e120fe638d --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmadc_vv.h @@ -0,0 +1,2 @@ +// vmadc.vvm vd, vs2, rs1 +#include "vmadc_vvm.h" diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmadc_vvm.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmadc_vvm.h new file mode 100644 index 0000000000..96a7f2cb03 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmadc_vvm.h @@ -0,0 +1,5 @@ +// vmadc.vvm vd, vs2, rs1, v0 +VI_VV_LOOP_CARRY +({ + res = (((op_mask & vs1) + (op_mask & vs2) + carry) >> sew) & 0x1u; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmadc_vx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmadc_vx.h new file mode 100644 index 0000000000..39c20b1e80 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmadc_vx.h @@ -0,0 +1,2 @@ +// vadc.vx vd, vs2, rs1 +#include "vmadc_vxm.h" diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmadc_vxm.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmadc_vxm.h new file mode 100644 index 0000000000..1561d85865 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmadc_vxm.h @@ -0,0 +1,5 @@ +// vadc.vx vd, vs2, rs1, v0 +VI_XI_LOOP_CARRY +({ + res = (((op_mask & rs1) + (op_mask & vs2) + carry) >> sew) & 0x1u; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmadd_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmadd_vv.h new file mode 100644 index 0000000000..a1c0d2ed64 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmadd_vv.h @@ -0,0 +1,5 @@ +// vmadd: vd[i] = (vd[i] * vs1[i]) + vs2[i] +VI_VV_LOOP +({ + vd = vd * vs1 + vs2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmadd_vx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmadd_vx.h new file mode 100644 index 0000000000..1a8a001593 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmadd_vx.h @@ -0,0 +1,5 @@ +// vmadd: vd[i] = (vd[i] * x[rs1]) + vs2[i] +VI_VX_LOOP +({ + vd = vd * rs1 + vs2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmand_mm.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmand_mm.h new file mode 100644 index 0000000000..04615c60fc --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmand_mm.h @@ -0,0 +1,2 @@ +// vmand.mm vd, vs2, vs1 +VI_LOOP_MASK(vs2 & vs1); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmandn_mm.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmandn_mm.h new file mode 100644 index 0000000000..e9a87cf4be --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmandn_mm.h @@ -0,0 +1,2 @@ +// vmandn.mm vd, vs2, vs1 +VI_LOOP_MASK(vs2 & ~vs1); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmax_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmax_vv.h new file mode 100644 index 0000000000..b9f15c5f18 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmax_vv.h @@ -0,0 +1,10 @@ +// vmax.vv vd, vs2, vs1, vm # Vector-vector +VI_VV_LOOP +({ + if (vs1 >= vs2) { + vd = vs1; + } else { + vd = vs2; + } + +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmax_vx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmax_vx.h new file mode 100644 index 0000000000..06f3f43160 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmax_vx.h @@ -0,0 +1,10 @@ +// vmax.vx vd, vs2, rs1, vm # vector-scalar +VI_VX_LOOP +({ + if (rs1 >= vs2) { + vd = rs1; + } else { + vd = vs2; + } + +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmaxu_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmaxu_vv.h new file mode 100644 index 0000000000..4e6868d19e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmaxu_vv.h @@ -0,0 +1,9 @@ +// vmaxu.vv vd, vs2, vs1, vm # Vector-vector +VI_VV_ULOOP +({ + if (vs1 >= vs2) { + vd = vs1; + } else { + vd = vs2; + } +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmaxu_vx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmaxu_vx.h new file mode 100644 index 0000000000..cab89188f7 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmaxu_vx.h @@ -0,0 +1,9 @@ +// vmaxu.vx vd, vs2, rs1, vm # vector-scalar +VI_VX_ULOOP +({ + if (rs1 >= vs2) { + vd = rs1; + } else { + vd = vs2; + } +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmerge_vim.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmerge_vim.h new file mode 100644 index 0000000000..0b2fac9817 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmerge_vim.h @@ -0,0 +1,5 @@ +// vmerge.vim vd, vs2, simm5 +VI_VI_MERGE_LOOP +({ + vd = use_first ? simm5 : vs2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmerge_vvm.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmerge_vvm.h new file mode 100644 index 0000000000..b60c152691 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmerge_vvm.h @@ -0,0 +1,5 @@ +// vmerge.vvm vd, vs2, vs1 +VI_VV_MERGE_LOOP +({ + vd = use_first ? vs1 : vs2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmerge_vxm.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmerge_vxm.h new file mode 100644 index 0000000000..a22da8a139 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmerge_vxm.h @@ -0,0 +1,5 @@ +// vmerge.vxm vd, vs2, rs1 +VI_VX_MERGE_LOOP +({ + vd = use_first ? rs1 : vs2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmfeq_vf.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmfeq_vf.h new file mode 100644 index 0000000000..a4d7c50c4e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmfeq_vf.h @@ -0,0 +1,11 @@ +// vmfeq.vf vd, vs2, fs1 +VI_VFP_VF_LOOP_CMP +({ + res = f16_eq(vs2, rs1); +}, +{ + res = f32_eq(vs2, rs1); +}, +{ + res = f64_eq(vs2, rs1); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmfeq_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmfeq_vv.h new file mode 100644 index 0000000000..b08ce980f2 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmfeq_vv.h @@ -0,0 +1,11 @@ +// vmfeq.vv vd, vs2, vs1 +VI_VFP_VV_LOOP_CMP +({ + res = f16_eq(vs2, vs1); +}, +{ + res = f32_eq(vs2, vs1); +}, +{ + res = f64_eq(vs2, vs1); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmfge_vf.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmfge_vf.h new file mode 100644 index 0000000000..ab4df5ce10 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmfge_vf.h @@ -0,0 +1,11 @@ +// vmfge.vf vd, vs2, rs1 +VI_VFP_VF_LOOP_CMP +({ + res = f16_le(rs1, vs2); +}, +{ + res = f32_le(rs1, vs2); +}, +{ + res = f64_le(rs1, vs2); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmfgt_vf.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmfgt_vf.h new file mode 100644 index 0000000000..dcc3ea37c8 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmfgt_vf.h @@ -0,0 +1,11 @@ +// vmfgt.vf vd, vs2, rs1 +VI_VFP_VF_LOOP_CMP +({ + res = f16_lt(rs1, vs2); +}, +{ + res = f32_lt(rs1, vs2); +}, +{ + res = f64_lt(rs1, vs2); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmfle_vf.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmfle_vf.h new file mode 100644 index 0000000000..a942705d41 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmfle_vf.h @@ -0,0 +1,11 @@ +// vmfle.vf vd, vs2, rs1 +VI_VFP_VF_LOOP_CMP +({ + res = f16_le(vs2, rs1); +}, +{ + res = f32_le(vs2, rs1); +}, +{ + res = f64_le(vs2, rs1); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmfle_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmfle_vv.h new file mode 100644 index 0000000000..dd6f81dac6 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmfle_vv.h @@ -0,0 +1,11 @@ +// vmfle.vv vd, vs2, rs1 +VI_VFP_VV_LOOP_CMP +({ + res = f16_le(vs2, vs1); +}, +{ + res = f32_le(vs2, vs1); +}, +{ + res = f64_le(vs2, vs1); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmflt_vf.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmflt_vf.h new file mode 100644 index 0000000000..110dbd1b62 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmflt_vf.h @@ -0,0 +1,11 @@ +// vmflt.vf vd, vs2, rs1 +VI_VFP_VF_LOOP_CMP +({ + res = f16_lt(vs2, rs1); +}, +{ + res = f32_lt(vs2, rs1); +}, +{ + res = f64_lt(vs2, rs1); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmflt_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmflt_vv.h new file mode 100644 index 0000000000..35f8d702cd --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmflt_vv.h @@ -0,0 +1,11 @@ +// vmflt.vv vd, vs2, vs1 +VI_VFP_VV_LOOP_CMP +({ + res = f16_lt(vs2, vs1); +}, +{ + res = f32_lt(vs2, vs1); +}, +{ + res = f64_lt(vs2, vs1); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmfne_vf.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmfne_vf.h new file mode 100644 index 0000000000..1b61d57100 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmfne_vf.h @@ -0,0 +1,11 @@ +// vmfne.vf vd, vs2, rs1 +VI_VFP_VF_LOOP_CMP +({ + res = !f16_eq(vs2, rs1); +}, +{ + res = !f32_eq(vs2, rs1); +}, +{ + res = !f64_eq(vs2, rs1); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmfne_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmfne_vv.h new file mode 100644 index 0000000000..4447c3ccba --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmfne_vv.h @@ -0,0 +1,11 @@ +// vmfne.vv vd, vs2, rs1 +VI_VFP_VV_LOOP_CMP +({ + res = !f16_eq(vs2, vs1); +}, +{ + res = !f32_eq(vs2, vs1); +}, +{ + res = !f64_eq(vs2, vs1); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmin_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmin_vv.h new file mode 100644 index 0000000000..21da0b3c5b --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmin_vv.h @@ -0,0 +1,11 @@ +// vmin.vv vd, vs2, vs1, vm # Vector-vector +VI_VV_LOOP +({ + if (vs1 <= vs2) { + vd = vs1; + } else { + vd = vs2; + } + + +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmin_vx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmin_vx.h new file mode 100644 index 0000000000..3291776d05 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmin_vx.h @@ -0,0 +1,11 @@ +// vminx.vx vd, vs2, rs1, vm # vector-scalar +VI_VX_LOOP +({ + if (rs1 <= vs2) { + vd = rs1; + } else { + vd = vs2; + } + + +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vminu_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vminu_vv.h new file mode 100644 index 0000000000..c0ab1958d0 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vminu_vv.h @@ -0,0 +1,9 @@ +// vminu.vv vd, vs2, vs1, vm # Vector-vector +VI_VV_ULOOP +({ + if (vs1 <= vs2) { + vd = vs1; + } else { + vd = vs2; + } +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vminu_vx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vminu_vx.h new file mode 100644 index 0000000000..1055895ac3 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vminu_vx.h @@ -0,0 +1,10 @@ +// vminu.vx vd, vs2, rs1, vm # vector-scalar +VI_VX_ULOOP +({ + if (rs1 <= vs2) { + vd = rs1; + } else { + vd = vs2; + } + +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmnand_mm.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmnand_mm.h new file mode 100644 index 0000000000..5a3ab090ae --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmnand_mm.h @@ -0,0 +1,2 @@ +// vmnand.mm vd, vs2, vs1 +VI_LOOP_MASK(~(vs2 & vs1)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmnor_mm.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmnor_mm.h new file mode 100644 index 0000000000..ab933786c9 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmnor_mm.h @@ -0,0 +1,2 @@ +// vmnor.mm vd, vs2, vs1 +VI_LOOP_MASK(~(vs2 | vs1)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmor_mm.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmor_mm.h new file mode 100644 index 0000000000..32e71b934a --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmor_mm.h @@ -0,0 +1,2 @@ +// vmor.mm vd, vs2, vs1 +VI_LOOP_MASK(vs2 | vs1); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmorn_mm.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmorn_mm.h new file mode 100644 index 0000000000..23026f5cc5 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmorn_mm.h @@ -0,0 +1,2 @@ +// vmorn.mm vd, vs2, vs1 +VI_LOOP_MASK(vs2 | ~vs1); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmsbc_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmsbc_vv.h new file mode 100644 index 0000000000..a7bbba18ff --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmsbc_vv.h @@ -0,0 +1,2 @@ +// vmsbc.vv vd, vs2, rs1 +#include "vmsbc_vvm.h" diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmsbc_vvm.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmsbc_vvm.h new file mode 100644 index 0000000000..3225c62d66 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmsbc_vvm.h @@ -0,0 +1,5 @@ +// vmsbc.vvm vd, vs2, rs1, v0 +VI_VV_LOOP_CARRY +({ + res = (((op_mask & vs2) - (op_mask & vs1) - carry) >> sew) & 0x1u; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmsbc_vx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmsbc_vx.h new file mode 100644 index 0000000000..cc6b927955 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmsbc_vx.h @@ -0,0 +1,2 @@ +// vmsbc.vx vd, vs2, rs1 +#include "vmsbc_vxm.h" diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmsbc_vxm.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmsbc_vxm.h new file mode 100644 index 0000000000..8cc46bad31 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmsbc_vxm.h @@ -0,0 +1,5 @@ +// vmsbc.vxm vd, vs2, rs1, v0 +VI_XI_LOOP_CARRY +({ + res = (((op_mask & vs2) - (op_mask & rs1) - carry) >> sew) & 0x1u; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmsbf_m.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmsbf_m.h new file mode 100644 index 0000000000..1275872142 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmsbf_m.h @@ -0,0 +1,32 @@ +// vmsbf.m vd, vs2, vm +require(P.VU.vsew >= e8 && P.VU.vsew <= e64); +require_vector(true); +require(P.VU.vstart->read() == 0); +require_vm; +require(insn.rd() != insn.rs2()); + +reg_t vl = P.VU.vl->read(); +reg_t rd_num = insn.rd(); +reg_t rs2_num = insn.rs2(); + +bool has_one = false; +for (reg_t i = P.VU.vstart->read(); i < vl; ++i) { + const int midx = i / 64; + const int mpos = i % 64; + const uint64_t mmask = UINT64_C(1) << mpos; \ + + bool vs2_lsb = ((P.VU.elt<uint64_t>(rs2_num, midx) >> mpos) & 0x1) == 1; + bool do_mask = (P.VU.elt<uint64_t>(0, midx) >> mpos) & 0x1; + + + if (insn.v_vm() == 1 || (insn.v_vm() == 0 && do_mask)) { + auto &vd = P.VU.elt<uint64_t>(rd_num, midx, true); + uint64_t res = 0; + if (!has_one && !vs2_lsb) { + res = 1; + } else if (!has_one && vs2_lsb) { + has_one = true; + } + vd = (vd & ~mmask) | ((res << mpos) & mmask); + } +} diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmseq_vi.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmseq_vi.h new file mode 100644 index 0000000000..cfc16825f2 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmseq_vi.h @@ -0,0 +1,5 @@ +// vseq.vi vd, vs2, simm5 +VI_VI_LOOP_CMP +({ + res = simm5 == vs2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmseq_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmseq_vv.h new file mode 100644 index 0000000000..91fd204a50 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmseq_vv.h @@ -0,0 +1,6 @@ +// vseq.vv vd, vs2, vs1 +VI_VV_LOOP_CMP +({ + res = vs2 == vs1; +}) + diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmseq_vx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmseq_vx.h new file mode 100644 index 0000000000..ab63323134 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmseq_vx.h @@ -0,0 +1,5 @@ +// vseq.vx vd, vs2, rs1 +VI_VX_LOOP_CMP +({ + res = rs1 == vs2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmsgt_vi.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmsgt_vi.h new file mode 100644 index 0000000000..4f7dea8e4b --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmsgt_vi.h @@ -0,0 +1,5 @@ +// vsgt.vi vd, vs2, simm5 +VI_VI_LOOP_CMP +({ + res = vs2 > simm5; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmsgt_vx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmsgt_vx.h new file mode 100644 index 0000000000..5f24db6964 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmsgt_vx.h @@ -0,0 +1,5 @@ +// vsgt.vx vd, vs2, rs1 +VI_VX_LOOP_CMP +({ + res = vs2 > rs1; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmsgtu_vi.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmsgtu_vi.h new file mode 100644 index 0000000000..be28fee1e7 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmsgtu_vi.h @@ -0,0 +1,5 @@ +// vmsgtu.vi vd, vd2, simm5 +VI_VI_ULOOP_CMP +({ + res = vs2 > (insn.v_simm5() & (UINT64_MAX >> (64 - P.VU.vsew))); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmsgtu_vx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmsgtu_vx.h new file mode 100644 index 0000000000..7f39800804 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmsgtu_vx.h @@ -0,0 +1,5 @@ +// vsgtu.vx vd, vs2, rs1 +VI_VX_ULOOP_CMP +({ + res = vs2 > rs1; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmsif_m.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmsif_m.h new file mode 100644 index 0000000000..cbcbc2a681 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmsif_m.h @@ -0,0 +1,32 @@ +// vmsif.m rd, vs2, vm +require(P.VU.vsew >= e8 && P.VU.vsew <= e64); +require_vector(true); +require(P.VU.vstart->read() == 0); +require_vm; +require(insn.rd() != insn.rs2()); + +reg_t vl = P.VU.vl->read(); +reg_t rd_num = insn.rd(); +reg_t rs2_num = insn.rs2(); + +bool has_one = false; +for (reg_t i = P.VU.vstart->read(); i < vl; ++i) { + const int midx = i / 64; + const int mpos = i % 64; + const uint64_t mmask = UINT64_C(1) << mpos; \ + + bool vs2_lsb = ((P.VU.elt<uint64_t>(rs2_num, midx ) >> mpos) & 0x1) == 1; + bool do_mask = (P.VU.elt<uint64_t>(0, midx) >> mpos) & 0x1; + + if (insn.v_vm() == 1 || (insn.v_vm() == 0 && do_mask)) { + auto &vd = P.VU.elt<uint64_t>(rd_num, midx, true); + uint64_t res = 0; + if (!has_one && !vs2_lsb) { + res = 1; + } else if (!has_one && vs2_lsb) { + has_one = true; + res = 1; + } + vd = (vd & ~mmask) | ((res << mpos) & mmask); + } +} diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmsle_vi.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmsle_vi.h new file mode 100644 index 0000000000..f0f67d0213 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmsle_vi.h @@ -0,0 +1,5 @@ +// vsle.vi vd, vs2, simm5 +VI_VI_LOOP_CMP +({ + res = vs2 <= simm5; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmsle_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmsle_vv.h new file mode 100644 index 0000000000..30aba06d41 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmsle_vv.h @@ -0,0 +1,5 @@ +// vsle.vv vd, vs2, vs1 +VI_VV_LOOP_CMP +({ + res = vs2 <= vs1; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmsle_vx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmsle_vx.h new file mode 100644 index 0000000000..c26d59692e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmsle_vx.h @@ -0,0 +1,5 @@ +// vsle.vx vd, vs2, rs1 +VI_VX_LOOP_CMP +({ + res = vs2 <= rs1; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmsleu_vi.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmsleu_vi.h new file mode 100644 index 0000000000..0e66b781a0 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmsleu_vi.h @@ -0,0 +1,5 @@ +// vmsleu.vi vd, vs2, simm5 +VI_VI_ULOOP_CMP +({ + res = vs2 <= (insn.v_simm5() & (UINT64_MAX >> (64 - P.VU.vsew))); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmsleu_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmsleu_vv.h new file mode 100644 index 0000000000..0e460326f8 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmsleu_vv.h @@ -0,0 +1,5 @@ +// vsleu.vv vd, vs2, vs1 +VI_VV_ULOOP_CMP +({ + res = vs2 <= vs1; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmsleu_vx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmsleu_vx.h new file mode 100644 index 0000000000..935b17681c --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmsleu_vx.h @@ -0,0 +1,5 @@ +// vsleu.vx vd, vs2, rs1 +VI_VX_ULOOP_CMP +({ + res = vs2 <= rs1; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmslt_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmslt_vv.h new file mode 100644 index 0000000000..71e6f87f1f --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmslt_vv.h @@ -0,0 +1,5 @@ +// vslt.vv vd, vd2, vs1 +VI_VV_LOOP_CMP +({ + res = vs2 < vs1; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmslt_vx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmslt_vx.h new file mode 100644 index 0000000000..b32bb14537 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmslt_vx.h @@ -0,0 +1,5 @@ +// vslt.vx vd, vs2, vs1 +VI_VX_LOOP_CMP +({ + res = vs2 < rs1; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmsltu_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmsltu_vv.h new file mode 100644 index 0000000000..53a570ae9d --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmsltu_vv.h @@ -0,0 +1,5 @@ +// vsltu.vv vd, vs2, vs1 +VI_VV_ULOOP_CMP +({ + res = vs2 < vs1; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmsltu_vx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmsltu_vx.h new file mode 100644 index 0000000000..8082544876 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmsltu_vx.h @@ -0,0 +1,5 @@ +// vsltu.vx vd, vs2, vs1 +VI_VX_ULOOP_CMP +({ + res = vs2 < rs1; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmsne_vi.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmsne_vi.h new file mode 100644 index 0000000000..5e9758ef94 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmsne_vi.h @@ -0,0 +1,5 @@ +// vsne.vi vd, vs2, simm5 +VI_VI_LOOP_CMP +({ + res = vs2 != simm5; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmsne_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmsne_vv.h new file mode 100644 index 0000000000..e6a7174a48 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmsne_vv.h @@ -0,0 +1,5 @@ +// vneq.vv vd, vs2, vs1 +VI_VV_LOOP_CMP +({ + res = vs2 != vs1; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmsne_vx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmsne_vx.h new file mode 100644 index 0000000000..9e4c155387 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmsne_vx.h @@ -0,0 +1,5 @@ +// vsne.vx vd, vs2, rs1 +VI_VX_LOOP_CMP +({ + res = vs2 != rs1; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmsof_m.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmsof_m.h new file mode 100644 index 0000000000..9bd4f0c078 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmsof_m.h @@ -0,0 +1,30 @@ +// vmsof.m rd, vs2, vm +require(P.VU.vsew >= e8 && P.VU.vsew <= e64); +require_vector(true); +require(P.VU.vstart->read() == 0); +require_vm; +require(insn.rd() != insn.rs2()); + +reg_t vl = P.VU.vl->read(); +reg_t rd_num = insn.rd(); +reg_t rs2_num = insn.rs2(); + +bool has_one = false; +for (reg_t i = P.VU.vstart->read() ; i < vl; ++i) { + const int midx = i / 64; + const int mpos = i % 64; + const uint64_t mmask = UINT64_C(1) << mpos; \ + + bool vs2_lsb = ((P.VU.elt<uint64_t>(rs2_num, midx ) >> mpos) & 0x1) == 1; + bool do_mask = (P.VU.elt<uint64_t>(0, midx) >> mpos) & 0x1; + + if (insn.v_vm() == 1 || (insn.v_vm() == 0 && do_mask)) { + uint64_t &vd = P.VU.elt<uint64_t>(rd_num, midx, true); + uint64_t res = 0; + if (!has_one && vs2_lsb) { + has_one = true; + res = 1; + } + vd = (vd & ~mmask) | ((res << mpos) & mmask); + } +} diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmul_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmul_vv.h new file mode 100644 index 0000000000..a3278171dd --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmul_vv.h @@ -0,0 +1,5 @@ +// vmul vd, vs2, vs1 +VI_VV_LOOP +({ + vd = vs2 * vs1; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmul_vx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmul_vx.h new file mode 100644 index 0000000000..8d68390276 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmul_vx.h @@ -0,0 +1,5 @@ +// vmul vd, vs2, rs1 +VI_VX_LOOP +({ + vd = vs2 * rs1; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmulh_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmulh_vv.h new file mode 100644 index 0000000000..e861a3397a --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmulh_vv.h @@ -0,0 +1,5 @@ +// vmulh vd, vs2, vs1 +VI_VV_LOOP +({ + vd = ((int128_t)vs2 * vs1) >> sew; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmulh_vx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmulh_vx.h new file mode 100644 index 0000000000..b6b5503674 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmulh_vx.h @@ -0,0 +1,5 @@ +// vmulh vd, vs2, rs1 +VI_VX_LOOP +({ + vd = ((int128_t)vs2 * rs1) >> sew; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmulhsu_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmulhsu_vv.h new file mode 100644 index 0000000000..e1c0ba6052 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmulhsu_vv.h @@ -0,0 +1,4 @@ +// vmulhsu.vv vd, vs2, vs1 +VI_VV_SU_LOOP({ + vd = ((int128_t)vs2 * (uint128_t)vs1) >> sew; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmulhsu_vx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmulhsu_vx.h new file mode 100644 index 0000000000..4619ea896f --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmulhsu_vx.h @@ -0,0 +1,4 @@ +// vmulhsu.vx vd, vs2, rs1 +VI_VX_SU_LOOP({ + vd = ((int128_t)vs2 * (uint128_t)rs1) >> sew; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmulhu_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmulhu_vv.h new file mode 100644 index 0000000000..8e318edb75 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmulhu_vv.h @@ -0,0 +1,5 @@ +// vmulhu vd ,vs2, vs1 +VI_VV_ULOOP +({ + vd = ((uint128_t)vs2 * vs1) >> sew; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmulhu_vx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmulhu_vx.h new file mode 100644 index 0000000000..672ad32df2 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmulhu_vx.h @@ -0,0 +1,5 @@ +// vmulhu vd ,vs2, rs1 +VI_VX_ULOOP +({ + vd = ((uint128_t)vs2 * rs1) >> sew; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmv1r_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmv1r_v.h new file mode 100644 index 0000000000..bbdeab9a1d --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmv1r_v.h @@ -0,0 +1,2 @@ +// vmv1r.v vd, vs2 +#include "vmvnfr_v.h" diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmv2r_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmv2r_v.h new file mode 100644 index 0000000000..1ac8e09eb0 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmv2r_v.h @@ -0,0 +1,2 @@ +// vmv2r.v vd, vs2 +#include "vmvnfr_v.h" diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmv4r_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmv4r_v.h new file mode 100644 index 0000000000..2068731a9e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmv4r_v.h @@ -0,0 +1,2 @@ +// vmv4r.v vd, vs2 +#include "vmvnfr_v.h" diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmv8r_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmv8r_v.h new file mode 100644 index 0000000000..2b205fc79e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmv8r_v.h @@ -0,0 +1,2 @@ +// vmv8r.v vd, vs2 +#include "vmvnfr_v.h" diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmv_s_x.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmv_s_x.h new file mode 100644 index 0000000000..23a6b56d34 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmv_s_x.h @@ -0,0 +1,29 @@ +// vmv_s_x: vd[0] = rs1 +require_vector(true); +require(insn.v_vm() == 1); +require(P.VU.vsew >= e8 && P.VU.vsew <= e64); +reg_t vl = P.VU.vl->read(); + +if (vl > 0 && P.VU.vstart->read() < vl) { + reg_t rd_num = insn.rd(); + reg_t sew = P.VU.vsew; + + switch (sew) { + case e8: + P.VU.elt<uint8_t>(rd_num, 0, true) = RS1; + break; + case e16: + P.VU.elt<uint16_t>(rd_num, 0, true) = RS1; + break; + case e32: + P.VU.elt<uint32_t>(rd_num, 0, true) = RS1; + break; + default: + P.VU.elt<uint64_t>(rd_num, 0, true) = RS1; + break; + } + + vl = 0; +} + +P.VU.vstart->write(0); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmv_v_i.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmv_v_i.h new file mode 100644 index 0000000000..3d5737e842 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmv_v_i.h @@ -0,0 +1,5 @@ +// vmv.v.i vd, simm5 +VI_VI_MERGE_LOOP +({ + vd = simm5; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmv_v_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmv_v_v.h new file mode 100644 index 0000000000..429f5a3308 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmv_v_v.h @@ -0,0 +1,5 @@ +// vvmv.v.v vd, vs1 +VI_VV_MERGE_LOOP +({ + vd = vs1; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmv_v_x.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmv_v_x.h new file mode 100644 index 0000000000..1eac782e9f --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmv_v_x.h @@ -0,0 +1,5 @@ +// vmv.v.x vd, rs1 +VI_VX_MERGE_LOOP +({ + vd = rs1; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmv_x_s.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmv_x_s.h new file mode 100644 index 0000000000..57a9e1a9ae --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmv_x_s.h @@ -0,0 +1,27 @@ +// vmv_x_s: rd = vs2[0] +require_vector(true); +require(insn.v_vm() == 1); +reg_t sew = P.VU.vsew; +reg_t rs2_num = insn.rs2(); +reg_t res; + +switch (sew) { +case e8: + res = P.VU.elt<int8_t>(rs2_num, 0); + break; +case e16: + res = P.VU.elt<int16_t>(rs2_num, 0); + break; +case e32: + res = P.VU.elt<int32_t>(rs2_num, 0); + break; +case e64: + res = P.VU.elt<uint64_t>(rs2_num, 0); + break; +default: + abort(); +} + +WRITE_RD(sext_xlen(res)); + +P.VU.vstart->write(0); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmvnfr_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmvnfr_v.h new file mode 100644 index 0000000000..9c52810470 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmvnfr_v.h @@ -0,0 +1,27 @@ +// vmv<nf>r.v vd, vs2 +require_vector(true); +const reg_t vd = insn.rd(); +const reg_t vs2 = insn.rs2(); +const reg_t len = insn.rs1() + 1; +require_align(vd, len); +require_align(vs2, len); +const reg_t size = len * P.VU.vlenb; +const reg_t start = P.VU.vstart->read() * (P.VU.vsew >> 3); + +//register needs one-by-one copy to keep commitlog correct +if (vd != vs2 && start < size) { + reg_t i = start / P.VU.vlenb; + reg_t off = start % P.VU.vlenb; + if (off) { + memcpy(&P.VU.elt<uint8_t>(vd + i, off, true), + &P.VU.elt<uint8_t>(vs2 + i, off), P.VU.vlenb - off); + i++; + } + + for (; i < len; ++i) { + memcpy(&P.VU.elt<uint8_t>(vd + i, 0, true), + &P.VU.elt<uint8_t>(vs2 + i, 0), P.VU.vlenb); + } +} + +P.VU.vstart->write(0); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmxnor_mm.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmxnor_mm.h new file mode 100644 index 0000000000..0736d5b21e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmxnor_mm.h @@ -0,0 +1,2 @@ +// vmnxor.mm vd, vs2, vs1 +VI_LOOP_MASK(~(vs2 ^ vs1)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vmxor_mm.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vmxor_mm.h new file mode 100644 index 0000000000..7f0c576e37 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vmxor_mm.h @@ -0,0 +1,2 @@ +// vmxor.mm vd, vs2, vs1 +VI_LOOP_MASK(vs2 ^ vs1); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vnclip_wi.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vnclip_wi.h new file mode 100644 index 0000000000..ea6898cf50 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vnclip_wi.h @@ -0,0 +1,25 @@ +// vnclip: vd[i] = clip(round(vs2[i] + rnd) >> simm) +VRM xrm = P.VU.get_vround_mode(); +int64_t int_max = INT64_MAX >> (64 - P.VU.vsew); +int64_t int_min = INT64_MIN >> (64 - P.VU.vsew); +VI_VI_LOOP_NARROW +({ + int128_t result = vs2; + unsigned shift = zimm5 & ((sew * 2) - 1); + + // rounding + INT_ROUNDING(result, xrm, shift); + + result = result >> shift; + + // saturation + if (result < int_min) { + result = int_min; + P_SET_OV(1); + } else if (result > int_max) { + result = int_max; + P_SET_OV(1); + } + + vd = result; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vnclip_wv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vnclip_wv.h new file mode 100644 index 0000000000..63b84c6582 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vnclip_wv.h @@ -0,0 +1,25 @@ +// vnclip: vd[i] = clip(round(vs2[i] + rnd) >> vs1[i]) +VRM xrm = P.VU.get_vround_mode(); +int64_t int_max = INT64_MAX >> (64 - P.VU.vsew); +int64_t int_min = INT64_MIN >> (64 - P.VU.vsew); +VI_VV_LOOP_NARROW +({ + int128_t result = vs2; + unsigned shift = vs1 & ((sew * 2) - 1); + + // rounding + INT_ROUNDING(result, xrm, shift); + + result = result >> shift; + + // saturation + if (result < int_min) { + result = int_min; + P_SET_OV(1); + } else if (result > int_max) { + result = int_max; + P_SET_OV(1); + } + + vd = result; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vnclip_wx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vnclip_wx.h new file mode 100644 index 0000000000..482eace493 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vnclip_wx.h @@ -0,0 +1,25 @@ +// vnclip: vd[i] = clip(round(vs2[i] + rnd) >> rs1[i]) +VRM xrm = P.VU.get_vround_mode(); +int64_t int_max = INT64_MAX >> (64 - P.VU.vsew); +int64_t int_min = INT64_MIN >> (64 - P.VU.vsew); +VI_VX_LOOP_NARROW +({ + int128_t result = vs2; + unsigned shift = rs1 & ((sew * 2) - 1); + + // rounding + INT_ROUNDING(result, xrm, shift); + + result = result >> shift; + + // saturation + if (result < int_min) { + result = int_min; + P_SET_OV(1); + } else if (result > int_max) { + result = int_max; + P_SET_OV(1); + } + + vd = result; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vnclipu_wi.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vnclipu_wi.h new file mode 100644 index 0000000000..441a3a7d61 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vnclipu_wi.h @@ -0,0 +1,23 @@ +// vnclipu: vd[i] = clip(round(vs2[i] + rnd) >> simm) +VRM xrm = P.VU.get_vround_mode(); +uint64_t uint_max = UINT64_MAX >> (64 - P.VU.vsew); +uint64_t sign_mask = UINT64_MAX << P.VU.vsew; +VI_VI_LOOP_NARROW +({ + uint128_t result = vs2_u; + unsigned shift = zimm5 & ((sew * 2) - 1); + + // rounding + INT_ROUNDING(result, xrm, shift); + + // unsigned shifting to rs1 + result = result >> shift; + + // saturation + if (result & sign_mask) { + result = uint_max; + P_SET_OV(1); + } + + vd = result; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vnclipu_wv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vnclipu_wv.h new file mode 100644 index 0000000000..8072489904 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vnclipu_wv.h @@ -0,0 +1,22 @@ +// vnclipu: vd[i] = clip(round(vs2[i] + rnd) >> vs1[i]) +VRM xrm = P.VU.get_vround_mode(); +uint64_t uint_max = UINT64_MAX >> (64 - P.VU.vsew); +uint64_t sign_mask = UINT64_MAX << P.VU.vsew; +VI_VV_LOOP_NARROW +({ + uint128_t result = vs2_u; + unsigned shift = vs1 & ((sew * 2) - 1); + + // rounding + INT_ROUNDING(result, xrm, shift); + + result = result >> shift; + + // saturation + if (result & sign_mask) { + result = uint_max; + P_SET_OV(1); + } + + vd = result; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vnclipu_wx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vnclipu_wx.h new file mode 100644 index 0000000000..b2d91c3339 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vnclipu_wx.h @@ -0,0 +1,22 @@ +// vnclipu: vd[i] = clip(round(vs2[i] + rnd) >> rs1[i]) +VRM xrm = P.VU.get_vround_mode(); +uint64_t uint_max = UINT64_MAX >> (64 - P.VU.vsew); +uint64_t sign_mask = UINT64_MAX << P.VU.vsew; +VI_VX_LOOP_NARROW +({ + uint128_t result = vs2_u; + unsigned shift = rs1 & ((sew * 2) - 1); + + // rounding + INT_ROUNDING(result, xrm, shift); + + result = result >> shift; + + // saturation + if (result & sign_mask) { + result = uint_max; + P_SET_OV(1); + } + + vd = result; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vnmsac_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vnmsac_vv.h new file mode 100644 index 0000000000..7c10f29af7 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vnmsac_vv.h @@ -0,0 +1,5 @@ +// vmsac.vv: vd[i] = -(vs1[i] * vs2[i]) + vd[i] +VI_VV_LOOP +({ + vd = -(vs1 * vs2) + vd; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vnmsac_vx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vnmsac_vx.h new file mode 100644 index 0000000000..44920be4b2 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vnmsac_vx.h @@ -0,0 +1,5 @@ +// vmsac: vd[i] = -(x[rs1] * vs2[i]) + vd[i] +VI_VX_LOOP +({ + vd = -(rs1 * vs2) + vd; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vnmsub_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vnmsub_vv.h new file mode 100644 index 0000000000..37f82286c4 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vnmsub_vv.h @@ -0,0 +1,5 @@ +// vnmsub.vv: vd[i] = -(vd[i] * vs1[i]) + vs2[i] +VI_VV_LOOP +({ + vd = -(vd * vs1) + vs2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vnmsub_vx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vnmsub_vx.h new file mode 100644 index 0000000000..2e00d22e4a --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vnmsub_vx.h @@ -0,0 +1,5 @@ +// vnmsub.vx: vd[i] = -(vd[i] * x[rs1]) + vs2[i] +VI_VX_LOOP +({ + vd = -(vd * rs1) + vs2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vnsra_wi.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vnsra_wi.h new file mode 100644 index 0000000000..0502ff1a10 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vnsra_wi.h @@ -0,0 +1,5 @@ +// vnsra.vi vd, vs2, zimm5 +VI_VI_LOOP_NSHIFT +({ + vd = vs2 >> (zimm5 & (sew * 2 - 1) & 0x1f); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vnsra_wv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vnsra_wv.h new file mode 100644 index 0000000000..555ce3fb21 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vnsra_wv.h @@ -0,0 +1,5 @@ +// vnsra.vv vd, vs2, vs1 +VI_VV_LOOP_NSHIFT +({ + vd = vs2 >> (vs1 & (sew * 2 - 1)); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vnsra_wx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vnsra_wx.h new file mode 100644 index 0000000000..05a55e3e70 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vnsra_wx.h @@ -0,0 +1,5 @@ +// vnsra.vx vd, vs2, rs1 +VI_VX_LOOP_NSHIFT +({ + vd = vs2 >> (rs1 & (sew * 2 - 1)); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vnsrl_wi.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vnsrl_wi.h new file mode 100644 index 0000000000..d4dfcf0753 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vnsrl_wi.h @@ -0,0 +1,5 @@ +// vnsrl.vi vd, vs2, zimm5 +VI_VI_LOOP_NSHIFT +({ + vd = vs2_u >> (zimm5 & (sew * 2 - 1)); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vnsrl_wv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vnsrl_wv.h new file mode 100644 index 0000000000..ab72b849b6 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vnsrl_wv.h @@ -0,0 +1,5 @@ +// vnsrl.vv vd, vs2, vs1 +VI_VV_LOOP_NSHIFT +({ + vd = vs2_u >> (vs1 & (sew * 2 - 1)); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vnsrl_wx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vnsrl_wx.h new file mode 100644 index 0000000000..e149b38db5 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vnsrl_wx.h @@ -0,0 +1,5 @@ +// vnsrl.vx vd, vs2, rs1 +VI_VX_LOOP_NSHIFT +({ + vd = vs2_u >> (rs1 & (sew * 2 - 1)); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vor_vi.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vor_vi.h new file mode 100644 index 0000000000..f759607497 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vor_vi.h @@ -0,0 +1,5 @@ +// vor +VI_VI_LOOP +({ + vd = simm5 | vs2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vor_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vor_vv.h new file mode 100644 index 0000000000..0c460662bf --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vor_vv.h @@ -0,0 +1,5 @@ +// vor +VI_VV_LOOP +({ + vd = vs1 | vs2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vor_vx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vor_vx.h new file mode 100644 index 0000000000..01c003ab35 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vor_vx.h @@ -0,0 +1,5 @@ +// vor +VI_VX_LOOP +({ + vd = rs1 | vs2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vredand_vs.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vredand_vs.h new file mode 100644 index 0000000000..6c2d9089fa --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vredand_vs.h @@ -0,0 +1,5 @@ +// vredand.vs vd, vs2 ,vs1 +VI_VV_LOOP_REDUCTION +({ + vd_0_res &= vs2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vredmax_vs.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vredmax_vs.h new file mode 100644 index 0000000000..be2e76ab3a --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vredmax_vs.h @@ -0,0 +1,5 @@ +// vredmax.vs vd, vs2 ,vs1 +VI_VV_LOOP_REDUCTION +({ + vd_0_res = (vd_0_res >= vs2) ? vd_0_res : vs2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vredmaxu_vs.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vredmaxu_vs.h new file mode 100644 index 0000000000..960f486181 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vredmaxu_vs.h @@ -0,0 +1,5 @@ +// vredmaxu.vs vd, vs2 ,vs1 +VI_VV_ULOOP_REDUCTION +({ + vd_0_res = (vd_0_res >= vs2) ? vd_0_res : vs2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vredmin_vs.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vredmin_vs.h new file mode 100644 index 0000000000..50359b7a53 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vredmin_vs.h @@ -0,0 +1,5 @@ +// vredmin.vs vd, vs2 ,vs1 +VI_VV_LOOP_REDUCTION +({ + vd_0_res = (vd_0_res <= vs2) ? vd_0_res : vs2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vredminu_vs.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vredminu_vs.h new file mode 100644 index 0000000000..708247592f --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vredminu_vs.h @@ -0,0 +1,5 @@ +// vredminu.vs vd, vs2 ,vs1 +VI_VV_ULOOP_REDUCTION +({ + vd_0_res = (vd_0_res <= vs2) ? vd_0_res : vs2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vredor_vs.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vredor_vs.h new file mode 100644 index 0000000000..f7acd9aa9d --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vredor_vs.h @@ -0,0 +1,5 @@ +// vredor.vs vd, vs2 ,vs1 +VI_VV_LOOP_REDUCTION +({ + vd_0_res |= vs2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vredsum_vs.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vredsum_vs.h new file mode 100644 index 0000000000..c4fefe57f6 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vredsum_vs.h @@ -0,0 +1,5 @@ +// vredsum.vs vd, vs2 ,vs1 +VI_VV_LOOP_REDUCTION +({ + vd_0_res += vs2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vredxor_vs.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vredxor_vs.h new file mode 100644 index 0000000000..bb81ad9a4f --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vredxor_vs.h @@ -0,0 +1,5 @@ +// vredxor.vs vd, vs2 ,vs1 +VI_VV_LOOP_REDUCTION +({ + vd_0_res ^= vs2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vrem_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vrem_vv.h new file mode 100644 index 0000000000..5c58fa499f --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vrem_vv.h @@ -0,0 +1,11 @@ +// vrem.vv vd, vs2, vs1 +VI_VV_LOOP +({ + if (vs1 == 0) + vd = vs2; + else if (vs2 == -(((intmax_t)1) << (sew - 1)) && vs1 == -1) + vd = 0; + else { + vd = vs2 % vs1; + } +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vrem_vx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vrem_vx.h new file mode 100644 index 0000000000..3702f02f41 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vrem_vx.h @@ -0,0 +1,10 @@ +// vrem.vx vd, vs2, rs1 +VI_VX_LOOP +({ + if (rs1 == 0) + vd = vs2; + else if (vs2 == -(((intmax_t)1) << (sew - 1)) && rs1 == -1) + vd = 0; + else + vd = vs2 % rs1; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vremu_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vremu_vv.h new file mode 100644 index 0000000000..7e1507235a --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vremu_vv.h @@ -0,0 +1,8 @@ +// vremu.vv vd, vs2, vs1 +VI_VV_ULOOP +({ + if (vs1 == 0) + vd = vs2; + else + vd = vs2 % vs1; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vremu_vx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vremu_vx.h new file mode 100644 index 0000000000..a87a8200a8 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vremu_vx.h @@ -0,0 +1,8 @@ +// vremu.vx vd, vs2, rs1 +VI_VX_ULOOP +({ + if (rs1 == 0) + vd = vs2; + else + vd = vs2 % rs1; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vrgather_vi.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vrgather_vi.h new file mode 100644 index 0000000000..85ba621cb7 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vrgather_vi.h @@ -0,0 +1,24 @@ +// vrgather.vi vd, vs2, zimm5 vm # vd[i] = (zimm5 >= VLMAX) ? 0 : vs2[zimm5]; +require_align(insn.rd(), P.VU.vflmul); +require_align(insn.rs2(), P.VU.vflmul); +require(insn.rd() != insn.rs2()); +require_vm; + +reg_t zimm5 = insn.v_zimm5(); + +VI_LOOP_BASE + switch (sew) { + case e8: + P.VU.elt<uint8_t>(rd_num, i, true) = zimm5 >= P.VU.vlmax ? 0 : P.VU.elt<uint8_t>(rs2_num, zimm5); + break; + case e16: + P.VU.elt<uint16_t>(rd_num, i, true) = zimm5 >= P.VU.vlmax ? 0 : P.VU.elt<uint16_t>(rs2_num, zimm5); + break; + case e32: + P.VU.elt<uint32_t>(rd_num, i, true) = zimm5 >= P.VU.vlmax ? 0 : P.VU.elt<uint32_t>(rs2_num, zimm5); + break; + default: + P.VU.elt<uint64_t>(rd_num, i, true) = zimm5 >= P.VU.vlmax ? 0 : P.VU.elt<uint64_t>(rs2_num, zimm5); + break; + } +VI_LOOP_END; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vrgather_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vrgather_vv.h new file mode 100644 index 0000000000..a3a32f560f --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vrgather_vv.h @@ -0,0 +1,32 @@ +// vrgather.vv vd, vs2, vs1, vm # vd[i] = (vs1[i] >= VLMAX) ? 0 : vs2[vs1[i]]; +require_align(insn.rd(), P.VU.vflmul); +require_align(insn.rs2(), P.VU.vflmul); +require_align(insn.rs1(), P.VU.vflmul); +require(insn.rd() != insn.rs2() && insn.rd() != insn.rs1()); +require_vm; + +VI_LOOP_BASE + switch (sew) { + case e8: { + auto vs1 = P.VU.elt<uint8_t>(rs1_num, i); + //if (i > 255) continue; + P.VU.elt<uint8_t>(rd_num, i, true) = vs1 >= P.VU.vlmax ? 0 : P.VU.elt<uint8_t>(rs2_num, vs1); + break; + } + case e16: { + auto vs1 = P.VU.elt<uint16_t>(rs1_num, i); + P.VU.elt<uint16_t>(rd_num, i, true) = vs1 >= P.VU.vlmax ? 0 : P.VU.elt<uint16_t>(rs2_num, vs1); + break; + } + case e32: { + auto vs1 = P.VU.elt<uint32_t>(rs1_num, i); + P.VU.elt<uint32_t>(rd_num, i, true) = vs1 >= P.VU.vlmax ? 0 : P.VU.elt<uint32_t>(rs2_num, vs1); + break; + } + default: { + auto vs1 = P.VU.elt<uint64_t>(rs1_num, i); + P.VU.elt<uint64_t>(rd_num, i, true) = vs1 >= P.VU.vlmax ? 0 : P.VU.elt<uint64_t>(rs2_num, vs1); + break; + } + } +VI_LOOP_END; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vrgather_vx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vrgather_vx.h new file mode 100644 index 0000000000..058ffae104 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vrgather_vx.h @@ -0,0 +1,24 @@ +// vrgather.vx vd, vs2, rs1, vm # vd[i] = (rs1 >= VLMAX) ? 0 : vs2[rs1]; +require_align(insn.rd(), P.VU.vflmul); +require_align(insn.rs2(), P.VU.vflmul); +require(insn.rd() != insn.rs2()); +require_vm; + +reg_t rs1 = RS1; + +VI_LOOP_BASE + switch (sew) { + case e8: + P.VU.elt<uint8_t>(rd_num, i, true) = rs1 >= P.VU.vlmax ? 0 : P.VU.elt<uint8_t>(rs2_num, rs1); + break; + case e16: + P.VU.elt<uint16_t>(rd_num, i, true) = rs1 >= P.VU.vlmax ? 0 : P.VU.elt<uint16_t>(rs2_num, rs1); + break; + case e32: + P.VU.elt<uint32_t>(rd_num, i, true) = rs1 >= P.VU.vlmax ? 0 : P.VU.elt<uint32_t>(rs2_num, rs1); + break; + default: + P.VU.elt<uint64_t>(rd_num, i, true) = rs1 >= P.VU.vlmax ? 0 : P.VU.elt<uint64_t>(rs2_num, rs1); + break; + } +VI_LOOP_END; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vrgatherei16_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vrgatherei16_vv.h new file mode 100644 index 0000000000..3bb166a237 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vrgatherei16_vv.h @@ -0,0 +1,34 @@ +// vrgatherei16.vv vd, vs2, vs1, vm # vd[i] = (vs1[i] >= VLMAX) ? 0 : vs2[vs1[i]]; +float vemul = (16.0 / P.VU.vsew * P.VU.vflmul); +require(vemul >= 0.125 && vemul <= 8); +require_align(insn.rd(), P.VU.vflmul); +require_align(insn.rs2(), P.VU.vflmul); +require_align(insn.rs1(), vemul); +require_noover(insn.rd(), P.VU.vflmul, insn.rs1(), vemul); +require(insn.rd() != insn.rs2()); +require_vm; + +VI_LOOP_BASE + switch (sew) { + case e8: { + auto vs1 = P.VU.elt<uint16_t>(rs1_num, i); + P.VU.elt<uint8_t>(rd_num, i, true) = vs1 >= P.VU.vlmax ? 0 : P.VU.elt<uint8_t>(rs2_num, vs1); + break; + } + case e16: { + auto vs1 = P.VU.elt<uint16_t>(rs1_num, i); + P.VU.elt<uint16_t>(rd_num, i, true) = vs1 >= P.VU.vlmax ? 0 : P.VU.elt<uint16_t>(rs2_num, vs1); + break; + } + case e32: { + auto vs1 = P.VU.elt<uint16_t>(rs1_num, i); + P.VU.elt<uint32_t>(rd_num, i, true) = vs1 >= P.VU.vlmax ? 0 : P.VU.elt<uint32_t>(rs2_num, vs1); + break; + } + default: { + auto vs1 = P.VU.elt<uint16_t>(rs1_num, i); + P.VU.elt<uint64_t>(rd_num, i, true) = vs1 >= P.VU.vlmax ? 0 : P.VU.elt<uint64_t>(rs2_num, vs1); + break; + } + } +VI_LOOP_END; diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vrsub_vi.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vrsub_vi.h new file mode 100644 index 0000000000..198c33f927 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vrsub_vi.h @@ -0,0 +1,5 @@ +// vrsub.vi vd, vs2, imm, vm # vd[i] = imm - vs2[i] +VI_VI_LOOP +({ + vd = simm5 - vs2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vrsub_vx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vrsub_vx.h new file mode 100644 index 0000000000..bfd62594db --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vrsub_vx.h @@ -0,0 +1,5 @@ +// vrsub.vx vd, vs2, rs1, vm # vd[i] = rs1 - vs2[i] +VI_VX_LOOP +({ + vd = rs1 - vs2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vs1r_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vs1r_v.h new file mode 100644 index 0000000000..1932ec0b88 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vs1r_v.h @@ -0,0 +1,2 @@ +// vs1r.v vs3, (rs1) +VI_ST_WHOLE diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vs2r_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vs2r_v.h new file mode 100644 index 0000000000..2e515b476c --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vs2r_v.h @@ -0,0 +1,2 @@ +// vs2r.v vs3, (rs1) +VI_ST_WHOLE diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vs4r_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vs4r_v.h new file mode 100644 index 0000000000..161bf89a31 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vs4r_v.h @@ -0,0 +1,2 @@ +// vs4r.v vs3, (rs1) +VI_ST_WHOLE diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vs8r_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vs8r_v.h new file mode 100644 index 0000000000..1ad2575638 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vs8r_v.h @@ -0,0 +1,2 @@ +// vs8r.v vs3, (rs1) +VI_ST_WHOLE diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vsadd_vi.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vsadd_vi.h new file mode 100644 index 0000000000..3a8b1d486b --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vsadd_vi.h @@ -0,0 +1,28 @@ +// vsadd.vi vd, vs2 simm5 +VI_CHECK_SSS(false); +VI_LOOP_BASE +bool sat = false; +switch (sew) { +case e8: { + VI_PARAMS(e8); + vd = sat_add<int8_t, uint8_t>(vs2, vsext(simm5, sew), sat); + break; +} +case e16: { + VI_PARAMS(e16); + vd = sat_add<int16_t, uint16_t>(vs2, vsext(simm5, sew), sat); + break; +} +case e32: { + VI_PARAMS(e32); + vd = sat_add<int32_t, uint32_t>(vs2, vsext(simm5, sew), sat); + break; +} +default: { + VI_PARAMS(e64); + vd = sat_add<int64_t, uint64_t>(vs2, vsext(simm5, sew), sat); + break; +} +} +P_SET_OV(sat); +VI_LOOP_END diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vsadd_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vsadd_vv.h new file mode 100644 index 0000000000..d4cfe78a1d --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vsadd_vv.h @@ -0,0 +1,28 @@ +// vsadd.vv vd, vs2, vs1 +VI_CHECK_SSS(true); +VI_LOOP_BASE +bool sat = false; +switch (sew) { +case e8: { + VV_PARAMS(e8); + vd = sat_add<int8_t, uint8_t>(vs2, vs1, sat); + break; +} +case e16: { + VV_PARAMS(e16); + vd = sat_add<int16_t, uint16_t>(vs2, vs1, sat); + break; +} +case e32: { + VV_PARAMS(e32); + vd = sat_add<int32_t, uint32_t>(vs2, vs1, sat); + break; +} +default: { + VV_PARAMS(e64); + vd = sat_add<int64_t, uint64_t>(vs2, vs1, sat); + break; +} +} +P_SET_OV(sat); +VI_LOOP_END diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vsadd_vx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vsadd_vx.h new file mode 100644 index 0000000000..e5e6c408d4 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vsadd_vx.h @@ -0,0 +1,28 @@ +// vsadd.vx vd, vs2, rs1 +VI_CHECK_SSS(false); +VI_LOOP_BASE +bool sat = false; +switch (sew) { +case e8: { + VX_PARAMS(e8); + vd = sat_add<int8_t, uint8_t>(vs2, rs1, sat); + break; +} +case e16: { + VX_PARAMS(e16); + vd = sat_add<int16_t, uint16_t>(vs2, rs1, sat); + break; +} +case e32: { + VX_PARAMS(e32); + vd = sat_add<int32_t, uint32_t>(vs2, rs1, sat); + break; +} +default: { + VX_PARAMS(e64); + vd = sat_add<int64_t, uint64_t>(vs2, rs1, sat); + break; +} +} +P_SET_OV(sat); +VI_LOOP_END diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vsaddu_vi.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vsaddu_vi.h new file mode 100644 index 0000000000..38607140f6 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vsaddu_vi.h @@ -0,0 +1,11 @@ +// vsaddu vd, vs2, zimm5 +VI_VI_ULOOP +({ + bool sat = false; + vd = vs2 + (insn.v_simm5() & (UINT64_MAX >> (64 - P.VU.vsew))); + + sat = vd < vs2; + vd |= -(vd < vs2); + + P_SET_OV(sat); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vsaddu_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vsaddu_vv.h new file mode 100644 index 0000000000..a0cba811f7 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vsaddu_vv.h @@ -0,0 +1,11 @@ +// vsaddu vd, vs2, vs1 +VI_VV_ULOOP +({ + bool sat = false; + vd = vs2 + vs1; + + sat = vd < vs2; + vd |= -(vd < vs2); + + P_SET_OV(sat); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vsaddu_vx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vsaddu_vx.h new file mode 100644 index 0000000000..c0a7d8724d --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vsaddu_vx.h @@ -0,0 +1,12 @@ +// vsaddu vd, vs2, rs1 +VI_VX_ULOOP +({ + bool sat = false; + vd = vs2 + rs1; + + sat = vd < vs2; + vd |= -(vd < vs2); + + P_SET_OV(sat); + +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vsbc_vvm.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vsbc_vvm.h new file mode 100644 index 0000000000..8ab6d4464d --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vsbc_vvm.h @@ -0,0 +1,5 @@ +// vsbc.vvm vd, vs2, rs1, v0 +VI_VV_LOOP_WITH_CARRY +({ + vd = (uint128_t)((op_mask & vs2) - (op_mask & vs1) - carry); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vsbc_vxm.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vsbc_vxm.h new file mode 100644 index 0000000000..fc98321856 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vsbc_vxm.h @@ -0,0 +1,5 @@ +// vsbc.vxm vd, vs2, rs1, v0 +VI_XI_LOOP_WITH_CARRY +({ + vd = (uint128_t)((op_mask & vs2) - (op_mask & rs1) - carry); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vse16_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vse16_v.h new file mode 100644 index 0000000000..9f9afecb9a --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vse16_v.h @@ -0,0 +1,2 @@ +// vse16.v and vsseg[2-8]e16.v +VI_ST(0, (i * nf + fn), uint16, false); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vse32_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vse32_v.h new file mode 100644 index 0000000000..1c6a231056 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vse32_v.h @@ -0,0 +1,2 @@ +// vse32.v and vsseg[2-8]e32.v +VI_ST(0, (i * nf + fn), uint32, false); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vse64_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vse64_v.h new file mode 100644 index 0000000000..61d0ba6403 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vse64_v.h @@ -0,0 +1,2 @@ +// vse64.v and vsseg[2-8]e64.v +VI_ST(0, (i * nf + fn), uint64, false); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vse8_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vse8_v.h new file mode 100644 index 0000000000..01f59cebdd --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vse8_v.h @@ -0,0 +1,2 @@ +// vse8.v and vsseg[2-8]e8.v +VI_ST(0, (i * nf + fn), uint8, false); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vsetivli.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vsetivli.h new file mode 100644 index 0000000000..f880e96a3d --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vsetivli.h @@ -0,0 +1,2 @@ +require_vector_novtype(false); +WRITE_RD(P.VU.set_vl(insn.rd(), -1, insn.rs1(), insn.v_zimm10())); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vsetvl.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vsetvl.h new file mode 100644 index 0000000000..4d03542ec7 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vsetvl.h @@ -0,0 +1,2 @@ +require_vector_novtype(false); +WRITE_RD(P.VU.set_vl(insn.rd(), insn.rs1(), RS1, RS2)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vsetvli.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vsetvli.h new file mode 100644 index 0000000000..d1f43b5715 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vsetvli.h @@ -0,0 +1,2 @@ +require_vector_novtype(false); +WRITE_RD(P.VU.set_vl(insn.rd(), insn.rs1(), RS1, insn.v_zimm11())); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vsext_vf2.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vsext_vf2.h new file mode 100644 index 0000000000..16ccfac607 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vsext_vf2.h @@ -0,0 +1 @@ +VI_VV_EXT(2, int); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vsext_vf4.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vsext_vf4.h new file mode 100644 index 0000000000..d4476a310f --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vsext_vf4.h @@ -0,0 +1 @@ +VI_VV_EXT(4, int); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vsext_vf8.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vsext_vf8.h new file mode 100644 index 0000000000..09fdc2c75c --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vsext_vf8.h @@ -0,0 +1 @@ +VI_VV_EXT(8, int); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vslide1down_vx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vslide1down_vx.h new file mode 100644 index 0000000000..e867722fa8 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vslide1down_vx.h @@ -0,0 +1,44 @@ +//vslide1down.vx vd, vs2, rs1 +VI_CHECK_SLIDE(false); + +VI_LOOP_BASE +if (i != vl - 1) { + switch (sew) { + case e8: { + VI_XI_SLIDEDOWN_PARAMS(e8, 1); + vd = vs2; + } + break; + case e16: { + VI_XI_SLIDEDOWN_PARAMS(e16, 1); + vd = vs2; + } + break; + case e32: { + VI_XI_SLIDEDOWN_PARAMS(e32, 1); + vd = vs2; + } + break; + default: { + VI_XI_SLIDEDOWN_PARAMS(e64, 1); + vd = vs2; + } + break; + } +} else { + switch (sew) { + case e8: + P.VU.elt<uint8_t>(rd_num, vl - 1, true) = RS1; + break; + case e16: + P.VU.elt<uint16_t>(rd_num, vl - 1, true) = RS1; + break; + case e32: + P.VU.elt<uint32_t>(rd_num, vl - 1, true) = RS1; + break; + default: + P.VU.elt<uint64_t>(rd_num, vl - 1, true) = RS1; + break; + } +} +VI_LOOP_END diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vslide1up_vx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vslide1up_vx.h new file mode 100644 index 0000000000..256419eadb --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vslide1up_vx.h @@ -0,0 +1,30 @@ +//vslide1up.vx vd, vs2, rs1 +VI_CHECK_SLIDE(true); + +VI_LOOP_BASE +if (i != 0) { + if (sew == e8) { + VI_XI_SLIDEUP_PARAMS(e8, 1); + vd = vs2; + } else if (sew == e16) { + VI_XI_SLIDEUP_PARAMS(e16, 1); + vd = vs2; + } else if (sew == e32) { + VI_XI_SLIDEUP_PARAMS(e32, 1); + vd = vs2; + } else if (sew == e64) { + VI_XI_SLIDEUP_PARAMS(e64, 1); + vd = vs2; + } +} else { + if (sew == e8) { + P.VU.elt<uint8_t>(rd_num, 0, true) = RS1; + } else if (sew == e16) { + P.VU.elt<uint16_t>(rd_num, 0, true) = RS1; + } else if (sew == e32) { + P.VU.elt<uint32_t>(rd_num, 0, true) = RS1; + } else if (sew == e64) { + P.VU.elt<uint64_t>(rd_num, 0, true) = RS1; + } +} +VI_LOOP_END diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vslidedown_vi.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vslidedown_vi.h new file mode 100644 index 0000000000..bc440cf2bd --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vslidedown_vi.h @@ -0,0 +1,36 @@ +// vslidedown.vi vd, vs2, rs1 +VI_CHECK_SLIDE(false); + +const reg_t sh = insn.v_zimm5(); +VI_LOOP_BASE + +reg_t offset = 0; +bool is_valid = (i + sh) < P.VU.vlmax; + +if (is_valid) { + offset = sh; +} + +switch (sew) { +case e8: { + VI_XI_SLIDEDOWN_PARAMS(e8, offset); + vd = is_valid ? vs2 : 0; +} +break; +case e16: { + VI_XI_SLIDEDOWN_PARAMS(e16, offset); + vd = is_valid ? vs2 : 0; +} +break; +case e32: { + VI_XI_SLIDEDOWN_PARAMS(e32, offset); + vd = is_valid ? vs2 : 0; +} +break; +default: { + VI_XI_SLIDEDOWN_PARAMS(e64, offset); + vd = is_valid ? vs2 : 0; +} +break; +} +VI_LOOP_END diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vslidedown_vx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vslidedown_vx.h new file mode 100644 index 0000000000..074aa50868 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vslidedown_vx.h @@ -0,0 +1,36 @@ +//vslidedown.vx vd, vs2, rs1 +VI_CHECK_SLIDE(false); + +const uint128_t sh = RS1; +VI_LOOP_BASE + +reg_t offset = 0; +bool is_valid = (i + sh) < P.VU.vlmax; + +if (is_valid) { + offset = sh; +} + +switch (sew) { +case e8: { + VI_XI_SLIDEDOWN_PARAMS(e8, offset); + vd = is_valid ? vs2 : 0; +} +break; +case e16: { + VI_XI_SLIDEDOWN_PARAMS(e16, offset); + vd = is_valid ? vs2 : 0; +} +break; +case e32: { + VI_XI_SLIDEDOWN_PARAMS(e32, offset); + vd = is_valid ? vs2 : 0; +} +break; +default: { + VI_XI_SLIDEDOWN_PARAMS(e64, offset); + vd = is_valid ? vs2 : 0; +} +break; +} +VI_LOOP_END diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vslideup_vi.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vslideup_vi.h new file mode 100644 index 0000000000..3d537944a4 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vslideup_vi.h @@ -0,0 +1,31 @@ +// vslideup.vi vd, vs2, rs1 +VI_CHECK_SLIDE(true); + +const reg_t offset = insn.v_zimm5(); +VI_LOOP_BASE +if (P.VU.vstart->read() < offset && i < offset) + continue; + +switch (sew) { +case e8: { + VI_XI_SLIDEUP_PARAMS(e8, offset); + vd = vs2; +} +break; +case e16: { + VI_XI_SLIDEUP_PARAMS(e16, offset); + vd = vs2; +} +break; +case e32: { + VI_XI_SLIDEUP_PARAMS(e32, offset); + vd = vs2; +} +break; +default: { + VI_XI_SLIDEUP_PARAMS(e64, offset); + vd = vs2; +} +break; +} +VI_LOOP_END diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vslideup_vx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vslideup_vx.h new file mode 100644 index 0000000000..43d41fb3a4 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vslideup_vx.h @@ -0,0 +1,31 @@ +//vslideup.vx vd, vs2, rs1 +VI_CHECK_SLIDE(true); + +const reg_t offset = RS1; +VI_LOOP_BASE +if (P.VU.vstart->read() < offset && i < offset) + continue; + +switch (sew) { +case e8: { + VI_XI_SLIDEUP_PARAMS(e8, offset); + vd = vs2; +} +break; +case e16: { + VI_XI_SLIDEUP_PARAMS(e16, offset); + vd = vs2; +} +break; +case e32: { + VI_XI_SLIDEUP_PARAMS(e32, offset); + vd = vs2; +} +break; +default: { + VI_XI_SLIDEUP_PARAMS(e64, offset); + vd = vs2; +} +break; +} +VI_LOOP_END diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vsll_vi.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vsll_vi.h new file mode 100644 index 0000000000..be4650669f --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vsll_vi.h @@ -0,0 +1,5 @@ +// vsll.vi vd, vs2, zimm5 +VI_VI_LOOP +({ + vd = vs2 << (simm5 & (sew - 1) & 0x1f); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vsll_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vsll_vv.h new file mode 100644 index 0000000000..ce82022504 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vsll_vv.h @@ -0,0 +1,5 @@ +// vsll +VI_VV_LOOP +({ + vd = vs2 << (vs1 & (sew - 1)); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vsll_vx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vsll_vx.h new file mode 100644 index 0000000000..823510b2c5 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vsll_vx.h @@ -0,0 +1,5 @@ +// vsll +VI_VX_LOOP +({ + vd = vs2 << (rs1 & (sew - 1)); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vsm_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vsm_v.h new file mode 100644 index 0000000000..e1d468be8c --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vsm_v.h @@ -0,0 +1,2 @@ +// vse1.v +VI_ST(0, (i * nf + fn), uint8, true); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vsmul_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vsmul_vv.h new file mode 100644 index 0000000000..49e42c1fa6 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vsmul_vv.h @@ -0,0 +1,24 @@ +// vsmul.vv vd, vs2, vs1 +VRM xrm = P.VU.get_vround_mode(); +int64_t int_max = INT64_MAX >> (64 - P.VU.vsew); +int64_t int_min = INT64_MIN >> (64 - P.VU.vsew); + +VI_VV_LOOP +({ + bool overflow = vs1 == vs2 && vs1 == int_min; + int128_t result = (int128_t)vs1 * (int128_t)vs2; + + // rounding + INT_ROUNDING(result, xrm, sew - 1); + + // remove guard bits + result = result >> (sew - 1); + + // max saturation + if (overflow) { + result = int_max; + P_SET_OV(1); + } + + vd = result; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vsmul_vx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vsmul_vx.h new file mode 100644 index 0000000000..d2724eee4e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vsmul_vx.h @@ -0,0 +1,24 @@ +// vsmul.vx vd, vs2, rs1 +VRM xrm = P.VU.get_vround_mode(); +int64_t int_max = INT64_MAX >> (64 - P.VU.vsew); +int64_t int_min = INT64_MIN >> (64 - P.VU.vsew); + +VI_VX_LOOP +({ + bool overflow = rs1 == vs2 && rs1 == int_min; + int128_t result = (int128_t)rs1 * (int128_t)vs2; + + // rounding + INT_ROUNDING(result, xrm, sew - 1); + + // remove guard bits + result = result >> (sew - 1); + + // max saturation + if (overflow) { + result = int_max; + P_SET_OV(1); + } + + vd = result; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vsoxei16_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vsoxei16_v.h new file mode 100644 index 0000000000..42c3c78dbb --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vsoxei16_v.h @@ -0,0 +1,2 @@ +// vsxei16.v and vsxseg[2-8]ei16.v +VI_ST_INDEX(e16, true); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vsoxei32_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vsoxei32_v.h new file mode 100644 index 0000000000..f0aed6bd6e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vsoxei32_v.h @@ -0,0 +1,2 @@ +// vsxei32.v and vsxseg[2-8]ei32.v +VI_ST_INDEX(e32, true); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vsoxei64_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vsoxei64_v.h new file mode 100644 index 0000000000..88ddaf3fd7 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vsoxei64_v.h @@ -0,0 +1,2 @@ +// vsxei64.v and vsxseg[2-8]ei64.v +VI_ST_INDEX(e64, true); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vsoxei8_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vsoxei8_v.h new file mode 100644 index 0000000000..621512c50c --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vsoxei8_v.h @@ -0,0 +1,2 @@ +// vsxei8.v and vsxseg[2-8]ei8.v +VI_ST_INDEX(e8, true); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vsra_vi.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vsra_vi.h new file mode 100644 index 0000000000..5c589274ef --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vsra_vi.h @@ -0,0 +1,5 @@ +// vsra.vi vd, vs2, zimm5 +VI_VI_LOOP +({ + vd = vs2 >> (simm5 & (sew - 1) & 0x1f); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vsra_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vsra_vv.h new file mode 100644 index 0000000000..8889af9c08 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vsra_vv.h @@ -0,0 +1,5 @@ +// vsra.vv vd, vs2, vs1 +VI_VV_LOOP +({ + vd = vs2 >> (vs1 & (sew - 1)); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vsra_vx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vsra_vx.h new file mode 100644 index 0000000000..c1b0c10728 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vsra_vx.h @@ -0,0 +1,5 @@ +// vsra.vx vd, vs2, rs1 +VI_VX_LOOP +({ + vd = vs2 >> (rs1 & (sew - 1)); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vsrl_vi.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vsrl_vi.h new file mode 100644 index 0000000000..fe5d272025 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vsrl_vi.h @@ -0,0 +1,5 @@ +// vsrl.vi vd, vs2, zimm5 +VI_VI_ULOOP +({ + vd = vs2 >> (zimm5 & (sew - 1) & 0x1f); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vsrl_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vsrl_vv.h new file mode 100644 index 0000000000..6376af36bc --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vsrl_vv.h @@ -0,0 +1,5 @@ +// vsrl.vv vd, vs2, vs1 +VI_VV_ULOOP +({ + vd = vs2 >> (vs1 & (sew - 1)); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vsrl_vx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vsrl_vx.h new file mode 100644 index 0000000000..a4f899ca2c --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vsrl_vx.h @@ -0,0 +1,5 @@ +// vsrl.vx vd, vs2, rs1 +VI_VX_ULOOP +({ + vd = vs2 >> (rs1 & (sew - 1)); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vsse16_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vsse16_v.h new file mode 100644 index 0000000000..5dcbaf9f17 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vsse16_v.h @@ -0,0 +1,2 @@ +// vsse16v and vssseg[2-8]e16.v +VI_ST(i * RS2, fn, uint16, false); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vsse32_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vsse32_v.h new file mode 100644 index 0000000000..80276b25ff --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vsse32_v.h @@ -0,0 +1,2 @@ +// vsse32.v and vssseg[2-8]e32.v +VI_ST(i * RS2, fn, uint32, false); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vsse64_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vsse64_v.h new file mode 100644 index 0000000000..a4b6290b30 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vsse64_v.h @@ -0,0 +1,2 @@ +// vsse64.v and vssseg[2-8]e64.v +VI_ST(i * RS2, fn, uint64, false); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vsse8_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vsse8_v.h new file mode 100644 index 0000000000..5ba3ccec79 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vsse8_v.h @@ -0,0 +1,2 @@ +// vsse8.v and vssseg[2-8]e8.v +VI_ST(i * RS2, fn, uint8, false); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vssra_vi.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vssra_vi.h new file mode 100644 index 0000000000..ff2e1c585c --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vssra_vi.h @@ -0,0 +1,10 @@ +// vssra.vi vd, vs2, simm5 +VRM xrm = P.VU.get_vround_mode(); +VI_VI_LOOP +({ + int sh = simm5 & (sew - 1) & 0x1f; + int128_t val = vs2; + + INT_ROUNDING(val, xrm, sh); + vd = val >> sh; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vssra_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vssra_vv.h new file mode 100644 index 0000000000..7bbc766ff1 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vssra_vv.h @@ -0,0 +1,10 @@ +// vssra.vv vd, vs2, vs1 +VRM xrm = P.VU.get_vround_mode(); +VI_VV_LOOP +({ + int sh = vs1 & (sew - 1); + int128_t val = vs2; + + INT_ROUNDING(val, xrm, sh); + vd = val >> sh; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vssra_vx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vssra_vx.h new file mode 100644 index 0000000000..068a22b692 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vssra_vx.h @@ -0,0 +1,10 @@ +// vssra.vx vd, vs2, rs1 +VRM xrm = P.VU.get_vround_mode(); +VI_VX_LOOP +({ + int sh = rs1 & (sew - 1); + int128_t val = vs2; + + INT_ROUNDING(val, xrm, sh); + vd = val >> sh; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vssrl_vi.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vssrl_vi.h new file mode 100644 index 0000000000..d125164d6a --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vssrl_vi.h @@ -0,0 +1,10 @@ +// vssra.vi vd, vs2, simm5 +VRM xrm = P.VU.get_vround_mode(); +VI_VI_ULOOP +({ + int sh = zimm5 & (sew - 1) & 0x1f; + uint128_t val = vs2; + + INT_ROUNDING(val, xrm, sh); + vd = val >> sh; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vssrl_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vssrl_vv.h new file mode 100644 index 0000000000..a8e5d16423 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vssrl_vv.h @@ -0,0 +1,10 @@ +// vssrl.vv vd, vs2, vs1 +VRM xrm = P.VU.get_vround_mode(); +VI_VV_ULOOP +({ + int sh = vs1 & (sew - 1); + uint128_t val = vs2; + + INT_ROUNDING(val, xrm, sh); + vd = val >> sh; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vssrl_vx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vssrl_vx.h new file mode 100644 index 0000000000..ee3cb3462f --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vssrl_vx.h @@ -0,0 +1,10 @@ +// vssrl.vx vd, vs2, rs1 +VRM xrm = P.VU.get_vround_mode(); +VI_VX_ULOOP +({ + int sh = rs1 & (sew - 1); + uint128_t val = vs2; + + INT_ROUNDING(val, xrm, sh); + vd = val >> sh; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vssub_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vssub_vv.h new file mode 100644 index 0000000000..d55df23899 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vssub_vv.h @@ -0,0 +1,29 @@ +// vssub.vv vd, vs2, vs1 +VI_CHECK_SSS(true); +VI_LOOP_BASE +bool sat = false; + +switch (sew) { +case e8: { + VV_PARAMS(e8); + vd = sat_sub<int8_t, uint8_t>(vs2, vs1, sat); + break; +} +case e16: { + VV_PARAMS(e16); + vd = sat_sub<int16_t, uint16_t>(vs2, vs1, sat); + break; +} +case e32: { + VV_PARAMS(e32); + vd = sat_sub<int32_t, uint32_t>(vs2, vs1, sat); + break; +} +default: { + VV_PARAMS(e64); + vd = sat_sub<int64_t, uint64_t>(vs2, vs1, sat); + break; +} +} +P_SET_OV(sat); +VI_LOOP_END diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vssub_vx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vssub_vx.h new file mode 100644 index 0000000000..cbfa288056 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vssub_vx.h @@ -0,0 +1,29 @@ +// vssub.vx vd, vs2, rs1 +VI_CHECK_SSS(false); +VI_LOOP_BASE +bool sat = false; + +switch (sew) { +case e8: { + VX_PARAMS(e8); + vd = sat_sub<int8_t, uint8_t>(vs2, rs1, sat); + break; +} +case e16: { + VX_PARAMS(e16); + vd = sat_sub<int16_t, uint16_t>(vs2, rs1, sat); + break; +} +case e32: { + VX_PARAMS(e32); + vd = sat_sub<int32_t, uint32_t>(vs2, rs1, sat); + break; +} +default: { + VX_PARAMS(e64); + vd = sat_sub<int64_t, uint64_t>(vs2, rs1, sat); + break; +} +} +P_SET_OV(sat); +VI_LOOP_END diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vssubu_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vssubu_vv.h new file mode 100644 index 0000000000..667a2c5157 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vssubu_vv.h @@ -0,0 +1,30 @@ +// vssubu.vv vd, vs2, vs1 +VI_CHECK_SSS(true); +VI_LOOP_BASE +bool sat = false; + +switch (sew) { +case e8: { + VV_U_PARAMS(e8); + vd = sat_subu<uint8_t>(vs2, vs1, sat); + break; +} +case e16: { + VV_U_PARAMS(e16); + vd = sat_subu<uint16_t>(vs2, vs1, sat); + break; +} +case e32: { + VV_U_PARAMS(e32); + vd = sat_subu<uint32_t>(vs2, vs1, sat); + break; +} +default: { + VV_U_PARAMS(e64); + vd = sat_subu<uint64_t>(vs2, vs1, sat); + break; +} +} +P_SET_OV(sat); + +VI_LOOP_END diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vssubu_vx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vssubu_vx.h new file mode 100644 index 0000000000..603f35e715 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vssubu_vx.h @@ -0,0 +1,29 @@ +// vssubu.vx vd, vs2, rs1 +VI_CHECK_SSS(false); +VI_LOOP_BASE +bool sat = false; + +switch (sew) { +case e8: { + VX_U_PARAMS(e8); + vd = sat_subu<uint8_t>(vs2, rs1, sat); + break; +} +case e16: { + VX_U_PARAMS(e16); + vd = sat_subu<uint16_t>(vs2, rs1, sat); + break; +} +case e32: { + VX_U_PARAMS(e32); + vd = sat_subu<uint32_t>(vs2, rs1, sat); + break; +} +default: { + VX_U_PARAMS(e64); + vd = sat_subu<uint64_t>(vs2, rs1, sat); + break; +} +} +P_SET_OV(sat); +VI_LOOP_END diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vsub_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vsub_vv.h new file mode 100644 index 0000000000..7d119d50fd --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vsub_vv.h @@ -0,0 +1,5 @@ +// vsub +VI_VV_LOOP +({ + vd = vs2 - vs1; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vsub_vx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vsub_vx.h new file mode 100644 index 0000000000..e075b42370 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vsub_vx.h @@ -0,0 +1,5 @@ +// vsub: vd[i] = (vd[i] * x[rs1]) - vs2[i] +VI_VX_LOOP +({ + vd = vs2 - rs1; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vsuxei16_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vsuxei16_v.h new file mode 100644 index 0000000000..f55491875d --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vsuxei16_v.h @@ -0,0 +1,2 @@ +// vsuxe16.v +VI_ST_INDEX(e16, true); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vsuxei32_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vsuxei32_v.h new file mode 100644 index 0000000000..783bbadeb5 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vsuxei32_v.h @@ -0,0 +1,2 @@ +// vsuxe32.v +VI_ST_INDEX(e32, true); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vsuxei64_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vsuxei64_v.h new file mode 100644 index 0000000000..9e6018b620 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vsuxei64_v.h @@ -0,0 +1,2 @@ +// vsuxe64.v +VI_ST_INDEX(e64, true); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vsuxei8_v.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vsuxei8_v.h new file mode 100644 index 0000000000..322dc35e2e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vsuxei8_v.h @@ -0,0 +1,2 @@ +// vsuxe8.v +VI_ST_INDEX(e8, true); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vwadd_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vwadd_vv.h new file mode 100644 index 0000000000..df4a13534d --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vwadd_vv.h @@ -0,0 +1,6 @@ +// vwadd.vv vd, vs2, vs1 +VI_CHECK_DSS(true); +VI_VV_LOOP_WIDEN +({ + VI_WIDE_OP_AND_ASSIGN(vs2, vs1, 0, +, +, int); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vwadd_vx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vwadd_vx.h new file mode 100644 index 0000000000..c226389342 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vwadd_vx.h @@ -0,0 +1,6 @@ +// vwadd.vx vd, vs2, rs1 +VI_CHECK_DSS(false); +VI_VX_LOOP_WIDEN +({ + VI_WIDE_OP_AND_ASSIGN(vs2, rs1, 0, +, +, int); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vwadd_wv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vwadd_wv.h new file mode 100644 index 0000000000..54d2ba4072 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vwadd_wv.h @@ -0,0 +1,6 @@ +// vwadd.wv vd, vs2, vs1 +VI_CHECK_DDS(true); +VI_VV_LOOP_WIDEN +({ + VI_WIDE_WVX_OP(vs1, +, int); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vwadd_wx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vwadd_wx.h new file mode 100644 index 0000000000..bb4cee5100 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vwadd_wx.h @@ -0,0 +1,6 @@ +// vwaddu.wx vd, vs2, rs1 +VI_CHECK_DDS(false); +VI_VX_LOOP_WIDEN +({ + VI_WIDE_WVX_OP(rs1, +, int); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vwaddu_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vwaddu_vv.h new file mode 100644 index 0000000000..286ebc858e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vwaddu_vv.h @@ -0,0 +1,6 @@ +// vwaddu.vv vd, vs2, vs1 +VI_CHECK_DSS(true); +VI_VV_LOOP_WIDEN +({ + VI_WIDE_OP_AND_ASSIGN(vs2, vs1, 0, +, +, uint); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vwaddu_vx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vwaddu_vx.h new file mode 100644 index 0000000000..61cddfc897 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vwaddu_vx.h @@ -0,0 +1,6 @@ +// vwaddu.vx vd, vs2, rs1 +VI_CHECK_DSS(false); +VI_VX_LOOP_WIDEN +({ + VI_WIDE_OP_AND_ASSIGN(vs2, rs1, 0, +, +, uint); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vwaddu_wv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vwaddu_wv.h new file mode 100644 index 0000000000..fee813657e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vwaddu_wv.h @@ -0,0 +1,6 @@ +// vwaddu.wv vd, vs2, vs1 +VI_CHECK_DDS(true); +VI_VV_LOOP_WIDEN +({ + VI_WIDE_WVX_OP(vs1, +, uint); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vwaddu_wx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vwaddu_wx.h new file mode 100644 index 0000000000..0073ac35c5 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vwaddu_wx.h @@ -0,0 +1,6 @@ +// vwaddu.wx vd, vs2, rs1 +VI_CHECK_DDS(false); +VI_VX_LOOP_WIDEN +({ + VI_WIDE_WVX_OP(rs1, +, uint); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vwmacc_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vwmacc_vv.h new file mode 100644 index 0000000000..7208c6d696 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vwmacc_vv.h @@ -0,0 +1,6 @@ +// vwmacc.vv vd, vs2, vs1 +VI_CHECK_DSS(true); +VI_VV_LOOP_WIDEN +({ + VI_WIDE_OP_AND_ASSIGN(vs2, vs1, vd_w, *, +, int); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vwmacc_vx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vwmacc_vx.h new file mode 100644 index 0000000000..5ae597a267 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vwmacc_vx.h @@ -0,0 +1,6 @@ +// vwmacc.vx vd, vs2, rs1 +VI_CHECK_DSS(false); +VI_VX_LOOP_WIDEN +({ + VI_WIDE_OP_AND_ASSIGN(vs2, rs1, vd_w, *, +, int); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vwmaccsu_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vwmaccsu_vv.h new file mode 100644 index 0000000000..3aa43ef44d --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vwmaccsu_vv.h @@ -0,0 +1,6 @@ +// vwmaccsu.vv vd, vs2, vs1 +VI_CHECK_DSS(true); +VI_VV_LOOP_WIDEN +({ + VI_WIDE_OP_AND_ASSIGN_MIX(vs2, vs1, vd_w, *, +, int, uint, int); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vwmaccsu_vx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vwmaccsu_vx.h new file mode 100644 index 0000000000..e00a21ddc1 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vwmaccsu_vx.h @@ -0,0 +1,6 @@ +// vwmaccsu.vx vd, vs2, rs1 +VI_CHECK_DSS(false); +VI_VX_LOOP_WIDEN +({ + VI_WIDE_OP_AND_ASSIGN_MIX(vs2, rs1, vd_w, *, +, int, uint, int); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vwmaccu_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vwmaccu_vv.h new file mode 100644 index 0000000000..2cbdaa312b --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vwmaccu_vv.h @@ -0,0 +1,6 @@ +// vwmaccu.vv vd, vs2, vs1 +VI_CHECK_DSS(true); +VI_VV_LOOP_WIDEN +({ + VI_WIDE_OP_AND_ASSIGN(vs2, vs1, vd_w, *, +, uint); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vwmaccu_vx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vwmaccu_vx.h new file mode 100644 index 0000000000..533297f3fa --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vwmaccu_vx.h @@ -0,0 +1,6 @@ +// vwmaccu.vx vd, vs2, rs1 +VI_CHECK_DSS(false); +VI_VX_LOOP_WIDEN +({ + VI_WIDE_OP_AND_ASSIGN(vs2, rs1, vd_w, *, +, uint); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vwmaccus_vx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vwmaccus_vx.h new file mode 100644 index 0000000000..5310f0e9be --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vwmaccus_vx.h @@ -0,0 +1,6 @@ +// vwmaccus.vx vd, vs2, rs1 +VI_CHECK_DSS(false); +VI_VX_LOOP_WIDEN +({ + VI_WIDE_OP_AND_ASSIGN_MIX(vs2, rs1, vd_w, *, +, int, int, uint); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vwmul_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vwmul_vv.h new file mode 100644 index 0000000000..2197edbfbf --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vwmul_vv.h @@ -0,0 +1,6 @@ +// vwmul.vv vd, vs2, vs1 +VI_CHECK_DSS(true); +VI_VV_LOOP_WIDEN +({ + VI_WIDE_OP_AND_ASSIGN(vs2, vs1, 0, *, +, int); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vwmul_vx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vwmul_vx.h new file mode 100644 index 0000000000..bc1422d400 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vwmul_vx.h @@ -0,0 +1,6 @@ +// vwmul.vx vd, vs2, rs1 +VI_CHECK_DSS(false); +VI_VX_LOOP_WIDEN +({ + VI_WIDE_OP_AND_ASSIGN(vs2, rs1, 0, *, +, int); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vwmulsu_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vwmulsu_vv.h new file mode 100644 index 0000000000..ec373771ab --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vwmulsu_vv.h @@ -0,0 +1,6 @@ +// vwmulsu.vv vd, vs2, vs1 +VI_CHECK_DSS(true); +VI_VV_LOOP_WIDEN +({ + VI_WIDE_OP_AND_ASSIGN_MIX(vs2, vs1, 0, *, +, uint, int, uint) +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vwmulsu_vx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vwmulsu_vx.h new file mode 100644 index 0000000000..d58ecce0d5 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vwmulsu_vx.h @@ -0,0 +1,6 @@ +// vwmulsu.vx vd, vs2, rs1 +VI_CHECK_DSS(false); +VI_VX_LOOP_WIDEN +({ + VI_WIDE_OP_AND_ASSIGN_MIX(vs2, rs1, 0, *, +, uint, int, uint) +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vwmulu_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vwmulu_vv.h new file mode 100644 index 0000000000..8ddbb4b488 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vwmulu_vv.h @@ -0,0 +1,6 @@ +// vwmulu.vv vd, vs2, vs1 +VI_CHECK_DSS(true); +VI_VV_LOOP_WIDEN +({ + VI_WIDE_OP_AND_ASSIGN(vs2, vs1, 0, *, +, uint); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vwmulu_vx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vwmulu_vx.h new file mode 100644 index 0000000000..1ce77eefdc --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vwmulu_vx.h @@ -0,0 +1,6 @@ +// vwmul.vx vd, vs2, rs1 +VI_CHECK_DSS(false); +VI_VX_LOOP_WIDEN +({ + VI_WIDE_OP_AND_ASSIGN(vs2, rs1, 0, *, +, uint); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vwredsum_vs.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vwredsum_vs.h new file mode 100644 index 0000000000..c7a87db431 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vwredsum_vs.h @@ -0,0 +1,5 @@ +// vwredsum.vs vd, vs2, vs1 +VI_VV_LOOP_WIDE_REDUCTION +({ + vd_0_res += vs2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vwredsumu_vs.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vwredsumu_vs.h new file mode 100644 index 0000000000..889a77d310 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vwredsumu_vs.h @@ -0,0 +1,5 @@ +// vwredsum.vs vd, vs2, vs1 +VI_VV_ULOOP_WIDE_REDUCTION +({ + vd_0_res += vs2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vwsub_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vwsub_vv.h new file mode 100644 index 0000000000..99f9348985 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vwsub_vv.h @@ -0,0 +1,6 @@ +// vwsub.vv vd, vs2, vs1 +VI_CHECK_DSS(true); +VI_VV_LOOP_WIDEN +({ + VI_WIDE_OP_AND_ASSIGN(vs2, vs1, 0, -, +, int); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vwsub_vx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vwsub_vx.h new file mode 100644 index 0000000000..affdf62ce0 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vwsub_vx.h @@ -0,0 +1,6 @@ +// vwsub.vx vd, vs2, rs1 +VI_CHECK_DSS(false); +VI_VX_LOOP_WIDEN +({ + VI_WIDE_OP_AND_ASSIGN(vs2, rs1, 0, -, +, int); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vwsub_wv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vwsub_wv.h new file mode 100644 index 0000000000..10db7308e2 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vwsub_wv.h @@ -0,0 +1,6 @@ +// vwsub.wv vd, vs2, vs1 +VI_CHECK_DDS(true); +VI_VV_LOOP_WIDEN +({ + VI_WIDE_WVX_OP(vs1, -, int); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vwsub_wx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vwsub_wx.h new file mode 100644 index 0000000000..f72341ba80 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vwsub_wx.h @@ -0,0 +1,6 @@ +// vwsub.wx vd, vs2, rs1 +VI_CHECK_DDS(false); +VI_VX_LOOP_WIDEN +({ + VI_WIDE_WVX_OP(rs1, -, int); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vwsubu_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vwsubu_vv.h new file mode 100644 index 0000000000..cf68adb9fa --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vwsubu_vv.h @@ -0,0 +1,6 @@ +// vwsubu.vv vd, vs2, vs1 +VI_CHECK_DSS(true); +VI_VV_LOOP_WIDEN +({ + VI_WIDE_OP_AND_ASSIGN(vs2, vs1, 0, -, +, uint); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vwsubu_vx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vwsubu_vx.h new file mode 100644 index 0000000000..3e972dd211 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vwsubu_vx.h @@ -0,0 +1,6 @@ +// vwsubu.vx vd, vs2, rs1 +VI_CHECK_DSS(false); +VI_VX_LOOP_WIDEN +({ + VI_WIDE_OP_AND_ASSIGN(vs2, rs1, 0, -, +, uint); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vwsubu_wv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vwsubu_wv.h new file mode 100644 index 0000000000..3687c3d237 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vwsubu_wv.h @@ -0,0 +1,6 @@ +// vwsubu.wv vd, vs2, vs1 +VI_CHECK_DDS(true); +VI_VV_LOOP_WIDEN +({ + VI_WIDE_WVX_OP(vs1, -, uint); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vwsubu_wx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vwsubu_wx.h new file mode 100644 index 0000000000..c7f20edd79 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vwsubu_wx.h @@ -0,0 +1,6 @@ +// vwsubu.wx vd, vs2, rs1 +VI_CHECK_DDS(false); +VI_VX_LOOP_WIDEN +({ + VI_WIDE_WVX_OP(rs1, -, uint); +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vxor_vi.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vxor_vi.h new file mode 100644 index 0000000000..b2dcf946dc --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vxor_vi.h @@ -0,0 +1,5 @@ +// vxor +VI_VI_LOOP +({ + vd = simm5 ^ vs2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vxor_vv.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vxor_vv.h new file mode 100644 index 0000000000..c37b6ab729 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vxor_vv.h @@ -0,0 +1,5 @@ +// vxor +VI_VV_LOOP +({ + vd = vs1 ^ vs2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vxor_vx.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vxor_vx.h new file mode 100644 index 0000000000..8021e0e851 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vxor_vx.h @@ -0,0 +1,5 @@ +// vxor +VI_VX_LOOP +({ + vd = rs1 ^ vs2; +}) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vzext_vf2.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vzext_vf2.h new file mode 100644 index 0000000000..100f2e359a --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vzext_vf2.h @@ -0,0 +1 @@ +VI_VV_EXT(2, uint); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vzext_vf4.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vzext_vf4.h new file mode 100644 index 0000000000..6ff920e0bc --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vzext_vf4.h @@ -0,0 +1 @@ +VI_VV_EXT(4, uint); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/vzext_vf8.h b/vendor/riscv/riscv-isa-sim/riscv/insns/vzext_vf8.h new file mode 100644 index 0000000000..b1762fbf67 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/vzext_vf8.h @@ -0,0 +1 @@ +VI_VV_EXT(8, uint); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/wfi.h b/vendor/riscv/riscv-isa-sim/riscv/insns/wfi.h new file mode 100644 index 0000000000..3411da0ce1 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/wfi.h @@ -0,0 +1,13 @@ +if (STATE.v && STATE.prv == PRV_U) { + require_novirt(); +} else if (get_field(STATE.mstatus->read(), MSTATUS_TW)) { + require_privilege(PRV_M); +} else if (STATE.v) { // VS-mode + if (get_field(STATE.hstatus->read(), HSTATUS_VTW)) + require_novirt(); +} else if (p->extension_enabled('S')) { + // When S-mode is implemented, then executing WFI in + // U-mode causes an illegal instruction exception. + require_privilege(PRV_S); +} +wfi(); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/xnor.h b/vendor/riscv/riscv-isa-sim/riscv/insns/xnor.h new file mode 100644 index 0000000000..ccf1c9f77b --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/xnor.h @@ -0,0 +1,2 @@ +require_either_extension(EXT_ZBB, EXT_ZBKB); +WRITE_RD(RS1 ^ ~RS2); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/xor.h b/vendor/riscv/riscv-isa-sim/riscv/insns/xor.h new file mode 100644 index 0000000000..771efa7fa0 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/xor.h @@ -0,0 +1 @@ +WRITE_RD(RS1 ^ RS2); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/xori.h b/vendor/riscv/riscv-isa-sim/riscv/insns/xori.h new file mode 100644 index 0000000000..33ce630741 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/xori.h @@ -0,0 +1 @@ +WRITE_RD(insn.i_imm() ^ RS1); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/xperm16.h b/vendor/riscv/riscv-isa-sim/riscv/insns/xperm16.h new file mode 100644 index 0000000000..6b0ad51f0e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/xperm16.h @@ -0,0 +1,2 @@ +require_extension(EXT_XZBP); +WRITE_RD(sext_xlen(xperm(RS1, RS2, 4, xlen))); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/xperm32.h b/vendor/riscv/riscv-isa-sim/riscv/insns/xperm32.h new file mode 100644 index 0000000000..64d90a406d --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/xperm32.h @@ -0,0 +1,3 @@ +require_rv64; +require_extension(EXT_XZBP); +WRITE_RD(xperm(RS1, RS2, 5, xlen)); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/xperm4.h b/vendor/riscv/riscv-isa-sim/riscv/insns/xperm4.h new file mode 100644 index 0000000000..38800f3bfb --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/xperm4.h @@ -0,0 +1,2 @@ +require_either_extension(EXT_ZBKX, EXT_XZBP); +WRITE_RD(sext_xlen(xperm(RS1, RS2, 2, xlen))); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/xperm8.h b/vendor/riscv/riscv-isa-sim/riscv/insns/xperm8.h new file mode 100644 index 0000000000..c272d66949 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/xperm8.h @@ -0,0 +1,2 @@ +require_either_extension(EXT_ZBKX, EXT_XZBP); +WRITE_RD(sext_xlen(xperm(RS1, RS2, 3, xlen))); diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/zunpkd810.h b/vendor/riscv/riscv-isa-sim/riscv/insns/zunpkd810.h new file mode 100644 index 0000000000..88434deea1 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/zunpkd810.h @@ -0,0 +1 @@ +P_ZUNPKD8(1, 0) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/zunpkd820.h b/vendor/riscv/riscv-isa-sim/riscv/insns/zunpkd820.h new file mode 100644 index 0000000000..f2065081fa --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/zunpkd820.h @@ -0,0 +1 @@ +P_ZUNPKD8(2, 0) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/zunpkd830.h b/vendor/riscv/riscv-isa-sim/riscv/insns/zunpkd830.h new file mode 100644 index 0000000000..13655149cb --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/zunpkd830.h @@ -0,0 +1 @@ +P_ZUNPKD8(3, 0) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/zunpkd831.h b/vendor/riscv/riscv-isa-sim/riscv/insns/zunpkd831.h new file mode 100644 index 0000000000..8febe77f6d --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/zunpkd831.h @@ -0,0 +1 @@ +P_ZUNPKD8(3, 1) diff --git a/vendor/riscv/riscv-isa-sim/riscv/insns/zunpkd832.h b/vendor/riscv/riscv-isa-sim/riscv/insns/zunpkd832.h new file mode 100644 index 0000000000..f14030bcc0 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/insns/zunpkd832.h @@ -0,0 +1 @@ +P_ZUNPKD8(3, 2) diff --git a/vendor/riscv/riscv-isa-sim/riscv/interactive.cc b/vendor/riscv/riscv-isa-sim/riscv/interactive.cc new file mode 100644 index 0000000000..d9fb39b41a --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/interactive.cc @@ -0,0 +1,801 @@ +// See LICENSE for license details. + +#include "config.h" +#include "sim.h" +#include "decode.h" +#include "decode_macros.h" +#include "disasm.h" +#include "mmu.h" +#include "vector_unit.h" +#include "socketif.h" +#include <sys/mman.h> +#include <termios.h> +#include <map> +#include <iostream> +#include <iomanip> +#include <climits> +#include <cinttypes> +#include <assert.h> +#include <stdlib.h> +#include <unistd.h> +#include <sstream> +#include <string> +#include <vector> +#include <algorithm> +#include <math.h> + +#ifdef __GNUC__ +# pragma GCC diagnostic ignored "-Wunused-parameter" +#endif + +#define MAX_CMD_STR 40 // maximum possible size of a command line +#define BITS_PER_CHAR 8 + +#define STR_(X) #X // these definitions allow to use a macro as a string +#define STR(X) STR_(X) + +DECLARE_TRAP(-1, interactive) + +static std::vector<std::string> history_commands; + +// if input an arrow/home key, there will be a 3/4-key input sequence, +// so we use an uint32_t to buffer it +typedef uint32_t keybuffer_t; + +enum KEYCODE +{ + KEYCODE_HEADER0 = 0x1b, + KEYCODE_HEADER1 = 0x1b5b, + KEYCODE_LEFT = 0x1b5b44, + KEYCODE_RIGHT = 0x1b5b43, + KEYCODE_UP = 0x1b5b41, + KEYCODE_DOWN = 0x1b5b42, + KEYCODE_HOME0 = 0x1b5b48, + KEYCODE_HOME1_0 = 0x1b5b31, + KEYCODE_HOME1_1 = 0x1b5b317e, + KEYCODE_END0 = 0x1b5b46, + KEYCODE_END1_0 = 0x1b5b34, + KEYCODE_END1_1 = 0x1b5b347e, + KEYCODE_BACKSPACE0 = 0x8, + KEYCODE_BACKSPACE1_0 = 0x1b5b33, + KEYCODE_BACKSPACE1_1 = 0x1b5b337e, + KEYCODE_BACKSPACE2 = 0x7f, + KEYCODE_ENTER = '\n', +}; + +processor_t *sim_t::get_core(const std::string& i) +{ + char *ptr; + unsigned long p = strtoul(i.c_str(), &ptr, 10); + if (*ptr || p >= procs.size()) + throw trap_interactive(); + return get_core(p); +} + +static void clear_str(bool noncanonical, int fd, std::string target_str) +{ + if (noncanonical) + { + std::string clear_motion; + clear_motion += '\r'; + for (unsigned i = 0; i < target_str.size(); i++) + { + clear_motion += ' '; + } + clear_motion += '\r'; + if (write(fd, clear_motion.c_str(), clear_motion.size() + 1)) + ; // shut up gcc + } +} + +static void send_key(bool noncanonical, int fd, keybuffer_t key_code, const int len) +{ + if (noncanonical) + { + std::string key_motion; + for (int i = len - 1; i >= 0; i--) + { + key_motion += (char) ((key_code >> (i * BITS_PER_CHAR)) & 0xff); + } + if (write(fd, key_motion.c_str(), len) != len) + ; // shut up gcc + } +} + +static std::string readline(int fd) +{ + struct termios tios; + // try to make sure the terminal is noncanonical and nonecho + if (tcgetattr(fd, &tios) == 0) + { + tios.c_lflag &= (~ICANON); + tios.c_lflag &= (~ECHO); + tcsetattr(fd, TCSANOW, &tios); + } + bool noncanonical = tcgetattr(fd, &tios) == 0 && (tios.c_lflag & ICANON) == 0; + + std::string s_head = std::string("(spike) "); + std::string s = s_head; + keybuffer_t key_buffer = 0; + // index for up/down arrow + size_t history_index = 0; + // position for left/right arrow + size_t cursor_pos = s.size(); + const size_t initial_s_len = cursor_pos; + std::cerr << s << std::flush; + for (char ch; read(fd, &ch, 1) == 1; ) + { + uint32_t keycode = key_buffer << BITS_PER_CHAR | ch; + switch (keycode) + { + // the partial keycode, add to the key_buffer + case KEYCODE_HEADER0: + case KEYCODE_HEADER1: + case KEYCODE_HOME1_0: + case KEYCODE_END1_0: + case KEYCODE_BACKSPACE1_0: + key_buffer = keycode; + break; + // for backspace key + case KEYCODE_BACKSPACE0: + case KEYCODE_BACKSPACE1_1: + case KEYCODE_BACKSPACE2: + if (cursor_pos <= initial_s_len) + continue; + clear_str(noncanonical, fd, s); + cursor_pos--; + s.erase(cursor_pos, 1); + if (noncanonical && write(fd, s.c_str(), s.size() + 1) != 1) + ; // shut up gcc + // move cursor by left arrow key + for (unsigned i = 0; i < s.size() - cursor_pos; i++) { + send_key(noncanonical, fd, KEYCODE_LEFT, 3); + } + key_buffer = 0; + break; + case KEYCODE_HOME0: + case KEYCODE_HOME1_1: + // move cursor by left arrow key + for (unsigned i = 0; i < cursor_pos - initial_s_len; i++) { + send_key(noncanonical, fd, KEYCODE_LEFT, 3); + } + cursor_pos = initial_s_len; + key_buffer = 0; + break; + case KEYCODE_END0: + case KEYCODE_END1_1: + // move cursor by right arrow key + for (unsigned i = 0; i < s.size() - cursor_pos; i++) { + send_key(noncanonical, fd, KEYCODE_RIGHT, 3); + } + cursor_pos = s.size(); + key_buffer = 0; + break; + case KEYCODE_UP: + // up arrow + if (history_commands.size() > 0) { + clear_str(noncanonical, fd, s); + history_index = std::min(history_commands.size(), history_index + 1); + s = history_commands[history_commands.size() - history_index]; + if (noncanonical && write(fd, s.c_str(), s.size() + 1)) + ; // shut up gcc + cursor_pos = s.size(); + } + key_buffer = 0; + break; + case KEYCODE_DOWN: + // down arrow + if (history_commands.size() > 0) { + clear_str(noncanonical, fd, s); + history_index = std::max(0, (int)history_index - 1); + if (history_index == 0) { + s = s_head; + } else { + s = history_commands[history_commands.size() - history_index]; + } + if (noncanonical && write(fd, s.c_str(), s.size() + 1)) + ; // shut up gcc + cursor_pos = s.size(); + } + key_buffer = 0; + break; + case KEYCODE_LEFT: + if (s.size() > initial_s_len) { + cursor_pos = cursor_pos - 1; + if ((int)cursor_pos < (int)initial_s_len) { + cursor_pos = initial_s_len; + } else { + send_key(noncanonical, fd, KEYCODE_LEFT, 3); + } + } + key_buffer = 0; + break; + case KEYCODE_RIGHT: + if (s.size() > initial_s_len) { + cursor_pos = cursor_pos + 1; + if (cursor_pos > s.size()) { + cursor_pos = s.size(); + } else { + send_key(noncanonical, fd, KEYCODE_RIGHT, 3); + } + } + key_buffer = 0; + break; + case KEYCODE_ENTER: + if (noncanonical && write(fd, &ch, 1) != 1) + ; // shut up gcc + if (s.size() > initial_s_len && (history_commands.size() == 0 || s != history_commands[history_commands.size() - 1])) { + history_commands.push_back(s); + } + return s.substr(initial_s_len); + default: + DEFAULT_KEY: + // unknown buffered key, do nothing + if (key_buffer != 0) { + key_buffer = 0; + break; + } + clear_str(noncanonical, fd, s); + s.insert(cursor_pos, 1, ch); + cursor_pos++; + if (noncanonical && write(fd, s.c_str(), s.size() + 1) != 1) + ; // shut up gcc + // send left arrow key to move cursor + for (unsigned i = 0; i < s.size() - cursor_pos; i++) { + send_key(noncanonical, fd, KEYCODE_LEFT, 3); + } + break; + } + } + return s.substr(initial_s_len); +} + +void sim_t::interactive() +{ + if (ctrlc_pressed) { + next_interactive_action = std::nullopt; + ctrlc_pressed = false; + } + + if (next_interactive_action.has_value()) { + ctrlc_pressed = false; + auto f = next_interactive_action.value(); + next_interactive_action = std::nullopt; + return f(); + } + + typedef void (sim_t::*interactive_func)(const std::string&, const std::vector<std::string>&); + std::map<std::string,interactive_func> funcs; + + funcs["run"] = &sim_t::interactive_run_noisy; + funcs["r"] = funcs["run"]; + funcs["rs"] = &sim_t::interactive_run_silent; + funcs["vreg"] = &sim_t::interactive_vreg; + funcs["reg"] = &sim_t::interactive_reg; + funcs["freg"] = &sim_t::interactive_freg; + funcs["fregh"] = &sim_t::interactive_fregh; + funcs["fregs"] = &sim_t::interactive_fregs; + funcs["fregd"] = &sim_t::interactive_fregd; + funcs["pc"] = &sim_t::interactive_pc; + funcs["priv"] = &sim_t::interactive_priv; + funcs["mem"] = &sim_t::interactive_mem; + funcs["str"] = &sim_t::interactive_str; + funcs["mtime"] = &sim_t::interactive_mtime; + funcs["mtimecmp"] = &sim_t::interactive_mtimecmp; + funcs["until"] = &sim_t::interactive_until_silent; + funcs["untiln"] = &sim_t::interactive_until_noisy; + funcs["while"] = &sim_t::interactive_until_silent; + funcs["dump"] = &sim_t::interactive_dumpmems; + funcs["quit"] = &sim_t::interactive_quit; + funcs["q"] = funcs["quit"]; + funcs["help"] = &sim_t::interactive_help; + funcs["h"] = funcs["help"]; + + while (!done()) + { + std::string s; + char cmd_str[MAX_CMD_STR+1]; // only used for following fscanf + // first get commands from file, if cmd_file has been set + if (cmd_file && !feof(cmd_file) && fscanf(cmd_file,"%" STR(MAX_CMD_STR) "[^\n]\n", cmd_str)==1) { + // up to MAX_CMD_STR characters before \n, skipping \n + s = cmd_str; + // while we get input from file, output goes to stderr + sout_.rdbuf(std::cerr.rdbuf()); + } else { + // when there are no commands left from file or if there was no file from the beginning + cmd_file = NULL; // mark file pointer as being not valid, so any method can test this easily +#ifdef HAVE_BOOST_ASIO + if (socketif) { + s = socketif->rin(sout_); // get command string from socket or terminal + } + else +#endif + { + s = readline(2); // 2 is stderr, but when doing reads it reverts to stdin + } + } + + std::stringstream ss(s); + std::string cmd, tmp; + std::vector<std::string> args; + + if (!(ss >> cmd)) + { + set_procs_debug(true); + step(1); +#ifdef HAVE_BOOST_ASIO + if (socketif) + socketif->wout(); // socket output, if required +#endif + break; + } + + while (ss >> tmp) + args.push_back(tmp); + + std::ostream out(sout_.rdbuf()); + + try + { + if (funcs.count(cmd)) + (this->*funcs[cmd])(cmd, args); + else + out << "Unknown command " << cmd << std::endl; + } catch(trap_t& t) { + out << "Bad or missing arguments for command " << cmd << std::endl; + } +#ifdef HAVE_BOOST_ASIO + if (socketif) + socketif->wout(); // socket output, if required +#endif + + if (next_interactive_action.has_value()) + break; + } + ctrlc_pressed = false; +} + +void sim_t::interactive_help(const std::string& cmd, const std::vector<std::string>& args) +{ + std::ostream out(sout_.rdbuf()); + out << + "Interactive commands:\n" + "reg <core> [reg] # Display [reg] (all if omitted) in <core>\n" + "freg <core> <reg> # Display float <reg> in <core> as hex\n" + "fregh <core> <reg> # Display half precision <reg> in <core>\n" + "fregs <core> <reg> # Display single precision <reg> in <core>\n" + "fregd <core> <reg> # Display double precision <reg> in <core>\n" + "vreg <core> [reg] # Display vector [reg] (all if omitted) in <core>\n" + "pc <core> # Show current PC in <core>\n" + "priv <core> # Show current privilege level in <core>\n" + "mem [core] <hex addr> # Show contents of virtual memory <hex addr> in [core] (physical memory <hex addr> if omitted)\n" + "str [core] <hex addr> # Show NUL-terminated C string at virtual address <hex addr> in [core] (physical address <hex addr> if omitted)\n" + "dump # Dump physical memory to binary files\n" + "mtime # Show mtime\n" + "mtimecmp <core> # Show mtimecmp for <core>\n" + "until reg <core> <reg> <val> # Stop when <reg> in <core> hits <val>\n" + "untiln reg <core> <reg> <val> # Run noisy and stop when <reg> in <core> hits <val>\n" + "until pc <core> <val> # Stop when PC in <core> hits <val>\n" + "untiln pc <core> <val> # Run noisy and stop when PC in <core> hits <val>\n" + "until mem [core] <addr> <val> # Stop when virtual memory <addr> in [core] (physical address <addr> if omitted) becomes <val>\n" + "untiln mem [core] <addr> <val> # Run noisy and stop when virtual memory <addr> in [core] (physical address <addr> if omitted) becomes <val>\n" + "while reg <core> <reg> <val> # Run while <reg> in <core> is <val>\n" + "while pc <core> <val> # Run while PC in <core> is <val>\n" + "while mem [core] <addr> <val> # Run while virtual memory <addr> in [core] (physical memory <addr> if omitted) is <val>\n" + "run [count] # Resume noisy execution (until CTRL+C, or [count] insns)\n" + "r [count] Alias for run\n" + "rs [count] # Resume silent execution (until CTRL+C, or [count] insns)\n" + "quit # End the simulation\n" + "q Alias for quit\n" + "help # This screen!\n" + "h Alias for help\n" + "Note: Hitting enter is the same as: run 1" + << std::endl; +} + +void sim_t::interactive_run_noisy(const std::string& cmd, const std::vector<std::string>& args) +{ + interactive_run(cmd,args,true); +} + +void sim_t::interactive_run_silent(const std::string& cmd, const std::vector<std::string>& args) +{ + interactive_run(cmd,args,false); +} + +void sim_t::interactive_run(const std::string& cmd, const std::vector<std::string>& args, bool noisy) +{ + size_t steps = args.size() ? atoll(args[0].c_str()) : -1; + set_procs_debug(noisy); + + const size_t actual_steps = std::min(INTERLEAVE, steps); + for (size_t i = 0; i < actual_steps && !ctrlc_pressed && !done(); i++) + step(1); + + if (actual_steps < steps) { + next_interactive_action = [=](){ interactive_run(cmd, {std::to_string(steps - actual_steps)}, noisy); }; + return; + } + + std::ostream out(sout_.rdbuf()); + if (!noisy) out << ":" << std::endl; +} + +void sim_t::interactive_quit(const std::string& cmd, const std::vector<std::string>& args) +{ + exit(0); +} + +reg_t sim_t::get_pc(const std::vector<std::string>& args) +{ + if (args.size() != 1) + throw trap_interactive(); + + processor_t *p = get_core(args[0]); + return p->get_state()->pc; +} + +void sim_t::interactive_pc(const std::string& cmd, const std::vector<std::string>& args) +{ + if (args.size() != 1) + throw trap_interactive(); + + processor_t *p = get_core(args[0]); + int max_xlen = p->get_isa().get_max_xlen(); + + std::ostream out(sout_.rdbuf()); + out << std::hex << std::setfill('0') << "0x" << std::setw(max_xlen/4) + << zext(get_pc(args), max_xlen) << std::endl; +} + +void sim_t::interactive_priv(const std::string& cmd, const std::vector<std::string>& args) +{ + if (args.size() != 1) + throw trap_interactive(); + + processor_t *p = get_core(args[0]); + std::ostream out(sout_.rdbuf()); + out << p->get_privilege_string() << std::endl; +} + +reg_t sim_t::get_reg(const std::vector<std::string>& args) +{ + if (args.size() != 2) + throw trap_interactive(); + + processor_t *p = get_core(args[0]); + + unsigned long r = std::find(xpr_name, xpr_name + NXPR, args[1]) - xpr_name; + if (r == NXPR) { + char *ptr; + r = strtoul(args[1].c_str(), &ptr, 10); + if (*ptr) { + #define DECLARE_CSR(name, number) if (args[1] == #name) return p->get_csr(number); + #include "encoding.h" // generates if's for all csrs + r = NXPR; // else case (csr name not found) + #undef DECLARE_CSR + } + } + + if (r >= NXPR) + throw trap_interactive(); + + return p->get_state()->XPR[r]; +} + +freg_t sim_t::get_freg(const std::vector<std::string>& args, int size) +{ + if (args.size() != 2) + throw trap_interactive(); + + processor_t *p = get_core(args[0]); + if (p->extension_enabled(EXT_ZFINX)) { + int r = std::find(xpr_name, xpr_name + NXPR, args[1]) - xpr_name; + if (r == NXPR) + r = atoi(args[1].c_str()); + if (r >= NXPR) + throw trap_interactive(); + if ((p->get_xlen() == 32) && (size == 64)) { + if (r % 2 != 0) + throw trap_interactive(); + return freg(f64(r== 0 ? reg_t(0) : (READ_REG(r + 1) << 32) + zext32(READ_REG(r)))); + } else { //xlen >= size + return {p->get_state()->XPR[r] | ~(((uint64_t)-1) >> (64 - size)) ,(uint64_t)-1}; + } + } else { + int r = std::find(fpr_name, fpr_name + NFPR, args[1]) - fpr_name; + if (r == NFPR) + r = atoi(args[1].c_str()); + if (r >= NFPR) + throw trap_interactive(); + return p->get_state()->FPR[r]; + } +} + +void sim_t::interactive_vreg(const std::string& cmd, const std::vector<std::string>& args) +{ + if (args.size() < 1) + throw trap_interactive(); + + int rstart = 0; + int rend = NVPR; + if (args.size() >= 2) { + rstart = strtol(args[1].c_str(), NULL, 0); + if (!(rstart >= 0 && rstart < NVPR)) { + rstart = 0; + } else { + rend = rstart + 1; + } + } + + // Show all the regs! + processor_t *p = get_core(args[0]); + const int vlen = (int)(p->VU.get_vlen()) >> 3; + const int elen = (int)(p->VU.get_elen()) >> 3; + const int num_elem = vlen/elen; + + std::ostream out(sout_.rdbuf()); + out << std::dec << "VLEN=" << (vlen << 3) << " bits; ELEN=" << (elen << 3) << " bits" << std::endl; + + for (int r = rstart; r < rend; ++r) { + out << std::setfill (' ') << std::left << std::setw(4) << vr_name[r] << std::right << ": "; + for (int e = num_elem-1; e >= 0; --e) { + uint64_t val; + switch (elen) { + case 8: + val = p->VU.elt<uint64_t>(r, e); + out << std::dec << "[" << e << "]: 0x" << std::hex << std::setfill ('0') << std::setw(16) << val << " "; + break; + case 4: + val = p->VU.elt<uint32_t>(r, e); + out << std::dec << "[" << e << "]: 0x" << std::hex << std::setfill ('0') << std::setw(8) << (uint32_t)val << " "; + break; + case 2: + val = p->VU.elt<uint16_t>(r, e); + out << std::dec << "[" << e << "]: 0x" << std::hex << std::setfill ('0') << std::setw(8) << (uint16_t)val << " "; + break; + case 1: + val = p->VU.elt<uint8_t>(r, e); + out << std::dec << "[" << e << "]: 0x" << std::hex << std::setfill ('0') << std::setw(8) << (int)(uint8_t)val << " "; + break; + } + } + out << std::endl; + } +} + +void sim_t::interactive_reg(const std::string& cmd, const std::vector<std::string>& args) +{ + if (args.size() < 1) + throw trap_interactive(); + + processor_t *p = get_core(args[0]); + int max_xlen = p->get_isa().get_max_xlen(); + + std::ostream out(sout_.rdbuf()); + out << std::hex; + + if (args.size() == 1) { + // Show all the regs! + + for (int r = 0; r < NXPR; ++r) { + out << std::setfill(' ') << std::setw(4) << xpr_name[r] + << ": 0x" << std::setfill('0') << std::setw(max_xlen/4) + << zext(p->get_state()->XPR[r], max_xlen); + if ((r + 1) % 4 == 0) + out << std::endl; + } + } else { + out << "0x" << std::setfill('0') << std::setw(max_xlen/4) + << zext(get_reg(args), max_xlen) << std::endl; + } +} + +union fpr +{ + freg_t r; + float s; + double d; +}; + +void sim_t::interactive_freg(const std::string& cmd, const std::vector<std::string>& args) +{ + freg_t r = get_freg(args, 64); + + std::ostream out(sout_.rdbuf()); + out << std::hex << "0x" << std::setfill ('0') << std::setw(16) << r.v[1] << std::setw(16) << r.v[0] << std::endl; +} + +void sim_t::interactive_fregh(const std::string& cmd, const std::vector<std::string>& args) +{ + fpr f; + f.r = freg(f16_to_f32(f16(get_freg(args, 16)))); + + std::ostream out(sout_.rdbuf()); + out << (isBoxedF32(f.r) ? (double)f.s : NAN) << std::endl; +} + +void sim_t::interactive_fregs(const std::string& cmd, const std::vector<std::string>& args) +{ + fpr f; + f.r = get_freg(args, 32); + + std::ostream out(sout_.rdbuf()); + out << (isBoxedF32(f.r) ? (double)f.s : NAN) << std::endl; +} + +void sim_t::interactive_fregd(const std::string& cmd, const std::vector<std::string>& args) +{ + fpr f; + f.r = get_freg(args, 64); + + std::ostream out(sout_.rdbuf()); + out << (isBoxedF64(f.r) ? f.d : NAN) << std::endl; +} + +reg_t sim_t::get_mem(const std::vector<std::string>& args) +{ + if (args.size() != 1 && args.size() != 2) + throw trap_interactive(); + + std::string addr_str = args[0]; + mmu_t* mmu = debug_mmu; + if (args.size() == 2) + { + processor_t *p = get_core(args[0]); + mmu = p->get_mmu(); + addr_str = args[1]; + } + + reg_t addr = strtol(addr_str.c_str(),NULL,16), val; + if (addr == LONG_MAX) + addr = strtoul(addr_str.c_str(),NULL,16); + + switch (addr % 8) + { + case 0: + val = mmu->load<uint64_t>(addr); + break; + case 4: + val = mmu->load<uint32_t>(addr); + break; + case 2: + case 6: + val = mmu->load<uint16_t>(addr); + break; + default: + val = mmu->load<uint8_t>(addr); + break; + } + return val; +} + +void sim_t::interactive_mem(const std::string& cmd, const std::vector<std::string>& args) +{ + int max_xlen = procs[0]->get_isa().get_max_xlen(); + + std::ostream out(sout_.rdbuf()); + out << std::hex << "0x" << std::setfill('0') << std::setw(max_xlen/4) + << zext(get_mem(args), max_xlen) << std::endl; +} + +void sim_t::interactive_str(const std::string& cmd, const std::vector<std::string>& args) +{ + if (args.size() != 1 && args.size() != 2) + throw trap_interactive(); + + std::string addr_str = args[0]; + mmu_t* mmu = debug_mmu; + if (args.size() == 2) + { + processor_t *p = get_core(args[0]); + mmu = p->get_mmu(); + addr_str = args[1]; + } + + reg_t addr = strtol(addr_str.c_str(),NULL,16); + + std::ostream out(sout_.rdbuf()); + + char ch; + while ((ch = mmu->load<uint8_t>(addr++))) + out << ch; + + out << std::endl; +} + +void sim_t::interactive_until_silent(const std::string& cmd, const std::vector<std::string>& args) +{ + interactive_until(cmd, args, false); +} + +void sim_t::interactive_until_noisy(const std::string& cmd, const std::vector<std::string>& args) +{ + interactive_until(cmd, args, true); +} + +void sim_t::interactive_until(const std::string& cmd, const std::vector<std::string>& args, bool noisy) +{ + bool cmd_until = cmd == "until" || cmd == "untiln"; + + if (args.size() < 3) + throw trap_interactive(); + + if (args.size() == 3) + get_core(args[1]); // make sure that argument is a valid core number + + char *end; + reg_t val = strtol(args[args.size()-1].c_str(),&end,16); + if (val == LONG_MAX) + val = strtoul(args[args.size()-1].c_str(),&end,16); + if (args[args.size()-1].c_str() == end) // not a valid number + throw trap_interactive(); + + // mask bits above max_xlen + int max_xlen = procs[strtol(args[1].c_str(),NULL,10)]->get_isa().get_max_xlen(); + if (max_xlen == 32) val &= 0xFFFFFFFF; + + std::vector<std::string> args2; + args2 = std::vector<std::string>(args.begin()+1,args.end()-1); + + auto func = args[0] == "reg" ? &sim_t::get_reg : + args[0] == "pc" ? &sim_t::get_pc : + args[0] == "mem" ? &sim_t::get_mem : + NULL; + + if (func == NULL) + throw trap_interactive(); + + for (size_t i = 0; i < INTERLEAVE; i++) + { + try + { + reg_t current = (this->*func)(args2); + + // mask bits above max_xlen + if (max_xlen == 32) current &= 0xFFFFFFFF; + + if (cmd_until == (current == val)) + return; + if (ctrlc_pressed) + return; + } + catch (trap_t& t) {} + + set_procs_debug(noisy); + step(1); + } + + next_interactive_action = [=](){ interactive_until(cmd, args, noisy); }; +} + +void sim_t::interactive_dumpmems(const std::string& cmd, const std::vector<std::string>& args) +{ + for (unsigned i = 0; i < mems.size(); i++) { + std::stringstream mem_fname; + mem_fname << "mem.0x" << std::hex << mems[i].first << ".bin"; + + std::ofstream mem_file(mem_fname.str()); + mems[i].second->dump(mem_file); + mem_file.close(); + } +} + +void sim_t::interactive_mtime(const std::string& cmd, const std::vector<std::string>& args) +{ + std::ostream out(sout_.rdbuf()); + out << std::hex << std::setfill('0') << "0x" << std::setw(16) + << clint->get_mtime() << std::endl; +} + +void sim_t::interactive_mtimecmp(const std::string& cmd, const std::vector<std::string>& args) +{ + if (args.size() != 1) + throw trap_interactive(); + + processor_t *p = get_core(args[0]); + std::ostream out(sout_.rdbuf()); + out << std::hex << std::setfill('0') << "0x" << std::setw(16) + << clint->get_mtimecmp(p->get_id()) << std::endl; +} + diff --git a/vendor/riscv/riscv-isa-sim/riscv/isa_parser.cc b/vendor/riscv/riscv-isa-sim/riscv/isa_parser.cc new file mode 100644 index 0000000000..7335a147e4 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/isa_parser.cc @@ -0,0 +1,334 @@ +#include "isa_parser.h" +#include "extension.h" + +static std::string strtolower(const char* str) +{ + std::string res; + for (const char *r = str; *r; r++) + res += std::tolower(*r); + return res; +} + +static void bad_option_string(const char *option, const char *value, + const char *msg) +{ + fprintf(stderr, "error: bad %s option '%s'. %s\n", option, value, msg); + abort(); +} + +static void bad_isa_string(const char* isa, const char* msg) +{ + bad_option_string("--isa", isa, msg); +} + +static void bad_priv_string(const char* priv) +{ + fprintf(stderr, "error: bad --priv option %s\n", priv); + abort(); +} + +isa_parser_t::isa_parser_t(const char* str, const char *priv) +{ + isa_string = strtolower(str); + const char* all_subsets = "mafdqchpv"; + + if (isa_string.compare(0, 4, "rv32") == 0) + max_xlen = 32; + else if (isa_string.compare(0, 4, "rv64") == 0) + max_xlen = 64; + else + bad_isa_string(str, "ISA strings must begin with RV32 or RV64"); + + switch (isa_string[4]) { + case 'g': + // G = IMAFD_Zicsr_Zifencei, but Spike includes the latter two + // unconditionally, so they need not be explicitly added here. + isa_string = isa_string.substr(0, 4) + "imafd" + isa_string.substr(5); + // Fall through + case 'i': + extension_table['I'] = true; + break; + + case 'e': + extension_table['E'] = true; + break; + + default: + bad_isa_string(str, ("'" + isa_string.substr(0, 4) + "' must be followed by I, E, or G").c_str()); + } + + const char* isa_str = isa_string.c_str(); + auto p = isa_str, subset = all_subsets; + for (p += 5; islower(*p) && !strchr("zsx", *p); ++p) { + while (*subset && (*p != *subset)) + ++subset; + + if (!*subset) { + if (strchr(all_subsets, *p)) + bad_isa_string(str, ("Extension '" + std::string(1, *p) + "' appears too late in ISA string").c_str()); + else + bad_isa_string(str, ("Unsupported extension '" + std::string(1, *p) + "'").c_str()); + } + + switch (*p) { + case 'p': extension_table[EXT_ZBPBO] = true; + extension_table[EXT_ZPN] = true; + extension_table[EXT_ZPSFOPERAND] = true; + extension_table[EXT_ZMMUL] = true; break; + case 'v': // even rv32iv implies double float + case 'q': extension_table['D'] = true; + // Fall through + case 'd': extension_table['F'] = true; + } + extension_table[toupper(*p)] = true; + while (isdigit(*(p + 1))) { + ++p; // skip major version, point, and minor version if presented + if (*(p + 1) == 'p') ++p; + } + p += *(p + 1) == '_'; // underscores may be used to improve readability + } + + while (islower(*p) || (*p == '_')) { + p += *p == '_'; // first underscore is optional + auto end = p; + do ++end; while (*end && *end != '_'); + auto ext_str = std::string(p, end); + if (ext_str == "zfh" || ext_str == "zfhmin") { + if (!extension_table['F']) + bad_isa_string(str, ("'" + ext_str + "' extension requires 'F'").c_str()); + extension_table[EXT_ZFHMIN] = true; + if (ext_str == "zfh") + extension_table[EXT_ZFH] = true; + } else if (ext_str == "zvfh" || ext_str == "zvfhmin") { + if (!extension_table['V']) + bad_isa_string(str, ("'" + ext_str + "' extension requires 'V'").c_str()); + + extension_table[EXT_ZVFHMIN] = true; + + if (ext_str == "zvfh") { + extension_table[EXT_ZVFH] = true; + // Zvfh implies Zfhmin + extension_table[EXT_ZFHMIN] = true; + } + } else if (ext_str == "zicsr") { + // Spike necessarily has Zicsr, because + // Zicsr is implied by the privileged architecture + } else if (ext_str == "zifencei") { + // For compatibility with version 2.0 of the base ISAs, we + // unconditionally include FENCE.I, so Zifencei adds nothing more. + } else if (ext_str == "zihintpause") { + // HINTs encoded in base-ISA instructions are always present. + } else if (ext_str == "zihintntl") { + // HINTs encoded in base-ISA instructions are always present. + } else if (ext_str == "zmmul") { + extension_table[EXT_ZMMUL] = true; + } else if (ext_str == "zba") { + extension_table[EXT_ZBA] = true; + } else if (ext_str == "zbb") { + extension_table[EXT_ZBB] = true; + } else if (ext_str == "zbc") { + extension_table[EXT_ZBC] = true; + } else if (ext_str == "zbs") { + extension_table[EXT_ZBS] = true; + } else if (ext_str == "zbkb") { + extension_table[EXT_ZBKB] = true; + } else if (ext_str == "zbkc") { + extension_table[EXT_ZBKC] = true; + } else if (ext_str == "zbkx") { + extension_table[EXT_ZBKX] = true; + } else if (ext_str == "zdinx") { + extension_table[EXT_ZFINX] = true; + extension_table[EXT_ZDINX] = true; + } else if (ext_str == "zfinx") { + extension_table[EXT_ZFINX] = true; + } else if (ext_str == "zhinx") { + extension_table[EXT_ZFINX] = true; + extension_table[EXT_ZHINX] = true; + extension_table[EXT_ZHINXMIN] = true; + } else if (ext_str == "zhinxmin") { + extension_table[EXT_ZFINX] = true; + extension_table[EXT_ZHINXMIN] = true; + } else if (ext_str == "zce") { + extension_table[EXT_ZCA] = true; + extension_table[EXT_ZCB] = true; + extension_table[EXT_ZCMT] = true; + extension_table[EXT_ZCMP] = true; + if (extension_table['F'] && max_xlen == 32) + extension_table[EXT_ZCF] = true; + } else if (ext_str == "zca") { + extension_table[EXT_ZCA] = true; + } else if (ext_str == "zcf") { + if (max_xlen != 32) + bad_isa_string(str, "'Zcf' requires RV32"); + extension_table[EXT_ZCF] = true; + } else if (ext_str == "zcb") { + extension_table[EXT_ZCB] = true; + } else if (ext_str == "zcd") { + extension_table[EXT_ZCD] = true; + } else if (ext_str == "zcmp") { + extension_table[EXT_ZCMP] = true; + } else if (ext_str == "zcmt") { + extension_table[EXT_ZCMT] = true; + } else if (ext_str == "zk") { + extension_table[EXT_ZBKB] = true; + extension_table[EXT_ZBKC] = true; + extension_table[EXT_ZBKX] = true; + extension_table[EXT_ZKND] = true; + extension_table[EXT_ZKNE] = true; + extension_table[EXT_ZKNH] = true; + extension_table[EXT_ZKR] = true; + } else if (ext_str == "zkn") { + extension_table[EXT_ZBKB] = true; + extension_table[EXT_ZBKC] = true; + extension_table[EXT_ZBKX] = true; + extension_table[EXT_ZKND] = true; + extension_table[EXT_ZKNE] = true; + extension_table[EXT_ZKNH] = true; + } else if (ext_str == "zknd") { + extension_table[EXT_ZKND] = true; + } else if (ext_str == "zkne") { + extension_table[EXT_ZKNE] = true; + } else if (ext_str == "zknh") { + extension_table[EXT_ZKNH] = true; + } else if (ext_str == "zks") { + extension_table[EXT_ZBKB] = true; + extension_table[EXT_ZBKC] = true; + extension_table[EXT_ZBKX] = true; + extension_table[EXT_ZKSED] = true; + extension_table[EXT_ZKSH] = true; + } else if (ext_str == "zksed") { + extension_table[EXT_ZKSED] = true; + } else if (ext_str == "zksh") { + extension_table[EXT_ZKSH] = true; + } else if (ext_str == "zkr") { + extension_table[EXT_ZKR] = true; + } else if (ext_str == "zkt") { + } else if (ext_str == "smepmp") { + extension_table[EXT_SMEPMP] = true; + } else if (ext_str == "smstateen") { + extension_table[EXT_SMSTATEEN] = true; + } else if (ext_str == "smrnmi") { + extension_table[EXT_SMRNMI] = true; + } else if (ext_str == "sscofpmf") { + extension_table[EXT_SSCOFPMF] = true; + } else if (ext_str == "svadu") { + extension_table[EXT_SVADU] = true; + } else if (ext_str == "svnapot") { + extension_table[EXT_SVNAPOT] = true; + } else if (ext_str == "svpbmt") { + extension_table[EXT_SVPBMT] = true; + } else if (ext_str == "svinval") { + extension_table[EXT_SVINVAL] = true; + } else if (ext_str == "zfa") { + extension_table[EXT_ZFA] = true; + } else if (ext_str == "zicbom") { + extension_table[EXT_ZICBOM] = true; + } else if (ext_str == "zicboz") { + extension_table[EXT_ZICBOZ] = true; + } else if (ext_str == "zicbop") { + } else if (ext_str == "zicntr") { + extension_table[EXT_ZICNTR] = true; + } else if (ext_str == "zicond") { + extension_table[EXT_ZICOND] = true; + } else if (ext_str == "zihpm") { + extension_table[EXT_ZIHPM] = true; + } else if (ext_str == "sstc") { + extension_table[EXT_SSTC] = true; + } else if (ext_str[0] == 'x') { + extension_table['X'] = true; + if (ext_str == "xbitmanip") { + extension_table[EXT_XZBP] = true; + extension_table[EXT_XZBS] = true; + extension_table[EXT_XZBE] = true; + extension_table[EXT_XZBF] = true; + extension_table[EXT_XZBC] = true; + extension_table[EXT_XZBM] = true; + extension_table[EXT_XZBR] = true; + extension_table[EXT_XZBT] = true; + } else if (ext_str == "xzbp") { + extension_table[EXT_XZBP] = true; + } else if (ext_str == "xzbs") { + extension_table[EXT_XZBS] = true; + } else if (ext_str == "xzbe") { + extension_table[EXT_XZBE] = true; + } else if (ext_str == "xzbf") { + extension_table[EXT_XZBF] = true; + } else if (ext_str == "xzbc") { + extension_table[EXT_XZBC] = true; + } else if (ext_str == "xzbm") { + extension_table[EXT_XZBM] = true; + } else if (ext_str == "xzbr") { + extension_table[EXT_XZBR] = true; + } else if (ext_str == "xzbt") { + extension_table[EXT_XZBT] = true; + } else if (ext_str.size() == 1) { + bad_isa_string(str, "single 'X' is not a proper name"); + } else if (ext_str != "xdummy") { + extension_t* x = find_extension(ext_str.substr(1).c_str())(); + if (!extensions.insert(std::make_pair(x->name(), x)).second) { + fprintf(stderr, "extensions must have unique names (got two named \"%s\"!)\n", x->name()); + abort(); + } + } + } else { + bad_isa_string(str, ("unsupported extension: " + ext_str).c_str()); + } + p = end; + } + if (*p) { + bad_isa_string(str, ("can't parse: " + std::string(p)).c_str()); + } + + if (extension_table['C']) { + extension_table[EXT_ZCA] = true; + if (extension_table['F'] && max_xlen == 32) + extension_table[EXT_ZCF] = true; + if (extension_table['D']) + extension_table[EXT_ZCD] = true; + } + + if (extension_table[EXT_ZFINX] && extension_table['F']) { + bad_isa_string(str, ("Zfinx/Zdinx/Zhinx{min} extensions conflict with 'F/D/Q/Zfh{min}' extensions")); + } + + if (extension_table[EXT_ZCF] && !extension_table['F']) { + bad_isa_string(str, "'Zcf' extension requires 'F' extension"); + } + + if (extension_table[EXT_ZCD] && !extension_table['D']) { + bad_isa_string(str, "'Zcd' extension requires 'D' extension"); + } + + if ((extension_table[EXT_ZCMP] || extension_table[EXT_ZCMT]) && extension_table[EXT_ZCD]) { + bad_isa_string(str, "Zcmp' and 'Zcmt' exensions are incompatible with 'Zcd' extension"); + } + + if ((extension_table[EXT_ZCF] || extension_table[EXT_ZCD] || extension_table[EXT_ZCB] || + extension_table[EXT_ZCMP] || extension_table[EXT_ZCMT]) && !extension_table[EXT_ZCA]) { + bad_isa_string(str, "'Zcf/Zcd/Zcb/Zcmp/Zcmt' extensions require 'Zca' extension"); + } + + std::string lowercase = strtolower(priv); + bool user = false, supervisor = false; + + if (lowercase == "m") + ; + else if (lowercase == "mu") + user = true; + else if (lowercase == "msu") + user = supervisor = true; + else + bad_priv_string(priv); + + extension_table['U'] = user; + extension_table['S'] = supervisor; + + if (extension_table['H'] && !supervisor) + bad_isa_string(str, "'H' extension requires S mode"); + + max_isa = max_xlen == 32 ? reg_t(1) << 30 : reg_t(2) << 62; + for (unsigned char ch = 'A'; ch <= 'Z'; ch++) { + if (extension_table[ch]) + max_isa |= 1UL << (ch - 'A'); + } +} diff --git a/vendor/riscv/riscv-isa-sim/riscv/isa_parser.h b/vendor/riscv/riscv-isa-sim/riscv/isa_parser.h new file mode 100644 index 0000000000..9effd164d8 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/isa_parser.h @@ -0,0 +1,110 @@ +// See LICENSE for license details. +#ifndef _RISCV_ISA_PARSER_H +#define _RISCV_ISA_PARSER_H + +#include "decode.h" + +#include <bitset> +#include <string> +#include <unordered_map> + +class extension_t; + +typedef enum { + // 65('A') ~ 90('Z') is reserved for standard isa in misa + EXT_ZFH = 'Z' + 1, + EXT_ZFHMIN, + EXT_ZBA, + EXT_ZBB, + EXT_ZBC, + EXT_ZBS, + EXT_ZBKB, + EXT_ZBKC, + EXT_ZBKX, + EXT_ZCA, + EXT_ZCB, + EXT_ZCD, + EXT_ZCF, + EXT_ZCMP, + EXT_ZCMT, + EXT_ZKND, + EXT_ZKNE, + EXT_ZKNH, + EXT_ZKSED, + EXT_ZKSH, + EXT_ZKR, + EXT_ZMMUL, + EXT_ZBPBO, + EXT_ZPN, + EXT_ZPSFOPERAND, + EXT_ZVFH, + EXT_ZVFHMIN, + EXT_SMEPMP, + EXT_SMSTATEEN, + EXT_SMRNMI, + EXT_SSCOFPMF, + EXT_SVADU, + EXT_SVNAPOT, + EXT_SVPBMT, + EXT_SVINVAL, + EXT_ZDINX, + EXT_ZFA, + EXT_ZFINX, + EXT_ZHINX, + EXT_ZHINXMIN, + EXT_ZICBOM, + EXT_ZICBOZ, + EXT_ZICNTR, + EXT_ZICOND, + EXT_ZIHPM, + EXT_XZBP, + EXT_XZBS, + EXT_XZBE, + EXT_XZBF, + EXT_XZBC, + EXT_XZBM, + EXT_XZBR, + EXT_XZBT, + EXT_SSTC, + NUM_ISA_EXTENSIONS +} isa_extension_t; + +typedef enum { + IMPL_MMU_SV32, + IMPL_MMU_SV39, + IMPL_MMU_SV48, + IMPL_MMU_SV57, + IMPL_MMU_SBARE, + IMPL_MMU, + IMPL_MMU_VMID, + IMPL_MMU_ASID, +} impl_extension_t; + +class isa_parser_t { +public: + isa_parser_t(const char* str, const char *priv); + ~isa_parser_t() {}; + unsigned get_max_xlen() const { return max_xlen; } + reg_t get_max_isa() const { return max_isa; } + std::string get_isa_string() const { return isa_string; } + bool extension_enabled(unsigned char ext) const { + return extension_enabled(isa_extension_t(ext)); + } + bool extension_enabled(isa_extension_t ext) const { + return extension_table[ext]; + } + + std::bitset<NUM_ISA_EXTENSIONS> get_extension_table() const { return extension_table; } + + const std::unordered_map<std::string, extension_t*> & + get_extensions() const { return extensions; } + +protected: + unsigned max_xlen; + reg_t max_isa; + std::bitset<NUM_ISA_EXTENSIONS> extension_table; + std::string isa_string; + std::unordered_map<std::string, extension_t*> extensions; +}; + +#endif diff --git a/vendor/riscv/riscv-isa-sim/riscv/jtag_dtm.cc b/vendor/riscv/riscv-isa-sim/riscv/jtag_dtm.cc new file mode 100644 index 0000000000..9ca38afbed --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/jtag_dtm.cc @@ -0,0 +1,204 @@ +#include <stdio.h> + +#include "decode.h" +#include "jtag_dtm.h" +#include "debug_module.h" +#include "debug_defines.h" + +#if 0 +# define D(x) x +#else +# define D(x) +#endif + +enum { + IR_IDCODE=1, + IR_DTMCONTROL=0x10, + IR_DBUS=0x11, + IR_BYPASS=0x1f +}; + +#define DTMCONTROL_VERSION 0xf +#define DTMCONTROL_ABITS (0x3f << 4) +#define DTMCONTROL_DMISTAT (3<<10) +#define DTMCONTROL_IDLE (7<<12) +#define DTMCONTROL_DMIRESET (1<<16) +#define DTMCONTROL_DMIHARDRESET (1<<17) + +#define DMI_OP 3 +#define DMI_DATA (0xffffffffLL<<2) +#define DMI_ADDRESS ((1LL<<(abits+34)) - (1LL<<34)) + +#define DMI_OP_STATUS_SUCCESS 0 +#define DMI_OP_STATUS_RESERVED 1 +#define DMI_OP_STATUS_FAILED 2 +#define DMI_OP_STATUS_BUSY 3 + +#define DMI_OP_NOP 0 +#define DMI_OP_READ 1 +#define DMI_OP_WRITE 2 +#define DMI_OP_RESERVED 3 + +jtag_dtm_t::jtag_dtm_t(debug_module_t *dm, unsigned required_rti_cycles) : + dm(dm), required_rti_cycles(required_rti_cycles), + _tck(false), _tms(false), _tdi(false), _tdo(false), + dtmcontrol((abits << DTM_DTMCS_ABITS_OFFSET) | 1), + dmi(DMI_OP_STATUS_SUCCESS << DTM_DMI_OP_OFFSET), + bypass(0), + _state(TEST_LOGIC_RESET) +{ +} + +void jtag_dtm_t::reset() { + _state = TEST_LOGIC_RESET; + busy_stuck = false; + rti_remaining = 0; + dmi = 0; +} + +void jtag_dtm_t::set_pins(bool tck, bool tms, bool tdi) { + const jtag_state_t next[16][2] = { + /* TEST_LOGIC_RESET */ { RUN_TEST_IDLE, TEST_LOGIC_RESET }, + /* RUN_TEST_IDLE */ { RUN_TEST_IDLE, SELECT_DR_SCAN }, + /* SELECT_DR_SCAN */ { CAPTURE_DR, SELECT_IR_SCAN }, + /* CAPTURE_DR */ { SHIFT_DR, EXIT1_DR }, + /* SHIFT_DR */ { SHIFT_DR, EXIT1_DR }, + /* EXIT1_DR */ { PAUSE_DR, UPDATE_DR }, + /* PAUSE_DR */ { PAUSE_DR, EXIT2_DR }, + /* EXIT2_DR */ { SHIFT_DR, UPDATE_DR }, + /* UPDATE_DR */ { RUN_TEST_IDLE, SELECT_DR_SCAN }, + /* SELECT_IR_SCAN */ { CAPTURE_IR, TEST_LOGIC_RESET }, + /* CAPTURE_IR */ { SHIFT_IR, EXIT1_IR }, + /* SHIFT_IR */ { SHIFT_IR, EXIT1_IR }, + /* EXIT1_IR */ { PAUSE_IR, UPDATE_IR }, + /* PAUSE_IR */ { PAUSE_IR, EXIT2_IR }, + /* EXIT2_IR */ { SHIFT_IR, UPDATE_IR }, + /* UPDATE_IR */ { RUN_TEST_IDLE, SELECT_DR_SCAN } + }; + + if (!_tck && tck) { + // Positive clock edge. TMS and TDI are sampled on the rising edge of TCK by + // Target. + switch (_state) { + case SHIFT_DR: + dr >>= 1; + dr |= (uint64_t) _tdi << (dr_length-1); + break; + case SHIFT_IR: + ir >>= 1; + ir |= _tdi << (ir_length-1); + break; + default: + break; + } + _state = next[_state][_tms]; + + } else { + // Negative clock edge. TDO is updated. + switch (_state) { + case RUN_TEST_IDLE: + if (rti_remaining > 0) + rti_remaining--; + dm->run_test_idle(); + break; + case TEST_LOGIC_RESET: + ir = IR_IDCODE; + break; + case CAPTURE_DR: + capture_dr(); + break; + case SHIFT_DR: + _tdo = dr & 1; + break; + case UPDATE_DR: + update_dr(); + break; + case SHIFT_IR: + _tdo = ir & 1; + break; + default: + break; + } + } + + D(fprintf(stderr, "state=%2d, tdi=%d, tdo=%d, tms=%d, tck=%d, ir=0x%02x, " + "dr=0x%lx\n", + _state, _tdi, _tdo, _tms, _tck, ir, dr)); + + _tck = tck; + _tms = tms; + _tdi = tdi; +} + +void jtag_dtm_t::capture_dr() +{ + switch (ir) { + case IR_IDCODE: + dr = idcode; + dr_length = 32; + break; + case IR_DTMCONTROL: + dr = dtmcontrol; + dr_length = 32; + break; + case IR_DBUS: + if (rti_remaining > 0 || busy_stuck) { + dr = DMI_OP_STATUS_BUSY; + busy_stuck = true; + } else { + dr = dmi; + } + dr_length = abits + 34; + break; + case IR_BYPASS: + dr = bypass; + dr_length = 1; + break; + default: + fprintf(stderr, "Unsupported IR: 0x%x\n", ir); + break; + } + D(fprintf(stderr, "Capture DR; IR=0x%x, DR=0x%lx (%d bits)\n", + ir, dr, dr_length)); +} + +void jtag_dtm_t::update_dr() +{ + D(fprintf(stderr, "Update DR; IR=0x%x, DR=0x%lx (%d bits)\n", + ir, dr, dr_length)); + if (ir == IR_DTMCONTROL) { + if (dr & DTMCONTROL_DMIRESET) + busy_stuck = false; + if (dr & DTMCONTROL_DMIHARDRESET) + reset(); + } else if (ir == IR_BYPASS) { + bypass = dr; + } else if (ir == IR_DBUS && !busy_stuck) { + unsigned op = get_field(dr, DMI_OP); + uint32_t data = get_field(dr, DMI_DATA); + unsigned address = get_field(dr, DMI_ADDRESS); + + dmi = dr; + + bool success = true; + if (op == DMI_OP_READ) { + uint32_t value; + if (dm->dmi_read(address, &value)) { + dmi = set_field(dmi, DMI_DATA, value); + } else { + success = false; + } + } else if (op == DMI_OP_WRITE) { + success = dm->dmi_write(address, data); + } + + if (success) { + dmi = set_field(dmi, DMI_OP, DMI_OP_STATUS_SUCCESS); + } else { + dmi = set_field(dmi, DMI_OP, DMI_OP_STATUS_FAILED); + } + D(fprintf(stderr, "dmi=0x%lx\n", dmi)); + + rti_remaining = required_rti_cycles; + } +} diff --git a/vendor/riscv/riscv-isa-sim/riscv/jtag_dtm.h b/vendor/riscv/riscv-isa-sim/riscv/jtag_dtm.h new file mode 100644 index 0000000000..23a54be1f7 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/jtag_dtm.h @@ -0,0 +1,69 @@ +#ifndef JTAG_DTM_H +#define JTAG_DTM_H + +#include <stdint.h> + +class debug_module_t; + +typedef enum { + TEST_LOGIC_RESET, + RUN_TEST_IDLE, + SELECT_DR_SCAN, + CAPTURE_DR, + SHIFT_DR, + EXIT1_DR, + PAUSE_DR, + EXIT2_DR, + UPDATE_DR, + SELECT_IR_SCAN, + CAPTURE_IR, + SHIFT_IR, + EXIT1_IR, + PAUSE_IR, + EXIT2_IR, + UPDATE_IR +} jtag_state_t; + +class jtag_dtm_t +{ + static const unsigned idcode = 0xdeadbeef; + + public: + jtag_dtm_t(debug_module_t *dm, unsigned required_rti_cycles); + void reset(); + + void set_pins(bool tck, bool tms, bool tdi); + + bool tdo() const { return _tdo; } + + jtag_state_t state() const { return _state; } + + private: + debug_module_t *dm; + // The number of Run-Test/Idle cycles required before a DMI access is + // complete. + unsigned required_rti_cycles; + bool _tck, _tms, _tdi, _tdo; + uint32_t ir; + const unsigned ir_length = 5; + uint64_t dr; + unsigned dr_length; + + // abits must come before dtmcontrol so it can easily be used in the + // constructor. + const unsigned abits = 6; + uint32_t dtmcontrol; + uint64_t dmi; + unsigned bypass; + // Number of Run-Test/Idle cycles needed before we call this access + // complete. + unsigned rti_remaining; + bool busy_stuck; + + jtag_state_t _state; + + void capture_dr(); + void update_dr(); +}; + +#endif diff --git a/vendor/riscv/riscv-isa-sim/riscv/log_file.h b/vendor/riscv/riscv-isa-sim/riscv/log_file.h new file mode 100644 index 0000000000..d039859dc6 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/log_file.h @@ -0,0 +1,37 @@ +// See LICENSE for license details. +#ifndef _RISCV_LOGFILE_H +#define _RISCV_LOGFILE_H + +#include <stdio.h> +#include <memory> +#include <sstream> +#include <stdexcept> + +// Header-only class wrapping a log file. When constructed with an +// actual path, it opens the named file for writing. When constructed +// with the null path, it wraps stderr. +class log_file_t +{ +public: + log_file_t(const char *path) + : wrapped_file (nullptr, &fclose) + { + if (!path) + return; + + wrapped_file.reset(fopen(path, "w")); + if (! wrapped_file) { + std::ostringstream oss; + oss << "Failed to open log file at `" << path << "': " + << strerror (errno); + throw std::runtime_error(oss.str()); + } + } + + FILE *get() { return wrapped_file ? wrapped_file.get() : stderr; } + +private: + std::unique_ptr<FILE, decltype(&fclose)> wrapped_file; +}; + +#endif diff --git a/vendor/riscv/riscv-isa-sim/riscv/memtracer.h b/vendor/riscv/riscv-isa-sim/riscv/memtracer.h new file mode 100644 index 0000000000..72bb3a88b1 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/memtracer.h @@ -0,0 +1,56 @@ +// See LICENSE for license details. + +#ifndef _MEMTRACER_H +#define _MEMTRACER_H + +#include <cstdint> +#include <string.h> +#include <vector> + +enum access_type { + LOAD, + STORE, + FETCH, +}; + +class memtracer_t +{ + public: + memtracer_t() {} + virtual ~memtracer_t() {} + + virtual bool interested_in_range(uint64_t begin, uint64_t end, access_type type) = 0; + virtual void trace(uint64_t addr, size_t bytes, access_type type) = 0; + virtual void clean_invalidate(uint64_t addr, size_t bytes, bool clean, bool inval) = 0; +}; + +class memtracer_list_t : public memtracer_t +{ + public: + bool empty() { return list.empty(); } + bool interested_in_range(uint64_t begin, uint64_t end, access_type type) + { + for (auto it: list) + if (it->interested_in_range(begin, end, type)) + return true; + return false; + } + void trace(uint64_t addr, size_t bytes, access_type type) + { + for (auto it: list) + it->trace(addr, bytes, type); + } + void clean_invalidate(uint64_t addr, size_t bytes, bool clean, bool inval) + { + for (auto it: list) + it->clean_invalidate(addr, bytes, clean, inval); + } + void hook(memtracer_t* h) + { + list.push_back(h); + } + private: + std::vector<memtracer_t*> list; +}; + +#endif diff --git a/vendor/riscv/riscv-isa-sim/riscv/mmio_plugin.h b/vendor/riscv/riscv-isa-sim/riscv/mmio_plugin.h new file mode 100644 index 0000000000..f14470bf38 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/mmio_plugin.h @@ -0,0 +1,91 @@ +#ifndef _RISCV_MMIO_PLUGIN_H +#define _RISCV_MMIO_PLUGIN_H + +#include <stdbool.h> +#include <stddef.h> +#include <stdint.h> + +#ifdef __cplusplus +extern "C" +{ +#endif + +typedef uint64_t reg_t; + +typedef struct { + // Allocate user data for an instance of the plugin. The parameter is a simple + // c-string containing arguments used to construct the plugin. It returns a + // void* to the allocated data. + void* (*alloc)(const char*); + + // Load a memory address of the MMIO plugin. The parameters are the user_data + // (void*), memory offset (reg_t), number of bytes to load (size_t), and the + // buffer into which the loaded data should be written (uint8_t*). Return true + // if the load is successful and false otherwise. + bool (*load)(void*, reg_t, size_t, uint8_t*); + + // Store some bytes to a memory address of the MMIO plugin. The parameters are + // the user_data (void*), memory offset (reg_t), number of bytes to store + // (size_t), and the buffer containing the data to be stored (const uint8_t*). + // Return true if the store is successful and false otherwise. + bool (*store)(void*, reg_t, size_t, const uint8_t*); + + // Deallocate the data allocated during the call to alloc. The parameter is a + // pointer to the user data allocated during the call to alloc. + void (*dealloc)(void*); +} mmio_plugin_t; + +// Register an mmio plugin with the application. This should be called by +// plugins as part of their loading process. +extern void register_mmio_plugin(const char* name_cstr, + const mmio_plugin_t* mmio_plugin); + +#ifdef __cplusplus +} + +#include <string> + +// Wrapper around the C plugin API that makes registering a C++ class with +// correctly formed constructor, load, and store functions easier. The template +// type should be the type that implements the MMIO plugin interface. Simply +// make a global mmio_plugin_registration_t and your plugin should register +// itself with the application when it is loaded because the +// mmio_plugin_registration_t constructor will be called. +template <typename T> +struct mmio_plugin_registration_t +{ + static void* alloc(const char* args) + { + return reinterpret_cast<void*>(new T(std::string(args))); + } + + static bool load(void* self, reg_t addr, size_t len, uint8_t* bytes) + { + return reinterpret_cast<T*>(self)->load(addr, len, bytes); + } + + static bool store(void* self, reg_t addr, size_t len, const uint8_t* bytes) + { + return reinterpret_cast<T*>(self)->store(addr, len, bytes); + } + + static void dealloc(void* self) + { + delete reinterpret_cast<T*>(self); + } + + mmio_plugin_registration_t(const std::string& name) + { + mmio_plugin_t plugin = { + mmio_plugin_registration_t<T>::alloc, + mmio_plugin_registration_t<T>::load, + mmio_plugin_registration_t<T>::store, + mmio_plugin_registration_t<T>::dealloc, + }; + + register_mmio_plugin(name.c_str(), &plugin); + } +}; +#endif // __cplusplus + +#endif diff --git a/vendor/riscv/riscv-isa-sim/riscv/mmu.cc b/vendor/riscv/riscv-isa-sim/riscv/mmu.cc new file mode 100644 index 0000000000..be24f40f0c --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/mmu.cc @@ -0,0 +1,561 @@ +// See LICENSE for license details. + +#include "config.h" +#include "mmu.h" +#include "arith.h" +#include "simif.h" +#include "processor.h" + +mmu_t::mmu_t(simif_t* sim, endianness_t endianness, processor_t* proc) + : sim(sim), proc(proc), +#ifdef RISCV_ENABLE_DUAL_ENDIAN + target_big_endian(endianness == endianness_big), +#endif + check_triggers_fetch(false), + check_triggers_load(false), + check_triggers_store(false), + matched_trigger(NULL) +{ +#ifndef RISCV_ENABLE_DUAL_ENDIAN + assert(endianness == endianness_little); +#endif + flush_tlb(); + yield_load_reservation(); +} + +mmu_t::~mmu_t() +{ +} + +void mmu_t::flush_icache() +{ + for (size_t i = 0; i < ICACHE_ENTRIES; i++) + icache[i].tag = -1; +} + +void mmu_t::flush_tlb() +{ + memset(tlb_insn_tag, -1, sizeof(tlb_insn_tag)); + memset(tlb_load_tag, -1, sizeof(tlb_load_tag)); + memset(tlb_store_tag, -1, sizeof(tlb_store_tag)); + + flush_icache(); +} + +void throw_access_exception(bool virt, reg_t addr, access_type type) +{ + switch (type) { + case FETCH: throw trap_instruction_access_fault(virt, addr, 0, 0); + case LOAD: throw trap_load_access_fault(virt, addr, 0, 0); + case STORE: throw trap_store_access_fault(virt, addr, 0, 0); + default: abort(); + } +} + +reg_t mmu_t::translate(reg_t addr, reg_t len, access_type type, uint32_t xlate_flags) +{ + if (!proc) + return addr; + + bool virt = proc->state.v; + bool hlvx = xlate_flags & RISCV_XLATE_VIRT_HLVX; + reg_t mode = proc->state.prv; + if (type != FETCH) { + if (in_mprv()) { + mode = get_field(proc->state.mstatus->read(), MSTATUS_MPP); + if (get_field(proc->state.mstatus->read(), MSTATUS_MPV) && mode != PRV_M) + virt = true; + } + if (xlate_flags & RISCV_XLATE_VIRT) { + virt = true; + mode = get_field(proc->state.hstatus->read(), HSTATUS_SPVP); + } + } + + reg_t paddr = walk(addr, type, mode, virt, hlvx) | (addr & (PGSIZE-1)); + if (!pmp_ok(paddr, len, type, mode)) + throw_access_exception(virt, addr, type); + return paddr; +} + +tlb_entry_t mmu_t::fetch_slow_path(reg_t vaddr) +{ + check_triggers(triggers::OPERATION_EXECUTE, vaddr); + + tlb_entry_t result; + reg_t vpn = vaddr >> PGSHIFT; + if (unlikely(tlb_insn_tag[vpn % TLB_ENTRIES] != (vpn | TLB_CHECK_TRIGGERS))) { + reg_t paddr = translate(vaddr, sizeof(fetch_temp), FETCH, 0); + if (auto host_addr = sim->addr_to_mem(paddr)) { + result = refill_tlb(vaddr, paddr, host_addr, FETCH); + } else { + if (!mmio_fetch(paddr, sizeof fetch_temp, (uint8_t*)&fetch_temp)) + throw trap_instruction_access_fault(proc->state.v, vaddr, 0, 0); + result = {(char*)&fetch_temp - vaddr, paddr - vaddr}; + } + } else { + result = tlb_data[vpn % TLB_ENTRIES]; + } + + check_triggers(triggers::OPERATION_EXECUTE, vaddr, from_le(*(const uint16_t*)(result.host_offset + vaddr))); + + return result; +} + +reg_t reg_from_bytes(size_t len, const uint8_t* bytes) +{ + switch (len) { + case 1: + return bytes[0]; + case 2: + return bytes[0] | + (((reg_t) bytes[1]) << 8); + case 4: + return bytes[0] | + (((reg_t) bytes[1]) << 8) | + (((reg_t) bytes[2]) << 16) | + (((reg_t) bytes[3]) << 24); + case 8: + return bytes[0] | + (((reg_t) bytes[1]) << 8) | + (((reg_t) bytes[2]) << 16) | + (((reg_t) bytes[3]) << 24) | + (((reg_t) bytes[4]) << 32) | + (((reg_t) bytes[5]) << 40) | + (((reg_t) bytes[6]) << 48) | + (((reg_t) bytes[7]) << 56); + } + abort(); +} + +bool mmu_t::mmio_ok(reg_t paddr, access_type UNUSED type) +{ + // Disallow access to debug region when not in debug mode + if (paddr >= DEBUG_START && paddr <= DEBUG_END && proc && !proc->state.debug_mode) + return false; + + return true; +} + +bool mmu_t::mmio_fetch(reg_t paddr, size_t len, uint8_t* bytes) +{ + if (!mmio_ok(paddr, FETCH)) + return false; + + return sim->mmio_fetch(paddr, len, bytes); +} + +bool mmu_t::mmio_load(reg_t paddr, size_t len, uint8_t* bytes) +{ + return mmio(paddr, len, bytes, LOAD); +} + +bool mmu_t::mmio_store(reg_t paddr, size_t len, const uint8_t* bytes) +{ + return mmio(paddr, len, const_cast<uint8_t*>(bytes), STORE); +} + +bool mmu_t::mmio(reg_t paddr, size_t len, uint8_t* bytes, access_type type) +{ + bool power_of_2 = (len & (len - 1)) == 0; + bool naturally_aligned = (paddr & (len - 1)) == 0; + + if (power_of_2 && naturally_aligned) { + if (!mmio_ok(paddr, type)) + return false; + + if (type == STORE) + return sim->mmio_store(paddr, len, bytes); + else + return sim->mmio_load(paddr, len, bytes); + } + + for (size_t i = 0; i < len; i++) { + if (!mmio(paddr + i, 1, bytes + i, type)) + return false; + } + + return true; +} + +void mmu_t::check_triggers(triggers::operation_t operation, reg_t address, std::optional<reg_t> data) +{ + if (matched_trigger || !proc) + return; + + auto match = proc->TM.detect_memory_access_match(operation, address, data); + + if (match.has_value()) + switch (match->timing) { + case triggers::TIMING_BEFORE: + throw triggers::matched_t(operation, address, match->action); + + case triggers::TIMING_AFTER: + // We want to take this exception on the next instruction. We check + // whether to do so in the I$ refill path, so flush the I$. + flush_icache(); + matched_trigger = new triggers::matched_t(operation, address, match->action); + } +} + +void mmu_t::load_slow_path_intrapage(reg_t addr, reg_t len, uint8_t* bytes, uint32_t xlate_flags) +{ + reg_t vpn = addr >> PGSHIFT; + if (xlate_flags == 0 && vpn == (tlb_load_tag[vpn % TLB_ENTRIES] & ~TLB_CHECK_TRIGGERS)) { + auto host_addr = tlb_data[vpn % TLB_ENTRIES].host_offset + addr; + memcpy(bytes, host_addr, len); + return; + } + + reg_t paddr = translate(addr, len, LOAD, xlate_flags); + + if ((xlate_flags & RISCV_XLATE_LR) && !sim->reservable(paddr)) { + throw trap_load_access_fault((proc) ? proc->state.v : false, addr, 0, 0); + } + + if (auto host_addr = sim->addr_to_mem(paddr)) { + memcpy(bytes, host_addr, len); + if (tracer.interested_in_range(paddr, paddr + PGSIZE, LOAD)) + tracer.trace(paddr, len, LOAD); + else if (xlate_flags == 0) + refill_tlb(addr, paddr, host_addr, LOAD); + + } else if (!mmio_load(paddr, len, bytes)) { + throw trap_load_access_fault((proc) ? proc->state.v : false, addr, 0, 0); + } + + if (xlate_flags & RISCV_XLATE_LR) { + load_reservation_address = paddr; + } +} + +void mmu_t::load_slow_path(reg_t addr, reg_t len, uint8_t* bytes, uint32_t xlate_flags) +{ + check_triggers(triggers::OPERATION_LOAD, addr); + + if ((addr & (len - 1)) == 0) { + load_slow_path_intrapage(addr, len, bytes, xlate_flags); + } else { + bool gva = ((proc) ? proc->state.v : false) || (RISCV_XLATE_VIRT & xlate_flags); + if (!is_misaligned_enabled()) + throw trap_load_address_misaligned(gva, addr, 0, 0); + + if (xlate_flags & RISCV_XLATE_LR) + throw trap_load_access_fault(gva, addr, 0, 0); + + reg_t len_page0 = std::min(len, PGSIZE - addr % PGSIZE); + load_slow_path_intrapage(addr, len_page0, bytes, xlate_flags); + if (len_page0 != len) + load_slow_path_intrapage(addr + len_page0, len - len_page0, bytes + len_page0, xlate_flags); + } + + check_triggers(triggers::OPERATION_LOAD, addr, reg_from_bytes(len, bytes)); +} + +void mmu_t::store_slow_path_intrapage(reg_t addr, reg_t len, const uint8_t* bytes, uint32_t xlate_flags, bool actually_store) +{ + reg_t vpn = addr >> PGSHIFT; + if (xlate_flags == 0 && vpn == (tlb_store_tag[vpn % TLB_ENTRIES] & ~TLB_CHECK_TRIGGERS)) { + if (actually_store) { + auto host_addr = tlb_data[vpn % TLB_ENTRIES].host_offset + addr; + memcpy(host_addr, bytes, len); + } + return; + } + + reg_t paddr = translate(addr, len, STORE, xlate_flags); + + if (actually_store) { + if (auto host_addr = sim->addr_to_mem(paddr)) { + memcpy(host_addr, bytes, len); + if (tracer.interested_in_range(paddr, paddr + PGSIZE, STORE)) + tracer.trace(paddr, len, STORE); + else if (xlate_flags == 0) + refill_tlb(addr, paddr, host_addr, STORE); + } else if (!mmio_store(paddr, len, bytes)) { + throw trap_store_access_fault((proc) ? proc->state.v : false, addr, 0, 0); + } + } +} + +void mmu_t::store_slow_path(reg_t addr, reg_t len, const uint8_t* bytes, uint32_t xlate_flags, bool actually_store, bool UNUSED require_alignment) +{ + if (actually_store) + check_triggers(triggers::OPERATION_STORE, addr, reg_from_bytes(len, bytes)); + + if (addr & (len - 1)) { + bool gva = ((proc) ? proc->state.v : false) || (RISCV_XLATE_VIRT & xlate_flags); + if (!is_misaligned_enabled()) + throw trap_store_address_misaligned(gva, addr, 0, 0); + + if (require_alignment) + throw trap_store_access_fault(gva, addr, 0, 0); + + reg_t len_page0 = std::min(len, PGSIZE - addr % PGSIZE); + store_slow_path_intrapage(addr, len_page0, bytes, xlate_flags, actually_store); + if (len_page0 != len) + store_slow_path_intrapage(addr + len_page0, len - len_page0, bytes + len_page0, xlate_flags, actually_store); + } else { + store_slow_path_intrapage(addr, len, bytes, xlate_flags, actually_store); + } +} + +tlb_entry_t mmu_t::refill_tlb(reg_t vaddr, reg_t paddr, char* host_addr, access_type type) +{ + reg_t idx = (vaddr >> PGSHIFT) % TLB_ENTRIES; + reg_t expected_tag = vaddr >> PGSHIFT; + + tlb_entry_t entry = {host_addr - vaddr, paddr - vaddr}; + + if (in_mprv()) + return entry; + + if ((tlb_load_tag[idx] & ~TLB_CHECK_TRIGGERS) != expected_tag) + tlb_load_tag[idx] = -1; + if ((tlb_store_tag[idx] & ~TLB_CHECK_TRIGGERS) != expected_tag) + tlb_store_tag[idx] = -1; + if ((tlb_insn_tag[idx] & ~TLB_CHECK_TRIGGERS) != expected_tag) + tlb_insn_tag[idx] = -1; + + if ((check_triggers_fetch && type == FETCH) || + (check_triggers_load && type == LOAD) || + (check_triggers_store && type == STORE)) + expected_tag |= TLB_CHECK_TRIGGERS; + + if (pmp_homogeneous(paddr & ~reg_t(PGSIZE - 1), PGSIZE)) { + if (type == FETCH) tlb_insn_tag[idx] = expected_tag; + else if (type == STORE) tlb_store_tag[idx] = expected_tag; + else tlb_load_tag[idx] = expected_tag; + } + + tlb_data[idx] = entry; + return entry; +} + +bool mmu_t::pmp_ok(reg_t addr, reg_t len, access_type type, reg_t mode) +{ + if (!proc || proc->n_pmp == 0) + return true; + + for (size_t i = 0; i < proc->n_pmp; i++) { + // Check each 4-byte sector of the access + bool any_match = false; + bool all_match = true; + for (reg_t offset = 0; offset < len; offset += 1 << PMP_SHIFT) { + reg_t cur_addr = addr + offset; + bool match = proc->state.pmpaddr[i]->match4(cur_addr); + any_match |= match; + all_match &= match; + } + + if (any_match) { + // If the PMP matches only a strict subset of the access, fail it + if (!all_match) + return false; + + return proc->state.pmpaddr[i]->access_ok(type, mode); + } + } + + // in case matching region is not found + const bool mseccfg_mml = proc->state.mseccfg->get_mml(); + const bool mseccfg_mmwp = proc->state.mseccfg->get_mmwp(); + return ((mode == PRV_M) && !mseccfg_mmwp + && (!mseccfg_mml || ((type == LOAD) || (type == STORE)))); +} + +reg_t mmu_t::pmp_homogeneous(reg_t addr, reg_t len) +{ + if ((addr | len) & (len - 1)) + abort(); + + if (!proc) + return true; + + for (size_t i = 0; i < proc->n_pmp; i++) + if (proc->state.pmpaddr[i]->subset_match(addr, len)) + return false; + + return true; +} + +reg_t mmu_t::s2xlate(reg_t gva, reg_t gpa, access_type type, access_type trap_type, bool virt, bool hlvx) +{ + if (!virt) + return gpa; + + vm_info vm = decode_vm_info(proc->get_const_xlen(), true, 0, proc->get_state()->hgatp->read()); + if (vm.levels == 0) + return gpa; + + int maxgpabits = vm.levels * vm.idxbits + vm.widenbits + PGSHIFT; + reg_t maxgpa = (1ULL << maxgpabits) - 1; + + bool mxr = proc->state.sstatus->readvirt(false) & MSTATUS_MXR; + + reg_t base = vm.ptbase; + if ((gpa & ~maxgpa) == 0) { + for (int i = vm.levels - 1; i >= 0; i--) { + int ptshift = i * vm.idxbits; + int idxbits = (i == (vm.levels - 1)) ? vm.idxbits + vm.widenbits : vm.idxbits; + reg_t idx = (gpa >> (PGSHIFT + ptshift)) & ((reg_t(1) << idxbits) - 1); + + // check that physical address of PTE is legal + auto pte_paddr = base + idx * vm.ptesize; + reg_t pte = pte_load(pte_paddr, gva, virt, trap_type, vm.ptesize); + reg_t ppn = (pte & ~reg_t(PTE_ATTR)) >> PTE_PPN_SHIFT; + bool pbmte = proc->get_state()->menvcfg->read() & MENVCFG_PBMTE; + bool hade = proc->get_state()->menvcfg->read() & MENVCFG_HADE; + + if (pte & PTE_RSVD) { + break; + } else if (!proc->extension_enabled(EXT_SVNAPOT) && (pte & PTE_N)) { + break; + } else if (!pbmte && (pte & PTE_PBMT)) { + break; + } else if ((pte & PTE_PBMT) == PTE_PBMT) { + break; + } else if (PTE_TABLE(pte)) { // next level of page table + if (pte & (PTE_D | PTE_A | PTE_U | PTE_N | PTE_PBMT)) + break; + base = ppn << PGSHIFT; + } else if (!(pte & PTE_V) || (!(pte & PTE_R) && (pte & PTE_W))) { + break; + } else if (!(pte & PTE_U)) { + break; + } else if (type == FETCH || hlvx ? !(pte & PTE_X) : + type == LOAD ? !(pte & PTE_R) && !(mxr && (pte & PTE_X)) : + !((pte & PTE_R) && (pte & PTE_W))) { + break; + } else if ((ppn & ((reg_t(1) << ptshift) - 1)) != 0) { + break; + } else { + reg_t ad = PTE_A | ((type == STORE) * PTE_D); + + if ((pte & ad) != ad) { + if (hade) { + // set accessed and possibly dirty bits + pte_store(pte_paddr, pte | ad, gva, virt, type, vm.ptesize); + } else { + // take exception if access or possibly dirty bit is not set. + break; + } + } + + reg_t vpn = gpa >> PGSHIFT; + reg_t page_mask = (reg_t(1) << PGSHIFT) - 1; + + int napot_bits = ((pte & PTE_N) ? (ctz(ppn) + 1) : 0); + if (((pte & PTE_N) && (ppn == 0 || i != 0)) || (napot_bits != 0 && napot_bits != 4)) + break; + + reg_t page_base = ((ppn & ~((reg_t(1) << napot_bits) - 1)) + | (vpn & ((reg_t(1) << napot_bits) - 1)) + | (vpn & ((reg_t(1) << ptshift) - 1))) << PGSHIFT; + return page_base | (gpa & page_mask); + } + } + } + + switch (trap_type) { + case FETCH: throw trap_instruction_guest_page_fault(gva, gpa >> 2, 0); + case LOAD: throw trap_load_guest_page_fault(gva, gpa >> 2, 0); + case STORE: throw trap_store_guest_page_fault(gva, gpa >> 2, 0); + default: abort(); + } +} + +reg_t mmu_t::walk(reg_t addr, access_type type, reg_t mode, bool virt, bool hlvx) +{ + reg_t page_mask = (reg_t(1) << PGSHIFT) - 1; + reg_t satp = proc->get_state()->satp->readvirt(virt); + vm_info vm = decode_vm_info(proc->get_const_xlen(), false, mode, satp); + if (vm.levels == 0) + return s2xlate(addr, addr & ((reg_t(2) << (proc->xlen-1))-1), type, type, virt, hlvx) & ~page_mask; // zero-extend from xlen + + bool s_mode = mode == PRV_S; + bool sum = proc->state.sstatus->readvirt(virt) & MSTATUS_SUM; + bool mxr = (proc->state.sstatus->readvirt(false) | proc->state.sstatus->readvirt(virt)) & MSTATUS_MXR; + + // verify bits xlen-1:va_bits-1 are all equal + int va_bits = PGSHIFT + vm.levels * vm.idxbits; + reg_t mask = (reg_t(1) << (proc->xlen - (va_bits-1))) - 1; + reg_t masked_msbs = (addr >> (va_bits-1)) & mask; + if (masked_msbs != 0 && masked_msbs != mask) + vm.levels = 0; + + reg_t base = vm.ptbase; + for (int i = vm.levels - 1; i >= 0; i--) { + int ptshift = i * vm.idxbits; + reg_t idx = (addr >> (PGSHIFT + ptshift)) & ((1 << vm.idxbits) - 1); + + // check that physical address of PTE is legal + auto pte_paddr = s2xlate(addr, base + idx * vm.ptesize, LOAD, type, virt, false); + reg_t pte = pte_load(pte_paddr, addr, virt, type, vm.ptesize); + reg_t ppn = (pte & ~reg_t(PTE_ATTR)) >> PTE_PPN_SHIFT; + bool pbmte = virt ? (proc->get_state()->henvcfg->read() & HENVCFG_PBMTE) : (proc->get_state()->menvcfg->read() & MENVCFG_PBMTE); + bool hade = virt ? (proc->get_state()->henvcfg->read() & HENVCFG_HADE) : (proc->get_state()->menvcfg->read() & MENVCFG_HADE); + + if (pte & PTE_RSVD) { + break; + } else if (!proc->extension_enabled(EXT_SVNAPOT) && (pte & PTE_N)) { + break; + } else if (!pbmte && (pte & PTE_PBMT)) { + break; + } else if ((pte & PTE_PBMT) == PTE_PBMT) { + break; + } else if (PTE_TABLE(pte)) { // next level of page table + if (pte & (PTE_D | PTE_A | PTE_U | PTE_N | PTE_PBMT)) + break; + base = ppn << PGSHIFT; + } else if ((pte & PTE_U) ? s_mode && (type == FETCH || !sum) : !s_mode) { + break; + } else if (!(pte & PTE_V) || (!(pte & PTE_R) && (pte & PTE_W))) { + break; + } else if (type == FETCH || hlvx ? !(pte & PTE_X) : + type == LOAD ? !(pte & PTE_R) && !(mxr && (pte & PTE_X)) : + !((pte & PTE_R) && (pte & PTE_W))) { + break; + } else if ((ppn & ((reg_t(1) << ptshift) - 1)) != 0) { + break; + } else { + reg_t ad = PTE_A | ((type == STORE) * PTE_D); + + if ((pte & ad) != ad) { + if (hade) { + // set accessed and possibly dirty bits. + pte_store(pte_paddr, pte | ad, addr, virt, type, vm.ptesize); + } else { + // take exception if access or possibly dirty bit is not set. + break; + } + } + + // for superpage or Svnapot NAPOT mappings, make a fake leaf PTE for the TLB's benefit. + reg_t vpn = addr >> PGSHIFT; + + int napot_bits = ((pte & PTE_N) ? (ctz(ppn) + 1) : 0); + if (((pte & PTE_N) && (ppn == 0 || i != 0)) || (napot_bits != 0 && napot_bits != 4)) + break; + + reg_t page_base = ((ppn & ~((reg_t(1) << napot_bits) - 1)) + | (vpn & ((reg_t(1) << napot_bits) - 1)) + | (vpn & ((reg_t(1) << ptshift) - 1))) << PGSHIFT; + reg_t phys = page_base | (addr & page_mask); + return s2xlate(addr, phys, type, type, virt, hlvx) & ~page_mask; + } + } + + switch (type) { + case FETCH: throw trap_instruction_page_fault(virt, addr, 0, 0); + case LOAD: throw trap_load_page_fault(virt, addr, 0, 0); + case STORE: throw trap_store_page_fault(virt, addr, 0, 0); + default: abort(); + } +} + +void mmu_t::register_memtracer(memtracer_t* t) +{ + flush_tlb(); + tracer.hook(t); +} diff --git a/vendor/riscv/riscv-isa-sim/riscv/mmu.h b/vendor/riscv/riscv-isa-sim/riscv/mmu.h new file mode 100644 index 0000000000..ef054cf59c --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/mmu.h @@ -0,0 +1,477 @@ +// See LICENSE for license details. + +#ifndef _RISCV_MMU_H +#define _RISCV_MMU_H + +#include "decode.h" +#include "trap.h" +#include "common.h" +#include "simif.h" +#include "processor.h" +#include "memtracer.h" +#include "../fesvr/byteorder.h" +#include "triggers.h" +#include "cfg.h" +#include <stdlib.h> +#include <vector> + +// virtual memory configuration +#define PGSHIFT 12 +const reg_t PGSIZE = 1 << PGSHIFT; +const reg_t PGMASK = ~(PGSIZE-1); +#define MAX_PADDR_BITS 56 // imposed by Sv39 / Sv48 + +struct insn_fetch_t +{ + insn_func_t func; + insn_t insn; +}; + +struct icache_entry_t { + reg_t tag; + struct icache_entry_t* next; + insn_fetch_t data; +}; + +struct tlb_entry_t { + char* host_offset; + reg_t target_offset; +}; + +void throw_access_exception(bool virt, reg_t addr, access_type type); + +// this class implements a processor's port into the virtual memory system. +// an MMU and instruction cache are maintained for simulator performance. +class mmu_t +{ +private: + std::map<reg_t, reg_t> alloc_cache; + std::vector<std::pair<reg_t, reg_t >> addr_tbl; +public: + mmu_t(simif_t* sim, endianness_t endianness, processor_t* proc); + ~mmu_t(); + +#define RISCV_XLATE_VIRT (1U << 0) +#define RISCV_XLATE_VIRT_HLVX (1U << 1) +#define RISCV_XLATE_LR (1U << 2) + + template<typename T> + T ALWAYS_INLINE load(reg_t addr, uint32_t xlate_flags = 0) { + target_endian<T> res; + reg_t vpn = addr >> PGSHIFT; + bool aligned = (addr & (sizeof(T) - 1)) == 0; + bool tlb_hit = tlb_load_tag[vpn % TLB_ENTRIES] == vpn; + + if (likely(xlate_flags == 0 && aligned && tlb_hit)) { + res = *(target_endian<T>*)(tlb_data[vpn % TLB_ENTRIES].host_offset + addr); + } else { + load_slow_path(addr, sizeof(T), (uint8_t*)&res, xlate_flags); + } + + if (unlikely(proc && proc->get_log_commits_enabled())) + proc->state.log_mem_read.push_back(std::make_tuple(addr, 0, sizeof(T))); + + return from_target(res); + } + + template<typename T> + T load_reserved(reg_t addr) { + return load<T>(addr, RISCV_XLATE_LR); + } + + template<typename T> + T guest_load(reg_t addr) { + return load<T>(addr, RISCV_XLATE_VIRT); + } + + template<typename T> + T guest_load_x(reg_t addr) { + return load<T>(addr, RISCV_XLATE_VIRT|RISCV_XLATE_VIRT_HLVX); + } + + template<typename T> + void ALWAYS_INLINE store(reg_t addr, T val, uint32_t xlate_flags = 0) { + reg_t vpn = addr >> PGSHIFT; + bool aligned = (addr & (sizeof(T) - 1)) == 0; + bool tlb_hit = tlb_store_tag[vpn % TLB_ENTRIES] == vpn; + + if (xlate_flags == 0 && likely(aligned && tlb_hit)) { + *(target_endian<T>*)(tlb_data[vpn % TLB_ENTRIES].host_offset + addr) = to_target(val); + } else { + target_endian<T> target_val = to_target(val); + store_slow_path(addr, sizeof(T), (const uint8_t*)&target_val, xlate_flags, true, false); + } + + if (unlikely(proc && proc->get_log_commits_enabled())) + proc->state.log_mem_write.push_back(std::make_tuple(addr, val, sizeof(T))); + } + + template<typename T> + void guest_store(reg_t addr, T val) { + store(addr, val, RISCV_XLATE_VIRT); + } + + // AMO/Zicbom faults should be reported as store faults + #define convert_load_traps_to_store_traps(BODY) \ + try { \ + BODY \ + } catch (trap_load_address_misaligned& t) { \ + /* Misaligned fault will not be triggered by Zicbom */ \ + throw trap_store_address_misaligned(t.has_gva(), t.get_tval(), t.get_tval2(), t.get_tinst()); \ + } catch (trap_load_page_fault& t) { \ + throw trap_store_page_fault(t.has_gva(), t.get_tval(), t.get_tval2(), t.get_tinst()); \ + } catch (trap_load_access_fault& t) { \ + throw trap_store_access_fault(t.has_gva(), t.get_tval(), t.get_tval2(), t.get_tinst()); \ + } catch (trap_load_guest_page_fault& t) { \ + throw trap_store_guest_page_fault(t.get_tval(), t.get_tval2(), t.get_tinst()); \ + } + + // template for functions that perform an atomic memory operation + template<typename T, typename op> + T amo(reg_t addr, op f) { + convert_load_traps_to_store_traps({ + store_slow_path(addr, sizeof(T), nullptr, 0, false, true); + auto lhs = load<T>(addr); + store<T>(addr, f(lhs)); + return lhs; + }) + } + + void store_float128(reg_t addr, float128_t val) + { + if (unlikely(addr & (sizeof(float128_t)-1)) && !is_misaligned_enabled()) { + throw trap_store_address_misaligned((proc) ? proc->state.v : false, addr, 0, 0); + } + + store<uint64_t>(addr, val.v[0]); + store<uint64_t>(addr + 8, val.v[1]); + } + + float128_t load_float128(reg_t addr) + { + if (unlikely(addr & (sizeof(float128_t)-1)) && !is_misaligned_enabled()) { + throw trap_load_address_misaligned((proc) ? proc->state.v : false, addr, 0, 0); + } + + return (float128_t){load<uint64_t>(addr), load<uint64_t>(addr + 8)}; + } + + void cbo_zero(reg_t addr) { + auto base = addr & ~(blocksz - 1); + for (size_t offset = 0; offset < blocksz; offset += 1) + store<uint8_t>(base + offset, 0); + } + + void clean_inval(reg_t addr, bool clean, bool inval) { + convert_load_traps_to_store_traps({ + const reg_t paddr = translate(addr, blocksz, LOAD, 0) & ~(blocksz - 1); + if (sim->reservable(paddr)) { + if (tracer.interested_in_range(paddr, paddr + PGSIZE, LOAD)) + tracer.clean_invalidate(paddr, blocksz, clean, inval); + } else { + throw trap_store_access_fault((proc) ? proc->state.v : false, addr, 0, 0); + } + }) + } + + inline void yield_load_reservation() + { + load_reservation_address = (reg_t)-1; + } + + inline bool check_load_reservation(reg_t vaddr, size_t size) + { + if (vaddr & (size-1)) { + // Raise either access fault or misaligned exception + store_slow_path(vaddr, size, nullptr, 0, false, true); + } + + reg_t paddr = translate(vaddr, 1, STORE, 0); + if (sim->reservable(paddr)) + return load_reservation_address == paddr; + else + throw trap_store_access_fault((proc) ? proc->state.v : false, vaddr, 0, 0); + } + + template<typename T> + bool store_conditional(reg_t addr, T val) + { + bool have_reservation = check_load_reservation(addr, sizeof(T)); + + if (have_reservation) + store(addr, val); + + yield_load_reservation(); + + return have_reservation; + } + + static const reg_t ICACHE_ENTRIES = 1024; + + inline size_t icache_index(reg_t addr) + { + return (addr / PC_ALIGN) % ICACHE_ENTRIES; + } + + template<typename T> + T ALWAYS_INLINE fetch_jump_table(reg_t addr) { + auto tlb_entry = translate_insn_addr(addr); + return from_target(*(target_endian<T>*)(tlb_entry.host_offset + addr)); + } + + inline icache_entry_t* refill_icache(reg_t addr, icache_entry_t* entry) + { + if (matched_trigger) + throw *matched_trigger; + + auto tlb_entry = translate_insn_addr(addr); + insn_bits_t insn = from_le(*(uint16_t*)(tlb_entry.host_offset + addr)); + int length = insn_length(insn); + + if (likely(length == 4)) { + insn |= (insn_bits_t)from_le(*(const uint16_t*)translate_insn_addr_to_host(addr + 2)) << 16; + } else if (length == 2) { + // entire instruction already fetched + } else if (length == 6) { + insn |= (insn_bits_t)from_le(*(const uint16_t*)translate_insn_addr_to_host(addr + 4)) << 32; + insn |= (insn_bits_t)from_le(*(const uint16_t*)translate_insn_addr_to_host(addr + 2)) << 16; + } else { + static_assert(sizeof(insn_bits_t) == 8, "insn_bits_t must be uint64_t"); + insn |= (insn_bits_t)from_le(*(const uint16_t*)translate_insn_addr_to_host(addr + 6)) << 48; + insn |= (insn_bits_t)from_le(*(const uint16_t*)translate_insn_addr_to_host(addr + 4)) << 32; + insn |= (insn_bits_t)from_le(*(const uint16_t*)translate_insn_addr_to_host(addr + 2)) << 16; + } + + insn_fetch_t fetch = {proc->decode_insn(insn), insn}; + entry->tag = addr; + entry->next = &icache[icache_index(addr + length)]; + entry->data = fetch; + + reg_t paddr = tlb_entry.target_offset + addr;; + if (tracer.interested_in_range(paddr, paddr + 1, FETCH)) { + entry->tag = -1; + tracer.trace(paddr, length, FETCH); + } + return entry; + } + + inline icache_entry_t* access_icache(reg_t addr) + { + icache_entry_t* entry = &icache[icache_index(addr)]; + if (likely(entry->tag == addr)) + return entry; + return refill_icache(addr, entry); + } + + inline insn_fetch_t load_insn(reg_t addr) + { + icache_entry_t entry; + return refill_icache(addr, &entry)->data; + } + + void flush_tlb(); + void flush_icache(); + + void register_memtracer(memtracer_t*); + + int is_misaligned_enabled() + { + return proc && proc->get_cfg().misaligned; + } + + bool is_target_big_endian() + { + return target_big_endian; + } + + template<typename T> inline T from_target(target_endian<T> n) const + { + return target_big_endian? n.from_be() : n.from_le(); + } + + template<typename T> inline target_endian<T> to_target(T n) const + { + return target_big_endian? target_endian<T>::to_be(n) : target_endian<T>::to_le(n); + } + + void set_cache_blocksz(reg_t size) + { + blocksz = size; + } + +private: + simif_t* sim; + processor_t* proc; + memtracer_list_t tracer; + reg_t load_reservation_address; + uint16_t fetch_temp; + reg_t blocksz; + + // implement an instruction cache for simulator performance + icache_entry_t icache[ICACHE_ENTRIES]; + + // implement a TLB for simulator performance + static const reg_t TLB_ENTRIES = 256; + // If a TLB tag has TLB_CHECK_TRIGGERS set, then the MMU must check for a + // trigger match before completing an access. + static const reg_t TLB_CHECK_TRIGGERS = reg_t(1) << 63; + tlb_entry_t tlb_data[TLB_ENTRIES]; + reg_t tlb_insn_tag[TLB_ENTRIES]; + reg_t tlb_load_tag[TLB_ENTRIES]; + reg_t tlb_store_tag[TLB_ENTRIES]; + + // finish translation on a TLB miss and update the TLB + tlb_entry_t refill_tlb(reg_t vaddr, reg_t paddr, char* host_addr, access_type type); + const char* fill_from_mmio(reg_t vaddr, reg_t paddr); + + // perform a stage2 translation for a given guest address + reg_t s2xlate(reg_t gva, reg_t gpa, access_type type, access_type trap_type, bool virt, bool hlvx); + + // perform a page table walk for a given VA; set referenced/dirty bits + reg_t walk(reg_t addr, access_type type, reg_t prv, bool virt, bool hlvx); + + // handle uncommon cases: TLB misses, page faults, MMIO + tlb_entry_t fetch_slow_path(reg_t addr); + void load_slow_path(reg_t addr, reg_t len, uint8_t* bytes, uint32_t xlate_flags); + void load_slow_path_intrapage(reg_t addr, reg_t len, uint8_t* bytes, uint32_t xlate_flags); + void store_slow_path(reg_t addr, reg_t len, const uint8_t* bytes, uint32_t xlate_flags, bool actually_store, bool require_alignment); + void store_slow_path_intrapage(reg_t addr, reg_t len, const uint8_t* bytes, uint32_t xlate_flags, bool actually_store); + bool mmio_fetch(reg_t paddr, size_t len, uint8_t* bytes); + bool mmio_load(reg_t paddr, size_t len, uint8_t* bytes); + bool mmio_store(reg_t paddr, size_t len, const uint8_t* bytes); + bool mmio(reg_t paddr, size_t len, uint8_t* bytes, access_type type); + bool mmio_ok(reg_t paddr, access_type type); + void check_triggers(triggers::operation_t operation, reg_t address, std::optional<reg_t> data = std::nullopt); + reg_t translate(reg_t addr, reg_t len, access_type type, uint32_t xlate_flags); + + reg_t pte_load(reg_t pte_paddr, reg_t addr, bool virt, access_type trap_type, size_t ptesize) { + if (ptesize == 4) + return pte_load<uint32_t>(pte_paddr, addr, virt, trap_type); + else + return pte_load<uint64_t>(pte_paddr, addr, virt, trap_type); + } + + void pte_store(reg_t pte_paddr, reg_t new_pte, reg_t addr, bool virt, access_type trap_type, size_t ptesize) { + if (ptesize == 4) + return pte_store<uint32_t>(pte_paddr, new_pte, addr, virt, trap_type); + else + return pte_store<uint64_t>(pte_paddr, new_pte, addr, virt, trap_type); + } + + template<typename T> inline reg_t pte_load(reg_t pte_paddr, reg_t addr, bool virt, access_type trap_type) + { + const size_t ptesize = sizeof(T); + + if (!pmp_ok(pte_paddr, ptesize, LOAD, PRV_S)) + throw_access_exception(virt, addr, trap_type); + + void* host_pte_addr = sim->addr_to_mem(pte_paddr); + target_endian<T> target_pte; + if (host_pte_addr) { + memcpy(&target_pte, host_pte_addr, ptesize); + } else if (!mmio_load(pte_paddr, ptesize, (uint8_t*)&target_pte)) { + throw_access_exception(virt, addr, trap_type); + } + return from_target(target_pte); + } + + template<typename T> inline void pte_store(reg_t pte_paddr, reg_t new_pte, reg_t addr, bool virt, access_type trap_type) + { + const size_t ptesize = sizeof(T); + + if (!pmp_ok(pte_paddr, ptesize, STORE, PRV_S)) + throw_access_exception(virt, addr, trap_type); + + void* host_pte_addr = sim->addr_to_mem(pte_paddr); + target_endian<T> target_pte = to_target((T)new_pte); + if (host_pte_addr) { + memcpy(host_pte_addr, &target_pte, ptesize); + } else if (!mmio_store(pte_paddr, ptesize, (uint8_t*)&target_pte)) { + throw_access_exception(virt, addr, trap_type); + } + } + + // ITLB lookup + inline tlb_entry_t translate_insn_addr(reg_t addr) { + reg_t vpn = addr >> PGSHIFT; + if (likely(tlb_insn_tag[vpn % TLB_ENTRIES] == vpn)) + return tlb_data[vpn % TLB_ENTRIES]; + return fetch_slow_path(addr); + } + + inline const uint16_t* translate_insn_addr_to_host(reg_t addr) { + return (uint16_t*)(translate_insn_addr(addr).host_offset + addr); + } + + inline bool in_mprv() + { + return proc != nullptr + && !(proc->state.mnstatus && !get_field(proc->state.mnstatus->read(), MNSTATUS_NMIE)) + && !proc->state.debug_mode + && get_field(proc->state.mstatus->read(), MSTATUS_MPRV); + } + + reg_t pmp_homogeneous(reg_t addr, reg_t len); + bool pmp_ok(reg_t addr, reg_t len, access_type type, reg_t mode); + +#ifdef RISCV_ENABLE_DUAL_ENDIAN + bool target_big_endian; +#else + static const bool target_big_endian = false; +#endif + bool check_triggers_fetch; + bool check_triggers_load; + bool check_triggers_store; + // The exception describing a matched trigger, or NULL. + triggers::matched_t *matched_trigger; + + friend class processor_t; +}; + +struct vm_info { + int levels; + int idxbits; + int widenbits; + int ptesize; + reg_t ptbase; +}; + +inline vm_info decode_vm_info(int xlen, bool stage2, reg_t prv, reg_t satp) +{ + if (prv == PRV_M) { + return {0, 0, 0, 0, 0}; + } else if (!stage2 && prv <= PRV_S && xlen == 32) { + switch (get_field(satp, SATP32_MODE)) { + case SATP_MODE_OFF: return {0, 0, 0, 0, 0}; + case SATP_MODE_SV32: return {2, 10, 0, 4, (satp & SATP32_PPN) << PGSHIFT}; + default: abort(); + } + } else if (!stage2 && prv <= PRV_S && xlen == 64) { + switch (get_field(satp, SATP64_MODE)) { + case SATP_MODE_OFF: return {0, 0, 0, 0, 0}; + case SATP_MODE_SV39: return {3, 9, 0, 8, (satp & SATP64_PPN) << PGSHIFT}; + case SATP_MODE_SV48: return {4, 9, 0, 8, (satp & SATP64_PPN) << PGSHIFT}; + case SATP_MODE_SV57: return {5, 9, 0, 8, (satp & SATP64_PPN) << PGSHIFT}; + case SATP_MODE_SV64: return {6, 9, 0, 8, (satp & SATP64_PPN) << PGSHIFT}; + default: abort(); + } + } else if (stage2 && xlen == 32) { + switch (get_field(satp, HGATP32_MODE)) { + case HGATP_MODE_OFF: return {0, 0, 0, 0, 0}; + case HGATP_MODE_SV32X4: return {2, 10, 2, 4, (satp & HGATP32_PPN) << PGSHIFT}; + default: abort(); + } + } else if (stage2 && xlen == 64) { + switch (get_field(satp, HGATP64_MODE)) { + case HGATP_MODE_OFF: return {0, 0, 0, 0, 0}; + case HGATP_MODE_SV39X4: return {3, 9, 2, 8, (satp & HGATP64_PPN) << PGSHIFT}; + case HGATP_MODE_SV48X4: return {4, 9, 2, 8, (satp & HGATP64_PPN) << PGSHIFT}; + case HGATP_MODE_SV57X4: return {5, 9, 2, 8, (satp & HGATP64_PPN) << PGSHIFT}; + default: abort(); + } + } else { + abort(); + } +} + +#endif diff --git a/vendor/riscv/riscv-isa-sim/riscv/ns16550.cc b/vendor/riscv/riscv-isa-sim/riscv/ns16550.cc new file mode 100644 index 0000000000..8d7e4de2d7 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/ns16550.cc @@ -0,0 +1,319 @@ +#include <sys/time.h> +#include "devices.h" +#include "processor.h" +#include "term.h" + +#define UART_QUEUE_SIZE 64 + +#define UART_RX 0 /* In: Receive buffer */ +#define UART_TX 0 /* Out: Transmit buffer */ + +#define UART_IER 1 /* Out: Interrupt Enable Register */ +#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ +#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ +#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ +#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ + +#define UART_IIR 2 /* In: Interrupt ID Register */ +#define UART_IIR_NO_INT 0x01 /* No interrupts pending */ +#define UART_IIR_ID 0x0e /* Mask for the interrupt ID */ +#define UART_IIR_MSI 0x00 /* Modem status interrupt */ +#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ +#define UART_IIR_RDI 0x04 /* Receiver data interrupt */ +#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ + +#define UART_IIR_TYPE_BITS 0xc0 + +#define UART_FCR 2 /* Out: FIFO Control Register */ +#define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */ +#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ +#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ +#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */ + +#define UART_LCR 3 /* Out: Line Control Register */ +#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ +#define UART_LCR_SBC 0x40 /* Set break control */ +#define UART_LCR_SPAR 0x20 /* Stick parity (?) */ +#define UART_LCR_EPAR 0x10 /* Even parity select */ +#define UART_LCR_PARITY 0x08 /* Parity Enable */ +#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 bit, 1=2 bits */ + +#define UART_MCR 4 /* Out: Modem Control Register */ +#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ +#define UART_MCR_OUT2 0x08 /* Out2 complement */ +#define UART_MCR_OUT1 0x04 /* Out1 complement */ +#define UART_MCR_RTS 0x02 /* RTS complement */ +#define UART_MCR_DTR 0x01 /* DTR complement */ + +#define UART_LSR 5 /* In: Line Status Register */ +#define UART_LSR_FIFOE 0x80 /* Fifo error */ +#define UART_LSR_TEMT 0x40 /* Transmitter empty */ +#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ +#define UART_LSR_BI 0x10 /* Break interrupt indicator */ +#define UART_LSR_FE 0x08 /* Frame error indicator */ +#define UART_LSR_PE 0x04 /* Parity error indicator */ +#define UART_LSR_OE 0x02 /* Overrun error indicator */ +#define UART_LSR_DR 0x01 /* Receiver data ready */ +#define UART_LSR_BRK_ERROR_BITS 0x1E /* BI, FE, PE, OE bits */ + +#define UART_MSR 6 /* In: Modem Status Register */ +#define UART_MSR_DCD 0x80 /* Data Carrier Detect */ +#define UART_MSR_RI 0x40 /* Ring Indicator */ +#define UART_MSR_DSR 0x20 /* Data Set Ready */ +#define UART_MSR_CTS 0x10 /* Clear to Send */ +#define UART_MSR_DDCD 0x08 /* Delta DCD */ +#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ +#define UART_MSR_DDSR 0x02 /* Delta DSR */ +#define UART_MSR_DCTS 0x01 /* Delta CTS */ +#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ + +#define UART_SCR 7 /* I/O: Scratch Register */ + +ns16550_t::ns16550_t(class bus_t *bus, abstract_interrupt_controller_t *intctrl, + uint32_t interrupt_id, uint32_t reg_shift, uint32_t reg_io_width) + : bus(bus), intctrl(intctrl), interrupt_id(interrupt_id), reg_shift(reg_shift), reg_io_width(reg_io_width), backoff_counter(0) +{ + ier = 0; + iir = UART_IIR_NO_INT; + fcr = 0; + lcr = 0; + lsr = UART_LSR_TEMT | UART_LSR_THRE; + msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS; + dll = 0x0C; + mcr = UART_MCR_OUT2; + scr = 0; +} + +void ns16550_t::update_interrupt(void) +{ + uint8_t interrupts = 0; + + /* Handle clear rx */ + if (lcr & UART_FCR_CLEAR_RCVR) { + lcr &= ~UART_FCR_CLEAR_RCVR; + while (!rx_queue.empty()) { + rx_queue.pop(); + } + lsr &= ~UART_LSR_DR; + } + + /* Handle clear tx */ + if (lcr & UART_FCR_CLEAR_XMIT) { + lcr &= ~UART_FCR_CLEAR_XMIT; + lsr |= UART_LSR_TEMT | UART_LSR_THRE; + } + + /* Data ready and rcv interrupt enabled ? */ + if ((ier & UART_IER_RDI) && (lsr & UART_LSR_DR)) { + interrupts |= UART_IIR_RDI; + } + + /* Transmitter empty and interrupt enabled ? */ + if ((ier & UART_IER_THRI) && (lsr & UART_LSR_TEMT)) { + interrupts |= UART_IIR_THRI; + } + + /* Now update the interrup line, if necessary */ + if (!interrupts) { + iir = UART_IIR_NO_INT; + intctrl->set_interrupt_level(interrupt_id, 0); + } else { + iir = interrupts; + intctrl->set_interrupt_level(interrupt_id, 1); + } + + /* + * If the OS disabled the tx interrupt, we know that there is nothing + * more to transmit. + */ + if (!(ier & UART_IER_THRI)) { + lsr |= UART_LSR_TEMT | UART_LSR_THRE; + } +} + +uint8_t ns16550_t::rx_byte(void) +{ + if (rx_queue.empty()) { + lsr &= ~UART_LSR_DR; + return 0; + } + + /* Break issued ? */ + if (lsr & UART_LSR_BI) { + lsr &= ~UART_LSR_BI; + return 0; + } + + uint8_t ret = rx_queue.front(); + rx_queue.pop(); + if (rx_queue.empty()) { + lsr &= ~UART_LSR_DR; + } + + return ret; +} + +void ns16550_t::tx_byte(uint8_t val) +{ + lsr |= UART_LSR_TEMT | UART_LSR_THRE; + canonical_terminal_t::write(val); +} + +bool ns16550_t::load(reg_t addr, size_t len, uint8_t* bytes) +{ + uint8_t val; + bool ret = true, update = false; + + if (reg_io_width != len) { + return false; + } + addr >>= reg_shift; + addr &= 7; + + switch (addr) { + case UART_RX: + if (lcr & UART_LCR_DLAB) { + val = dll; + } else { + val = rx_byte(); + } + update = true; + break; + case UART_IER: + if (lcr & UART_LCR_DLAB) { + val = dlm; + } else { + val = ier; + } + break; + case UART_IIR: + val = iir | UART_IIR_TYPE_BITS; + break; + case UART_LCR: + val = lcr; + break; + case UART_MCR: + val = mcr; + break; + case UART_LSR: + val = lsr; + break; + case UART_MSR: + val = msr; + break; + case UART_SCR: + val = scr; + break; + default: + ret = false; + break; + }; + + if (ret) { + bytes[0] = val; + } + if (update) { + update_interrupt(); + } + + return ret; +} + +bool ns16550_t::store(reg_t addr, size_t len, const uint8_t* bytes) +{ + uint8_t val; + bool ret = true, update = false; + + if (reg_io_width != len) { + return false; + } + addr >>= reg_shift; + addr &= 7; + val = bytes[0]; + + switch (addr) { + case UART_TX: + update = true; + + if (lcr & UART_LCR_DLAB) { + dll = val; + break; + } + + /* Loopback mode */ + if (mcr & UART_MCR_LOOP) { + if (rx_queue.size() < UART_QUEUE_SIZE) { + rx_queue.push(val); + lsr |= UART_LSR_DR; + } + break; + } + + tx_byte(val); + break; + case UART_IER: + if (!(lcr & UART_LCR_DLAB)) { + ier = val & 0x0f; + } else { + dlm = val; + } + update = true; + break; + case UART_FCR: + fcr = val; + update = true; + break; + case UART_LCR: + lcr = val; + update = true; + break; + case UART_MCR: + mcr = val; + update = true; + break; + case UART_LSR: + /* Factory test */ + break; + case UART_MSR: + /* Not used */ + break; + case UART_SCR: + scr = val; + break; + default: + ret = false; + break; + }; + + if (update) { + update_interrupt(); + } + + return ret; +} + +void ns16550_t::tick(void) +{ + if (!(fcr & UART_FCR_ENABLE_FIFO) || + (mcr & UART_MCR_LOOP) || + (UART_QUEUE_SIZE <= rx_queue.size())) { + return; + } + + if (backoff_counter > 0 && backoff_counter < MAX_BACKOFF) { + backoff_counter++; + return; + } + + int rc = canonical_terminal_t::read(); + if (rc < 0) { + backoff_counter = 1; + return; + } + + backoff_counter = 0; + + rx_queue.push((uint8_t)rc); + lsr |= UART_LSR_DR; + update_interrupt(); +} diff --git a/vendor/riscv/riscv-isa-sim/riscv/opcodes.h b/vendor/riscv/riscv-isa-sim/riscv/opcodes.h new file mode 100644 index 0000000000..065934a238 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/opcodes.h @@ -0,0 +1,249 @@ +#include "encoding.h" + +#define ZERO 0 +#define T0 5 +#define S0 8 +#define S1 9 + +static uint32_t bits(uint32_t value, unsigned int hi, unsigned int lo) { + return (value >> lo) & ((1 << (hi+1-lo)) - 1); +} + +static uint32_t bit(uint32_t value, unsigned int b) { + return (value >> b) & 1; +} + +static uint32_t jal(unsigned int rd, uint32_t imm) __attribute__ ((unused)); +static uint32_t jal(unsigned int rd, uint32_t imm) { + return (bit(imm, 20) << 31) | + (bits(imm, 10, 1) << 21) | + (bit(imm, 11) << 20) | + (bits(imm, 19, 12) << 12) | + (rd << 7) | + MATCH_JAL; +} + +static uint32_t csrsi(unsigned int csr, uint16_t imm) __attribute__ ((unused)); +static uint32_t csrsi(unsigned int csr, uint16_t imm) { + return (csr << 20) | + (bits(imm, 4, 0) << 15) | + MATCH_CSRRSI; +} + +static uint32_t sw(unsigned int src, unsigned int base, uint16_t offset) __attribute__ ((unused)); +static uint32_t sw(unsigned int src, unsigned int base, uint16_t offset) +{ + return (bits(offset, 11, 5) << 25) | + (src << 20) | + (base << 15) | + (bits(offset, 4, 0) << 7) | + MATCH_SW; +} + +static uint32_t sd(unsigned int src, unsigned int base, uint16_t offset) __attribute__ ((unused)); +static uint32_t sd(unsigned int src, unsigned int base, uint16_t offset) +{ + return (bits(offset, 11, 5) << 25) | + (src << 20) | + (base << 15) | + (bits(offset, 4, 0) << 7) | + MATCH_SD; +} + +static uint32_t sh(unsigned int src, unsigned int base, uint16_t offset) __attribute__ ((unused)); +static uint32_t sh(unsigned int src, unsigned int base, uint16_t offset) +{ + return (bits(offset, 11, 5) << 25) | + (src << 20) | + (base << 15) | + (bits(offset, 4, 0) << 7) | + MATCH_SH; +} + +static uint32_t sb(unsigned int src, unsigned int base, uint16_t offset) __attribute__ ((unused)); +static uint32_t sb(unsigned int src, unsigned int base, uint16_t offset) +{ + return (bits(offset, 11, 5) << 25) | + (src << 20) | + (base << 15) | + (bits(offset, 4, 0) << 7) | + MATCH_SB; +} + +static uint32_t ld(unsigned int rd, unsigned int base, uint16_t offset) __attribute__ ((unused)); +static uint32_t ld(unsigned int rd, unsigned int base, uint16_t offset) +{ + return (bits(offset, 11, 0) << 20) | + (base << 15) | + (bits(rd, 4, 0) << 7) | + MATCH_LD; +} + +static uint32_t lw(unsigned int rd, unsigned int base, uint16_t offset) __attribute__ ((unused)); +static uint32_t lw(unsigned int rd, unsigned int base, uint16_t offset) +{ + return (bits(offset, 11, 0) << 20) | + (base << 15) | + (bits(rd, 4, 0) << 7) | + MATCH_LW; +} + +static uint32_t lh(unsigned int rd, unsigned int base, uint16_t offset) __attribute__ ((unused)); +static uint32_t lh(unsigned int rd, unsigned int base, uint16_t offset) +{ + return (bits(offset, 11, 0) << 20) | + (base << 15) | + (bits(rd, 4, 0) << 7) | + MATCH_LH; +} + +static uint32_t lb(unsigned int rd, unsigned int base, uint16_t offset) __attribute__ ((unused)); +static uint32_t lb(unsigned int rd, unsigned int base, uint16_t offset) +{ + return (bits(offset, 11, 0) << 20) | + (base << 15) | + (bits(rd, 4, 0) << 7) | + MATCH_LB; +} + +static uint32_t csrw(unsigned int source, unsigned int csr) __attribute__ ((unused)); +static uint32_t csrw(unsigned int source, unsigned int csr) { + return (csr << 20) | (source << 15) | MATCH_CSRRW; +} + +static uint32_t addi(unsigned int dest, unsigned int src, uint16_t imm) __attribute__ ((unused)); +static uint32_t addi(unsigned int dest, unsigned int src, uint16_t imm) +{ + return (bits(imm, 11, 0) << 20) | + (src << 15) | + (dest << 7) | + MATCH_ADDI; +} + +static uint32_t csrr(unsigned int rd, unsigned int csr) __attribute__ ((unused)); +static uint32_t csrr(unsigned int rd, unsigned int csr) { + return (csr << 20) | (rd << 7) | MATCH_CSRRS; +} + +static uint32_t csrrs(unsigned int rd, unsigned int rs1, unsigned int csr) __attribute__ ((unused)); +static uint32_t csrrs(unsigned int rd, unsigned int rs1, unsigned int csr) { + return (csr << 20) | (rs1 << 15) | (rd << 7) | MATCH_CSRRS; +} + +static uint32_t fsw(unsigned int src, unsigned int base, uint16_t offset) __attribute__ ((unused)); +static uint32_t fsw(unsigned int src, unsigned int base, uint16_t offset) +{ + return (bits(offset, 11, 5) << 25) | + (bits(src, 4, 0) << 20) | + (base << 15) | + (bits(offset, 4, 0) << 7) | + MATCH_FSW; +} + +static uint32_t fsd(unsigned int src, unsigned int base, uint16_t offset) __attribute__ ((unused)); +static uint32_t fsd(unsigned int src, unsigned int base, uint16_t offset) +{ + return (bits(offset, 11, 5) << 25) | + (bits(src, 4, 0) << 20) | + (base << 15) | + (bits(offset, 4, 0) << 7) | + MATCH_FSD; +} + +static uint32_t flw(unsigned int dest, unsigned int base, uint16_t offset) __attribute__ ((unused)); +static uint32_t flw(unsigned int dest, unsigned int base, uint16_t offset) +{ + return (bits(offset, 11, 0) << 20) | + (base << 15) | + (bits(dest, 4, 0) << 7) | + MATCH_FLW; +} + +static uint32_t fld(unsigned int dest, unsigned int base, uint16_t offset) __attribute__ ((unused)); +static uint32_t fld(unsigned int dest, unsigned int base, uint16_t offset) +{ + return (bits(offset, 11, 0) << 20) | + (base << 15) | + (bits(dest, 4, 0) << 7) | + MATCH_FLD; +} + +static uint32_t ebreak(void) __attribute__ ((unused)); +static uint32_t ebreak(void) { return MATCH_EBREAK; } +static uint32_t ebreak_c(void) __attribute__ ((unused)); +static uint32_t ebreak_c(void) { return MATCH_C_EBREAK; } + +static uint32_t dret(void) __attribute__ ((unused)); +static uint32_t dret(void) { return MATCH_DRET; } + +static uint32_t fence_i(void) __attribute__ ((unused)); +static uint32_t fence_i(void) +{ + return MATCH_FENCE_I; +} + +static uint32_t lui(unsigned int dest, uint32_t imm) __attribute__ ((unused)); +static uint32_t lui(unsigned int dest, uint32_t imm) +{ + return (bits(imm, 19, 0) << 12) | + (dest << 7) | + MATCH_LUI; +} + +/* +static uint32_t csrci(unsigned int csr, uint16_t imm) __attribute__ ((unused)); +static uint32_t csrci(unsigned int csr, uint16_t imm) { + return (csr << 20) | + (bits(imm, 4, 0) << 15) | + MATCH_CSRRCI; +} + +static uint32_t li(unsigned int dest, uint16_t imm) __attribute__ ((unused)); +static uint32_t li(unsigned int dest, uint16_t imm) +{ + return addi(dest, 0, imm); +} + +static uint32_t fsd(unsigned int src, unsigned int base, uint16_t offset) __attribute__ ((unused)); +static uint32_t fsd(unsigned int src, unsigned int base, uint16_t offset) +{ + return (bits(offset, 11, 5) << 25) | + (bits(src, 4, 0) << 20) | + (base << 15) | + (bits(offset, 4, 0) << 7) | + MATCH_FSD; +} + +static uint32_t ori(unsigned int dest, unsigned int src, uint16_t imm) __attribute__ ((unused)); +static uint32_t ori(unsigned int dest, unsigned int src, uint16_t imm) +{ + return (bits(imm, 11, 0) << 20) | + (src << 15) | + (dest << 7) | + MATCH_ORI; +} + +static uint32_t nop(void) __attribute__ ((unused)); +static uint32_t nop(void) +{ + return addi(0, 0, 0); +} +*/ + +static uint32_t xori(unsigned int dest, unsigned int src, uint16_t imm) __attribute__ ((unused)); +static uint32_t xori(unsigned int dest, unsigned int src, uint16_t imm) +{ + return (bits(imm, 11, 0) << 20) | + (src << 15) | + (dest << 7) | + MATCH_XORI; +} + +static uint32_t srli(unsigned int dest, unsigned int src, uint8_t shamt) __attribute__ ((unused)); +static uint32_t srli(unsigned int dest, unsigned int src, uint8_t shamt) +{ + return (bits(shamt, 4, 0) << 20) | + (src << 15) | + (dest << 7) | + MATCH_SRLI; +} diff --git a/vendor/riscv/riscv-isa-sim/riscv/overlap_list.h b/vendor/riscv/riscv-isa-sim/riscv/overlap_list.h new file mode 100644 index 0000000000..fc3b307743 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/overlap_list.h @@ -0,0 +1,11 @@ +DECLARE_OVERLAP_INSN(c_fsdsp, EXT_ZCD) +DECLARE_OVERLAP_INSN(c_fld, EXT_ZCD) +DECLARE_OVERLAP_INSN(c_fldsp, EXT_ZCD) +DECLARE_OVERLAP_INSN(cm_push, EXT_ZCMP) +DECLARE_OVERLAP_INSN(cm_pop, EXT_ZCMP) +DECLARE_OVERLAP_INSN(cm_popret, EXT_ZCMP) +DECLARE_OVERLAP_INSN(cm_popretz, EXT_ZCMP) +DECLARE_OVERLAP_INSN(cm_mva01s, EXT_ZCMP) +DECLARE_OVERLAP_INSN(cm_mvsa01, EXT_ZCMP) +DECLARE_OVERLAP_INSN(cm_jalt, EXT_ZCMT) +DECLARE_OVERLAP_INSN(c_fsd, EXT_ZCD) diff --git a/vendor/riscv/riscv-isa-sim/riscv/p_ext_macros.h b/vendor/riscv/riscv-isa-sim/riscv/p_ext_macros.h new file mode 100644 index 0000000000..29437ad2e2 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/p_ext_macros.h @@ -0,0 +1,506 @@ +// See LICENSE for license details. + +#ifndef _RISCV_P_EXT_MACROS_H +#define _RISCV_P_EXT_MACROS_H + +// The p-extension support is contributed by +// Programming Langauge Lab, Department of Computer Science, National Tsing-Hua University, Taiwan + +#define P_FIELD(R, INDEX, SIZE) \ + (type_sew_t<SIZE>::type)get_field(R, make_mask64(((INDEX) * SIZE), SIZE)) + +#define P_UFIELD(R, INDEX, SIZE) \ + (type_usew_t<SIZE>::type)get_field(R, make_mask64(((INDEX) * SIZE), SIZE)) + +#define P_B(R, INDEX) P_UFIELD(R, INDEX, 8) +#define P_H(R, INDEX) P_UFIELD(R, INDEX, 16) +#define P_W(R, INDEX) P_UFIELD(R, INDEX, 32) +#define P_SB(R, INDEX) P_FIELD(R, INDEX, 8) +#define P_SH(R, INDEX) P_FIELD(R, INDEX, 16) +#define P_SW(R, INDEX) P_FIELD(R, INDEX, 32) + +#define READ_REG_PAIR(reg) ({ \ + require((reg) % 2 == 0); \ + (reg) == 0 ? reg_t(0) : \ + (READ_REG((reg) + 1) << 32) + zext32(READ_REG(reg)); }) + +#define RS1_PAIR READ_REG_PAIR(insn.rs1()) +#define RS2_PAIR READ_REG_PAIR(insn.rs2()) +#define RD_PAIR READ_REG_PAIR(insn.rd()) + +#define WRITE_PD() \ + rd_tmp = set_field(rd_tmp, make_mask64((i * sizeof(pd) * 8), sizeof(pd) * 8), pd); + +#define WRITE_RD_PAIR(value) \ + if (insn.rd() != 0) { \ + require(insn.rd() % 2 == 0); \ + WRITE_REG(insn.rd(), sext32(value)); \ + WRITE_REG(insn.rd() + 1, (sreg_t(value)) >> 32); \ + } + +#define P_SET_OV(ov) \ + if (ov) P.VU.vxsat->write(1); + +#define P_SAT(R, BIT) \ + if (R > INT##BIT##_MAX) { \ + R = INT##BIT##_MAX; \ + P_SET_OV(1); \ + } else if (R < INT##BIT##_MIN) { \ + R = INT##BIT##_MIN; \ + P_SET_OV(1); \ + } + +#define P_SATU(R, BIT) \ + if (R > UINT##BIT##_MAX) { \ + R = UINT##BIT##_MAX; \ + P_SET_OV(1); \ + } else if (R < 0) { \ + P_SET_OV(1); \ + R = 0; \ + } + +#define P_LOOP_BASE(BIT) \ + require_extension(EXT_ZPN); \ + require(BIT == e8 || BIT == e16 || BIT == e32); \ + reg_t rd_tmp = RD; \ + reg_t rs1 = RS1; \ + reg_t rs2 = RS2; \ + sreg_t len = xlen / BIT; \ + for (sreg_t i = len - 1; i >= 0; --i) { + +#define P_ONE_LOOP_BASE(BIT) \ + require_extension(EXT_ZPN); \ + require(BIT == e8 || BIT == e16 || BIT == e32); \ + reg_t rd_tmp = RD; \ + reg_t rs1 = RS1; \ + sreg_t len = xlen / BIT; \ + for (sreg_t i = len - 1; i >= 0; --i) { + +#define P_I_LOOP_BASE(BIT, IMMBIT) \ + require_extension(EXT_ZPN); \ + require(BIT == e8 || BIT == e16 || BIT == e32); \ + reg_t rd_tmp = RD; \ + reg_t rs1 = RS1; \ + type_usew_t<BIT>::type imm##IMMBIT##u = insn.p_imm##IMMBIT(); \ + sreg_t len = xlen / BIT; \ + for (sreg_t i = len - 1; i >= 0; --i) { + +#define P_X_LOOP_BASE(BIT, LOWBIT) \ + require_extension(EXT_ZPN); \ + require(BIT == e8 || BIT == e16 || BIT == e32); \ + reg_t rd_tmp = RD; \ + reg_t rs1 = RS1; \ + type_usew_t<BIT>::type sa = RS2 & ((uint64_t(1) << LOWBIT) - 1); \ + type_sew_t<BIT>::type UNUSED ssa = int64_t(RS2) << (64 - LOWBIT) >> (64 - LOWBIT); \ + sreg_t len = xlen / BIT; \ + for (sreg_t i = len - 1; i >= 0; --i) { + +#define P_MUL_LOOP_BASE(BIT) \ + require_extension(EXT_ZPN); \ + require(BIT == e8 || BIT == e16 || BIT == e32); \ + reg_t rd_tmp = RD; \ + reg_t rs1 = RS1; \ + reg_t rs2 = RS2; \ + sreg_t len = 32 / BIT; \ + for (sreg_t i = len - 1; i >= 0; --i) { + +#define P_REDUCTION_LOOP_BASE(BIT, BIT_INNER, USE_RD) \ + require_extension(EXT_ZPN); \ + require(BIT == e16 || BIT == e32 || BIT == e64); \ + reg_t rd_tmp = USE_RD ? zext_xlen(RD) : 0; \ + reg_t rs1 = zext_xlen(RS1); \ + reg_t rs2 = zext_xlen(RS2); \ + sreg_t len = 64 / BIT; \ + sreg_t len_inner = BIT / BIT_INNER; \ + for (sreg_t i = len - 1; i >= 0; --i) { \ + sreg_t pd_res = P_FIELD(rd_tmp, i, BIT); \ + for (sreg_t j = i * len_inner; j < (i + 1) * len_inner; ++j) { + +#define P_REDUCTION_ULOOP_BASE(BIT, BIT_INNER, USE_RD) \ + require_extension(EXT_ZPN); \ + require(BIT == e16 || BIT == e32 || BIT == e64); \ + reg_t rd_tmp = USE_RD ? zext_xlen(RD) : 0; \ + reg_t rs1 = zext_xlen(RS1); \ + reg_t rs2 = zext_xlen(RS2); \ + sreg_t len = 64 / BIT; \ + sreg_t len_inner = BIT / BIT_INNER; \ + for (sreg_t i = len - 1; i >=0; --i) { \ + reg_t pd_res = P_UFIELD(rd_tmp, i, BIT); \ + for (sreg_t j = i * len_inner; j < (i + 1) * len_inner; ++j) { + +#define P_PARAMS(BIT) \ + auto pd = P_FIELD(rd_tmp, i, BIT); \ + auto ps1 = P_FIELD(rs1, i, BIT); \ + auto ps2 = P_FIELD(rs2, i, BIT); + +#define P_UPARAMS(BIT) \ + auto pd = P_UFIELD(rd_tmp, i, BIT); \ + auto ps1 = P_UFIELD(rs1, i, BIT); \ + auto ps2 = P_UFIELD(rs2, i, BIT); + +#define P_CORSS_PARAMS(BIT) \ + auto pd = P_FIELD(rd_tmp, i, BIT); \ + auto UNUSED ps1 = P_FIELD(rs1, i, BIT); \ + auto UNUSED ps2 = P_FIELD(rs2, (i ^ 1), BIT); + +#define P_CORSS_UPARAMS(BIT) \ + auto pd = P_UFIELD(rd_tmp, i, BIT); \ + auto ps1 = P_UFIELD(rs1, i, BIT); \ + auto ps2 = P_UFIELD(rs2, (i ^ 1), BIT); + +#define P_ONE_PARAMS(BIT) \ + auto pd = P_FIELD(rd_tmp, i, BIT); \ + auto ps1 = P_FIELD(rs1, i, BIT); + +#define P_ONE_UPARAMS(BIT) \ + auto pd = P_UFIELD(rd_tmp, i, BIT); \ + auto ps1 = P_UFIELD(rs1, i, BIT); + +#define P_ONE_SUPARAMS(BIT) \ + auto pd = P_UFIELD(rd_tmp, i, BIT); \ + auto ps1 = P_FIELD(rs1, i, BIT); + +#define P_MUL_PARAMS(BIT) \ + auto pd = P_FIELD(rd_tmp, i, BIT * 2); \ + auto ps1 = P_FIELD(rs1, i, BIT); \ + auto ps2 = P_FIELD(rs2, i, BIT); + +#define P_MUL_UPARAMS(BIT) \ + auto pd = P_UFIELD(rd_tmp, i, BIT * 2); \ + auto ps1 = P_UFIELD(rs1, i, BIT); \ + auto ps2 = P_UFIELD(rs2, i, BIT); + +#define P_MUL_CROSS_PARAMS(BIT) \ + auto pd = P_FIELD(rd_tmp, i, BIT * 2); \ + auto ps1 = P_FIELD(rs1, i, BIT); \ + auto ps2 = P_FIELD(rs2, (i ^ 1), BIT); + +#define P_MUL_CROSS_UPARAMS(BIT) \ + auto pd = P_UFIELD(rd_tmp, i, BIT*2); \ + auto ps1 = P_UFIELD(rs1, i, BIT); \ + auto ps2 = P_UFIELD(rs2, (i ^ 1), BIT); + +#define P_REDUCTION_PARAMS(BIT_INNER) \ + auto ps1 = P_FIELD(rs1, j, BIT_INNER); \ + auto ps2 = P_FIELD(rs2, j, BIT_INNER); + +#define P_REDUCTION_UPARAMS(BIT_INNER) \ + auto ps1 = P_UFIELD(rs1, j, BIT_INNER); \ + auto ps2 = P_UFIELD(rs2, j, BIT_INNER); + +#define P_REDUCTION_SUPARAMS(BIT_INNER) \ + auto ps1 = P_FIELD(rs1, j, BIT_INNER); \ + auto ps2 = P_UFIELD(rs2, j, BIT_INNER); + +#define P_REDUCTION_CROSS_PARAMS(BIT_INNER) \ + auto ps1 = P_FIELD(rs1, j, BIT_INNER); \ + auto ps2 = P_FIELD(rs2, (j ^ 1), BIT_INNER); + +#define P_LOOP_BODY(BIT, BODY) { \ + P_PARAMS(BIT) \ + BODY \ + WRITE_PD(); \ +} + +#define P_ULOOP_BODY(BIT, BODY) { \ + P_UPARAMS(BIT) \ + BODY \ + WRITE_PD(); \ +} + +#define P_ONE_LOOP_BODY(BIT, BODY) { \ + P_ONE_PARAMS(BIT) \ + BODY \ + WRITE_PD(); \ +} + +#define P_CROSS_LOOP_BODY(BIT, BODY) { \ + P_CORSS_PARAMS(BIT) \ + BODY \ + WRITE_PD(); \ +} + +#define P_CROSS_ULOOP_BODY(BIT, BODY) { \ + P_CORSS_UPARAMS(BIT) \ + BODY \ + WRITE_PD(); \ +} + +#define P_ONE_ULOOP_BODY(BIT, BODY) { \ + P_ONE_UPARAMS(BIT) \ + BODY \ + WRITE_PD(); \ +} + +#define P_MUL_LOOP_BODY(BIT, BODY) { \ + P_MUL_PARAMS(BIT) \ + BODY \ + WRITE_PD(); \ +} + +#define P_MUL_ULOOP_BODY(BIT, BODY) { \ + P_MUL_UPARAMS(BIT) \ + BODY \ + WRITE_PD(); \ +} + +#define P_MUL_CROSS_LOOP_BODY(BIT, BODY) { \ + P_MUL_CROSS_PARAMS(BIT) \ + BODY \ + WRITE_PD(); \ +} + +#define P_MUL_CROSS_ULOOP_BODY(BIT, BODY) { \ + P_MUL_CROSS_UPARAMS(BIT) \ + BODY \ + WRITE_PD(); \ +} + +#define P_LOOP(BIT, BODY) \ + P_LOOP_BASE(BIT) \ + P_LOOP_BODY(BIT, BODY) \ + P_LOOP_END() + +#define P_ONE_LOOP(BIT, BODY) \ + P_ONE_LOOP_BASE(BIT) \ + P_ONE_LOOP_BODY(BIT, BODY) \ + P_LOOP_END() + +#define P_ULOOP(BIT, BODY) \ + P_LOOP_BASE(BIT) \ + P_ULOOP_BODY(BIT, BODY) \ + P_LOOP_END() + +#define P_CROSS_LOOP(BIT, BODY1, BODY2) \ + P_LOOP_BASE(BIT) \ + P_CROSS_LOOP_BODY(BIT, BODY1) \ + --i; \ + if (sizeof(#BODY2) == 1) { \ + P_CROSS_LOOP_BODY(BIT, BODY1) \ + } \ + else { \ + P_CROSS_LOOP_BODY(BIT, BODY2) \ + } \ + P_LOOP_END() + +#define P_CROSS_ULOOP(BIT, BODY1, BODY2) \ + P_LOOP_BASE(BIT) \ + P_CROSS_ULOOP_BODY(BIT, BODY1) \ + --i; \ + P_CROSS_ULOOP_BODY(BIT, BODY2) \ + P_LOOP_END() + +#define P_STRAIGHT_LOOP(BIT, BODY1, BODY2) \ + P_LOOP_BASE(BIT) \ + P_LOOP_BODY(BIT, BODY1) \ + --i; \ + P_LOOP_BODY(BIT, BODY2) \ + P_LOOP_END() + +#define P_STRAIGHT_ULOOP(BIT, BODY1, BODY2) \ + P_LOOP_BASE(BIT) \ + P_ULOOP_BODY(BIT, BODY1) \ + --i; \ + P_ULOOP_BODY(BIT, BODY2) \ + P_LOOP_END() + +#define P_X_LOOP(BIT, RS2_LOW_BIT, BODY) \ + P_X_LOOP_BASE(BIT, RS2_LOW_BIT) \ + P_ONE_LOOP_BODY(BIT, BODY) \ + P_LOOP_END() + +#define P_X_ULOOP(BIT, RS2_LOW_BIT, BODY) \ + P_X_LOOP_BASE(BIT, RS2_LOW_BIT) \ + P_ONE_ULOOP_BODY(BIT, BODY) \ + P_LOOP_END() + +#define P_I_LOOP(BIT, IMMBIT, BODY) \ + P_I_LOOP_BASE(BIT, IMMBIT) \ + P_ONE_LOOP_BODY(BIT, BODY) \ + P_LOOP_END() + +#define P_I_ULOOP(BIT, IMMBIT, BODY) \ + P_I_LOOP_BASE(BIT, IMMBIT) \ + P_ONE_ULOOP_BODY(BIT, BODY) \ + P_LOOP_END() + +#define P_MUL_LOOP(BIT, BODY) \ + P_MUL_LOOP_BASE(BIT) \ + P_MUL_LOOP_BODY(BIT, BODY) \ + P_PAIR_LOOP_END() + +#define P_MUL_ULOOP(BIT, BODY) \ + P_MUL_LOOP_BASE(BIT) \ + P_MUL_ULOOP_BODY(BIT, BODY) \ + P_PAIR_LOOP_END() + +#define P_MUL_CROSS_LOOP(BIT, BODY) \ + P_MUL_LOOP_BASE(BIT) \ + P_MUL_CROSS_LOOP_BODY(BIT, BODY) \ + P_PAIR_LOOP_END() + +#define P_MUL_CROSS_ULOOP(BIT, BODY) \ + P_MUL_LOOP_BASE(BIT) \ + P_MUL_CROSS_ULOOP_BODY(BIT, BODY) \ + P_PAIR_LOOP_END() + +#define P_REDUCTION_LOOP(BIT, BIT_INNER, USE_RD, IS_SAT, BODY) \ + P_REDUCTION_LOOP_BASE(BIT, BIT_INNER, USE_RD) \ + P_REDUCTION_PARAMS(BIT_INNER) \ + BODY \ + P_REDUCTION_LOOP_END(BIT, IS_SAT) + +#define P_REDUCTION_ULOOP(BIT, BIT_INNER, USE_RD, IS_SAT, BODY) \ + P_REDUCTION_ULOOP_BASE(BIT, BIT_INNER, USE_RD) \ + P_REDUCTION_UPARAMS(BIT_INNER) \ + BODY \ + P_REDUCTION_ULOOP_END(BIT, IS_SAT) + +#define P_REDUCTION_SULOOP(BIT, BIT_INNER, USE_RD, IS_SAT, BODY) \ + P_REDUCTION_LOOP_BASE(BIT, BIT_INNER, USE_RD) \ + P_REDUCTION_SUPARAMS(BIT_INNER) \ + BODY \ + P_REDUCTION_LOOP_END(BIT, IS_SAT) + +#define P_REDUCTION_CROSS_LOOP(BIT, BIT_INNER, USE_RD, IS_SAT, BODY) \ + P_REDUCTION_LOOP_BASE(BIT, BIT_INNER, USE_RD) \ + P_REDUCTION_CROSS_PARAMS(BIT_INNER) \ + BODY \ + P_REDUCTION_LOOP_END(BIT, IS_SAT) + +#define P_LOOP_END() \ + } \ + WRITE_RD(sext_xlen(rd_tmp)); + +#define P_PAIR_LOOP_END() \ + } \ + if (xlen == 32) { \ + WRITE_RD_PAIR(rd_tmp); \ + } \ + else { \ + WRITE_RD(sext_xlen(rd_tmp)); \ + } + +#define P_REDUCTION_LOOP_END(BIT, IS_SAT) \ + } \ + if (IS_SAT) { \ + P_SAT(pd_res, BIT); \ + } \ + type_usew_t<BIT>::type pd = pd_res; \ + WRITE_PD(); \ + } \ + WRITE_RD(sext_xlen(rd_tmp)); + +#define P_REDUCTION_ULOOP_END(BIT, IS_SAT) \ + } \ + if (IS_SAT) { \ + P_SATU(pd_res, BIT); \ + } \ + type_usew_t<BIT>::type pd = pd_res; \ + WRITE_PD(); \ + } \ + WRITE_RD(sext_xlen(rd_tmp)); + +#define P_SUNPKD8(X, Y) \ + require_extension(EXT_ZPN); \ + reg_t rd_tmp = 0; \ + int16_t pd[4] = { \ + P_SB(RS1, Y), \ + P_SB(RS1, X), \ + P_SB(RS1, Y + 4), \ + P_SB(RS1, X + 4), \ + }; \ + if (xlen == 64) { \ + memcpy(&rd_tmp, pd, 8); \ + } else { \ + memcpy(&rd_tmp, pd, 4); \ + } \ + WRITE_RD(sext_xlen(rd_tmp)); + +#define P_ZUNPKD8(X, Y) \ + require_extension(EXT_ZPN); \ + reg_t rd_tmp = 0; \ + uint16_t pd[4] = { \ + P_B(RS1, Y), \ + P_B(RS1, X), \ + P_B(RS1, Y + 4), \ + P_B(RS1, X + 4), \ + }; \ + if (xlen == 64) { \ + memcpy(&rd_tmp, pd, 8); \ + } else { \ + memcpy(&rd_tmp, pd, 4); \ + } \ + WRITE_RD(sext_xlen(rd_tmp)); + +#define P_PK(BIT, X, Y) \ + require_extension(EXT_ZPN); \ + require(BIT == e16 || BIT == e32); \ + reg_t rd_tmp = 0, UNUSED rs1 = RS1, UNUSED rs2 = RS2; \ + for (sreg_t i = 0; i < xlen / BIT / 2; i++) { \ + rd_tmp = set_field(rd_tmp, make_mask64(i * 2 * BIT, BIT), \ + P_UFIELD(RS2, i * 2 + Y, BIT)); \ + rd_tmp = set_field(rd_tmp, make_mask64((i * 2 + 1) * BIT, BIT), \ + P_UFIELD(RS1, i * 2 + X, BIT)); \ + } \ + WRITE_RD(sext_xlen(rd_tmp)); + +#define P_64_PROFILE_BASE() \ + require_extension(EXT_ZPSFOPERAND); \ + sreg_t rd, rs1, rs2; + +#define P_64_UPROFILE_BASE() \ + require_extension(EXT_ZPSFOPERAND); \ + reg_t rd, rs1, rs2; + +#define P_64_PROFILE_PARAM(USE_RD, INPUT_PAIR) \ + if (xlen == 32) { \ + rs1 = INPUT_PAIR ? RS1_PAIR : RS1; \ + rs2 = INPUT_PAIR ? RS2_PAIR : RS2; \ + rd = USE_RD ? RD_PAIR : 0; \ + } else { \ + rs1 = RS1; \ + rs2 = RS2; \ + rd = USE_RD ? RD : 0; \ + } + +#define P_64_PROFILE(BODY) \ + P_64_PROFILE_BASE() \ + P_64_PROFILE_PARAM(false, true) \ + BODY \ + P_64_PROFILE_END() \ + +#define P_64_UPROFILE(BODY) \ + P_64_UPROFILE_BASE() \ + P_64_PROFILE_PARAM(false, true) \ + BODY \ + P_64_PROFILE_END() \ + +#define P_64_PROFILE_REDUCTION(BIT, BODY) \ + P_64_PROFILE_BASE() \ + P_64_PROFILE_PARAM(true, false) \ + for (sreg_t i = 0; i < xlen / BIT; i++) { \ + sreg_t ps1 = P_FIELD(rs1, i, BIT); \ + sreg_t ps2 = P_FIELD(rs2, i, BIT); \ + BODY \ + } \ + P_64_PROFILE_END() \ + +#define P_64_UPROFILE_REDUCTION(BIT, BODY) \ + P_64_UPROFILE_BASE() \ + P_64_PROFILE_PARAM(true, false) \ + for (sreg_t i = 0; i < xlen / BIT; i++) { \ + reg_t ps1 = P_UFIELD(rs1, i, BIT); \ + reg_t ps2 = P_UFIELD(rs2, i, BIT); \ + BODY \ + } \ + P_64_PROFILE_END() \ + +#define P_64_PROFILE_END() \ + if (xlen == 32) { \ + WRITE_RD_PAIR(rd); \ + } else { \ + WRITE_RD(sext_xlen(rd)); \ + } + +#endif diff --git a/vendor/riscv/riscv-isa-sim/riscv/platform.h b/vendor/riscv/riscv-isa-sim/riscv/platform.h new file mode 100644 index 0000000000..7fffdc84bb --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/platform.h @@ -0,0 +1,21 @@ +// See LICENSE for license details. +#ifndef _RISCV_PLATFORM_H +#define _RISCV_PLATFORM_H + +#define DEFAULT_KERNEL_BOOTARGS "console=ttyS0 earlycon" +#define DEFAULT_RSTVEC 0x00001000 +#define CLINT_BASE 0x02000000 +#define CLINT_SIZE 0x000c0000 +#define PLIC_BASE 0x0c000000 +#define PLIC_SIZE 0x01000000 +#define PLIC_NDEV 31 +#define PLIC_PRIO_BITS 4 +#define NS16550_BASE 0x10000000 +#define NS16550_SIZE 0x100 +#define NS16550_REG_SHIFT 0 +#define NS16550_REG_IO_WIDTH 1 +#define NS16550_INTERRUPT_ID 1 +#define EXT_IO_BASE 0x40000000 +#define DRAM_BASE 0x80000000 + +#endif diff --git a/vendor/riscv/riscv-isa-sim/riscv/plic.cc b/vendor/riscv/riscv-isa-sim/riscv/plic.cc new file mode 100644 index 0000000000..37a5f53ba0 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/plic.cc @@ -0,0 +1,390 @@ +#include <sys/time.h> +#include "devices.h" +#include "processor.h" +#include "simif.h" + +#define PLIC_MAX_CONTEXTS 15872 + +/* + * The PLIC consists of memory-mapped control registers, with a memory map + * as follows: + * + * base + 0x000000: Reserved (interrupt source 0 does not exist) + * base + 0x000004: Interrupt source 1 priority + * base + 0x000008: Interrupt source 2 priority + * ... + * base + 0x000FFC: Interrupt source 1023 priority + * base + 0x001000: Pending 0 + * base + 0x001FFF: Pending + * base + 0x002000: Enable bits for sources 0-31 on context 0 + * base + 0x002004: Enable bits for sources 32-63 on context 0 + * ... + * base + 0x0020FC: Enable bits for sources 992-1023 on context 0 + * base + 0x002080: Enable bits for sources 0-31 on context 1 + * ... + * base + 0x002100: Enable bits for sources 0-31 on context 2 + * ... + * base + 0x1F1F80: Enable bits for sources 992-1023 on context 15871 + * base + 0x1F1F84: Reserved + * ... (higher context IDs would fit here, but wouldn't fit + * inside the per-context priority vector) + * base + 0x1FFFFC: Reserved + * base + 0x200000: Priority threshold for context 0 + * base + 0x200004: Claim/complete for context 0 + * base + 0x200008: Reserved + * ... + * base + 0x200FFC: Reserved + * base + 0x201000: Priority threshold for context 1 + * base + 0x201004: Claim/complete for context 1 + * ... + * base + 0xFFE000: Priority threshold for context 15871 + * base + 0xFFE004: Claim/complete for context 15871 + * base + 0xFFE008: Reserved + * ... + * base + 0xFFFFFC: Reserved + */ + +/* Each interrupt source has a priority register associated with it. */ +#define PRIORITY_BASE 0 +#define PRIORITY_PER_ID 4 + +/* Each interrupt source has a pending bit associated with it. */ +#define PENDING_BASE 0x1000 + +/* + * Each hart context has a vector of interupt enable bits associated with it. + * There's one bit for each interrupt source. + */ +#define ENABLE_BASE 0x2000 +#define ENABLE_PER_HART 0x80 + +/* + * Each hart context has a set of control registers associated with it. Right + * now there's only two: a source priority threshold over which the hart will + * take an interrupt, and a register to claim interrupts. + */ +#define CONTEXT_BASE 0x200000 +#define CONTEXT_PER_HART 0x1000 +#define CONTEXT_THRESHOLD 0 +#define CONTEXT_CLAIM 4 + +#define REG_SIZE 0x1000000 + +plic_t::plic_t(simif_t* sim, uint32_t ndev) + : num_ids(ndev + 1), num_ids_word(((ndev + 1) + (32 - 1)) / 32), + max_prio((1UL << PLIC_PRIO_BITS) - 1), priority{}, level{} +{ + // PLIC contexts are contiguous in memory even if harts are discontiguous. + for (const auto& [hart_id, hart] : sim->get_harts()) { + contexts.push_back(plic_context_t(hart, true)); + + if (hart->extension_enabled_const('S')) { + contexts.push_back(plic_context_t(hart, false)); + } + } +} + +uint32_t plic_t::context_best_pending(const plic_context_t *c) +{ + uint8_t best_id_prio = 0; + uint32_t best_id = 0; + + for (uint32_t i = 0; i < num_ids_word; i++) { + if (!c->pending[i]) { + continue; + } + + for (uint32_t j = 0; j < 32; j++) { + uint32_t id = i * 32 + j; + if ((num_ids <= id) || + !(c->pending[i] & (1 << j)) || + (c->claimed[i] & (1 << j))) { + continue; + } + + if (!best_id || + (best_id_prio < c->pending_priority[id])) { + best_id = id; + best_id_prio = c->pending_priority[id]; + } + } + } + + return best_id; +} + +void plic_t::context_update(const plic_context_t *c) +{ + uint32_t best_id = context_best_pending(c); + reg_t mask = c->mmode ? MIP_MEIP : MIP_SEIP; + + c->proc->state.mip->backdoor_write_with_mask(mask, best_id ? mask : 0); +} + +uint32_t plic_t::context_claim(plic_context_t *c) +{ + uint32_t best_id = context_best_pending(c); + uint32_t best_id_word = best_id / 32; + uint32_t best_id_mask = (1 << (best_id % 32)); + + if (best_id) { + c->claimed[best_id_word] |= best_id_mask; + } + + context_update(c); + return best_id; +} + +bool plic_t::priority_read(reg_t offset, uint32_t *val) +{ + uint32_t id = (offset >> 2); + + if (id > 0 && id < num_ids) + *val = priority[id]; + else + *val = 0; + + return true; +} + +bool plic_t::priority_write(reg_t offset, uint32_t val) +{ + uint32_t id = (offset >> 2); + + if (id > 0 && id < num_ids) { + val &= ((1 << PLIC_PRIO_BITS) - 1); + priority[id] = val; + } + + return true; +} + +bool plic_t::pending_read(reg_t offset, uint32_t *val) +{ + uint32_t id_word = (offset >> 2); + + if (id_word < num_ids_word) { + *val = 0; + for (auto context: contexts) { + *val |= context.pending[id_word]; + } + } else + *val = 0; + + return true; +} + +bool plic_t::context_enable_read(const plic_context_t *c, + reg_t offset, uint32_t *val) +{ + uint32_t id_word = offset >> 2; + + if (id_word < num_ids_word) + *val = c->enable[id_word]; + else + *val = 0; + + return true; +} + +bool plic_t::context_enable_write(plic_context_t *c, + reg_t offset, uint32_t val) +{ + uint32_t id_word = offset >> 2; + + if (id_word >= num_ids_word) + return true; + + uint32_t old_val = c->enable[id_word]; + uint32_t new_val = id_word == 0 ? val & ~(uint32_t)1 : val; + uint32_t xor_val = old_val ^ new_val; + + c->enable[id_word] = new_val; + + for (uint32_t i = 0; i < 32; i++) { + uint32_t id = id_word * 32 + i; + uint32_t id_mask = 1 << i; + uint8_t id_prio = priority[id]; + if (!(xor_val & id_mask)) { + continue; + } + if ((new_val & id_mask) && + (level[id_word] & id_mask)) { + c->pending[id_word] |= id_mask; + c->pending_priority[id] = id_prio; + } else if (!(new_val & id_mask)) { + c->pending[id_word] &= ~id_mask; + c->pending_priority[id] = 0; + c->claimed[id_word] &= ~id_mask; + } + } + + context_update(c); + return true; +} + +bool plic_t::context_read(plic_context_t *c, + reg_t offset, uint32_t *val) +{ + switch (offset) { + case CONTEXT_THRESHOLD: + *val = c->priority_threshold; + return true; + case CONTEXT_CLAIM: + *val = context_claim(c); + return true; + default: + return true; + }; +} + +bool plic_t::context_write(plic_context_t *c, + reg_t offset, uint32_t val) +{ + bool ret = true, update = false; + + switch (offset) { + case CONTEXT_THRESHOLD: + val &= ((1 << PLIC_PRIO_BITS) - 1); + if (val <= max_prio) { + c->priority_threshold = val; + update = true; + } else { + ret = false; + } + break; + case CONTEXT_CLAIM: { + uint32_t id_word = val / 32; + uint32_t id_mask = 1 << (val % 32); + if ((val < num_ids) && + (c->enable[id_word] & id_mask)) { + c->claimed[id_word] &= ~id_mask; + update = true; + } + break; + } + default: + ret = false; + break; + }; + + if (update) { + context_update(c); + } + + return ret; +} + +void plic_t::set_interrupt_level(uint32_t id, int lvl) +{ + if (id <= 0 || num_ids <= id) { + return; + } + + uint8_t id_prio = priority[id]; + uint32_t id_word = id / 32; + uint32_t id_mask = 1 << (id % 32); + + if (lvl) { + level[id_word] |= id_mask; + } else { + level[id_word] &= ~id_mask; + } + + /* + * Note: PLIC interrupts are level-triggered. As of now, + * there is no notion of edge-triggered interrupts. To + * handle this we auto-clear edge-triggered interrupts + * when PLIC context CLAIM register is read. + */ + for (size_t i = 0; i < contexts.size(); i++) { + plic_context_t* c = &contexts[i]; + + if (c->enable[id_word] & id_mask) { + if (lvl) { + c->pending[id_word] |= id_mask; + c->pending_priority[id] = id_prio; + } else { + c->pending[id_word] &= ~id_mask; + c->pending_priority[id] = 0; + c->claimed[id_word] &= ~id_mask; + } + context_update(c); + break; + } + } +} + +bool plic_t::load(reg_t addr, size_t len, uint8_t* bytes) +{ + bool ret = false; + uint32_t val = 0; + + switch (len) { + case 4: + break; + case 8: + // Implement double-word loads as a pair of word loads + return load(addr, 4, bytes) && load(addr + 4, 4, bytes + 4); + default: + // Subword loads are not supported + return false; + } + + if (PRIORITY_BASE <= addr && addr < PENDING_BASE) { + ret = priority_read(addr, &val); + } else if (PENDING_BASE <= addr && addr < ENABLE_BASE) { + ret = pending_read(addr - PENDING_BASE, &val); + } else if (ENABLE_BASE <= addr && addr < CONTEXT_BASE) { + uint32_t cntx = (addr - ENABLE_BASE) / ENABLE_PER_HART; + addr -= cntx * ENABLE_PER_HART + ENABLE_BASE; + if (cntx < contexts.size()) { + ret = context_enable_read(&contexts[cntx], addr, &val); + } + } else if (CONTEXT_BASE <= addr && addr < REG_SIZE) { + uint32_t cntx = (addr - CONTEXT_BASE) / CONTEXT_PER_HART; + addr -= cntx * CONTEXT_PER_HART + CONTEXT_BASE; + if (cntx < contexts.size()) { + ret = context_read(&contexts[cntx], addr, &val); + } + } + + read_little_endian_reg(val, addr, len, bytes); + + return ret; +} + +bool plic_t::store(reg_t addr, size_t len, const uint8_t* bytes) +{ + bool ret = false; + uint32_t val = 0; + + switch (len) { + case 4: + break; + case 8: + // Implement double-word stores as a pair of word stores + return store(addr, 4, bytes) && store(addr + 4, 4, bytes + 4); + default: + // Subword stores are not supported + return false; + } + + write_little_endian_reg(&val, addr, len, bytes); + + if (PRIORITY_BASE <= addr && addr < ENABLE_BASE) { + ret = priority_write(addr, val); + } else if (ENABLE_BASE <= addr && addr < CONTEXT_BASE) { + uint32_t cntx = (addr - ENABLE_BASE) / ENABLE_PER_HART; + addr -= cntx * ENABLE_PER_HART + ENABLE_BASE; + if (cntx < contexts.size()) + ret = context_enable_write(&contexts[cntx], addr, val); + } else if (CONTEXT_BASE <= addr && addr < REG_SIZE) { + uint32_t cntx = (addr - CONTEXT_BASE) / CONTEXT_PER_HART; + addr -= cntx * CONTEXT_PER_HART + CONTEXT_BASE; + if (cntx < contexts.size()) + ret = context_write(&contexts[cntx], addr, val); + } + + return ret; +} diff --git a/vendor/riscv/riscv-isa-sim/riscv/processor.cc b/vendor/riscv/riscv-isa-sim/riscv/processor.cc new file mode 100644 index 0000000000..330bd30c7b --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/processor.cc @@ -0,0 +1,1160 @@ +// See LICENSE for license details. + +#include "arith.h" +#include "processor.h" +#include "extension.h" +#include "common.h" +#include "config.h" +#include "decode_macros.h" +#include "simif.h" +#include "mmu.h" +#include "disasm.h" +#include "platform.h" +#include "vector_unit.h" +#include <cinttypes> +#include <cmath> +#include <cstdlib> +#include <iostream> +#include <iomanip> +#include <assert.h> +#include <limits.h> +#include <stdexcept> +#include <string> +#include <algorithm> + +#ifdef __GNUC__ +# pragma GCC diagnostic ignored "-Wunused-variable" +#endif + +#undef STATE +#define STATE state + +processor_t::processor_t(const isa_parser_t *isa, const cfg_t *cfg, + simif_t* sim, uint32_t id, bool halt_on_reset, + FILE* log_file, std::ostream& sout_) + : debug(false), halt_request(HR_NONE), isa(isa), cfg(cfg), sim(sim), id(id), xlen(0), + histogram_enabled(false), log_commits_enabled(false), + log_file(log_file), sout_(sout_.rdbuf()), halt_on_reset(halt_on_reset), + in_wfi(false), check_triggers_icount(false), + impl_table(256, false), extension_enable_table(isa->get_extension_table()), + last_pc(1), executions(1), TM(cfg->trigger_count) +{ + VU.p = this; + TM.proc = this; + +#ifndef __SIZEOF_INT128__ + if (extension_enabled('V')) { + fprintf(stderr, "V extension is not supported on platforms without __int128 type\n"); + abort(); + } +#endif + + parse_varch_string(cfg->varch()); + + register_base_instructions(); + mmu = new mmu_t(sim, cfg->endianness, this); + + disassembler = new disassembler_t(isa); + for (auto e : isa->get_extensions()) + register_extension(e.second); + + set_pmp_granularity(1 << PMP_SHIFT); + set_pmp_num(cfg->pmpregions); + + if (isa->get_max_xlen() == 32) + set_mmu_capability(IMPL_MMU_SV32); + else if (isa->get_max_xlen() == 64) + set_mmu_capability(IMPL_MMU_SV57); + + set_impl(IMPL_MMU_ASID, true); + set_impl(IMPL_MMU_VMID, true); + + reset(); +} + +processor_t::~processor_t() +{ + if (histogram_enabled) + { + std::vector<std::pair<reg_t, uint64_t>> ordered_histo(pc_histogram.begin(), pc_histogram.end()); + std::sort(ordered_histo.begin(), ordered_histo.end(), + [](auto& lhs, auto& rhs) { return lhs.second < rhs.second; }); + + fprintf(stderr, "PC Histogram size:%zu\n", ordered_histo.size()); + for (auto it : ordered_histo) + fprintf(stderr, "%0" PRIx64 " %" PRIu64 "\n", it.first, it.second); + } + + delete mmu; + delete disassembler; +} + +static void bad_option_string(const char *option, const char *value, + const char *msg) +{ + fprintf(stderr, "error: bad %s option '%s'. %s\n", option, value, msg); + abort(); +} + +static void bad_varch_string(const char* varch, const char *msg) +{ + bad_option_string("--varch", varch, msg); +} + +static std::string get_string_token(std::string str, const char delimiter, size_t& pos) +{ + size_t _pos = pos; + while (pos < str.length() && str[pos] != delimiter) ++pos; + return str.substr(_pos, pos - _pos); +} + +static int get_int_token(std::string str, const char delimiter, size_t& pos) +{ + size_t _pos = pos; + while (pos < str.length() && str[pos] != delimiter) { + if (!isdigit(str[pos])) + bad_varch_string(str.c_str(), "Unsupported value"); // An integer is expected + ++pos; + } + return (pos == _pos) ? 0 : stoi(str.substr(_pos, pos - _pos)); +} + +static bool check_pow2(int val) +{ + return ((val & (val - 1))) == 0; +} + +static std::string strtolower(const char* str) +{ + std::string res; + for (const char *r = str; *r; r++) + res += std::tolower(*r); + return res; +} + +void processor_t::parse_varch_string(const char* s) +{ + std::string str = strtolower(s); + size_t pos = 0; + size_t len = str.length(); + int vlen = 0; + int elen = 0; + int vstart_alu = 0; + + while (pos < len) { + std::string attr = get_string_token(str, ':', pos); + + ++pos; + + if (attr == "vlen") + vlen = get_int_token(str, ',', pos); + else if (attr == "elen") + elen = get_int_token(str, ',', pos); + else if (attr == "vstartalu") + vstart_alu = get_int_token(str, ',', pos); + else + bad_varch_string(s, "Unsupported token"); + + ++pos; + } + + // The integer should be the power of 2 + if (!check_pow2(vlen) || !check_pow2(elen)) { + bad_varch_string(s, "The integer value should be the power of 2"); + } + + /* Vector spec requirements. */ + if (vlen < elen) + bad_varch_string(s, "vlen must be >= elen"); + + /* spike requirements. */ + if (vlen > 4096) + bad_varch_string(s, "vlen must be <= 4096"); + + VU.VLEN = vlen; + VU.ELEN = elen; + VU.vlenb = vlen / 8; + VU.vstart_alu = vstart_alu; +} + +static int xlen_to_uxl(int xlen) +{ + if (xlen == 32) + return 1; + if (xlen == 64) + return 2; + abort(); +} + +void state_t::reset(processor_t* const proc, reg_t max_isa) +{ + pc = DEFAULT_RSTVEC; + XPR.reset(); + FPR.reset(); + + // This assumes xlen is always max_xlen, which is true today (see + // mstatus_csr_t::unlogged_write()): + auto xlen = proc->get_isa().get_max_xlen(); + + prv = PRV_M; + v = false; + csrmap[CSR_MISA] = misa = std::make_shared<misa_csr_t>(proc, CSR_MISA, max_isa); + mstatus = std::make_shared<mstatus_csr_t>(proc, CSR_MSTATUS); + + if (xlen == 32) { + csrmap[CSR_MSTATUS] = std::make_shared<rv32_low_csr_t>(proc, CSR_MSTATUS, mstatus); + csrmap[CSR_MSTATUSH] = mstatush = std::make_shared<rv32_high_csr_t>(proc, CSR_MSTATUSH, mstatus); + } else { + csrmap[CSR_MSTATUS] = mstatus; + } + csrmap[CSR_MEPC] = mepc = std::make_shared<epc_csr_t>(proc, CSR_MEPC); + csrmap[CSR_MTVAL] = mtval = std::make_shared<basic_csr_t>(proc, CSR_MTVAL, 0); + csrmap[CSR_MSCRATCH] = std::make_shared<basic_csr_t>(proc, CSR_MSCRATCH, 0); + csrmap[CSR_MTVEC] = mtvec = std::make_shared<tvec_csr_t>(proc, CSR_MTVEC); + csrmap[CSR_MCAUSE] = mcause = std::make_shared<cause_csr_t>(proc, CSR_MCAUSE); + minstret = std::make_shared<wide_counter_csr_t>(proc, CSR_MINSTRET); + mcycle = std::make_shared<wide_counter_csr_t>(proc, CSR_MCYCLE); + time = std::make_shared<time_counter_csr_t>(proc, CSR_TIME); + if (proc->extension_enabled_const(EXT_ZICNTR)) { + csrmap[CSR_INSTRET] = std::make_shared<counter_proxy_csr_t>(proc, CSR_INSTRET, minstret); + csrmap[CSR_CYCLE] = std::make_shared<counter_proxy_csr_t>(proc, CSR_CYCLE, mcycle); + csrmap[CSR_TIME] = time_proxy = std::make_shared<counter_proxy_csr_t>(proc, CSR_TIME, time); + } + if (xlen == 32) { + csr_t_p minstreth, mcycleh; + csrmap[CSR_MINSTRET] = std::make_shared<rv32_low_csr_t>(proc, CSR_MINSTRET, minstret); + csrmap[CSR_MINSTRETH] = minstreth = std::make_shared<rv32_high_csr_t>(proc, CSR_MINSTRETH, minstret); + csrmap[CSR_MCYCLE] = std::make_shared<rv32_low_csr_t>(proc, CSR_MCYCLE, mcycle); + csrmap[CSR_MCYCLEH] = mcycleh = std::make_shared<rv32_high_csr_t>(proc, CSR_MCYCLEH, mcycle); + if (proc->extension_enabled_const(EXT_ZICNTR)) { + auto timeh = std::make_shared<rv32_high_csr_t>(proc, CSR_TIMEH, time); + csrmap[CSR_INSTRETH] = std::make_shared<counter_proxy_csr_t>(proc, CSR_INSTRETH, minstreth); + csrmap[CSR_CYCLEH] = std::make_shared<counter_proxy_csr_t>(proc, CSR_CYCLEH, mcycleh); + csrmap[CSR_TIMEH] = std::make_shared<counter_proxy_csr_t>(proc, CSR_TIMEH, timeh); + } + } else { + csrmap[CSR_MINSTRET] = minstret; + csrmap[CSR_MCYCLE] = mcycle; + } + for (reg_t i = 3; i < N_HPMCOUNTERS + 3; ++i) { + const reg_t which_mevent = CSR_MHPMEVENT3 + i - 3; + const reg_t which_meventh = CSR_MHPMEVENT3H + i - 3; + const reg_t which_mcounter = CSR_MHPMCOUNTER3 + i - 3; + const reg_t which_mcounterh = CSR_MHPMCOUNTER3H + i - 3; + const reg_t which_counter = CSR_HPMCOUNTER3 + i - 3; + const reg_t which_counterh = CSR_HPMCOUNTER3H + i - 3; + mevent[i - 3] = std::make_shared<mevent_csr_t>(proc, which_mevent); + auto mcounter = std::make_shared<const_csr_t>(proc, which_mcounter, 0); + csrmap[which_mcounter] = mcounter; + + if (proc->extension_enabled_const(EXT_ZIHPM)) { + auto counter = std::make_shared<counter_proxy_csr_t>(proc, which_counter, mcounter); + csrmap[which_counter] = counter; + } + if (xlen == 32) { + csrmap[which_mevent] = std::make_shared<rv32_low_csr_t>(proc, which_mevent, mevent[i - 3]);; + auto mcounterh = std::make_shared<const_csr_t>(proc, which_mcounterh, 0); + csrmap[which_mcounterh] = mcounterh; + if (proc->extension_enabled_const(EXT_ZIHPM)) { + auto counterh = std::make_shared<counter_proxy_csr_t>(proc, which_counterh, mcounterh); + csrmap[which_counterh] = counterh; + } + if (proc->extension_enabled_const(EXT_SSCOFPMF)) { + auto meventh = std::make_shared<rv32_high_csr_t>(proc, which_meventh, mevent[i - 3]); + csrmap[which_meventh] = meventh; + } + } else { + csrmap[which_mevent] = mevent[i - 3]; + } + } + csrmap[CSR_MCOUNTINHIBIT] = std::make_shared<const_csr_t>(proc, CSR_MCOUNTINHIBIT, 0); + if (proc->extension_enabled_const(EXT_SSCOFPMF)) + csrmap[CSR_SCOUNTOVF] = std::make_shared<scountovf_csr_t>(proc, CSR_SCOUNTOVF); + csrmap[CSR_MIE] = mie = std::make_shared<mie_csr_t>(proc, CSR_MIE); + csrmap[CSR_MIP] = mip = std::make_shared<mip_csr_t>(proc, CSR_MIP); + auto sip_sie_accr = std::make_shared<generic_int_accessor_t>( + this, + ~MIP_HS_MASK, // read_mask + MIP_SSIP | MIP_LCOFIP, // ip_write_mask + ~MIP_HS_MASK, // ie_write_mask + generic_int_accessor_t::mask_mode_t::MIDELEG, + 0 // shiftamt + ); + + auto hip_hie_accr = std::make_shared<generic_int_accessor_t>( + this, + MIP_HS_MASK, // read_mask + MIP_VSSIP, // ip_write_mask + MIP_HS_MASK, // ie_write_mask + generic_int_accessor_t::mask_mode_t::MIDELEG, + 0 // shiftamt + ); + + auto hvip_accr = std::make_shared<generic_int_accessor_t>( + this, + MIP_VS_MASK, // read_mask + MIP_VS_MASK, // ip_write_mask + MIP_VS_MASK, // ie_write_mask + generic_int_accessor_t::mask_mode_t::NONE, + 0 // shiftamt + ); + + auto vsip_vsie_accr = std::make_shared<generic_int_accessor_t>( + this, + MIP_VS_MASK, // read_mask + MIP_VSSIP, // ip_write_mask + MIP_VS_MASK, // ie_write_mask + generic_int_accessor_t::mask_mode_t::HIDELEG, + 1 // shiftamt + ); + + auto nonvirtual_sip = std::make_shared<mip_proxy_csr_t>(proc, CSR_SIP, sip_sie_accr); + auto vsip = std::make_shared<mip_proxy_csr_t>(proc, CSR_VSIP, vsip_vsie_accr); + csrmap[CSR_VSIP] = vsip; + csrmap[CSR_SIP] = std::make_shared<virtualized_csr_t>(proc, nonvirtual_sip, vsip); + csrmap[CSR_HIP] = std::make_shared<mip_proxy_csr_t>(proc, CSR_HIP, hip_hie_accr); + csrmap[CSR_HVIP] = std::make_shared<mip_proxy_csr_t>(proc, CSR_HVIP, hvip_accr); + + auto nonvirtual_sie = std::make_shared<mie_proxy_csr_t>(proc, CSR_SIE, sip_sie_accr); + auto vsie = std::make_shared<mie_proxy_csr_t>(proc, CSR_VSIE, vsip_vsie_accr); + csrmap[CSR_VSIE] = vsie; + csrmap[CSR_SIE] = std::make_shared<virtualized_csr_t>(proc, nonvirtual_sie, vsie); + csrmap[CSR_HIE] = std::make_shared<mie_proxy_csr_t>(proc, CSR_HIE, hip_hie_accr); + + csrmap[CSR_MEDELEG] = medeleg = std::make_shared<medeleg_csr_t>(proc, CSR_MEDELEG); + csrmap[CSR_MIDELEG] = mideleg = std::make_shared<mideleg_csr_t>(proc, CSR_MIDELEG); + const reg_t counteren_mask = (proc->extension_enabled_const(EXT_ZICNTR) ? 0x7UL : 0x0) | (proc->extension_enabled_const(EXT_ZIHPM) ? 0xfffffff8ULL : 0x0); + mcounteren = std::make_shared<masked_csr_t>(proc, CSR_MCOUNTEREN, counteren_mask, 0); + if (proc->extension_enabled_const('U')) csrmap[CSR_MCOUNTEREN] = mcounteren; + csrmap[CSR_SCOUNTEREN] = scounteren = std::make_shared<masked_csr_t>(proc, CSR_SCOUNTEREN, counteren_mask, 0); + auto nonvirtual_sepc = std::make_shared<epc_csr_t>(proc, CSR_SEPC); + csrmap[CSR_VSEPC] = vsepc = std::make_shared<epc_csr_t>(proc, CSR_VSEPC); + csrmap[CSR_SEPC] = sepc = std::make_shared<virtualized_csr_t>(proc, nonvirtual_sepc, vsepc); + auto nonvirtual_stval = std::make_shared<basic_csr_t>(proc, CSR_STVAL, 0); + csrmap[CSR_VSTVAL] = vstval = std::make_shared<basic_csr_t>(proc, CSR_VSTVAL, 0); + csrmap[CSR_STVAL] = stval = std::make_shared<virtualized_csr_t>(proc, nonvirtual_stval, vstval); + auto sscratch = std::make_shared<basic_csr_t>(proc, CSR_SSCRATCH, 0); + auto vsscratch = std::make_shared<basic_csr_t>(proc, CSR_VSSCRATCH, 0); + // Note: if max_isa does not include H, we don't really need this virtualized_csr_t at all (though it doesn't hurt): + csrmap[CSR_SSCRATCH] = std::make_shared<virtualized_csr_t>(proc, sscratch, vsscratch); + csrmap[CSR_VSSCRATCH] = vsscratch; + auto nonvirtual_stvec = std::make_shared<tvec_csr_t>(proc, CSR_STVEC); + csrmap[CSR_VSTVEC] = vstvec = std::make_shared<tvec_csr_t>(proc, CSR_VSTVEC); + csrmap[CSR_STVEC] = stvec = std::make_shared<virtualized_csr_t>(proc, nonvirtual_stvec, vstvec); + auto nonvirtual_satp = std::make_shared<satp_csr_t>(proc, CSR_SATP); + csrmap[CSR_VSATP] = vsatp = std::make_shared<base_atp_csr_t>(proc, CSR_VSATP); + csrmap[CSR_SATP] = satp = std::make_shared<virtualized_satp_csr_t>(proc, nonvirtual_satp, vsatp); + auto nonvirtual_scause = std::make_shared<cause_csr_t>(proc, CSR_SCAUSE); + csrmap[CSR_VSCAUSE] = vscause = std::make_shared<cause_csr_t>(proc, CSR_VSCAUSE); + csrmap[CSR_SCAUSE] = scause = std::make_shared<virtualized_csr_t>(proc, nonvirtual_scause, vscause); + csrmap[CSR_MTVAL2] = mtval2 = std::make_shared<hypervisor_csr_t>(proc, CSR_MTVAL2); + csrmap[CSR_MTINST] = mtinst = std::make_shared<hypervisor_csr_t>(proc, CSR_MTINST); + const reg_t hstatus_init = set_field((reg_t)0, HSTATUS_VSXL, xlen_to_uxl(proc->get_const_xlen())); + const reg_t hstatus_mask = HSTATUS_VTSR | HSTATUS_VTW + | (proc->supports_impl(IMPL_MMU) ? HSTATUS_VTVM : 0) + | HSTATUS_HU | HSTATUS_SPVP | HSTATUS_SPV | HSTATUS_GVA; + csrmap[CSR_HSTATUS] = hstatus = std::make_shared<masked_csr_t>(proc, CSR_HSTATUS, hstatus_mask, hstatus_init); + csrmap[CSR_HGEIE] = std::make_shared<const_csr_t>(proc, CSR_HGEIE, 0); + csrmap[CSR_HGEIP] = std::make_shared<const_csr_t>(proc, CSR_HGEIP, 0); + csrmap[CSR_HIDELEG] = hideleg = std::make_shared<hideleg_csr_t>(proc, CSR_HIDELEG, mideleg); + const reg_t hedeleg_mask = + (1 << CAUSE_MISALIGNED_FETCH) | + (1 << CAUSE_FETCH_ACCESS) | + (1 << CAUSE_ILLEGAL_INSTRUCTION) | + (1 << CAUSE_BREAKPOINT) | + (1 << CAUSE_MISALIGNED_LOAD) | + (1 << CAUSE_LOAD_ACCESS) | + (1 << CAUSE_MISALIGNED_STORE) | + (1 << CAUSE_STORE_ACCESS) | + (1 << CAUSE_USER_ECALL) | + (1 << CAUSE_FETCH_PAGE_FAULT) | + (1 << CAUSE_LOAD_PAGE_FAULT) | + (1 << CAUSE_STORE_PAGE_FAULT); + csrmap[CSR_HEDELEG] = hedeleg = std::make_shared<masked_csr_t>(proc, CSR_HEDELEG, hedeleg_mask, 0); + csrmap[CSR_HCOUNTEREN] = hcounteren = std::make_shared<masked_csr_t>(proc, CSR_HCOUNTEREN, counteren_mask, 0); + htimedelta = std::make_shared<basic_csr_t>(proc, CSR_HTIMEDELTA, 0); + if (xlen == 32) { + csrmap[CSR_HTIMEDELTA] = std::make_shared<rv32_low_csr_t>(proc, CSR_HTIMEDELTA, htimedelta); + csrmap[CSR_HTIMEDELTAH] = std::make_shared<rv32_high_csr_t>(proc, CSR_HTIMEDELTAH, htimedelta); + } else { + csrmap[CSR_HTIMEDELTA] = htimedelta; + } + csrmap[CSR_HTVAL] = htval = std::make_shared<basic_csr_t>(proc, CSR_HTVAL, 0); + csrmap[CSR_HTINST] = htinst = std::make_shared<basic_csr_t>(proc, CSR_HTINST, 0); + csrmap[CSR_HGATP] = hgatp = std::make_shared<hgatp_csr_t>(proc, CSR_HGATP); + auto nonvirtual_sstatus = std::make_shared<sstatus_proxy_csr_t>(proc, CSR_SSTATUS, mstatus); + csrmap[CSR_VSSTATUS] = vsstatus = std::make_shared<vsstatus_csr_t>(proc, CSR_VSSTATUS); + csrmap[CSR_SSTATUS] = sstatus = std::make_shared<sstatus_csr_t>(proc, nonvirtual_sstatus, vsstatus); + + csrmap[CSR_DPC] = dpc = std::make_shared<dpc_csr_t>(proc, CSR_DPC); + csrmap[CSR_DSCRATCH0] = std::make_shared<debug_mode_csr_t>(proc, CSR_DSCRATCH0); + csrmap[CSR_DSCRATCH1] = std::make_shared<debug_mode_csr_t>(proc, CSR_DSCRATCH1); + csrmap[CSR_DCSR] = dcsr = std::make_shared<dcsr_csr_t>(proc, CSR_DCSR); + + csrmap[CSR_TSELECT] = tselect = std::make_shared<tselect_csr_t>(proc, CSR_TSELECT); + if (proc->get_cfg().trigger_count > 0) { + csrmap[CSR_TDATA1] = std::make_shared<tdata1_csr_t>(proc, CSR_TDATA1); + csrmap[CSR_TDATA2] = tdata2 = std::make_shared<tdata2_csr_t>(proc, CSR_TDATA2); + csrmap[CSR_TDATA3] = std::make_shared<tdata3_csr_t>(proc, CSR_TDATA3); + csrmap[CSR_TINFO] = std::make_shared<tinfo_csr_t>(proc, CSR_TINFO); + } else { + csrmap[CSR_TDATA1] = std::make_shared<const_csr_t>(proc, CSR_TDATA1, 0); + csrmap[CSR_TDATA2] = tdata2 = std::make_shared<const_csr_t>(proc, CSR_TDATA2, 0); + csrmap[CSR_TDATA3] = std::make_shared<const_csr_t>(proc, CSR_TDATA3, 0); + csrmap[CSR_TINFO] = std::make_shared<const_csr_t>(proc, CSR_TINFO, 0); + } + unsigned scontext_length = (xlen == 32 ? 16 : 34); // debug spec suggests 16-bit for RV32 and 34-bit for RV64 + csrmap[CSR_SCONTEXT] = scontext = std::make_shared<masked_csr_t>(proc, CSR_SCONTEXT, (reg_t(1) << scontext_length) - 1, 0); + unsigned hcontext_length = (xlen == 32 ? 6 : 13) + (proc->extension_enabled('H') ? 1 : 0); // debug spec suggest 7-bit (6-bit) for RV32 and 14-bit (13-bit) for RV64 with (without) H extension + csrmap[CSR_HCONTEXT] = std::make_shared<masked_csr_t>(proc, CSR_HCONTEXT, (reg_t(1) << hcontext_length) - 1, 0); + csrmap[CSR_MCONTEXT] = mcontext = std::make_shared<proxy_csr_t>(proc, CSR_MCONTEXT, csrmap[CSR_HCONTEXT]); + debug_mode = false; + single_step = STEP_NONE; + + csrmap[CSR_MSECCFG] = mseccfg = std::make_shared<mseccfg_csr_t>(proc, CSR_MSECCFG); + + for (int i = 0; i < max_pmp; ++i) { + csrmap[CSR_PMPADDR0 + i] = pmpaddr[i] = std::make_shared<pmpaddr_csr_t>(proc, CSR_PMPADDR0 + i); + } + for (int i = 0; i < max_pmp; i += xlen / 8) { + reg_t addr = CSR_PMPCFG0 + i / 4; + csrmap[addr] = std::make_shared<pmpcfg_csr_t>(proc, addr); + } + + csrmap[CSR_FFLAGS] = fflags = std::make_shared<float_csr_t>(proc, CSR_FFLAGS, FSR_AEXC >> FSR_AEXC_SHIFT, 0); + csrmap[CSR_FRM] = frm = std::make_shared<float_csr_t>(proc, CSR_FRM, FSR_RD >> FSR_RD_SHIFT, 0); + assert(FSR_AEXC_SHIFT == 0); // composite_csr_t assumes fflags begins at bit 0 + csrmap[CSR_FCSR] = std::make_shared<composite_csr_t>(proc, CSR_FCSR, frm, fflags, FSR_RD_SHIFT); + + csrmap[CSR_SEED] = std::make_shared<seed_csr_t>(proc, CSR_SEED); + + csrmap[CSR_MARCHID] = std::make_shared<const_csr_t>(proc, CSR_MARCHID, 5); + csrmap[CSR_MIMPID] = std::make_shared<const_csr_t>(proc, CSR_MIMPID, 0); + csrmap[CSR_MVENDORID] = std::make_shared<const_csr_t>(proc, CSR_MVENDORID, 0); + csrmap[CSR_MHARTID] = std::make_shared<const_csr_t>(proc, CSR_MHARTID, proc->get_id()); + csrmap[CSR_MCONFIGPTR] = std::make_shared<const_csr_t>(proc, CSR_MCONFIGPTR, 0); + if (proc->extension_enabled_const('U')) { + const reg_t menvcfg_mask = (proc->extension_enabled(EXT_ZICBOM) ? MENVCFG_CBCFE | MENVCFG_CBIE : 0) | + (proc->extension_enabled(EXT_ZICBOZ) ? MENVCFG_CBZE : 0) | + (proc->extension_enabled(EXT_SVADU) ? MENVCFG_HADE: 0) | + (proc->extension_enabled(EXT_SVPBMT) ? MENVCFG_PBMTE : 0) | + (proc->extension_enabled(EXT_SSTC) ? MENVCFG_STCE : 0); + const reg_t menvcfg_init = (proc->extension_enabled(EXT_SVPBMT) ? MENVCFG_PBMTE : 0); + menvcfg = std::make_shared<masked_csr_t>(proc, CSR_MENVCFG, menvcfg_mask, menvcfg_init); + if (xlen == 32) { + csrmap[CSR_MENVCFG] = std::make_shared<rv32_low_csr_t>(proc, CSR_MENVCFG, menvcfg); + csrmap[CSR_MENVCFGH] = std::make_shared<rv32_high_csr_t>(proc, CSR_MENVCFGH, menvcfg); + } else { + csrmap[CSR_MENVCFG] = menvcfg; + } + const reg_t senvcfg_mask = (proc->extension_enabled(EXT_ZICBOM) ? SENVCFG_CBCFE | SENVCFG_CBIE : 0) | + (proc->extension_enabled(EXT_ZICBOZ) ? SENVCFG_CBZE : 0); + csrmap[CSR_SENVCFG] = senvcfg = std::make_shared<senvcfg_csr_t>(proc, CSR_SENVCFG, senvcfg_mask, 0); + const reg_t henvcfg_mask = (proc->extension_enabled(EXT_ZICBOM) ? HENVCFG_CBCFE | HENVCFG_CBIE : 0) | + (proc->extension_enabled(EXT_ZICBOZ) ? HENVCFG_CBZE : 0) | + (proc->extension_enabled(EXT_SVADU) ? HENVCFG_HADE: 0) | + (proc->extension_enabled(EXT_SVPBMT) ? HENVCFG_PBMTE : 0) | + (proc->extension_enabled(EXT_SSTC) ? HENVCFG_STCE : 0); + const reg_t henvcfg_init = (proc->extension_enabled(EXT_SVPBMT) ? HENVCFG_PBMTE : 0); + henvcfg = std::make_shared<henvcfg_csr_t>(proc, CSR_HENVCFG, henvcfg_mask, henvcfg_init, menvcfg); + if (xlen == 32) { + csrmap[CSR_HENVCFG] = std::make_shared<rv32_low_csr_t>(proc, CSR_HENVCFG, henvcfg); + csrmap[CSR_HENVCFGH] = std::make_shared<rv32_high_csr_t>(proc, CSR_HENVCFGH, henvcfg); + } else { + csrmap[CSR_HENVCFG] = henvcfg; + } + } + if (proc->extension_enabled_const(EXT_SMSTATEEN)) { + const reg_t sstateen0_mask = (proc->extension_enabled(EXT_ZFINX) ? SSTATEEN0_FCSR : 0) | + (proc->extension_enabled(EXT_ZCMT) ? SSTATEEN0_JVT : 0) | + SSTATEEN0_CS; + const reg_t hstateen0_mask = sstateen0_mask | HSTATEEN0_SENVCFG | HSTATEEN_SSTATEEN; + const reg_t mstateen0_mask = hstateen0_mask; + for (int i = 0; i < 4; i++) { + const reg_t mstateen_mask = i == 0 ? mstateen0_mask : MSTATEEN_HSTATEEN; + mstateen[i] = std::make_shared<masked_csr_t>(proc, CSR_MSTATEEN0 + i, mstateen_mask, 0); + if (xlen == 32) { + csrmap[CSR_MSTATEEN0 + i] = std::make_shared<rv32_low_csr_t>(proc, CSR_MSTATEEN0 + i, mstateen[i]); + csrmap[CSR_MSTATEEN0H + i] = std::make_shared<rv32_high_csr_t>(proc, CSR_MSTATEEN0H + i, mstateen[i]); + } else { + csrmap[CSR_MSTATEEN0 + i] = mstateen[i]; + } + + const reg_t hstateen_mask = i == 0 ? hstateen0_mask : HSTATEEN_SSTATEEN; + hstateen[i] = std::make_shared<hstateen_csr_t>(proc, CSR_HSTATEEN0 + i, hstateen_mask, 0, i); + if (xlen == 32) { + csrmap[CSR_HSTATEEN0 + i] = std::make_shared<rv32_low_csr_t>(proc, CSR_HSTATEEN0 + i, hstateen[i]); + csrmap[CSR_HSTATEEN0H + i] = std::make_shared<rv32_high_csr_t>(proc, CSR_HSTATEEN0H + i, hstateen[i]); + } else { + csrmap[CSR_HSTATEEN0 + i] = hstateen[i]; + } + + const reg_t sstateen_mask = i == 0 ? sstateen0_mask : 0; + csrmap[CSR_SSTATEEN0 + i] = sstateen[i] = std::make_shared<sstateen_csr_t>(proc, CSR_HSTATEEN0 + i, sstateen_mask, 0, i); + } + } + + if (proc->extension_enabled_const(EXT_SMRNMI)) { + csrmap[CSR_MNSCRATCH] = std::make_shared<basic_csr_t>(proc, CSR_MNSCRATCH, 0); + csrmap[CSR_MNEPC] = mnepc = std::make_shared<epc_csr_t>(proc, CSR_MNEPC); + csrmap[CSR_MNCAUSE] = std::make_shared<const_csr_t>(proc, CSR_MNCAUSE, (reg_t)1 << (xlen - 1)); + csrmap[CSR_MNSTATUS] = mnstatus = std::make_shared<mnstatus_csr_t>(proc, CSR_MNSTATUS); + } + + if (proc->extension_enabled_const(EXT_SSTC)) { + stimecmp = std::make_shared<stimecmp_csr_t>(proc, CSR_STIMECMP, MIP_STIP); + vstimecmp = std::make_shared<stimecmp_csr_t>(proc, CSR_VSTIMECMP, MIP_VSTIP); + auto virtualized_stimecmp = std::make_shared<virtualized_stimecmp_csr_t>(proc, stimecmp, vstimecmp); + if (xlen == 32) { + csrmap[CSR_STIMECMP] = std::make_shared<rv32_low_csr_t>(proc, CSR_STIMECMP, virtualized_stimecmp); + csrmap[CSR_STIMECMPH] = std::make_shared<rv32_high_csr_t>(proc, CSR_STIMECMPH, virtualized_stimecmp); + csrmap[CSR_VSTIMECMP] = std::make_shared<rv32_low_csr_t>(proc, CSR_VSTIMECMP, vstimecmp); + csrmap[CSR_VSTIMECMPH] = std::make_shared<rv32_high_csr_t>(proc, CSR_VSTIMECMPH, vstimecmp); + } else { + csrmap[CSR_STIMECMP] = virtualized_stimecmp; + csrmap[CSR_VSTIMECMP] = vstimecmp; + } + } + + if (proc->extension_enabled(EXT_ZCMT)) + csrmap[CSR_JVT] = jvt = std::make_shared<jvt_csr_t>(proc, CSR_JVT, 0); + + serialized = false; + + log_reg_write.clear(); + log_mem_read.clear(); + log_mem_write.clear(); + last_inst_priv = 0; + last_inst_xlen = 0; + last_inst_flen = 0; +} + +void processor_t::set_debug(bool value) +{ + debug = value; + + for (auto e : custom_extensions) + e.second->set_debug(value); +} + +void processor_t::set_histogram(bool value) +{ + histogram_enabled = value; +} + +void processor_t::enable_log_commits() +{ + log_commits_enabled = true; +} + +void processor_t::reset() +{ + xlen = isa->get_max_xlen(); + state.reset(this, isa->get_max_isa()); + state.dcsr->halt = halt_on_reset; + halt_on_reset = false; + VU.reset(); + in_wfi = false; + + if (n_pmp > 0) { + // For backwards compatibility with software that is unaware of PMP, + // initialize PMP to permit unprivileged access to all of memory. + put_csr(CSR_PMPADDR0, ~reg_t(0)); + put_csr(CSR_PMPCFG0, PMP_R | PMP_W | PMP_X | PMP_NAPOT); + } + + for (auto e : custom_extensions) // reset any extensions + e.second->reset(); + + if (sim) + sim->proc_reset(id); +} + +extension_t* processor_t::get_extension() +{ + switch (custom_extensions.size()) { + case 0: return NULL; + case 1: return custom_extensions.begin()->second; + default: + fprintf(stderr, "processor_t::get_extension() is ambiguous when multiple extensions\n"); + fprintf(stderr, "are present!\n"); + abort(); + } +} + +extension_t* processor_t::get_extension(const char* name) +{ + auto it = custom_extensions.find(name); + if (it == custom_extensions.end()) + abort(); + return it->second; +} + +void processor_t::set_pmp_num(reg_t n) +{ + // check the number of pmp is in a reasonable range + if (n > state.max_pmp) { + fprintf(stderr, "error: number of PMP regions requested (%" PRIu64 ") exceeds maximum (%d)\n", n, state.max_pmp); + abort(); + } + n_pmp = n; +} + +void processor_t::set_pmp_granularity(reg_t gran) +{ + // check the pmp granularity is set from dtb(!=0) and is power of 2 + unsigned min = 1 << PMP_SHIFT; + if (gran < min || (gran & (gran - 1)) != 0) { + fprintf(stderr, "error: PMP granularity (%" PRIu64 ") must be a power of two and at least %u\n", gran, min); + abort(); + } + + lg_pmp_granularity = ctz(gran); +} + +void processor_t::set_mmu_capability(int cap) +{ + switch (cap) { + case IMPL_MMU_SV32: + set_impl(IMPL_MMU_SV32, true); + set_impl(IMPL_MMU, true); + break; + case IMPL_MMU_SV57: + set_impl(IMPL_MMU_SV57, true); + // Fall through + case IMPL_MMU_SV48: + set_impl(IMPL_MMU_SV48, true); + // Fall through + case IMPL_MMU_SV39: + set_impl(IMPL_MMU_SV39, true); + set_impl(IMPL_MMU, true); + break; + default: + set_impl(IMPL_MMU_SV32, false); + set_impl(IMPL_MMU_SV39, false); + set_impl(IMPL_MMU_SV48, false); + set_impl(IMPL_MMU_SV57, false); + set_impl(IMPL_MMU, false); + break; + } +} + +void processor_t::take_interrupt(reg_t pending_interrupts) +{ + // Do nothing if no pending interrupts + if (!pending_interrupts) { + return; + } + + // Exit WFI if there are any pending interrupts + in_wfi = false; + + // M-ints have higher priority over HS-ints and VS-ints + const reg_t mie = get_field(state.mstatus->read(), MSTATUS_MIE); + const reg_t m_enabled = state.prv < PRV_M || (state.prv == PRV_M && mie); + reg_t enabled_interrupts = pending_interrupts & ~state.mideleg->read() & -m_enabled; + if (enabled_interrupts == 0) { + // HS-ints have higher priority over VS-ints + const reg_t deleg_to_hs = state.mideleg->read() & ~state.hideleg->read(); + const reg_t sie = get_field(state.sstatus->read(), MSTATUS_SIE); + const reg_t hs_enabled = state.v || state.prv < PRV_S || (state.prv == PRV_S && sie); + enabled_interrupts = pending_interrupts & deleg_to_hs & -hs_enabled; + if (state.v && enabled_interrupts == 0) { + // VS-ints have least priority and can only be taken with virt enabled + const reg_t deleg_to_vs = state.hideleg->read(); + const reg_t vs_enabled = state.prv < PRV_S || (state.prv == PRV_S && sie); + enabled_interrupts = pending_interrupts & deleg_to_vs & -vs_enabled; + } + } + + const bool nmie = !(state.mnstatus && !get_field(state.mnstatus->read(), MNSTATUS_NMIE)); + if (!state.debug_mode && nmie && enabled_interrupts) { + // nonstandard interrupts have highest priority + if (enabled_interrupts >> (IRQ_M_EXT + 1)) + enabled_interrupts = enabled_interrupts >> (IRQ_M_EXT + 1) << (IRQ_M_EXT + 1); + // standard interrupt priority is MEI, MSI, MTI, SEI, SSI, STI + else if (enabled_interrupts & MIP_MEIP) + enabled_interrupts = MIP_MEIP; + else if (enabled_interrupts & MIP_MSIP) + enabled_interrupts = MIP_MSIP; + else if (enabled_interrupts & MIP_MTIP) + enabled_interrupts = MIP_MTIP; + else if (enabled_interrupts & MIP_SEIP) + enabled_interrupts = MIP_SEIP; + else if (enabled_interrupts & MIP_SSIP) + enabled_interrupts = MIP_SSIP; + else if (enabled_interrupts & MIP_STIP) + enabled_interrupts = MIP_STIP; + else if (enabled_interrupts & MIP_LCOFIP) + enabled_interrupts = MIP_LCOFIP; + else if (enabled_interrupts & MIP_VSEIP) + enabled_interrupts = MIP_VSEIP; + else if (enabled_interrupts & MIP_VSSIP) + enabled_interrupts = MIP_VSSIP; + else if (enabled_interrupts & MIP_VSTIP) + enabled_interrupts = MIP_VSTIP; + else + abort(); + + if (check_triggers_icount) TM.detect_icount_match(); + throw trap_t(((reg_t)1 << (isa->get_max_xlen() - 1)) | ctz(enabled_interrupts)); + } +} + +reg_t processor_t::legalize_privilege(reg_t prv) +{ + assert(prv <= PRV_M); + + if (!extension_enabled('U')) + return PRV_M; + + if (prv == PRV_HS || (prv == PRV_S && !extension_enabled('S'))) + return PRV_U; + + return prv; +} + +void processor_t::set_privilege(reg_t prv) +{ + mmu->flush_tlb(); + state.prv = legalize_privilege(prv); +} + +const char* processor_t::get_privilege_string() +{ + if (state.debug_mode) + return "D"; + if (state.v) { + switch (state.prv) { + case 0x0: return "VU"; + case 0x1: return "VS"; + } + } else { + switch (state.prv) { + case 0x0: return "U"; + case 0x1: return "S"; + case 0x3: return "M"; + } + } + fprintf(stderr, "Invalid prv=%lx v=%x\n", (unsigned long)state.prv, state.v); + abort(); +} + +void processor_t::set_virt(bool virt) +{ + reg_t tmp, mask; + + if (state.prv == PRV_M) + return; + + if (state.v != virt) { + /* + * Ideally, we should flush TLB here but we don't need it because + * set_virt() is always used in conjucter with set_privilege() and + * set_privilege() will flush TLB unconditionally. + * + * The virtualized sstatus register also relies on this TLB flush, + * since changing V might change sstatus.MXR and sstatus.SUM. + */ + state.v = virt; + } +} + +void processor_t::enter_debug_mode(uint8_t cause) +{ + state.debug_mode = true; + state.dcsr->write_cause_and_prv(cause, state.prv); + set_privilege(PRV_M); + state.dpc->write(state.pc); + state.pc = DEBUG_ROM_ENTRY; + in_wfi = false; +} + +void processor_t::debug_output_log(std::stringstream *s) +{ + if (log_file == stderr) { + std::ostream out(sout_.rdbuf()); + out << s->str(); // handles command line options -d -s -l + } else { + fputs(s->str().c_str(), log_file); // handles command line option --log + } +} + +void processor_t::take_trap(trap_t& t, reg_t epc) +{ + unsigned max_xlen = isa->get_max_xlen(); + + if (debug) { + std::stringstream s; // first put everything in a string, later send it to output + s << "core " << std::dec << std::setfill(' ') << std::setw(3) << id + << ": exception " << t.name() << ", epc 0x" + << std::hex << std::setfill('0') << std::setw(max_xlen/4) << zext(epc, max_xlen) << std::endl; + if (t.has_tval()) + s << "core " << std::dec << std::setfill(' ') << std::setw(3) << id + << ": tval 0x" << std::hex << std::setfill('0') << std::setw(max_xlen / 4) + << zext(t.get_tval(), max_xlen) << std::endl; + debug_output_log(&s); + } + + if (state.debug_mode) { + if (t.cause() == CAUSE_BREAKPOINT) { + state.pc = DEBUG_ROM_ENTRY; + } else { + state.pc = DEBUG_ROM_TVEC; + } + return; + } + + // By default, trap to M-mode, unless delegated to HS-mode or VS-mode + reg_t vsdeleg, hsdeleg; + reg_t bit = t.cause(); + bool curr_virt = state.v; + bool interrupt = (bit & ((reg_t)1 << (max_xlen - 1))) != 0; + if (interrupt) { + vsdeleg = (curr_virt && state.prv <= PRV_S) ? state.hideleg->read() : 0; + hsdeleg = (state.prv <= PRV_S) ? state.mideleg->read() : 0; + bit &= ~((reg_t)1 << (max_xlen - 1)); + } else { + vsdeleg = (curr_virt && state.prv <= PRV_S) ? (state.medeleg->read() & state.hedeleg->read()) : 0; + hsdeleg = (state.prv <= PRV_S) ? state.medeleg->read() : 0; + } + if (state.prv <= PRV_S && bit < max_xlen && ((vsdeleg >> bit) & 1)) { + // Handle the trap in VS-mode + reg_t vector = (state.vstvec->read() & 1) && interrupt ? 4 * bit : 0; + state.pc = (state.vstvec->read() & ~(reg_t)1) + vector; + state.vscause->write((interrupt) ? (t.cause() - 1) : t.cause()); + state.vsepc->write(epc); + state.vstval->write(t.get_tval()); + + reg_t s = state.sstatus->read(); + s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE)); + s = set_field(s, MSTATUS_SPP, state.prv); + s = set_field(s, MSTATUS_SIE, 0); + state.sstatus->write(s); + set_privilege(PRV_S); + } else if (state.prv <= PRV_S && bit < max_xlen && ((hsdeleg >> bit) & 1)) { + // Handle the trap in HS-mode + set_virt(false); + reg_t vector = (state.stvec->read() & 1) && interrupt ? 4 * bit : 0; + state.pc = (state.stvec->read() & ~(reg_t)1) + vector; + state.scause->write(t.cause()); + state.sepc->write(epc); + state.stval->write(t.get_tval()); + state.htval->write(t.get_tval2()); + state.htinst->write(t.get_tinst()); + + reg_t s = state.sstatus->read(); + s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE)); + s = set_field(s, MSTATUS_SPP, state.prv); + s = set_field(s, MSTATUS_SIE, 0); + state.sstatus->write(s); + if (extension_enabled('H')) { + s = state.hstatus->read(); + if (curr_virt) + s = set_field(s, HSTATUS_SPVP, state.prv); + s = set_field(s, HSTATUS_SPV, curr_virt); + s = set_field(s, HSTATUS_GVA, t.has_gva()); + state.hstatus->write(s); + } + set_privilege(PRV_S); + } else { + // Handle the trap in M-mode + set_virt(false); + const reg_t vector = (state.mtvec->read() & 1) && interrupt ? 4 * bit : 0; + const reg_t trap_handler_address = (state.mtvec->read() & ~(reg_t)1) + vector; + // RNMI exception vector is implementation-defined. Since we don't model + // RNMI sources, the feature isn't very useful, so pick an invalid address. + const reg_t rnmi_trap_handler_address = 0; + const bool nmie = !(state.mnstatus && !get_field(state.mnstatus->read(), MNSTATUS_NMIE)); + state.pc = !nmie ? rnmi_trap_handler_address : trap_handler_address; + state.mepc->write(epc); + state.mcause->write(t.cause()); + state.mtval->write(t.get_tval()); + state.mtval2->write(t.get_tval2()); + state.mtinst->write(t.get_tinst()); + + reg_t s = state.mstatus->read(); + s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE)); + s = set_field(s, MSTATUS_MPP, state.prv); + s = set_field(s, MSTATUS_MIE, 0); + s = set_field(s, MSTATUS_MPV, curr_virt); + s = set_field(s, MSTATUS_GVA, t.has_gva()); + state.mstatus->write(s); + if (state.mstatush) state.mstatush->write(s >> 32); // log mstatush change + set_privilege(PRV_M); + } +} + +void processor_t::take_trigger_action(triggers::action_t action, reg_t breakpoint_tval, reg_t epc) +{ + if (debug) { + std::stringstream s; // first put everything in a string, later send it to output + s << "core " << std::dec << std::setfill(' ') << std::setw(3) << id + << ": trigger action " << (int)action << std::endl; + debug_output_log(&s); + } + + switch (action) { + case triggers::ACTION_DEBUG_MODE: + enter_debug_mode(DCSR_CAUSE_HWBP); + break; + case triggers::ACTION_DEBUG_EXCEPTION: { + trap_breakpoint trap(state.v, breakpoint_tval); + take_trap(trap, epc); + break; + } + default: + abort(); + } +} + +const char* processor_t::get_symbol(uint64_t addr) +{ + return sim->get_symbol(addr); +} + +void processor_t::disasm(insn_t insn) +{ + uint64_t bits = insn.bits(); + if (last_pc != state.pc || last_bits != bits) { + std::stringstream s; // first put everything in a string, later send it to output + + const char* sym = get_symbol(state.pc); + if (sym != nullptr) + { + s << "core " << std::dec << std::setfill(' ') << std::setw(3) << id + << ": >>>> " << sym << std::endl; + } + + if (executions != 1) { + s << "core " << std::dec << std::setfill(' ') << std::setw(3) << id + << ": Executed " << executions << " times" << std::endl; + } + + unsigned max_xlen = isa->get_max_xlen(); + + s << "core " << std::dec << std::setfill(' ') << std::setw(3) << id + << std::hex << ": 0x" << std::setfill('0') << std::setw(max_xlen / 4) + << zext(state.pc, max_xlen) << " (0x" << std::setw(8) << bits << ") " + << disassembler->disassemble(insn) << std::endl; + + debug_output_log(&s); + + last_pc = state.pc; + last_bits = bits; + executions = 1; + } else { + executions++; + } +} + +int processor_t::paddr_bits() +{ + unsigned max_xlen = isa->get_max_xlen(); + assert(xlen == max_xlen); + return max_xlen == 64 ? 50 : 34; +} + +void processor_t::put_csr(int which, reg_t val) +{ + val = zext_xlen(val); + auto search = state.csrmap.find(which); + if (search != state.csrmap.end()) { + search->second->write(val); + return; + } +} + +// Note that get_csr is sometimes called when read side-effects should not +// be actioned. In other words, Spike cannot currently support CSRs with +// side effects on reads. +reg_t processor_t::get_csr(int which, insn_t insn, bool write, bool peek) +{ + auto search = state.csrmap.find(which); + if (search != state.csrmap.end()) { + if (!peek) + search->second->verify_permissions(insn, write); + return search->second->read(); + } + // If we get here, the CSR doesn't exist. Unimplemented CSRs always throw + // illegal-instruction exceptions, not virtual-instruction exceptions. + throw trap_illegal_instruction(insn.bits()); +} + +reg_t illegal_instruction(processor_t UNUSED *p, insn_t insn, reg_t UNUSED pc) +{ + // The illegal instruction can be longer than ILEN bits, where the tval will + // contain the first ILEN bits of the faulting instruction. We hard-code the + // ILEN to 32 bits since all official instructions have at most 32 bits. + throw trap_illegal_instruction(insn.bits() & 0xffffffffULL); +} + +insn_func_t processor_t::decode_insn(insn_t insn) +{ + // look up opcode in hash table + size_t idx = insn.bits() % OPCODE_CACHE_SIZE; + insn_desc_t desc = opcode_cache[idx]; + + bool rve = extension_enabled('E'); + + if (unlikely(insn.bits() != desc.match)) { + // fall back to linear search + int cnt = 0; + insn_desc_t* p = &instructions[0]; + while ((insn.bits() & p->mask) != p->match) + p++, cnt++; + desc = *p; + + if (p->mask != 0 && p > &instructions[0]) { + if (p->match != (p - 1)->match && p->match != (p + 1)->match) { + // move to front of opcode list to reduce miss penalty + while (--p >= &instructions[0]) + *(p + 1) = *p; + instructions[0] = desc; + } + } + + opcode_cache[idx] = desc; + opcode_cache[idx].match = insn.bits(); + } + + return desc.func(xlen, rve, log_commits_enabled); +} + +void processor_t::register_insn(insn_desc_t desc) +{ + assert(desc.fast_rv32i && desc.fast_rv64i && desc.fast_rv32e && desc.fast_rv64e && + desc.logged_rv32i && desc.logged_rv64i && desc.logged_rv32e && desc.logged_rv64e); + + instructions.push_back(desc); +} + +void processor_t::build_opcode_map() +{ + struct cmp { + bool operator()(const insn_desc_t& lhs, const insn_desc_t& rhs) { + if (lhs.match == rhs.match) + return lhs.mask > rhs.mask; + return lhs.match > rhs.match; + } + }; + std::sort(instructions.begin(), instructions.end(), cmp()); + + for (size_t i = 0; i < OPCODE_CACHE_SIZE; i++) + opcode_cache[i] = insn_desc_t::illegal(); +} + +void processor_t::register_extension(extension_t* x) +{ + for (auto insn : x->get_instructions()) + register_insn(insn); + build_opcode_map(); + + for (auto disasm_insn : x->get_disasms()) + disassembler->add_insn(disasm_insn); + + if (!custom_extensions.insert(std::make_pair(x->name(), x)).second) { + fprintf(stderr, "extensions must have unique names (got two named \"%s\"!)\n", x->name()); + abort(); + } + x->set_processor(this); +} + +void processor_t::register_base_instructions() +{ + #define DECLARE_INSN(name, match, mask) \ + insn_bits_t name##_match = (match), name##_mask = (mask); \ + bool name##_supported = true; + + #include "encoding.h" + #undef DECLARE_INSN + + #define DECLARE_OVERLAP_INSN(name, ext) { name##_supported = isa->extension_enabled(ext); } + #include "overlap_list.h" + #undef DECLARE_OVERLAP_INSN + + #define DEFINE_INSN(name) \ + extern reg_t fast_rv32i_##name(processor_t*, insn_t, reg_t); \ + extern reg_t fast_rv64i_##name(processor_t*, insn_t, reg_t); \ + extern reg_t fast_rv32e_##name(processor_t*, insn_t, reg_t); \ + extern reg_t fast_rv64e_##name(processor_t*, insn_t, reg_t); \ + extern reg_t logged_rv32i_##name(processor_t*, insn_t, reg_t); \ + extern reg_t logged_rv64i_##name(processor_t*, insn_t, reg_t); \ + extern reg_t logged_rv32e_##name(processor_t*, insn_t, reg_t); \ + extern reg_t logged_rv64e_##name(processor_t*, insn_t, reg_t); \ + if (name##_supported) { \ + register_insn((insn_desc_t) { \ + name##_match, \ + name##_mask, \ + fast_rv32i_##name, \ + fast_rv64i_##name, \ + fast_rv32e_##name, \ + fast_rv64e_##name, \ + logged_rv32i_##name, \ + logged_rv64i_##name, \ + logged_rv32e_##name, \ + logged_rv64e_##name}); \ + } + #include "insn_list.h" + #undef DEFINE_INSN + + // terminate instruction list with a catch-all + register_insn(insn_desc_t::illegal()); + + build_opcode_map(); +} + +bool processor_t::load(reg_t addr, size_t len, uint8_t* bytes) +{ + switch (addr) + { + case 0: + if (len <= 4) { + memset(bytes, 0, len); + bytes[0] = get_field(state.mip->read(), MIP_MSIP); + return true; + } + break; + } + + return false; +} + +bool processor_t::store(reg_t addr, size_t len, const uint8_t* bytes) +{ + switch (addr) + { + case 0: + if (len <= 4) { + state.mip->write_with_mask(MIP_MSIP, bytes[0] << IRQ_M_SOFT); + return true; + } + break; + } + + return false; +} + +void processor_t::trigger_updated(const std::vector<triggers::trigger_t *> &triggers) +{ + mmu->flush_tlb(); + mmu->check_triggers_fetch = false; + mmu->check_triggers_load = false; + mmu->check_triggers_store = false; + check_triggers_icount = false; + + for (auto trigger : triggers) { + if (trigger->get_execute()) { + mmu->check_triggers_fetch = true; + } + if (trigger->get_load()) { + mmu->check_triggers_load = true; + } + if (trigger->get_store()) { + mmu->check_triggers_store = true; + } + if (trigger->icount_check_needed()) { + check_triggers_icount = true; + } + } +} diff --git a/vendor/riscv/riscv-isa-sim/riscv/processor.h b/vendor/riscv/riscv-isa-sim/riscv/processor.h new file mode 100644 index 0000000000..2f7b8bbfaa --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/processor.h @@ -0,0 +1,369 @@ +// See LICENSE for license details. +#ifndef _RISCV_PROCESSOR_H +#define _RISCV_PROCESSOR_H + +#include "decode.h" +#include "trap.h" +#include "abstract_device.h" +#include <string> +#include <vector> +#include <unordered_map> +#include <map> +#include <cassert> +#include "debug_rom_defines.h" +#include "entropy_source.h" +#include "csrs.h" +#include "isa_parser.h" +#include "triggers.h" +#include "../fesvr/memif.h" +#include "vector_unit.h" + +#define N_HPMCOUNTERS 29 + +class processor_t; +class mmu_t; +typedef reg_t (*insn_func_t)(processor_t*, insn_t, reg_t); +class simif_t; +class trap_t; +class extension_t; +class disassembler_t; + +reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc); + +struct insn_desc_t +{ + insn_bits_t match; + insn_bits_t mask; + insn_func_t fast_rv32i; + insn_func_t fast_rv64i; + insn_func_t fast_rv32e; + insn_func_t fast_rv64e; + insn_func_t logged_rv32i; + insn_func_t logged_rv64i; + insn_func_t logged_rv32e; + insn_func_t logged_rv64e; + + insn_func_t func(int xlen, bool rve, bool logged) + { + if (logged) + if (rve) + return xlen == 64 ? logged_rv64e : logged_rv32e; + else + return xlen == 64 ? logged_rv64i : logged_rv32i; + else + if (rve) + return xlen == 64 ? fast_rv64e : fast_rv32e; + else + return xlen == 64 ? fast_rv64i : fast_rv32i; + } + + static insn_desc_t illegal() + { + return {0, 0, + &illegal_instruction, &illegal_instruction, &illegal_instruction, &illegal_instruction, + &illegal_instruction, &illegal_instruction, &illegal_instruction, &illegal_instruction}; + } +}; + +// regnum, data +typedef std::unordered_map<reg_t, freg_t> commit_log_reg_t; + +// addr, value, size +typedef std::vector<std::tuple<reg_t, uint64_t, uint8_t>> commit_log_mem_t; + +// architectural state of a RISC-V hart +struct state_t +{ + void reset(processor_t* const proc, reg_t max_isa); + + reg_t pc; + regfile_t<reg_t, NXPR, true> XPR; + regfile_t<freg_t, NFPR, false> FPR; + + // control and status registers + std::unordered_map<reg_t, csr_t_p> csrmap; + reg_t prv; // TODO: Can this be an enum instead? + bool v; + misa_csr_t_p misa; + mstatus_csr_t_p mstatus; + csr_t_p mstatush; + csr_t_p mepc; + csr_t_p mtval; + csr_t_p mtvec; + csr_t_p mcause; + wide_counter_csr_t_p minstret; + wide_counter_csr_t_p mcycle; + mie_csr_t_p mie; + mip_csr_t_p mip; + csr_t_p medeleg; + csr_t_p mideleg; + csr_t_p mcounteren; + csr_t_p mevent[N_HPMCOUNTERS]; + csr_t_p mnstatus; + csr_t_p mnepc; + csr_t_p scounteren; + csr_t_p sepc; + csr_t_p stval; + csr_t_p stvec; + virtualized_csr_t_p satp; + csr_t_p scause; + + csr_t_p mtval2; + csr_t_p mtinst; + csr_t_p hstatus; + csr_t_p hideleg; + csr_t_p hedeleg; + csr_t_p hcounteren; + csr_t_p htval; + csr_t_p htinst; + csr_t_p hgatp; + sstatus_csr_t_p sstatus; + vsstatus_csr_t_p vsstatus; + csr_t_p vstvec; + csr_t_p vsepc; + csr_t_p vscause; + csr_t_p vstval; + csr_t_p vsatp; + + csr_t_p dpc; + dcsr_csr_t_p dcsr; + csr_t_p tselect; + csr_t_p tdata2; + csr_t_p scontext; + csr_t_p mcontext; + + csr_t_p jvt; + + bool debug_mode; + + mseccfg_csr_t_p mseccfg; + + static const int max_pmp = 64; + pmpaddr_csr_t_p pmpaddr[max_pmp]; + + float_csr_t_p fflags; + float_csr_t_p frm; + + csr_t_p menvcfg; + csr_t_p senvcfg; + csr_t_p henvcfg; + + csr_t_p mstateen[4]; + csr_t_p sstateen[4]; + csr_t_p hstateen[4]; + + csr_t_p htimedelta; + time_counter_csr_t_p time; + csr_t_p time_proxy; + + csr_t_p stimecmp; + csr_t_p vstimecmp; + + bool serialized; // whether timer CSRs are in a well-defined state + + // When true, execute a single instruction and then enter debug mode. This + // can only be set by executing dret. + enum { + STEP_NONE, + STEP_STEPPING, + STEP_STEPPED + } single_step; + + commit_log_reg_t log_reg_write; + commit_log_mem_t log_mem_read; + commit_log_mem_t log_mem_write; + reg_t last_inst_priv; + int last_inst_xlen; + int last_inst_flen; +}; + +// this class represents one processor in a RISC-V machine. +class processor_t : public abstract_device_t +{ +public: + processor_t(const isa_parser_t *isa, const cfg_t* cfg, + simif_t* sim, uint32_t id, bool halt_on_reset, + FILE *log_file, std::ostream& sout_); // because of command line option --log and -s we need both + ~processor_t(); + + const isa_parser_t &get_isa() { return *isa; } + const cfg_t &get_cfg() { return *cfg; } + + void set_debug(bool value); + void set_histogram(bool value); + void enable_log_commits(); + bool get_log_commits_enabled() const { return log_commits_enabled; } + void reset(); + void step(size_t n); // run for n cycles + void put_csr(int which, reg_t val); + uint32_t get_id() const { return id; } + reg_t get_csr(int which, insn_t insn, bool write, bool peek = 0); + reg_t get_csr(int which) { return get_csr(which, insn_t(0), false, true); } + mmu_t* get_mmu() { return mmu; } + state_t* get_state() { return &state; } + unsigned get_xlen() const { return xlen; } + unsigned get_const_xlen() const { + // Any code that assumes a const xlen should use this method to + // document that assumption. If Spike ever changes to allow + // variable xlen, this method should be removed. + return xlen; + } + unsigned get_flen() const { + return extension_enabled('Q') ? 128 : + extension_enabled('D') ? 64 : + extension_enabled('F') ? 32 : 0; + } + extension_t* get_extension(); + extension_t* get_extension(const char* name); + bool any_custom_extensions() const { + return !custom_extensions.empty(); + } + bool extension_enabled(unsigned char ext) const { + return extension_enabled(isa_extension_t(ext)); + } + bool extension_enabled(isa_extension_t ext) const { + if (ext >= 'A' && ext <= 'Z') + return state.misa->extension_enabled(ext); + else + return extension_enable_table[ext]; + } + // Is this extension enabled? and abort if this extension can + // possibly be disabled dynamically. Useful for documenting + // assumptions about writable misa bits. + bool extension_enabled_const(unsigned char ext) const { + return extension_enabled_const(isa_extension_t(ext)); + } + bool extension_enabled_const(isa_extension_t ext) const { + if (ext >= 'A' && ext <= 'Z') { + return state.misa->extension_enabled_const(ext); + } else { + assert(!extension_dynamic[ext]); + extension_assumed_const[ext] = true; + return extension_enabled(ext); + } + } + void set_extension_enable(unsigned char ext, bool enable) { + assert(!extension_assumed_const[ext]); + extension_dynamic[ext] = true; + extension_enable_table[ext] = enable && isa->extension_enabled(ext); + } + void set_impl(uint8_t impl, bool val) { impl_table[impl] = val; } + bool supports_impl(uint8_t impl) const { + return impl_table[impl]; + } + reg_t pc_alignment_mask() { + const int ialign = extension_enabled(EXT_ZCA) ? 16 : 32; + return ~(reg_t)(ialign == 16 ? 0 : 2); + } + void check_pc_alignment(reg_t pc) { + if (unlikely(pc & ~pc_alignment_mask())) + throw trap_instruction_address_misaligned(state.v, pc, 0, 0); + } + reg_t legalize_privilege(reg_t); + void set_privilege(reg_t); + void set_virt(bool); + const char* get_privilege_string(); + void update_histogram(reg_t pc); + const disassembler_t* get_disassembler() { return disassembler; } + + FILE *get_log_file() { return log_file; } + + void register_insn(insn_desc_t); + void register_extension(extension_t*); + + // MMIO slave interface + bool load(reg_t addr, size_t len, uint8_t* bytes); + bool store(reg_t addr, size_t len, const uint8_t* bytes); + + // When true, display disassembly of each instruction that's executed. + bool debug; + // When true, take the slow simulation path. + bool slow_path(); + bool halted() { return state.debug_mode; } + enum { + HR_NONE, /* Halt request is inactive. */ + HR_REGULAR, /* Regular halt request/debug interrupt. */ + HR_GROUP /* Halt requested due to halt group. */ + } halt_request; + + void trigger_updated(const std::vector<triggers::trigger_t *> &triggers); + + void set_pmp_num(reg_t pmp_num); + void set_pmp_granularity(reg_t pmp_granularity); + void set_mmu_capability(int cap); + + const char* get_symbol(uint64_t addr); + + void clear_waiting_for_interrupt() { in_wfi = false; }; + bool is_waiting_for_interrupt() { return in_wfi; }; + void set_nb_register_source(uint8_t new_number) {nb_register_src = new_number;} + uint8_t get_nb_register_source() {return nb_register_src;} + +private: + uint8_t nb_register_src = 2; + const isa_parser_t * const isa; + const cfg_t * const cfg; + + simif_t* sim; + mmu_t* mmu; // main memory is always accessed via the mmu + std::unordered_map<std::string, extension_t*> custom_extensions; + disassembler_t* disassembler; + state_t state; + uint32_t id; + unsigned xlen; + bool histogram_enabled; + bool log_commits_enabled; + FILE *log_file; + std::ostream sout_; // needed for socket command interface -s, also used for -d and -l, but not for --log + bool halt_on_reset; + bool in_wfi; + bool check_triggers_icount; + std::vector<bool> impl_table; + + // Note: does not include single-letter extensions in misa + std::bitset<NUM_ISA_EXTENSIONS> extension_enable_table; + std::bitset<NUM_ISA_EXTENSIONS> extension_dynamic; + mutable std::bitset<NUM_ISA_EXTENSIONS> extension_assumed_const; + + std::vector<insn_desc_t> instructions; + std::unordered_map<reg_t,uint64_t> pc_histogram; + + static const size_t OPCODE_CACHE_SIZE = 8191; + insn_desc_t opcode_cache[OPCODE_CACHE_SIZE]; + + void take_pending_interrupt() { take_interrupt(state.mip->read() & state.mie->read()); } + void take_interrupt(reg_t mask); // take first enabled interrupt in mask + void take_trap(trap_t& t, reg_t epc); // take an exception + void take_trigger_action(triggers::action_t action, reg_t breakpoint_tval, reg_t epc); + void disasm(insn_t insn); // disassemble and print an instruction + int paddr_bits(); + + void enter_debug_mode(uint8_t cause); + + void debug_output_log(std::stringstream *s); // either output to interactive user or write to log file + + friend class mmu_t; + friend class clint_t; + friend class plic_t; + friend class extension_t; + + void parse_varch_string(const char*); + void parse_priv_string(const char*); + void build_opcode_map(); + void register_base_instructions(); + insn_func_t decode_insn(insn_t insn); + + // Track repeated executions for processor_t::disasm() + uint64_t last_pc, last_bits, executions; +public: + entropy_source es; // Crypto ISE Entropy source. + + reg_t n_pmp; + reg_t lg_pmp_granularity; + reg_t pmp_tor_mask() { return -(reg_t(1) << (lg_pmp_granularity - PMP_SHIFT)); } + + vectorUnit_t VU; + triggers::module_t TM; +}; + +#endif diff --git a/vendor/riscv/riscv-isa-sim/riscv/remote_bitbang.cc b/vendor/riscv/riscv-isa-sim/riscv/remote_bitbang.cc new file mode 100644 index 0000000000..8453e85abd --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/remote_bitbang.cc @@ -0,0 +1,187 @@ +#include <arpa/inet.h> +#include <errno.h> +#include <fcntl.h> +#include <stdlib.h> +#include <string.h> +#include <unistd.h> + +#ifndef AF_INET +#include <sys/socket.h> +#endif +#ifndef INADDR_ANY +#include <netinet/in.h> +#endif + +#include <algorithm> +#include <cassert> +#include <cstdio> + +#include "remote_bitbang.h" + +#if 1 +# define D(x) x +#else +# define D(x) +#endif + +/////////// remote_bitbang_t + +remote_bitbang_t::remote_bitbang_t(uint16_t port, jtag_dtm_t *tap) : + tap(tap), + socket_fd(0), + client_fd(0), + recv_start(0), + recv_end(0) +{ + socket_fd = socket(AF_INET, SOCK_STREAM, 0); + if (socket_fd == -1) { + fprintf(stderr, "remote_bitbang failed to make socket: %s (%d)\n", + strerror(errno), errno); + abort(); + } + + fcntl(socket_fd, F_SETFL, O_NONBLOCK); + int reuseaddr = 1; + if (setsockopt(socket_fd, SOL_SOCKET, SO_REUSEADDR, &reuseaddr, + sizeof(int)) == -1) { + fprintf(stderr, "remote_bitbang failed setsockopt: %s (%d)\n", + strerror(errno), errno); + abort(); + } + + struct sockaddr_in addr; + memset(&addr, 0, sizeof(addr)); + addr.sin_family = AF_INET; + addr.sin_addr.s_addr = INADDR_ANY; + addr.sin_port = htons(port); + + if (bind(socket_fd, (struct sockaddr *) &addr, sizeof(addr)) == -1) { + fprintf(stderr, "remote_bitbang failed to bind socket: %s (%d)\n", + strerror(errno), errno); + abort(); + } + + if (listen(socket_fd, 1) == -1) { + fprintf(stderr, "remote_bitbang failed to listen on socket: %s (%d)\n", + strerror(errno), errno); + abort(); + } + + socklen_t addrlen = sizeof(addr); + if (getsockname(socket_fd, (struct sockaddr *) &addr, &addrlen) == -1) { + fprintf(stderr, "remote_bitbang getsockname failed: %s (%d)\n", + strerror(errno), errno); + abort(); + } + + printf("Listening for remote bitbang connection on port %d.\n", + ntohs(addr.sin_port)); + fflush(stdout); +} + +void remote_bitbang_t::accept() +{ + client_fd = ::accept(socket_fd, NULL, NULL); + if (client_fd == -1) { + if (errno == EAGAIN) { + // No client waiting to connect right now. + } else { + fprintf(stderr, "failed to accept on socket: %s (%d)\n", strerror(errno), + errno); + abort(); + } + } else { + fcntl(client_fd, F_SETFL, O_NONBLOCK); + } +} + +void remote_bitbang_t::tick() +{ + if (client_fd > 0) { + execute_commands(); + } else { + this->accept(); + } +} + +void remote_bitbang_t::execute_commands() +{ + static char send_buf[buf_size]; + unsigned total_processed = 0; + bool quit = false; + bool in_rti = tap->state() == RUN_TEST_IDLE; + bool entered_rti = false; + while (1) { + if (recv_start < recv_end) { + unsigned send_offset = 0; + while (recv_start < recv_end) { + uint8_t command = recv_buf[recv_start]; + + switch (command) { + case 'B': /* fprintf(stderr, "*BLINK*\n"); */ break; + case 'b': /* fprintf(stderr, "_______\n"); */ break; + case 'r': tap->reset(); break; + case '0': tap->set_pins(0, 0, 0); break; + case '1': tap->set_pins(0, 0, 1); break; + case '2': tap->set_pins(0, 1, 0); break; + case '3': tap->set_pins(0, 1, 1); break; + case '4': tap->set_pins(1, 0, 0); break; + case '5': tap->set_pins(1, 0, 1); break; + case '6': tap->set_pins(1, 1, 0); break; + case '7': tap->set_pins(1, 1, 1); break; + case 'R': send_buf[send_offset++] = tap->tdo() ? '1' : '0'; break; + case 'Q': quit = true; break; + default: + fprintf(stderr, "remote_bitbang got unsupported command '%c'\n", + command); + } + recv_start++; + total_processed++; + if (!in_rti && tap->state() == RUN_TEST_IDLE) { + entered_rti = true; + break; + } + in_rti = false; + } + unsigned sent = 0; + while (sent < send_offset) { + ssize_t bytes = write(client_fd, send_buf + sent, send_offset); + if (bytes == -1) { + fprintf(stderr, "failed to write to socket: %s (%d)\n", strerror(errno), errno); + abort(); + } + sent += bytes; + } + } + + if (total_processed > buf_size || quit || entered_rti) { + // Don't go forever, because that could starve the main simulation. + break; + } + + recv_start = 0; + recv_end = read(client_fd, recv_buf, buf_size); + + if (recv_end == -1) { + if (errno == EAGAIN) { + break; + } else { + fprintf(stderr, "remote_bitbang failed to read on socket: %s (%d)\n", + strerror(errno), errno); + abort(); + } + } + + if (quit) { + fprintf(stderr, "Remote Bitbang received 'Q'\n"); + } + + if (recv_end == 0 || quit) { + // The remote disconnected. + fprintf(stderr, "Received nothing. Quitting.\n"); + close(client_fd); + client_fd = 0; + break; + } + } +} diff --git a/vendor/riscv/riscv-isa-sim/riscv/remote_bitbang.h b/vendor/riscv/riscv-isa-sim/riscv/remote_bitbang.h new file mode 100644 index 0000000000..1db4d55014 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/remote_bitbang.h @@ -0,0 +1,34 @@ +#ifndef REMOTE_BITBANG_H +#define REMOTE_BITBANG_H + +#include <stdint.h> + +#include "jtag_dtm.h" + +class remote_bitbang_t +{ +public: + // Create a new server, listening for connections from localhost on the given + // port. + remote_bitbang_t(uint16_t port, jtag_dtm_t *tap); + + // Do a bit of work. + void tick(); + +private: + jtag_dtm_t *tap; + + int socket_fd; + int client_fd; + + static const ssize_t buf_size = 64 * 1024; + char recv_buf[buf_size]; + ssize_t recv_start, recv_end; + + // Check for a client connecting, and accept if there is one. + void accept(); + // Execute any commands the client has for us. + void execute_commands(); +}; + +#endif diff --git a/vendor/riscv/riscv-isa-sim/riscv/riscv.ac b/vendor/riscv/riscv-isa-sim/riscv/riscv.ac new file mode 100644 index 0000000000..e52c57016d --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/riscv.ac @@ -0,0 +1,45 @@ +AC_LANG_CPLUSPLUS + +AX_BOOST_BASE([1.53]) +AX_BOOST_ASIO +AX_BOOST_REGEX + +AC_CHECK_LIB([boost_system], [main], [], []) + +AC_CHECK_LIB([boost_regex], [main], [], []) + +AC_ARG_WITH(isa, + [AS_HELP_STRING([--with-isa=RV64IMAFDC_zicntr_zihpm], + [Sets the default RISC-V ISA])], + AC_DEFINE_UNQUOTED([DEFAULT_ISA], "$withval", [Default value for --isa switch]), + AC_DEFINE_UNQUOTED([DEFAULT_ISA], "RV64IMAFDC_zicntr_zihpm", [Default value for --isa switch])) + +AC_ARG_WITH(priv, + [AS_HELP_STRING([--with-priv=MSU], + [Sets the default RISC-V privilege modes supported])], + AC_DEFINE_UNQUOTED([DEFAULT_PRIV], "$withval", [Default value for --priv switch]), + AC_DEFINE_UNQUOTED([DEFAULT_PRIV], "MSU", [Default value for --priv switch])) + +AC_ARG_WITH(varch, + [AS_HELP_STRING([--with-varch=vlen:128,elen:64], + [Sets the default vector config])], + AC_DEFINE_UNQUOTED([DEFAULT_VARCH], "$withval", [Default value for --varch switch]), + AC_DEFINE_UNQUOTED([DEFAULT_VARCH], ["vlen:128,elen:64"], [Default value for --varch switch])) + +AC_ARG_WITH(target, + [AS_HELP_STRING([--with-target=riscv64-unknown-elf], + [Sets the default target config])], + AC_DEFINE_UNQUOTED([TARGET_ARCH], "$withval", [Default value for --target switch]), + AC_DEFINE_UNQUOTED([TARGET_ARCH], ["riscv64-unknown-elf"], [Default value for --target switch])) + +AC_SEARCH_LIBS([dlopen], [dl dld], [ + AC_DEFINE([HAVE_DLOPEN], [], [Dynamic library loading is supported]) + AC_SUBST([HAVE_DLOPEN], [yes]) +]) + +AC_CHECK_LIB(pthread, pthread_create, [], [AC_MSG_ERROR([libpthread is required])]) + +AC_ARG_ENABLE([dual-endian], AS_HELP_STRING([--enable-dual-endian], [Enable support for running target in either endianness])) +AS_IF([test "x$enable_dual_endian" = "xyes"], [ + AC_DEFINE([RISCV_ENABLE_DUAL_ENDIAN],,[Enable support for running target in either endianness]) +]) diff --git a/vendor/riscv/riscv-isa-sim/riscv/riscv.mk.in b/vendor/riscv/riscv-isa-sim/riscv/riscv.mk.in new file mode 100644 index 0000000000..5765a91ff7 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/riscv.mk.in @@ -0,0 +1,1399 @@ +get_insn_list = $(shell grep ^DECLARE_INSN $(1) | sed 's/DECLARE_INSN(\(.*\),.*,.*)/\1/') +get_opcode = $(shell grep ^DECLARE_INSN.*\\\<$(2)\\\> $(1) | sed 's/DECLARE_INSN(.*,\(.*\),.*)/\1/') + +riscv_subproject_deps = \ + fdt \ + disasm \ + fesvr \ + softfloat \ + +riscv_CFLAGS = -fPIC + +riscv_install_shared_lib = yes + +riscv_install_prog_srcs = \ + +riscv_install_hdrs = \ + abstract_device.h \ + abstract_interrupt_controller.h \ + cachesim.h \ + cfg.h \ + common.h \ + csrs.h \ + cvxif.h \ + debug_defines.h \ + debug_module.h \ + debug_rom_defines.h \ + decode.h \ + devices.h \ + disasm.h \ + encoding.h \ + entropy_source.h \ + extension.h \ + isa_parser.h \ + log_file.h \ + memtracer.h \ + mmio_plugin.h \ + mmu.h \ + platform.h \ + processor.h \ + rocc.h \ + sim.h \ + simif.h \ + trap.h \ + triggers.h \ + vector_unit.h \ + +riscv_precompiled_hdrs = \ + insn_template.h \ + +riscv_srcs = \ + isa_parser.cc \ + processor.cc \ + execute.cc \ + dts.cc \ + sim.cc \ + interactive.cc \ + cachesim.cc \ + mmu.cc \ + extension.cc \ + extensions.cc \ + rocc.cc \ + cvxif_base.cc \ + devices.cc \ + rom.cc \ + clint.cc \ + plic.cc \ + ns16550.cc \ + debug_module.cc \ + remote_bitbang.cc \ + jtag_dtm.cc \ + csrs.cc \ + triggers.cc \ + vector_unit.cc \ + socketif.cc \ + cfg.cc \ + $(riscv_gen_srcs) \ + +riscv_test_srcs = + +riscv_gen_hdrs = \ + insn_list.h \ + + +riscv_insn_ext_i = \ + add \ + addi \ + addiw \ + addw \ + and \ + andi \ + auipc \ + beq \ + bge \ + bgeu \ + blt \ + bltu \ + bne \ + jal \ + jalr \ + lb \ + lbu \ + ld \ + lh \ + lhu \ + lui \ + lw \ + lwu \ + or \ + ori \ + sb \ + sd \ + sh \ + sll \ + slli \ + slliw \ + sllw \ + slt \ + slti \ + sltiu \ + sltu \ + sra \ + srai \ + sraiw \ + sraw \ + srl \ + srli \ + srliw \ + srlw \ + sub \ + subw \ + sw \ + xor \ + xori \ + fence \ + fence_i \ + +riscv_insn_ext_a = \ + amoadd_d \ + amoadd_w \ + amoand_d \ + amoand_w \ + amomax_d \ + amomaxu_d \ + amomaxu_w \ + amomax_w \ + amomin_d \ + amominu_d \ + amominu_w \ + amomin_w \ + amoor_d \ + amoor_w \ + amoswap_d \ + amoswap_w \ + amoxor_d \ + amoxor_w \ + lr_d \ + lr_w \ + sc_d \ + sc_w \ + +riscv_insn_ext_c = \ + c_add \ + c_addi \ + c_addi4spn \ + c_addw \ + c_and \ + c_andi \ + c_beqz \ + c_bnez \ + c_ebreak \ + c_fld \ + c_fldsp \ + c_flw \ + c_flwsp \ + c_fsd \ + c_fsdsp \ + c_fsw \ + c_fswsp \ + c_j \ + c_jal \ + c_jalr \ + c_jr \ + c_li \ + c_lui \ + c_lw \ + c_lwsp \ + c_mv \ + c_or \ + c_slli \ + c_srai \ + c_srli \ + c_sub \ + c_subw \ + c_sw \ + c_swsp \ + c_xor \ + +riscv_insn_ext_m = \ + div \ + divu \ + divuw \ + divw \ + mul \ + mulh \ + mulhsu \ + mulhu \ + mulw \ + rem \ + remu \ + remuw \ + remw \ + +riscv_insn_ext_f = \ + fadd_s \ + fclass_s \ + fcvt_l_s \ + fcvt_lu_s \ + fcvt_s_l \ + fcvt_s_lu \ + fcvt_s_w \ + fcvt_s_wu \ + fcvt_w_s \ + fcvt_wu_s \ + fdiv_s \ + feq_s \ + fle_s \ + flt_s \ + flw \ + fmadd_s \ + fmax_s \ + fmin_s \ + fmsub_s \ + fmul_s \ + fmv_w_x \ + fmv_x_w \ + fnmadd_s \ + fnmsub_s \ + fsgnj_s \ + fsgnjn_s \ + fsgnjx_s \ + fsqrt_s \ + fsub_s \ + fsw \ + +riscv_insn_ext_f_zfa= \ + fli_s \ + fmaxm_s \ + fminm_s \ + fround_s \ + froundnx_s \ + fleq_s \ + fltq_s + +riscv_insn_ext_d = \ + fadd_d \ + fclass_d \ + fcvt_d_l \ + fcvt_d_lu \ + fcvt_d_q \ + fcvt_d_s \ + fcvt_d_w \ + fcvt_d_wu \ + fcvt_l_d \ + fcvt_lu_d \ + fcvt_s_d \ + fcvt_w_d \ + fcvt_wu_d \ + fdiv_d \ + feq_d \ + fld \ + fle_d \ + flt_d \ + fmadd_d \ + fmax_d \ + fmin_d \ + fmsub_d \ + fmul_d \ + fmv_d_x \ + fmv_x_d \ + fnmadd_d \ + fnmsub_d \ + fsd \ + fsgnj_d \ + fsgnjn_d \ + fsgnjx_d \ + fsqrt_d \ + fsub_d \ + +riscv_insn_ext_d_zfa = \ + fli_d \ + fmaxm_d \ + fminm_d \ + fround_d \ + froundnx_d \ + fmvh_x_d \ + fmvp_d_x \ + fcvtmod_w_d \ + fleq_d \ + fltq_d + +riscv_insn_ext_zfh = \ + fadd_h \ + fclass_h \ + fcvt_l_h \ + fcvt_lu_h \ + fcvt_d_h \ + fcvt_h_d \ + fcvt_h_l \ + fcvt_h_lu \ + fcvt_h_q \ + fcvt_h_s \ + fcvt_h_w \ + fcvt_h_wu \ + fcvt_q_h \ + fcvt_s_h \ + fcvt_w_h \ + fcvt_wu_h \ + fdiv_h \ + feq_h \ + fle_h \ + flh \ + flt_h \ + fmadd_h \ + fmax_h \ + fmin_h \ + fmsub_h \ + fmul_h \ + fmv_h_x \ + fmv_x_h \ + fnmadd_h \ + fnmsub_h \ + fsgnj_h \ + fsgnjn_h \ + fsgnjx_h \ + fsh \ + fsqrt_h \ + fsub_h \ + +riscv_insn_ext_zfh_zfa = \ + fli_h \ + fmaxm_h \ + fminm_h \ + fround_h \ + froundnx_h \ + fleq_h \ + fltq_h + +riscv_insn_ext_q = \ + fadd_q \ + fclass_q \ + fcvt_l_q \ + fcvt_lu_q \ + fcvt_q_d \ + fcvt_q_l \ + fcvt_q_lu \ + fcvt_q_s \ + fcvt_q_w \ + fcvt_q_wu \ + fcvt_s_q \ + fcvt_w_q \ + fcvt_wu_q \ + fdiv_q \ + feq_q \ + fle_q \ + flq \ + flt_q \ + fmadd_q \ + fmax_q \ + fmin_q \ + fmsub_q \ + fmul_q \ + fnmadd_q \ + fnmsub_q \ + fsgnj_q \ + fsgnjn_q \ + fsgnjx_q \ + fsq \ + fsqrt_q \ + fsub_q \ + +riscv_insn_ext_q_zfa = \ + fli_q \ + fmaxm_q \ + fminm_q \ + fround_q \ + froundnx_q \ + fmvh_x_q \ + fmvp_q_x \ + fleq_q \ + fltq_q + +riscv_insn_ext_b = \ + add_uw \ + andn \ + bdecompress \ + bdecompressw \ + bcompress \ + bcompressw \ + bfp \ + bfpw \ + bmatflip \ + bmator \ + bmatxor \ + sh1add \ + sh1add_uw \ + sh2add \ + sh2add_uw \ + sh3add \ + sh3add_uw \ + clmul \ + clmulh \ + clmulr \ + clz \ + clzw \ + cmix \ + cmov \ + crc32_b \ + crc32c_b \ + crc32c_d \ + crc32c_h \ + crc32c_w \ + crc32_d \ + crc32_h \ + crc32_w \ + ctz \ + ctzw \ + fsl \ + fslw \ + fsr \ + fsri \ + fsriw \ + fsrw \ + gorc \ + gorci \ + gorciw \ + gorcw \ + grev \ + grevi \ + greviw \ + grevw \ + max \ + maxu \ + min \ + minu \ + orn \ + pack \ + packh \ + packu \ + packuw \ + packw \ + cpop \ + cpopw \ + rol \ + rolw \ + ror \ + rori \ + roriw \ + rorw \ + bclr \ + bclri \ + bext \ + bexti \ + binv \ + binvi \ + bset \ + bseti \ + sext_b \ + sext_h \ + shfl \ + shfli \ + shflw \ + slli_uw \ + slo \ + sloi \ + sloiw \ + slow \ + sro \ + sroi \ + sroiw \ + srow \ + unshfl \ + unshfli \ + unshflw \ + xnor \ + xperm4 \ + xperm8 \ + xperm16 \ + xperm32 \ + +# Scalar Crypto ISE +riscv_insn_ext_k = \ + aes32dsi \ + aes32dsmi \ + aes32esi \ + aes32esmi \ + aes64ds \ + aes64dsm \ + aes64es \ + aes64esm \ + aes64ks1i \ + aes64ks2 \ + aes64im \ + sha256sig0 \ + sha256sig1 \ + sha256sum0 \ + sha256sum1 \ + sha512sig0 \ + sha512sig0h \ + sha512sig0l \ + sha512sig1 \ + sha512sig1h \ + sha512sig1l \ + sha512sum0 \ + sha512sum0r \ + sha512sum1 \ + sha512sum1r \ + sm3p0 \ + sm3p1 \ + sm4ed \ + sm4ks + +riscv_insn_ext_v_alu_int = \ + vaadd_vv \ + vaaddu_vv \ + vaadd_vx \ + vaaddu_vx \ + vadc_vim \ + vadc_vvm \ + vadc_vxm \ + vadd_vi \ + vadd_vv \ + vadd_vx \ + vand_vi \ + vand_vv \ + vand_vx \ + vasub_vv \ + vasubu_vv \ + vasub_vx \ + vasubu_vx \ + vcompress_vm \ + vcpop_m \ + vdiv_vv \ + vdiv_vx \ + vdivu_vv \ + vdivu_vx \ + vid_v \ + viota_m \ + vmacc_vv \ + vmacc_vx \ + vmadc_vv \ + vmadc_vx \ + vmadc_vi \ + vmadc_vim \ + vmadc_vvm \ + vmadc_vxm \ + vmadd_vv \ + vmadd_vx \ + vmand_mm \ + vmandn_mm \ + vmax_vv \ + vmax_vx \ + vmaxu_vv \ + vmaxu_vx \ + vmerge_vim \ + vmerge_vvm \ + vmerge_vxm \ + vfirst_m \ + vmin_vv \ + vmin_vx \ + vminu_vv \ + vminu_vx \ + vmnand_mm \ + vmnor_mm \ + vmor_mm \ + vmorn_mm \ + vmsbc_vv \ + vmsbc_vx \ + vmsbc_vvm \ + vmsbc_vxm \ + vmsbf_m \ + vmseq_vi \ + vmseq_vv \ + vmseq_vx \ + vmsgt_vi \ + vmsgt_vx \ + vmsgtu_vi \ + vmsgtu_vx \ + vmsif_m \ + vmsle_vi \ + vmsle_vv \ + vmsle_vx \ + vmsleu_vi \ + vmsleu_vv \ + vmsleu_vx \ + vmslt_vv \ + vmslt_vx \ + vmsltu_vv \ + vmsltu_vx \ + vmsne_vi \ + vmsne_vv \ + vmsne_vx \ + vmsof_m \ + vmul_vv \ + vmul_vx \ + vmulh_vv \ + vmulh_vx \ + vmulhsu_vv \ + vmulhsu_vx \ + vmulhu_vv \ + vmulhu_vx \ + vmv_s_x \ + vmv_v_i \ + vmv_v_v \ + vmv_v_x \ + vmv_x_s \ + vmv1r_v \ + vmv2r_v \ + vmv4r_v \ + vmv8r_v \ + vmxnor_mm \ + vmxor_mm \ + vnclip_wi \ + vnclip_wv \ + vnclip_wx \ + vnclipu_wi \ + vnclipu_wv \ + vnclipu_wx \ + vnmsac_vv \ + vnmsac_vx \ + vnmsub_vv \ + vnmsub_vx \ + vnsra_wi \ + vnsra_wv \ + vnsra_wx \ + vnsrl_wi \ + vnsrl_wv \ + vnsrl_wx \ + vor_vi \ + vor_vv \ + vor_vx \ + vredand_vs \ + vredmax_vs \ + vredmaxu_vs \ + vredmin_vs \ + vredminu_vs \ + vredor_vs \ + vredsum_vs \ + vredxor_vs \ + vrem_vv \ + vrem_vx \ + vremu_vv \ + vremu_vx \ + vrgather_vi \ + vrgather_vv \ + vrgather_vx \ + vrgatherei16_vv \ + vrsub_vi \ + vrsub_vx \ + vsadd_vi \ + vsadd_vv \ + vsadd_vx \ + vsaddu_vi \ + vsaddu_vv \ + vsaddu_vx \ + vsbc_vvm \ + vsbc_vxm \ + vsext_vf2 \ + vsext_vf4 \ + vsext_vf8 \ + vslide1down_vx \ + vslide1up_vx \ + vslidedown_vi \ + vslidedown_vx \ + vslideup_vi \ + vslideup_vx \ + vsll_vi \ + vsll_vv \ + vsll_vx \ + vsmul_vv \ + vsmul_vx \ + vsra_vi \ + vsra_vv \ + vsra_vx \ + vsrl_vi \ + vsrl_vv \ + vsrl_vx \ + vssra_vi \ + vssra_vv \ + vssra_vx \ + vssrl_vi \ + vssrl_vv \ + vssrl_vx \ + vssub_vv \ + vssub_vx \ + vssubu_vv \ + vssubu_vx \ + vsub_vv \ + vsub_vx \ + vwadd_vv \ + vwadd_vx \ + vwadd_wv \ + vwadd_wx \ + vwaddu_vv \ + vwaddu_vx \ + vwaddu_wv \ + vwaddu_wx \ + vwmacc_vv \ + vwmacc_vx \ + vwmaccsu_vv \ + vwmaccsu_vx \ + vwmaccu_vv \ + vwmaccu_vx \ + vwmaccus_vx \ + vwmul_vv \ + vwmul_vx \ + vwmulsu_vv \ + vwmulsu_vx \ + vwmulu_vv \ + vwmulu_vx \ + vwredsum_vs \ + vwredsumu_vs \ + vwsub_vv \ + vwsub_vx \ + vwsub_wv \ + vwsub_wx \ + vwsubu_vv \ + vwsubu_vx \ + vwsubu_wv \ + vwsubu_wx \ + vxor_vi \ + vxor_vv \ + vxor_vx \ + vzext_vf2 \ + vzext_vf4 \ + vzext_vf8 \ + +riscv_insn_ext_v_alu_fp = \ + vfadd_vf \ + vfadd_vv \ + vfclass_v \ + vfcvt_f_x_v \ + vfcvt_f_xu_v \ + vfcvt_rtz_x_f_v \ + vfcvt_rtz_xu_f_v \ + vfcvt_x_f_v \ + vfcvt_xu_f_v \ + vfdiv_vf \ + vfdiv_vv \ + vfmacc_vf \ + vfmacc_vv \ + vfmadd_vf \ + vfmadd_vv \ + vfmax_vf \ + vfmax_vv \ + vfmerge_vfm \ + vfmin_vf \ + vfmin_vv \ + vfmsac_vf \ + vfmsac_vv \ + vfmsub_vf \ + vfmsub_vv \ + vfmul_vf \ + vfmul_vv \ + vfmv_f_s \ + vfmv_s_f \ + vfmv_v_f \ + vfncvt_f_f_w \ + vfncvt_f_x_w \ + vfncvt_f_xu_w \ + vfncvt_rod_f_f_w \ + vfncvt_rtz_x_f_w \ + vfncvt_rtz_xu_f_w \ + vfncvt_x_f_w \ + vfncvt_xu_f_w \ + vfnmacc_vf \ + vfnmacc_vv \ + vfnmadd_vf \ + vfnmadd_vv \ + vfnmsac_vf \ + vfnmsac_vv \ + vfnmsub_vf \ + vfnmsub_vv \ + vfrdiv_vf \ + vfredmax_vs \ + vfredmin_vs \ + vfredosum_vs \ + vfredusum_vs \ + vfrec7_v \ + vfrsub_vf \ + vfrsqrt7_v \ + vfsgnj_vf \ + vfsgnj_vv \ + vfsgnjn_vf \ + vfsgnjn_vv \ + vfsgnjx_vf \ + vfsgnjx_vv \ + vfsqrt_v \ + vfslide1down_vf \ + vfslide1up_vf \ + vfsub_vf \ + vfsub_vv \ + vfwadd_vf \ + vfwadd_vv \ + vfwadd_wf \ + vfwadd_wv \ + vfwcvt_f_f_v \ + vfwcvt_f_x_v \ + vfwcvt_f_xu_v \ + vfwcvt_rtz_x_f_v \ + vfwcvt_rtz_xu_f_v \ + vfwcvt_x_f_v \ + vfwcvt_xu_f_v \ + vfwmacc_vf \ + vfwmacc_vv \ + vfwmsac_vf \ + vfwmsac_vv \ + vfwmul_vf \ + vfwmul_vv \ + vfwnmacc_vf \ + vfwnmacc_vv \ + vfwnmsac_vf \ + vfwnmsac_vv \ + vfwredosum_vs \ + vfwredusum_vs \ + vfwsub_vf \ + vfwsub_vv \ + vfwsub_wf \ + vfwsub_wv \ + vmfeq_vf \ + vmfeq_vv \ + vmfge_vf \ + vmfgt_vf \ + vmfle_vf \ + vmfle_vv \ + vmflt_vf \ + vmflt_vv \ + vmfne_vf \ + vmfne_vv \ + +riscv_insn_ext_v_amo = \ + vamoswapei8_v \ + vamoaddei8_v \ + vamoandei8_v \ + vamomaxei8_v \ + vamomaxuei8_v \ + vamominei8_v \ + vamominuei8_v \ + vamoorei8_v \ + vamoxorei8_v \ + vamoswapei16_v \ + vamoaddei16_v \ + vamoandei16_v \ + vamomaxei16_v \ + vamomaxuei16_v \ + vamominei16_v \ + vamominuei16_v \ + vamoorei16_v \ + vamoxorei16_v \ + vamoswapei32_v \ + vamoaddei32_v \ + vamoandei32_v \ + vamomaxei32_v \ + vamomaxuei32_v \ + vamominei32_v \ + vamominuei32_v \ + vamoorei32_v \ + vamoxorei32_v \ + vamoswapei64_v \ + vamoaddei64_v \ + vamoandei64_v \ + vamomaxei64_v \ + vamomaxuei64_v \ + vamominei64_v \ + vamominuei64_v \ + vamoorei64_v \ + vamoxorei64_v \ + +riscv_insn_ext_v_ldst = \ + vlm_v \ + vle8_v \ + vle16_v \ + vle32_v \ + vle64_v \ + vloxei8_v \ + vloxei16_v \ + vloxei32_v \ + vloxei64_v \ + vlse8_v \ + vlse16_v \ + vlse32_v \ + vlse64_v \ + vluxei8_v \ + vluxei16_v \ + vluxei32_v \ + vluxei64_v \ + vle8ff_v \ + vle16ff_v \ + vle32ff_v \ + vle64ff_v \ + vl1re8_v \ + vl2re8_v \ + vl4re8_v \ + vl8re8_v \ + vl1re16_v \ + vl2re16_v \ + vl4re16_v \ + vl8re16_v \ + vl1re32_v \ + vl2re32_v \ + vl4re32_v \ + vl8re32_v \ + vl1re64_v \ + vl2re64_v \ + vl4re64_v \ + vl8re64_v \ + vsm_v \ + vse8_v \ + vse16_v \ + vse32_v \ + vse64_v \ + vsse8_v \ + vsoxei8_v \ + vsoxei16_v \ + vsoxei32_v \ + vsoxei64_v \ + vsse16_v \ + vsse32_v \ + vsse64_v \ + vsuxei8_v \ + vsuxei16_v \ + vsuxei32_v \ + vsuxei64_v \ + vs1r_v \ + vs2r_v \ + vs4r_v \ + vs8r_v \ + +riscv_insn_ext_v_ctrl = \ + vsetivli \ + vsetvli \ + vsetvl \ + +riscv_insn_ext_v = \ + $(riscv_insn_ext_v_alu_fp) \ + $(riscv_insn_ext_v_alu_int) \ + $(riscv_insn_ext_v_amo) \ + $(riscv_insn_ext_v_ctrl) \ + $(riscv_insn_ext_v_ldst) \ + +riscv_insn_ext_h = \ + hfence_gvma \ + hfence_vvma \ + hlv_b \ + hlv_bu \ + hlv_h \ + hlv_hu \ + hlvx_hu \ + hlv_w \ + hlv_wu \ + hlvx_wu \ + hlv_d \ + hsv_b \ + hsv_h \ + hsv_w \ + hsv_d \ + +riscv_insn_ext_p_simd = \ + add16 \ + radd16 \ + uradd16 \ + kadd16 \ + ukadd16 \ + sub16 \ + rsub16 \ + ursub16 \ + ksub16 \ + uksub16 \ + cras16 \ + rcras16 \ + urcras16 \ + kcras16 \ + ukcras16 \ + crsa16 \ + rcrsa16 \ + urcrsa16 \ + kcrsa16 \ + ukcrsa16 \ + stas16 \ + rstas16 \ + urstas16 \ + kstas16 \ + ukstas16 \ + stsa16 \ + rstsa16 \ + urstsa16 \ + kstsa16 \ + ukstsa16 \ + add8 \ + radd8 \ + uradd8 \ + kadd8 \ + ukadd8 \ + sub8 \ + rsub8 \ + ursub8 \ + ksub8 \ + uksub8 \ + sra16 \ + srai16 \ + sra16_u \ + srai16_u \ + srl16 \ + srli16 \ + srl16_u \ + srli16_u \ + sll16 \ + slli16 \ + ksll16 \ + kslli16 \ + kslra16 \ + kslra16_u \ + sra8 \ + srai8 \ + sra8_u \ + srai8_u \ + srl8 \ + srli8 \ + srl8_u \ + srli8_u \ + sll8 \ + slli8 \ + ksll8 \ + kslli8 \ + kslra8 \ + kslra8_u \ + cmpeq16 \ + scmplt16 \ + scmple16 \ + ucmplt16 \ + ucmple16 \ + cmpeq8 \ + scmplt8 \ + scmple8 \ + ucmplt8 \ + ucmple8 \ + smul16 \ + smulx16 \ + umul16 \ + umulx16 \ + khm16 \ + khmx16 \ + smul8 \ + smulx8 \ + umul8 \ + umulx8 \ + khm8 \ + khmx8 \ + smin16 \ + umin16 \ + smax16 \ + umax16 \ + sclip16 \ + uclip16 \ + kabs16 \ + clrs16 \ + clz16 \ + smin8 \ + umin8 \ + smax8 \ + umax8 \ + sclip8 \ + uclip8 \ + kabs8 \ + clrs8 \ + clz8 \ + sunpkd810 \ + sunpkd820 \ + sunpkd830 \ + sunpkd831 \ + sunpkd832 \ + zunpkd810 \ + zunpkd820 \ + zunpkd830 \ + zunpkd831 \ + zunpkd832 \ + +riscv_insn_ext_p_partial_simd = \ + pkbb16 \ + pkbt16 \ + pktb16 \ + pktt16 \ + smmul \ + smmul_u \ + kmmac \ + kmmac_u \ + kmmsb \ + kmmsb_u \ + kwmmul \ + kwmmul_u \ + smmwb \ + smmwb_u \ + smmwt \ + smmwt_u \ + kmmawb \ + kmmawb_u \ + kmmawt \ + kmmawt_u \ + kmmwb2 \ + kmmwb2_u \ + kmmwt2 \ + kmmwt2_u \ + kmmawb2 \ + kmmawb2_u \ + kmmawt2 \ + kmmawt2_u \ + smbb16 \ + smbt16 \ + smtt16 \ + kmda \ + kmxda \ + smds \ + smdrs \ + smxds \ + kmabb \ + kmabt \ + kmatt \ + kmada \ + kmaxda \ + kmads \ + kmadrs \ + kmaxds \ + kmsda \ + kmsxda \ + smal \ + sclip32 \ + uclip32 \ + clrs32 \ + pbsad \ + pbsada \ + smaqa \ + umaqa \ + smaqa_su \ + +riscv_insn_ext_p_64_bit_profile = \ + add64 \ + radd64 \ + uradd64 \ + kadd64 \ + ukadd64 \ + sub64 \ + rsub64 \ + ursub64 \ + ksub64 \ + uksub64 \ + smar64 \ + smsr64 \ + umar64 \ + umsr64 \ + kmar64 \ + kmsr64 \ + ukmar64 \ + ukmsr64 \ + smalbb \ + smalbt \ + smaltt \ + smalda \ + smalxda \ + smalds \ + smaldrs \ + smalxds \ + smslda \ + smslxda \ + +riscv_insn_ext_p_non_simd = \ + kaddh \ + ksubh \ + khmbb \ + khmbt \ + khmtt \ + ukaddh \ + uksubh \ + kaddw \ + ukaddw \ + ksubw \ + uksubw \ + kdmbb \ + kdmbt \ + kdmtt \ + kslraw \ + kslraw_u \ + ksllw \ + kslliw \ + kdmabb \ + kdmabt \ + kdmatt \ + kabsw \ + raddw \ + uraddw \ + rsubw \ + ursubw \ + mulr64 \ + mulsr64 \ + msubr32 \ + ave \ + sra_u \ + srai_u \ + insb \ + maddr32 \ + +riscv_insn_ext_p_rv64_only = \ + add32 \ + radd32 \ + uradd32 \ + kadd32 \ + ukadd32 \ + sub32 \ + rsub32 \ + ursub32 \ + ksub32 \ + uksub32 \ + cras32 \ + rcras32 \ + urcras32 \ + kcras32 \ + ukcras32 \ + crsa32 \ + rcrsa32 \ + urcrsa32 \ + kcrsa32 \ + ukcrsa32 \ + stas32 \ + rstas32 \ + urstas32 \ + kstas32 \ + ukstas32 \ + stsa32 \ + rstsa32 \ + urstsa32 \ + kstsa32 \ + ukstsa32 \ + sra32 \ + srai32 \ + sra32_u \ + srai32_u \ + srl32 \ + srli32 \ + srl32_u \ + srli32_u \ + sll32 \ + slli32 \ + ksll32 \ + kslli32 \ + kslra32 \ + kslra32_u \ + smin32 \ + umin32 \ + smax32 \ + umax32 \ + kabs32 \ + khmbb16 \ + khmbt16 \ + khmtt16 \ + kdmbb16 \ + kdmbt16 \ + kdmtt16 \ + kdmabb16 \ + kdmabt16 \ + kdmatt16 \ + smbt32 \ + smtt32 \ + kmabb32 \ + kmabt32 \ + kmatt32 \ + kmda32 \ + kmxda32 \ + kmaxda32 \ + kmads32 \ + kmadrs32 \ + kmaxds32 \ + kmsda32 \ + kmsxda32 \ + smds32 \ + smdrs32 \ + smxds32 \ + sraiw_u \ + pkbt32 \ + pktb32 \ + clz32 \ + +riscv_insn_ext_p = \ + $(riscv_insn_ext_p_simd) \ + $(riscv_insn_ext_p_partial_simd) \ + $(riscv_insn_ext_p_64_bit_profile) \ + $(riscv_insn_ext_p_non_simd) \ + $(riscv_insn_ext_p_rv64_only) \ + +riscv_insn_priv = \ + csrrc \ + csrrci \ + csrrs \ + csrrsi \ + csrrw \ + csrrwi \ + dret \ + ebreak \ + ecall \ + mret \ + sfence_vma \ + sret \ + wfi \ + +riscv_insn_smrnmi = \ + mnret \ + +riscv_insn_svinval = \ + sfence_w_inval \ + sfence_inval_ir \ + sinval_vma \ + hinval_vvma \ + hinval_gvma \ + +riscv_insn_ext_zcb = \ + c_zext_b \ + c_zext_h \ + c_zext_w \ + c_sext_b \ + c_sext_h \ + c_not \ + c_mul \ + c_lbu \ + c_lhu \ + c_lh \ + c_sb \ + c_sh \ + +riscv_insn_ext_zcmp = \ + cm_push \ + cm_pop \ + cm_popret \ + cm_popretz \ + cm_mva01s \ + cm_mvsa01 \ + +riscv_insn_ext_zcmt = \ + cm_jalt \ + +riscv_insn_ext_zce = \ + $(riscv_insn_ext_zcb) \ + $(riscv_insn_ext_zcmp) \ + $(riscv_insn_ext_zcmt) \ + +riscv_insn_ext_cmo = \ + cbo_clean \ + cbo_flush \ + cbo_inval \ + cbo_zero \ + +riscv_insn_ext_zicond = \ + czero_eqz \ + czero_nez \ + +riscv_insn_list = \ + $(riscv_insn_ext_a) \ + $(riscv_insn_ext_c) \ + $(riscv_insn_ext_i) \ + $(riscv_insn_ext_m) \ + $(riscv_insn_ext_f) \ + $(riscv_insn_ext_f_zfa) \ + $(riscv_insn_ext_d) \ + $(riscv_insn_ext_d_zfa) \ + $(riscv_insn_ext_zfh) \ + $(riscv_insn_ext_zfh_zfa) \ + $(riscv_insn_ext_q) \ + $(riscv_insn_ext_q_zfa) \ + $(riscv_insn_ext_b) \ + $(riscv_insn_ext_k) \ + $(if $(HAVE_INT128),$(riscv_insn_ext_v),) \ + $(riscv_insn_ext_zce) \ + $(riscv_insn_ext_h) \ + $(riscv_insn_ext_p) \ + $(riscv_insn_priv) \ + $(riscv_insn_svinval) \ + $(riscv_insn_smrnmi) \ + $(riscv_insn_ext_cmo) \ + $(riscv_insn_ext_zicond) \ + +riscv_gen_srcs = $(addsuffix .cc,$(riscv_insn_list)) + +insn_list.h: $(src_dir)/riscv/riscv.mk.in + for insn in $(foreach insn,$(riscv_insn_list),$(subst .,_,$(insn))) ; do \ + printf 'DEFINE_INSN(%s)\n' "$${insn}" ; \ + done > $@.tmp + mv $@.tmp $@ + +$(riscv_gen_srcs): %.cc: insns/%.h insn_template.cc + sed 's/NAME/$(subst .cc,,$@)/' $(src_dir)/riscv/insn_template.cc | sed 's/OPCODE/$(call get_opcode,$(src_dir)/riscv/encoding.h,$(subst .cc,,$@))/' > $@ + +riscv_junk = \ + $(riscv_gen_srcs) \ diff --git a/vendor/riscv/riscv-isa-sim/riscv/rocc.cc b/vendor/riscv/riscv-isa-sim/riscv/rocc.cc new file mode 100644 index 0000000000..53ee0512b1 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/rocc.cc @@ -0,0 +1,56 @@ +// See LICENSE for license details. + +#define DECODE_MACRO_USAGE_LOGGED 1 +#include "decode_macros.h" +#include "rocc.h" +#include "trap.h" +#include <cstdlib> + +#define customX(n) \ + static reg_t c##n(processor_t* p, insn_t insn, reg_t pc) \ + { \ + rocc_t* rocc = static_cast<rocc_t*>(p->get_extension()); \ + rocc_insn_union_t u; \ + u.i = insn; \ + reg_t xs1 = u.r.xs1 ? RS1 : -1; \ + reg_t xs2 = u.r.xs2 ? RS2 : -1; \ + reg_t xd = rocc->custom##n(u.r, xs1, xs2); \ + if (u.r.xd) \ + WRITE_RD(xd); \ + return pc+4; \ + } \ + \ + reg_t rocc_t::custom##n(rocc_insn_t UNUSED insn, reg_t UNUSED xs1, reg_t UNUSED xs2) \ + { \ + illegal_instruction(); \ + return 0; \ + } + +customX(0) +customX(1) +customX(2) +customX(3) + +std::vector<insn_desc_t> rocc_t::get_instructions() +{ + std::vector<insn_desc_t> insns; + insns.push_back((insn_desc_t){0x0b, 0x7f, + &::illegal_instruction, c0, &::illegal_instruction, c0, + &::illegal_instruction, c0, &::illegal_instruction, c0}); + insns.push_back((insn_desc_t){0x2b, 0x7f, + &::illegal_instruction, c1, &::illegal_instruction, c1, + &::illegal_instruction, c1, &::illegal_instruction, c1}); + insns.push_back((insn_desc_t){0x5b, 0x7f, + &::illegal_instruction, c2, &::illegal_instruction, c2, + &::illegal_instruction, c2, &::illegal_instruction, c2}); + insns.push_back((insn_desc_t){0x7b, 0x7f, + &::illegal_instruction, c3, &::illegal_instruction, c3, + &::illegal_instruction, c0, &::illegal_instruction, c3}); + return insns; +} + +std::vector<disasm_insn_t*> rocc_t::get_disasms() +{ + std::vector<disasm_insn_t*> insns; + return insns; +} diff --git a/vendor/riscv/riscv-isa-sim/riscv/rocc.h b/vendor/riscv/riscv-isa-sim/riscv/rocc.h new file mode 100644 index 0000000000..d65ec979a2 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/rocc.h @@ -0,0 +1,69 @@ +#ifndef _RISCV_ROCC_H +#define _RISCV_ROCC_H + +#include "extension.h" + +struct rocc_insn_t +{ + unsigned opcode : 7; + unsigned rd : 5; + unsigned xs2 : 1; + unsigned xs1 : 1; + unsigned xd : 1; + unsigned rs1 : 5; + unsigned rs2 : 5; + unsigned funct : 7; +}; + +union rocc_insn_union_t +{ + rocc_insn_t r; + insn_t i; +}; + +class rocc_t : public extension_t +{ + public: + virtual reg_t custom0(rocc_insn_t insn, reg_t xs1, reg_t xs2); + virtual reg_t custom1(rocc_insn_t insn, reg_t xs1, reg_t xs2); + virtual reg_t custom2(rocc_insn_t insn, reg_t xs1, reg_t xs2); + virtual reg_t custom3(rocc_insn_t insn, reg_t xs1, reg_t xs2); + std::vector<insn_desc_t> get_instructions(); + std::vector<disasm_insn_t*> get_disasms(); +}; + +#define define_custom_func(type_name, ext_name_str, func_name, method_name) \ + static reg_t func_name(processor_t* p, insn_t insn, reg_t pc) \ + { \ + type_name* rocc = static_cast<type_name*>(p->get_extension(ext_name_str)); \ + rocc_insn_union_t u; \ + state_t* state = p->get_state(); \ + u.i = insn; \ + reg_t xs1 = u.r.xs1 ? state->XPR[insn.rs1()] : -1; \ + reg_t xs2 = u.r.xs2 ? state->XPR[insn.rs2()] : -1; \ + reg_t xd = rocc->method_name(u.r, xs1, xs2); \ + if (u.r.xd) { \ + state->log_reg_write[insn.rd() << 4] = {xd, 0}; \ + state->XPR.write(insn.rd(), xd); \ + } \ + return pc+4; \ + } \ + +#define push_custom_insn(insn_list, opcode, opcode_mask, func_name_32, func_name_64) \ + insn_list.push_back((insn_desc_t){opcode, opcode_mask, \ + func_name_32, func_name_64, \ + func_name_32, func_name_64, \ + func_name_32, func_name_64, \ + func_name_32, func_name_64, \ + }) \ + +#define ILLEGAL_INSN_FUNC &::illegal_instruction + +#define ROCC_OPCODE0 0x0b +#define ROCC_OPCODE1 0x2b +#define ROCC_OPCODE2 0x5b +#define ROCC_OPCODE3 0x7b + +#define ROCC_OPCODE_MASK 0x7f + +#endif diff --git a/vendor/riscv/riscv-isa-sim/riscv/rom.cc b/vendor/riscv/riscv-isa-sim/riscv/rom.cc new file mode 100644 index 0000000000..6f25652ae4 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/rom.cc @@ -0,0 +1,20 @@ +#include "common.h" +#include "devices.h" + +rom_device_t::rom_device_t(std::vector<char> data) + : data(data) +{ +} + +bool rom_device_t::load(reg_t addr, size_t len, uint8_t* bytes) +{ + if (addr + len > data.size()) + return false; + memcpy(bytes, &data[addr], len); + return true; +} + +bool rom_device_t::store(reg_t UNUSED addr, size_t UNUSED len, const uint8_t UNUSED *bytes) +{ + return false; +} diff --git a/vendor/riscv/riscv-isa-sim/riscv/sim.cc b/vendor/riscv/riscv-isa-sim/riscv/sim.cc new file mode 100644 index 0000000000..9179ee4e33 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/sim.cc @@ -0,0 +1,460 @@ +// See LICENSE for license details. + +#include "config.h" +#include "sim.h" +#include "mmu.h" +#include "dts.h" +#include "remote_bitbang.h" +#include "byteorder.h" +#include "platform.h" +#include "libfdt.h" +#include "socketif.h" +#include <fstream> +#include <map> +#include <iostream> +#include <sstream> +#include <climits> +#include <cstdlib> +#include <cassert> +#include <signal.h> +#include <unistd.h> +#include <sys/wait.h> +#include <sys/types.h> + +volatile bool ctrlc_pressed = false; +static void handle_signal(int sig) +{ + if (ctrlc_pressed) + exit(-1); + ctrlc_pressed = true; + signal(sig, &handle_signal); +} + +const size_t sim_t::INTERLEAVE; + +sim_t::sim_t(const cfg_t *cfg, bool halted, + std::vector<std::pair<reg_t, mem_t*>> mems, + std::vector<std::pair<reg_t, abstract_device_t*>> plugin_devices, + const std::vector<std::string>& args, + const debug_module_config_t &dm_config, + const char *log_path, + bool dtb_enabled, const char *dtb_file, + bool socket_enabled, + FILE *cmd_file, // needed for command line option --cmd + size_t max_steps) + : htif_t(args), + isa(cfg->isa(), cfg->priv()), + cfg(cfg), + mems(mems), + plugin_devices(plugin_devices), + procs(std::max(cfg->nprocs(), size_t(1))), + dtb_enabled(dtb_enabled), + log_file(log_path), + cmd_file(cmd_file), + sout_(nullptr), + current_step(0), + total_steps(0), + max_steps(max_steps), + current_proc(0), + debug(false), + histogram_enabled(false), + log(false), + remote_bitbang(NULL), + debug_module(this, dm_config) +{ + signal(SIGINT, &handle_signal); + + sout_.rdbuf(std::cerr.rdbuf()); // debug output goes to stderr by default + + for (auto& x : mems) + bus.add_device(x.first, x.second); + + for (auto& x : plugin_devices) + bus.add_device(x.first, x.second); + + debug_module.add_device(&bus); + + socketif = NULL; +#ifdef HAVE_BOOST_ASIO + if (socket_enabled) { + socketif = new socketif_t(); + } +#else + if (socket_enabled) { + fputs("Socket support requires compilation with boost asio; " + "please rebuild the riscv-isa-sim project using " + "\"configure --with-boost-asio\".\n", + stderr); + abort(); + } +#endif + +#ifndef RISCV_ENABLE_DUAL_ENDIAN + if (cfg->endianness != endianness_little) { + fputs("Big-endian support has not been prroperly enabled; " + "please rebuild the riscv-isa-sim project using " + "\"configure --enable-dual-endian\".\n", + stderr); + abort(); + } +#endif + + debug_mmu = new mmu_t(this, cfg->endianness, NULL); + + for (size_t i = 0; i < cfg->nprocs(); i++) { + procs[i] = new processor_t(&isa, cfg, this, cfg->hartids()[i], halted, + log_file.get(), sout_); + harts[cfg->hartids()[i]] = procs[i]; + } + + // When running without using a dtb, skip the fdt-based configuration steps + if (!dtb_enabled) return; + + // Load dtb_file if provided, otherwise self-generate a dts/dtb + make_dtb(dtb_file); + + void *fdt = (void *)dtb.c_str(); + + // Only make a CLINT (Core-Local INTerrupt controller) if one is specified in + // the device tree configuration. + // + // This isn't *quite* as general as we could get (because you might have one + // that's not bus-accessible), but it should handle the normal use cases. In + // particular, the default device tree configuration that you get without + // setting the dtb_file argument has one. + reg_t clint_base; + if (fdt_parse_clint(fdt, &clint_base, "riscv,clint0") == 0) { + clint.reset(new clint_t(this, CPU_HZ / INSNS_PER_RTC_TICK, cfg->real_time_clint())); + bus.add_device(clint_base, clint.get()); + } + + // pointer to wired interrupt controller + abstract_interrupt_controller_t *intctrl = NULL; + + // create plic + reg_t plic_base; + uint32_t plic_ndev; + if (fdt_parse_plic(fdt, &plic_base, &plic_ndev, "riscv,plic0") == 0) { + plic.reset(new plic_t(this, plic_ndev)); + bus.add_device(plic_base, plic.get()); + intctrl = plic.get(); + } + + // create ns16550 + reg_t ns16550_base; + uint32_t ns16550_shift, ns16550_io_width; + if (fdt_parse_ns16550(fdt, &ns16550_base, + &ns16550_shift, &ns16550_io_width, "ns16550a") == 0) { + assert(intctrl); + ns16550.reset(new ns16550_t(&bus, intctrl, NS16550_INTERRUPT_ID, + ns16550_shift, ns16550_io_width)); + bus.add_device(ns16550_base, ns16550.get()); + } + + //per core attribute + int cpu_offset = 0, rc; + size_t cpu_idx = 0; + cpu_offset = fdt_get_offset(fdt, "/cpus"); + if (cpu_offset < 0) + return; + + for (cpu_offset = fdt_get_first_subnode(fdt, cpu_offset); cpu_offset >= 0; + cpu_offset = fdt_get_next_subnode(fdt, cpu_offset)) { + + if (cpu_idx >= nprocs()) + break; + + //handle pmp + reg_t pmp_num, pmp_granularity; + if (fdt_parse_pmp_num(fdt, cpu_offset, &pmp_num) != 0) + pmp_num = 0; + procs[cpu_idx]->set_pmp_num(pmp_num); + + if (fdt_parse_pmp_alignment(fdt, cpu_offset, &pmp_granularity) == 0) { + procs[cpu_idx]->set_pmp_granularity(pmp_granularity); + } + + //handle mmu-type + const char *mmu_type; + rc = fdt_parse_mmu_type(fdt, cpu_offset, &mmu_type); + if (rc == 0) { + procs[cpu_idx]->set_mmu_capability(IMPL_MMU_SBARE); + if (strncmp(mmu_type, "riscv,sv32", strlen("riscv,sv32")) == 0) { + procs[cpu_idx]->set_mmu_capability(IMPL_MMU_SV32); + } else if (strncmp(mmu_type, "riscv,sv39", strlen("riscv,sv39")) == 0) { + procs[cpu_idx]->set_mmu_capability(IMPL_MMU_SV39); + } else if (strncmp(mmu_type, "riscv,sv48", strlen("riscv,sv48")) == 0) { + procs[cpu_idx]->set_mmu_capability(IMPL_MMU_SV48); + } else if (strncmp(mmu_type, "riscv,sv57", strlen("riscv,sv57")) == 0) { + procs[cpu_idx]->set_mmu_capability(IMPL_MMU_SV57); + } else if (strncmp(mmu_type, "riscv,sbare", strlen("riscv,sbare")) == 0) { + //has been set in the beginning + } else { + std::cerr << "core (" + << cpu_idx + << ") has an invalid 'mmu-type': " + << mmu_type << ").\n"; + exit(1); + } + } else { + procs[cpu_idx]->set_mmu_capability(IMPL_MMU_SBARE); + } + + cpu_idx++; + } + + if (cpu_idx != nprocs()) { + std::cerr << "core number in dts (" + << cpu_idx + << ") doesn't match it in command line (" + << nprocs() << ").\n"; + exit(1); + } +} + +sim_t::~sim_t() +{ + for (size_t i = 0; i < procs.size(); i++) + delete procs[i]; + delete debug_mmu; +} + +int sim_t::run() +{ + if (!debug && log) + set_procs_debug(true); + + htif_t::set_expected_xlen(isa.get_max_xlen()); + + // htif_t::run() will repeatedly call back into sim_t::idle(), each + // invocation of which will advance target time + return htif_t::run(); +} + +void sim_t::step(size_t n) +{ + for (size_t i = 0, steps = 0; i < n; i += steps) + { + steps = std::min(n - i, INTERLEAVE - current_step); + procs[current_proc]->step(steps); + + current_step += steps; + total_steps += steps; + + // max_steps must be non-zero to act as an execution limit. + if (max_steps && total_steps >= max_steps) + { + // "Stepout": max step count reached/exceeded. + std::cerr << "*** Maximum step count reached (total_steps = " + << std::dec << total_steps << ", max_steps = " + << max_steps << "), exiting!" << std::endl; + // TODO FIXME: Determine the best method of terminating. + // FORNOW: Exit successfully and let the caller of Spike + // decide how to proceed in view of simulation results. + exit(0); + } + + if (current_step == INTERLEAVE) + { + current_step = 0; + if (procs.size() > 1) + procs[current_proc]->get_mmu()->yield_load_reservation(); + if (++current_proc == procs.size()) { + current_proc = 0; + if (clint) clint->increment(INTERLEAVE / INSNS_PER_RTC_TICK); + if (ns16550) ns16550->tick(); + } + } + } +} + +void sim_t::set_debug(bool value) +{ + debug = value; +} + +void sim_t::set_histogram(bool value) +{ + histogram_enabled = value; + for (size_t i = 0; i < procs.size(); i++) { + procs[i]->set_histogram(histogram_enabled); + } +} + +void sim_t::configure_log(bool enable_log, bool enable_commitlog) +{ + log = enable_log; + + if (!enable_commitlog) + return; + + for (processor_t *proc : procs) { + proc->enable_log_commits(); + } +} + +void sim_t::set_procs_debug(bool value) +{ + for (size_t i=0; i< procs.size(); i++) + procs[i]->set_debug(value); +} + +static bool paddr_ok(reg_t addr) +{ + return (addr >> MAX_PADDR_BITS) == 0; +} + +bool sim_t::mmio_load(reg_t paddr, size_t len, uint8_t* bytes) +{ + if (paddr + len < paddr || !paddr_ok(paddr + len - 1)) + return false; + return bus.load(paddr, len, bytes); +} + +bool sim_t::mmio_store(reg_t paddr, size_t len, const uint8_t* bytes) +{ + if (paddr + len < paddr || !paddr_ok(paddr + len - 1)) + return false; + return bus.store(paddr, len, bytes); +} + +void sim_t::make_dtb(const char* dtb_file) +{ + if (dtb_file) { + std::ifstream fin(dtb_file, std::ios::binary); + if (!fin.good()) { + std::cerr << "can't find dtb file: " << dtb_file << std::endl; + exit(-1); + } + + std::stringstream strstream; + strstream << fin.rdbuf(); + + dtb = strstream.str(); + } else { + std::pair<reg_t, reg_t> initrd_bounds = cfg->initrd_bounds(); + dts = make_dts(INSNS_PER_RTC_TICK, CPU_HZ, + initrd_bounds.first, initrd_bounds.second, + cfg->bootargs(), cfg->pmpregions, procs, mems); + dtb = dts_compile(dts); + } + + int fdt_code = fdt_check_header(dtb.c_str()); + if (fdt_code) { + std::cerr << "Failed to read DTB from "; + if (!dtb_file) { + std::cerr << "auto-generated DTS string"; + } else { + std::cerr << "`" << dtb_file << "'"; + } + std::cerr << ": " << fdt_strerror(fdt_code) << ".\n"; + exit(-1); + } +} + +void sim_t::set_rom() +{ + const int reset_vec_size = 8; + + reg_t start_pc = cfg->start_pc.value_or(get_entry_point()); + + uint32_t reset_vec[reset_vec_size] = { + 0x297, // auipc t0,0x0 + 0x28593 + (reset_vec_size * 4 << 20), // addi a1, t0, &dtb + 0xf1402573, // csrr a0, mhartid + get_core(0)->get_xlen() == 32 ? + 0x0182a283u : // lw t0,24(t0) + 0x0182b283u, // ld t0,24(t0) + 0x28067, // jr t0 + 0, + (uint32_t) (start_pc & 0xffffffff), + (uint32_t) (start_pc >> 32) + }; + if (get_target_endianness() == endianness_big) { + int i; + // Instuctions are little endian + for (i = 0; reset_vec[i] != 0; i++) + reset_vec[i] = to_le(reset_vec[i]); + // Data is big endian + for (; i < reset_vec_size; i++) + reset_vec[i] = to_be(reset_vec[i]); + + // Correct the high/low order of 64-bit start PC + if (get_core(0)->get_xlen() != 32) + std::swap(reset_vec[reset_vec_size-2], reset_vec[reset_vec_size-1]); + } else { + for (int i = 0; i < reset_vec_size; i++) + reset_vec[i] = to_le(reset_vec[i]); + } + + std::vector<char> rom((char*)reset_vec, (char*)reset_vec + sizeof(reset_vec)); + + rom.insert(rom.end(), dtb.begin(), dtb.end()); + const int align = 0x1000; + rom.resize((rom.size() + align - 1) / align * align); + + boot_rom.reset(new rom_device_t(rom)); + bus.add_device(DEFAULT_RSTVEC, boot_rom.get()); +} + +char* sim_t::addr_to_mem(reg_t paddr) { + if (!paddr_ok(paddr)) + return NULL; + auto desc = bus.find_device(paddr); + if (auto mem = dynamic_cast<mem_t*>(desc.second)) + if (paddr - desc.first < mem->size()) + return mem->contents(paddr - desc.first); + return NULL; +} + +const char* sim_t::get_symbol(uint64_t paddr) +{ + return htif_t::get_symbol(paddr); +} + +// htif + +void sim_t::reset() +{ + if (dtb_enabled) + set_rom(); +} + +void sim_t::idle() +{ + if (done()) + return; + + if (debug || ctrlc_pressed) + interactive(); + else + step(INTERLEAVE); + + if (remote_bitbang) + remote_bitbang->tick(); +} + +void sim_t::read_chunk(addr_t taddr, size_t len, void* dst) +{ + assert(len == 8); + auto data = debug_mmu->to_target(debug_mmu->load<uint64_t>(taddr)); + memcpy(dst, &data, sizeof data); +} + +void sim_t::write_chunk(addr_t taddr, size_t len, const void* src) +{ + assert(len == 8); + target_endian<uint64_t> data; + memcpy(&data, src, sizeof data); + debug_mmu->store<uint64_t>(taddr, debug_mmu->from_target(data)); +} + +endianness_t sim_t::get_target_endianness() const +{ + return debug_mmu->is_target_big_endian()? endianness_big : endianness_little; +} + +void sim_t::proc_reset(unsigned id) +{ + debug_module.proc_reset(id); +} diff --git a/vendor/riscv/riscv-isa-sim/riscv/sim.h b/vendor/riscv/riscv-isa-sim/riscv/sim.h new file mode 100644 index 0000000000..377e96514c --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/sim.h @@ -0,0 +1,161 @@ +// See LICENSE for license details. + +#ifndef _RISCV_SIM_H +#define _RISCV_SIM_H + +#include "cfg.h" +#include "debug_module.h" +#include "devices.h" +#include "log_file.h" +#include "processor.h" +#include "simif.h" + +#include <fesvr/htif.h> +#include <vector> +#include <map> +#include <string> +#include <memory> +#include <sys/types.h> + +class mmu_t; +class remote_bitbang_t; +class socketif_t; + +// this class encapsulates the processors and memory in a RISC-V machine. +class sim_t : public htif_t, public simif_t +{ +public: + sim_t(const cfg_t *cfg, bool halted, + std::vector<std::pair<reg_t, mem_t*>> mems, + std::vector<std::pair<reg_t, abstract_device_t*>> plugin_devices, + const std::vector<std::string>& args, + const debug_module_config_t &dm_config, const char *log_path, + bool dtb_enabled, const char *dtb_file, + bool socket_enabled, + FILE *cmd_file, // needed for command line option --cmd + size_t max_steps); + ~sim_t(); + + // run the simulation to completion + int run(); + void set_debug(bool value); + void set_histogram(bool value); + + // Configure logging + // + // If enable_log is true, an instruction trace will be generated. If + // enable_commitlog is true, so will the commit results + void configure_log(bool enable_log, bool enable_commitlog); + + void set_procs_debug(bool value); + void set_remote_bitbang(remote_bitbang_t* remote_bitbang) { + this->remote_bitbang = remote_bitbang; + } + const char* get_dts() { return dts.c_str(); } + processor_t* get_core(size_t i) { return procs.at(i); } + virtual const cfg_t &get_cfg() const override { return *cfg; } + + virtual const std::map<size_t, processor_t*>& get_harts() const override { return harts; } + + // Callback for processors to let the simulation know they were reset. + virtual void proc_reset(unsigned id) override; + +private: + isa_parser_t isa; + const cfg_t * const cfg; + std::vector<std::pair<reg_t, mem_t*>> mems; + std::vector<std::pair<reg_t, abstract_device_t*>> plugin_devices; + std::vector<processor_t*> procs; + std::map<size_t, processor_t*> harts; + std::pair<reg_t, reg_t> initrd_range; + std::string dts; + std::string dtb; + bool dtb_enabled; + std::unique_ptr<rom_device_t> boot_rom; + std::unique_ptr<clint_t> clint; + std::unique_ptr<plic_t> plic; + std::unique_ptr<ns16550_t> ns16550; + bus_t bus; + log_file_t log_file; + + FILE *cmd_file; // pointer to debug command input file + + socketif_t *socketif; + std::ostream sout_; // used for socket and terminal interface + + processor_t* get_core(const std::string& i); + void step(size_t n); // step through simulation + static const size_t INTERLEAVE = 5000; + static const size_t INSNS_PER_RTC_TICK = 100; // 10 MHz clock for 1 BIPS core + static const size_t CPU_HZ = 1000000000; // 1GHz CPU + size_t current_step; + size_t total_steps; + size_t max_steps; + size_t current_proc; + bool debug; + bool histogram_enabled; // provide a histogram of PCs + bool log; + remote_bitbang_t* remote_bitbang; + std::optional<std::function<void()>> next_interactive_action; + + // memory-mapped I/O routines + virtual char* addr_to_mem(reg_t paddr) override; + virtual bool mmio_load(reg_t paddr, size_t len, uint8_t* bytes) override; + virtual bool mmio_store(reg_t paddr, size_t len, const uint8_t* bytes) override; + void make_dtb(const char* dtb_file); + void set_rom(); + + virtual const char* get_symbol(uint64_t paddr) override; + + // presents a prompt for introspection into the simulation + void interactive(); + + // functions that help implement interactive() + void interactive_help(const std::string& cmd, const std::vector<std::string>& args); + void interactive_quit(const std::string& cmd, const std::vector<std::string>& args); + void interactive_run(const std::string& cmd, const std::vector<std::string>& args, bool noisy); + void interactive_run_noisy(const std::string& cmd, const std::vector<std::string>& args); + void interactive_run_silent(const std::string& cmd, const std::vector<std::string>& args); + void interactive_vreg(const std::string& cmd, const std::vector<std::string>& args); + void interactive_reg(const std::string& cmd, const std::vector<std::string>& args); + void interactive_freg(const std::string& cmd, const std::vector<std::string>& args); + void interactive_fregh(const std::string& cmd, const std::vector<std::string>& args); + void interactive_fregs(const std::string& cmd, const std::vector<std::string>& args); + void interactive_fregd(const std::string& cmd, const std::vector<std::string>& args); + void interactive_pc(const std::string& cmd, const std::vector<std::string>& args); + void interactive_priv(const std::string& cmd, const std::vector<std::string>& args); + void interactive_mem(const std::string& cmd, const std::vector<std::string>& args); + void interactive_str(const std::string& cmd, const std::vector<std::string>& args); + void interactive_dumpmems(const std::string& cmd, const std::vector<std::string>& args); + void interactive_mtime(const std::string& cmd, const std::vector<std::string>& args); + void interactive_mtimecmp(const std::string& cmd, const std::vector<std::string>& args); + void interactive_until(const std::string& cmd, const std::vector<std::string>& args, bool noisy); + void interactive_until_silent(const std::string& cmd, const std::vector<std::string>& args); + void interactive_until_noisy(const std::string& cmd, const std::vector<std::string>& args); + reg_t get_reg(const std::vector<std::string>& args); + freg_t get_freg(const std::vector<std::string>& args, int size); + reg_t get_mem(const std::vector<std::string>& args); + reg_t get_pc(const std::vector<std::string>& args); + + friend class processor_t; + friend class mmu_t; + + // htif + virtual void reset() override; + virtual void idle() override; + virtual void read_chunk(addr_t taddr, size_t len, void* dst) override; + virtual void write_chunk(addr_t taddr, size_t len, const void* src) override; + virtual size_t chunk_align() override { return 8; } + virtual size_t chunk_max_size() override { return 8; } + virtual endianness_t get_target_endianness() const override; + +public: + // Initialize this after procs, because in debug_module_t::reset() we + // enumerate processors, which segfaults if procs hasn't been initialized + // yet. + debug_module_t debug_module; +}; + +extern volatile bool ctrlc_pressed; + +#endif diff --git a/vendor/riscv/riscv-isa-sim/riscv/simif.h b/vendor/riscv/riscv-isa-sim/riscv/simif.h new file mode 100644 index 0000000000..aeab5dba77 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/simif.h @@ -0,0 +1,39 @@ +// See LICENSE for license details. + +#ifndef _RISCV_SIMIF_H +#define _RISCV_SIMIF_H + +#include <map> +#include "decode.h" +#include "cfg.h" + +class processor_t; +class mmu_t; + +// this is the interface to the simulator used by the processors and memory +class simif_t +{ +public: + // should return NULL for MMIO addresses + virtual char* addr_to_mem(reg_t paddr) = 0; + virtual bool reservable(reg_t paddr) { return addr_to_mem(paddr); } + // used for MMIO addresses + virtual bool mmio_fetch(reg_t paddr, size_t len, uint8_t* bytes) { return mmio_load(paddr, len, bytes); } + virtual bool mmio_load(reg_t paddr, size_t len, uint8_t* bytes) = 0; + virtual bool mmio_store(reg_t paddr, size_t len, const uint8_t* bytes) = 0; + // Callback for processors to let the simulation know they were reset. + virtual void proc_reset(unsigned id) = 0; + + virtual const cfg_t &get_cfg() const = 0; + virtual const std::map<size_t, processor_t*>& get_harts() const = 0; + + virtual const char* get_symbol(uint64_t paddr) = 0; + + virtual ~simif_t() = default; + + unsigned nprocs() const { return get_cfg().nprocs(); } + + mmu_t* debug_mmu; // debug port into main memory, for use by debug_module +}; + +#endif diff --git a/vendor/riscv/riscv-isa-sim/riscv/socketif.cc b/vendor/riscv/riscv-isa-sim/riscv/socketif.cc new file mode 100644 index 0000000000..0884752597 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/socketif.cc @@ -0,0 +1,74 @@ +// See LICENSE for license details. + +#include "socketif.h" + +#ifdef HAVE_BOOST_ASIO + +#include <iostream> + +socketif_t::socketif_t() +{ + try { // create socket server + using boost::asio::ip::tcp; + io_service_ptr = new boost::asio::io_service; + acceptor_ptr = new tcp::acceptor(*io_service_ptr, tcp::endpoint(tcp::v4(), 0)); + // acceptor is created passing argument port=0, so O.S. will choose a free port + std::string name = boost::asio::ip::host_name(); + std::cout << "Listening for debug commands on " << name.substr(0,name.find('.')) + << " port " << acceptor_ptr->local_endpoint().port() << " ." << std::endl; + // at the end, add space and some other character for convenience of javascript .split(" ") + } catch (std::exception& e) { + std::cerr << e.what() << std::endl; + exit(-1); + } +} + +socketif_t::~socketif_t() +{ + delete io_service_ptr; + delete acceptor_ptr; +} + +// read input command string +std::string socketif_t::rin(std::ostream &sout_) +{ + std::string s; + try { + socket_ptr.reset(new boost::asio::ip::tcp::socket(*io_service_ptr)); + acceptor_ptr->accept(*socket_ptr); // wait for someone to open connection + boost::asio::streambuf buf; + boost::asio::read_until(*socket_ptr, buf, "\n"); // wait for command + s = boost::asio::buffer_cast<const char*>(buf.data()); + boost::erase_all(s, "\r"); // get rid off any cr and lf + boost::erase_all(s, "\n"); + // The socket client is a web server and it appends the IP of the computer + // that sent the command from its web browser. + + // For now, erase the IP if it is there. + boost::regex re(" ((25[0-5]|2[0-4][0-9]|[01]?[0-9]?[0-9])\\.){3}" + "(25[0-5]|2[0-4][0-9]|[01]?[0-9]?[0-9])$"); + s = boost::regex_replace(s, re, (std::string)""); + + // TODO: check the IP against the IP used to upload RISC-V source files + } catch (std::exception& e) { + std::cerr << e.what() << std::endl; + } + // output goes to socket + sout_.rdbuf(&bout); + return s; +} + +// write sout_ to socket (via bout) +void socketif_t::wout() { + try { + boost::system::error_code ignored_error; + boost::asio::write(*socket_ptr, bout, boost::asio::transfer_all(), ignored_error); + socket_ptr->close(); // close the socket after each command input/ouput + // This is need to in order to make the socket interface + // acessible by HTTP GET via a socket client in a web server. + } catch (std::exception& e) { + std::cerr << e.what() << std::endl; + } +} + +#endif diff --git a/vendor/riscv/riscv-isa-sim/riscv/socketif.h b/vendor/riscv/riscv-isa-sim/riscv/socketif.h new file mode 100644 index 0000000000..7ce9142d3f --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/socketif.h @@ -0,0 +1,32 @@ +// See LICENSE for license details. + +#ifndef _RISCV_SOCKETIF_H +#define _RISCV_SOCKETIF_H + +#include "config.h" + +#ifdef HAVE_BOOST_ASIO + +#include <boost/algorithm/string.hpp> +#include <boost/regex.hpp> +#include <boost/asio.hpp> + +class socketif_t +{ +public: + socketif_t(); + ~socketif_t(); + + std::string rin(std::ostream &sout_); // read input command string + void wout(); // write output to socket + +private: + // the following are needed for command socket interface + boost::asio::io_service *io_service_ptr; + boost::asio::ip::tcp::acceptor *acceptor_ptr; + std::unique_ptr<boost::asio::ip::tcp::socket> socket_ptr; + boost::asio::streambuf bout; +}; + +#endif +#endif diff --git a/vendor/riscv/riscv-isa-sim/riscv/tracer.h b/vendor/riscv/riscv-isa-sim/riscv/tracer.h new file mode 100644 index 0000000000..d74edae901 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/tracer.h @@ -0,0 +1,11 @@ +// See LICENSE for license details. + +#ifndef _RISCV_TRACER_H +#define _RISCV_TRACER_H + +#include "processor.h" + +static inline void trace_opcode(processor_t UNUSED *p, insn_bits_t UNUSED opc, insn_t UNUSED insn) { +} + +#endif diff --git a/vendor/riscv/riscv-isa-sim/riscv/trap.h b/vendor/riscv/riscv-isa-sim/riscv/trap.h new file mode 100644 index 0000000000..78b549cfed --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/trap.h @@ -0,0 +1,130 @@ +// See LICENSE for license details. + +#ifndef _RISCV_TRAP_H +#define _RISCV_TRAP_H + +#include "decode.h" +#include "encoding.h" +#include <string> + +struct state_t; + +class trap_debug_mode +{ + /* Used to enter debug mode, which isn't quite a normal trap. */ +}; + +class trap_t +{ + public: + trap_t(reg_t which) : which(which) {} + virtual bool has_gva() { return false; } + virtual bool has_tval() { return false; } + virtual reg_t get_tval() { return 0; } + virtual bool has_tval2() { return false; } + virtual reg_t get_tval2() { return 0; } + virtual bool has_tinst() { return false; } + virtual reg_t get_tinst() { return 0; } + reg_t cause() const { return which; } + + virtual std::string name() + { + const uint8_t code = uint8_t(which); + const bool is_interrupt = code != which; + return (is_interrupt ? "interrupt #" : "trap #") + std::to_string(code); + } + + virtual ~trap_t() = default; + + private: + reg_t which; +}; + +class insn_trap_t : public trap_t +{ + public: + insn_trap_t(reg_t which, bool gva, reg_t tval) + : trap_t(which), gva(gva), tval(tval) {} + bool has_gva() override { return gva; } + bool has_tval() override { return true; } + reg_t get_tval() override { return tval; } + private: + bool gva; + reg_t tval; +}; + +class mem_trap_t : public trap_t +{ + public: + mem_trap_t(reg_t which, bool gva, reg_t tval, reg_t tval2, reg_t tinst) + : trap_t(which), gva(gva), tval(tval), tval2(tval2), tinst(tinst) {} + bool has_gva() override { return gva; } + bool has_tval() override { return true; } + reg_t get_tval() override { return tval; } + bool has_tval2() override { return true; } + reg_t get_tval2() override { return tval2; } + bool has_tinst() override { return true; } + reg_t get_tinst() override { return tinst; } + private: + bool gva; + reg_t tval, tval2, tinst; +}; + +#define DECLARE_TRAP(n, x) class trap_##x : public trap_t { \ + public: \ + trap_##x() : trap_t(n) {} \ + std::string name() { return "trap_"#x; } \ +}; + +#define DECLARE_INST_TRAP(n, x) class trap_##x : public insn_trap_t { \ + public: \ + trap_##x(reg_t tval) : insn_trap_t(n, /*gva*/false, tval) {} \ + std::string name() { return "trap_"#x; } \ +}; + +#define DECLARE_CUSTOM_TRAP(x) class trap_##x : public insn_trap_t { \ + public: \ + trap_##x(reg_t n, reg_t tval) : insn_trap_t(n, false, tval) {} \ + std::string name() { return "trap_"#x; } \ +}; + +#define DECLARE_INST_WITH_GVA_TRAP(n, x) class trap_##x : public insn_trap_t { \ + public: \ + trap_##x(bool gva, reg_t tval) : insn_trap_t(n, gva, tval) {} \ + std::string name() { return "trap_"#x; } \ +}; + +#define DECLARE_MEM_TRAP(n, x) class trap_##x : public mem_trap_t { \ + public: \ + trap_##x(bool gva, reg_t tval, reg_t tval2, reg_t tinst) : mem_trap_t(n, gva, tval, tval2, tinst) {} \ + std::string name() { return "trap_"#x; } \ +}; + +#define DECLARE_MEM_GVA_TRAP(n, x) class trap_##x : public mem_trap_t { \ + public: \ + trap_##x(reg_t tval, reg_t tval2, reg_t tinst) : mem_trap_t(n, true, tval, tval2, tinst) {} \ + std::string name() { return "trap_"#x; } \ +}; + +DECLARE_MEM_TRAP(CAUSE_MISALIGNED_FETCH, instruction_address_misaligned) +DECLARE_MEM_TRAP(CAUSE_FETCH_ACCESS, instruction_access_fault) +DECLARE_INST_TRAP(CAUSE_ILLEGAL_INSTRUCTION, illegal_instruction) +DECLARE_INST_WITH_GVA_TRAP(CAUSE_BREAKPOINT, breakpoint) +DECLARE_MEM_TRAP(CAUSE_MISALIGNED_LOAD, load_address_misaligned) +DECLARE_MEM_TRAP(CAUSE_MISALIGNED_STORE, store_address_misaligned) +DECLARE_MEM_TRAP(CAUSE_LOAD_ACCESS, load_access_fault) +DECLARE_MEM_TRAP(CAUSE_STORE_ACCESS, store_access_fault) +DECLARE_TRAP(CAUSE_USER_ECALL, user_ecall) +DECLARE_TRAP(CAUSE_SUPERVISOR_ECALL, supervisor_ecall) +DECLARE_TRAP(CAUSE_VIRTUAL_SUPERVISOR_ECALL, virtual_supervisor_ecall) +DECLARE_TRAP(CAUSE_MACHINE_ECALL, machine_ecall) +DECLARE_MEM_TRAP(CAUSE_FETCH_PAGE_FAULT, instruction_page_fault) +DECLARE_MEM_TRAP(CAUSE_LOAD_PAGE_FAULT, load_page_fault) +DECLARE_MEM_TRAP(CAUSE_STORE_PAGE_FAULT, store_page_fault) +DECLARE_MEM_GVA_TRAP(CAUSE_FETCH_GUEST_PAGE_FAULT, instruction_guest_page_fault) +DECLARE_MEM_GVA_TRAP(CAUSE_LOAD_GUEST_PAGE_FAULT, load_guest_page_fault) +DECLARE_INST_TRAP(CAUSE_VIRTUAL_INSTRUCTION, virtual_instruction) +DECLARE_MEM_GVA_TRAP(CAUSE_STORE_GUEST_PAGE_FAULT, store_guest_page_fault) +DECLARE_CUSTOM_TRAP(unknown_instruction) + +#endif diff --git a/vendor/riscv/riscv-isa-sim/riscv/triggers.cc b/vendor/riscv/riscv-isa-sim/riscv/triggers.cc new file mode 100644 index 0000000000..86dcc81a11 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/triggers.cc @@ -0,0 +1,620 @@ +#include "arith.h" +#include "debug_defines.h" +#include "processor.h" +#include "triggers.h" + +#define ASIDMAX(SXLEN) (SXLEN == 32 ? 9 : 16) +#define SATP_ASID(SXLEN) (SXLEN == 32 ? SATP32_ASID : SATP64_ASID) +#define VMIDMAX(HSXLEN) (HSXLEN == 32 ? 7 : 14) +#define HGATP_VMID(HSXLEN) (HSXLEN == 32 ? HGATP32_VMID : HGATP64_VMID) + +#define CSR_TEXTRA_MHVALUE_LENGTH(XLEN) (XLEN == 32 ? CSR_TEXTRA32_MHVALUE_LENGTH : CSR_TEXTRA64_MHVALUE_LENGTH) +#define CSR_TEXTRA_MHVALUE(XLEN) (XLEN == 32 ? CSR_TEXTRA32_MHVALUE : CSR_TEXTRA64_MHVALUE) +#define CSR_TEXTRA_MHSELECT(XLEN) (XLEN == 32 ? CSR_TEXTRA32_MHSELECT : CSR_TEXTRA64_MHSELECT) +#define CSR_TEXTRA_SBYTEMASK(XLEN) (XLEN == 32 ? CSR_TEXTRA32_SBYTEMASK : CSR_TEXTRA64_SBYTEMASK) +#define CSR_TEXTRA_SVALUE(XLEN) (XLEN == 32 ? CSR_TEXTRA32_SVALUE : CSR_TEXTRA64_SVALUE) +#define CSR_TEXTRA_SSELECT(XLEN) (XLEN == 32 ? CSR_TEXTRA32_SSELECT : CSR_TEXTRA64_SSELECT) + +namespace triggers { + +reg_t trigger_t::tdata2_read(const processor_t UNUSED * const proc) const noexcept { + return tdata2; +} + +void trigger_t::tdata2_write(processor_t UNUSED * const proc, const reg_t UNUSED val) noexcept { + tdata2 = val; +} + +action_t trigger_t::legalize_action(reg_t val, reg_t action_mask, reg_t dmode_mask) noexcept { + reg_t act = get_field(val, action_mask); + return (act > ACTION_MAXVAL || (act == ACTION_DEBUG_MODE && get_field(val, dmode_mask) == 0)) ? ACTION_DEBUG_EXCEPTION : (action_t)act; +} + +unsigned trigger_t::legalize_mhselect(bool h_enabled) const noexcept { + const auto interp = interpret_mhselect(h_enabled); + return interp.mhselect; +} + +reg_t trigger_t::tdata3_read(const processor_t * const proc) const noexcept { + auto xlen = proc->get_xlen(); + reg_t tdata3 = 0; + tdata3 = set_field(tdata3, CSR_TEXTRA_MHVALUE(xlen), mhvalue); + tdata3 = set_field(tdata3, CSR_TEXTRA_MHSELECT(xlen), legalize_mhselect(proc->extension_enabled('H'))); + tdata3 = set_field(tdata3, CSR_TEXTRA_SBYTEMASK(xlen), sbytemask); + tdata3 = set_field(tdata3, CSR_TEXTRA_SVALUE(xlen), svalue); + tdata3 = set_field(tdata3, CSR_TEXTRA_SSELECT(xlen), sselect); + return tdata3; +} + +void trigger_t::tdata3_write(processor_t * const proc, const reg_t val) noexcept { + auto xlen = proc->get_xlen(); + mhvalue = get_field(val, CSR_TEXTRA_MHVALUE(xlen)); + mhselect = get_field(val, CSR_TEXTRA_MHSELECT(xlen)); + sbytemask = get_field(val, CSR_TEXTRA_SBYTEMASK(xlen)); + svalue = proc->extension_enabled_const('S') ? get_field(val, CSR_TEXTRA_SVALUE(xlen)) : 0; + sselect = (sselect_t)((proc->extension_enabled_const('S') && get_field(val, CSR_TEXTRA_SSELECT(xlen)) <= SSELECT_MAXVAL) ? get_field(val, CSR_TEXTRA_SSELECT(xlen)) : SSELECT_IGNORE); +} + +bool trigger_t::common_match(processor_t * const proc) const noexcept { + return mode_match(proc->get_state()) && textra_match(proc); +} + +bool trigger_t::mode_match(state_t * const state) const noexcept +{ + switch (state->prv) { + case PRV_M: return m; + case PRV_S: return state->v ? vs : s; + case PRV_U: return state->v ? vu : u; + default: assert(false); + } +} + +bool trigger_t::textra_match(processor_t * const proc) const noexcept +{ + auto xlen = proc->get_xlen(); + auto hsxlen = proc->get_xlen(); // use xlen since no hsxlen + state_t * const state = proc->get_state(); + + assert(sselect <= SSELECT_MAXVAL); + if (sselect == SSELECT_SCONTEXT) { + reg_t mask = (reg_t(1) << ((xlen == 32) ? CSR_TEXTRA32_SVALUE_LENGTH : CSR_TEXTRA64_SVALUE_LENGTH)) - 1; + assert(CSR_TEXTRA32_SBYTEMASK_LENGTH < CSR_TEXTRA64_SBYTEMASK_LENGTH); + for (int i = 0; i < CSR_TEXTRA64_SBYTEMASK_LENGTH; i++) + if (sbytemask & (1 << i)) + mask &= 0xff << (i * 8); + if ((state->scontext->read() & mask) != (svalue & mask)) + return false; + } else if (sselect == SSELECT_ASID) { + const reg_t satp = state->satp->read(); + const reg_t asid = get_field(satp, SATP_ASID(xlen)); + if (asid != (svalue & ((1 << ASIDMAX(xlen)) - 1))) + return false; + } + + const auto mhselect_interp = interpret_mhselect(proc->extension_enabled('H')); + const mhselect_mode_t mode = mhselect_interp.mode; + if (mode == MHSELECT_MODE_MCONTEXT) { // 4, 1, and 5 are mcontext + reg_t mask = (1 << (CSR_TEXTRA_MHVALUE_LENGTH(xlen) + 1)) - 1; + if ((state->mcontext->read() & mask) != mhselect_interp.compare_val(mhvalue)) + return false; + } else if (mode == MHSELECT_MODE_VMID) { // 2 and 6 are vmid + const reg_t vmid = get_field(state->hgatp->read(), HGATP_VMID(hsxlen)); + if (vmid != (mhselect_interp.compare_val(mhvalue) & ((1 << VMIDMAX(hsxlen)) - 1))) + return false; + } + + return true; +} + +bool trigger_t::allow_action(const state_t * const state) const +{ + if (get_action() == ACTION_DEBUG_EXCEPTION) { + const bool mstatus_mie = state->mstatus->read() & MSTATUS_MIE; + const bool sstatus_sie = state->sstatus->read() & MSTATUS_SIE; + const bool vsstatus_sie = state->vsstatus->read() & MSTATUS_SIE; + const bool medeleg_breakpoint = (state->medeleg->read() >> CAUSE_BREAKPOINT) & 1; + const bool hedeleg_breakpoint = (state->hedeleg->read() >> CAUSE_BREAKPOINT) & 1; + return (state->prv != PRV_M || mstatus_mie) && + (state->prv != PRV_S || state->v || !medeleg_breakpoint || sstatus_sie) && + (state->prv != PRV_S || !state->v || !medeleg_breakpoint || !hedeleg_breakpoint || vsstatus_sie); + } + return true; +} + +reg_t disabled_trigger_t::tdata1_read(const processor_t * const proc) const noexcept +{ + auto xlen = proc->get_xlen(); + reg_t tdata1 = 0; + tdata1 = set_field(tdata1, CSR_TDATA1_TYPE(xlen), CSR_TDATA1_TYPE_DISABLED); + tdata1 = set_field(tdata1, CSR_TDATA1_DMODE(xlen), dmode); + return tdata1; +} + +void disabled_trigger_t::tdata1_write(processor_t * const proc, const reg_t val, const bool UNUSED allow_chain) noexcept +{ + // Any supported tdata.type results in disabled trigger + auto xlen = proc->get_xlen(); + dmode = get_field(val, CSR_TDATA1_DMODE(xlen)); +} + +reg_t mcontrol_t::tdata1_read(const processor_t * const proc) const noexcept { + reg_t v = 0; + auto xlen = proc->get_xlen(); + v = set_field(v, MCONTROL_TYPE(xlen), CSR_TDATA1_TYPE_MCONTROL); + v = set_field(v, CSR_MCONTROL_DMODE(xlen), dmode); + v = set_field(v, MCONTROL_MASKMAX(xlen), 0); + v = set_field(v, CSR_MCONTROL_HIT, hit); + v = set_field(v, MCONTROL_SELECT, select); + v = set_field(v, MCONTROL_TIMING, timing); + v = set_field(v, MCONTROL_ACTION, action); + v = set_field(v, MCONTROL_CHAIN, chain); + v = set_field(v, MCONTROL_MATCH, match); + v = set_field(v, MCONTROL_M, m); + v = set_field(v, MCONTROL_S, s); + v = set_field(v, MCONTROL_U, u); + v = set_field(v, MCONTROL_EXECUTE, execute); + v = set_field(v, MCONTROL_STORE, store); + v = set_field(v, MCONTROL_LOAD, load); + return v; +} + +void mcontrol_t::tdata1_write(processor_t * const proc, const reg_t val, const bool allow_chain) noexcept { + auto xlen = proc->get_xlen(); + assert(get_field(val, CSR_MCONTROL_TYPE(xlen)) == CSR_TDATA1_TYPE_MCONTROL); + dmode = get_field(val, CSR_MCONTROL_DMODE(xlen)); + hit = get_field(val, CSR_MCONTROL_HIT); + select = get_field(val, MCONTROL_SELECT); + timing = legalize_timing(val, MCONTROL_TIMING, MCONTROL_SELECT, MCONTROL_EXECUTE, MCONTROL_LOAD); + action = legalize_action(val, MCONTROL_ACTION, CSR_MCONTROL_DMODE(xlen)); + chain = allow_chain ? get_field(val, MCONTROL_CHAIN) : 0; + match = legalize_match(get_field(val, MCONTROL_MATCH)); + m = get_field(val, MCONTROL_M); + s = proc->extension_enabled_const('S') ? get_field(val, CSR_MCONTROL_S) : 0; + u = proc->extension_enabled_const('U') ? get_field(val, CSR_MCONTROL_U) : 0; + execute = get_field(val, MCONTROL_EXECUTE); + store = get_field(val, MCONTROL_STORE); + load = get_field(val, MCONTROL_LOAD); +} + +bool mcontrol_common_t::simple_match(unsigned xlen, reg_t value) const { + switch (match) { + case MATCH_EQUAL: + return value == tdata2; + case MATCH_NAPOT: + { + reg_t mask = ~((1 << (cto(tdata2)+1)) - 1); + return (value & mask) == (tdata2 & mask); + } + case MATCH_GE: + return value >= tdata2; + case MATCH_LT: + return value < tdata2; + case MATCH_MASK_LOW: + { + reg_t mask = tdata2 >> (xlen/2); + return (value & mask) == (tdata2 & mask); + } + case MATCH_MASK_HIGH: + { + reg_t mask = tdata2 >> (xlen/2); + return ((value >> (xlen/2)) & mask) == (tdata2 & mask); + } + } + assert(0); +} + +std::optional<match_result_t> mcontrol_common_t::detect_memory_access_match(processor_t * const proc, operation_t operation, reg_t address, std::optional<reg_t> data) noexcept { + if ((operation == triggers::OPERATION_EXECUTE && !execute) || + (operation == triggers::OPERATION_STORE && !store) || + (operation == triggers::OPERATION_LOAD && !load) || + !common_match(proc)) { + return std::nullopt; + } + + reg_t value; + if (select) { + if (!data.has_value()) + return std::nullopt; + value = *data; + } else { + value = address; + } + + // We need this because in 32-bit mode sometimes the PC bits get sign + // extended. + auto xlen = proc->get_xlen(); + if (xlen == 32) { + value &= 0xffffffff; + } + + if (simple_match(xlen, value) && allow_action(proc->get_state())) { + /* This is OK because this function is only called if the trigger was not + * inhibited by the previous trigger in the chain. */ + hit = true; + return match_result_t(timing_t(timing), action); + } + return std::nullopt; +} + +mcontrol_common_t::match_t mcontrol_common_t::legalize_match(reg_t val) noexcept +{ + switch (val) { + case MATCH_EQUAL: + case MATCH_NAPOT: + case MATCH_GE: + case MATCH_LT: + case MATCH_MASK_LOW: + case MATCH_MASK_HIGH: + return (match_t)val; + default: + return MATCH_EQUAL; + } +} + +bool mcontrol_common_t::legalize_timing(reg_t val, reg_t timing_mask, reg_t select_mask, reg_t execute_mask, reg_t load_mask) noexcept { + // For load data triggers, force timing=after to avoid debugger having to repeat loads which may have side effects. + if (get_field(val, select_mask) && get_field(val, load_mask)) + return TIMING_AFTER; + if (get_field(val, execute_mask)) + return TIMING_BEFORE; + return get_field(val, timing_mask); +} + +reg_t mcontrol6_t::tdata1_read(const processor_t * const proc) const noexcept { + unsigned xlen = proc->get_const_xlen(); + reg_t tdata1 = 0; + tdata1 = set_field(tdata1, CSR_MCONTROL6_TYPE(xlen), CSR_TDATA1_TYPE_MCONTROL6); + tdata1 = set_field(tdata1, CSR_MCONTROL6_DMODE(xlen), dmode); + tdata1 = set_field(tdata1, CSR_MCONTROL6_VS, proc->extension_enabled('H') ? vs : 0); + tdata1 = set_field(tdata1, CSR_MCONTROL6_VU, proc->extension_enabled('H') ? vu : 0); + tdata1 = set_field(tdata1, CSR_MCONTROL6_HIT, hit); + tdata1 = set_field(tdata1, CSR_MCONTROL6_SELECT, select); + tdata1 = set_field(tdata1, CSR_MCONTROL6_TIMING, timing); + tdata1 = set_field(tdata1, CSR_MCONTROL6_ACTION, action); + tdata1 = set_field(tdata1, CSR_MCONTROL6_CHAIN, chain); + tdata1 = set_field(tdata1, CSR_MCONTROL6_MATCH, match); + tdata1 = set_field(tdata1, CSR_MCONTROL6_M, m); + tdata1 = set_field(tdata1, CSR_MCONTROL6_S, s); + tdata1 = set_field(tdata1, CSR_MCONTROL6_U, u); + tdata1 = set_field(tdata1, CSR_MCONTROL6_EXECUTE, execute); + tdata1 = set_field(tdata1, CSR_MCONTROL6_STORE, store); + tdata1 = set_field(tdata1, CSR_MCONTROL6_LOAD, load); + return tdata1; +} + +void mcontrol6_t::tdata1_write(processor_t * const proc, const reg_t val, const bool allow_chain) noexcept { + auto xlen = proc->get_const_xlen(); + assert(get_field(val, CSR_MCONTROL6_TYPE(xlen)) == CSR_TDATA1_TYPE_MCONTROL6); + dmode = get_field(val, CSR_MCONTROL6_DMODE(xlen)); + vs = get_field(val, CSR_MCONTROL6_VS); + vu = get_field(val, CSR_MCONTROL6_VU); + hit = get_field(val, CSR_MCONTROL6_HIT); + select = get_field(val, CSR_MCONTROL6_SELECT); + timing = legalize_timing(val, CSR_MCONTROL6_TIMING, CSR_MCONTROL6_SELECT, CSR_MCONTROL6_EXECUTE, CSR_MCONTROL6_LOAD); + action = legalize_action(val, CSR_MCONTROL6_ACTION, CSR_MCONTROL6_DMODE(xlen)); + chain = allow_chain ? get_field(val, CSR_MCONTROL6_CHAIN) : 0; + match = legalize_match(get_field(val, CSR_MCONTROL6_MATCH)); + m = get_field(val, CSR_MCONTROL6_M); + s = proc->extension_enabled_const('S') ? get_field(val, CSR_MCONTROL6_S) : 0; + u = proc->extension_enabled_const('U') ? get_field(val, CSR_MCONTROL6_U) : 0; + execute = get_field(val, CSR_MCONTROL6_EXECUTE); + store = get_field(val, CSR_MCONTROL6_STORE); + load = get_field(val, CSR_MCONTROL6_LOAD); +} + +std::optional<match_result_t> icount_t::detect_icount_match(processor_t * const proc) noexcept +{ + if (!common_match(proc) || !allow_action(proc->get_state())) + return std::nullopt; + + std::optional<match_result_t> ret = std::nullopt; + if (pending) { + pending = 0; + hit = true; + ret = match_result_t(TIMING_BEFORE, action); + } + + if (count >= 1) { + if (count == 1) + pending = 1; + count = count - 1; + } + + return ret; +} + +reg_t icount_t::tdata1_read(const processor_t * const proc) const noexcept +{ + auto xlen = proc->get_xlen(); + reg_t tdata1 = 0; + tdata1 = set_field(tdata1, CSR_ICOUNT_TYPE(xlen), CSR_TDATA1_TYPE_ICOUNT); + tdata1 = set_field(tdata1, CSR_ICOUNT_DMODE(xlen), dmode); + tdata1 = set_field(tdata1, CSR_ICOUNT_VS, proc->extension_enabled('H') ? vs : 0); + tdata1 = set_field(tdata1, CSR_ICOUNT_VU, proc->extension_enabled('H') ? vu : 0); + tdata1 = set_field(tdata1, CSR_ICOUNT_HIT, hit); + tdata1 = set_field(tdata1, CSR_ICOUNT_COUNT, count_read_value); + tdata1 = set_field(tdata1, CSR_ICOUNT_M, m); + tdata1 = set_field(tdata1, CSR_ICOUNT_PENDING, pending_read_value); + tdata1 = set_field(tdata1, CSR_ICOUNT_S, s); + tdata1 = set_field(tdata1, CSR_ICOUNT_U, u); + tdata1 = set_field(tdata1, CSR_ICOUNT_ACTION, action); + return tdata1; +} + +void icount_t::tdata1_write(processor_t * const proc, const reg_t val, const bool UNUSED allow_chain) noexcept +{ + auto xlen = proc->get_xlen(); + assert(get_field(val, CSR_ICOUNT_TYPE(xlen)) == CSR_TDATA1_TYPE_ICOUNT); + dmode = proc->get_state()->debug_mode ? get_field(val, CSR_ICOUNT_DMODE(xlen)) : 0; + vs = get_field(val, CSR_ICOUNT_VS); + vu = get_field(val, CSR_ICOUNT_VU); + hit = get_field(val, CSR_ICOUNT_HIT); + count = count_read_value = get_field(val, CSR_ICOUNT_COUNT); + m = get_field(val, CSR_ICOUNT_M); + pending = pending_read_value = get_field(val, CSR_ICOUNT_PENDING); + s = proc->extension_enabled_const('S') ? get_field(val, CSR_ICOUNT_S) : 0; + u = proc->extension_enabled_const('U') ? get_field(val, CSR_ICOUNT_U) : 0; + action = legalize_action(val, CSR_ICOUNT_ACTION, CSR_ICOUNT_DMODE(xlen)); +} + +void icount_t::stash_read_values() +{ + count_read_value = count; + pending_read_value = pending; +} + +reg_t itrigger_t::tdata1_read(const processor_t * const proc) const noexcept +{ + auto xlen = proc->get_xlen(); + reg_t tdata1 = 0; + tdata1 = set_field(tdata1, CSR_ITRIGGER_TYPE(xlen), CSR_TDATA1_TYPE_ITRIGGER); + tdata1 = set_field(tdata1, CSR_ITRIGGER_DMODE(xlen), dmode); + tdata1 = set_field(tdata1, CSR_ITRIGGER_HIT(xlen), hit); + tdata1 = set_field(tdata1, CSR_ITRIGGER_VS, proc->extension_enabled('H') ? vs : 0); + tdata1 = set_field(tdata1, CSR_ITRIGGER_VU, proc->extension_enabled('H') ? vu : 0); + tdata1 = set_field(tdata1, CSR_ITRIGGER_NMI, nmi); + tdata1 = set_field(tdata1, CSR_ITRIGGER_M, m); + tdata1 = set_field(tdata1, CSR_ITRIGGER_S, s); + tdata1 = set_field(tdata1, CSR_ITRIGGER_U, u); + tdata1 = set_field(tdata1, CSR_ITRIGGER_ACTION, action); + return tdata1; +} + +void itrigger_t::tdata1_write(processor_t * const proc, const reg_t val, const bool UNUSED allow_chain) noexcept +{ + auto xlen = proc->get_xlen(); + assert(get_field(val, CSR_ITRIGGER_TYPE(xlen)) == CSR_TDATA1_TYPE_ITRIGGER); + dmode = get_field(val, CSR_ITRIGGER_DMODE(xlen)); + hit = get_field(val, CSR_ITRIGGER_HIT(xlen)); + vs = get_field(val, CSR_ITRIGGER_VS); + vu = get_field(val, CSR_ITRIGGER_VU); + nmi = get_field(val, CSR_ITRIGGER_NMI); + m = get_field(val, CSR_ITRIGGER_M); + s = proc->extension_enabled_const('S') ? get_field(val, CSR_ITRIGGER_S) : 0; + u = proc->extension_enabled_const('U') ? get_field(val, CSR_ITRIGGER_U) : 0; + action = legalize_action(val, CSR_ITRIGGER_ACTION, CSR_ITRIGGER_DMODE(xlen)); +} + +std::optional<match_result_t> trap_common_t::detect_trap_match(processor_t * const proc, const trap_t& t) noexcept +{ + if (!common_match(proc)) + return std::nullopt; + + auto xlen = proc->get_xlen(); + bool interrupt = (t.cause() & ((reg_t)1 << (xlen - 1))) != 0; + reg_t bit = t.cause() & ~((reg_t)1 << (xlen - 1)); + assert(bit < xlen); + if (simple_match(interrupt, bit) && allow_action(proc->get_state())) { + hit = true; + return match_result_t(TIMING_AFTER, action); + } + return std::nullopt; +} + +bool itrigger_t::simple_match(bool interrupt, reg_t bit) const +{ + return interrupt && ((bit == 0 && nmi) || ((tdata2 >> bit) & 1)); // Assume NMI's exception code is 0 +} + +reg_t etrigger_t::tdata1_read(const processor_t * const proc) const noexcept +{ + auto xlen = proc->get_xlen(); + reg_t tdata1 = 0; + tdata1 = set_field(tdata1, CSR_ETRIGGER_TYPE(xlen), CSR_TDATA1_TYPE_ETRIGGER); + tdata1 = set_field(tdata1, CSR_ETRIGGER_DMODE(xlen), dmode); + tdata1 = set_field(tdata1, CSR_ETRIGGER_HIT(xlen), hit); + tdata1 = set_field(tdata1, CSR_ETRIGGER_VS, proc->extension_enabled('H') ? vs : 0); + tdata1 = set_field(tdata1, CSR_ETRIGGER_VU, proc->extension_enabled('H') ? vu : 0); + tdata1 = set_field(tdata1, CSR_ETRIGGER_M, m); + tdata1 = set_field(tdata1, CSR_ETRIGGER_S, s); + tdata1 = set_field(tdata1, CSR_ETRIGGER_U, u); + tdata1 = set_field(tdata1, CSR_ETRIGGER_ACTION, action); + return tdata1; +} + +void etrigger_t::tdata1_write(processor_t * const proc, const reg_t val, const bool UNUSED allow_chain) noexcept +{ + auto xlen = proc->get_xlen(); + assert(get_field(val, CSR_ETRIGGER_TYPE(xlen)) == CSR_TDATA1_TYPE_ETRIGGER); + dmode = get_field(val, CSR_ETRIGGER_DMODE(xlen)); + hit = get_field(val, CSR_ETRIGGER_HIT(xlen)); + vs = get_field(val, CSR_ETRIGGER_VS); + vu = get_field(val, CSR_ETRIGGER_VU); + m = get_field(val, CSR_ETRIGGER_M); + s = proc->extension_enabled_const('S') ? get_field(val, CSR_ETRIGGER_S) : 0; + u = proc->extension_enabled_const('U') ? get_field(val, CSR_ETRIGGER_U) : 0; + action = legalize_action(val, CSR_ETRIGGER_ACTION, CSR_ETRIGGER_DMODE(xlen)); +} + +bool etrigger_t::simple_match(bool interrupt, reg_t bit) const +{ + return !interrupt && ((tdata2 >> bit) & 1); +} + +module_t::module_t(unsigned count) : triggers(count) { + for (unsigned i = 0; i < count; i++) { + triggers[i] = new disabled_trigger_t(); + } +} + +module_t::~module_t() { + for (auto trigger : triggers) { + delete trigger; + } +} + +reg_t module_t::tdata1_read(unsigned index) const noexcept +{ + return triggers[index]->tdata1_read(proc); +} + +bool module_t::tdata1_write(unsigned index, const reg_t val) noexcept +{ + if (triggers[index]->get_dmode() && !proc->get_state()->debug_mode) { + return false; + } + + auto xlen = proc->get_xlen(); + + reg_t tdata1 = val; + + // hardware must zero chain in writes that set dmode to 0 if the next trigger has dmode of 1 + const bool allow_chain = !(index+1 < triggers.size() && triggers[index+1]->get_dmode() && !get_field(val, CSR_TDATA1_DMODE(xlen))); + + // dmode only writable from debug mode + if (!proc->get_state()->debug_mode) { + assert(CSR_TDATA1_DMODE(xlen) == CSR_MCONTROL_DMODE(xlen)); + assert(CSR_TDATA1_DMODE(xlen) == CSR_ITRIGGER_DMODE(xlen)); + assert(CSR_TDATA1_DMODE(xlen) == CSR_ETRIGGER_DMODE(xlen)); + tdata1 = set_field(tdata1, CSR_TDATA1_DMODE(xlen), 0); + } + + // hardware should ignore writes that set dmode to 1 if the previous trigger has both dmode of 0 and chain of 1 + if (index > 0 && !triggers[index-1]->get_dmode() && triggers[index-1]->get_chain() && get_field(tdata1, CSR_TDATA1_DMODE(xlen))) + return false; + + unsigned type = get_field(val, CSR_TDATA1_TYPE(xlen)); + reg_t tdata2 = triggers[index]->tdata2_read(proc); + reg_t tdata3 = triggers[index]->tdata3_read(proc); + delete triggers[index]; + switch (type) { + case CSR_TDATA1_TYPE_MCONTROL: triggers[index] = new mcontrol_t(); break; + case CSR_TDATA1_TYPE_ICOUNT: triggers[index] = new icount_t(); break; + case CSR_TDATA1_TYPE_ITRIGGER: triggers[index] = new itrigger_t(); break; + case CSR_TDATA1_TYPE_ETRIGGER: triggers[index] = new etrigger_t(); break; + case CSR_TDATA1_TYPE_MCONTROL6: triggers[index] = new mcontrol6_t(); break; + default: triggers[index] = new disabled_trigger_t(); break; + } + + triggers[index]->tdata1_write(proc, tdata1, allow_chain); + triggers[index]->tdata2_write(proc, tdata2); + triggers[index]->tdata3_write(proc, tdata3); + proc->trigger_updated(triggers); + return true; +} + +reg_t module_t::tdata2_read(unsigned index) const noexcept +{ + return triggers[index]->tdata2_read(proc); +} + +bool module_t::tdata2_write(unsigned index, const reg_t val) noexcept +{ + if (triggers[index]->get_dmode() && !proc->get_state()->debug_mode) { + return false; + } + triggers[index]->tdata2_write(proc, val); + proc->trigger_updated(triggers); + return true; +} + +reg_t module_t::tdata3_read(unsigned index) const noexcept +{ + return triggers[index]->tdata3_read(proc); +} + +bool module_t::tdata3_write(unsigned index, const reg_t val) noexcept +{ + if (triggers[index]->get_dmode() && !proc->get_state()->debug_mode) { + return false; + } + triggers[index]->tdata3_write(proc, val); + proc->trigger_updated(triggers); + return true; +} + +std::optional<match_result_t> module_t::detect_memory_access_match(operation_t operation, reg_t address, std::optional<reg_t> data) noexcept +{ + state_t * const state = proc->get_state(); + if (state->debug_mode) + return std::nullopt; + + bool chain_ok = true; + + std::optional<match_result_t> ret = std::nullopt; + for (auto trigger: triggers) { + if (!chain_ok) { + chain_ok = !trigger->get_chain(); + continue; + } + + /* Note: We call detect_memory_access_match for each trigger in a chain as long as + * the triggers are matching. This results in "temperature coding" so that + * `hit` is set on each of the consecutive triggers that matched, even if the + * entire chain did not match. This is allowed by the spec, because the final + * trigger in the chain will never get `hit` set unless the entire chain + * matches. */ + auto result = trigger->detect_memory_access_match(proc, operation, address, data); + if (result.has_value() && !trigger->get_chain() && (!ret.has_value() || ret->action < result->action)) + ret = result; + + chain_ok = result.has_value() || !trigger->get_chain(); + } + return ret; +} + +std::optional<match_result_t> module_t::detect_icount_match() noexcept +{ + for (auto trigger: triggers) + trigger->stash_read_values(); + + state_t * const state = proc->get_state(); + if (state->debug_mode) + return std::nullopt; + + std::optional<match_result_t> ret = std::nullopt; + for (auto trigger: triggers) { + auto result = trigger->detect_icount_match(proc); + if (result.has_value() && (!ret.has_value() || ret->action < result->action)) + ret = result; + } + return ret; +} + +std::optional<match_result_t> module_t::detect_trap_match(const trap_t& t) noexcept +{ + state_t * const state = proc->get_state(); + if (state->debug_mode) + return std::nullopt; + + std::optional<match_result_t> ret = std::nullopt; + for (auto trigger: triggers) { + auto result = trigger->detect_trap_match(proc, t); + if (result.has_value() && (!ret.has_value() || ret->action < result->action)) + ret = result; + } + return ret; +} + +reg_t module_t::tinfo_read(unsigned UNUSED index) const noexcept +{ + /* In spike, every trigger supports the same types. */ + return (1 << CSR_TDATA1_TYPE_MCONTROL) | + (1 << CSR_TDATA1_TYPE_ICOUNT) | + (1 << CSR_TDATA1_TYPE_ITRIGGER) | + (1 << CSR_TDATA1_TYPE_ETRIGGER) | + (1 << CSR_TDATA1_TYPE_MCONTROL6) | + (1 << CSR_TDATA1_TYPE_DISABLED); +} + +}; diff --git a/vendor/riscv/riscv-isa-sim/riscv/triggers.h b/vendor/riscv/riscv-isa-sim/riscv/triggers.h new file mode 100644 index 0000000000..6e3d74d8c1 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/triggers.h @@ -0,0 +1,286 @@ +#ifndef _RISCV_TRIGGERS_H +#define _RISCV_TRIGGERS_H + +#include <vector> +#include <optional> + +#include "decode.h" + +namespace triggers { + +typedef enum { + OPERATION_EXECUTE, + OPERATION_STORE, + OPERATION_LOAD, +} operation_t; + +typedef enum +{ + ACTION_DEBUG_EXCEPTION = MCONTROL_ACTION_DEBUG_EXCEPTION, + ACTION_DEBUG_MODE = MCONTROL_ACTION_DEBUG_MODE, + ACTION_TRACE_START = MCONTROL_ACTION_TRACE_START, + ACTION_TRACE_STOP = MCONTROL_ACTION_TRACE_STOP, + ACTION_TRACE_EMIT = MCONTROL_ACTION_TRACE_EMIT, + ACTION_MAXVAL = MCONTROL_ACTION_TRACE_EMIT +} action_t; + +typedef enum { + TIMING_BEFORE = 0, + TIMING_AFTER = 1 +} timing_t; + +typedef enum { + SSELECT_IGNORE = 0, + SSELECT_SCONTEXT = 1, + SSELECT_ASID = 2, + SSELECT_MAXVAL = 2 +} sselect_t; + +typedef enum { + MHSELECT_MODE_IGNORE, + MHSELECT_MODE_MCONTEXT, + MHSELECT_MODE_VMID, +} mhselect_mode_t; + +struct match_result_t { + match_result_t(const timing_t t=TIMING_BEFORE, const action_t a=ACTION_DEBUG_EXCEPTION) { + timing = t; + action = a; + } + timing_t timing; + action_t action; +}; + +class matched_t +{ + public: + matched_t(triggers::operation_t operation, reg_t address, action_t action) : + operation(operation), address(address), action(action) {} + + triggers::operation_t operation; + reg_t address; + action_t action; +}; + +class trigger_t { +public: + virtual ~trigger_t() {}; + + virtual reg_t tdata1_read(const processor_t * const proc) const noexcept = 0; + virtual void tdata1_write(processor_t * const proc, const reg_t val, const bool allow_chain) noexcept = 0; + reg_t tdata2_read(const processor_t * const proc) const noexcept; + void tdata2_write(processor_t * const proc, const reg_t val) noexcept; + reg_t tdata3_read(const processor_t * const proc) const noexcept; + void tdata3_write(processor_t * const proc, const reg_t val) noexcept; + + virtual bool get_dmode() const = 0; + virtual bool get_chain() const { return false; } + virtual bool get_execute() const { return false; } + virtual bool get_store() const { return false; } + virtual bool get_load() const { return false; } + virtual action_t get_action() const { return ACTION_DEBUG_EXCEPTION; } + virtual bool icount_check_needed() const { return false; } + virtual void stash_read_values() {} + + virtual std::optional<match_result_t> detect_memory_access_match(processor_t UNUSED * const proc, + operation_t UNUSED operation, reg_t UNUSED address, std::optional<reg_t> UNUSED data) noexcept { return std::nullopt; } + virtual std::optional<match_result_t> detect_icount_match(processor_t UNUSED * const proc) { return std::nullopt; } + virtual std::optional<match_result_t> detect_trap_match(processor_t UNUSED * const proc, const trap_t UNUSED & t) noexcept { return std::nullopt; } + +protected: + static action_t legalize_action(reg_t val, reg_t action_mask, reg_t dmode_mask) noexcept; + bool common_match(processor_t * const proc) const noexcept; + bool allow_action(const state_t * const state) const; + reg_t tdata2; + + bool vs = false; + bool vu = false; + bool m = false; + bool s = false; + bool u = false; + +private: + unsigned legalize_mhselect(bool h_enabled) const noexcept; + bool mode_match(state_t * const state) const noexcept; + bool textra_match(processor_t * const proc) const noexcept; + + struct mhselect_interpretation { + const unsigned mhselect; + const mhselect_mode_t mode; + const std::optional<bool> shift_mhvalue; + unsigned compare_val(const unsigned mhvalue) const { + return shift_mhvalue.value() ? (mhvalue << 1 | mhselect >> 2) : mhvalue; + }; + }; + + mhselect_interpretation interpret_mhselect(bool h_enabled) const noexcept { + static unsigned warlize_if_h[8] = { 0, 1, 2, 0, 4, 5, 6, 4 }; // 3,7 downgrade + static unsigned warlize_no_h[8] = { 0, 0, 0, 0, 4, 4, 4, 4 }; // only 0,4 legal + static std::optional<mhselect_interpretation> table[8] = { + mhselect_interpretation{ 0, MHSELECT_MODE_IGNORE, std::nullopt }, + mhselect_interpretation{ 1, MHSELECT_MODE_MCONTEXT, true }, + mhselect_interpretation{ 2, MHSELECT_MODE_VMID, true }, + std::nullopt, + mhselect_interpretation{ 4, MHSELECT_MODE_MCONTEXT, false }, + mhselect_interpretation{ 5, MHSELECT_MODE_MCONTEXT, true }, + mhselect_interpretation{ 6, MHSELECT_MODE_VMID, true }, + std::nullopt + }; + assert(mhselect < 8); + unsigned legal = h_enabled ? warlize_if_h[mhselect] : warlize_no_h[mhselect]; + assert(legal < 8); + return table[legal].value(); + } + + sselect_t sselect; + unsigned svalue; + unsigned sbytemask; + unsigned mhselect; + unsigned mhvalue; +}; + +class disabled_trigger_t : public trigger_t { +public: + virtual reg_t tdata1_read(const processor_t * const proc) const noexcept override; + virtual void tdata1_write(processor_t * const proc, const reg_t val, const bool allow_chain) noexcept override; + + virtual bool get_dmode() const override { return dmode; } + +private: + bool dmode; +}; + +class trap_common_t : public trigger_t { +public: + bool get_dmode() const override { return dmode; } + virtual action_t get_action() const override { return action; } + + virtual std::optional<match_result_t> detect_trap_match(processor_t * const proc, const trap_t& t) noexcept override; + +private: + virtual bool simple_match(bool interrupt, reg_t bit) const = 0; + +protected: + bool dmode; + bool hit; + action_t action; +}; + +class itrigger_t : public trap_common_t { +public: + virtual reg_t tdata1_read(const processor_t * const proc) const noexcept override; + virtual void tdata1_write(processor_t * const proc, const reg_t val, const bool allow_chain) noexcept override; + +private: + virtual bool simple_match(bool interrupt, reg_t bit) const override; + bool nmi; +}; + +class etrigger_t : public trap_common_t { +public: + virtual reg_t tdata1_read(const processor_t * const proc) const noexcept override; + virtual void tdata1_write(processor_t * const proc, const reg_t val, const bool allow_chain) noexcept override; + +private: + virtual bool simple_match(bool interrupt, reg_t bit) const override; +}; + +class mcontrol_common_t : public trigger_t { +public: + typedef enum + { + MATCH_EQUAL = MCONTROL_MATCH_EQUAL, + MATCH_NAPOT = MCONTROL_MATCH_NAPOT, + MATCH_GE = MCONTROL_MATCH_GE, + MATCH_LT = MCONTROL_MATCH_LT, + MATCH_MASK_LOW = MCONTROL_MATCH_MASK_LOW, + MATCH_MASK_HIGH = MCONTROL_MATCH_MASK_HIGH + } match_t; + + virtual bool get_dmode() const override { return dmode; } + virtual bool get_chain() const override { return chain; } + virtual bool get_execute() const override { return execute; } + virtual bool get_store() const override { return store; } + virtual bool get_load() const override { return load; } + virtual action_t get_action() const override { return action; } + + virtual std::optional<match_result_t> detect_memory_access_match(processor_t * const proc, + operation_t operation, reg_t address, std::optional<reg_t> data) noexcept override; + +private: + bool simple_match(unsigned xlen, reg_t value) const; + +protected: + static match_t legalize_match(reg_t val) noexcept; + static bool legalize_timing(reg_t val, reg_t timing_mask, reg_t select_mask, reg_t execute_mask, reg_t load_mask) noexcept; + bool dmode = false; + action_t action = ACTION_DEBUG_EXCEPTION; + bool hit = false; + bool select = false; + bool timing = false; + bool chain = false; + match_t match = MATCH_EQUAL; + bool execute = false; + bool store = false; + bool load = false; +}; + +class mcontrol_t : public mcontrol_common_t { +public: + virtual reg_t tdata1_read(const processor_t * const proc) const noexcept override; + virtual void tdata1_write(processor_t * const proc, const reg_t val, const bool allow_chain) noexcept override; +}; + +class mcontrol6_t : public mcontrol_common_t { +public: + virtual reg_t tdata1_read(const processor_t * const proc) const noexcept override; + virtual void tdata1_write(processor_t * const proc, const reg_t val, const bool allow_chain) noexcept override; +}; + +class icount_t : public trigger_t { +public: + virtual reg_t tdata1_read(const processor_t * const proc) const noexcept override; + virtual void tdata1_write(processor_t * const proc, const reg_t val, const bool allow_chain) noexcept override; + + bool get_dmode() const override { return dmode; } + virtual action_t get_action() const override { return action; } + virtual bool icount_check_needed() const override { return count > 0 || pending; } + virtual void stash_read_values() override; + + virtual std::optional<match_result_t> detect_icount_match(processor_t * const proc) noexcept override; + +private: + bool dmode = false; + bool hit = false; + unsigned count = 1, count_read_value = 1; + bool pending = false, pending_read_value = false; + action_t action = (action_t)0; +}; + +class module_t { +public: + module_t(unsigned count); + ~module_t(); + + reg_t tdata1_read(unsigned index) const noexcept; + bool tdata1_write(unsigned index, const reg_t val) noexcept; + reg_t tdata2_read(unsigned index) const noexcept; + bool tdata2_write(unsigned index, const reg_t val) noexcept; + reg_t tdata3_read(unsigned index) const noexcept; + bool tdata3_write(unsigned index, const reg_t val) noexcept; + reg_t tinfo_read(unsigned index) const noexcept; + + unsigned count() const { return triggers.size(); } + + std::optional<match_result_t> detect_memory_access_match(operation_t operation, reg_t address, std::optional<reg_t> data) noexcept; + std::optional<match_result_t> detect_icount_match() noexcept; + std::optional<match_result_t> detect_trap_match(const trap_t& t) noexcept; + + processor_t *proc; +private: + std::vector<trigger_t *> triggers; +}; + +}; + +#endif diff --git a/vendor/riscv/riscv-isa-sim/riscv/v_ext_macros.h b/vendor/riscv/riscv-isa-sim/riscv/v_ext_macros.h new file mode 100644 index 0000000000..e00b0c0a3e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/v_ext_macros.h @@ -0,0 +1,2073 @@ +// See LICENSE for license details. + +#ifndef _RISCV_V_EXT_MACROS_H +#define _RISCV_V_EXT_MACROS_H + +#include "vector_unit.h" + +// +// vector: masking skip helper +// +#define VI_MASK_VARS \ + const int midx = i / 64; \ + const int mpos = i % 64; + +#define VI_LOOP_ELEMENT_SKIP(BODY) \ + VI_MASK_VARS \ + if (insn.v_vm() == 0) { \ + BODY; \ + bool skip = ((P.VU.elt<uint64_t>(0, midx) >> mpos) & 0x1) == 0; \ + if (skip) { \ + continue; \ + } \ + } + +#define VI_ELEMENT_SKIP \ + if (i >= vl) { \ + continue; \ + } else if (i < P.VU.vstart->read()) { \ + continue; \ + } else { \ + VI_LOOP_ELEMENT_SKIP(); \ + } + +// +// vector: operation and register acccess check helper +// +static inline bool is_overlapped(const int astart, int asize, + const int bstart, int bsize) +{ + asize = asize == 0 ? 1 : asize; + bsize = bsize == 0 ? 1 : bsize; + + const int aend = astart + asize; + const int bend = bstart + bsize; + + return std::max(aend, bend) - std::min(astart, bstart) < asize + bsize; +} + +static inline bool is_overlapped_widen(const int astart, int asize, + const int bstart, int bsize) +{ + asize = asize == 0 ? 1 : asize; + bsize = bsize == 0 ? 1 : bsize; + + const int aend = astart + asize; + const int bend = bstart + bsize; + + if (astart < bstart && + is_overlapped(astart, asize, bstart, bsize) && + !is_overlapped(astart, asize, bstart + bsize, bsize)) { + return false; + } else { + return std::max(aend, bend) - std::min(astart, bstart) < asize + bsize; + } +} + +static inline bool is_aligned(const unsigned val, const unsigned pos) +{ + return pos ? (val & (pos - 1)) == 0 : true; +} + +#define VI_NARROW_CHECK_COMMON \ + require_vector(true); \ + require(P.VU.vflmul <= 4); \ + require(P.VU.vsew * 2 <= P.VU.ELEN); \ + require_align(insn.rs2(), P.VU.vflmul * 2); \ + require_align(insn.rd(), P.VU.vflmul); \ + require_vm; \ + +#define VI_WIDE_CHECK_COMMON \ + require_vector(true); \ + require(P.VU.vflmul <= 4); \ + require(P.VU.vsew * 2 <= P.VU.ELEN); \ + require_align(insn.rd(), P.VU.vflmul * 2); \ + require_vm; \ + +#define VI_CHECK_ST_INDEX(elt_width) \ + require_vector(false); \ + require(elt_width <= P.VU.ELEN); \ + float vemul = ((float)elt_width / P.VU.vsew * P.VU.vflmul); \ + require(vemul >= 0.125 && vemul <= 8); \ + reg_t UNUSED emul = vemul < 1 ? 1 : vemul; \ + reg_t flmul = P.VU.vflmul < 1 ? 1 : P.VU.vflmul; \ + require_align(insn.rd(), P.VU.vflmul); \ + require_align(insn.rs2(), vemul); \ + require((nf * flmul) <= (NVPR / 4) && \ + (insn.rd() + nf * flmul) <= NVPR); \ + +#define VI_CHECK_LD_INDEX(elt_width) \ + VI_CHECK_ST_INDEX(elt_width); \ + for (reg_t idx = 0; idx < nf; ++idx) { \ + reg_t flmul = P.VU.vflmul < 1 ? 1 : P.VU.vflmul; \ + reg_t seg_vd = insn.rd() + flmul * idx; \ + if (elt_width > P.VU.vsew) { \ + if (seg_vd != insn.rs2()) \ + require_noover(seg_vd, P.VU.vflmul, insn.rs2(), vemul); \ + } else if (elt_width < P.VU.vsew) { \ + if (vemul < 1) { \ + require_noover(seg_vd, P.VU.vflmul, insn.rs2(), vemul); \ + } else { \ + require_noover_widen(seg_vd, P.VU.vflmul, insn.rs2(), vemul); \ + } \ + } \ + if (nf >= 2) { \ + require_noover(seg_vd, P.VU.vflmul, insn.rs2(), vemul); \ + } \ + } \ + require_vm; \ + +#define VI_CHECK_MSS(is_vs1) \ + if (insn.rd() != insn.rs2()) \ + require_noover(insn.rd(), 1, insn.rs2(), P.VU.vflmul); \ + require_align(insn.rs2(), P.VU.vflmul); \ + if (is_vs1) { \ + if (insn.rd() != insn.rs1()) \ + require_noover(insn.rd(), 1, insn.rs1(), P.VU.vflmul); \ + require_align(insn.rs1(), P.VU.vflmul); \ + } \ + +#define VI_CHECK_SSS(is_vs1) \ + require_vm; \ + if (P.VU.vflmul > 1) { \ + require_align(insn.rd(), P.VU.vflmul); \ + require_align(insn.rs2(), P.VU.vflmul); \ + if (is_vs1) { \ + require_align(insn.rs1(), P.VU.vflmul); \ + } \ + } + +#define VI_CHECK_STORE(elt_width, is_mask_ldst) \ + require_vector(false); \ + reg_t veew = is_mask_ldst ? 1 : sizeof(elt_width##_t) * 8; \ + float vemul = is_mask_ldst ? 1 : ((float)veew / P.VU.vsew * P.VU.vflmul); \ + reg_t emul = vemul < 1 ? 1 : vemul; \ + require(vemul >= 0.125 && vemul <= 8); \ + require_align(insn.rd(), vemul); \ + require((nf * emul) <= (NVPR / 4) && \ + (insn.rd() + nf * emul) <= NVPR); \ + require(veew <= P.VU.ELEN); \ + +#define VI_CHECK_LOAD(elt_width, is_mask_ldst) \ + VI_CHECK_STORE(elt_width, is_mask_ldst); \ + require_vm; \ + +#define VI_CHECK_DSS(is_vs1) \ + VI_WIDE_CHECK_COMMON; \ + require_align(insn.rs2(), P.VU.vflmul); \ + if (P.VU.vflmul < 1) { \ + require_noover(insn.rd(), P.VU.vflmul * 2, insn.rs2(), P.VU.vflmul); \ + } else { \ + require_noover_widen(insn.rd(), P.VU.vflmul * 2, insn.rs2(), P.VU.vflmul); \ + } \ + if (is_vs1) { \ + require_align(insn.rs1(), P.VU.vflmul); \ + if (P.VU.vflmul < 1) { \ + require_noover(insn.rd(), P.VU.vflmul * 2, insn.rs1(), P.VU.vflmul); \ + } else { \ + require_noover_widen(insn.rd(), P.VU.vflmul * 2, insn.rs1(), P.VU.vflmul); \ + } \ + } + +#define VI_CHECK_DDS(is_rs) \ + VI_WIDE_CHECK_COMMON; \ + require_align(insn.rs2(), P.VU.vflmul * 2); \ + if (is_rs) { \ + require_align(insn.rs1(), P.VU.vflmul); \ + if (P.VU.vflmul < 1) { \ + require_noover(insn.rd(), P.VU.vflmul * 2, insn.rs1(), P.VU.vflmul); \ + } else { \ + require_noover_widen(insn.rd(), P.VU.vflmul * 2, insn.rs1(), P.VU.vflmul); \ + } \ + } + +#define VI_CHECK_SDS(is_vs1) \ + VI_NARROW_CHECK_COMMON; \ + if (insn.rd() != insn.rs2()) \ + require_noover(insn.rd(), P.VU.vflmul, insn.rs2(), P.VU.vflmul * 2); \ + if (is_vs1) \ + require_align(insn.rs1(), P.VU.vflmul); \ + +#define VI_CHECK_REDUCTION(is_wide) \ + require_vector(true); \ + if (is_wide) { \ + require(P.VU.vsew * 2 <= P.VU.ELEN); \ + } \ + require_align(insn.rs2(), P.VU.vflmul); \ + require(P.VU.vstart->read() == 0); \ + +#define VI_CHECK_SLIDE(is_over) \ + require_align(insn.rs2(), P.VU.vflmul); \ + require_align(insn.rd(), P.VU.vflmul); \ + require_vm; \ + if (is_over) \ + require(insn.rd() != insn.rs2()); \ + +// +// vector: loop header and end helper +// +#define VI_GENERAL_LOOP_BASE \ + require(P.VU.vsew >= e8 && P.VU.vsew <= e64); \ + require_vector(true); \ + reg_t vl = P.VU.vl->read(); \ + reg_t UNUSED sew = P.VU.vsew; \ + reg_t rd_num = insn.rd(); \ + reg_t UNUSED rs1_num = insn.rs1(); \ + reg_t rs2_num = insn.rs2(); \ + for (reg_t i = P.VU.vstart->read(); i < vl; ++i) { + +#define VI_LOOP_BASE \ + VI_GENERAL_LOOP_BASE \ + VI_LOOP_ELEMENT_SKIP(); + +#define VI_LOOP_END \ + } \ + P.VU.vstart->write(0); + +#define VI_LOOP_REDUCTION_END(x) \ + } \ + if (vl > 0) { \ + vd_0_des = vd_0_res; \ + } \ + P.VU.vstart->write(0); + +#define VI_LOOP_CARRY_BASE \ + VI_GENERAL_LOOP_BASE \ + VI_MASK_VARS \ + auto v0 = P.VU.elt<uint64_t>(0, midx); \ + const uint64_t mmask = UINT64_C(1) << mpos; \ + const uint128_t op_mask = (UINT64_MAX >> (64 - sew)); \ + uint64_t carry = insn.v_vm() == 0 ? (v0 >> mpos) & 0x1 : 0; \ + uint128_t res = 0; \ + auto &vd = P.VU.elt<uint64_t>(rd_num, midx, true); + +#define VI_LOOP_CARRY_END \ + vd = (vd & ~mmask) | (((res) << mpos) & mmask); \ + } \ + P.VU.vstart->write(0); +#define VI_LOOP_WITH_CARRY_BASE \ + VI_GENERAL_LOOP_BASE \ + VI_MASK_VARS \ + auto &v0 = P.VU.elt<uint64_t>(0, midx); \ + const uint128_t op_mask = (UINT64_MAX >> (64 - sew)); \ + uint64_t carry = (v0 >> mpos) & 0x1; + +#define VI_LOOP_CMP_BASE \ + require(P.VU.vsew >= e8 && P.VU.vsew <= e64); \ + require_vector(true); \ + reg_t vl = P.VU.vl->read(); \ + reg_t sew = P.VU.vsew; \ + reg_t UNUSED rd_num = insn.rd(); \ + reg_t UNUSED rs1_num = insn.rs1(); \ + reg_t rs2_num = insn.rs2(); \ + for (reg_t i = P.VU.vstart->read(); i < vl; ++i) { \ + VI_LOOP_ELEMENT_SKIP(); \ + uint64_t mmask = UINT64_C(1) << mpos; \ + uint64_t &vdi = P.VU.elt<uint64_t>(insn.rd(), midx, true); \ + uint64_t res = 0; + +#define VI_LOOP_CMP_END \ + vdi = (vdi & ~mmask) | (((res) << mpos) & mmask); \ + } \ + P.VU.vstart->write(0); + +#define VI_LOOP_MASK(op) \ + require(P.VU.vsew <= e64); \ + require_vector(true); \ + reg_t vl = P.VU.vl->read(); \ + for (reg_t i = P.VU.vstart->read(); i < vl; ++i) { \ + int midx = i / 64; \ + int mpos = i % 64; \ + uint64_t mmask = UINT64_C(1) << mpos; \ + uint64_t vs2 = P.VU.elt<uint64_t>(insn.rs2(), midx); \ + uint64_t vs1 = P.VU.elt<uint64_t>(insn.rs1(), midx); \ + uint64_t &res = P.VU.elt<uint64_t>(insn.rd(), midx, true); \ + res = (res & ~mmask) | ((op) & (1ULL << mpos)); \ + } \ + P.VU.vstart->write(0); + +#define VI_LOOP_NSHIFT_BASE \ + VI_GENERAL_LOOP_BASE; \ + VI_LOOP_ELEMENT_SKIP({ \ + require(!(insn.rd() == 0 && P.VU.vflmul > 1)); \ + }); + +#define INT_ROUNDING(result, xrm, gb) \ + do { \ + const uint64_t lsb = 1UL << (gb); \ + const uint64_t lsb_half = lsb >> 1; \ + switch (xrm) { \ + case VRM::RNU: \ + result += lsb_half; \ + break; \ + case VRM::RNE: \ + if ((result & lsb_half) && ((result & (lsb_half - 1)) || (result & lsb))) \ + result += lsb; \ + break; \ + case VRM::RDN: \ + break; \ + case VRM::ROD: \ + if (result & (lsb - 1)) \ + result |= lsb; \ + break; \ + case VRM::INVALID_RM: \ + assert(true); \ + } \ + } while (0) + +// +// vector: integer and masking operand access helper +// +#define VXI_PARAMS(x) \ + type_sew_t<x>::type &vd = P.VU.elt<type_sew_t<x>::type>(rd_num, i, true); \ + type_sew_t<x>::type vs1 = P.VU.elt<type_sew_t<x>::type>(rs1_num, i); \ + type_sew_t<x>::type vs2 = P.VU.elt<type_sew_t<x>::type>(rs2_num, i); \ + type_sew_t<x>::type rs1 = (type_sew_t<x>::type)RS1; \ + type_sew_t<x>::type simm5 = (type_sew_t<x>::type)insn.v_simm5(); + +#define VV_U_PARAMS(x) \ + type_usew_t<x>::type &vd = P.VU.elt<type_usew_t<x>::type>(rd_num, i, true); \ + type_usew_t<x>::type vs1 = P.VU.elt<type_usew_t<x>::type>(rs1_num, i); \ + type_usew_t<x>::type vs2 = P.VU.elt<type_usew_t<x>::type>(rs2_num, i); + +#define VX_U_PARAMS(x) \ + type_usew_t<x>::type &vd = P.VU.elt<type_usew_t<x>::type>(rd_num, i, true); \ + type_usew_t<x>::type rs1 = (type_usew_t<x>::type)RS1; \ + type_usew_t<x>::type vs2 = P.VU.elt<type_usew_t<x>::type>(rs2_num, i); + +#define VI_U_PARAMS(x) \ + type_usew_t<x>::type &vd = P.VU.elt<type_usew_t<x>::type>(rd_num, i, true); \ + type_usew_t<x>::type UNUSED zimm5 = (type_usew_t<x>::type)insn.v_zimm5(); \ + type_usew_t<x>::type vs2 = P.VU.elt<type_usew_t<x>::type>(rs2_num, i); + +#define VV_PARAMS(x) \ + type_sew_t<x>::type UNUSED &vd = P.VU.elt<type_sew_t<x>::type>(rd_num, i, true); \ + type_sew_t<x>::type vs1 = P.VU.elt<type_sew_t<x>::type>(rs1_num, i); \ + type_sew_t<x>::type UNUSED vs2 = P.VU.elt<type_sew_t<x>::type>(rs2_num, i); + +#define VX_PARAMS(x) \ + type_sew_t<x>::type UNUSED &vd = P.VU.elt<type_sew_t<x>::type>(rd_num, i, true); \ + type_sew_t<x>::type rs1 = (type_sew_t<x>::type)RS1; \ + type_sew_t<x>::type UNUSED vs2 = P.VU.elt<type_sew_t<x>::type>(rs2_num, i); + +#define VI_PARAMS(x) \ + type_sew_t<x>::type &vd = P.VU.elt<type_sew_t<x>::type>(rd_num, i, true); \ + type_sew_t<x>::type simm5 = (type_sew_t<x>::type)insn.v_simm5(); \ + type_sew_t<x>::type UNUSED vs2 = P.VU.elt<type_sew_t<x>::type>(rs2_num, i); + +#define XV_PARAMS(x) \ + type_sew_t<x>::type &vd = P.VU.elt<type_sew_t<x>::type>(rd_num, i, true); \ + type_usew_t<x>::type vs2 = P.VU.elt<type_usew_t<x>::type>(rs2_num, RS1); + +#define VV_SU_PARAMS(x) \ + type_sew_t<x>::type &vd = P.VU.elt<type_sew_t<x>::type>(rd_num, i, true); \ + type_usew_t<x>::type vs1 = P.VU.elt<type_usew_t<x>::type>(rs1_num, i); \ + type_sew_t<x>::type vs2 = P.VU.elt<type_sew_t<x>::type>(rs2_num, i); + +#define VX_SU_PARAMS(x) \ + type_sew_t<x>::type &vd = P.VU.elt<type_sew_t<x>::type>(rd_num, i, true); \ + type_usew_t<x>::type rs1 = (type_usew_t<x>::type)RS1; \ + type_sew_t<x>::type vs2 = P.VU.elt<type_sew_t<x>::type>(rs2_num, i); + +#define VV_UCMP_PARAMS(x) \ + type_usew_t<x>::type vs1 = P.VU.elt<type_usew_t<x>::type>(rs1_num, i); \ + type_usew_t<x>::type vs2 = P.VU.elt<type_usew_t<x>::type>(rs2_num, i); + +#define VX_UCMP_PARAMS(x) \ + type_usew_t<x>::type rs1 = (type_usew_t<x>::type)RS1; \ + type_usew_t<x>::type vs2 = P.VU.elt<type_usew_t<x>::type>(rs2_num, i); + +#define VI_UCMP_PARAMS(x) \ + type_usew_t<x>::type vs2 = P.VU.elt<type_usew_t<x>::type>(rs2_num, i); + +#define VV_CMP_PARAMS(x) \ + type_sew_t<x>::type vs1 = P.VU.elt<type_sew_t<x>::type>(rs1_num, i); \ + type_sew_t<x>::type vs2 = P.VU.elt<type_sew_t<x>::type>(rs2_num, i); + +#define VX_CMP_PARAMS(x) \ + type_sew_t<x>::type rs1 = (type_sew_t<x>::type)RS1; \ + type_sew_t<x>::type vs2 = P.VU.elt<type_sew_t<x>::type>(rs2_num, i); + +#define VI_CMP_PARAMS(x) \ + type_sew_t<x>::type simm5 = (type_sew_t<x>::type)insn.v_simm5(); \ + type_sew_t<x>::type vs2 = P.VU.elt<type_sew_t<x>::type>(rs2_num, i); + +#define VI_XI_SLIDEDOWN_PARAMS(x, off) \ + auto &vd = P.VU.elt<type_sew_t<x>::type>(rd_num, i, true); \ + auto vs2 = P.VU.elt<type_sew_t<x>::type>(rs2_num, i + off); + +#define VI_XI_SLIDEUP_PARAMS(x, offset) \ + auto &vd = P.VU.elt<type_sew_t<x>::type>(rd_num, i, true); \ + auto vs2 = P.VU.elt<type_sew_t<x>::type>(rs2_num, i - offset); + +#define VI_NARROW_PARAMS(sew1, sew2) \ + auto &vd = P.VU.elt<type_usew_t<sew1>::type>(rd_num, i, true); \ + auto UNUSED vs2_u = P.VU.elt<type_usew_t<sew2>::type>(rs2_num, i); \ + auto UNUSED vs2 = P.VU.elt<type_sew_t<sew2>::type>(rs2_num, i); \ + auto zimm5 = (type_usew_t<sew1>::type)insn.v_zimm5(); + +#define VX_NARROW_PARAMS(sew1, sew2) \ + auto &vd = P.VU.elt<type_usew_t<sew1>::type>(rd_num, i, true); \ + auto UNUSED vs2_u = P.VU.elt<type_usew_t<sew2>::type>(rs2_num, i); \ + auto UNUSED vs2 = P.VU.elt<type_sew_t<sew2>::type>(rs2_num, i); \ + auto rs1 = (type_sew_t<sew1>::type)RS1; + +#define VV_NARROW_PARAMS(sew1, sew2) \ + auto &vd = P.VU.elt<type_usew_t<sew1>::type>(rd_num, i, true); \ + auto UNUSED vs2_u = P.VU.elt<type_usew_t<sew2>::type>(rs2_num, i); \ + auto UNUSED vs2 = P.VU.elt<type_sew_t<sew2>::type>(rs2_num, i); \ + auto vs1 = P.VU.elt<type_sew_t<sew1>::type>(rs1_num, i); + +#define XI_CARRY_PARAMS(x) \ + auto vs2 = P.VU.elt<type_sew_t<x>::type>(rs2_num, i); \ + auto UNUSED rs1 = (type_sew_t<x>::type)RS1; \ + auto UNUSED simm5 = (type_sew_t<x>::type)insn.v_simm5(); \ + +#define VV_CARRY_PARAMS(x) \ + auto vs2 = P.VU.elt<type_sew_t<x>::type>(rs2_num, i); \ + auto vs1 = P.VU.elt<type_sew_t<x>::type>(rs1_num, i); \ + +#define XI_WITH_CARRY_PARAMS(x) \ + auto vs2 = P.VU.elt<type_sew_t<x>::type>(rs2_num, i); \ + auto UNUSED rs1 = (type_sew_t<x>::type)RS1; \ + auto UNUSED simm5 = (type_sew_t<x>::type)insn.v_simm5(); \ + auto &vd = P.VU.elt<type_sew_t<x>::type>(rd_num, i, true); + +#define VV_WITH_CARRY_PARAMS(x) \ + auto vs2 = P.VU.elt<type_sew_t<x>::type>(rs2_num, i); \ + auto vs1 = P.VU.elt<type_sew_t<x>::type>(rs1_num, i); \ + auto &vd = P.VU.elt<type_sew_t<x>::type>(rd_num, i, true); + +#define VFP_V_PARAMS(width) \ + float##width##_t &vd = P.VU.elt<float##width##_t>(rd_num, i, true); \ + float##width##_t vs2 = P.VU.elt<float##width##_t>(rs2_num, i); + +#define VFP_VV_CMP_PARAMS(width) \ + float##width##_t vs1 = P.VU.elt<float##width##_t>(rs1_num, i); \ + float##width##_t vs2 = P.VU.elt<float##width##_t>(rs2_num, i); + +#define VFP_VV_PARAMS(width) \ + float##width##_t &vd = P.VU.elt<float##width##_t>(rd_num, i, true); \ + VFP_VV_CMP_PARAMS(width) + +#define VFP_VF_CMP_PARAMS(width) \ + float##width##_t rs1 = f##width(READ_FREG(rs1_num)); \ + float##width##_t vs2 = P.VU.elt<float##width##_t>(rs2_num, i); + +#define VFP_VF_PARAMS(width) \ + float##width##_t &vd = P.VU.elt<float##width##_t>(rd_num, i, true); \ + VFP_VF_CMP_PARAMS(width) + +#define CVT_FP_TO_FP_PARAMS(from_width, to_width) \ + auto vs2 = P.VU.elt<float##from_width##_t>(rs2_num, i); \ + auto &vd = P.VU.elt<float##to_width##_t>(rd_num, i, true); + +#define CVT_INT_TO_FP_PARAMS(from_width, to_width, sign) \ + auto vs2 = P.VU.elt<sign##from_width##_t>(rs2_num, i); \ + auto &vd = P.VU.elt<float##to_width##_t>(rd_num, i, true); + +#define CVT_FP_TO_INT_PARAMS(from_width, to_width, sign) \ + auto vs2 = P.VU.elt<float##from_width##_t>(rs2_num, i); \ + auto &vd = P.VU.elt<sign##to_width##_t>(rd_num, i, true); + +// +// vector: integer and masking operation loop +// + +#define INSNS_BASE(PARAMS, BODY) \ + if (sew == e8) { \ + PARAMS(e8); \ + BODY; \ + } else if (sew == e16) { \ + PARAMS(e16); \ + BODY; \ + } else if (sew == e32) { \ + PARAMS(e32); \ + BODY; \ + } else if (sew == e64) { \ + PARAMS(e64); \ + BODY; \ + } + +// comparision result to masking register +#define VI_LOOP_CMP_BODY(PARAMS, BODY) \ + VI_LOOP_CMP_BASE \ + INSNS_BASE(PARAMS, BODY) \ + VI_LOOP_CMP_END + +#define VI_VV_LOOP_CMP(BODY) \ + VI_CHECK_MSS(true); \ + VI_LOOP_CMP_BODY(VV_CMP_PARAMS, BODY) + +#define VI_VX_LOOP_CMP(BODY) \ + VI_CHECK_MSS(false); \ + VI_LOOP_CMP_BODY(VX_CMP_PARAMS, BODY) + +#define VI_VI_LOOP_CMP(BODY) \ + VI_CHECK_MSS(false); \ + VI_LOOP_CMP_BODY(VI_CMP_PARAMS, BODY) + +#define VI_VV_ULOOP_CMP(BODY) \ + VI_CHECK_MSS(true); \ + VI_LOOP_CMP_BODY(VV_UCMP_PARAMS, BODY) + +#define VI_VX_ULOOP_CMP(BODY) \ + VI_CHECK_MSS(false); \ + VI_LOOP_CMP_BODY(VX_UCMP_PARAMS, BODY) + +#define VI_VI_ULOOP_CMP(BODY) \ + VI_CHECK_MSS(false); \ + VI_LOOP_CMP_BODY(VI_UCMP_PARAMS, BODY) + +// merge and copy loop +#define VI_MERGE_VARS \ + VI_MASK_VARS \ + bool UNUSED use_first = (P.VU.elt<uint64_t>(0, midx) >> mpos) & 0x1; + +#define VI_MERGE_LOOP_BASE \ + VI_GENERAL_LOOP_BASE \ + VI_MERGE_VARS + +#define VI_VV_MERGE_LOOP(BODY) \ + VI_CHECK_SSS(true); \ + VI_MERGE_LOOP_BASE \ + if (sew == e8) { \ + VV_PARAMS(e8); \ + BODY; \ + } else if (sew == e16) { \ + VV_PARAMS(e16); \ + BODY; \ + } else if (sew == e32) { \ + VV_PARAMS(e32); \ + BODY; \ + } else if (sew == e64) { \ + VV_PARAMS(e64); \ + BODY; \ + } \ + VI_LOOP_END + +#define VI_VX_MERGE_LOOP(BODY) \ + VI_CHECK_SSS(false); \ + VI_MERGE_LOOP_BASE \ + if (sew == e8) { \ + VX_PARAMS(e8); \ + BODY; \ + } else if (sew == e16) { \ + VX_PARAMS(e16); \ + BODY; \ + } else if (sew == e32) { \ + VX_PARAMS(e32); \ + BODY; \ + } else if (sew == e64) { \ + VX_PARAMS(e64); \ + BODY; \ + } \ + VI_LOOP_END + +#define VI_VI_MERGE_LOOP(BODY) \ + VI_CHECK_SSS(false); \ + VI_MERGE_LOOP_BASE \ + if (sew == e8) { \ + VI_PARAMS(e8); \ + BODY; \ + } else if (sew == e16) { \ + VI_PARAMS(e16); \ + BODY; \ + } else if (sew == e32) { \ + VI_PARAMS(e32); \ + BODY; \ + } else if (sew == e64) { \ + VI_PARAMS(e64); \ + BODY; \ + } \ + VI_LOOP_END + +#define VI_VF_MERGE_LOOP(BODY) \ + VI_CHECK_SSS(false); \ + VI_VFP_COMMON \ + for (reg_t i = P.VU.vstart->read(); i < vl; ++i) { \ + VI_MERGE_VARS \ + if (P.VU.vsew == e16) { \ + VFP_VF_PARAMS(16); \ + BODY; \ + } else if (P.VU.vsew == e32) { \ + VFP_VF_PARAMS(32); \ + BODY; \ + } else if (P.VU.vsew == e64) { \ + VFP_VF_PARAMS(64); \ + BODY; \ + } \ + VI_LOOP_END + +// reduction loop - signed +#define VI_LOOP_REDUCTION_BASE(x) \ + require(x >= e8 && x <= e64); \ + reg_t vl = P.VU.vl->read(); \ + reg_t rd_num = insn.rd(); \ + reg_t rs1_num = insn.rs1(); \ + reg_t rs2_num = insn.rs2(); \ + auto &vd_0_des = P.VU.elt<type_sew_t<x>::type>(rd_num, 0, true); \ + auto vd_0_res = P.VU.elt<type_sew_t<x>::type>(rs1_num, 0); \ + for (reg_t i = P.VU.vstart->read(); i < vl; ++i) { \ + VI_LOOP_ELEMENT_SKIP(); \ + auto vs2 = P.VU.elt<type_sew_t<x>::type>(rs2_num, i); \ + +#define REDUCTION_LOOP(x, BODY) \ + VI_LOOP_REDUCTION_BASE(x) \ + BODY; \ + VI_LOOP_REDUCTION_END(x) + +#define VI_VV_LOOP_REDUCTION(BODY) \ + VI_CHECK_REDUCTION(false); \ + reg_t sew = P.VU.vsew; \ + if (sew == e8) { \ + REDUCTION_LOOP(e8, BODY) \ + } else if (sew == e16) { \ + REDUCTION_LOOP(e16, BODY) \ + } else if (sew == e32) { \ + REDUCTION_LOOP(e32, BODY) \ + } else if (sew == e64) { \ + REDUCTION_LOOP(e64, BODY) \ + } + +// reduction loop - unsigned +#define VI_ULOOP_REDUCTION_BASE(x) \ + require(x >= e8 && x <= e64); \ + reg_t vl = P.VU.vl->read(); \ + reg_t rd_num = insn.rd(); \ + reg_t rs1_num = insn.rs1(); \ + reg_t rs2_num = insn.rs2(); \ + auto &vd_0_des = P.VU.elt<type_usew_t<x>::type>(rd_num, 0, true); \ + auto vd_0_res = P.VU.elt<type_usew_t<x>::type>(rs1_num, 0); \ + for (reg_t i = P.VU.vstart->read(); i < vl; ++i) { \ + VI_LOOP_ELEMENT_SKIP(); \ + auto vs2 = P.VU.elt<type_usew_t<x>::type>(rs2_num, i); + +#define REDUCTION_ULOOP(x, BODY) \ + VI_ULOOP_REDUCTION_BASE(x) \ + BODY; \ + VI_LOOP_REDUCTION_END(x) + +#define VI_VV_ULOOP_REDUCTION(BODY) \ + VI_CHECK_REDUCTION(false); \ + reg_t sew = P.VU.vsew; \ + if (sew == e8) { \ + REDUCTION_ULOOP(e8, BODY) \ + } else if (sew == e16) { \ + REDUCTION_ULOOP(e16, BODY) \ + } else if (sew == e32) { \ + REDUCTION_ULOOP(e32, BODY) \ + } else if (sew == e64) { \ + REDUCTION_ULOOP(e64, BODY) \ + } + +// genearl VXI signed/unsigned loop +#define VI_VV_ULOOP(BODY) \ + VI_CHECK_SSS(true) \ + VI_LOOP_BASE \ + if (sew == e8) { \ + VV_U_PARAMS(e8); \ + BODY; \ + } else if (sew == e16) { \ + VV_U_PARAMS(e16); \ + BODY; \ + } else if (sew == e32) { \ + VV_U_PARAMS(e32); \ + BODY; \ + } else if (sew == e64) { \ + VV_U_PARAMS(e64); \ + BODY; \ + } \ + VI_LOOP_END + +#define VI_VV_LOOP(BODY) \ + VI_CHECK_SSS(true) \ + VI_LOOP_BASE \ + if (sew == e8) { \ + VV_PARAMS(e8); \ + BODY; \ + } else if (sew == e16) { \ + VV_PARAMS(e16); \ + BODY; \ + } else if (sew == e32) { \ + VV_PARAMS(e32); \ + BODY; \ + } else if (sew == e64) { \ + VV_PARAMS(e64); \ + BODY; \ + } \ + VI_LOOP_END + +#define VI_VX_ULOOP(BODY) \ + VI_CHECK_SSS(false) \ + VI_LOOP_BASE \ + if (sew == e8) { \ + VX_U_PARAMS(e8); \ + BODY; \ + } else if (sew == e16) { \ + VX_U_PARAMS(e16); \ + BODY; \ + } else if (sew == e32) { \ + VX_U_PARAMS(e32); \ + BODY; \ + } else if (sew == e64) { \ + VX_U_PARAMS(e64); \ + BODY; \ + } \ + VI_LOOP_END + +#define VI_VX_LOOP(BODY) \ + VI_CHECK_SSS(false) \ + VI_LOOP_BASE \ + if (sew == e8) { \ + VX_PARAMS(e8); \ + BODY; \ + } else if (sew == e16) { \ + VX_PARAMS(e16); \ + BODY; \ + } else if (sew == e32) { \ + VX_PARAMS(e32); \ + BODY; \ + } else if (sew == e64) { \ + VX_PARAMS(e64); \ + BODY; \ + } \ + VI_LOOP_END + +#define VI_VI_ULOOP(BODY) \ + VI_CHECK_SSS(false) \ + VI_LOOP_BASE \ + if (sew == e8) { \ + VI_U_PARAMS(e8); \ + BODY; \ + } else if (sew == e16) { \ + VI_U_PARAMS(e16); \ + BODY; \ + } else if (sew == e32) { \ + VI_U_PARAMS(e32); \ + BODY; \ + } else if (sew == e64) { \ + VI_U_PARAMS(e64); \ + BODY; \ + } \ + VI_LOOP_END + +#define VI_VI_LOOP(BODY) \ + VI_CHECK_SSS(false) \ + VI_LOOP_BASE \ + if (sew == e8) { \ + VI_PARAMS(e8); \ + BODY; \ + } else if (sew == e16) { \ + VI_PARAMS(e16); \ + BODY; \ + } else if (sew == e32) { \ + VI_PARAMS(e32); \ + BODY; \ + } else if (sew == e64) { \ + VI_PARAMS(e64); \ + BODY; \ + } \ + VI_LOOP_END + +// signed unsigned operation loop (e.g. mulhsu) +#define VI_VV_SU_LOOP(BODY) \ + VI_CHECK_SSS(true) \ + VI_LOOP_BASE \ + if (sew == e8) { \ + VV_SU_PARAMS(e8); \ + BODY; \ + } else if (sew == e16) { \ + VV_SU_PARAMS(e16); \ + BODY; \ + } else if (sew == e32) { \ + VV_SU_PARAMS(e32); \ + BODY; \ + } else if (sew == e64) { \ + VV_SU_PARAMS(e64); \ + BODY; \ + } \ + VI_LOOP_END + +#define VI_VX_SU_LOOP(BODY) \ + VI_CHECK_SSS(false) \ + VI_LOOP_BASE \ + if (sew == e8) { \ + VX_SU_PARAMS(e8); \ + BODY; \ + } else if (sew == e16) { \ + VX_SU_PARAMS(e16); \ + BODY; \ + } else if (sew == e32) { \ + VX_SU_PARAMS(e32); \ + BODY; \ + } else if (sew == e64) { \ + VX_SU_PARAMS(e64); \ + BODY; \ + } \ + VI_LOOP_END + +// narrow operation loop +#define VI_VV_LOOP_NARROW(BODY) \ + VI_CHECK_SDS(true); \ + VI_LOOP_BASE \ + if (sew == e8) { \ + VV_NARROW_PARAMS(e8, e16) \ + BODY; \ + } else if (sew == e16) { \ + VV_NARROW_PARAMS(e16, e32) \ + BODY; \ + } else if (sew == e32) { \ + VV_NARROW_PARAMS(e32, e64) \ + BODY; \ + } \ + VI_LOOP_END + +#define VI_VX_LOOP_NARROW(BODY) \ + VI_CHECK_SDS(false); \ + VI_LOOP_BASE \ + if (sew == e8) { \ + VX_NARROW_PARAMS(e8, e16) \ + BODY; \ + } else if (sew == e16) { \ + VX_NARROW_PARAMS(e16, e32) \ + BODY; \ + } else if (sew == e32) { \ + VX_NARROW_PARAMS(e32, e64) \ + BODY; \ + } \ + VI_LOOP_END + +#define VI_VI_LOOP_NARROW(BODY) \ + VI_CHECK_SDS(false); \ + VI_LOOP_BASE \ + if (sew == e8) { \ + VI_NARROW_PARAMS(e8, e16) \ + BODY; \ + } else if (sew == e16) { \ + VI_NARROW_PARAMS(e16, e32) \ + BODY; \ + } else if (sew == e32) { \ + VI_NARROW_PARAMS(e32, e64) \ + BODY; \ + } \ + VI_LOOP_END + +#define VI_VI_LOOP_NSHIFT(BODY) \ + VI_CHECK_SDS(false); \ + VI_LOOP_NSHIFT_BASE \ + if (sew == e8) { \ + VI_NARROW_PARAMS(e8, e16) \ + BODY; \ + } else if (sew == e16) { \ + VI_NARROW_PARAMS(e16, e32) \ + BODY; \ + } else if (sew == e32) { \ + VI_NARROW_PARAMS(e32, e64) \ + BODY; \ + } \ + VI_LOOP_END + +#define VI_VX_LOOP_NSHIFT(BODY) \ + VI_CHECK_SDS(false); \ + VI_LOOP_NSHIFT_BASE \ + if (sew == e8) { \ + VX_NARROW_PARAMS(e8, e16) \ + BODY; \ + } else if (sew == e16) { \ + VX_NARROW_PARAMS(e16, e32) \ + BODY; \ + } else if (sew == e32) { \ + VX_NARROW_PARAMS(e32, e64) \ + BODY; \ + } \ + VI_LOOP_END + +#define VI_VV_LOOP_NSHIFT(BODY) \ + VI_CHECK_SDS(true); \ + VI_LOOP_NSHIFT_BASE \ + if (sew == e8) { \ + VV_NARROW_PARAMS(e8, e16) \ + BODY; \ + } else if (sew == e16) { \ + VV_NARROW_PARAMS(e16, e32) \ + BODY; \ + } else if (sew == e32) { \ + VV_NARROW_PARAMS(e32, e64) \ + BODY; \ + } \ + VI_LOOP_END + +// widen operation loop +#define VI_VV_LOOP_WIDEN(BODY) \ + VI_LOOP_BASE \ + if (sew == e8) { \ + VV_PARAMS(e8); \ + BODY; \ + } else if (sew == e16) { \ + VV_PARAMS(e16); \ + BODY; \ + } else if (sew == e32) { \ + VV_PARAMS(e32); \ + BODY; \ + } \ + VI_LOOP_END + +#define VI_VX_LOOP_WIDEN(BODY) \ + VI_LOOP_BASE \ + if (sew == e8) { \ + VX_PARAMS(e8); \ + BODY; \ + } else if (sew == e16) { \ + VX_PARAMS(e16); \ + BODY; \ + } else if (sew == e32) { \ + VX_PARAMS(e32); \ + BODY; \ + } \ + VI_LOOP_END + +#define VI_WIDE_OP_AND_ASSIGN(var0, var1, var2, op0, op1, sign) \ + switch (P.VU.vsew) { \ + case e8: { \ + sign##16_t UNUSED vd_w = P.VU.elt<sign##16_t>(rd_num, i); \ + P.VU.elt<uint16_t>(rd_num, i, true) = \ + op1((sign##16_t)(sign##8_t)var0 op0 (sign##16_t)(sign##8_t)var1) + var2; \ + } \ + break; \ + case e16: { \ + sign##32_t UNUSED vd_w = P.VU.elt<sign##32_t>(rd_num, i); \ + P.VU.elt<uint32_t>(rd_num, i, true) = \ + op1((sign##32_t)(sign##16_t)var0 op0 (sign##32_t)(sign##16_t)var1) + var2; \ + } \ + break; \ + default: { \ + sign##64_t UNUSED vd_w = P.VU.elt<sign##64_t>(rd_num, i); \ + P.VU.elt<uint64_t>(rd_num, i, true) = \ + op1((sign##64_t)(sign##32_t)var0 op0 (sign##64_t)(sign##32_t)var1) + var2; \ + } \ + break; \ + } + +#define VI_WIDE_OP_AND_ASSIGN_MIX(var0, var1, var2, op0, op1, sign_d, sign_1, sign_2) \ + switch (P.VU.vsew) { \ + case e8: { \ + sign_d##16_t UNUSED vd_w = P.VU.elt<sign_d##16_t>(rd_num, i); \ + P.VU.elt<uint16_t>(rd_num, i, true) = \ + op1((sign_1##16_t)(sign_1##8_t)var0 op0 (sign_2##16_t)(sign_2##8_t)var1) + var2; \ + } \ + break; \ + case e16: { \ + sign_d##32_t UNUSED vd_w = P.VU.elt<sign_d##32_t>(rd_num, i); \ + P.VU.elt<uint32_t>(rd_num, i, true) = \ + op1((sign_1##32_t)(sign_1##16_t)var0 op0 (sign_2##32_t)(sign_2##16_t)var1) + var2; \ + } \ + break; \ + default: { \ + sign_d##64_t UNUSED vd_w = P.VU.elt<sign_d##64_t>(rd_num, i); \ + P.VU.elt<uint64_t>(rd_num, i, true) = \ + op1((sign_1##64_t)(sign_1##32_t)var0 op0 (sign_2##64_t)(sign_2##32_t)var1) + var2; \ + } \ + break; \ + } + +#define VI_WIDE_WVX_OP(var0, op0, sign) \ + switch (P.VU.vsew) { \ + case e8: { \ + sign##16_t &vd_w = P.VU.elt<sign##16_t>(rd_num, i, true); \ + sign##16_t vs2_w = P.VU.elt<sign##16_t>(rs2_num, i); \ + vd_w = vs2_w op0 (sign##16_t)(sign##8_t)var0; \ + } \ + break; \ + case e16: { \ + sign##32_t &vd_w = P.VU.elt<sign##32_t>(rd_num, i, true); \ + sign##32_t vs2_w = P.VU.elt<sign##32_t>(rs2_num, i); \ + vd_w = vs2_w op0 (sign##32_t)(sign##16_t)var0; \ + } \ + break; \ + default: { \ + sign##64_t &vd_w = P.VU.elt<sign##64_t>(rd_num, i, true); \ + sign##64_t vs2_w = P.VU.elt<sign##64_t>(rs2_num, i); \ + vd_w = vs2_w op0 (sign##64_t)(sign##32_t)var0; \ + } \ + break; \ + } + +// wide reduction loop - signed +#define VI_LOOP_WIDE_REDUCTION_BASE(sew1, sew2) \ + reg_t vl = P.VU.vl->read(); \ + reg_t rd_num = insn.rd(); \ + reg_t rs1_num = insn.rs1(); \ + reg_t rs2_num = insn.rs2(); \ + auto &vd_0_des = P.VU.elt<type_sew_t<sew2>::type>(rd_num, 0, true); \ + auto vd_0_res = P.VU.elt<type_sew_t<sew2>::type>(rs1_num, 0); \ + for (reg_t i = P.VU.vstart->read(); i < vl; ++i) { \ + VI_LOOP_ELEMENT_SKIP(); \ + auto vs2 = P.VU.elt<type_sew_t<sew1>::type>(rs2_num, i); + +#define WIDE_REDUCTION_LOOP(sew1, sew2, BODY) \ + VI_LOOP_WIDE_REDUCTION_BASE(sew1, sew2) \ + BODY; \ + VI_LOOP_REDUCTION_END(sew2) + +#define VI_VV_LOOP_WIDE_REDUCTION(BODY) \ + VI_CHECK_REDUCTION(true); \ + reg_t sew = P.VU.vsew; \ + if (sew == e8) { \ + WIDE_REDUCTION_LOOP(e8, e16, BODY) \ + } else if (sew == e16) { \ + WIDE_REDUCTION_LOOP(e16, e32, BODY) \ + } else if (sew == e32) { \ + WIDE_REDUCTION_LOOP(e32, e64, BODY) \ + } + +// wide reduction loop - unsigned +#define VI_ULOOP_WIDE_REDUCTION_BASE(sew1, sew2) \ + reg_t vl = P.VU.vl->read(); \ + reg_t rd_num = insn.rd(); \ + reg_t rs1_num = insn.rs1(); \ + reg_t rs2_num = insn.rs2(); \ + auto &vd_0_des = P.VU.elt<type_usew_t<sew2>::type>(rd_num, 0, true); \ + auto vd_0_res = P.VU.elt<type_usew_t<sew2>::type>(rs1_num, 0); \ + for (reg_t i = P.VU.vstart->read(); i < vl; ++i) { \ + VI_LOOP_ELEMENT_SKIP(); \ + auto vs2 = P.VU.elt<type_usew_t<sew1>::type>(rs2_num, i); + +#define WIDE_REDUCTION_ULOOP(sew1, sew2, BODY) \ + VI_ULOOP_WIDE_REDUCTION_BASE(sew1, sew2) \ + BODY; \ + VI_LOOP_REDUCTION_END(sew2) + +#define VI_VV_ULOOP_WIDE_REDUCTION(BODY) \ + VI_CHECK_REDUCTION(true); \ + reg_t sew = P.VU.vsew; \ + if (sew == e8) { \ + WIDE_REDUCTION_ULOOP(e8, e16, BODY) \ + } else if (sew == e16) { \ + WIDE_REDUCTION_ULOOP(e16, e32, BODY) \ + } else if (sew == e32) { \ + WIDE_REDUCTION_ULOOP(e32, e64, BODY) \ + } + +// carry/borrow bit loop +#define VI_VV_LOOP_CARRY(BODY) \ + VI_CHECK_MSS(true); \ + VI_LOOP_CARRY_BASE \ + if (sew == e8) { \ + VV_CARRY_PARAMS(e8) \ + BODY; \ + } else if (sew == e16) { \ + VV_CARRY_PARAMS(e16) \ + BODY; \ + } else if (sew == e32) { \ + VV_CARRY_PARAMS(e32) \ + BODY; \ + } else if (sew == e64) { \ + VV_CARRY_PARAMS(e64) \ + BODY; \ + } \ + VI_LOOP_CARRY_END + +#define VI_XI_LOOP_CARRY(BODY) \ + VI_CHECK_MSS(false); \ + VI_LOOP_CARRY_BASE \ + if (sew == e8) { \ + XI_CARRY_PARAMS(e8) \ + BODY; \ + } else if (sew == e16) { \ + XI_CARRY_PARAMS(e16) \ + BODY; \ + } else if (sew == e32) { \ + XI_CARRY_PARAMS(e32) \ + BODY; \ + } else if (sew == e64) { \ + XI_CARRY_PARAMS(e64) \ + BODY; \ + } \ + VI_LOOP_CARRY_END + +#define VI_VV_LOOP_WITH_CARRY(BODY) \ + VI_CHECK_SSS(true); \ + VI_LOOP_WITH_CARRY_BASE \ + if (sew == e8) { \ + VV_WITH_CARRY_PARAMS(e8) \ + BODY; \ + } else if (sew == e16) { \ + VV_WITH_CARRY_PARAMS(e16) \ + BODY; \ + } else if (sew == e32) { \ + VV_WITH_CARRY_PARAMS(e32) \ + BODY; \ + } else if (sew == e64) { \ + VV_WITH_CARRY_PARAMS(e64) \ + BODY; \ + } \ + VI_LOOP_END + +#define VI_XI_LOOP_WITH_CARRY(BODY) \ + VI_CHECK_SSS(false); \ + VI_LOOP_WITH_CARRY_BASE \ + if (sew == e8) { \ + XI_WITH_CARRY_PARAMS(e8) \ + BODY; \ + } else if (sew == e16) { \ + XI_WITH_CARRY_PARAMS(e16) \ + BODY; \ + } else if (sew == e32) { \ + XI_WITH_CARRY_PARAMS(e32) \ + BODY; \ + } else if (sew == e64) { \ + XI_WITH_CARRY_PARAMS(e64) \ + BODY; \ + } \ + VI_LOOP_END + +// average loop +#define VI_VV_LOOP_AVG(op) \ +VRM xrm = p->VU.get_vround_mode(); \ +VI_VV_LOOP({ \ + uint128_t res = ((uint128_t)vs2) op vs1; \ + INT_ROUNDING(res, xrm, 1); \ + vd = res >> 1; \ +}) + +#define VI_VX_LOOP_AVG(op) \ +VRM xrm = p->VU.get_vround_mode(); \ +VI_VX_LOOP({ \ + uint128_t res = ((uint128_t)vs2) op rs1; \ + INT_ROUNDING(res, xrm, 1); \ + vd = res >> 1; \ +}) + +#define VI_VV_ULOOP_AVG(op) \ +VRM xrm = p->VU.get_vround_mode(); \ +VI_VV_ULOOP({ \ + uint128_t res = ((uint128_t)vs2) op vs1; \ + INT_ROUNDING(res, xrm, 1); \ + vd = res >> 1; \ +}) + +#define VI_VX_ULOOP_AVG(op) \ +VRM xrm = p->VU.get_vround_mode(); \ +VI_VX_ULOOP({ \ + uint128_t res = ((uint128_t)vs2) op rs1; \ + INT_ROUNDING(res, xrm, 1); \ + vd = res >> 1; \ +}) + +// +// vector: load/store helper +// +#define VI_STRIP(inx) \ + reg_t vreg_inx = inx; + +#define VI_DUPLICATE_VREG(reg_num, idx_sew) \ +reg_t index[P.VU.vlmax]; \ + for (reg_t i = 0; i < P.VU.vlmax && P.VU.vl->read() != 0; ++i) { \ + switch (idx_sew) { \ + case e8: \ + index[i] = P.VU.elt<uint8_t>(reg_num, i); \ + break; \ + case e16: \ + index[i] = P.VU.elt<uint16_t>(reg_num, i); \ + break; \ + case e32: \ + index[i] = P.VU.elt<uint32_t>(reg_num, i); \ + break; \ + case e64: \ + index[i] = P.VU.elt<uint64_t>(reg_num, i); \ + break; \ + } \ +} + +#define VI_LD(stride, offset, elt_width, is_mask_ldst) \ + const reg_t nf = insn.v_nf() + 1; \ + const reg_t vl = is_mask_ldst ? ((P.VU.vl->read() + 7) / 8) : P.VU.vl->read(); \ + const reg_t baseAddr = RS1; \ + const reg_t vd = insn.rd(); \ + VI_CHECK_LOAD(elt_width, is_mask_ldst); \ + for (reg_t i = 0; i < vl; ++i) { \ + VI_ELEMENT_SKIP; \ + VI_STRIP(i); \ + P.VU.vstart->write(i); \ + for (reg_t fn = 0; fn < nf; ++fn) { \ + elt_width##_t val = MMU.load<elt_width##_t>( \ + baseAddr + (stride) + (offset) * sizeof(elt_width##_t)); \ + P.VU.elt<elt_width##_t>(vd + fn * emul, vreg_inx, true) = val; \ + } \ + } \ + P.VU.vstart->write(0); + +#define VI_LD_INDEX(elt_width, is_seg) \ + const reg_t nf = insn.v_nf() + 1; \ + const reg_t vl = P.VU.vl->read(); \ + const reg_t baseAddr = RS1; \ + const reg_t vd = insn.rd(); \ + if (!is_seg) \ + require(nf == 1); \ + VI_CHECK_LD_INDEX(elt_width); \ + VI_DUPLICATE_VREG(insn.rs2(), elt_width); \ + for (reg_t i = 0; i < vl; ++i) { \ + VI_ELEMENT_SKIP; \ + VI_STRIP(i); \ + P.VU.vstart->write(i); \ + for (reg_t fn = 0; fn < nf; ++fn) { \ + switch (P.VU.vsew) { \ + case e8: \ + P.VU.elt<uint8_t>(vd + fn * flmul, vreg_inx, true) = \ + MMU.load<uint8_t>(baseAddr + index[i] + fn * 1); \ + break; \ + case e16: \ + P.VU.elt<uint16_t>(vd + fn * flmul, vreg_inx, true) = \ + MMU.load<uint16_t>(baseAddr + index[i] + fn * 2); \ + break; \ + case e32: \ + P.VU.elt<uint32_t>(vd + fn * flmul, vreg_inx, true) = \ + MMU.load<uint32_t>(baseAddr + index[i] + fn * 4); \ + break; \ + default: \ + P.VU.elt<uint64_t>(vd + fn * flmul, vreg_inx, true) = \ + MMU.load<uint64_t>(baseAddr + index[i] + fn * 8); \ + break; \ + } \ + } \ + } \ + P.VU.vstart->write(0); + +#define VI_ST(stride, offset, elt_width, is_mask_ldst) \ + const reg_t nf = insn.v_nf() + 1; \ + const reg_t vl = is_mask_ldst ? ((P.VU.vl->read() + 7) / 8) : P.VU.vl->read(); \ + const reg_t baseAddr = RS1; \ + const reg_t vs3 = insn.rd(); \ + VI_CHECK_STORE(elt_width, is_mask_ldst); \ + for (reg_t i = 0; i < vl; ++i) { \ + VI_STRIP(i) \ + VI_ELEMENT_SKIP; \ + P.VU.vstart->write(i); \ + for (reg_t fn = 0; fn < nf; ++fn) { \ + elt_width##_t val = P.VU.elt<elt_width##_t>(vs3 + fn * emul, vreg_inx); \ + MMU.store<elt_width##_t>( \ + baseAddr + (stride) + (offset) * sizeof(elt_width##_t), val); \ + } \ + } \ + P.VU.vstart->write(0); + +#define VI_ST_INDEX(elt_width, is_seg) \ + const reg_t nf = insn.v_nf() + 1; \ + const reg_t vl = P.VU.vl->read(); \ + const reg_t baseAddr = RS1; \ + const reg_t vs3 = insn.rd(); \ + if (!is_seg) \ + require(nf == 1); \ + VI_CHECK_ST_INDEX(elt_width); \ + VI_DUPLICATE_VREG(insn.rs2(), elt_width); \ + for (reg_t i = 0; i < vl; ++i) { \ + VI_STRIP(i) \ + VI_ELEMENT_SKIP; \ + P.VU.vstart->write(i); \ + for (reg_t fn = 0; fn < nf; ++fn) { \ + switch (P.VU.vsew) { \ + case e8: \ + MMU.store<uint8_t>(baseAddr + index[i] + fn * 1, \ + P.VU.elt<uint8_t>(vs3 + fn * flmul, vreg_inx)); \ + break; \ + case e16: \ + MMU.store<uint16_t>(baseAddr + index[i] + fn * 2, \ + P.VU.elt<uint16_t>(vs3 + fn * flmul, vreg_inx)); \ + break; \ + case e32: \ + MMU.store<uint32_t>(baseAddr + index[i] + fn * 4, \ + P.VU.elt<uint32_t>(vs3 + fn * flmul, vreg_inx)); \ + break; \ + default: \ + MMU.store<uint64_t>(baseAddr + index[i] + fn * 8, \ + P.VU.elt<uint64_t>(vs3 + fn * flmul, vreg_inx)); \ + break; \ + } \ + } \ + } \ + P.VU.vstart->write(0); + +#define VI_LDST_FF(elt_width) \ + const reg_t nf = insn.v_nf() + 1; \ + const reg_t vl = p->VU.vl->read(); \ + const reg_t baseAddr = RS1; \ + const reg_t rd_num = insn.rd(); \ + VI_CHECK_LOAD(elt_width, false); \ + bool early_stop = false; \ + for (reg_t i = p->VU.vstart->read(); i < vl; ++i) { \ + VI_STRIP(i); \ + VI_ELEMENT_SKIP; \ + \ + for (reg_t fn = 0; fn < nf; ++fn) { \ + uint64_t val; \ + try { \ + val = MMU.load<elt_width##_t>( \ + baseAddr + (i * nf + fn) * sizeof(elt_width##_t)); \ + } catch (trap_t& t) { \ + if (i == 0) \ + throw; /* Only take exception on zeroth element */ \ + /* Reduce VL if an exception occurs on a later element */ \ + early_stop = true; \ + P.VU.vl->write_raw(i); \ + break; \ + } \ + p->VU.elt<elt_width##_t>(rd_num + fn * emul, vreg_inx, true) = val; \ + } \ + \ + if (early_stop) { \ + break; \ + } \ + } \ + p->VU.vstart->write(0); + +#define VI_LD_WHOLE(elt_width) \ + require_vector_novtype(true); \ + require(sizeof(elt_width ## _t) * 8 <= P.VU.ELEN); \ + const reg_t baseAddr = RS1; \ + const reg_t vd = insn.rd(); \ + const reg_t len = insn.v_nf() + 1; \ + require_align(vd, len); \ + const reg_t elt_per_reg = P.VU.vlenb / sizeof(elt_width ## _t); \ + const reg_t size = len * elt_per_reg; \ + if (P.VU.vstart->read() < size) { \ + reg_t i = P.VU.vstart->read() / elt_per_reg; \ + reg_t off = P.VU.vstart->read() % elt_per_reg; \ + if (off) { \ + for (reg_t pos = off; pos < elt_per_reg; ++pos) { \ + auto val = MMU.load<elt_width##_t>(baseAddr + \ + P.VU.vstart->read() * sizeof(elt_width ## _t)); \ + P.VU.elt<elt_width ## _t>(vd + i, pos, true) = val; \ + P.VU.vstart->write(P.VU.vstart->read() + 1); \ + } \ + ++i; \ + } \ + for (; i < len; ++i) { \ + for (reg_t pos = 0; pos < elt_per_reg; ++pos) { \ + auto val = MMU.load<elt_width##_t>(baseAddr + \ + P.VU.vstart->read() * sizeof(elt_width ## _t)); \ + P.VU.elt<elt_width ## _t>(vd + i, pos, true) = val; \ + P.VU.vstart->write(P.VU.vstart->read() + 1); \ + } \ + } \ + } \ + P.VU.vstart->write(0); + +#define VI_ST_WHOLE \ + require_vector_novtype(true); \ + const reg_t baseAddr = RS1; \ + const reg_t vs3 = insn.rd(); \ + const reg_t len = insn.v_nf() + 1; \ + require_align(vs3, len); \ + const reg_t size = len * P.VU.vlenb; \ + \ + if (P.VU.vstart->read() < size) { \ + reg_t i = P.VU.vstart->read() / P.VU.vlenb; \ + reg_t off = P.VU.vstart->read() % P.VU.vlenb; \ + if (off) { \ + for (reg_t pos = off; pos < P.VU.vlenb; ++pos) { \ + auto val = P.VU.elt<uint8_t>(vs3 + i, pos); \ + MMU.store<uint8_t>(baseAddr + P.VU.vstart->read(), val); \ + P.VU.vstart->write(P.VU.vstart->read() + 1); \ + } \ + i++; \ + } \ + for (; i < len; ++i) { \ + for (reg_t pos = 0; pos < P.VU.vlenb; ++pos) { \ + auto val = P.VU.elt<uint8_t>(vs3 + i, pos); \ + MMU.store<uint8_t>(baseAddr + P.VU.vstart->read(), val); \ + P.VU.vstart->write(P.VU.vstart->read() + 1); \ + } \ + } \ + } \ + P.VU.vstart->write(0); + +// +// vector: amo +// +#define VI_AMO(op, type, idx_type) \ + require_vector(false); \ + require_align(insn.rd(), P.VU.vflmul); \ + require(P.VU.vsew <= P.get_xlen() && P.VU.vsew >= 32); \ + require_align(insn.rd(), P.VU.vflmul); \ + float vemul = ((float)idx_type / P.VU.vsew * P.VU.vflmul); \ + require(vemul >= 0.125 && vemul <= 8); \ + require_align(insn.rs2(), vemul); \ + if (insn.v_wd()) { \ + require_vm; \ + if (idx_type > P.VU.vsew) { \ + if (insn.rd() != insn.rs2()) \ + require_noover(insn.rd(), P.VU.vflmul, insn.rs2(), vemul); \ + } else if (idx_type < P.VU.vsew) { \ + if (vemul < 1) { \ + require_noover(insn.rd(), P.VU.vflmul, insn.rs2(), vemul); \ + } else { \ + require_noover_widen(insn.rd(), P.VU.vflmul, insn.rs2(), vemul); \ + } \ + } \ + } \ + VI_DUPLICATE_VREG(insn.rs2(), idx_type); \ + const reg_t vl = P.VU.vl->read(); \ + const reg_t baseAddr = RS1; \ + const reg_t vd = insn.rd(); \ + for (reg_t i = P.VU.vstart->read(); i < vl; ++i) { \ + VI_ELEMENT_SKIP; \ + VI_STRIP(i); \ + P.VU.vstart->write(i); \ + switch (P.VU.vsew) { \ + case e32: { \ + auto vs3 = P.VU.elt< type ## 32_t>(vd, vreg_inx); \ + auto val = MMU.amo<uint32_t>(baseAddr + index[i], [&](type ## 32_t UNUSED lhs) { op }); \ + if (insn.v_wd()) \ + P.VU.elt< type ## 32_t>(vd, vreg_inx, true) = val; \ + } \ + break; \ + case e64: { \ + auto vs3 = P.VU.elt< type ## 64_t>(vd, vreg_inx); \ + auto val = MMU.amo<uint64_t>(baseAddr + index[i], [&](type ## 64_t UNUSED lhs) { op }); \ + if (insn.v_wd()) \ + P.VU.elt< type ## 64_t>(vd, vreg_inx, true) = val; \ + } \ + break; \ + default: \ + require(0); \ + break; \ + } \ + } \ + P.VU.vstart->write(0); + +// vector: sign/unsiged extension +#define VI_VV_EXT(div, type) \ + require(insn.rd() != insn.rs2()); \ + require_vm; \ + reg_t from = P.VU.vsew / div; \ + require(from >= e8 && from <= e64); \ + require(((float)P.VU.vflmul / div) >= 0.125 && ((float)P.VU.vflmul / div) <= 8 ); \ + require_align(insn.rd(), P.VU.vflmul); \ + require_align(insn.rs2(), P.VU.vflmul / div); \ + if ((P.VU.vflmul / div) < 1) { \ + require_noover(insn.rd(), P.VU.vflmul, insn.rs2(), P.VU.vflmul / div); \ + } else { \ + require_noover_widen(insn.rd(), P.VU.vflmul, insn.rs2(), P.VU.vflmul / div); \ + } \ + reg_t pat = (((P.VU.vsew >> 3) << 4) | from >> 3); \ + VI_GENERAL_LOOP_BASE \ + VI_LOOP_ELEMENT_SKIP(); \ + switch (pat) { \ + case 0x21: \ + P.VU.elt<type##16_t>(rd_num, i, true) = P.VU.elt<type##8_t>(rs2_num, i); \ + break; \ + case 0x41: \ + P.VU.elt<type##32_t>(rd_num, i, true) = P.VU.elt<type##8_t>(rs2_num, i); \ + break; \ + case 0x81: \ + P.VU.elt<type##64_t>(rd_num, i, true) = P.VU.elt<type##8_t>(rs2_num, i); \ + break; \ + case 0x42: \ + P.VU.elt<type##32_t>(rd_num, i, true) = P.VU.elt<type##16_t>(rs2_num, i); \ + break; \ + case 0x82: \ + P.VU.elt<type##64_t>(rd_num, i, true) = P.VU.elt<type##16_t>(rs2_num, i); \ + break; \ + case 0x84: \ + P.VU.elt<type##64_t>(rd_num, i, true) = P.VU.elt<type##32_t>(rs2_num, i); \ + break; \ + default: \ + break; \ + } \ + VI_LOOP_END + +// +// vector: vfp helper +// +#define VI_VFP_COMMON \ + require_fp; \ + require((P.VU.vsew == e16 && p->extension_enabled(EXT_ZVFH)) || \ + (P.VU.vsew == e32 && p->extension_enabled('F')) || \ + (P.VU.vsew == e64 && p->extension_enabled('D'))); \ + require_vector(true); \ + require(STATE.frm->read() < 0x5); \ + reg_t UNUSED vl = P.VU.vl->read(); \ + reg_t UNUSED rd_num = insn.rd(); \ + reg_t UNUSED rs1_num = insn.rs1(); \ + reg_t UNUSED rs2_num = insn.rs2(); \ + softfloat_roundingMode = STATE.frm->read(); + +#define VI_VFP_LOOP_BASE \ + VI_VFP_COMMON \ + for (reg_t i = P.VU.vstart->read(); i < vl; ++i) { \ + VI_LOOP_ELEMENT_SKIP(); + +#define VI_VFP_LOOP_CMP_BASE \ + VI_VFP_COMMON \ + for (reg_t i = P.VU.vstart->read(); i < vl; ++i) { \ + VI_LOOP_ELEMENT_SKIP(); \ + uint64_t mmask = UINT64_C(1) << mpos; \ + uint64_t &vd = P.VU.elt<uint64_t>(rd_num, midx, true); \ + uint64_t res = 0; + +#define VI_VFP_LOOP_REDUCTION_BASE(width) \ + float##width##_t vd_0 = P.VU.elt<float##width##_t>(rd_num, 0); \ + float##width##_t vs1_0 = P.VU.elt<float##width##_t>(rs1_num, 0); \ + vd_0 = vs1_0; \ + bool is_active = false; \ + for (reg_t i = P.VU.vstart->read(); i < vl; ++i) { \ + VI_LOOP_ELEMENT_SKIP(); \ + float##width##_t vs2 = P.VU.elt<float##width##_t>(rs2_num, i); \ + is_active = true; \ + +#define VI_VFP_LOOP_WIDE_REDUCTION_BASE \ + VI_VFP_COMMON \ + float64_t vd_0 = f64(P.VU.elt<float64_t>(rs1_num, 0).v); \ + for (reg_t i = P.VU.vstart->read(); i < vl; ++i) { \ + VI_LOOP_ELEMENT_SKIP(); + +#define VI_VFP_LOOP_END \ + } \ + P.VU.vstart->write(0); \ + +#define VI_VFP_LOOP_REDUCTION_END(x) \ + } \ + P.VU.vstart->write(0); \ + if (vl > 0) { \ + if (is_propagate && !is_active) { \ + switch (x) { \ + case e16: { \ + auto ret = f16_classify(f16(vd_0.v)); \ + if (ret & 0x300) { \ + if (ret & 0x100) { \ + softfloat_exceptionFlags |= softfloat_flag_invalid; \ + set_fp_exceptions; \ + } \ + P.VU.elt<uint16_t>(rd_num, 0, true) = defaultNaNF16UI; \ + } else { \ + P.VU.elt<uint16_t>(rd_num, 0, true) = vd_0.v; \ + } \ + } \ + break; \ + case e32: { \ + auto ret = f32_classify(f32(vd_0.v)); \ + if (ret & 0x300) { \ + if (ret & 0x100) { \ + softfloat_exceptionFlags |= softfloat_flag_invalid; \ + set_fp_exceptions; \ + } \ + P.VU.elt<uint32_t>(rd_num, 0, true) = defaultNaNF32UI; \ + } else { \ + P.VU.elt<uint32_t>(rd_num, 0, true) = vd_0.v; \ + } \ + } \ + break; \ + case e64: { \ + auto ret = f64_classify(f64(vd_0.v)); \ + if (ret & 0x300) { \ + if (ret & 0x100) { \ + softfloat_exceptionFlags |= softfloat_flag_invalid; \ + set_fp_exceptions; \ + } \ + P.VU.elt<uint64_t>(rd_num, 0, true) = defaultNaNF64UI; \ + } else { \ + P.VU.elt<uint64_t>(rd_num, 0, true) = vd_0.v; \ + } \ + } \ + break; \ + } \ + } else { \ + P.VU.elt<type_sew_t<x>::type>(rd_num, 0, true) = vd_0.v; \ + } \ + } + +#define VI_VFP_LOOP_CMP_END \ + switch (P.VU.vsew) { \ + case e16: \ + case e32: \ + case e64: { \ + vd = (vd & ~mmask) | (((res) << mpos) & mmask); \ + break; \ + } \ + default: \ + require(0); \ + break; \ + }; \ + } \ + P.VU.vstart->write(0); + +#define VI_VFP_VV_LOOP(BODY16, BODY32, BODY64) \ + VI_CHECK_SSS(true); \ + VI_VFP_LOOP_BASE \ + switch (P.VU.vsew) { \ + case e16: { \ + VFP_VV_PARAMS(16); \ + BODY16; \ + set_fp_exceptions; \ + break; \ + } \ + case e32: { \ + VFP_VV_PARAMS(32); \ + BODY32; \ + set_fp_exceptions; \ + break; \ + } \ + case e64: { \ + VFP_VV_PARAMS(64); \ + BODY64; \ + set_fp_exceptions; \ + break; \ + } \ + default: \ + require(0); \ + break; \ + }; \ + DEBUG_RVV_FP_VV; \ + VI_VFP_LOOP_END + +#define VI_VFP_V_LOOP(BODY16, BODY32, BODY64) \ + VI_CHECK_SSS(false); \ + VI_VFP_LOOP_BASE \ + switch (P.VU.vsew) { \ + case e16: { \ + VFP_V_PARAMS(16); \ + BODY16; \ + break; \ + } \ + case e32: { \ + VFP_V_PARAMS(32); \ + BODY32; \ + break; \ + } \ + case e64: { \ + VFP_V_PARAMS(64); \ + BODY64; \ + break; \ + } \ + default: \ + require(0); \ + break; \ + }; \ + set_fp_exceptions; \ + VI_VFP_LOOP_END + +#define VI_VFP_VV_LOOP_REDUCTION(BODY16, BODY32, BODY64) \ + VI_CHECK_REDUCTION(false) \ + VI_VFP_COMMON \ + switch (P.VU.vsew) { \ + case e16: { \ + VI_VFP_LOOP_REDUCTION_BASE(16) \ + BODY16; \ + set_fp_exceptions; \ + VI_VFP_LOOP_REDUCTION_END(e16) \ + break; \ + } \ + case e32: { \ + VI_VFP_LOOP_REDUCTION_BASE(32) \ + BODY32; \ + set_fp_exceptions; \ + VI_VFP_LOOP_REDUCTION_END(e32) \ + break; \ + } \ + case e64: { \ + VI_VFP_LOOP_REDUCTION_BASE(64) \ + BODY64; \ + set_fp_exceptions; \ + VI_VFP_LOOP_REDUCTION_END(e64) \ + break; \ + } \ + default: \ + require(0); \ + break; \ + }; \ + +#define VI_VFP_VV_LOOP_WIDE_REDUCTION(BODY16, BODY32) \ + VI_CHECK_REDUCTION(true) \ + VI_VFP_COMMON \ + require((P.VU.vsew == e16 && p->extension_enabled('F')) || \ + (P.VU.vsew == e32 && p->extension_enabled('D'))); \ + bool is_active = false; \ + switch (P.VU.vsew) { \ + case e16: { \ + float32_t vd_0 = P.VU.elt<float32_t>(rs1_num, 0); \ + for (reg_t i = P.VU.vstart->read(); i < vl; ++i) { \ + VI_LOOP_ELEMENT_SKIP(); \ + is_active = true; \ + float32_t vs2 = f16_to_f32(P.VU.elt<float16_t>(rs2_num, i)); \ + BODY16; \ + set_fp_exceptions; \ + VI_VFP_LOOP_REDUCTION_END(e32) \ + break; \ + } \ + case e32: { \ + float64_t vd_0 = P.VU.elt<float64_t>(rs1_num, 0); \ + for (reg_t i = P.VU.vstart->read(); i < vl; ++i) { \ + VI_LOOP_ELEMENT_SKIP(); \ + is_active = true; \ + float64_t vs2 = f32_to_f64(P.VU.elt<float32_t>(rs2_num, i)); \ + BODY32; \ + set_fp_exceptions; \ + VI_VFP_LOOP_REDUCTION_END(e64) \ + break; \ + } \ + default: \ + require(0); \ + break; \ + }; \ + +#define VI_VFP_VF_LOOP(BODY16, BODY32, BODY64) \ + VI_CHECK_SSS(false); \ + VI_VFP_LOOP_BASE \ + switch (P.VU.vsew) { \ + case e16: { \ + VFP_VF_PARAMS(16); \ + BODY16; \ + set_fp_exceptions; \ + break; \ + } \ + case e32: { \ + VFP_VF_PARAMS(32); \ + BODY32; \ + set_fp_exceptions; \ + break; \ + } \ + case e64: { \ + VFP_VF_PARAMS(64); \ + BODY64; \ + set_fp_exceptions; \ + break; \ + } \ + default: \ + require(0); \ + break; \ + }; \ + DEBUG_RVV_FP_VF; \ + VI_VFP_LOOP_END + +#define VI_VFP_VV_LOOP_CMP(BODY16, BODY32, BODY64) \ + VI_CHECK_MSS(true); \ + VI_VFP_LOOP_CMP_BASE \ + switch (P.VU.vsew) { \ + case e16: { \ + VFP_VV_CMP_PARAMS(16); \ + BODY16; \ + set_fp_exceptions; \ + break; \ + } \ + case e32: { \ + VFP_VV_CMP_PARAMS(32); \ + BODY32; \ + set_fp_exceptions; \ + break; \ + } \ + case e64: { \ + VFP_VV_CMP_PARAMS(64); \ + BODY64; \ + set_fp_exceptions; \ + break; \ + } \ + default: \ + require(0); \ + break; \ + }; \ + VI_VFP_LOOP_CMP_END \ + +#define VI_VFP_VF_LOOP_CMP(BODY16, BODY32, BODY64) \ + VI_CHECK_MSS(false); \ + VI_VFP_LOOP_CMP_BASE \ + switch (P.VU.vsew) { \ + case e16: { \ + VFP_VF_CMP_PARAMS(16); \ + BODY16; \ + set_fp_exceptions; \ + break; \ + } \ + case e32: { \ + VFP_VF_CMP_PARAMS(32); \ + BODY32; \ + set_fp_exceptions; \ + break; \ + } \ + case e64: { \ + VFP_VF_CMP_PARAMS(64); \ + BODY64; \ + set_fp_exceptions; \ + break; \ + } \ + default: \ + require(0); \ + break; \ + }; \ + VI_VFP_LOOP_CMP_END \ + +#define VI_VFP_VF_LOOP_WIDE(BODY16, BODY32) \ + VI_CHECK_DSS(false); \ + VI_VFP_LOOP_BASE \ + switch (P.VU.vsew) { \ + case e16: { \ + float32_t &vd = P.VU.elt<float32_t>(rd_num, i, true); \ + float32_t vs2 = f16_to_f32(P.VU.elt<float16_t>(rs2_num, i)); \ + float32_t rs1 = f16_to_f32(FRS1_H); \ + BODY16; \ + set_fp_exceptions; \ + break; \ + } \ + case e32: { \ + float64_t &vd = P.VU.elt<float64_t>(rd_num, i, true); \ + float64_t vs2 = f32_to_f64(P.VU.elt<float32_t>(rs2_num, i)); \ + float64_t rs1 = f32_to_f64(FRS1_F); \ + BODY32; \ + set_fp_exceptions; \ + break; \ + } \ + default: \ + require(0); \ + break; \ + }; \ + DEBUG_RVV_FP_VV; \ + VI_VFP_LOOP_END + +#define VI_VFP_VV_LOOP_WIDE(BODY16, BODY32) \ + VI_CHECK_DSS(true); \ + VI_VFP_LOOP_BASE \ + switch (P.VU.vsew) { \ + case e16: { \ + float32_t &vd = P.VU.elt<float32_t>(rd_num, i, true); \ + float32_t vs2 = f16_to_f32(P.VU.elt<float16_t>(rs2_num, i)); \ + float32_t vs1 = f16_to_f32(P.VU.elt<float16_t>(rs1_num, i)); \ + BODY16; \ + set_fp_exceptions; \ + break; \ + } \ + case e32: { \ + float64_t &vd = P.VU.elt<float64_t>(rd_num, i, true); \ + float64_t vs2 = f32_to_f64(P.VU.elt<float32_t>(rs2_num, i)); \ + float64_t vs1 = f32_to_f64(P.VU.elt<float32_t>(rs1_num, i)); \ + BODY32; \ + set_fp_exceptions; \ + break; \ + } \ + default: \ + require(0); \ + break; \ + }; \ + DEBUG_RVV_FP_VV; \ + VI_VFP_LOOP_END + +#define VI_VFP_WF_LOOP_WIDE(BODY16, BODY32) \ + VI_CHECK_DDS(false); \ + VI_VFP_LOOP_BASE \ + switch (P.VU.vsew) { \ + case e16: { \ + float32_t &vd = P.VU.elt<float32_t>(rd_num, i, true); \ + float32_t vs2 = P.VU.elt<float32_t>(rs2_num, i); \ + float32_t rs1 = f16_to_f32(FRS1_H); \ + BODY16; \ + set_fp_exceptions; \ + break; \ + } \ + case e32: { \ + float64_t &vd = P.VU.elt<float64_t>(rd_num, i, true); \ + float64_t vs2 = P.VU.elt<float64_t>(rs2_num, i); \ + float64_t rs1 = f32_to_f64(FRS1_F); \ + BODY32; \ + set_fp_exceptions; \ + break; \ + } \ + default: \ + require(0); \ + }; \ + DEBUG_RVV_FP_VV; \ + VI_VFP_LOOP_END + +#define VI_VFP_WV_LOOP_WIDE(BODY16, BODY32) \ + VI_CHECK_DDS(true); \ + VI_VFP_LOOP_BASE \ + switch (P.VU.vsew) { \ + case e16: { \ + float32_t &vd = P.VU.elt<float32_t>(rd_num, i, true); \ + float32_t vs2 = P.VU.elt<float32_t>(rs2_num, i); \ + float32_t vs1 = f16_to_f32(P.VU.elt<float16_t>(rs1_num, i)); \ + BODY16; \ + set_fp_exceptions; \ + break; \ + } \ + case e32: { \ + float64_t &vd = P.VU.elt<float64_t>(rd_num, i, true); \ + float64_t vs2 = P.VU.elt<float64_t>(rs2_num, i); \ + float64_t vs1 = f32_to_f64(P.VU.elt<float32_t>(rs1_num, i)); \ + BODY32; \ + set_fp_exceptions; \ + break; \ + } \ + default: \ + require(0); \ + }; \ + DEBUG_RVV_FP_VV; \ + VI_VFP_LOOP_END + +#define VI_VFP_LOOP_SCALE_BASE \ + require_fp; \ + require_vector(true); \ + require(STATE.frm->read() < 0x5); \ + reg_t vl = P.VU.vl->read(); \ + reg_t rd_num = insn.rd(); \ + reg_t UNUSED rs1_num = insn.rs1(); \ + reg_t rs2_num = insn.rs2(); \ + softfloat_roundingMode = STATE.frm->read(); \ + for (reg_t i = P.VU.vstart->read(); i < vl; ++i) { \ + VI_LOOP_ELEMENT_SKIP(); + +#define VI_VFP_CVT_LOOP(CVT_PARAMS, CHECK, BODY) \ + CHECK \ + VI_VFP_LOOP_SCALE_BASE \ + CVT_PARAMS \ + BODY \ + set_fp_exceptions; \ + VI_VFP_LOOP_END + +#define VI_VFP_CVT_INT_TO_FP(BODY16, BODY32, BODY64, sign) \ + VI_CHECK_SSS(false); \ + VI_VFP_COMMON \ + switch (P.VU.vsew) { \ + case e16: \ + { VI_VFP_CVT_LOOP(CVT_INT_TO_FP_PARAMS(16, 16, sign), \ + { p->extension_enabled(EXT_ZVFH); }, \ + BODY16); } \ + break; \ + case e32: \ + { VI_VFP_CVT_LOOP(CVT_INT_TO_FP_PARAMS(32, 32, sign), \ + { p->extension_enabled('F'); }, \ + BODY32); } \ + break; \ + case e64: \ + { VI_VFP_CVT_LOOP(CVT_INT_TO_FP_PARAMS(64, 64, sign), \ + { p->extension_enabled('D'); }, \ + BODY64); } \ + break; \ + default: \ + require(0); \ + break; \ + } + +#define VI_VFP_CVT_FP_TO_INT(BODY16, BODY32, BODY64, sign) \ + VI_CHECK_SSS(false); \ + VI_VFP_COMMON \ + switch (P.VU.vsew) { \ + case e16: \ + { VI_VFP_CVT_LOOP(CVT_FP_TO_INT_PARAMS(16, 16, sign), \ + { p->extension_enabled(EXT_ZVFH); }, \ + BODY16); } \ + break; \ + case e32: \ + { VI_VFP_CVT_LOOP(CVT_FP_TO_INT_PARAMS(32, 32, sign), \ + { p->extension_enabled('F'); }, \ + BODY32); } \ + break; \ + case e64: \ + { VI_VFP_CVT_LOOP(CVT_FP_TO_INT_PARAMS(64, 64, sign), \ + { p->extension_enabled('D'); }, \ + BODY64); } \ + break; \ + default: \ + require(0); \ + break; \ + } + +#define VI_VFP_WCVT_FP_TO_FP(BODY16, BODY32, \ + CHECK16, CHECK32) \ + VI_CHECK_DSS(false); \ + switch (P.VU.vsew) { \ + case e16: \ + { VI_VFP_CVT_LOOP(CVT_FP_TO_FP_PARAMS(16, 32), CHECK16, BODY16); } \ + break; \ + case e32: \ + { VI_VFP_CVT_LOOP(CVT_FP_TO_FP_PARAMS(32, 64), CHECK32, BODY32); } \ + break; \ + default: \ + require(0); \ + break; \ + } + +#define VI_VFP_WCVT_INT_TO_FP(BODY8, BODY16, BODY32, \ + CHECK8, CHECK16, CHECK32, \ + sign) \ + VI_CHECK_DSS(false); \ + switch (P.VU.vsew) { \ + case e8: \ + { VI_VFP_CVT_LOOP(CVT_INT_TO_FP_PARAMS(8, 16, sign), CHECK8, BODY8); } \ + break; \ + case e16: \ + { VI_VFP_CVT_LOOP(CVT_INT_TO_FP_PARAMS(16, 32, sign), CHECK16, BODY16); } \ + break; \ + case e32: \ + { VI_VFP_CVT_LOOP(CVT_INT_TO_FP_PARAMS(32, 64, sign), CHECK32, BODY32); } \ + break; \ + default: \ + require(0); \ + break; \ + } + +#define VI_VFP_WCVT_FP_TO_INT(BODY16, BODY32, \ + CHECK16, CHECK32, \ + sign) \ + VI_CHECK_DSS(false); \ + switch (P.VU.vsew) { \ + case e16: \ + { VI_VFP_CVT_LOOP(CVT_FP_TO_INT_PARAMS(16, 32, sign), CHECK16, BODY16); } \ + break; \ + case e32: \ + { VI_VFP_CVT_LOOP(CVT_FP_TO_INT_PARAMS(32, 64, sign), CHECK32, BODY32); } \ + break; \ + default: \ + require(0); \ + break; \ + } + +#define VI_VFP_NCVT_FP_TO_FP(BODY32, BODY64, \ + CHECK32, CHECK64) \ + VI_CHECK_SDS(false); \ + switch (P.VU.vsew) { \ + case e16: \ + { VI_VFP_CVT_LOOP(CVT_FP_TO_FP_PARAMS(32, 16), CHECK32, BODY32); } \ + break; \ + case e32: \ + { VI_VFP_CVT_LOOP(CVT_FP_TO_FP_PARAMS(64, 32), CHECK64, BODY64); } \ + break; \ + default: \ + require(0); \ + break; \ + } + +#define VI_VFP_NCVT_INT_TO_FP(BODY32, BODY64, \ + CHECK32, CHECK64, \ + sign) \ + VI_CHECK_SDS(false); \ + switch (P.VU.vsew) { \ + case e16: \ + { VI_VFP_CVT_LOOP(CVT_INT_TO_FP_PARAMS(32, 16, sign), CHECK32, BODY32); } \ + break; \ + case e32: \ + { VI_VFP_CVT_LOOP(CVT_INT_TO_FP_PARAMS(64, 32, sign), CHECK64, BODY64); } \ + break; \ + default: \ + require(0); \ + break; \ + } + +#define VI_VFP_NCVT_FP_TO_INT(BODY16, BODY32, BODY64, \ + CHECK16, CHECK32, CHECK64, \ + sign) \ + VI_CHECK_SDS(false); \ + switch (P.VU.vsew) { \ + case e8: \ + { VI_VFP_CVT_LOOP(CVT_FP_TO_INT_PARAMS(16, 8, sign), CHECK16, BODY16); } \ + break; \ + case e16: \ + { VI_VFP_CVT_LOOP(CVT_FP_TO_INT_PARAMS(32, 16, sign), CHECK32, BODY32); } \ + break; \ + case e32: \ + { VI_VFP_CVT_LOOP(CVT_FP_TO_INT_PARAMS(64, 32, sign), CHECK64, BODY64); } \ + break; \ + default: \ + require(0); \ + break; \ + } + +#endif diff --git a/vendor/riscv/riscv-isa-sim/riscv/vector_unit.cc b/vendor/riscv/riscv-isa-sim/riscv/vector_unit.cc new file mode 100644 index 0000000000..ff3dd82fb9 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/vector_unit.cc @@ -0,0 +1,100 @@ +// See LICENSE for license details + +#include "config.h" +#include "vector_unit.h" +#include "processor.h" +#include "arith.h" + +void vectorUnit_t::vectorUnit_t::reset() +{ + free(reg_file); + VLEN = get_vlen(); + ELEN = get_elen(); + reg_file = malloc(NVPR * vlenb); + memset(reg_file, 0, NVPR * vlenb); + + auto& csrmap = p->get_state()->csrmap; + csrmap[CSR_VXSAT] = vxsat = std::make_shared<vxsat_csr_t>(p, CSR_VXSAT); + csrmap[CSR_VSTART] = vstart = std::make_shared<vector_csr_t>(p, CSR_VSTART, /*mask*/ VLEN - 1); + csrmap[CSR_VXRM] = vxrm = std::make_shared<vector_csr_t>(p, CSR_VXRM, /*mask*/ 0x3ul); + csrmap[CSR_VL] = vl = std::make_shared<vector_csr_t>(p, CSR_VL, /*mask*/ 0); + csrmap[CSR_VTYPE] = vtype = std::make_shared<vector_csr_t>(p, CSR_VTYPE, /*mask*/ 0); + csrmap[CSR_VLENB] = std::make_shared<vector_csr_t>(p, CSR_VLENB, /*mask*/ 0, /*init*/ vlenb); + assert(VCSR_VXSAT_SHIFT == 0); // composite_csr_t assumes vxsat begins at bit 0 + csrmap[CSR_VCSR] = std::make_shared<composite_csr_t>(p, CSR_VCSR, vxrm, vxsat, VCSR_VXRM_SHIFT); + + vtype->write_raw(0); + set_vl(0, 0, 0, -1); // default to illegal configuration +} + +reg_t vectorUnit_t::vectorUnit_t::set_vl(int rd, int rs1, reg_t reqVL, reg_t newType) +{ + int new_vlmul = 0; + if (vtype->read() != newType) { + vsew = 1 << (extract64(newType, 3, 3) + 3); + new_vlmul = int8_t(extract64(newType, 0, 3) << 5) >> 5; + vflmul = new_vlmul >= 0 ? 1 << new_vlmul : 1.0 / (1 << -new_vlmul); + vlmax = (VLEN/vsew) * vflmul; + vta = extract64(newType, 6, 1); + vma = extract64(newType, 7, 1); + + vill = !(vflmul >= 0.125 && vflmul <= 8) + || vsew > std::min(vflmul, 1.0f) * ELEN + || (newType >> 8) != 0; + + if (vill) { + vlmax = 0; + vtype->write_raw(UINT64_MAX << (p->get_xlen() - 1)); + } else { + vtype->write_raw(newType); + } + } + + // set vl + if (vlmax == 0) { + vl->write_raw(0); + } else if (rd == 0 && rs1 == 0) { + vl->write_raw(vl->read() > vlmax ? vlmax : vl->read()); + } else if (rd != 0 && rs1 == 0) { + vl->write_raw(vlmax); + } else if (rs1 != 0) { + vl->write_raw(reqVL > vlmax ? vlmax : reqVL); + } + + vstart->write_raw(0); + setvl_count++; + return vl->read(); +} + +template<class T> T& vectorUnit_t::elt(reg_t vReg, reg_t n, bool UNUSED is_write) { + assert(vsew != 0); + assert((VLEN >> 3)/sizeof(T) > 0); + reg_t elts_per_reg = (VLEN >> 3) / (sizeof(T)); + vReg += n / elts_per_reg; + n = n % elts_per_reg; +#ifdef WORDS_BIGENDIAN + // "V" spec 0.7.1 requires lower indices to map to lower significant + // bits when changing SEW, thus we need to index from the end on BE. + n ^= elts_per_reg - 1; +#endif + reg_referenced[vReg] = 1; + + if (unlikely(p->get_log_commits_enabled() && is_write)) + p->get_state()->log_reg_write[((vReg) << 4) | 2] = {0, 0}; + + T *regStart = (T*)((char*)reg_file + vReg * (VLEN >> 3)); + return regStart[n]; +} + +template signed char& vectorUnit_t::elt<signed char>(reg_t, reg_t, bool); +template short& vectorUnit_t::elt<short>(reg_t, reg_t, bool); +template int& vectorUnit_t::elt<int>(reg_t, reg_t, bool); +template long& vectorUnit_t::elt<long>(reg_t, reg_t, bool); +template long long& vectorUnit_t::elt<long long>(reg_t, reg_t, bool); +template uint8_t& vectorUnit_t::elt<uint8_t>(reg_t, reg_t, bool); +template uint16_t& vectorUnit_t::elt<uint16_t>(reg_t, reg_t, bool); +template uint32_t& vectorUnit_t::elt<uint32_t>(reg_t, reg_t, bool); +template uint64_t& vectorUnit_t::elt<uint64_t>(reg_t, reg_t, bool); +template float16_t& vectorUnit_t::elt<float16_t>(reg_t, reg_t, bool); +template float32_t& vectorUnit_t::elt<float32_t>(reg_t, reg_t, bool); +template float64_t& vectorUnit_t::elt<float64_t>(reg_t, reg_t, bool); diff --git a/vendor/riscv/riscv-isa-sim/riscv/vector_unit.h b/vendor/riscv/riscv-isa-sim/riscv/vector_unit.h new file mode 100644 index 0000000000..b9f706c53a --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/riscv/vector_unit.h @@ -0,0 +1,135 @@ +// See LICENSE for license details. +#ifndef _RISCV_VECTOR_UNIT_H +#define _RISCV_VECTOR_UNIT_H + +#include "decode.h" +#include "csrs.h" + +class processor_t; + +enum VRM{ + RNU = 0, + RNE, + RDN, + ROD, + INVALID_RM +}; + +template<uint64_t N> +struct type_usew_t; + +template<> +struct type_usew_t<8> +{ + using type=uint8_t; +}; + +template<> +struct type_usew_t<16> +{ + using type=uint16_t; +}; + +template<> +struct type_usew_t<32> +{ + using type=uint32_t; +}; + +template<> +struct type_usew_t<64> +{ + using type=uint64_t; +}; + +template<uint64_t N> +struct type_sew_t; + +template<> +struct type_sew_t<8> +{ + using type=int8_t; +}; + +template<> +struct type_sew_t<16> +{ + using type=int16_t; +}; + +template<> +struct type_sew_t<32> +{ + using type=int32_t; +}; + +template<> +struct type_sew_t<64> +{ + using type=int64_t; +}; + + +class vectorUnit_t +{ +public: + processor_t* p; + void *reg_file; + char reg_referenced[NVPR]; + int setvl_count; + reg_t vlmax; + reg_t vlenb; + csr_t_p vxsat; + vector_csr_t_p vxrm, vstart, vl, vtype; + reg_t vma, vta; + reg_t vsew; + float vflmul; + reg_t ELEN, VLEN; + bool vill; + bool vstart_alu; + + // vector element for varies SEW + template<class T> T& elt(reg_t vReg, reg_t n, bool is_write = false); + +public: + + void reset(); + + vectorUnit_t(): + p(0), + reg_file(0), + reg_referenced{0}, + setvl_count(0), + vlmax(0), + vlenb(0), + vxsat(0), + vxrm(0), + vstart(0), + vl(0), + vtype(0), + vma(0), + vta(0), + vsew(0), + vflmul(0), + ELEN(0), + VLEN(0), + vill(false), + vstart_alu(false) { + } + + ~vectorUnit_t() { + free(reg_file); + reg_file = 0; + } + + reg_t set_vl(int rd, int rs1, reg_t reqVL, reg_t newType); + + reg_t get_vlen() { return VLEN; } + reg_t get_elen() { return ELEN; } + reg_t get_slen() { return VLEN; } + + VRM get_vround_mode() { + return (VRM)(vxrm->read()); + } +}; +#endif diff --git a/vendor/riscv/riscv-isa-sim/scripts/config.guess b/vendor/riscv/riscv-isa-sim/scripts/config.guess new file mode 100644 index 0000000000..699b3a10b2 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/scripts/config.guess @@ -0,0 +1,1698 @@ +#! /bin/sh +# Attempt to guess a canonical system name. +# Copyright 1992-2020 Free Software Foundation, Inc. + +timestamp='2020-11-19' + +# This file is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, see <https://www.gnu.org/licenses/>. +# +# As a special exception to the GNU General Public License, if you +# distribute this file as part of a program that contains a +# configuration script generated by Autoconf, you may include it under +# the same distribution terms that you use for the rest of that +# program. This Exception is an additional permission under section 7 +# of the GNU General Public License, version 3 ("GPLv3"). +# +# Originally written by Per Bothner; maintained since 2000 by Ben Elliston. +# +# You can get the latest version of this script from: +# https://git.savannah.gnu.org/cgit/config.git/plain/config.guess +# +# Please send patches to <config-patches@gnu.org>. + + +me=$(echo "$0" | sed -e 's,.*/,,') + +usage="\ +Usage: $0 [OPTION] + +Output the configuration name of the system \`$me' is run on. + +Options: + -h, --help print this help, then exit + -t, --time-stamp print date of last modification, then exit + -v, --version print version number, then exit + +Report bugs and patches to <config-patches@gnu.org>." + +version="\ +GNU config.guess ($timestamp) + +Originally written by Per Bothner. +Copyright 1992-2020 Free Software Foundation, Inc. + +This is free software; see the source for copying conditions. There is NO +warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE." + +help=" +Try \`$me --help' for more information." + +# Parse command line +while test $# -gt 0 ; do + case $1 in + --time-stamp | --time* | -t ) + echo "$timestamp" ; exit ;; + --version | -v ) + echo "$version" ; exit ;; + --help | --h* | -h ) + echo "$usage"; exit ;; + -- ) # Stop option processing + shift; break ;; + - ) # Use stdin as input. + break ;; + -* ) + echo "$me: invalid option $1$help" >&2 + exit 1 ;; + * ) + break ;; + esac +done + +if test $# != 0; then + echo "$me: too many arguments$help" >&2 + exit 1 +fi + +# CC_FOR_BUILD -- compiler used by this script. Note that the use of a +# compiler to aid in system detection is discouraged as it requires +# temporary files to be created and, as you can see below, it is a +# headache to deal with in a portable fashion. + +# Historically, `CC_FOR_BUILD' used to be named `HOST_CC'. We still +# use `HOST_CC' if defined, but it is deprecated. + +# Portable tmp directory creation inspired by the Autoconf team. + +tmp= +# shellcheck disable=SC2172 +trap 'test -z "$tmp" || rm -fr "$tmp"' 0 1 2 13 15 + +set_cc_for_build() { + # prevent multiple calls if $tmp is already set + test "$tmp" && return 0 + : "${TMPDIR=/tmp}" + # shellcheck disable=SC2039 + { tmp=$( (umask 077 && mktemp -d "$TMPDIR/cgXXXXXX") 2>/dev/null) && test -n "$tmp" && test -d "$tmp" ; } || + { test -n "$RANDOM" && tmp=$TMPDIR/cg$$-$RANDOM && (umask 077 && mkdir "$tmp" 2>/dev/null) ; } || + { tmp=$TMPDIR/cg-$$ && (umask 077 && mkdir "$tmp" 2>/dev/null) && echo "Warning: creating insecure temp directory" >&2 ; } || + { echo "$me: cannot create a temporary directory in $TMPDIR" >&2 ; exit 1 ; } + dummy=$tmp/dummy + case ${CC_FOR_BUILD-},${HOST_CC-},${CC-} in + ,,) echo "int x;" > "$dummy.c" + for driver in cc gcc c89 c99 ; do + if ($driver -c -o "$dummy.o" "$dummy.c") >/dev/null 2>&1 ; then + CC_FOR_BUILD="$driver" + break + fi + done + if test x"$CC_FOR_BUILD" = x ; then + CC_FOR_BUILD=no_compiler_found + fi + ;; + ,,*) CC_FOR_BUILD=$CC ;; + ,*,*) CC_FOR_BUILD=$HOST_CC ;; + esac +} + +# This is needed to find uname on a Pyramid OSx when run in the BSD universe. +# (ghazi@noc.rutgers.edu 1994-08-24) +if test -f /.attbin/uname ; then + PATH=$PATH:/.attbin ; export PATH +fi + +UNAME_MACHINE=$( (uname -m) 2>/dev/null) || UNAME_MACHINE=unknown +UNAME_RELEASE=$( (uname -r) 2>/dev/null) || UNAME_RELEASE=unknown +UNAME_SYSTEM=$( (uname -s) 2>/dev/null) || UNAME_SYSTEM=unknown +UNAME_VERSION=$( (uname -v) 2>/dev/null) || UNAME_VERSION=unknown + +case "$UNAME_SYSTEM" in +Linux|GNU|GNU/*) + LIBC=unknown + + set_cc_for_build + cat <<-EOF > "$dummy.c" + #include <features.h> + #if defined(__UCLIBC__) + LIBC=uclibc + #elif defined(__dietlibc__) + LIBC=dietlibc + #elif defined(__GLIBC__) + LIBC=gnu + #else + #include <stdarg.h> + /* First heuristic to detect musl libc. */ + #ifdef __DEFINED_va_list + LIBC=musl + #endif + #endif + EOF + eval "$($CC_FOR_BUILD -E "$dummy.c" 2>/dev/null | grep '^LIBC' | sed 's, ,,g')" + + # Second heuristic to detect musl libc. + if [ "$LIBC" = unknown ] && + command -v ldd >/dev/null && + ldd --version 2>&1 | grep -q ^musl; then + LIBC=musl + fi + + # If the system lacks a compiler, then just pick glibc. + # We could probably try harder. + if [ "$LIBC" = unknown ]; then + LIBC=gnu + fi + ;; +esac + +# Note: order is significant - the case branches are not exclusive. + +case "$UNAME_MACHINE:$UNAME_SYSTEM:$UNAME_RELEASE:$UNAME_VERSION" in + *:NetBSD:*:*) + # NetBSD (nbsd) targets should (where applicable) match one or + # more of the tuples: *-*-netbsdelf*, *-*-netbsdaout*, + # *-*-netbsdecoff* and *-*-netbsd*. For targets that recently + # switched to ELF, *-*-netbsd* would select the old + # object file format. This provides both forward + # compatibility and a consistent mechanism for selecting the + # object file format. + # + # Note: NetBSD doesn't particularly care about the vendor + # portion of the name. We always set it to "unknown". + sysctl="sysctl -n hw.machine_arch" + UNAME_MACHINE_ARCH=$( (uname -p 2>/dev/null || \ + "/sbin/$sysctl" 2>/dev/null || \ + "/usr/sbin/$sysctl" 2>/dev/null || \ + echo unknown)) + case "$UNAME_MACHINE_ARCH" in + aarch64eb) machine=aarch64_be-unknown ;; + armeb) machine=armeb-unknown ;; + arm*) machine=arm-unknown ;; + sh3el) machine=shl-unknown ;; + sh3eb) machine=sh-unknown ;; + sh5el) machine=sh5le-unknown ;; + earmv*) + arch=$(echo "$UNAME_MACHINE_ARCH" | sed -e 's,^e\(armv[0-9]\).*$,\1,') + endian=$(echo "$UNAME_MACHINE_ARCH" | sed -ne 's,^.*\(eb\)$,\1,p') + machine="${arch}${endian}"-unknown + ;; + *) machine="$UNAME_MACHINE_ARCH"-unknown ;; + esac + # The Operating System including object format, if it has switched + # to ELF recently (or will in the future) and ABI. + case "$UNAME_MACHINE_ARCH" in + earm*) + os=netbsdelf + ;; + arm*|i386|m68k|ns32k|sh3*|sparc|vax) + set_cc_for_build + if echo __ELF__ | $CC_FOR_BUILD -E - 2>/dev/null \ + | grep -q __ELF__ + then + # Once all utilities can be ECOFF (netbsdecoff) or a.out (netbsdaout). + # Return netbsd for either. FIX? + os=netbsd + else + os=netbsdelf + fi + ;; + *) + os=netbsd + ;; + esac + # Determine ABI tags. + case "$UNAME_MACHINE_ARCH" in + earm*) + expr='s/^earmv[0-9]/-eabi/;s/eb$//' + abi=$(echo "$UNAME_MACHINE_ARCH" | sed -e "$expr") + ;; + esac + # The OS release + # Debian GNU/NetBSD machines have a different userland, and + # thus, need a distinct triplet. However, they do not need + # kernel version information, so it can be replaced with a + # suitable tag, in the style of linux-gnu. + case "$UNAME_VERSION" in + Debian*) + release='-gnu' + ;; + *) + release=$(echo "$UNAME_RELEASE" | sed -e 's/[-_].*//' | cut -d. -f1,2) + ;; + esac + # Since CPU_TYPE-MANUFACTURER-KERNEL-OPERATING_SYSTEM: + # contains redundant information, the shorter form: + # CPU_TYPE-MANUFACTURER-OPERATING_SYSTEM is used. + echo "$machine-${os}${release}${abi-}" + exit ;; + *:Bitrig:*:*) + UNAME_MACHINE_ARCH=$(arch | sed 's/Bitrig.//') + echo "$UNAME_MACHINE_ARCH"-unknown-bitrig"$UNAME_RELEASE" + exit ;; + *:OpenBSD:*:*) + UNAME_MACHINE_ARCH=$(arch | sed 's/OpenBSD.//') + echo "$UNAME_MACHINE_ARCH"-unknown-openbsd"$UNAME_RELEASE" + exit ;; + *:LibertyBSD:*:*) + UNAME_MACHINE_ARCH=$(arch | sed 's/^.*BSD\.//') + echo "$UNAME_MACHINE_ARCH"-unknown-libertybsd"$UNAME_RELEASE" + exit ;; + *:MidnightBSD:*:*) + echo "$UNAME_MACHINE"-unknown-midnightbsd"$UNAME_RELEASE" + exit ;; + *:ekkoBSD:*:*) + echo "$UNAME_MACHINE"-unknown-ekkobsd"$UNAME_RELEASE" + exit ;; + *:SolidBSD:*:*) + echo "$UNAME_MACHINE"-unknown-solidbsd"$UNAME_RELEASE" + exit ;; + *:OS108:*:*) + echo "$UNAME_MACHINE"-unknown-os108_"$UNAME_RELEASE" + exit ;; + macppc:MirBSD:*:*) + echo powerpc-unknown-mirbsd"$UNAME_RELEASE" + exit ;; + *:MirBSD:*:*) + echo "$UNAME_MACHINE"-unknown-mirbsd"$UNAME_RELEASE" + exit ;; + *:Sortix:*:*) + echo "$UNAME_MACHINE"-unknown-sortix + exit ;; + *:Twizzler:*:*) + echo "$UNAME_MACHINE"-unknown-twizzler + exit ;; + *:Redox:*:*) + echo "$UNAME_MACHINE"-unknown-redox + exit ;; + mips:OSF1:*.*) + echo mips-dec-osf1 + exit ;; + alpha:OSF1:*:*) + case $UNAME_RELEASE in + *4.0) + UNAME_RELEASE=$(/usr/sbin/sizer -v | awk '{print $3}') + ;; + *5.*) + UNAME_RELEASE=$(/usr/sbin/sizer -v | awk '{print $4}') + ;; + esac + # According to Compaq, /usr/sbin/psrinfo has been available on + # OSF/1 and Tru64 systems produced since 1995. I hope that + # covers most systems running today. This code pipes the CPU + # types through head -n 1, so we only detect the type of CPU 0. + ALPHA_CPU_TYPE=$(/usr/sbin/psrinfo -v | sed -n -e 's/^ The alpha \(.*\) processor.*$/\1/p' | head -n 1) + case "$ALPHA_CPU_TYPE" in + "EV4 (21064)") + UNAME_MACHINE=alpha ;; + "EV4.5 (21064)") + UNAME_MACHINE=alpha ;; + "LCA4 (21066/21068)") + UNAME_MACHINE=alpha ;; + "EV5 (21164)") + UNAME_MACHINE=alphaev5 ;; + "EV5.6 (21164A)") + UNAME_MACHINE=alphaev56 ;; + "EV5.6 (21164PC)") + UNAME_MACHINE=alphapca56 ;; + "EV5.7 (21164PC)") + UNAME_MACHINE=alphapca57 ;; + "EV6 (21264)") + UNAME_MACHINE=alphaev6 ;; + "EV6.7 (21264A)") + UNAME_MACHINE=alphaev67 ;; + "EV6.8CB (21264C)") + UNAME_MACHINE=alphaev68 ;; + "EV6.8AL (21264B)") + UNAME_MACHINE=alphaev68 ;; + "EV6.8CX (21264D)") + UNAME_MACHINE=alphaev68 ;; + "EV6.9A (21264/EV69A)") + UNAME_MACHINE=alphaev69 ;; + "EV7 (21364)") + UNAME_MACHINE=alphaev7 ;; + "EV7.9 (21364A)") + UNAME_MACHINE=alphaev79 ;; + esac + # A Pn.n version is a patched version. + # A Vn.n version is a released version. + # A Tn.n version is a released field test version. + # A Xn.n version is an unreleased experimental baselevel. + # 1.2 uses "1.2" for uname -r. + echo "$UNAME_MACHINE"-dec-osf"$(echo "$UNAME_RELEASE" | sed -e 's/^[PVTX]//' | tr ABCDEFGHIJKLMNOPQRSTUVWXYZ abcdefghijklmnopqrstuvwxyz)" + # Reset EXIT trap before exiting to avoid spurious non-zero exit code. + exitcode=$? + trap '' 0 + exit $exitcode ;; + Amiga*:UNIX_System_V:4.0:*) + echo m68k-unknown-sysv4 + exit ;; + *:[Aa]miga[Oo][Ss]:*:*) + echo "$UNAME_MACHINE"-unknown-amigaos + exit ;; + *:[Mm]orph[Oo][Ss]:*:*) + echo "$UNAME_MACHINE"-unknown-morphos + exit ;; + *:OS/390:*:*) + echo i370-ibm-openedition + exit ;; + *:z/VM:*:*) + echo s390-ibm-zvmoe + exit ;; + *:OS400:*:*) + echo powerpc-ibm-os400 + exit ;; + arm:RISC*:1.[012]*:*|arm:riscix:1.[012]*:*) + echo arm-acorn-riscix"$UNAME_RELEASE" + exit ;; + arm*:riscos:*:*|arm*:RISCOS:*:*) + echo arm-unknown-riscos + exit ;; + SR2?01:HI-UX/MPP:*:* | SR8000:HI-UX/MPP:*:*) + echo hppa1.1-hitachi-hiuxmpp + exit ;; + Pyramid*:OSx*:*:* | MIS*:OSx*:*:* | MIS*:SMP_DC-OSx*:*:*) + # akee@wpdis03.wpafb.af.mil (Earle F. Ake) contributed MIS and NILE. + if test "$( (/bin/universe) 2>/dev/null)" = att ; then + echo pyramid-pyramid-sysv3 + else + echo pyramid-pyramid-bsd + fi + exit ;; + NILE*:*:*:dcosx) + echo pyramid-pyramid-svr4 + exit ;; + DRS?6000:unix:4.0:6*) + echo sparc-icl-nx6 + exit ;; + DRS?6000:UNIX_SV:4.2*:7* | DRS?6000:isis:4.2*:7*) + case $(/usr/bin/uname -p) in + sparc) echo sparc-icl-nx7; exit ;; + esac ;; + s390x:SunOS:*:*) + echo "$UNAME_MACHINE"-ibm-solaris2"$(echo "$UNAME_RELEASE" | sed -e 's/[^.]*//')" + exit ;; + sun4H:SunOS:5.*:*) + echo sparc-hal-solaris2"$(echo "$UNAME_RELEASE"|sed -e 's/[^.]*//')" + exit ;; + sun4*:SunOS:5.*:* | tadpole*:SunOS:5.*:*) + echo sparc-sun-solaris2"$(echo "$UNAME_RELEASE" | sed -e 's/[^.]*//')" + exit ;; + i86pc:AuroraUX:5.*:* | i86xen:AuroraUX:5.*:*) + echo i386-pc-auroraux"$UNAME_RELEASE" + exit ;; + i86pc:SunOS:5.*:* | i86xen:SunOS:5.*:*) + set_cc_for_build + SUN_ARCH=i386 + # If there is a compiler, see if it is configured for 64-bit objects. + # Note that the Sun cc does not turn __LP64__ into 1 like gcc does. + # This test works for both compilers. + if test "$CC_FOR_BUILD" != no_compiler_found; then + if (echo '#ifdef __amd64'; echo IS_64BIT_ARCH; echo '#endif') | \ + (CCOPTS="" $CC_FOR_BUILD -E - 2>/dev/null) | \ + grep IS_64BIT_ARCH >/dev/null + then + SUN_ARCH=x86_64 + fi + fi + echo "$SUN_ARCH"-pc-solaris2"$(echo "$UNAME_RELEASE"|sed -e 's/[^.]*//')" + exit ;; + sun4*:SunOS:6*:*) + # According to config.sub, this is the proper way to canonicalize + # SunOS6. Hard to guess exactly what SunOS6 will be like, but + # it's likely to be more like Solaris than SunOS4. + echo sparc-sun-solaris3"$(echo "$UNAME_RELEASE"|sed -e 's/[^.]*//')" + exit ;; + sun4*:SunOS:*:*) + case "$(/usr/bin/arch -k)" in + Series*|S4*) + UNAME_RELEASE=$(uname -v) + ;; + esac + # Japanese Language versions have a version number like `4.1.3-JL'. + echo sparc-sun-sunos"$(echo "$UNAME_RELEASE"|sed -e 's/-/_/')" + exit ;; + sun3*:SunOS:*:*) + echo m68k-sun-sunos"$UNAME_RELEASE" + exit ;; + sun*:*:4.2BSD:*) + UNAME_RELEASE=$( (sed 1q /etc/motd | awk '{print substr($5,1,3)}') 2>/dev/null) + test "x$UNAME_RELEASE" = x && UNAME_RELEASE=3 + case "$(/bin/arch)" in + sun3) + echo m68k-sun-sunos"$UNAME_RELEASE" + ;; + sun4) + echo sparc-sun-sunos"$UNAME_RELEASE" + ;; + esac + exit ;; + aushp:SunOS:*:*) + echo sparc-auspex-sunos"$UNAME_RELEASE" + exit ;; + # The situation for MiNT is a little confusing. The machine name + # can be virtually everything (everything which is not + # "atarist" or "atariste" at least should have a processor + # > m68000). The system name ranges from "MiNT" over "FreeMiNT" + # to the lowercase version "mint" (or "freemint"). Finally + # the system name "TOS" denotes a system which is actually not + # MiNT. But MiNT is downward compatible to TOS, so this should + # be no problem. + atarist[e]:*MiNT:*:* | atarist[e]:*mint:*:* | atarist[e]:*TOS:*:*) + echo m68k-atari-mint"$UNAME_RELEASE" + exit ;; + atari*:*MiNT:*:* | atari*:*mint:*:* | atarist[e]:*TOS:*:*) + echo m68k-atari-mint"$UNAME_RELEASE" + exit ;; + *falcon*:*MiNT:*:* | *falcon*:*mint:*:* | *falcon*:*TOS:*:*) + echo m68k-atari-mint"$UNAME_RELEASE" + exit ;; + milan*:*MiNT:*:* | milan*:*mint:*:* | *milan*:*TOS:*:*) + echo m68k-milan-mint"$UNAME_RELEASE" + exit ;; + hades*:*MiNT:*:* | hades*:*mint:*:* | *hades*:*TOS:*:*) + echo m68k-hades-mint"$UNAME_RELEASE" + exit ;; + *:*MiNT:*:* | *:*mint:*:* | *:*TOS:*:*) + echo m68k-unknown-mint"$UNAME_RELEASE" + exit ;; + m68k:machten:*:*) + echo m68k-apple-machten"$UNAME_RELEASE" + exit ;; + powerpc:machten:*:*) + echo powerpc-apple-machten"$UNAME_RELEASE" + exit ;; + RISC*:Mach:*:*) + echo mips-dec-mach_bsd4.3 + exit ;; + RISC*:ULTRIX:*:*) + echo mips-dec-ultrix"$UNAME_RELEASE" + exit ;; + VAX*:ULTRIX*:*:*) + echo vax-dec-ultrix"$UNAME_RELEASE" + exit ;; + 2020:CLIX:*:* | 2430:CLIX:*:*) + echo clipper-intergraph-clix"$UNAME_RELEASE" + exit ;; + mips:*:*:UMIPS | mips:*:*:RISCos) + set_cc_for_build + sed 's/^ //' << EOF > "$dummy.c" +#ifdef __cplusplus +#include <stdio.h> /* for printf() prototype */ + int main (int argc, char *argv[]) { +#else + int main (argc, argv) int argc; char *argv[]; { +#endif + #if defined (host_mips) && defined (MIPSEB) + #if defined (SYSTYPE_SYSV) + printf ("mips-mips-riscos%ssysv\\n", argv[1]); exit (0); + #endif + #if defined (SYSTYPE_SVR4) + printf ("mips-mips-riscos%ssvr4\\n", argv[1]); exit (0); + #endif + #if defined (SYSTYPE_BSD43) || defined(SYSTYPE_BSD) + printf ("mips-mips-riscos%sbsd\\n", argv[1]); exit (0); + #endif + #endif + exit (-1); + } +EOF + $CC_FOR_BUILD -o "$dummy" "$dummy.c" && + dummyarg=$(echo "$UNAME_RELEASE" | sed -n 's/\([0-9]*\).*/\1/p') && + SYSTEM_NAME=$("$dummy" "$dummyarg") && + { echo "$SYSTEM_NAME"; exit; } + echo mips-mips-riscos"$UNAME_RELEASE" + exit ;; + Motorola:PowerMAX_OS:*:*) + echo powerpc-motorola-powermax + exit ;; + Motorola:*:4.3:PL8-*) + echo powerpc-harris-powermax + exit ;; + Night_Hawk:*:*:PowerMAX_OS | Synergy:PowerMAX_OS:*:*) + echo powerpc-harris-powermax + exit ;; + Night_Hawk:Power_UNIX:*:*) + echo powerpc-harris-powerunix + exit ;; + m88k:CX/UX:7*:*) + echo m88k-harris-cxux7 + exit ;; + m88k:*:4*:R4*) + echo m88k-motorola-sysv4 + exit ;; + m88k:*:3*:R3*) + echo m88k-motorola-sysv3 + exit ;; + AViiON:dgux:*:*) + # DG/UX returns AViiON for all architectures + UNAME_PROCESSOR=$(/usr/bin/uname -p) + if test "$UNAME_PROCESSOR" = mc88100 || test "$UNAME_PROCESSOR" = mc88110 + then + if test "$TARGET_BINARY_INTERFACE"x = m88kdguxelfx || \ + test "$TARGET_BINARY_INTERFACE"x = x + then + echo m88k-dg-dgux"$UNAME_RELEASE" + else + echo m88k-dg-dguxbcs"$UNAME_RELEASE" + fi + else + echo i586-dg-dgux"$UNAME_RELEASE" + fi + exit ;; + M88*:DolphinOS:*:*) # DolphinOS (SVR3) + echo m88k-dolphin-sysv3 + exit ;; + M88*:*:R3*:*) + # Delta 88k system running SVR3 + echo m88k-motorola-sysv3 + exit ;; + XD88*:*:*:*) # Tektronix XD88 system running UTekV (SVR3) + echo m88k-tektronix-sysv3 + exit ;; + Tek43[0-9][0-9]:UTek:*:*) # Tektronix 4300 system running UTek (BSD) + echo m68k-tektronix-bsd + exit ;; + *:IRIX*:*:*) + echo mips-sgi-irix"$(echo "$UNAME_RELEASE"|sed -e 's/-/_/g')" + exit ;; + ????????:AIX?:[12].1:2) # AIX 2.2.1 or AIX 2.1.1 is RT/PC AIX. + echo romp-ibm-aix # uname -m gives an 8 hex-code CPU id + exit ;; # Note that: echo "'$(uname -s)'" gives 'AIX ' + i*86:AIX:*:*) + echo i386-ibm-aix + exit ;; + ia64:AIX:*:*) + if test -x /usr/bin/oslevel ; then + IBM_REV=$(/usr/bin/oslevel) + else + IBM_REV="$UNAME_VERSION.$UNAME_RELEASE" + fi + echo "$UNAME_MACHINE"-ibm-aix"$IBM_REV" + exit ;; + *:AIX:2:3) + if grep bos325 /usr/include/stdio.h >/dev/null 2>&1; then + set_cc_for_build + sed 's/^ //' << EOF > "$dummy.c" + #include <sys/systemcfg.h> + + main() + { + if (!__power_pc()) + exit(1); + puts("powerpc-ibm-aix3.2.5"); + exit(0); + } +EOF + if $CC_FOR_BUILD -o "$dummy" "$dummy.c" && SYSTEM_NAME=$("$dummy") + then + echo "$SYSTEM_NAME" + else + echo rs6000-ibm-aix3.2.5 + fi + elif grep bos324 /usr/include/stdio.h >/dev/null 2>&1; then + echo rs6000-ibm-aix3.2.4 + else + echo rs6000-ibm-aix3.2 + fi + exit ;; + *:AIX:*:[4567]) + IBM_CPU_ID=$(/usr/sbin/lsdev -C -c processor -S available | sed 1q | awk '{ print $1 }') + if /usr/sbin/lsattr -El "$IBM_CPU_ID" | grep ' POWER' >/dev/null 2>&1; then + IBM_ARCH=rs6000 + else + IBM_ARCH=powerpc + fi + if test -x /usr/bin/lslpp ; then + IBM_REV=$(/usr/bin/lslpp -Lqc bos.rte.libc | + awk -F: '{ print $3 }' | sed s/[0-9]*$/0/) + else + IBM_REV="$UNAME_VERSION.$UNAME_RELEASE" + fi + echo "$IBM_ARCH"-ibm-aix"$IBM_REV" + exit ;; + *:AIX:*:*) + echo rs6000-ibm-aix + exit ;; + ibmrt:4.4BSD:*|romp-ibm:4.4BSD:*) + echo romp-ibm-bsd4.4 + exit ;; + ibmrt:*BSD:*|romp-ibm:BSD:*) # covers RT/PC BSD and + echo romp-ibm-bsd"$UNAME_RELEASE" # 4.3 with uname added to + exit ;; # report: romp-ibm BSD 4.3 + *:BOSX:*:*) + echo rs6000-bull-bosx + exit ;; + DPX/2?00:B.O.S.:*:*) + echo m68k-bull-sysv3 + exit ;; + 9000/[34]??:4.3bsd:1.*:*) + echo m68k-hp-bsd + exit ;; + hp300:4.4BSD:*:* | 9000/[34]??:4.3bsd:2.*:*) + echo m68k-hp-bsd4.4 + exit ;; + 9000/[34678]??:HP-UX:*:*) + HPUX_REV=$(echo "$UNAME_RELEASE"|sed -e 's/[^.]*.[0B]*//') + case "$UNAME_MACHINE" in + 9000/31?) HP_ARCH=m68000 ;; + 9000/[34]??) HP_ARCH=m68k ;; + 9000/[678][0-9][0-9]) + if test -x /usr/bin/getconf; then + sc_cpu_version=$(/usr/bin/getconf SC_CPU_VERSION 2>/dev/null) + sc_kernel_bits=$(/usr/bin/getconf SC_KERNEL_BITS 2>/dev/null) + case "$sc_cpu_version" in + 523) HP_ARCH=hppa1.0 ;; # CPU_PA_RISC1_0 + 528) HP_ARCH=hppa1.1 ;; # CPU_PA_RISC1_1 + 532) # CPU_PA_RISC2_0 + case "$sc_kernel_bits" in + 32) HP_ARCH=hppa2.0n ;; + 64) HP_ARCH=hppa2.0w ;; + '') HP_ARCH=hppa2.0 ;; # HP-UX 10.20 + esac ;; + esac + fi + if test "$HP_ARCH" = ""; then + set_cc_for_build + sed 's/^ //' << EOF > "$dummy.c" + + #define _HPUX_SOURCE + #include <stdlib.h> + #include <unistd.h> + + int main () + { + #if defined(_SC_KERNEL_BITS) + long bits = sysconf(_SC_KERNEL_BITS); + #endif + long cpu = sysconf (_SC_CPU_VERSION); + + switch (cpu) + { + case CPU_PA_RISC1_0: puts ("hppa1.0"); break; + case CPU_PA_RISC1_1: puts ("hppa1.1"); break; + case CPU_PA_RISC2_0: + #if defined(_SC_KERNEL_BITS) + switch (bits) + { + case 64: puts ("hppa2.0w"); break; + case 32: puts ("hppa2.0n"); break; + default: puts ("hppa2.0"); break; + } break; + #else /* !defined(_SC_KERNEL_BITS) */ + puts ("hppa2.0"); break; + #endif + default: puts ("hppa1.0"); break; + } + exit (0); + } +EOF + (CCOPTS="" $CC_FOR_BUILD -o "$dummy" "$dummy.c" 2>/dev/null) && HP_ARCH=$("$dummy") + test -z "$HP_ARCH" && HP_ARCH=hppa + fi ;; + esac + if test "$HP_ARCH" = hppa2.0w + then + set_cc_for_build + + # hppa2.0w-hp-hpux* has a 64-bit kernel and a compiler generating + # 32-bit code. hppa64-hp-hpux* has the same kernel and a compiler + # generating 64-bit code. GNU and HP use different nomenclature: + # + # $ CC_FOR_BUILD=cc ./config.guess + # => hppa2.0w-hp-hpux11.23 + # $ CC_FOR_BUILD="cc +DA2.0w" ./config.guess + # => hppa64-hp-hpux11.23 + + if echo __LP64__ | (CCOPTS="" $CC_FOR_BUILD -E - 2>/dev/null) | + grep -q __LP64__ + then + HP_ARCH=hppa2.0w + else + HP_ARCH=hppa64 + fi + fi + echo "$HP_ARCH"-hp-hpux"$HPUX_REV" + exit ;; + ia64:HP-UX:*:*) + HPUX_REV=$(echo "$UNAME_RELEASE"|sed -e 's/[^.]*.[0B]*//') + echo ia64-hp-hpux"$HPUX_REV" + exit ;; + 3050*:HI-UX:*:*) + set_cc_for_build + sed 's/^ //' << EOF > "$dummy.c" + #include <unistd.h> + int + main () + { + long cpu = sysconf (_SC_CPU_VERSION); + /* The order matters, because CPU_IS_HP_MC68K erroneously returns + true for CPU_PA_RISC1_0. CPU_IS_PA_RISC returns correct + results, however. */ + if (CPU_IS_PA_RISC (cpu)) + { + switch (cpu) + { + case CPU_PA_RISC1_0: puts ("hppa1.0-hitachi-hiuxwe2"); break; + case CPU_PA_RISC1_1: puts ("hppa1.1-hitachi-hiuxwe2"); break; + case CPU_PA_RISC2_0: puts ("hppa2.0-hitachi-hiuxwe2"); break; + default: puts ("hppa-hitachi-hiuxwe2"); break; + } + } + else if (CPU_IS_HP_MC68K (cpu)) + puts ("m68k-hitachi-hiuxwe2"); + else puts ("unknown-hitachi-hiuxwe2"); + exit (0); + } +EOF + $CC_FOR_BUILD -o "$dummy" "$dummy.c" && SYSTEM_NAME=$("$dummy") && + { echo "$SYSTEM_NAME"; exit; } + echo unknown-hitachi-hiuxwe2 + exit ;; + 9000/7??:4.3bsd:*:* | 9000/8?[79]:4.3bsd:*:*) + echo hppa1.1-hp-bsd + exit ;; + 9000/8??:4.3bsd:*:*) + echo hppa1.0-hp-bsd + exit ;; + *9??*:MPE/iX:*:* | *3000*:MPE/iX:*:*) + echo hppa1.0-hp-mpeix + exit ;; + hp7??:OSF1:*:* | hp8?[79]:OSF1:*:*) + echo hppa1.1-hp-osf + exit ;; + hp8??:OSF1:*:*) + echo hppa1.0-hp-osf + exit ;; + i*86:OSF1:*:*) + if test -x /usr/sbin/sysversion ; then + echo "$UNAME_MACHINE"-unknown-osf1mk + else + echo "$UNAME_MACHINE"-unknown-osf1 + fi + exit ;; + parisc*:Lites*:*:*) + echo hppa1.1-hp-lites + exit ;; + C1*:ConvexOS:*:* | convex:ConvexOS:C1*:*) + echo c1-convex-bsd + exit ;; + C2*:ConvexOS:*:* | convex:ConvexOS:C2*:*) + if getsysinfo -f scalar_acc + then echo c32-convex-bsd + else echo c2-convex-bsd + fi + exit ;; + C34*:ConvexOS:*:* | convex:ConvexOS:C34*:*) + echo c34-convex-bsd + exit ;; + C38*:ConvexOS:*:* | convex:ConvexOS:C38*:*) + echo c38-convex-bsd + exit ;; + C4*:ConvexOS:*:* | convex:ConvexOS:C4*:*) + echo c4-convex-bsd + exit ;; + CRAY*Y-MP:*:*:*) + echo ymp-cray-unicos"$UNAME_RELEASE" | sed -e 's/\.[^.]*$/.X/' + exit ;; + CRAY*[A-Z]90:*:*:*) + echo "$UNAME_MACHINE"-cray-unicos"$UNAME_RELEASE" \ + | sed -e 's/CRAY.*\([A-Z]90\)/\1/' \ + -e y/ABCDEFGHIJKLMNOPQRSTUVWXYZ/abcdefghijklmnopqrstuvwxyz/ \ + -e 's/\.[^.]*$/.X/' + exit ;; + CRAY*TS:*:*:*) + echo t90-cray-unicos"$UNAME_RELEASE" | sed -e 's/\.[^.]*$/.X/' + exit ;; + CRAY*T3E:*:*:*) + echo alphaev5-cray-unicosmk"$UNAME_RELEASE" | sed -e 's/\.[^.]*$/.X/' + exit ;; + CRAY*SV1:*:*:*) + echo sv1-cray-unicos"$UNAME_RELEASE" | sed -e 's/\.[^.]*$/.X/' + exit ;; + *:UNICOS/mp:*:*) + echo craynv-cray-unicosmp"$UNAME_RELEASE" | sed -e 's/\.[^.]*$/.X/' + exit ;; + F30[01]:UNIX_System_V:*:* | F700:UNIX_System_V:*:*) + FUJITSU_PROC=$(uname -m | tr ABCDEFGHIJKLMNOPQRSTUVWXYZ abcdefghijklmnopqrstuvwxyz) + FUJITSU_SYS=$(uname -p | tr ABCDEFGHIJKLMNOPQRSTUVWXYZ abcdefghijklmnopqrstuvwxyz | sed -e 's/\///') + FUJITSU_REL=$(echo "$UNAME_RELEASE" | sed -e 's/ /_/') + echo "${FUJITSU_PROC}-fujitsu-${FUJITSU_SYS}${FUJITSU_REL}" + exit ;; + 5000:UNIX_System_V:4.*:*) + FUJITSU_SYS=$(uname -p | tr ABCDEFGHIJKLMNOPQRSTUVWXYZ abcdefghijklmnopqrstuvwxyz | sed -e 's/\///') + FUJITSU_REL=$(echo "$UNAME_RELEASE" | tr ABCDEFGHIJKLMNOPQRSTUVWXYZ abcdefghijklmnopqrstuvwxyz | sed -e 's/ /_/') + echo "sparc-fujitsu-${FUJITSU_SYS}${FUJITSU_REL}" + exit ;; + i*86:BSD/386:*:* | i*86:BSD/OS:*:* | *:Ascend\ Embedded/OS:*:*) + echo "$UNAME_MACHINE"-pc-bsdi"$UNAME_RELEASE" + exit ;; + sparc*:BSD/OS:*:*) + echo sparc-unknown-bsdi"$UNAME_RELEASE" + exit ;; + *:BSD/OS:*:*) + echo "$UNAME_MACHINE"-unknown-bsdi"$UNAME_RELEASE" + exit ;; + arm:FreeBSD:*:*) + UNAME_PROCESSOR=$(uname -p) + set_cc_for_build + if echo __ARM_PCS_VFP | $CC_FOR_BUILD -E - 2>/dev/null \ + | grep -q __ARM_PCS_VFP + then + echo "${UNAME_PROCESSOR}"-unknown-freebsd"$(echo ${UNAME_RELEASE}|sed -e 's/[-(].*//')"-gnueabi + else + echo "${UNAME_PROCESSOR}"-unknown-freebsd"$(echo ${UNAME_RELEASE}|sed -e 's/[-(].*//')"-gnueabihf + fi + exit ;; + *:FreeBSD:*:*) + UNAME_PROCESSOR=$(/usr/bin/uname -p) + case "$UNAME_PROCESSOR" in + amd64) + UNAME_PROCESSOR=x86_64 ;; + i386) + UNAME_PROCESSOR=i586 ;; + esac + echo "$UNAME_PROCESSOR"-unknown-freebsd"$(echo "$UNAME_RELEASE"|sed -e 's/[-(].*//')" + exit ;; + i*:CYGWIN*:*) + echo "$UNAME_MACHINE"-pc-cygwin + exit ;; + *:MINGW64*:*) + echo "$UNAME_MACHINE"-pc-mingw64 + exit ;; + *:MINGW*:*) + echo "$UNAME_MACHINE"-pc-mingw32 + exit ;; + *:MSYS*:*) + echo "$UNAME_MACHINE"-pc-msys + exit ;; + i*:PW*:*) + echo "$UNAME_MACHINE"-pc-pw32 + exit ;; + *:Interix*:*) + case "$UNAME_MACHINE" in + x86) + echo i586-pc-interix"$UNAME_RELEASE" + exit ;; + authenticamd | genuineintel | EM64T) + echo x86_64-unknown-interix"$UNAME_RELEASE" + exit ;; + IA64) + echo ia64-unknown-interix"$UNAME_RELEASE" + exit ;; + esac ;; + i*:UWIN*:*) + echo "$UNAME_MACHINE"-pc-uwin + exit ;; + amd64:CYGWIN*:*:* | x86_64:CYGWIN*:*:*) + echo x86_64-pc-cygwin + exit ;; + prep*:SunOS:5.*:*) + echo powerpcle-unknown-solaris2"$(echo "$UNAME_RELEASE"|sed -e 's/[^.]*//')" + exit ;; + *:GNU:*:*) + # the GNU system + echo "$(echo "$UNAME_MACHINE"|sed -e 's,[-/].*$,,')-unknown-$LIBC$(echo "$UNAME_RELEASE"|sed -e 's,/.*$,,')" + exit ;; + *:GNU/*:*:*) + # other systems with GNU libc and userland + echo "$UNAME_MACHINE-unknown-$(echo "$UNAME_SYSTEM" | sed 's,^[^/]*/,,' | tr "[:upper:]" "[:lower:]")$(echo "$UNAME_RELEASE"|sed -e 's/[-(].*//')-$LIBC" + exit ;; + *:Minix:*:*) + echo "$UNAME_MACHINE"-unknown-minix + exit ;; + aarch64:Linux:*:*) + echo "$UNAME_MACHINE"-unknown-linux-"$LIBC" + exit ;; + aarch64_be:Linux:*:*) + UNAME_MACHINE=aarch64_be + echo "$UNAME_MACHINE"-unknown-linux-"$LIBC" + exit ;; + alpha:Linux:*:*) + case $(sed -n '/^cpu model/s/^.*: \(.*\)/\1/p' /proc/cpuinfo 2>/dev/null) in + EV5) UNAME_MACHINE=alphaev5 ;; + EV56) UNAME_MACHINE=alphaev56 ;; + PCA56) UNAME_MACHINE=alphapca56 ;; + PCA57) UNAME_MACHINE=alphapca56 ;; + EV6) UNAME_MACHINE=alphaev6 ;; + EV67) UNAME_MACHINE=alphaev67 ;; + EV68*) UNAME_MACHINE=alphaev68 ;; + esac + objdump --private-headers /bin/sh | grep -q ld.so.1 + if test "$?" = 0 ; then LIBC=gnulibc1 ; fi + echo "$UNAME_MACHINE"-unknown-linux-"$LIBC" + exit ;; + arc:Linux:*:* | arceb:Linux:*:*) + echo "$UNAME_MACHINE"-unknown-linux-"$LIBC" + exit ;; + arm*:Linux:*:*) + set_cc_for_build + if echo __ARM_EABI__ | $CC_FOR_BUILD -E - 2>/dev/null \ + | grep -q __ARM_EABI__ + then + echo "$UNAME_MACHINE"-unknown-linux-"$LIBC" + else + if echo __ARM_PCS_VFP | $CC_FOR_BUILD -E - 2>/dev/null \ + | grep -q __ARM_PCS_VFP + then + echo "$UNAME_MACHINE"-unknown-linux-"$LIBC"eabi + else + echo "$UNAME_MACHINE"-unknown-linux-"$LIBC"eabihf + fi + fi + exit ;; + avr32*:Linux:*:*) + echo "$UNAME_MACHINE"-unknown-linux-"$LIBC" + exit ;; + cris:Linux:*:*) + echo "$UNAME_MACHINE"-axis-linux-"$LIBC" + exit ;; + crisv32:Linux:*:*) + echo "$UNAME_MACHINE"-axis-linux-"$LIBC" + exit ;; + e2k:Linux:*:*) + echo "$UNAME_MACHINE"-unknown-linux-"$LIBC" + exit ;; + frv:Linux:*:*) + echo "$UNAME_MACHINE"-unknown-linux-"$LIBC" + exit ;; + hexagon:Linux:*:*) + echo "$UNAME_MACHINE"-unknown-linux-"$LIBC" + exit ;; + i*86:Linux:*:*) + echo "$UNAME_MACHINE"-pc-linux-"$LIBC" + exit ;; + ia64:Linux:*:*) + echo "$UNAME_MACHINE"-unknown-linux-"$LIBC" + exit ;; + k1om:Linux:*:*) + echo "$UNAME_MACHINE"-unknown-linux-"$LIBC" + exit ;; + m32r*:Linux:*:*) + echo "$UNAME_MACHINE"-unknown-linux-"$LIBC" + exit ;; + m68*:Linux:*:*) + echo "$UNAME_MACHINE"-unknown-linux-"$LIBC" + exit ;; + mips:Linux:*:* | mips64:Linux:*:*) + set_cc_for_build + IS_GLIBC=0 + test x"${LIBC}" = xgnu && IS_GLIBC=1 + sed 's/^ //' << EOF > "$dummy.c" + #undef CPU + #undef mips + #undef mipsel + #undef mips64 + #undef mips64el + #if ${IS_GLIBC} && defined(_ABI64) + LIBCABI=gnuabi64 + #else + #if ${IS_GLIBC} && defined(_ABIN32) + LIBCABI=gnuabin32 + #else + LIBCABI=${LIBC} + #endif + #endif + + #if ${IS_GLIBC} && defined(__mips64) && defined(__mips_isa_rev) && __mips_isa_rev>=6 + CPU=mipsisa64r6 + #else + #if ${IS_GLIBC} && !defined(__mips64) && defined(__mips_isa_rev) && __mips_isa_rev>=6 + CPU=mipsisa32r6 + #else + #if defined(__mips64) + CPU=mips64 + #else + CPU=mips + #endif + #endif + #endif + + #if defined(__MIPSEL__) || defined(__MIPSEL) || defined(_MIPSEL) || defined(MIPSEL) + MIPS_ENDIAN=el + #else + #if defined(__MIPSEB__) || defined(__MIPSEB) || defined(_MIPSEB) || defined(MIPSEB) + MIPS_ENDIAN= + #else + MIPS_ENDIAN= + #endif + #endif +EOF + eval "$($CC_FOR_BUILD -E "$dummy.c" 2>/dev/null | grep '^CPU\|^MIPS_ENDIAN\|^LIBCABI')" + test "x$CPU" != x && { echo "$CPU${MIPS_ENDIAN}-unknown-linux-$LIBCABI"; exit; } + ;; + mips64el:Linux:*:*) + echo "$UNAME_MACHINE"-unknown-linux-"$LIBC" + exit ;; + openrisc*:Linux:*:*) + echo or1k-unknown-linux-"$LIBC" + exit ;; + or32:Linux:*:* | or1k*:Linux:*:*) + echo "$UNAME_MACHINE"-unknown-linux-"$LIBC" + exit ;; + padre:Linux:*:*) + echo sparc-unknown-linux-"$LIBC" + exit ;; + parisc64:Linux:*:* | hppa64:Linux:*:*) + echo hppa64-unknown-linux-"$LIBC" + exit ;; + parisc:Linux:*:* | hppa:Linux:*:*) + # Look for CPU level + case $(grep '^cpu[^a-z]*:' /proc/cpuinfo 2>/dev/null | cut -d' ' -f2) in + PA7*) echo hppa1.1-unknown-linux-"$LIBC" ;; + PA8*) echo hppa2.0-unknown-linux-"$LIBC" ;; + *) echo hppa-unknown-linux-"$LIBC" ;; + esac + exit ;; + ppc64:Linux:*:*) + echo powerpc64-unknown-linux-"$LIBC" + exit ;; + ppc:Linux:*:*) + echo powerpc-unknown-linux-"$LIBC" + exit ;; + ppc64le:Linux:*:*) + echo powerpc64le-unknown-linux-"$LIBC" + exit ;; + ppcle:Linux:*:*) + echo powerpcle-unknown-linux-"$LIBC" + exit ;; + riscv32:Linux:*:* | riscv64:Linux:*:*) + echo "$UNAME_MACHINE"-unknown-linux-"$LIBC" + exit ;; + s390:Linux:*:* | s390x:Linux:*:*) + echo "$UNAME_MACHINE"-ibm-linux-"$LIBC" + exit ;; + sh64*:Linux:*:*) + echo "$UNAME_MACHINE"-unknown-linux-"$LIBC" + exit ;; + sh*:Linux:*:*) + echo "$UNAME_MACHINE"-unknown-linux-"$LIBC" + exit ;; + sparc:Linux:*:* | sparc64:Linux:*:*) + echo "$UNAME_MACHINE"-unknown-linux-"$LIBC" + exit ;; + tile*:Linux:*:*) + echo "$UNAME_MACHINE"-unknown-linux-"$LIBC" + exit ;; + vax:Linux:*:*) + echo "$UNAME_MACHINE"-dec-linux-"$LIBC" + exit ;; + x86_64:Linux:*:*) + set_cc_for_build + LIBCABI=$LIBC + if test "$CC_FOR_BUILD" != no_compiler_found; then + if (echo '#ifdef __ILP32__'; echo IS_X32; echo '#endif') | \ + (CCOPTS="" $CC_FOR_BUILD -E - 2>/dev/null) | \ + grep IS_X32 >/dev/null + then + LIBCABI="$LIBC"x32 + fi + fi + echo "$UNAME_MACHINE"-pc-linux-"$LIBCABI" + exit ;; + xtensa*:Linux:*:*) + echo "$UNAME_MACHINE"-unknown-linux-"$LIBC" + exit ;; + i*86:DYNIX/ptx:4*:*) + # ptx 4.0 does uname -s correctly, with DYNIX/ptx in there. + # earlier versions are messed up and put the nodename in both + # sysname and nodename. + echo i386-sequent-sysv4 + exit ;; + i*86:UNIX_SV:4.2MP:2.*) + # Unixware is an offshoot of SVR4, but it has its own version + # number series starting with 2... + # I am not positive that other SVR4 systems won't match this, + # I just have to hope. -- rms. + # Use sysv4.2uw... so that sysv4* matches it. + echo "$UNAME_MACHINE"-pc-sysv4.2uw"$UNAME_VERSION" + exit ;; + i*86:OS/2:*:*) + # If we were able to find `uname', then EMX Unix compatibility + # is probably installed. + echo "$UNAME_MACHINE"-pc-os2-emx + exit ;; + i*86:XTS-300:*:STOP) + echo "$UNAME_MACHINE"-unknown-stop + exit ;; + i*86:atheos:*:*) + echo "$UNAME_MACHINE"-unknown-atheos + exit ;; + i*86:syllable:*:*) + echo "$UNAME_MACHINE"-pc-syllable + exit ;; + i*86:LynxOS:2.*:* | i*86:LynxOS:3.[01]*:* | i*86:LynxOS:4.[02]*:*) + echo i386-unknown-lynxos"$UNAME_RELEASE" + exit ;; + i*86:*DOS:*:*) + echo "$UNAME_MACHINE"-pc-msdosdjgpp + exit ;; + i*86:*:4.*:*) + UNAME_REL=$(echo "$UNAME_RELEASE" | sed 's/\/MP$//') + if grep Novell /usr/include/link.h >/dev/null 2>/dev/null; then + echo "$UNAME_MACHINE"-univel-sysv"$UNAME_REL" + else + echo "$UNAME_MACHINE"-pc-sysv"$UNAME_REL" + fi + exit ;; + i*86:*:5:[678]*) + # UnixWare 7.x, OpenUNIX and OpenServer 6. + case $(/bin/uname -X | grep "^Machine") in + *486*) UNAME_MACHINE=i486 ;; + *Pentium) UNAME_MACHINE=i586 ;; + *Pent*|*Celeron) UNAME_MACHINE=i686 ;; + esac + echo "$UNAME_MACHINE-unknown-sysv${UNAME_RELEASE}${UNAME_SYSTEM}${UNAME_VERSION}" + exit ;; + i*86:*:3.2:*) + if test -f /usr/options/cb.name; then + UNAME_REL=$(sed -n 's/.*Version //p' </usr/options/cb.name) + echo "$UNAME_MACHINE"-pc-isc"$UNAME_REL" + elif /bin/uname -X 2>/dev/null >/dev/null ; then + UNAME_REL=$( (/bin/uname -X|grep Release|sed -e 's/.*= //')) + (/bin/uname -X|grep i80486 >/dev/null) && UNAME_MACHINE=i486 + (/bin/uname -X|grep '^Machine.*Pentium' >/dev/null) \ + && UNAME_MACHINE=i586 + (/bin/uname -X|grep '^Machine.*Pent *II' >/dev/null) \ + && UNAME_MACHINE=i686 + (/bin/uname -X|grep '^Machine.*Pentium Pro' >/dev/null) \ + && UNAME_MACHINE=i686 + echo "$UNAME_MACHINE"-pc-sco"$UNAME_REL" + else + echo "$UNAME_MACHINE"-pc-sysv32 + fi + exit ;; + pc:*:*:*) + # Left here for compatibility: + # uname -m prints for DJGPP always 'pc', but it prints nothing about + # the processor, so we play safe by assuming i586. + # Note: whatever this is, it MUST be the same as what config.sub + # prints for the "djgpp" host, or else GDB configure will decide that + # this is a cross-build. + echo i586-pc-msdosdjgpp + exit ;; + Intel:Mach:3*:*) + echo i386-pc-mach3 + exit ;; + paragon:*:*:*) + echo i860-intel-osf1 + exit ;; + i860:*:4.*:*) # i860-SVR4 + if grep Stardent /usr/include/sys/uadmin.h >/dev/null 2>&1 ; then + echo i860-stardent-sysv"$UNAME_RELEASE" # Stardent Vistra i860-SVR4 + else # Add other i860-SVR4 vendors below as they are discovered. + echo i860-unknown-sysv"$UNAME_RELEASE" # Unknown i860-SVR4 + fi + exit ;; + mini*:CTIX:SYS*5:*) + # "miniframe" + echo m68010-convergent-sysv + exit ;; + mc68k:UNIX:SYSTEM5:3.51m) + echo m68k-convergent-sysv + exit ;; + M680?0:D-NIX:5.3:*) + echo m68k-diab-dnix + exit ;; + M68*:*:R3V[5678]*:*) + test -r /sysV68 && { echo 'm68k-motorola-sysv'; exit; } ;; + 3[345]??:*:4.0:3.0 | 3[34]??A:*:4.0:3.0 | 3[34]??,*:*:4.0:3.0 | 3[34]??/*:*:4.0:3.0 | 4400:*:4.0:3.0 | 4850:*:4.0:3.0 | SKA40:*:4.0:3.0 | SDS2:*:4.0:3.0 | SHG2:*:4.0:3.0 | S7501*:*:4.0:3.0) + OS_REL='' + test -r /etc/.relid \ + && OS_REL=.$(sed -n 's/[^ ]* [^ ]* \([0-9][0-9]\).*/\1/p' < /etc/.relid) + /bin/uname -p 2>/dev/null | grep 86 >/dev/null \ + && { echo i486-ncr-sysv4.3"$OS_REL"; exit; } + /bin/uname -p 2>/dev/null | /bin/grep entium >/dev/null \ + && { echo i586-ncr-sysv4.3"$OS_REL"; exit; } ;; + 3[34]??:*:4.0:* | 3[34]??,*:*:4.0:*) + /bin/uname -p 2>/dev/null | grep 86 >/dev/null \ + && { echo i486-ncr-sysv4; exit; } ;; + NCR*:*:4.2:* | MPRAS*:*:4.2:*) + OS_REL='.3' + test -r /etc/.relid \ + && OS_REL=.$(sed -n 's/[^ ]* [^ ]* \([0-9][0-9]\).*/\1/p' < /etc/.relid) + /bin/uname -p 2>/dev/null | grep 86 >/dev/null \ + && { echo i486-ncr-sysv4.3"$OS_REL"; exit; } + /bin/uname -p 2>/dev/null | /bin/grep entium >/dev/null \ + && { echo i586-ncr-sysv4.3"$OS_REL"; exit; } + /bin/uname -p 2>/dev/null | /bin/grep pteron >/dev/null \ + && { echo i586-ncr-sysv4.3"$OS_REL"; exit; } ;; + m68*:LynxOS:2.*:* | m68*:LynxOS:3.0*:*) + echo m68k-unknown-lynxos"$UNAME_RELEASE" + exit ;; + mc68030:UNIX_System_V:4.*:*) + echo m68k-atari-sysv4 + exit ;; + TSUNAMI:LynxOS:2.*:*) + echo sparc-unknown-lynxos"$UNAME_RELEASE" + exit ;; + rs6000:LynxOS:2.*:*) + echo rs6000-unknown-lynxos"$UNAME_RELEASE" + exit ;; + PowerPC:LynxOS:2.*:* | PowerPC:LynxOS:3.[01]*:* | PowerPC:LynxOS:4.[02]*:*) + echo powerpc-unknown-lynxos"$UNAME_RELEASE" + exit ;; + SM[BE]S:UNIX_SV:*:*) + echo mips-dde-sysv"$UNAME_RELEASE" + exit ;; + RM*:ReliantUNIX-*:*:*) + echo mips-sni-sysv4 + exit ;; + RM*:SINIX-*:*:*) + echo mips-sni-sysv4 + exit ;; + *:SINIX-*:*:*) + if uname -p 2>/dev/null >/dev/null ; then + UNAME_MACHINE=$( (uname -p) 2>/dev/null) + echo "$UNAME_MACHINE"-sni-sysv4 + else + echo ns32k-sni-sysv + fi + exit ;; + PENTIUM:*:4.0*:*) # Unisys `ClearPath HMP IX 4000' SVR4/MP effort + # says <Richard.M.Bartel@ccMail.Census.GOV> + echo i586-unisys-sysv4 + exit ;; + *:UNIX_System_V:4*:FTX*) + # From Gerald Hewes <hewes@openmarket.com>. + # How about differentiating between stratus architectures? -djm + echo hppa1.1-stratus-sysv4 + exit ;; + *:*:*:FTX*) + # From seanf@swdc.stratus.com. + echo i860-stratus-sysv4 + exit ;; + i*86:VOS:*:*) + # From Paul.Green@stratus.com. + echo "$UNAME_MACHINE"-stratus-vos + exit ;; + *:VOS:*:*) + # From Paul.Green@stratus.com. + echo hppa1.1-stratus-vos + exit ;; + mc68*:A/UX:*:*) + echo m68k-apple-aux"$UNAME_RELEASE" + exit ;; + news*:NEWS-OS:6*:*) + echo mips-sony-newsos6 + exit ;; + R[34]000:*System_V*:*:* | R4000:UNIX_SYSV:*:* | R*000:UNIX_SV:*:*) + if test -d /usr/nec; then + echo mips-nec-sysv"$UNAME_RELEASE" + else + echo mips-unknown-sysv"$UNAME_RELEASE" + fi + exit ;; + BeBox:BeOS:*:*) # BeOS running on hardware made by Be, PPC only. + echo powerpc-be-beos + exit ;; + BeMac:BeOS:*:*) # BeOS running on Mac or Mac clone, PPC only. + echo powerpc-apple-beos + exit ;; + BePC:BeOS:*:*) # BeOS running on Intel PC compatible. + echo i586-pc-beos + exit ;; + BePC:Haiku:*:*) # Haiku running on Intel PC compatible. + echo i586-pc-haiku + exit ;; + x86_64:Haiku:*:*) + echo x86_64-unknown-haiku + exit ;; + SX-4:SUPER-UX:*:*) + echo sx4-nec-superux"$UNAME_RELEASE" + exit ;; + SX-5:SUPER-UX:*:*) + echo sx5-nec-superux"$UNAME_RELEASE" + exit ;; + SX-6:SUPER-UX:*:*) + echo sx6-nec-superux"$UNAME_RELEASE" + exit ;; + SX-7:SUPER-UX:*:*) + echo sx7-nec-superux"$UNAME_RELEASE" + exit ;; + SX-8:SUPER-UX:*:*) + echo sx8-nec-superux"$UNAME_RELEASE" + exit ;; + SX-8R:SUPER-UX:*:*) + echo sx8r-nec-superux"$UNAME_RELEASE" + exit ;; + SX-ACE:SUPER-UX:*:*) + echo sxace-nec-superux"$UNAME_RELEASE" + exit ;; + Power*:Rhapsody:*:*) + echo powerpc-apple-rhapsody"$UNAME_RELEASE" + exit ;; + *:Rhapsody:*:*) + echo "$UNAME_MACHINE"-apple-rhapsody"$UNAME_RELEASE" + exit ;; + arm64:Darwin:*:*) + echo aarch64-apple-darwin"$UNAME_RELEASE" + exit ;; + *:Darwin:*:*) + UNAME_PROCESSOR=$(uname -p) + case $UNAME_PROCESSOR in + unknown) UNAME_PROCESSOR=powerpc ;; + esac + if command -v xcode-select > /dev/null 2> /dev/null && \ + ! xcode-select --print-path > /dev/null 2> /dev/null ; then + # Avoid executing cc if there is no toolchain installed as + # cc will be a stub that puts up a graphical alert + # prompting the user to install developer tools. + CC_FOR_BUILD=no_compiler_found + else + set_cc_for_build + fi + if test "$CC_FOR_BUILD" != no_compiler_found; then + if (echo '#ifdef __LP64__'; echo IS_64BIT_ARCH; echo '#endif') | \ + (CCOPTS="" $CC_FOR_BUILD -E - 2>/dev/null) | \ + grep IS_64BIT_ARCH >/dev/null + then + case $UNAME_PROCESSOR in + i386) UNAME_PROCESSOR=x86_64 ;; + powerpc) UNAME_PROCESSOR=powerpc64 ;; + esac + fi + # On 10.4-10.6 one might compile for PowerPC via gcc -arch ppc + if (echo '#ifdef __POWERPC__'; echo IS_PPC; echo '#endif') | \ + (CCOPTS="" $CC_FOR_BUILD -E - 2>/dev/null) | \ + grep IS_PPC >/dev/null + then + UNAME_PROCESSOR=powerpc + fi + elif test "$UNAME_PROCESSOR" = i386 ; then + # uname -m returns i386 or x86_64 + UNAME_PROCESSOR=$UNAME_MACHINE + fi + echo "$UNAME_PROCESSOR"-apple-darwin"$UNAME_RELEASE" + exit ;; + *:procnto*:*:* | *:QNX:[0123456789]*:*) + UNAME_PROCESSOR=$(uname -p) + if test "$UNAME_PROCESSOR" = x86; then + UNAME_PROCESSOR=i386 + UNAME_MACHINE=pc + fi + echo "$UNAME_PROCESSOR"-"$UNAME_MACHINE"-nto-qnx"$UNAME_RELEASE" + exit ;; + *:QNX:*:4*) + echo i386-pc-qnx + exit ;; + NEO-*:NONSTOP_KERNEL:*:*) + echo neo-tandem-nsk"$UNAME_RELEASE" + exit ;; + NSE-*:NONSTOP_KERNEL:*:*) + echo nse-tandem-nsk"$UNAME_RELEASE" + exit ;; + NSR-*:NONSTOP_KERNEL:*:*) + echo nsr-tandem-nsk"$UNAME_RELEASE" + exit ;; + NSV-*:NONSTOP_KERNEL:*:*) + echo nsv-tandem-nsk"$UNAME_RELEASE" + exit ;; + NSX-*:NONSTOP_KERNEL:*:*) + echo nsx-tandem-nsk"$UNAME_RELEASE" + exit ;; + *:NonStop-UX:*:*) + echo mips-compaq-nonstopux + exit ;; + BS2000:POSIX*:*:*) + echo bs2000-siemens-sysv + exit ;; + DS/*:UNIX_System_V:*:*) + echo "$UNAME_MACHINE"-"$UNAME_SYSTEM"-"$UNAME_RELEASE" + exit ;; + *:Plan9:*:*) + # "uname -m" is not consistent, so use $cputype instead. 386 + # is converted to i386 for consistency with other x86 + # operating systems. + # shellcheck disable=SC2154 + if test "$cputype" = 386; then + UNAME_MACHINE=i386 + else + UNAME_MACHINE="$cputype" + fi + echo "$UNAME_MACHINE"-unknown-plan9 + exit ;; + *:TOPS-10:*:*) + echo pdp10-unknown-tops10 + exit ;; + *:TENEX:*:*) + echo pdp10-unknown-tenex + exit ;; + KS10:TOPS-20:*:* | KL10:TOPS-20:*:* | TYPE4:TOPS-20:*:*) + echo pdp10-dec-tops20 + exit ;; + XKL-1:TOPS-20:*:* | TYPE5:TOPS-20:*:*) + echo pdp10-xkl-tops20 + exit ;; + *:TOPS-20:*:*) + echo pdp10-unknown-tops20 + exit ;; + *:ITS:*:*) + echo pdp10-unknown-its + exit ;; + SEI:*:*:SEIUX) + echo mips-sei-seiux"$UNAME_RELEASE" + exit ;; + *:DragonFly:*:*) + echo "$UNAME_MACHINE"-unknown-dragonfly"$(echo "$UNAME_RELEASE"|sed -e 's/[-(].*//')" + exit ;; + *:*VMS:*:*) + UNAME_MACHINE=$( (uname -p) 2>/dev/null) + case "$UNAME_MACHINE" in + A*) echo alpha-dec-vms ; exit ;; + I*) echo ia64-dec-vms ; exit ;; + V*) echo vax-dec-vms ; exit ;; + esac ;; + *:XENIX:*:SysV) + echo i386-pc-xenix + exit ;; + i*86:skyos:*:*) + echo "$UNAME_MACHINE"-pc-skyos"$(echo "$UNAME_RELEASE" | sed -e 's/ .*$//')" + exit ;; + i*86:rdos:*:*) + echo "$UNAME_MACHINE"-pc-rdos + exit ;; + i*86:AROS:*:*) + echo "$UNAME_MACHINE"-pc-aros + exit ;; + x86_64:VMkernel:*:*) + echo "$UNAME_MACHINE"-unknown-esx + exit ;; + amd64:Isilon\ OneFS:*:*) + echo x86_64-unknown-onefs + exit ;; + *:Unleashed:*:*) + echo "$UNAME_MACHINE"-unknown-unleashed"$UNAME_RELEASE" + exit ;; +esac + +# No uname command or uname output not recognized. +set_cc_for_build +cat > "$dummy.c" <<EOF +#ifdef _SEQUENT_ +#include <sys/types.h> +#include <sys/utsname.h> +#endif +#if defined(ultrix) || defined(_ultrix) || defined(__ultrix) || defined(__ultrix__) +#if defined (vax) || defined (__vax) || defined (__vax__) || defined(mips) || defined(__mips) || defined(__mips__) || defined(MIPS) || defined(__MIPS__) +#include <signal.h> +#if defined(_SIZE_T_) || defined(SIGLOST) +#include <sys/utsname.h> +#endif +#endif +#endif +main () +{ +#if defined (sony) +#if defined (MIPSEB) + /* BFD wants "bsd" instead of "newsos". Perhaps BFD should be changed, + I don't know.... */ + printf ("mips-sony-bsd\n"); exit (0); +#else +#include <sys/param.h> + printf ("m68k-sony-newsos%s\n", +#ifdef NEWSOS4 + "4" +#else + "" +#endif + ); exit (0); +#endif +#endif + +#if defined (NeXT) +#if !defined (__ARCHITECTURE__) +#define __ARCHITECTURE__ "m68k" +#endif + int version; + version=$( (hostinfo | sed -n 's/.*NeXT Mach \([0-9]*\).*/\1/p') 2>/dev/null); + if (version < 4) + printf ("%s-next-nextstep%d\n", __ARCHITECTURE__, version); + else + printf ("%s-next-openstep%d\n", __ARCHITECTURE__, version); + exit (0); +#endif + +#if defined (MULTIMAX) || defined (n16) +#if defined (UMAXV) + printf ("ns32k-encore-sysv\n"); exit (0); +#else +#if defined (CMU) + printf ("ns32k-encore-mach\n"); exit (0); +#else + printf ("ns32k-encore-bsd\n"); exit (0); +#endif +#endif +#endif + +#if defined (__386BSD__) + printf ("i386-pc-bsd\n"); exit (0); +#endif + +#if defined (sequent) +#if defined (i386) + printf ("i386-sequent-dynix\n"); exit (0); +#endif +#if defined (ns32000) + printf ("ns32k-sequent-dynix\n"); exit (0); +#endif +#endif + +#if defined (_SEQUENT_) + struct utsname un; + + uname(&un); + if (strncmp(un.version, "V2", 2) == 0) { + printf ("i386-sequent-ptx2\n"); exit (0); + } + if (strncmp(un.version, "V1", 2) == 0) { /* XXX is V1 correct? */ + printf ("i386-sequent-ptx1\n"); exit (0); + } + printf ("i386-sequent-ptx\n"); exit (0); +#endif + +#if defined (vax) +#if !defined (ultrix) +#include <sys/param.h> +#if defined (BSD) +#if BSD == 43 + printf ("vax-dec-bsd4.3\n"); exit (0); +#else +#if BSD == 199006 + printf ("vax-dec-bsd4.3reno\n"); exit (0); +#else + printf ("vax-dec-bsd\n"); exit (0); +#endif +#endif +#else + printf ("vax-dec-bsd\n"); exit (0); +#endif +#else +#if defined(_SIZE_T_) || defined(SIGLOST) + struct utsname un; + uname (&un); + printf ("vax-dec-ultrix%s\n", un.release); exit (0); +#else + printf ("vax-dec-ultrix\n"); exit (0); +#endif +#endif +#endif +#if defined(ultrix) || defined(_ultrix) || defined(__ultrix) || defined(__ultrix__) +#if defined(mips) || defined(__mips) || defined(__mips__) || defined(MIPS) || defined(__MIPS__) +#if defined(_SIZE_T_) || defined(SIGLOST) + struct utsname *un; + uname (&un); + printf ("mips-dec-ultrix%s\n", un.release); exit (0); +#else + printf ("mips-dec-ultrix\n"); exit (0); +#endif +#endif +#endif + +#if defined (alliant) && defined (i860) + printf ("i860-alliant-bsd\n"); exit (0); +#endif + + exit (1); +} +EOF + +$CC_FOR_BUILD -o "$dummy" "$dummy.c" 2>/dev/null && SYSTEM_NAME=$($dummy) && + { echo "$SYSTEM_NAME"; exit; } + +# Apollos put the system type in the environment. +test -d /usr/apollo && { echo "$ISP-apollo-$SYSTYPE"; exit; } + +echo "$0: unable to guess system type" >&2 + +case "$UNAME_MACHINE:$UNAME_SYSTEM" in + mips:Linux | mips64:Linux) + # If we got here on MIPS GNU/Linux, output extra information. + cat >&2 <<EOF + +NOTE: MIPS GNU/Linux systems require a C compiler to fully recognize +the system type. Please install a C compiler and try again. +EOF + ;; +esac + +cat >&2 <<EOF + +This script (version $timestamp), has failed to recognize the +operating system you are using. If your script is old, overwrite *all* +copies of config.guess and config.sub with the latest versions from: + + https://git.savannah.gnu.org/cgit/config.git/plain/config.guess +and + https://git.savannah.gnu.org/cgit/config.git/plain/config.sub +EOF + +year=$(echo $timestamp | sed 's,-.*,,') +# shellcheck disable=SC2003 +if test "$(expr "$(date +%Y)" - "$year")" -lt 3 ; then + cat >&2 <<EOF + +If $0 has already been updated, send the following data and any +information you think might be pertinent to config-patches@gnu.org to +provide the necessary information to handle your system. + +config.guess timestamp = $timestamp + +uname -m = $( (uname -m) 2>/dev/null || echo unknown) +uname -r = $( (uname -r) 2>/dev/null || echo unknown) +uname -s = $( (uname -s) 2>/dev/null || echo unknown) +uname -v = $( (uname -v) 2>/dev/null || echo unknown) + +/usr/bin/uname -p = $( (/usr/bin/uname -p) 2>/dev/null) +/bin/uname -X = $( (/bin/uname -X) 2>/dev/null) + +hostinfo = $( (hostinfo) 2>/dev/null) +/bin/universe = $( (/bin/universe) 2>/dev/null) +/usr/bin/arch -k = $( (/usr/bin/arch -k) 2>/dev/null) +/bin/arch = $( (/bin/arch) 2>/dev/null) +/usr/bin/oslevel = $( (/usr/bin/oslevel) 2>/dev/null) +/usr/convex/getsysinfo = $( (/usr/convex/getsysinfo) 2>/dev/null) + +UNAME_MACHINE = "$UNAME_MACHINE" +UNAME_RELEASE = "$UNAME_RELEASE" +UNAME_SYSTEM = "$UNAME_SYSTEM" +UNAME_VERSION = "$UNAME_VERSION" +EOF +fi + +exit 1 + +# Local variables: +# eval: (add-hook 'before-save-hook 'time-stamp) +# time-stamp-start: "timestamp='" +# time-stamp-format: "%:y-%02m-%02d" +# time-stamp-end: "'" +# End: diff --git a/vendor/riscv/riscv-isa-sim/scripts/config.sub b/vendor/riscv/riscv-isa-sim/scripts/config.sub new file mode 100644 index 0000000000..19c9553b18 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/scripts/config.sub @@ -0,0 +1,1854 @@ +#! /bin/sh +# Configuration validation subroutine script. +# Copyright 1992-2020 Free Software Foundation, Inc. + +timestamp='2020-12-02' + +# This file is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, see <https://www.gnu.org/licenses/>. +# +# As a special exception to the GNU General Public License, if you +# distribute this file as part of a program that contains a +# configuration script generated by Autoconf, you may include it under +# the same distribution terms that you use for the rest of that +# program. This Exception is an additional permission under section 7 +# of the GNU General Public License, version 3 ("GPLv3"). + + +# Please send patches to <config-patches@gnu.org>. +# +# Configuration subroutine to validate and canonicalize a configuration type. +# Supply the specified configuration type as an argument. +# If it is invalid, we print an error message on stderr and exit with code 1. +# Otherwise, we print the canonical config type on stdout and succeed. + +# You can get the latest version of this script from: +# https://git.savannah.gnu.org/cgit/config.git/plain/config.sub + +# This file is supposed to be the same for all GNU packages +# and recognize all the CPU types, system types and aliases +# that are meaningful with *any* GNU software. +# Each package is responsible for reporting which valid configurations +# it does not support. The user should be able to distinguish +# a failure to support a valid configuration from a meaningless +# configuration. + +# The goal of this file is to map all the various variations of a given +# machine specification into a single specification in the form: +# CPU_TYPE-MANUFACTURER-OPERATING_SYSTEM +# or in some cases, the newer four-part form: +# CPU_TYPE-MANUFACTURER-KERNEL-OPERATING_SYSTEM +# It is wrong to echo any other type of specification. + +me=$(echo "$0" | sed -e 's,.*/,,') + +usage="\ +Usage: $0 [OPTION] CPU-MFR-OPSYS or ALIAS + +Canonicalize a configuration name. + +Options: + -h, --help print this help, then exit + -t, --time-stamp print date of last modification, then exit + -v, --version print version number, then exit + +Report bugs and patches to <config-patches@gnu.org>." + +version="\ +GNU config.sub ($timestamp) + +Copyright 1992-2020 Free Software Foundation, Inc. + +This is free software; see the source for copying conditions. There is NO +warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE." + +help=" +Try \`$me --help' for more information." + +# Parse command line +while test $# -gt 0 ; do + case $1 in + --time-stamp | --time* | -t ) + echo "$timestamp" ; exit ;; + --version | -v ) + echo "$version" ; exit ;; + --help | --h* | -h ) + echo "$usage"; exit ;; + -- ) # Stop option processing + shift; break ;; + - ) # Use stdin as input. + break ;; + -* ) + echo "$me: invalid option $1$help" >&2 + exit 1 ;; + + *local*) + # First pass through any local machine types. + echo "$1" + exit ;; + + * ) + break ;; + esac +done + +case $# in + 0) echo "$me: missing argument$help" >&2 + exit 1;; + 1) ;; + *) echo "$me: too many arguments$help" >&2 + exit 1;; +esac + +# Split fields of configuration type +# shellcheck disable=SC2162 +IFS="-" read field1 field2 field3 field4 <<EOF +$1 +EOF + +# Separate into logical components for further validation +case $1 in + *-*-*-*-*) + echo Invalid configuration \`"$1"\': more than four components >&2 + exit 1 + ;; + *-*-*-*) + basic_machine=$field1-$field2 + basic_os=$field3-$field4 + ;; + *-*-*) + # Ambiguous whether COMPANY is present, or skipped and KERNEL-OS is two + # parts + maybe_os=$field2-$field3 + case $maybe_os in + nto-qnx* | linux-* | uclinux-uclibc* \ + | uclinux-gnu* | kfreebsd*-gnu* | knetbsd*-gnu* | netbsd*-gnu* \ + | netbsd*-eabi* | kopensolaris*-gnu* | cloudabi*-eabi* \ + | storm-chaos* | os2-emx* | rtmk-nova*) + basic_machine=$field1 + basic_os=$maybe_os + ;; + android-linux) + basic_machine=$field1-unknown + basic_os=linux-android + ;; + *) + basic_machine=$field1-$field2 + basic_os=$field3 + ;; + esac + ;; + *-*) + # A lone config we happen to match not fitting any pattern + case $field1-$field2 in + decstation-3100) + basic_machine=mips-dec + basic_os= + ;; + *-*) + # Second component is usually, but not always the OS + case $field2 in + # Prevent following clause from handling this valid os + sun*os*) + basic_machine=$field1 + basic_os=$field2 + ;; + # Manufacturers + dec* | mips* | sequent* | encore* | pc533* | sgi* | sony* \ + | att* | 7300* | 3300* | delta* | motorola* | sun[234]* \ + | unicom* | ibm* | next | hp | isi* | apollo | altos* \ + | convergent* | ncr* | news | 32* | 3600* | 3100* \ + | hitachi* | c[123]* | convex* | sun | crds | omron* | dg \ + | ultra | tti* | harris | dolphin | highlevel | gould \ + | cbm | ns | masscomp | apple | axis | knuth | cray \ + | microblaze* | sim | cisco \ + | oki | wec | wrs | winbond) + basic_machine=$field1-$field2 + basic_os= + ;; + *) + basic_machine=$field1 + basic_os=$field2 + ;; + esac + ;; + esac + ;; + *) + # Convert single-component short-hands not valid as part of + # multi-component configurations. + case $field1 in + 386bsd) + basic_machine=i386-pc + basic_os=bsd + ;; + a29khif) + basic_machine=a29k-amd + basic_os=udi + ;; + adobe68k) + basic_machine=m68010-adobe + basic_os=scout + ;; + alliant) + basic_machine=fx80-alliant + basic_os= + ;; + altos | altos3068) + basic_machine=m68k-altos + basic_os= + ;; + am29k) + basic_machine=a29k-none + basic_os=bsd + ;; + amdahl) + basic_machine=580-amdahl + basic_os=sysv + ;; + amiga) + basic_machine=m68k-unknown + basic_os= + ;; + amigaos | amigados) + basic_machine=m68k-unknown + basic_os=amigaos + ;; + amigaunix | amix) + basic_machine=m68k-unknown + basic_os=sysv4 + ;; + apollo68) + basic_machine=m68k-apollo + basic_os=sysv + ;; + apollo68bsd) + basic_machine=m68k-apollo + basic_os=bsd + ;; + aros) + basic_machine=i386-pc + basic_os=aros + ;; + aux) + basic_machine=m68k-apple + basic_os=aux + ;; + balance) + basic_machine=ns32k-sequent + basic_os=dynix + ;; + blackfin) + basic_machine=bfin-unknown + basic_os=linux + ;; + cegcc) + basic_machine=arm-unknown + basic_os=cegcc + ;; + convex-c1) + basic_machine=c1-convex + basic_os=bsd + ;; + convex-c2) + basic_machine=c2-convex + basic_os=bsd + ;; + convex-c32) + basic_machine=c32-convex + basic_os=bsd + ;; + convex-c34) + basic_machine=c34-convex + basic_os=bsd + ;; + convex-c38) + basic_machine=c38-convex + basic_os=bsd + ;; + cray) + basic_machine=j90-cray + basic_os=unicos + ;; + crds | unos) + basic_machine=m68k-crds + basic_os= + ;; + da30) + basic_machine=m68k-da30 + basic_os= + ;; + decstation | pmax | pmin | dec3100 | decstatn) + basic_machine=mips-dec + basic_os= + ;; + delta88) + basic_machine=m88k-motorola + basic_os=sysv3 + ;; + dicos) + basic_machine=i686-pc + basic_os=dicos + ;; + djgpp) + basic_machine=i586-pc + basic_os=msdosdjgpp + ;; + ebmon29k) + basic_machine=a29k-amd + basic_os=ebmon + ;; + es1800 | OSE68k | ose68k | ose | OSE) + basic_machine=m68k-ericsson + basic_os=ose + ;; + gmicro) + basic_machine=tron-gmicro + basic_os=sysv + ;; + go32) + basic_machine=i386-pc + basic_os=go32 + ;; + h8300hms) + basic_machine=h8300-hitachi + basic_os=hms + ;; + h8300xray) + basic_machine=h8300-hitachi + basic_os=xray + ;; + h8500hms) + basic_machine=h8500-hitachi + basic_os=hms + ;; + harris) + basic_machine=m88k-harris + basic_os=sysv3 + ;; + hp300 | hp300hpux) + basic_machine=m68k-hp + basic_os=hpux + ;; + hp300bsd) + basic_machine=m68k-hp + basic_os=bsd + ;; + hppaosf) + basic_machine=hppa1.1-hp + basic_os=osf + ;; + hppro) + basic_machine=hppa1.1-hp + basic_os=proelf + ;; + i386mach) + basic_machine=i386-mach + basic_os=mach + ;; + isi68 | isi) + basic_machine=m68k-isi + basic_os=sysv + ;; + m68knommu) + basic_machine=m68k-unknown + basic_os=linux + ;; + magnum | m3230) + basic_machine=mips-mips + basic_os=sysv + ;; + merlin) + basic_machine=ns32k-utek + basic_os=sysv + ;; + mingw64) + basic_machine=x86_64-pc + basic_os=mingw64 + ;; + mingw32) + basic_machine=i686-pc + basic_os=mingw32 + ;; + mingw32ce) + basic_machine=arm-unknown + basic_os=mingw32ce + ;; + monitor) + basic_machine=m68k-rom68k + basic_os=coff + ;; + morphos) + basic_machine=powerpc-unknown + basic_os=morphos + ;; + moxiebox) + basic_machine=moxie-unknown + basic_os=moxiebox + ;; + msdos) + basic_machine=i386-pc + basic_os=msdos + ;; + msys) + basic_machine=i686-pc + basic_os=msys + ;; + mvs) + basic_machine=i370-ibm + basic_os=mvs + ;; + nacl) + basic_machine=le32-unknown + basic_os=nacl + ;; + ncr3000) + basic_machine=i486-ncr + basic_os=sysv4 + ;; + netbsd386) + basic_machine=i386-pc + basic_os=netbsd + ;; + netwinder) + basic_machine=armv4l-rebel + basic_os=linux + ;; + news | news700 | news800 | news900) + basic_machine=m68k-sony + basic_os=newsos + ;; + news1000) + basic_machine=m68030-sony + basic_os=newsos + ;; + necv70) + basic_machine=v70-nec + basic_os=sysv + ;; + nh3000) + basic_machine=m68k-harris + basic_os=cxux + ;; + nh[45]000) + basic_machine=m88k-harris + basic_os=cxux + ;; + nindy960) + basic_machine=i960-intel + basic_os=nindy + ;; + mon960) + basic_machine=i960-intel + basic_os=mon960 + ;; + nonstopux) + basic_machine=mips-compaq + basic_os=nonstopux + ;; + os400) + basic_machine=powerpc-ibm + basic_os=os400 + ;; + OSE68000 | ose68000) + basic_machine=m68000-ericsson + basic_os=ose + ;; + os68k) + basic_machine=m68k-none + basic_os=os68k + ;; + paragon) + basic_machine=i860-intel + basic_os=osf + ;; + parisc) + basic_machine=hppa-unknown + basic_os=linux + ;; + psp) + basic_machine=mipsallegrexel-sony + basic_os=psp + ;; + pw32) + basic_machine=i586-unknown + basic_os=pw32 + ;; + rdos | rdos64) + basic_machine=x86_64-pc + basic_os=rdos + ;; + rdos32) + basic_machine=i386-pc + basic_os=rdos + ;; + rom68k) + basic_machine=m68k-rom68k + basic_os=coff + ;; + sa29200) + basic_machine=a29k-amd + basic_os=udi + ;; + sei) + basic_machine=mips-sei + basic_os=seiux + ;; + sequent) + basic_machine=i386-sequent + basic_os= + ;; + sps7) + basic_machine=m68k-bull + basic_os=sysv2 + ;; + st2000) + basic_machine=m68k-tandem + basic_os= + ;; + stratus) + basic_machine=i860-stratus + basic_os=sysv4 + ;; + sun2) + basic_machine=m68000-sun + basic_os= + ;; + sun2os3) + basic_machine=m68000-sun + basic_os=sunos3 + ;; + sun2os4) + basic_machine=m68000-sun + basic_os=sunos4 + ;; + sun3) + basic_machine=m68k-sun + basic_os= + ;; + sun3os3) + basic_machine=m68k-sun + basic_os=sunos3 + ;; + sun3os4) + basic_machine=m68k-sun + basic_os=sunos4 + ;; + sun4) + basic_machine=sparc-sun + basic_os= + ;; + sun4os3) + basic_machine=sparc-sun + basic_os=sunos3 + ;; + sun4os4) + basic_machine=sparc-sun + basic_os=sunos4 + ;; + sun4sol2) + basic_machine=sparc-sun + basic_os=solaris2 + ;; + sun386 | sun386i | roadrunner) + basic_machine=i386-sun + basic_os= + ;; + sv1) + basic_machine=sv1-cray + basic_os=unicos + ;; + symmetry) + basic_machine=i386-sequent + basic_os=dynix + ;; + t3e) + basic_machine=alphaev5-cray + basic_os=unicos + ;; + t90) + basic_machine=t90-cray + basic_os=unicos + ;; + toad1) + basic_machine=pdp10-xkl + basic_os=tops20 + ;; + tpf) + basic_machine=s390x-ibm + basic_os=tpf + ;; + udi29k) + basic_machine=a29k-amd + basic_os=udi + ;; + ultra3) + basic_machine=a29k-nyu + basic_os=sym1 + ;; + v810 | necv810) + basic_machine=v810-nec + basic_os=none + ;; + vaxv) + basic_machine=vax-dec + basic_os=sysv + ;; + vms) + basic_machine=vax-dec + basic_os=vms + ;; + vsta) + basic_machine=i386-pc + basic_os=vsta + ;; + vxworks960) + basic_machine=i960-wrs + basic_os=vxworks + ;; + vxworks68) + basic_machine=m68k-wrs + basic_os=vxworks + ;; + vxworks29k) + basic_machine=a29k-wrs + basic_os=vxworks + ;; + xbox) + basic_machine=i686-pc + basic_os=mingw32 + ;; + ymp) + basic_machine=ymp-cray + basic_os=unicos + ;; + *) + basic_machine=$1 + basic_os= + ;; + esac + ;; +esac + +# Decode 1-component or ad-hoc basic machines +case $basic_machine in + # Here we handle the default manufacturer of certain CPU types. It is in + # some cases the only manufacturer, in others, it is the most popular. + w89k) + cpu=hppa1.1 + vendor=winbond + ;; + op50n) + cpu=hppa1.1 + vendor=oki + ;; + op60c) + cpu=hppa1.1 + vendor=oki + ;; + ibm*) + cpu=i370 + vendor=ibm + ;; + orion105) + cpu=clipper + vendor=highlevel + ;; + mac | mpw | mac-mpw) + cpu=m68k + vendor=apple + ;; + pmac | pmac-mpw) + cpu=powerpc + vendor=apple + ;; + + # Recognize the various machine names and aliases which stand + # for a CPU type and a company and sometimes even an OS. + 3b1 | 7300 | 7300-att | att-7300 | pc7300 | safari | unixpc) + cpu=m68000 + vendor=att + ;; + 3b*) + cpu=we32k + vendor=att + ;; + bluegene*) + cpu=powerpc + vendor=ibm + basic_os=cnk + ;; + decsystem10* | dec10*) + cpu=pdp10 + vendor=dec + basic_os=tops10 + ;; + decsystem20* | dec20*) + cpu=pdp10 + vendor=dec + basic_os=tops20 + ;; + delta | 3300 | motorola-3300 | motorola-delta \ + | 3300-motorola | delta-motorola) + cpu=m68k + vendor=motorola + ;; + dpx2*) + cpu=m68k + vendor=bull + basic_os=sysv3 + ;; + encore | umax | mmax) + cpu=ns32k + vendor=encore + ;; + elxsi) + cpu=elxsi + vendor=elxsi + basic_os=${basic_os:-bsd} + ;; + fx2800) + cpu=i860 + vendor=alliant + ;; + genix) + cpu=ns32k + vendor=ns + ;; + h3050r* | hiux*) + cpu=hppa1.1 + vendor=hitachi + basic_os=hiuxwe2 + ;; + hp3k9[0-9][0-9] | hp9[0-9][0-9]) + cpu=hppa1.0 + vendor=hp + ;; + hp9k2[0-9][0-9] | hp9k31[0-9]) + cpu=m68000 + vendor=hp + ;; + hp9k3[2-9][0-9]) + cpu=m68k + vendor=hp + ;; + hp9k6[0-9][0-9] | hp6[0-9][0-9]) + cpu=hppa1.0 + vendor=hp + ;; + hp9k7[0-79][0-9] | hp7[0-79][0-9]) + cpu=hppa1.1 + vendor=hp + ;; + hp9k78[0-9] | hp78[0-9]) + # FIXME: really hppa2.0-hp + cpu=hppa1.1 + vendor=hp + ;; + hp9k8[67]1 | hp8[67]1 | hp9k80[24] | hp80[24] | hp9k8[78]9 | hp8[78]9 | hp9k893 | hp893) + # FIXME: really hppa2.0-hp + cpu=hppa1.1 + vendor=hp + ;; + hp9k8[0-9][13679] | hp8[0-9][13679]) + cpu=hppa1.1 + vendor=hp + ;; + hp9k8[0-9][0-9] | hp8[0-9][0-9]) + cpu=hppa1.0 + vendor=hp + ;; + i*86v32) + cpu=$(echo "$1" | sed -e 's/86.*/86/') + vendor=pc + basic_os=sysv32 + ;; + i*86v4*) + cpu=$(echo "$1" | sed -e 's/86.*/86/') + vendor=pc + basic_os=sysv4 + ;; + i*86v) + cpu=$(echo "$1" | sed -e 's/86.*/86/') + vendor=pc + basic_os=sysv + ;; + i*86sol2) + cpu=$(echo "$1" | sed -e 's/86.*/86/') + vendor=pc + basic_os=solaris2 + ;; + j90 | j90-cray) + cpu=j90 + vendor=cray + basic_os=${basic_os:-unicos} + ;; + iris | iris4d) + cpu=mips + vendor=sgi + case $basic_os in + irix*) + ;; + *) + basic_os=irix4 + ;; + esac + ;; + miniframe) + cpu=m68000 + vendor=convergent + ;; + *mint | mint[0-9]* | *MiNT | *MiNT[0-9]*) + cpu=m68k + vendor=atari + basic_os=mint + ;; + news-3600 | risc-news) + cpu=mips + vendor=sony + basic_os=newsos + ;; + next | m*-next) + cpu=m68k + vendor=next + case $basic_os in + openstep*) + ;; + nextstep*) + ;; + ns2*) + basic_os=nextstep2 + ;; + *) + basic_os=nextstep3 + ;; + esac + ;; + np1) + cpu=np1 + vendor=gould + ;; + op50n-* | op60c-*) + cpu=hppa1.1 + vendor=oki + basic_os=proelf + ;; + pa-hitachi) + cpu=hppa1.1 + vendor=hitachi + basic_os=hiuxwe2 + ;; + pbd) + cpu=sparc + vendor=tti + ;; + pbb) + cpu=m68k + vendor=tti + ;; + pc532) + cpu=ns32k + vendor=pc532 + ;; + pn) + cpu=pn + vendor=gould + ;; + power) + cpu=power + vendor=ibm + ;; + ps2) + cpu=i386 + vendor=ibm + ;; + rm[46]00) + cpu=mips + vendor=siemens + ;; + rtpc | rtpc-*) + cpu=romp + vendor=ibm + ;; + sde) + cpu=mipsisa32 + vendor=sde + basic_os=${basic_os:-elf} + ;; + simso-wrs) + cpu=sparclite + vendor=wrs + basic_os=vxworks + ;; + tower | tower-32) + cpu=m68k + vendor=ncr + ;; + vpp*|vx|vx-*) + cpu=f301 + vendor=fujitsu + ;; + w65) + cpu=w65 + vendor=wdc + ;; + w89k-*) + cpu=hppa1.1 + vendor=winbond + basic_os=proelf + ;; + none) + cpu=none + vendor=none + ;; + leon|leon[3-9]) + cpu=sparc + vendor=$basic_machine + ;; + leon-*|leon[3-9]-*) + cpu=sparc + vendor=$(echo "$basic_machine" | sed 's/-.*//') + ;; + + *-*) + # shellcheck disable=SC2162 + IFS="-" read cpu vendor <<EOF +$basic_machine +EOF + ;; + # We use `pc' rather than `unknown' + # because (1) that's what they normally are, and + # (2) the word "unknown" tends to confuse beginning users. + i*86 | x86_64) + cpu=$basic_machine + vendor=pc + ;; + # These rules are duplicated from below for sake of the special case above; + # i.e. things that normalized to x86 arches should also default to "pc" + pc98) + cpu=i386 + vendor=pc + ;; + x64 | amd64) + cpu=x86_64 + vendor=pc + ;; + # Recognize the basic CPU types without company name. + *) + cpu=$basic_machine + vendor=unknown + ;; +esac + +unset -v basic_machine + +# Decode basic machines in the full and proper CPU-Company form. +case $cpu-$vendor in + # Here we handle the default manufacturer of certain CPU types in canonical form. It is in + # some cases the only manufacturer, in others, it is the most popular. + craynv-unknown) + vendor=cray + basic_os=${basic_os:-unicosmp} + ;; + c90-unknown | c90-cray) + vendor=cray + basic_os=${Basic_os:-unicos} + ;; + fx80-unknown) + vendor=alliant + ;; + romp-unknown) + vendor=ibm + ;; + mmix-unknown) + vendor=knuth + ;; + microblaze-unknown | microblazeel-unknown) + vendor=xilinx + ;; + rs6000-unknown) + vendor=ibm + ;; + vax-unknown) + vendor=dec + ;; + pdp11-unknown) + vendor=dec + ;; + we32k-unknown) + vendor=att + ;; + cydra-unknown) + vendor=cydrome + ;; + i370-ibm*) + vendor=ibm + ;; + orion-unknown) + vendor=highlevel + ;; + xps-unknown | xps100-unknown) + cpu=xps100 + vendor=honeywell + ;; + + # Here we normalize CPU types with a missing or matching vendor + dpx20-unknown | dpx20-bull) + cpu=rs6000 + vendor=bull + basic_os=${basic_os:-bosx} + ;; + + # Here we normalize CPU types irrespective of the vendor + amd64-*) + cpu=x86_64 + ;; + blackfin-*) + cpu=bfin + basic_os=linux + ;; + c54x-*) + cpu=tic54x + ;; + c55x-*) + cpu=tic55x + ;; + c6x-*) + cpu=tic6x + ;; + e500v[12]-*) + cpu=powerpc + basic_os=${basic_os}"spe" + ;; + mips3*-*) + cpu=mips64 + ;; + ms1-*) + cpu=mt + ;; + m68knommu-*) + cpu=m68k + basic_os=linux + ;; + m9s12z-* | m68hcs12z-* | hcs12z-* | s12z-*) + cpu=s12z + ;; + openrisc-*) + cpu=or32 + ;; + parisc-*) + cpu=hppa + basic_os=linux + ;; + pentium-* | p5-* | k5-* | k6-* | nexgen-* | viac3-*) + cpu=i586 + ;; + pentiumpro-* | p6-* | 6x86-* | athlon-* | athalon_*-*) + cpu=i686 + ;; + pentiumii-* | pentium2-* | pentiumiii-* | pentium3-*) + cpu=i686 + ;; + pentium4-*) + cpu=i786 + ;; + pc98-*) + cpu=i386 + ;; + ppc-* | ppcbe-*) + cpu=powerpc + ;; + ppcle-* | powerpclittle-*) + cpu=powerpcle + ;; + ppc64-*) + cpu=powerpc64 + ;; + ppc64le-* | powerpc64little-*) + cpu=powerpc64le + ;; + sb1-*) + cpu=mipsisa64sb1 + ;; + sb1el-*) + cpu=mipsisa64sb1el + ;; + sh5e[lb]-*) + cpu=$(echo "$cpu" | sed 's/^\(sh.\)e\(.\)$/\1\2e/') + ;; + spur-*) + cpu=spur + ;; + strongarm-* | thumb-*) + cpu=arm + ;; + tx39-*) + cpu=mipstx39 + ;; + tx39el-*) + cpu=mipstx39el + ;; + x64-*) + cpu=x86_64 + ;; + xscale-* | xscalee[bl]-*) + cpu=$(echo "$cpu" | sed 's/^xscale/arm/') + ;; + arm64-*) + cpu=aarch64 + ;; + + # Recognize the canonical CPU Types that limit and/or modify the + # company names they are paired with. + cr16-*) + basic_os=${basic_os:-elf} + ;; + crisv32-* | etraxfs*-*) + cpu=crisv32 + vendor=axis + ;; + cris-* | etrax*-*) + cpu=cris + vendor=axis + ;; + crx-*) + basic_os=${basic_os:-elf} + ;; + neo-tandem) + cpu=neo + vendor=tandem + ;; + nse-tandem) + cpu=nse + vendor=tandem + ;; + nsr-tandem) + cpu=nsr + vendor=tandem + ;; + nsv-tandem) + cpu=nsv + vendor=tandem + ;; + nsx-tandem) + cpu=nsx + vendor=tandem + ;; + mipsallegrexel-sony) + cpu=mipsallegrexel + vendor=sony + ;; + tile*-*) + basic_os=${basic_os:-linux-gnu} + ;; + + *) + # Recognize the canonical CPU types that are allowed with any + # company name. + case $cpu in + 1750a | 580 \ + | a29k \ + | aarch64 | aarch64_be \ + | abacus \ + | alpha | alphaev[4-8] | alphaev56 | alphaev6[78] \ + | alpha64 | alpha64ev[4-8] | alpha64ev56 | alpha64ev6[78] \ + | alphapca5[67] | alpha64pca5[67] \ + | am33_2.0 \ + | amdgcn \ + | arc | arceb \ + | arm | arm[lb]e | arme[lb] | armv* \ + | avr | avr32 \ + | asmjs \ + | ba \ + | be32 | be64 \ + | bfin | bpf | bs2000 \ + | c[123]* | c30 | [cjt]90 | c4x \ + | c8051 | clipper | craynv | csky | cydra \ + | d10v | d30v | dlx | dsp16xx \ + | e2k | elxsi | epiphany \ + | f30[01] | f700 | fido | fr30 | frv | ft32 | fx80 \ + | h8300 | h8500 \ + | hppa | hppa1.[01] | hppa2.0 | hppa2.0[nw] | hppa64 \ + | hexagon \ + | i370 | i*86 | i860 | i960 | ia16 | ia64 \ + | ip2k | iq2000 \ + | k1om \ + | le32 | le64 \ + | lm32 \ + | m32c | m32r | m32rle \ + | m5200 | m68000 | m680[012346]0 | m68360 | m683?2 | m68k \ + | m6811 | m68hc11 | m6812 | m68hc12 | m68hcs12x \ + | m88110 | m88k | maxq | mb | mcore | mep | metag \ + | microblaze | microblazeel \ + | mips | mipsbe | mipseb | mipsel | mipsle \ + | mips16 \ + | mips64 | mips64eb | mips64el \ + | mips64octeon | mips64octeonel \ + | mips64orion | mips64orionel \ + | mips64r5900 | mips64r5900el \ + | mips64vr | mips64vrel \ + | mips64vr4100 | mips64vr4100el \ + | mips64vr4300 | mips64vr4300el \ + | mips64vr5000 | mips64vr5000el \ + | mips64vr5900 | mips64vr5900el \ + | mipsisa32 | mipsisa32el \ + | mipsisa32r2 | mipsisa32r2el \ + | mipsisa32r6 | mipsisa32r6el \ + | mipsisa64 | mipsisa64el \ + | mipsisa64r2 | mipsisa64r2el \ + | mipsisa64r6 | mipsisa64r6el \ + | mipsisa64sb1 | mipsisa64sb1el \ + | mipsisa64sr71k | mipsisa64sr71kel \ + | mipsr5900 | mipsr5900el \ + | mipstx39 | mipstx39el \ + | mmix \ + | mn10200 | mn10300 \ + | moxie \ + | mt \ + | msp430 \ + | nds32 | nds32le | nds32be \ + | nfp \ + | nios | nios2 | nios2eb | nios2el \ + | none | np1 | ns16k | ns32k | nvptx \ + | open8 \ + | or1k* \ + | or32 \ + | orion \ + | picochip \ + | pdp10 | pdp11 | pj | pjl | pn | power \ + | powerpc | powerpc64 | powerpc64le | powerpcle | powerpcspe \ + | pru \ + | pyramid \ + | riscv | riscv32 | riscv64 \ + | rl78 | romp | rs6000 | rx \ + | s390 | s390x \ + | score \ + | sh | shl \ + | sh[1234] | sh[24]a | sh[24]ae[lb] | sh[23]e | she[lb] | sh[lb]e \ + | sh[1234]e[lb] | sh[12345][lb]e | sh[23]ele | sh64 | sh64le \ + | sparc | sparc64 | sparc64b | sparc64v | sparc86x | sparclet \ + | sparclite \ + | sparcv8 | sparcv9 | sparcv9b | sparcv9v | sv1 | sx* \ + | spu \ + | tahoe \ + | thumbv7* \ + | tic30 | tic4x | tic54x | tic55x | tic6x | tic80 \ + | tron \ + | ubicom32 \ + | v70 | v850 | v850e | v850e1 | v850es | v850e2 | v850e2v3 \ + | vax \ + | visium \ + | w65 \ + | wasm32 | wasm64 \ + | we32k \ + | x86 | x86_64 | xc16x | xgate | xps100 \ + | xstormy16 | xtensa* \ + | ymp \ + | z8k | z80) + ;; + + *) + echo Invalid configuration \`"$1"\': machine \`"$cpu-$vendor"\' not recognized 1>&2 + exit 1 + ;; + esac + ;; +esac + +# Here we canonicalize certain aliases for manufacturers. +case $vendor in + digital*) + vendor=dec + ;; + commodore*) + vendor=cbm + ;; + *) + ;; +esac + +# Decode manufacturer-specific aliases for certain operating systems. + +if test x$basic_os != x +then + +# First recognize some ad-hoc caes, or perhaps split kernel-os, or else just +# set os. +case $basic_os in + gnu/linux*) + kernel=linux + os=$(echo $basic_os | sed -e 's|gnu/linux|gnu|') + ;; + os2-emx) + kernel=os2 + os=$(echo $basic_os | sed -e 's|os2-emx|emx|') + ;; + nto-qnx*) + kernel=nto + os=$(echo $basic_os | sed -e 's|nto-qnx|qnx|') + ;; + *-*) + # shellcheck disable=SC2162 + IFS="-" read kernel os <<EOF +$basic_os +EOF + ;; + # Default OS when just kernel was specified + nto*) + kernel=nto + os=$(echo $basic_os | sed -e 's|nto|qnx|') + ;; + linux*) + kernel=linux + os=$(echo $basic_os | sed -e 's|linux|gnu|') + ;; + *) + kernel= + os=$basic_os + ;; +esac + +# Now, normalize the OS (knowing we just have one component, it's not a kernel, +# etc.) +case $os in + # First match some system type aliases that might get confused + # with valid system types. + # solaris* is a basic system type, with this one exception. + auroraux) + os=auroraux + ;; + bluegene*) + os=cnk + ;; + solaris1 | solaris1.*) + os=$(echo $os | sed -e 's|solaris1|sunos4|') + ;; + solaris) + os=solaris2 + ;; + unixware*) + os=sysv4.2uw + ;; + # es1800 is here to avoid being matched by es* (a different OS) + es1800*) + os=ose + ;; + # Some version numbers need modification + chorusos*) + os=chorusos + ;; + isc) + os=isc2.2 + ;; + sco6) + os=sco5v6 + ;; + sco5) + os=sco3.2v5 + ;; + sco4) + os=sco3.2v4 + ;; + sco3.2.[4-9]*) + os=$(echo $os | sed -e 's/sco3.2./sco3.2v/') + ;; + sco*v* | scout) + # Don't match below + ;; + sco*) + os=sco3.2v2 + ;; + psos*) + os=psos + ;; + qnx*) + os=qnx + ;; + hiux*) + os=hiuxwe2 + ;; + lynx*178) + os=lynxos178 + ;; + lynx*5) + os=lynxos5 + ;; + lynxos*) + # don't get caught up in next wildcard + ;; + lynx*) + os=lynxos + ;; + mac[0-9]*) + os=$(echo "$os" | sed -e 's|mac|macos|') + ;; + opened*) + os=openedition + ;; + os400*) + os=os400 + ;; + sunos5*) + os=$(echo "$os" | sed -e 's|sunos5|solaris2|') + ;; + sunos6*) + os=$(echo "$os" | sed -e 's|sunos6|solaris3|') + ;; + wince*) + os=wince + ;; + utek*) + os=bsd + ;; + dynix*) + os=bsd + ;; + acis*) + os=aos + ;; + atheos*) + os=atheos + ;; + syllable*) + os=syllable + ;; + 386bsd) + os=bsd + ;; + ctix* | uts*) + os=sysv + ;; + nova*) + os=rtmk-nova + ;; + ns2) + os=nextstep2 + ;; + # Preserve the version number of sinix5. + sinix5.*) + os=$(echo $os | sed -e 's|sinix|sysv|') + ;; + sinix*) + os=sysv4 + ;; + tpf*) + os=tpf + ;; + triton*) + os=sysv3 + ;; + oss*) + os=sysv3 + ;; + svr4*) + os=sysv4 + ;; + svr3) + os=sysv3 + ;; + sysvr4) + os=sysv4 + ;; + ose*) + os=ose + ;; + *mint | mint[0-9]* | *MiNT | MiNT[0-9]*) + os=mint + ;; + dicos*) + os=dicos + ;; + pikeos*) + # Until real need of OS specific support for + # particular features comes up, bare metal + # configurations are quite functional. + case $cpu in + arm*) + os=eabi + ;; + *) + os=elf + ;; + esac + ;; + *) + # No normalization, but not necessarily accepted, that comes below. + ;; +esac + +else + +# Here we handle the default operating systems that come with various machines. +# The value should be what the vendor currently ships out the door with their +# machine or put another way, the most popular os provided with the machine. + +# Note that if you're going to try to match "-MANUFACTURER" here (say, +# "-sun"), then you have to tell the case statement up towards the top +# that MANUFACTURER isn't an operating system. Otherwise, code above +# will signal an error saying that MANUFACTURER isn't an operating +# system, and we'll never get to this point. + +kernel= +case $cpu-$vendor in + score-*) + os=elf + ;; + spu-*) + os=elf + ;; + *-acorn) + os=riscix1.2 + ;; + arm*-rebel) + kernel=linux + os=gnu + ;; + arm*-semi) + os=aout + ;; + c4x-* | tic4x-*) + os=coff + ;; + c8051-*) + os=elf + ;; + clipper-intergraph) + os=clix + ;; + hexagon-*) + os=elf + ;; + tic54x-*) + os=coff + ;; + tic55x-*) + os=coff + ;; + tic6x-*) + os=coff + ;; + # This must come before the *-dec entry. + pdp10-*) + os=tops20 + ;; + pdp11-*) + os=none + ;; + *-dec | vax-*) + os=ultrix4.2 + ;; + m68*-apollo) + os=domain + ;; + i386-sun) + os=sunos4.0.2 + ;; + m68000-sun) + os=sunos3 + ;; + m68*-cisco) + os=aout + ;; + mep-*) + os=elf + ;; + mips*-cisco) + os=elf + ;; + mips*-*) + os=elf + ;; + or32-*) + os=coff + ;; + *-tti) # must be before sparc entry or we get the wrong os. + os=sysv3 + ;; + sparc-* | *-sun) + os=sunos4.1.1 + ;; + pru-*) + os=elf + ;; + *-be) + os=beos + ;; + *-ibm) + os=aix + ;; + *-knuth) + os=mmixware + ;; + *-wec) + os=proelf + ;; + *-winbond) + os=proelf + ;; + *-oki) + os=proelf + ;; + *-hp) + os=hpux + ;; + *-hitachi) + os=hiux + ;; + i860-* | *-att | *-ncr | *-altos | *-motorola | *-convergent) + os=sysv + ;; + *-cbm) + os=amigaos + ;; + *-dg) + os=dgux + ;; + *-dolphin) + os=sysv3 + ;; + m68k-ccur) + os=rtu + ;; + m88k-omron*) + os=luna + ;; + *-next) + os=nextstep + ;; + *-sequent) + os=ptx + ;; + *-crds) + os=unos + ;; + *-ns) + os=genix + ;; + i370-*) + os=mvs + ;; + *-gould) + os=sysv + ;; + *-highlevel) + os=bsd + ;; + *-encore) + os=bsd + ;; + *-sgi) + os=irix + ;; + *-siemens) + os=sysv4 + ;; + *-masscomp) + os=rtu + ;; + f30[01]-fujitsu | f700-fujitsu) + os=uxpv + ;; + *-rom68k) + os=coff + ;; + *-*bug) + os=coff + ;; + *-apple) + os=macos + ;; + *-atari*) + os=mint + ;; + *-wrs) + os=vxworks + ;; + *) + os=none + ;; +esac + +fi + +# Now, validate our (potentially fixed-up) OS. +case $os in + # Sometimes we do "kernel-abi", so those need to count as OSes. + musl* | newlib* | uclibc*) + ;; + # Likewise for "kernel-libc" + eabi | eabihf | gnueabi | gnueabihf) + ;; + # Now accept the basic system types. + # The portable systems comes first. + # Each alternative MUST end in a * to match a version number. + gnu* | android* | bsd* | mach* | minix* | genix* | ultrix* | irix* \ + | *vms* | esix* | aix* | cnk* | sunos | sunos[34]* \ + | hpux* | unos* | osf* | luna* | dgux* | auroraux* | solaris* \ + | sym* | plan9* | psp* | sim* | xray* | os68k* | v88r* \ + | hiux* | abug | nacl* | netware* | windows* \ + | os9* | macos* | osx* | ios* \ + | mpw* | magic* | mmixware* | mon960* | lnews* \ + | amigaos* | amigados* | msdos* | newsos* | unicos* | aof* \ + | aos* | aros* | cloudabi* | sortix* | twizzler* \ + | nindy* | vxsim* | vxworks* | ebmon* | hms* | mvs* \ + | clix* | riscos* | uniplus* | iris* | isc* | rtu* | xenix* \ + | mirbsd* | netbsd* | dicos* | openedition* | ose* \ + | bitrig* | openbsd* | solidbsd* | libertybsd* | os108* \ + | ekkobsd* | freebsd* | riscix* | lynxos* | os400* \ + | bosx* | nextstep* | cxux* | aout* | elf* | oabi* \ + | ptx* | coff* | ecoff* | winnt* | domain* | vsta* \ + | udi* | lites* | ieee* | go32* | aux* | hcos* \ + | chorusrdb* | cegcc* | glidix* \ + | cygwin* | msys* | pe* | moss* | proelf* | rtems* \ + | midipix* | mingw32* | mingw64* | mint* \ + | uxpv* | beos* | mpeix* | udk* | moxiebox* \ + | interix* | uwin* | mks* | rhapsody* | darwin* \ + | openstep* | oskit* | conix* | pw32* | nonstopux* \ + | storm-chaos* | tops10* | tenex* | tops20* | its* \ + | os2* | vos* | palmos* | uclinux* | nucleus* | morphos* \ + | scout* | superux* | sysv* | rtmk* | tpf* | windiss* \ + | powermax* | dnix* | nx6 | nx7 | sei* | dragonfly* \ + | skyos* | haiku* | rdos* | toppers* | drops* | es* \ + | onefs* | tirtos* | phoenix* | fuchsia* | redox* | bme* \ + | midnightbsd* | amdhsa* | unleashed* | emscripten* | wasi* \ + | nsk* | powerunix* | genode* | zvmoe* | qnx* | emx*) + ;; + # This one is extra strict with allowed versions + sco3.2v2 | sco3.2v[4-9]* | sco5v6*) + # Don't forget version if it is 3.2v4 or newer. + ;; + none) + ;; + *) + echo Invalid configuration \`"$1"\': OS \`"$os"\' not recognized 1>&2 + exit 1 + ;; +esac + +# As a final step for OS-related things, validate the OS-kernel combination +# (given a valid OS), if there is a kernel. +case $kernel-$os in + linux-gnu* | linux-dietlibc* | linux-android* | linux-newlib* | linux-musl* | linux-uclibc* ) + ;; + uclinux-uclibc* ) + ;; + -dietlibc* | -newlib* | -musl* | -uclibc* ) + # These are just libc implementations, not actual OSes, and thus + # require a kernel. + echo "Invalid configuration \`$1': libc \`$os' needs explicit kernel." 1>&2 + exit 1 + ;; + kfreebsd*-gnu* | kopensolaris*-gnu*) + ;; + nto-qnx*) + ;; + os2-emx) + ;; + *-eabi* | *-gnueabi*) + ;; + -*) + # Blank kernel with real OS is always fine. + ;; + *-*) + echo "Invalid configuration \`$1': Kernel \`$kernel' not known to work with OS \`$os'." 1>&2 + exit 1 + ;; +esac + +# Here we handle the case where we know the os, and the CPU type, but not the +# manufacturer. We pick the logical manufacturer. +case $vendor in + unknown) + case $cpu-$os in + *-riscix*) + vendor=acorn + ;; + *-sunos*) + vendor=sun + ;; + *-cnk* | *-aix*) + vendor=ibm + ;; + *-beos*) + vendor=be + ;; + *-hpux*) + vendor=hp + ;; + *-mpeix*) + vendor=hp + ;; + *-hiux*) + vendor=hitachi + ;; + *-unos*) + vendor=crds + ;; + *-dgux*) + vendor=dg + ;; + *-luna*) + vendor=omron + ;; + *-genix*) + vendor=ns + ;; + *-clix*) + vendor=intergraph + ;; + *-mvs* | *-opened*) + vendor=ibm + ;; + *-os400*) + vendor=ibm + ;; + s390-* | s390x-*) + vendor=ibm + ;; + *-ptx*) + vendor=sequent + ;; + *-tpf*) + vendor=ibm + ;; + *-vxsim* | *-vxworks* | *-windiss*) + vendor=wrs + ;; + *-aux*) + vendor=apple + ;; + *-hms*) + vendor=hitachi + ;; + *-mpw* | *-macos*) + vendor=apple + ;; + *-*mint | *-mint[0-9]* | *-*MiNT | *-MiNT[0-9]*) + vendor=atari + ;; + *-vos*) + vendor=stratus + ;; + esac + ;; +esac + +echo "$cpu-$vendor-${kernel:+$kernel-}$os" +exit + +# Local variables: +# eval: (add-hook 'before-save-hook 'time-stamp) +# time-stamp-start: "timestamp='" +# time-stamp-format: "%:y-%02m-%02d" +# time-stamp-end: "'" +# End: diff --git a/vendor/riscv/riscv-isa-sim/scripts/install.sh b/vendor/riscv/riscv-isa-sim/scripts/install.sh new file mode 100755 index 0000000000..89fc9b098b --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/scripts/install.sh @@ -0,0 +1,238 @@ +#! /bin/sh +# +# install - install a program, script, or datafile +# This comes from X11R5. +# +# Calling this script install-sh is preferred over install.sh, to prevent +# `make' implicit rules from creating a file called install from it +# when there is no Makefile. +# +# This script is compatible with the BSD install script, but was written +# from scratch. +# + + +# set DOITPROG to echo to test this script + +# Don't use :- since 4.3BSD and earlier shells don't like it. +doit="${DOITPROG-}" + + +# put in absolute paths if you don't have them in your path; or use env. vars. + +mvprog="${MVPROG-mv}" +cpprog="${CPPROG-cp}" +chmodprog="${CHMODPROG-chmod}" +chownprog="${CHOWNPROG-chown}" +chgrpprog="${CHGRPPROG-chgrp}" +stripprog="${STRIPPROG-strip}" +rmprog="${RMPROG-rm}" +mkdirprog="${MKDIRPROG-mkdir}" + +tranformbasename="" +transform_arg="" +instcmd="$mvprog" +chmodcmd="$chmodprog 0755" +chowncmd="" +chgrpcmd="" +stripcmd="" +rmcmd="$rmprog -f" +mvcmd="$mvprog" +src="" +dst="" +dir_arg="" + +while [ x"$1" != x ]; do + case $1 in + -c) instcmd="$cpprog" + shift + continue;; + + -d) dir_arg=true + shift + continue;; + + -m) chmodcmd="$chmodprog $2" + shift + shift + continue;; + + -o) chowncmd="$chownprog $2" + shift + shift + continue;; + + -g) chgrpcmd="$chgrpprog $2" + shift + shift + continue;; + + -s) stripcmd="$stripprog" + shift + continue;; + + -t=*) transformarg=`echo $1 | sed 's/-t=//'` + shift + continue;; + + -b=*) transformbasename=`echo $1 | sed 's/-b=//'` + shift + continue;; + + *) if [ x"$src" = x ] + then + src=$1 + else + # this colon is to work around a 386BSD /bin/sh bug + : + dst=$1 + fi + shift + continue;; + esac +done + +if [ x"$src" = x ] +then + echo "install: no input file specified" + exit 1 +else + true +fi + +if [ x"$dir_arg" != x ]; then + dst=$src + src="" + + if [ -d $dst ]; then + instcmd=: + else + instcmd=mkdir + fi +else + +# Waiting for this to be detected by the "$instcmd $src $dsttmp" command +# might cause directories to be created, which would be especially bad +# if $src (and thus $dsttmp) contains '*'. + + if [ -f $src -o -d $src ] + then + true + else + echo "install: $src does not exist" + exit 1 + fi + + if [ x"$dst" = x ] + then + echo "install: no destination specified" + exit 1 + else + true + fi + +# If destination is a directory, append the input filename; if your system +# does not like double slashes in filenames, you may need to add some logic + + if [ -d $dst ] + then + dst="$dst"/`basename $src` + else + true + fi +fi + +## this sed command emulates the dirname command +dstdir=`echo $dst | sed -e 's,[^/]*$,,;s,/$,,;s,^$,.,'` + +# Make sure that the destination directory exists. +# this part is taken from Noah Friedman's mkinstalldirs script + +# Skip lots of stat calls in the usual case. +if [ ! -d "$dstdir" ]; then +defaultIFS=' +' +IFS="${IFS-${defaultIFS}}" + +oIFS="${IFS}" +# Some sh's can't handle IFS=/ for some reason. +IFS='%' +set - `echo ${dstdir} | sed -e 's@/@%@g' -e 's@^%@/@'` +IFS="${oIFS}" + +pathcomp='' + +while [ $# -ne 0 ] ; do + pathcomp="${pathcomp}${1}" + shift + + if [ ! -d "${pathcomp}" ] ; + then + $mkdirprog "${pathcomp}" + else + true + fi + + pathcomp="${pathcomp}/" +done +fi + +if [ x"$dir_arg" != x ] +then + $doit $instcmd $dst && + + if [ x"$chowncmd" != x ]; then $doit $chowncmd $dst; else true ; fi && + if [ x"$chgrpcmd" != x ]; then $doit $chgrpcmd $dst; else true ; fi && + if [ x"$stripcmd" != x ]; then $doit $stripcmd $dst; else true ; fi && + if [ x"$chmodcmd" != x ]; then $doit $chmodcmd $dst; else true ; fi +else + +# If we're going to rename the final executable, determine the name now. + + if [ x"$transformarg" = x ] + then + dstfile=`basename $dst` + else + dstfile=`basename $dst $transformbasename | + sed $transformarg`$transformbasename + fi + +# don't allow the sed command to completely eliminate the filename + + if [ x"$dstfile" = x ] + then + dstfile=`basename $dst` + else + true + fi + +# Make a temp file name in the proper directory. + + dsttmp=$dstdir/#inst.$$# + +# Move or copy the file name to the temp name + + $doit $instcmd $src $dsttmp && + + trap "rm -f ${dsttmp}" 0 && + +# and set any options; do chmod last to preserve setuid bits + +# If any of these fail, we abort the whole thing. If we want to +# ignore errors from any of these, just make sure not to ignore +# errors from the above "$doit $instcmd $src $dsttmp" command. + + if [ x"$chowncmd" != x ]; then $doit $chowncmd $dsttmp; else true;fi && + if [ x"$chgrpcmd" != x ]; then $doit $chgrpcmd $dsttmp; else true;fi && + if [ x"$stripcmd" != x ]; then $doit $stripcmd $dsttmp; else true;fi && + if [ x"$chmodcmd" != x ]; then $doit $chmodcmd $dsttmp; else true;fi && + +# Now rename the file to the real destination. + + $doit $rmcmd -f $dstdir/$dstfile && + $doit $mvcmd $dsttmp $dstdir/$dstfile + +fi && + + +exit 0 diff --git a/vendor/riscv/riscv-isa-sim/scripts/mk-install-dirs.sh b/vendor/riscv/riscv-isa-sim/scripts/mk-install-dirs.sh new file mode 100755 index 0000000000..644b5f728f --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/scripts/mk-install-dirs.sh @@ -0,0 +1,40 @@ +#! /bin/sh +# mkinstalldirs --- make directory hierarchy +# Author: Noah Friedman <friedman@prep.ai.mit.edu> +# Created: 1993-05-16 +# Public domain + +# $Id: mkinstalldirs,v 1.1 2003/09/09 22:24:03 mhampton Exp $ + +errstatus=0 + +for file +do + set fnord `echo ":$file" | sed -ne 's/^:\//#/;s/^://;s/\// /g;s/^#/\//;p'` + shift + + pathcomp= + for d + do + pathcomp="$pathcomp$d" + case "$pathcomp" in + -* ) pathcomp=./$pathcomp ;; + esac + + if test ! -d "$pathcomp"; then + echo "mkdir $pathcomp" 1>&2 + + mkdir "$pathcomp" || lasterr=$? + + if test ! -d "$pathcomp"; then + errstatus=$lasterr + fi + fi + + pathcomp="$pathcomp/" + done +done + +exit $errstatus + +# mkinstalldirs ends here diff --git a/vendor/riscv/riscv-isa-sim/scripts/vcs-version.sh b/vendor/riscv/riscv-isa-sim/scripts/vcs-version.sh new file mode 100755 index 0000000000..692c071ef7 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/scripts/vcs-version.sh @@ -0,0 +1,117 @@ +#!/usr/bin/env bash +#========================================================================= +# vcs-version.sh [options] [src-dir] +#========================================================================= +# +# -h Display this message +# -v Verbose mode +# +# This script will create a version string by querying a version control +# system. The string is appropriate for use in installations and +# distributions. Currently this script assumes we are using git as our +# version control system but it would be possible to check and see if we +# are using an alternative version control system and create a version +# string appropriately. +# +# The script uses git describe plus a few other git commands to create a +# version strings in the following format: +# +# X.Y[-Z-gN][-dirty] +# +# where X is the major release, Y is the minor release, Z is the number +# of commits since the X.Y release, N is an eight digit abbreviated SHA +# hash of the most recent commit and the dirty suffix is appended when +# the working directory used to create the installation or distribution +# is not a pristine checkout. Here are some example version strings: +# +# 0.0 : initial import +# 0.0-3-g99ef6933 : 3rd commit since initial import (N=99ef6933) +# 1.0 : release 1.0 +# 1.1-12-g3487ab12 : 12th commit since release 1.1 (N=3487ab12) +# 1.1-12-g3487ab12-dirty : 12th commit since release 1.1 (N=3487ab12) +# +# The last example is from a dirty working directory. To find the last +# release, the script looks for the last tag (does not need to be an +# annotated tag, but probably should be) which matches the format rel-*. +# If there is no such tag in the history, then the script uses 0.0 as +# the release number and counts the total number of commits since the +# original import for the commit count. +# +# If the current directory is not within the working directory, then the +# path to the source directory should be supplied on the command line. +# +# Author : Christopher Batten +# Date : August 5, 2009 + +set -e + +#------------------------------------------------------------------------- +# Command line parsing +#------------------------------------------------------------------------- + +if ( test "$1" = "-h" ); then + echo "" + sed -n '3p' $0 | sed -e 's/#//' + sed -n '5,/^$/p' $0 | sed -e 's/#//' + exit 1 +fi + +# Source directory command line option + +src_dir="." +if ( test -n "$1" ); then + src_dir="$1" +fi + +#------------------------------------------------------------------------- +# Verify source directory +#------------------------------------------------------------------------- +# If the source directory is not a git working directory output a +# question mark. A distribution will not be in a working directory, but +# the build system should be structured such that this script is not +# executed (and instead the version information should probably come +# from configure). If the user does not specify a source directory use +# the current directory. + +if !( git rev-parse --is-inside-work-tree &> /dev/null ); then + echo "?" + exit 1; +fi + +top_dir=`git rev-parse --show-cdup` +cd ./${top_dir} + +#------------------------------------------------------------------------- +# Create the version string +#------------------------------------------------------------------------- +# See if we can do a describe based on a tag and if not use a default +# release number of 0.0 so that we always get canonical version number + +if ( git describe --tags --match "rel-*" &> /dev/null ); then + ver_str=`git describe --tags --match "rel-*" | sed 's/rel-//'` +else + ver_num="0.0" + ver_commits=`git rev-list --all | wc -l | tr -d " "` + ver_sha=`git describe --tags --match "rel-*" --always` + ver_str="${ver_num}-${ver_commits}-g${ver_sha}" +fi + +# Add a dirty suffix if working directory is dirty + +if !( git diff --quiet ); then + ver_str="${ver_str}-dirty" +else + untracked=`git ls-files --directory --exclude-standard --others -t` + if ( test -n "${untracked}" ); then + ver_str="${ver_str}-dirty" + fi +fi + +# Output the final version string + +echo "${ver_str}" + +# Final exit status + +exit 0; + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f128_add.c b/vendor/riscv/riscv-isa-sim/softfloat/f128_add.c new file mode 100644 index 0000000000..6568ab6f34 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f128_add.c @@ -0,0 +1,78 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "softfloat.h" + +float128_t f128_add( float128_t a, float128_t b ) +{ + union ui128_f128 uA; + uint_fast64_t uiA64, uiA0; + bool signA; + union ui128_f128 uB; + uint_fast64_t uiB64, uiB0; + bool signB; +#if ! defined INLINE_LEVEL || (INLINE_LEVEL < 2) + float128_t + (*magsFuncPtr)( + uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast64_t, bool ); +#endif + + uA.f = a; + uiA64 = uA.ui.v64; + uiA0 = uA.ui.v0; + signA = signF128UI64( uiA64 ); + uB.f = b; + uiB64 = uB.ui.v64; + uiB0 = uB.ui.v0; + signB = signF128UI64( uiB64 ); +#if defined INLINE_LEVEL && (2 <= INLINE_LEVEL) + if ( signA == signB ) { + return softfloat_addMagsF128( uiA64, uiA0, uiB64, uiB0, signA ); + } else { + return softfloat_subMagsF128( uiA64, uiA0, uiB64, uiB0, signA ); + } +#else + magsFuncPtr = + (signA == signB) ? softfloat_addMagsF128 : softfloat_subMagsF128; + return (*magsFuncPtr)( uiA64, uiA0, uiB64, uiB0, signA ); +#endif + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f128_classify.c b/vendor/riscv/riscv-isa-sim/softfloat/f128_classify.c new file mode 100755 index 0000000000..1092a9b51f --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f128_classify.c @@ -0,0 +1,37 @@ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +uint_fast16_t f128_classify( float128_t a ) +{ + union ui128_f128 uA; + uint_fast64_t uiA64, uiA0; + + uA.f = a; + uiA64 = uA.ui.v64; + uiA0 = uA.ui.v0; + + uint_fast16_t infOrNaN = expF128UI64( uiA64 ) == 0x7FFF; + uint_fast16_t subnormalOrZero = expF128UI64( uiA64 ) == 0; + bool sign = signF128UI64( uiA64 ); + bool fracZero = fracF128UI64( uiA64 ) == 0 && uiA0 == 0; + bool isNaN = isNaNF128UI( uiA64, uiA0 ); + bool isSNaN = softfloat_isSigNaNF128UI( uiA64, uiA0 ); + + return + ( sign && infOrNaN && fracZero ) << 0 | + ( sign && !infOrNaN && !subnormalOrZero ) << 1 | + ( sign && subnormalOrZero && !fracZero ) << 2 | + ( sign && subnormalOrZero && fracZero ) << 3 | + ( !sign && infOrNaN && fracZero ) << 7 | + ( !sign && !infOrNaN && !subnormalOrZero ) << 6 | + ( !sign && subnormalOrZero && !fracZero ) << 5 | + ( !sign && subnormalOrZero && fracZero ) << 4 | + ( isNaN && isSNaN ) << 8 | + ( isNaN && !isSNaN ) << 9; +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f128_div.c b/vendor/riscv/riscv-isa-sim/softfloat/f128_div.c new file mode 100644 index 0000000000..9384e7562e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f128_div.c @@ -0,0 +1,199 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +float128_t f128_div( float128_t a, float128_t b ) +{ + union ui128_f128 uA; + uint_fast64_t uiA64, uiA0; + bool signA; + int_fast32_t expA; + struct uint128 sigA; + union ui128_f128 uB; + uint_fast64_t uiB64, uiB0; + bool signB; + int_fast32_t expB; + struct uint128 sigB; + bool signZ; + struct exp32_sig128 normExpSig; + int_fast32_t expZ; + struct uint128 rem; + uint_fast32_t recip32; + int ix; + uint_fast64_t q64; + uint_fast32_t q; + struct uint128 term; + uint_fast32_t qs[3]; + uint_fast64_t sigZExtra; + struct uint128 sigZ, uiZ; + union ui128_f128 uZ; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uA.f = a; + uiA64 = uA.ui.v64; + uiA0 = uA.ui.v0; + signA = signF128UI64( uiA64 ); + expA = expF128UI64( uiA64 ); + sigA.v64 = fracF128UI64( uiA64 ); + sigA.v0 = uiA0; + uB.f = b; + uiB64 = uB.ui.v64; + uiB0 = uB.ui.v0; + signB = signF128UI64( uiB64 ); + expB = expF128UI64( uiB64 ); + sigB.v64 = fracF128UI64( uiB64 ); + sigB.v0 = uiB0; + signZ = signA ^ signB; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( expA == 0x7FFF ) { + if ( sigA.v64 | sigA.v0 ) goto propagateNaN; + if ( expB == 0x7FFF ) { + if ( sigB.v64 | sigB.v0 ) goto propagateNaN; + goto invalid; + } + goto infinity; + } + if ( expB == 0x7FFF ) { + if ( sigB.v64 | sigB.v0 ) goto propagateNaN; + goto zero; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( ! expB ) { + if ( ! (sigB.v64 | sigB.v0) ) { + if ( ! (expA | sigA.v64 | sigA.v0) ) goto invalid; + softfloat_raiseFlags( softfloat_flag_infinite ); + goto infinity; + } + normExpSig = softfloat_normSubnormalF128Sig( sigB.v64, sigB.v0 ); + expB = normExpSig.exp; + sigB = normExpSig.sig; + } + if ( ! expA ) { + if ( ! (sigA.v64 | sigA.v0) ) goto zero; + normExpSig = softfloat_normSubnormalF128Sig( sigA.v64, sigA.v0 ); + expA = normExpSig.exp; + sigA = normExpSig.sig; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + expZ = expA - expB + 0x3FFE; + sigA.v64 |= UINT64_C( 0x0001000000000000 ); + sigB.v64 |= UINT64_C( 0x0001000000000000 ); + rem = sigA; + if ( softfloat_lt128( sigA.v64, sigA.v0, sigB.v64, sigB.v0 ) ) { + --expZ; + rem = softfloat_add128( sigA.v64, sigA.v0, sigA.v64, sigA.v0 ); + } + recip32 = softfloat_approxRecip32_1( sigB.v64>>17 ); + ix = 3; + for (;;) { + q64 = (uint_fast64_t) (uint32_t) (rem.v64>>19) * recip32; + q = (q64 + 0x80000000)>>32; + --ix; + if ( ix < 0 ) break; + rem = softfloat_shortShiftLeft128( rem.v64, rem.v0, 29 ); + term = softfloat_mul128By32( sigB.v64, sigB.v0, q ); + rem = softfloat_sub128( rem.v64, rem.v0, term.v64, term.v0 ); + if ( rem.v64 & UINT64_C( 0x8000000000000000 ) ) { + --q; + rem = softfloat_add128( rem.v64, rem.v0, sigB.v64, sigB.v0 ); + } + qs[ix] = q; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( ((q + 1) & 7) < 2 ) { + rem = softfloat_shortShiftLeft128( rem.v64, rem.v0, 29 ); + term = softfloat_mul128By32( sigB.v64, sigB.v0, q ); + rem = softfloat_sub128( rem.v64, rem.v0, term.v64, term.v0 ); + if ( rem.v64 & UINT64_C( 0x8000000000000000 ) ) { + --q; + rem = softfloat_add128( rem.v64, rem.v0, sigB.v64, sigB.v0 ); + } else if ( softfloat_le128( sigB.v64, sigB.v0, rem.v64, rem.v0 ) ) { + ++q; + rem = softfloat_sub128( rem.v64, rem.v0, sigB.v64, sigB.v0 ); + } + if ( rem.v64 | rem.v0 ) q |= 1; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + sigZExtra = (uint64_t) ((uint_fast64_t) q<<60); + term = softfloat_shortShiftLeft128( 0, qs[1], 54 ); + sigZ = + softfloat_add128( + (uint_fast64_t) qs[2]<<19, ((uint_fast64_t) qs[0]<<25) + (q>>4), + term.v64, term.v0 + ); + return + softfloat_roundPackToF128( signZ, expZ, sigZ.v64, sigZ.v0, sigZExtra ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + propagateNaN: + uiZ = softfloat_propagateNaNF128UI( uiA64, uiA0, uiB64, uiB0 ); + goto uiZ; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + invalid: + softfloat_raiseFlags( softfloat_flag_invalid ); + uiZ.v64 = defaultNaNF128UI64; + uiZ.v0 = defaultNaNF128UI0; + goto uiZ; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + infinity: + uiZ.v64 = packToF128UI64( signZ, 0x7FFF, 0 ); + goto uiZ0; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + zero: + uiZ.v64 = packToF128UI64( signZ, 0, 0 ); + uiZ0: + uiZ.v0 = 0; + uiZ: + uZ.ui = uiZ; + return uZ.f; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f128_eq.c b/vendor/riscv/riscv-isa-sim/softfloat/f128_eq.c new file mode 100644 index 0000000000..a0e1ad2868 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f128_eq.c @@ -0,0 +1,73 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +bool f128_eq( float128_t a, float128_t b ) +{ + union ui128_f128 uA; + uint_fast64_t uiA64, uiA0; + union ui128_f128 uB; + uint_fast64_t uiB64, uiB0; + + uA.f = a; + uiA64 = uA.ui.v64; + uiA0 = uA.ui.v0; + uB.f = b; + uiB64 = uB.ui.v64; + uiB0 = uB.ui.v0; + if ( isNaNF128UI( uiA64, uiA0 ) || isNaNF128UI( uiB64, uiB0 ) ) { + if ( + softfloat_isSigNaNF128UI( uiA64, uiA0 ) + || softfloat_isSigNaNF128UI( uiB64, uiB0 ) + ) { + softfloat_raiseFlags( softfloat_flag_invalid ); + } + return false; + } + return + (uiA0 == uiB0) + && ( (uiA64 == uiB64) + || (! uiA0 && ! ((uiA64 | uiB64) & UINT64_C( 0x7FFFFFFFFFFFFFFF ))) + ); + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f128_eq_signaling.c b/vendor/riscv/riscv-isa-sim/softfloat/f128_eq_signaling.c new file mode 100644 index 0000000000..bd37b979d2 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f128_eq_signaling.c @@ -0,0 +1,67 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "softfloat.h" + +bool f128_eq_signaling( float128_t a, float128_t b ) +{ + union ui128_f128 uA; + uint_fast64_t uiA64, uiA0; + union ui128_f128 uB; + uint_fast64_t uiB64, uiB0; + + uA.f = a; + uiA64 = uA.ui.v64; + uiA0 = uA.ui.v0; + uB.f = b; + uiB64 = uB.ui.v64; + uiB0 = uB.ui.v0; + if ( isNaNF128UI( uiA64, uiA0 ) || isNaNF128UI( uiB64, uiB0 ) ) { + softfloat_raiseFlags( softfloat_flag_invalid ); + return false; + } + return + (uiA0 == uiB0) + && ( (uiA64 == uiB64) + || (! uiA0 && ! ((uiA64 | uiB64) & UINT64_C( 0x7FFFFFFFFFFFFFFF ))) + ); + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f128_isSignalingNaN.c b/vendor/riscv/riscv-isa-sim/softfloat/f128_isSignalingNaN.c new file mode 100644 index 0000000000..fced58e503 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f128_isSignalingNaN.c @@ -0,0 +1,51 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +bool f128_isSignalingNaN( float128_t a ) +{ + union ui128_f128 uA; + + uA.f = a; + return softfloat_isSigNaNF128UI( uA.ui.v64, uA.ui.v0 ); + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f128_le.c b/vendor/riscv/riscv-isa-sim/softfloat/f128_le.c new file mode 100644 index 0000000000..9b0aa23445 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f128_le.c @@ -0,0 +1,72 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "softfloat.h" + +bool f128_le( float128_t a, float128_t b ) +{ + union ui128_f128 uA; + uint_fast64_t uiA64, uiA0; + union ui128_f128 uB; + uint_fast64_t uiB64, uiB0; + bool signA, signB; + + uA.f = a; + uiA64 = uA.ui.v64; + uiA0 = uA.ui.v0; + uB.f = b; + uiB64 = uB.ui.v64; + uiB0 = uB.ui.v0; + if ( isNaNF128UI( uiA64, uiA0 ) || isNaNF128UI( uiB64, uiB0 ) ) { + softfloat_raiseFlags( softfloat_flag_invalid ); + return false; + } + signA = signF128UI64( uiA64 ); + signB = signF128UI64( uiB64 ); + return + (signA != signB) + ? signA + || ! (((uiA64 | uiB64) & UINT64_C( 0x7FFFFFFFFFFFFFFF )) + | uiA0 | uiB0) + : ((uiA64 == uiB64) && (uiA0 == uiB0)) + || (signA ^ softfloat_lt128( uiA64, uiA0, uiB64, uiB0 )); + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f128_le_quiet.c b/vendor/riscv/riscv-isa-sim/softfloat/f128_le_quiet.c new file mode 100644 index 0000000000..3b44038859 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f128_le_quiet.c @@ -0,0 +1,78 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +bool f128_le_quiet( float128_t a, float128_t b ) +{ + union ui128_f128 uA; + uint_fast64_t uiA64, uiA0; + union ui128_f128 uB; + uint_fast64_t uiB64, uiB0; + bool signA, signB; + + uA.f = a; + uiA64 = uA.ui.v64; + uiA0 = uA.ui.v0; + uB.f = b; + uiB64 = uB.ui.v64; + uiB0 = uB.ui.v0; + if ( isNaNF128UI( uiA64, uiA0 ) || isNaNF128UI( uiB64, uiB0 ) ) { + if ( + softfloat_isSigNaNF128UI( uiA64, uiA0 ) + || softfloat_isSigNaNF128UI( uiB64, uiB0 ) + ) { + softfloat_raiseFlags( softfloat_flag_invalid ); + } + return false; + } + signA = signF128UI64( uiA64 ); + signB = signF128UI64( uiB64 ); + return + (signA != signB) + ? signA + || ! (((uiA64 | uiB64) & UINT64_C( 0x7FFFFFFFFFFFFFFF )) + | uiA0 | uiB0) + : ((uiA64 == uiB64) && (uiA0 == uiB0)) + || (signA ^ softfloat_lt128( uiA64, uiA0, uiB64, uiB0 )); + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f128_lt.c b/vendor/riscv/riscv-isa-sim/softfloat/f128_lt.c new file mode 100644 index 0000000000..a28f95b741 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f128_lt.c @@ -0,0 +1,72 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "softfloat.h" + +bool f128_lt( float128_t a, float128_t b ) +{ + union ui128_f128 uA; + uint_fast64_t uiA64, uiA0; + union ui128_f128 uB; + uint_fast64_t uiB64, uiB0; + bool signA, signB; + + uA.f = a; + uiA64 = uA.ui.v64; + uiA0 = uA.ui.v0; + uB.f = b; + uiB64 = uB.ui.v64; + uiB0 = uB.ui.v0; + if ( isNaNF128UI( uiA64, uiA0 ) || isNaNF128UI( uiB64, uiB0 ) ) { + softfloat_raiseFlags( softfloat_flag_invalid ); + return false; + } + signA = signF128UI64( uiA64 ); + signB = signF128UI64( uiB64 ); + return + (signA != signB) + ? signA + && (((uiA64 | uiB64) & UINT64_C( 0x7FFFFFFFFFFFFFFF )) + | uiA0 | uiB0) + : ((uiA64 != uiB64) || (uiA0 != uiB0)) + && (signA ^ softfloat_lt128( uiA64, uiA0, uiB64, uiB0 )); + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f128_lt_quiet.c b/vendor/riscv/riscv-isa-sim/softfloat/f128_lt_quiet.c new file mode 100644 index 0000000000..20146ee4ba --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f128_lt_quiet.c @@ -0,0 +1,78 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +bool f128_lt_quiet( float128_t a, float128_t b ) +{ + union ui128_f128 uA; + uint_fast64_t uiA64, uiA0; + union ui128_f128 uB; + uint_fast64_t uiB64, uiB0; + bool signA, signB; + + uA.f = a; + uiA64 = uA.ui.v64; + uiA0 = uA.ui.v0; + uB.f = b; + uiB64 = uB.ui.v64; + uiB0 = uB.ui.v0; + if ( isNaNF128UI( uiA64, uiA0 ) || isNaNF128UI( uiB64, uiB0 ) ) { + if ( + softfloat_isSigNaNF128UI( uiA64, uiA0 ) + || softfloat_isSigNaNF128UI( uiB64, uiB0 ) + ) { + softfloat_raiseFlags( softfloat_flag_invalid ); + } + return false; + } + signA = signF128UI64( uiA64 ); + signB = signF128UI64( uiB64 ); + return + (signA != signB) + ? signA + && (((uiA64 | uiB64) & UINT64_C( 0x7FFFFFFFFFFFFFFF )) + | uiA0 | uiB0) + : ((uiA64 != uiB64) || (uiA0 != uiB0)) + && (signA ^ softfloat_lt128( uiA64, uiA0, uiB64, uiB0 )); + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f128_mul.c b/vendor/riscv/riscv-isa-sim/softfloat/f128_mul.c new file mode 100644 index 0000000000..1871613954 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f128_mul.c @@ -0,0 +1,163 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +float128_t f128_mul( float128_t a, float128_t b ) +{ + union ui128_f128 uA; + uint_fast64_t uiA64, uiA0; + bool signA; + int_fast32_t expA; + struct uint128 sigA; + union ui128_f128 uB; + uint_fast64_t uiB64, uiB0; + bool signB; + int_fast32_t expB; + struct uint128 sigB; + bool signZ; + uint_fast64_t magBits; + struct exp32_sig128 normExpSig; + int_fast32_t expZ; + uint64_t sig256Z[4]; + uint_fast64_t sigZExtra; + struct uint128 sigZ; + struct uint128_extra sig128Extra; + struct uint128 uiZ; + union ui128_f128 uZ; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uA.f = a; + uiA64 = uA.ui.v64; + uiA0 = uA.ui.v0; + signA = signF128UI64( uiA64 ); + expA = expF128UI64( uiA64 ); + sigA.v64 = fracF128UI64( uiA64 ); + sigA.v0 = uiA0; + uB.f = b; + uiB64 = uB.ui.v64; + uiB0 = uB.ui.v0; + signB = signF128UI64( uiB64 ); + expB = expF128UI64( uiB64 ); + sigB.v64 = fracF128UI64( uiB64 ); + sigB.v0 = uiB0; + signZ = signA ^ signB; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( expA == 0x7FFF ) { + if ( + (sigA.v64 | sigA.v0) || ((expB == 0x7FFF) && (sigB.v64 | sigB.v0)) + ) { + goto propagateNaN; + } + magBits = expB | sigB.v64 | sigB.v0; + goto infArg; + } + if ( expB == 0x7FFF ) { + if ( sigB.v64 | sigB.v0 ) goto propagateNaN; + magBits = expA | sigA.v64 | sigA.v0; + goto infArg; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( ! expA ) { + if ( ! (sigA.v64 | sigA.v0) ) goto zero; + normExpSig = softfloat_normSubnormalF128Sig( sigA.v64, sigA.v0 ); + expA = normExpSig.exp; + sigA = normExpSig.sig; + } + if ( ! expB ) { + if ( ! (sigB.v64 | sigB.v0) ) goto zero; + normExpSig = softfloat_normSubnormalF128Sig( sigB.v64, sigB.v0 ); + expB = normExpSig.exp; + sigB = normExpSig.sig; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + expZ = expA + expB - 0x4000; + sigA.v64 |= UINT64_C( 0x0001000000000000 ); + sigB = softfloat_shortShiftLeft128( sigB.v64, sigB.v0, 16 ); + softfloat_mul128To256M( sigA.v64, sigA.v0, sigB.v64, sigB.v0, sig256Z ); + sigZExtra = sig256Z[indexWord( 4, 1 )] | (sig256Z[indexWord( 4, 0 )] != 0); + sigZ = + softfloat_add128( + sig256Z[indexWord( 4, 3 )], sig256Z[indexWord( 4, 2 )], + sigA.v64, sigA.v0 + ); + if ( UINT64_C( 0x0002000000000000 ) <= sigZ.v64 ) { + ++expZ; + sig128Extra = + softfloat_shortShiftRightJam128Extra( + sigZ.v64, sigZ.v0, sigZExtra, 1 ); + sigZ = sig128Extra.v; + sigZExtra = sig128Extra.extra; + } + return + softfloat_roundPackToF128( signZ, expZ, sigZ.v64, sigZ.v0, sigZExtra ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + propagateNaN: + uiZ = softfloat_propagateNaNF128UI( uiA64, uiA0, uiB64, uiB0 ); + goto uiZ; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + infArg: + if ( ! magBits ) { + softfloat_raiseFlags( softfloat_flag_invalid ); + uiZ.v64 = defaultNaNF128UI64; + uiZ.v0 = defaultNaNF128UI0; + goto uiZ; + } + uiZ.v64 = packToF128UI64( signZ, 0x7FFF, 0 ); + goto uiZ0; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + zero: + uiZ.v64 = packToF128UI64( signZ, 0, 0 ); + uiZ0: + uiZ.v0 = 0; + uiZ: + uZ.ui = uiZ; + return uZ.f; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f128_mulAdd.c b/vendor/riscv/riscv-isa-sim/softfloat/f128_mulAdd.c new file mode 100644 index 0000000000..b2e2142fa8 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f128_mulAdd.c @@ -0,0 +1,63 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "softfloat.h" + +float128_t f128_mulAdd( float128_t a, float128_t b, float128_t c ) +{ + union ui128_f128 uA; + uint_fast64_t uiA64, uiA0; + union ui128_f128 uB; + uint_fast64_t uiB64, uiB0; + union ui128_f128 uC; + uint_fast64_t uiC64, uiC0; + + uA.f = a; + uiA64 = uA.ui.v64; + uiA0 = uA.ui.v0; + uB.f = b; + uiB64 = uB.ui.v64; + uiB0 = uB.ui.v0; + uC.f = c; + uiC64 = uC.ui.v64; + uiC0 = uC.ui.v0; + return softfloat_mulAddF128( uiA64, uiA0, uiB64, uiB0, uiC64, uiC0, 0 ); + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f128_rem.c b/vendor/riscv/riscv-isa-sim/softfloat/f128_rem.c new file mode 100644 index 0000000000..555d71eb7a --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f128_rem.c @@ -0,0 +1,190 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +float128_t f128_rem( float128_t a, float128_t b ) +{ + union ui128_f128 uA; + uint_fast64_t uiA64, uiA0; + bool signA; + int_fast32_t expA; + struct uint128 sigA; + union ui128_f128 uB; + uint_fast64_t uiB64, uiB0; + int_fast32_t expB; + struct uint128 sigB; + struct exp32_sig128 normExpSig; + struct uint128 rem; + int_fast32_t expDiff; + uint_fast32_t q, recip32; + uint_fast64_t q64; + struct uint128 term, altRem, meanRem; + bool signRem; + struct uint128 uiZ; + union ui128_f128 uZ; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uA.f = a; + uiA64 = uA.ui.v64; + uiA0 = uA.ui.v0; + signA = signF128UI64( uiA64 ); + expA = expF128UI64( uiA64 ); + sigA.v64 = fracF128UI64( uiA64 ); + sigA.v0 = uiA0; + uB.f = b; + uiB64 = uB.ui.v64; + uiB0 = uB.ui.v0; + expB = expF128UI64( uiB64 ); + sigB.v64 = fracF128UI64( uiB64 ); + sigB.v0 = uiB0; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( expA == 0x7FFF ) { + if ( + (sigA.v64 | sigA.v0) || ((expB == 0x7FFF) && (sigB.v64 | sigB.v0)) + ) { + goto propagateNaN; + } + goto invalid; + } + if ( expB == 0x7FFF ) { + if ( sigB.v64 | sigB.v0 ) goto propagateNaN; + return a; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( ! expB ) { + if ( ! (sigB.v64 | sigB.v0) ) goto invalid; + normExpSig = softfloat_normSubnormalF128Sig( sigB.v64, sigB.v0 ); + expB = normExpSig.exp; + sigB = normExpSig.sig; + } + if ( ! expA ) { + if ( ! (sigA.v64 | sigA.v0) ) return a; + normExpSig = softfloat_normSubnormalF128Sig( sigA.v64, sigA.v0 ); + expA = normExpSig.exp; + sigA = normExpSig.sig; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + sigA.v64 |= UINT64_C( 0x0001000000000000 ); + sigB.v64 |= UINT64_C( 0x0001000000000000 ); + rem = sigA; + expDiff = expA - expB; + if ( expDiff < 1 ) { + if ( expDiff < -1 ) return a; + if ( expDiff ) { + --expB; + sigB = softfloat_add128( sigB.v64, sigB.v0, sigB.v64, sigB.v0 ); + q = 0; + } else { + q = softfloat_le128( sigB.v64, sigB.v0, rem.v64, rem.v0 ); + if ( q ) { + rem = softfloat_sub128( rem.v64, rem.v0, sigB.v64, sigB.v0 ); + } + } + } else { + recip32 = softfloat_approxRecip32_1( sigB.v64>>17 ); + expDiff -= 30; + for (;;) { + q64 = (uint_fast64_t) (uint32_t) (rem.v64>>19) * recip32; + if ( expDiff < 0 ) break; + q = (q64 + 0x80000000)>>32; + rem = softfloat_shortShiftLeft128( rem.v64, rem.v0, 29 ); + term = softfloat_mul128By32( sigB.v64, sigB.v0, q ); + rem = softfloat_sub128( rem.v64, rem.v0, term.v64, term.v0 ); + if ( rem.v64 & UINT64_C( 0x8000000000000000 ) ) { + rem = softfloat_add128( rem.v64, rem.v0, sigB.v64, sigB.v0 ); + } + expDiff -= 29; + } + /*-------------------------------------------------------------------- + | (`expDiff' cannot be less than -29 here.) + *--------------------------------------------------------------------*/ + q = (uint32_t) (q64>>32)>>(~expDiff & 31); + rem = softfloat_shortShiftLeft128( rem.v64, rem.v0, expDiff + 30 ); + term = softfloat_mul128By32( sigB.v64, sigB.v0, q ); + rem = softfloat_sub128( rem.v64, rem.v0, term.v64, term.v0 ); + if ( rem.v64 & UINT64_C( 0x8000000000000000 ) ) { + altRem = softfloat_add128( rem.v64, rem.v0, sigB.v64, sigB.v0 ); + goto selectRem; + } + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + do { + altRem = rem; + ++q; + rem = softfloat_sub128( rem.v64, rem.v0, sigB.v64, sigB.v0 ); + } while ( ! (rem.v64 & UINT64_C( 0x8000000000000000 )) ); + selectRem: + meanRem = softfloat_add128( rem.v64, rem.v0, altRem.v64, altRem.v0 ); + if ( + (meanRem.v64 & UINT64_C( 0x8000000000000000 )) + || (! (meanRem.v64 | meanRem.v0) && (q & 1)) + ) { + rem = altRem; + } + signRem = signA; + if ( rem.v64 & UINT64_C( 0x8000000000000000 ) ) { + signRem = ! signRem; + rem = softfloat_sub128( 0, 0, rem.v64, rem.v0 ); + } + return softfloat_normRoundPackToF128( signRem, expB - 1, rem.v64, rem.v0 ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + propagateNaN: + uiZ = softfloat_propagateNaNF128UI( uiA64, uiA0, uiB64, uiB0 ); + goto uiZ; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + invalid: + softfloat_raiseFlags( softfloat_flag_invalid ); + uiZ.v64 = defaultNaNF128UI64; + uiZ.v0 = defaultNaNF128UI0; + uiZ: + uZ.ui = uiZ; + return uZ.f; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f128_roundToInt.c b/vendor/riscv/riscv-isa-sim/softfloat/f128_roundToInt.c new file mode 100644 index 0000000000..0f1f07ecd3 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f128_roundToInt.c @@ -0,0 +1,160 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +float128_t + f128_roundToInt( float128_t a, uint_fast8_t roundingMode, bool exact ) +{ + union ui128_f128 uA; + uint_fast64_t uiA64, uiA0; + int_fast32_t exp; + struct uint128 uiZ; + uint_fast64_t lastBitMask, roundBitsMask; + bool roundNearEven; + union ui128_f128 uZ; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uA.f = a; + uiA64 = uA.ui.v64; + uiA0 = uA.ui.v0; + exp = expF128UI64( uiA64 ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( 0x402F <= exp ) { + /*-------------------------------------------------------------------- + *--------------------------------------------------------------------*/ + if ( 0x406F <= exp ) { + if ( (exp == 0x7FFF) && (fracF128UI64( uiA64 ) | uiA0) ) { + uiZ = softfloat_propagateNaNF128UI( uiA64, uiA0, 0, 0 ); + goto uiZ; + } + return a; + } + /*-------------------------------------------------------------------- + *--------------------------------------------------------------------*/ + lastBitMask = (uint_fast64_t) 2<<(0x406E - exp); + roundBitsMask = lastBitMask - 1; + uiZ.v64 = uiA64; + uiZ.v0 = uiA0; + roundNearEven = (roundingMode == softfloat_round_near_even); + if ( roundNearEven || (roundingMode == softfloat_round_near_maxMag) ) { + if ( exp == 0x402F ) { + if ( UINT64_C( 0x8000000000000000 ) <= uiZ.v0 ) { + ++uiZ.v64; + if ( + roundNearEven + && (uiZ.v0 == UINT64_C( 0x8000000000000000 )) + ) { + uiZ.v64 &= ~1; + } + } + } else { + uiZ = softfloat_add128( uiZ.v64, uiZ.v0, 0, lastBitMask>>1 ); + if ( roundNearEven && ! (uiZ.v0 & roundBitsMask) ) { + uiZ.v0 &= ~lastBitMask; + } + } + } else if ( + roundingMode + == (signF128UI64( uiZ.v64 ) ? softfloat_round_min + : softfloat_round_max) + ) { + uiZ = softfloat_add128( uiZ.v64, uiZ.v0, 0, roundBitsMask ); + } + uiZ.v0 &= ~roundBitsMask; + } else { + /*-------------------------------------------------------------------- + *--------------------------------------------------------------------*/ + if ( exp < 0x3FFF ) { + if ( ! ((uiA64 & UINT64_C( 0x7FFFFFFFFFFFFFFF )) | uiA0) ) { + return a; + } + if ( exact ) softfloat_exceptionFlags |= softfloat_flag_inexact; + uiZ.v64 = uiA64 & packToF128UI64( 1, 0, 0 ); + uiZ.v0 = 0; + switch ( roundingMode ) { + case softfloat_round_near_even: + if ( ! (fracF128UI64( uiA64 ) | uiA0) ) break; + case softfloat_round_near_maxMag: + if ( exp == 0x3FFE ) uiZ.v64 |= packToF128UI64( 0, 0x3FFF, 0 ); + break; + case softfloat_round_min: + if ( uiZ.v64 ) uiZ.v64 = packToF128UI64( 1, 0x3FFF, 0 ); + break; + case softfloat_round_max: + if ( ! uiZ.v64 ) uiZ.v64 = packToF128UI64( 0, 0x3FFF, 0 ); + break; + } + goto uiZ; + } + /*-------------------------------------------------------------------- + *--------------------------------------------------------------------*/ + uiZ.v64 = uiA64; + uiZ.v0 = 0; + lastBitMask = (uint_fast64_t) 1<<(0x402F - exp); + roundBitsMask = lastBitMask - 1; + if ( roundingMode == softfloat_round_near_maxMag ) { + uiZ.v64 += lastBitMask>>1; + } else if ( roundingMode == softfloat_round_near_even ) { + uiZ.v64 += lastBitMask>>1; + if ( ! ((uiZ.v64 & roundBitsMask) | uiA0) ) { + uiZ.v64 &= ~lastBitMask; + } + } else if ( + roundingMode + == (signF128UI64( uiZ.v64 ) ? softfloat_round_min + : softfloat_round_max) + ) { + uiZ.v64 = (uiZ.v64 | (uiA0 != 0)) + roundBitsMask; + } + uiZ.v64 &= ~roundBitsMask; + } + if ( exact && ((uiZ.v64 != uiA64) || (uiZ.v0 != uiA0)) ) { + softfloat_exceptionFlags |= softfloat_flag_inexact; + } + uiZ: + uZ.ui = uiZ; + return uZ.f; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f128_sqrt.c b/vendor/riscv/riscv-isa-sim/softfloat/f128_sqrt.c new file mode 100644 index 0000000000..5b99694ec4 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f128_sqrt.c @@ -0,0 +1,201 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the +University of California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +float128_t f128_sqrt( float128_t a ) +{ + union ui128_f128 uA; + uint_fast64_t uiA64, uiA0; + bool signA; + int_fast32_t expA; + struct uint128 sigA, uiZ; + struct exp32_sig128 normExpSig; + int_fast32_t expZ; + uint_fast32_t sig32A, recipSqrt32, sig32Z; + struct uint128 rem; + uint32_t qs[3]; + uint_fast32_t q; + uint_fast64_t x64, sig64Z; + struct uint128 y, term; + uint_fast64_t sigZExtra; + struct uint128 sigZ; + union ui128_f128 uZ; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uA.f = a; + uiA64 = uA.ui.v64; + uiA0 = uA.ui.v0; + signA = signF128UI64( uiA64 ); + expA = expF128UI64( uiA64 ); + sigA.v64 = fracF128UI64( uiA64 ); + sigA.v0 = uiA0; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( expA == 0x7FFF ) { + if ( sigA.v64 | sigA.v0 ) { + uiZ = softfloat_propagateNaNF128UI( uiA64, uiA0, 0, 0 ); + goto uiZ; + } + if ( ! signA ) return a; + goto invalid; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( signA ) { + if ( ! (expA | sigA.v64 | sigA.v0) ) return a; + goto invalid; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( ! expA ) { + if ( ! (sigA.v64 | sigA.v0) ) return a; + normExpSig = softfloat_normSubnormalF128Sig( sigA.v64, sigA.v0 ); + expA = normExpSig.exp; + sigA = normExpSig.sig; + } + /*------------------------------------------------------------------------ + | (`sig32Z' is guaranteed to be a lower bound on the square root of + | `sig32A', which makes `sig32Z' also a lower bound on the square root of + | `sigA'.) + *------------------------------------------------------------------------*/ + expZ = ((expA - 0x3FFF)>>1) + 0x3FFE; + expA &= 1; + sigA.v64 |= UINT64_C( 0x0001000000000000 ); + sig32A = sigA.v64>>17; + recipSqrt32 = softfloat_approxRecipSqrt32_1( expA, sig32A ); + sig32Z = ((uint_fast64_t) sig32A * recipSqrt32)>>32; + if ( expA ) { + sig32Z >>= 1; + rem = softfloat_shortShiftLeft128( sigA.v64, sigA.v0, 12 ); + } else { + rem = softfloat_shortShiftLeft128( sigA.v64, sigA.v0, 13 ); + } + qs[2] = sig32Z; + rem.v64 -= (uint_fast64_t) sig32Z * sig32Z; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + q = ((uint32_t) (rem.v64>>2) * (uint_fast64_t) recipSqrt32)>>32; + x64 = (uint_fast64_t) sig32Z<<32; + sig64Z = x64 + ((uint_fast64_t) q<<3); + y = softfloat_shortShiftLeft128( rem.v64, rem.v0, 29 ); + /*------------------------------------------------------------------------ + | (Repeating this loop is a rare occurrence.) + *------------------------------------------------------------------------*/ + for (;;) { + term = softfloat_mul64ByShifted32To128( x64 + sig64Z, q ); + rem = softfloat_sub128( y.v64, y.v0, term.v64, term.v0 ); + if ( ! (rem.v64 & UINT64_C( 0x8000000000000000 )) ) break; + --q; + sig64Z -= 1<<3; + } + qs[1] = q; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + q = ((rem.v64>>2) * recipSqrt32)>>32; + y = softfloat_shortShiftLeft128( rem.v64, rem.v0, 29 ); + sig64Z <<= 1; + /*------------------------------------------------------------------------ + | (Repeating this loop is a rare occurrence.) + *------------------------------------------------------------------------*/ + for (;;) { + term = softfloat_shortShiftLeft128( 0, sig64Z, 32 ); + term = softfloat_add128( term.v64, term.v0, 0, (uint_fast64_t) q<<6 ); + term = softfloat_mul128By32( term.v64, term.v0, q ); + rem = softfloat_sub128( y.v64, y.v0, term.v64, term.v0 ); + if ( ! (rem.v64 & UINT64_C( 0x8000000000000000 )) ) break; + --q; + } + qs[0] = q; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + q = (((rem.v64>>2) * recipSqrt32)>>32) + 2; + sigZExtra = (uint64_t) ((uint_fast64_t) q<<59); + term = softfloat_shortShiftLeft128( 0, qs[1], 53 ); + sigZ = + softfloat_add128( + (uint_fast64_t) qs[2]<<18, ((uint_fast64_t) qs[0]<<24) + (q>>5), + term.v64, term.v0 + ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( (q & 0xF) <= 2 ) { + q &= ~3; + sigZExtra = (uint64_t) ((uint_fast64_t) q<<59); + y = softfloat_shortShiftLeft128( sigZ.v64, sigZ.v0, 6 ); + y.v0 |= sigZExtra>>58; + term = softfloat_sub128( y.v64, y.v0, 0, q ); + y = softfloat_mul64ByShifted32To128( term.v0, q ); + term = softfloat_mul64ByShifted32To128( term.v64, q ); + term = softfloat_add128( term.v64, term.v0, 0, y.v64 ); + rem = softfloat_shortShiftLeft128( rem.v64, rem.v0, 20 ); + term = softfloat_sub128( term.v64, term.v0, rem.v64, rem.v0 ); + /*-------------------------------------------------------------------- + | The concatenation of `term' and `y.v0' is now the negative remainder + | (3 words altogether). + *--------------------------------------------------------------------*/ + if ( term.v64 & UINT64_C( 0x8000000000000000 ) ) { + sigZExtra |= 1; + } else { + if ( term.v64 | term.v0 | y.v0 ) { + if ( sigZExtra ) { + --sigZExtra; + } else { + sigZ = softfloat_sub128( sigZ.v64, sigZ.v0, 0, 1 ); + sigZExtra = ~0; + } + } + } + } + return softfloat_roundPackToF128( 0, expZ, sigZ.v64, sigZ.v0, sigZExtra ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + invalid: + softfloat_raiseFlags( softfloat_flag_invalid ); + uiZ.v64 = defaultNaNF128UI64; + uiZ.v0 = defaultNaNF128UI0; + uiZ: + uZ.ui = uiZ; + return uZ.f; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f128_sub.c b/vendor/riscv/riscv-isa-sim/softfloat/f128_sub.c new file mode 100644 index 0000000000..ce2e5adb13 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f128_sub.c @@ -0,0 +1,78 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "softfloat.h" + +float128_t f128_sub( float128_t a, float128_t b ) +{ + union ui128_f128 uA; + uint_fast64_t uiA64, uiA0; + bool signA; + union ui128_f128 uB; + uint_fast64_t uiB64, uiB0; + bool signB; +#if ! defined INLINE_LEVEL || (INLINE_LEVEL < 2) + float128_t + (*magsFuncPtr)( + uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast64_t, bool ); +#endif + + uA.f = a; + uiA64 = uA.ui.v64; + uiA0 = uA.ui.v0; + signA = signF128UI64( uiA64 ); + uB.f = b; + uiB64 = uB.ui.v64; + uiB0 = uB.ui.v0; + signB = signF128UI64( uiB64 ); +#if defined INLINE_LEVEL && (2 <= INLINE_LEVEL) + if ( signA == signB ) { + return softfloat_subMagsF128( uiA64, uiA0, uiB64, uiB0, signA ); + } else { + return softfloat_addMagsF128( uiA64, uiA0, uiB64, uiB0, signA ); + } +#else + magsFuncPtr = + (signA == signB) ? softfloat_subMagsF128 : softfloat_addMagsF128; + return (*magsFuncPtr)( uiA64, uiA0, uiB64, uiB0, signA ); +#endif + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f128_to_f16.c b/vendor/riscv/riscv-isa-sim/softfloat/f128_to_f16.c new file mode 100644 index 0000000000..a910c12a30 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f128_to_f16.c @@ -0,0 +1,95 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +float16_t f128_to_f16( float128_t a ) +{ + union ui128_f128 uA; + uint_fast64_t uiA64, uiA0; + bool sign; + int_fast32_t exp; + uint_fast64_t frac64; + struct commonNaN commonNaN; + uint_fast16_t uiZ, frac16; + union ui16_f16 uZ; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uA.f = a; + uiA64 = uA.ui.v64; + uiA0 = uA.ui.v0; + sign = signF128UI64( uiA64 ); + exp = expF128UI64( uiA64 ); + frac64 = fracF128UI64( uiA64 ) | (uiA0 != 0); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( exp == 0x7FFF ) { + if ( frac64 ) { + softfloat_f128UIToCommonNaN( uiA64, uiA0, &commonNaN ); + uiZ = softfloat_commonNaNToF16UI( &commonNaN ); + } else { + uiZ = packToF16UI( sign, 0x1F, 0 ); + } + goto uiZ; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + frac16 = softfloat_shortShiftRightJam64( frac64, 34 ); + if ( ! (exp | frac16) ) { + uiZ = packToF16UI( sign, 0, 0 ); + goto uiZ; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + exp -= 0x3FF1; + if ( sizeof (int_fast16_t) < sizeof (int_fast32_t) ) { + if ( exp < -0x40 ) exp = -0x40; + } + return softfloat_roundPackToF16( sign, exp, frac16 | 0x4000 ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uiZ: + uZ.ui = uiZ; + return uZ.f; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f128_to_f32.c b/vendor/riscv/riscv-isa-sim/softfloat/f128_to_f32.c new file mode 100644 index 0000000000..d890d3ebe7 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f128_to_f32.c @@ -0,0 +1,95 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +float32_t f128_to_f32( float128_t a ) +{ + union ui128_f128 uA; + uint_fast64_t uiA64, uiA0; + bool sign; + int_fast32_t exp; + uint_fast64_t frac64; + struct commonNaN commonNaN; + uint_fast32_t uiZ, frac32; + union ui32_f32 uZ; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uA.f = a; + uiA64 = uA.ui.v64; + uiA0 = uA.ui.v0; + sign = signF128UI64( uiA64 ); + exp = expF128UI64( uiA64 ); + frac64 = fracF128UI64( uiA64 ) | (uiA0 != 0); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( exp == 0x7FFF ) { + if ( frac64 ) { + softfloat_f128UIToCommonNaN( uiA64, uiA0, &commonNaN ); + uiZ = softfloat_commonNaNToF32UI( &commonNaN ); + } else { + uiZ = packToF32UI( sign, 0xFF, 0 ); + } + goto uiZ; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + frac32 = softfloat_shortShiftRightJam64( frac64, 18 ); + if ( ! (exp | frac32) ) { + uiZ = packToF32UI( sign, 0, 0 ); + goto uiZ; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + exp -= 0x3F81; + if ( sizeof (int_fast16_t) < sizeof (int_fast32_t) ) { + if ( exp < -0x1000 ) exp = -0x1000; + } + return softfloat_roundPackToF32( sign, exp, frac32 | 0x40000000 ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uiZ: + uZ.ui = uiZ; + return uZ.f; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f128_to_f64.c b/vendor/riscv/riscv-isa-sim/softfloat/f128_to_f64.c new file mode 100644 index 0000000000..e7aec20156 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f128_to_f64.c @@ -0,0 +1,100 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +float64_t f128_to_f64( float128_t a ) +{ + union ui128_f128 uA; + uint_fast64_t uiA64, uiA0; + bool sign; + int_fast32_t exp; + uint_fast64_t frac64, frac0; + struct commonNaN commonNaN; + uint_fast64_t uiZ; + struct uint128 frac128; + union ui64_f64 uZ; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uA.f = a; + uiA64 = uA.ui.v64; + uiA0 = uA.ui.v0; + sign = signF128UI64( uiA64 ); + exp = expF128UI64( uiA64 ); + frac64 = fracF128UI64( uiA64 ); + frac0 = uiA0; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( exp == 0x7FFF ) { + if ( frac64 | frac0 ) { + softfloat_f128UIToCommonNaN( uiA64, uiA0, &commonNaN ); + uiZ = softfloat_commonNaNToF64UI( &commonNaN ); + } else { + uiZ = packToF64UI( sign, 0x7FF, 0 ); + } + goto uiZ; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + frac128 = softfloat_shortShiftLeft128( frac64, frac0, 14 ); + frac64 = frac128.v64 | (frac128.v0 != 0); + if ( ! (exp | frac64) ) { + uiZ = packToF64UI( sign, 0, 0 ); + goto uiZ; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + exp -= 0x3C01; + if ( sizeof (int_fast16_t) < sizeof (int_fast32_t) ) { + if ( exp < -0x1000 ) exp = -0x1000; + } + return + softfloat_roundPackToF64( + sign, exp, frac64 | UINT64_C( 0x4000000000000000 ) ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uiZ: + uZ.ui = uiZ; + return uZ.f; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f128_to_i32.c b/vendor/riscv/riscv-isa-sim/softfloat/f128_to_i32.c new file mode 100644 index 0000000000..507691ccb8 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f128_to_i32.c @@ -0,0 +1,85 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the +University of California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +int_fast32_t f128_to_i32( float128_t a, uint_fast8_t roundingMode, bool exact ) +{ + union ui128_f128 uA; + uint_fast64_t uiA64, uiA0; + bool sign; + int_fast32_t exp; + uint_fast64_t sig64, sig0; + int_fast32_t shiftDist; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uA.f = a; + uiA64 = uA.ui.v64; + uiA0 = uA.ui.v0; + sign = signF128UI64( uiA64 ); + exp = expF128UI64( uiA64 ); + sig64 = fracF128UI64( uiA64 ); + sig0 = uiA0; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ +#if (i32_fromNaN != i32_fromPosOverflow) || (i32_fromNaN != i32_fromNegOverflow) + if ( (exp == 0x7FFF) && (sig64 | sig0) ) { +#if (i32_fromNaN == i32_fromPosOverflow) + sign = 0; +#elif (i32_fromNaN == i32_fromNegOverflow) + sign = 1; +#else + softfloat_raiseFlags( softfloat_flag_invalid ); + return i32_fromNaN; +#endif + } +#endif + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( exp ) sig64 |= UINT64_C( 0x0001000000000000 ); + sig64 |= (sig0 != 0); + shiftDist = 0x4023 - exp; + if ( 0 < shiftDist ) sig64 = softfloat_shiftRightJam64( sig64, shiftDist ); + return softfloat_roundToI32( sign, sig64, roundingMode, exact ); + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f128_to_i32_r_minMag.c b/vendor/riscv/riscv-isa-sim/softfloat/f128_to_i32_r_minMag.c new file mode 100644 index 0000000000..fc9f84f18b --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f128_to_i32_r_minMag.c @@ -0,0 +1,100 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +int_fast32_t f128_to_i32_r_minMag( float128_t a, bool exact ) +{ + union ui128_f128 uA; + uint_fast64_t uiA64, uiA0; + int_fast32_t exp; + uint_fast64_t sig64; + int_fast32_t shiftDist; + bool sign; + int_fast32_t absZ; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uA.f = a; + uiA64 = uA.ui.v64; + uiA0 = uA.ui.v0; + exp = expF128UI64( uiA64 ); + sig64 = fracF128UI64( uiA64 ) | (uiA0 != 0); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + shiftDist = 0x402F - exp; + if ( 49 <= shiftDist ) { + if ( exact && (exp | sig64) ) { + softfloat_exceptionFlags |= softfloat_flag_inexact; + } + return 0; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + sign = signF128UI64( uiA64 ); + if ( shiftDist < 18 ) { + if ( + sign && (shiftDist == 17) + && (sig64 < UINT64_C( 0x0000000000020000 )) + ) { + if ( exact && sig64 ) { + softfloat_exceptionFlags |= softfloat_flag_inexact; + } + return -0x7FFFFFFF - 1; + } + softfloat_raiseFlags( softfloat_flag_invalid ); + return + (exp == 0x7FFF) && sig64 ? i32_fromNaN + : sign ? i32_fromNegOverflow : i32_fromPosOverflow; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + sig64 |= UINT64_C( 0x0001000000000000 ); + absZ = sig64>>shiftDist; + if ( + exact && ((uint_fast64_t) (uint_fast32_t) absZ<<shiftDist != sig64) + ) { + softfloat_exceptionFlags |= softfloat_flag_inexact; + } + return sign ? -absZ : absZ; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f128_to_i64.c b/vendor/riscv/riscv-isa-sim/softfloat/f128_to_i64.c new file mode 100644 index 0000000000..2282eafde5 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f128_to_i64.c @@ -0,0 +1,95 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the +University of California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +int_fast64_t f128_to_i64( float128_t a, uint_fast8_t roundingMode, bool exact ) +{ + union ui128_f128 uA; + uint_fast64_t uiA64, uiA0; + bool sign; + int_fast32_t exp; + uint_fast64_t sig64, sig0; + int_fast32_t shiftDist; + struct uint128 sig128; + struct uint64_extra sigExtra; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uA.f = a; + uiA64 = uA.ui.v64; + uiA0 = uA.ui.v0; + sign = signF128UI64( uiA64 ); + exp = expF128UI64( uiA64 ); + sig64 = fracF128UI64( uiA64 ); + sig0 = uiA0; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + shiftDist = 0x402F - exp; + if ( shiftDist <= 0 ) { + /*-------------------------------------------------------------------- + *--------------------------------------------------------------------*/ + if ( shiftDist < -15 ) { + softfloat_raiseFlags( softfloat_flag_invalid ); + return + (exp == 0x7FFF) && (sig64 | sig0) ? i64_fromNaN + : sign ? i64_fromNegOverflow : i64_fromPosOverflow; + } + /*-------------------------------------------------------------------- + *--------------------------------------------------------------------*/ + sig64 |= UINT64_C( 0x0001000000000000 ); + if ( shiftDist ) { + sig128 = softfloat_shortShiftLeft128( sig64, sig0, -shiftDist ); + sig64 = sig128.v64; + sig0 = sig128.v0; + } + } else { + /*-------------------------------------------------------------------- + *--------------------------------------------------------------------*/ + if ( exp ) sig64 |= UINT64_C( 0x0001000000000000 ); + sigExtra = softfloat_shiftRightJam64Extra( sig64, sig0, shiftDist ); + sig64 = sigExtra.v; + sig0 = sigExtra.extra; + } + return softfloat_roundToI64( sign, sig64, sig0, roundingMode, exact ); + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f128_to_i64_r_minMag.c b/vendor/riscv/riscv-isa-sim/softfloat/f128_to_i64_r_minMag.c new file mode 100644 index 0000000000..7e0d63da9c --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f128_to_i64_r_minMag.c @@ -0,0 +1,113 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +int_fast64_t f128_to_i64_r_minMag( float128_t a, bool exact ) +{ + union ui128_f128 uA; + uint_fast64_t uiA64, uiA0; + bool sign; + int_fast32_t exp; + uint_fast64_t sig64, sig0; + int_fast32_t shiftDist; + int_fast8_t negShiftDist; + int_fast64_t absZ; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uA.f = a; + uiA64 = uA.ui.v64; + uiA0 = uA.ui.v0; + sign = signF128UI64( uiA64 ); + exp = expF128UI64( uiA64 ); + sig64 = fracF128UI64( uiA64 ); + sig0 = uiA0; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + shiftDist = 0x402F - exp; + if ( shiftDist < 0 ) { + /*-------------------------------------------------------------------- + *--------------------------------------------------------------------*/ + if ( shiftDist < -14 ) { + if ( + (uiA64 == UINT64_C( 0xC03E000000000000 )) + && (sig0 < UINT64_C( 0x0002000000000000 )) + ) { + if ( exact && sig0 ) { + softfloat_exceptionFlags |= softfloat_flag_inexact; + } + return -INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1; + } + softfloat_raiseFlags( softfloat_flag_invalid ); + return + (exp == 0x7FFF) && (sig64 | sig0) ? i64_fromNaN + : sign ? i64_fromNegOverflow : i64_fromPosOverflow; + } + /*-------------------------------------------------------------------- + *--------------------------------------------------------------------*/ + sig64 |= UINT64_C( 0x0001000000000000 ); + negShiftDist = -shiftDist; + absZ = sig64<<negShiftDist | sig0>>(shiftDist & 63); + if ( exact && (uint64_t) (sig0<<negShiftDist) ) { + softfloat_exceptionFlags |= softfloat_flag_inexact; + } + } else { + /*-------------------------------------------------------------------- + *--------------------------------------------------------------------*/ + if ( 49 <= shiftDist ) { + if ( exact && (exp | sig64 | sig0) ) { + softfloat_exceptionFlags |= softfloat_flag_inexact; + } + return 0; + } + /*-------------------------------------------------------------------- + *--------------------------------------------------------------------*/ + sig64 |= UINT64_C( 0x0001000000000000 ); + absZ = sig64>>shiftDist; + if ( exact && (sig0 || (absZ<<shiftDist != sig64)) ) { + softfloat_exceptionFlags |= softfloat_flag_inexact; + } + } + return sign ? -absZ : absZ; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f128_to_ui32.c b/vendor/riscv/riscv-isa-sim/softfloat/f128_to_ui32.c new file mode 100644 index 0000000000..75e53d9b27 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f128_to_ui32.c @@ -0,0 +1,86 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the +University of California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +uint_fast32_t + f128_to_ui32( float128_t a, uint_fast8_t roundingMode, bool exact ) +{ + union ui128_f128 uA; + uint_fast64_t uiA64, uiA0; + bool sign; + int_fast32_t exp; + uint_fast64_t sig64; + int_fast32_t shiftDist; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uA.f = a; + uiA64 = uA.ui.v64; + uiA0 = uA.ui.v0; + sign = signF128UI64( uiA64 ); + exp = expF128UI64( uiA64 ); + sig64 = fracF128UI64( uiA64 ) | (uiA0 != 0); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ +#if (ui32_fromNaN != ui32_fromPosOverflow) || (ui32_fromNaN != ui32_fromNegOverflow) + if ( (exp == 0x7FFF) && sig64 ) { +#if (ui32_fromNaN == ui32_fromPosOverflow) + sign = 0; +#elif (ui32_fromNaN == ui32_fromNegOverflow) + sign = 1; +#else + softfloat_raiseFlags( softfloat_flag_invalid ); + return ui32_fromNaN; +#endif + } +#endif + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( exp ) sig64 |= UINT64_C( 0x0001000000000000 ); + shiftDist = 0x4023 - exp; + if ( 0 < shiftDist ) { + sig64 = softfloat_shiftRightJam64( sig64, shiftDist ); + } + return softfloat_roundToUI32( sign, sig64, roundingMode, exact ); + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f128_to_ui32_r_minMag.c b/vendor/riscv/riscv-isa-sim/softfloat/f128_to_ui32_r_minMag.c new file mode 100644 index 0000000000..2097fb81f6 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f128_to_ui32_r_minMag.c @@ -0,0 +1,89 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +uint_fast32_t f128_to_ui32_r_minMag( float128_t a, bool exact ) +{ + union ui128_f128 uA; + uint_fast64_t uiA64, uiA0; + int_fast32_t exp; + uint_fast64_t sig64; + int_fast32_t shiftDist; + bool sign; + uint_fast32_t z; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uA.f = a; + uiA64 = uA.ui.v64; + uiA0 = uA.ui.v0; + exp = expF128UI64( uiA64 ); + sig64 = fracF128UI64( uiA64 ) | (uiA0 != 0); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + shiftDist = 0x402F - exp; + if ( 49 <= shiftDist ) { + if ( exact && (exp | sig64) ) { + softfloat_exceptionFlags |= softfloat_flag_inexact; + } + return 0; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + sign = signF128UI64( uiA64 ); + if ( sign || (shiftDist < 17) ) { + softfloat_raiseFlags( softfloat_flag_invalid ); + return + (exp == 0x7FFF) && sig64 ? ui32_fromNaN + : sign ? ui32_fromNegOverflow : ui32_fromPosOverflow; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + sig64 |= UINT64_C( 0x0001000000000000 ); + z = sig64>>shiftDist; + if ( exact && ((uint_fast64_t) z<<shiftDist != sig64) ) { + softfloat_exceptionFlags |= softfloat_flag_inexact; + } + return z; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f128_to_ui64.c b/vendor/riscv/riscv-isa-sim/softfloat/f128_to_ui64.c new file mode 100644 index 0000000000..b88d25151a --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f128_to_ui64.c @@ -0,0 +1,96 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the +University of California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +uint_fast64_t + f128_to_ui64( float128_t a, uint_fast8_t roundingMode, bool exact ) +{ + union ui128_f128 uA; + uint_fast64_t uiA64, uiA0; + bool sign; + int_fast32_t exp; + uint_fast64_t sig64, sig0; + int_fast32_t shiftDist; + struct uint128 sig128; + struct uint64_extra sigExtra; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uA.f = a; + uiA64 = uA.ui.v64; + uiA0 = uA.ui.v0; + sign = signF128UI64( uiA64 ); + exp = expF128UI64( uiA64 ); + sig64 = fracF128UI64( uiA64 ); + sig0 = uiA0; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + shiftDist = 0x402F - exp; + if ( shiftDist <= 0 ) { + /*-------------------------------------------------------------------- + *--------------------------------------------------------------------*/ + if ( shiftDist < -15 ) { + softfloat_raiseFlags( softfloat_flag_invalid ); + return + (exp == 0x7FFF) && (sig64 | sig0) ? ui64_fromNaN + : sign ? ui64_fromNegOverflow : ui64_fromPosOverflow; + } + /*-------------------------------------------------------------------- + *--------------------------------------------------------------------*/ + sig64 |= UINT64_C( 0x0001000000000000 ); + if ( shiftDist ) { + sig128 = softfloat_shortShiftLeft128( sig64, sig0, -shiftDist ); + sig64 = sig128.v64; + sig0 = sig128.v0; + } + } else { + /*-------------------------------------------------------------------- + *--------------------------------------------------------------------*/ + if ( exp ) sig64 |= UINT64_C( 0x0001000000000000 ); + sigExtra = softfloat_shiftRightJam64Extra( sig64, sig0, shiftDist ); + sig64 = sigExtra.v; + sig0 = sigExtra.extra; + } + return softfloat_roundToUI64( sign, sig64, sig0, roundingMode, exact ); + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f128_to_ui64_r_minMag.c b/vendor/riscv/riscv-isa-sim/softfloat/f128_to_ui64_r_minMag.c new file mode 100644 index 0000000000..fb16320aa5 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f128_to_ui64_r_minMag.c @@ -0,0 +1,105 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +uint_fast64_t f128_to_ui64_r_minMag( float128_t a, bool exact ) +{ + union ui128_f128 uA; + uint_fast64_t uiA64, uiA0; + bool sign; + int_fast32_t exp; + uint_fast64_t sig64, sig0; + int_fast32_t shiftDist; + int_fast8_t negShiftDist; + uint_fast64_t z; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uA.f = a; + uiA64 = uA.ui.v64; + uiA0 = uA.ui.v0; + sign = signF128UI64( uiA64 ); + exp = expF128UI64( uiA64 ); + sig64 = fracF128UI64( uiA64 ); + sig0 = uiA0; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + shiftDist = 0x402F - exp; + if ( shiftDist < 0 ) { + /*-------------------------------------------------------------------- + *--------------------------------------------------------------------*/ + if ( sign || (shiftDist < -15) ) goto invalid; + sig64 |= UINT64_C( 0x0001000000000000 ); + negShiftDist = -shiftDist; + z = sig64<<negShiftDist | sig0>>(shiftDist & 63); + if ( exact && (uint64_t) (sig0<<negShiftDist) ) { + softfloat_exceptionFlags |= softfloat_flag_inexact; + } + } else { + /*-------------------------------------------------------------------- + *--------------------------------------------------------------------*/ + if ( 49 <= shiftDist ) { + if ( exact && (exp | sig64 | sig0) ) { + softfloat_exceptionFlags |= softfloat_flag_inexact; + } + return 0; + } + /*-------------------------------------------------------------------- + *--------------------------------------------------------------------*/ + if ( sign ) goto invalid; + sig64 |= UINT64_C( 0x0001000000000000 ); + z = sig64>>shiftDist; + if ( exact && (sig0 || (z<<shiftDist != sig64)) ) { + softfloat_exceptionFlags |= softfloat_flag_inexact; + } + } + return z; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + invalid: + softfloat_raiseFlags( softfloat_flag_invalid ); + return + (exp == 0x7FFF) && (sig64 | sig0) ? ui64_fromNaN + : sign ? ui64_fromNegOverflow : ui64_fromPosOverflow; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f16_add.c b/vendor/riscv/riscv-isa-sim/softfloat/f16_add.c new file mode 100644 index 0000000000..eb763d0119 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f16_add.c @@ -0,0 +1,70 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "softfloat.h" + +float16_t f16_add( float16_t a, float16_t b ) +{ + union ui16_f16 uA; + uint_fast16_t uiA; + union ui16_f16 uB; + uint_fast16_t uiB; +#if ! defined INLINE_LEVEL || (INLINE_LEVEL < 1) + float16_t (*magsFuncPtr)( uint_fast16_t, uint_fast16_t ); +#endif + + uA.f = a; + uiA = uA.ui; + uB.f = b; + uiB = uB.ui; +#if defined INLINE_LEVEL && (1 <= INLINE_LEVEL) + if ( signF16UI( uiA ^ uiB ) ) { + return softfloat_subMagsF16( uiA, uiB ); + } else { + return softfloat_addMagsF16( uiA, uiB ); + } +#else + magsFuncPtr = + signF16UI( uiA ^ uiB ) ? softfloat_subMagsF16 : softfloat_addMagsF16; + return (*magsFuncPtr)( uiA, uiB ); +#endif + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f16_classify.c b/vendor/riscv/riscv-isa-sim/softfloat/f16_classify.c new file mode 100755 index 0000000000..9402ff13e8 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f16_classify.c @@ -0,0 +1,36 @@ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +uint_fast16_t f16_classify( float16_t a ) +{ + union ui16_f16 uA; + uint_fast16_t uiA; + + uA.f = a; + uiA = uA.ui; + + uint_fast16_t infOrNaN = expF16UI( uiA ) == 0x1F; + uint_fast16_t subnormalOrZero = expF16UI( uiA ) == 0; + bool sign = signF16UI( uiA ); + bool fracZero = fracF16UI( uiA ) == 0; + bool isNaN = isNaNF16UI( uiA ); + bool isSNaN = softfloat_isSigNaNF16UI( uiA ); + + return + ( sign && infOrNaN && fracZero ) << 0 | + ( sign && !infOrNaN && !subnormalOrZero ) << 1 | + ( sign && subnormalOrZero && !fracZero ) << 2 | + ( sign && subnormalOrZero && fracZero ) << 3 | + ( !sign && infOrNaN && fracZero ) << 7 | + ( !sign && !infOrNaN && !subnormalOrZero ) << 6 | + ( !sign && subnormalOrZero && !fracZero ) << 5 | + ( !sign && subnormalOrZero && fracZero ) << 4 | + ( isNaN && isSNaN ) << 8 | + ( isNaN && !isSNaN ) << 9; +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f16_div.c b/vendor/riscv/riscv-isa-sim/softfloat/f16_div.c new file mode 100644 index 0000000000..71b5c29b0c --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f16_div.c @@ -0,0 +1,186 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +extern const uint16_t softfloat_approxRecip_1k0s[]; +extern const uint16_t softfloat_approxRecip_1k1s[]; + +float16_t f16_div( float16_t a, float16_t b ) +{ + union ui16_f16 uA; + uint_fast16_t uiA; + bool signA; + int_fast8_t expA; + uint_fast16_t sigA; + union ui16_f16 uB; + uint_fast16_t uiB; + bool signB; + int_fast8_t expB; + uint_fast16_t sigB; + bool signZ; + struct exp8_sig16 normExpSig; + int_fast8_t expZ; +#ifdef SOFTFLOAT_FAST_DIV32TO16 + uint_fast32_t sig32A; + uint_fast16_t sigZ; +#else + int index; + uint16_t r0; + uint_fast16_t sigZ, rem; +#endif + uint_fast16_t uiZ; + union ui16_f16 uZ; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uA.f = a; + uiA = uA.ui; + signA = signF16UI( uiA ); + expA = expF16UI( uiA ); + sigA = fracF16UI( uiA ); + uB.f = b; + uiB = uB.ui; + signB = signF16UI( uiB ); + expB = expF16UI( uiB ); + sigB = fracF16UI( uiB ); + signZ = signA ^ signB; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( expA == 0x1F ) { + if ( sigA ) goto propagateNaN; + if ( expB == 0x1F ) { + if ( sigB ) goto propagateNaN; + goto invalid; + } + goto infinity; + } + if ( expB == 0x1F ) { + if ( sigB ) goto propagateNaN; + goto zero; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( ! expB ) { + if ( ! sigB ) { + if ( ! (expA | sigA) ) goto invalid; + softfloat_raiseFlags( softfloat_flag_infinite ); + goto infinity; + } + normExpSig = softfloat_normSubnormalF16Sig( sigB ); + expB = normExpSig.exp; + sigB = normExpSig.sig; + } + if ( ! expA ) { + if ( ! sigA ) goto zero; + normExpSig = softfloat_normSubnormalF16Sig( sigA ); + expA = normExpSig.exp; + sigA = normExpSig.sig; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + expZ = expA - expB + 0xE; + sigA |= 0x0400; + sigB |= 0x0400; +#ifdef SOFTFLOAT_FAST_DIV32TO16 + if ( sigA < sigB ) { + --expZ; + sig32A = (uint_fast32_t) sigA<<15; + } else { + sig32A = (uint_fast32_t) sigA<<14; + } + sigZ = sig32A / sigB; + if ( ! (sigZ & 7) ) sigZ |= ((uint_fast32_t) sigB * sigZ != sig32A); +#else + if ( sigA < sigB ) { + --expZ; + sigA <<= 5; + } else { + sigA <<= 4; + } + index = sigB>>6 & 0xF; + r0 = softfloat_approxRecip_1k0s[index] + - (((uint_fast32_t) softfloat_approxRecip_1k1s[index] + * (sigB & 0x3F)) + >>10); + sigZ = ((uint_fast32_t) sigA * r0)>>16; + rem = (sigA<<10) - sigZ * sigB; + sigZ += (rem * (uint_fast32_t) r0)>>26; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + ++sigZ; + if ( ! (sigZ & 7) ) { + sigZ &= ~1; + rem = (sigA<<10) - sigZ * sigB; + if ( rem & 0x8000 ) { + sigZ -= 2; + } else { + if ( rem ) sigZ |= 1; + } + } +#endif + return softfloat_roundPackToF16( signZ, expZ, sigZ ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + propagateNaN: + uiZ = softfloat_propagateNaNF16UI( uiA, uiB ); + goto uiZ; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + invalid: + softfloat_raiseFlags( softfloat_flag_invalid ); + uiZ = defaultNaNF16UI; + goto uiZ; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + infinity: + uiZ = packToF16UI( signZ, 0x1F, 0 ); + goto uiZ; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + zero: + uiZ = packToF16UI( signZ, 0, 0 ); + uiZ: + uZ.ui = uiZ; + return uZ.f; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f16_eq.c b/vendor/riscv/riscv-isa-sim/softfloat/f16_eq.c new file mode 100644 index 0000000000..37a60998f1 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f16_eq.c @@ -0,0 +1,66 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +bool f16_eq( float16_t a, float16_t b ) +{ + union ui16_f16 uA; + uint_fast16_t uiA; + union ui16_f16 uB; + uint_fast16_t uiB; + + uA.f = a; + uiA = uA.ui; + uB.f = b; + uiB = uB.ui; + if ( isNaNF16UI( uiA ) || isNaNF16UI( uiB ) ) { + if ( + softfloat_isSigNaNF16UI( uiA ) || softfloat_isSigNaNF16UI( uiB ) + ) { + softfloat_raiseFlags( softfloat_flag_invalid ); + } + return false; + } + return (uiA == uiB) || ! (uint16_t) ((uiA | uiB)<<1); + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f16_eq_signaling.c b/vendor/riscv/riscv-isa-sim/softfloat/f16_eq_signaling.c new file mode 100644 index 0000000000..894f7b59d7 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f16_eq_signaling.c @@ -0,0 +1,61 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "softfloat.h" + +bool f16_eq_signaling( float16_t a, float16_t b ) +{ + union ui16_f16 uA; + uint_fast16_t uiA; + union ui16_f16 uB; + uint_fast16_t uiB; + + uA.f = a; + uiA = uA.ui; + uB.f = b; + uiB = uB.ui; + if ( isNaNF16UI( uiA ) || isNaNF16UI( uiB ) ) { + softfloat_raiseFlags( softfloat_flag_invalid ); + return false; + } + return (uiA == uiB) || ! (uint16_t) ((uiA | uiB)<<1); + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f16_isSignalingNaN.c b/vendor/riscv/riscv-isa-sim/softfloat/f16_isSignalingNaN.c new file mode 100644 index 0000000000..657805be3f --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f16_isSignalingNaN.c @@ -0,0 +1,51 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +bool f16_isSignalingNaN( float16_t a ) +{ + union ui16_f16 uA; + + uA.f = a; + return softfloat_isSigNaNF16UI( uA.ui ); + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f16_le.c b/vendor/riscv/riscv-isa-sim/softfloat/f16_le.c new file mode 100644 index 0000000000..37eaf1879a --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f16_le.c @@ -0,0 +1,66 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "softfloat.h" + +bool f16_le( float16_t a, float16_t b ) +{ + union ui16_f16 uA; + uint_fast16_t uiA; + union ui16_f16 uB; + uint_fast16_t uiB; + bool signA, signB; + + uA.f = a; + uiA = uA.ui; + uB.f = b; + uiB = uB.ui; + if ( isNaNF16UI( uiA ) || isNaNF16UI( uiB ) ) { + softfloat_raiseFlags( softfloat_flag_invalid ); + return false; + } + signA = signF16UI( uiA ); + signB = signF16UI( uiB ); + return + (signA != signB) ? signA || ! (uint16_t) ((uiA | uiB)<<1) + : (uiA == uiB) || (signA ^ (uiA < uiB)); + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f16_le_quiet.c b/vendor/riscv/riscv-isa-sim/softfloat/f16_le_quiet.c new file mode 100644 index 0000000000..8391db74db --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f16_le_quiet.c @@ -0,0 +1,71 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +bool f16_le_quiet( float16_t a, float16_t b ) +{ + union ui16_f16 uA; + uint_fast16_t uiA; + union ui16_f16 uB; + uint_fast16_t uiB; + bool signA, signB; + + uA.f = a; + uiA = uA.ui; + uB.f = b; + uiB = uB.ui; + if ( isNaNF16UI( uiA ) || isNaNF16UI( uiB ) ) { + if ( + softfloat_isSigNaNF16UI( uiA ) || softfloat_isSigNaNF16UI( uiB ) + ) { + softfloat_raiseFlags( softfloat_flag_invalid ); + } + return false; + } + signA = signF16UI( uiA ); + signB = signF16UI( uiB ); + return + (signA != signB) ? signA || ! (uint16_t) ((uiA | uiB)<<1) + : (uiA == uiB) || (signA ^ (uiA < uiB)); + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f16_lt.c b/vendor/riscv/riscv-isa-sim/softfloat/f16_lt.c new file mode 100644 index 0000000000..3d3522a473 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f16_lt.c @@ -0,0 +1,66 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "softfloat.h" + +bool f16_lt( float16_t a, float16_t b ) +{ + union ui16_f16 uA; + uint_fast16_t uiA; + union ui16_f16 uB; + uint_fast16_t uiB; + bool signA, signB; + + uA.f = a; + uiA = uA.ui; + uB.f = b; + uiB = uB.ui; + if ( isNaNF16UI( uiA ) || isNaNF16UI( uiB ) ) { + softfloat_raiseFlags( softfloat_flag_invalid ); + return false; + } + signA = signF16UI( uiA ); + signB = signF16UI( uiB ); + return + (signA != signB) ? signA && ((uint16_t) ((uiA | uiB)<<1) != 0) + : (uiA != uiB) && (signA ^ (uiA < uiB)); + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f16_lt_quiet.c b/vendor/riscv/riscv-isa-sim/softfloat/f16_lt_quiet.c new file mode 100644 index 0000000000..37f762cdae --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f16_lt_quiet.c @@ -0,0 +1,71 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +bool f16_lt_quiet( float16_t a, float16_t b ) +{ + union ui16_f16 uA; + uint_fast16_t uiA; + union ui16_f16 uB; + uint_fast16_t uiB; + bool signA, signB; + + uA.f = a; + uiA = uA.ui; + uB.f = b; + uiB = uB.ui; + if ( isNaNF16UI( uiA ) || isNaNF16UI( uiB ) ) { + if ( + softfloat_isSigNaNF16UI( uiA ) || softfloat_isSigNaNF16UI( uiB ) + ) { + softfloat_raiseFlags( softfloat_flag_invalid ); + } + return false; + } + signA = signF16UI( uiA ); + signB = signF16UI( uiB ); + return + (signA != signB) ? signA && ((uint16_t) ((uiA | uiB)<<1) != 0) + : (uiA != uiB) && (signA ^ (uiA < uiB)); + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f16_mul.c b/vendor/riscv/riscv-isa-sim/softfloat/f16_mul.c new file mode 100644 index 0000000000..255caa7edc --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f16_mul.c @@ -0,0 +1,140 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +float16_t f16_mul( float16_t a, float16_t b ) +{ + union ui16_f16 uA; + uint_fast16_t uiA; + bool signA; + int_fast8_t expA; + uint_fast16_t sigA; + union ui16_f16 uB; + uint_fast16_t uiB; + bool signB; + int_fast8_t expB; + uint_fast16_t sigB; + bool signZ; + uint_fast16_t magBits; + struct exp8_sig16 normExpSig; + int_fast8_t expZ; + uint_fast32_t sig32Z; + uint_fast16_t sigZ, uiZ; + union ui16_f16 uZ; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uA.f = a; + uiA = uA.ui; + signA = signF16UI( uiA ); + expA = expF16UI( uiA ); + sigA = fracF16UI( uiA ); + uB.f = b; + uiB = uB.ui; + signB = signF16UI( uiB ); + expB = expF16UI( uiB ); + sigB = fracF16UI( uiB ); + signZ = signA ^ signB; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( expA == 0x1F ) { + if ( sigA || ((expB == 0x1F) && sigB) ) goto propagateNaN; + magBits = expB | sigB; + goto infArg; + } + if ( expB == 0x1F ) { + if ( sigB ) goto propagateNaN; + magBits = expA | sigA; + goto infArg; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( ! expA ) { + if ( ! sigA ) goto zero; + normExpSig = softfloat_normSubnormalF16Sig( sigA ); + expA = normExpSig.exp; + sigA = normExpSig.sig; + } + if ( ! expB ) { + if ( ! sigB ) goto zero; + normExpSig = softfloat_normSubnormalF16Sig( sigB ); + expB = normExpSig.exp; + sigB = normExpSig.sig; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + expZ = expA + expB - 0xF; + sigA = (sigA | 0x0400)<<4; + sigB = (sigB | 0x0400)<<5; + sig32Z = (uint_fast32_t) sigA * sigB; + sigZ = sig32Z>>16; + if ( sig32Z & 0xFFFF ) sigZ |= 1; + if ( sigZ < 0x4000 ) { + --expZ; + sigZ <<= 1; + } + return softfloat_roundPackToF16( signZ, expZ, sigZ ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + propagateNaN: + uiZ = softfloat_propagateNaNF16UI( uiA, uiB ); + goto uiZ; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + infArg: + if ( ! magBits ) { + softfloat_raiseFlags( softfloat_flag_invalid ); + uiZ = defaultNaNF16UI; + } else { + uiZ = packToF16UI( signZ, 0x1F, 0 ); + } + goto uiZ; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + zero: + uiZ = packToF16UI( signZ, 0, 0 ); + uiZ: + uZ.ui = uiZ; + return uZ.f; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f16_mulAdd.c b/vendor/riscv/riscv-isa-sim/softfloat/f16_mulAdd.c new file mode 100644 index 0000000000..4026196393 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f16_mulAdd.c @@ -0,0 +1,60 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "softfloat.h" + +float16_t f16_mulAdd( float16_t a, float16_t b, float16_t c ) +{ + union ui16_f16 uA; + uint_fast16_t uiA; + union ui16_f16 uB; + uint_fast16_t uiB; + union ui16_f16 uC; + uint_fast16_t uiC; + + uA.f = a; + uiA = uA.ui; + uB.f = b; + uiB = uB.ui; + uC.f = c; + uiC = uC.ui; + return softfloat_mulAddF16( uiA, uiB, uiC, 0 ); + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f16_rem.c b/vendor/riscv/riscv-isa-sim/softfloat/f16_rem.c new file mode 100644 index 0000000000..86c319ddce --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f16_rem.c @@ -0,0 +1,171 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +float16_t f16_rem( float16_t a, float16_t b ) +{ + union ui16_f16 uA; + uint_fast16_t uiA; + bool signA; + int_fast8_t expA; + uint_fast16_t sigA; + union ui16_f16 uB; + uint_fast16_t uiB; + int_fast8_t expB; + uint_fast16_t sigB; + struct exp8_sig16 normExpSig; + uint16_t rem; + int_fast8_t expDiff; + uint_fast16_t q; + uint32_t recip32, q32; + uint16_t altRem, meanRem; + bool signRem; + uint_fast16_t uiZ; + union ui16_f16 uZ; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uA.f = a; + uiA = uA.ui; + signA = signF16UI( uiA ); + expA = expF16UI( uiA ); + sigA = fracF16UI( uiA ); + uB.f = b; + uiB = uB.ui; + expB = expF16UI( uiB ); + sigB = fracF16UI( uiB ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( expA == 0x1F ) { + if ( sigA || ((expB == 0x1F) && sigB) ) goto propagateNaN; + goto invalid; + } + if ( expB == 0x1F ) { + if ( sigB ) goto propagateNaN; + return a; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( ! expB ) { + if ( ! sigB ) goto invalid; + normExpSig = softfloat_normSubnormalF16Sig( sigB ); + expB = normExpSig.exp; + sigB = normExpSig.sig; + } + if ( ! expA ) { + if ( ! sigA ) return a; + normExpSig = softfloat_normSubnormalF16Sig( sigA ); + expA = normExpSig.exp; + sigA = normExpSig.sig; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + rem = sigA | 0x0400; + sigB |= 0x0400; + expDiff = expA - expB; + if ( expDiff < 1 ) { + if ( expDiff < -1 ) return a; + sigB <<= 3; + if ( expDiff ) { + rem <<= 2; + q = 0; + } else { + rem <<= 3; + q = (sigB <= rem); + if ( q ) rem -= sigB; + } + } else { + recip32 = softfloat_approxRecip32_1( (uint_fast32_t) sigB<<21 ); + /*-------------------------------------------------------------------- + | Changing the shift of `rem' here requires also changing the initial + | subtraction from `expDiff'. + *--------------------------------------------------------------------*/ + rem <<= 4; + expDiff -= 31; + /*-------------------------------------------------------------------- + | The scale of `sigB' affects how many bits are obtained during each + | cycle of the loop. Currently this is 29 bits per loop iteration, + | which is believed to be the maximum possible. + *--------------------------------------------------------------------*/ + sigB <<= 3; + for (;;) { + q32 = (rem * (uint_fast64_t) recip32)>>16; + if ( expDiff < 0 ) break; + rem = -((uint_fast16_t) q32 * sigB); + expDiff -= 29; + } + /*-------------------------------------------------------------------- + | (`expDiff' cannot be less than -30 here.) + *--------------------------------------------------------------------*/ + q32 >>= ~expDiff & 31; + q = q32; + rem = (rem<<(expDiff + 30)) - q * sigB; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + do { + altRem = rem; + ++q; + rem -= sigB; + } while ( ! (rem & 0x8000) ); + meanRem = rem + altRem; + if ( (meanRem & 0x8000) || (! meanRem && (q & 1)) ) rem = altRem; + signRem = signA; + if ( 0x8000 <= rem ) { + signRem = ! signRem; + rem = -rem; + } + return softfloat_normRoundPackToF16( signRem, expB, rem ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + propagateNaN: + uiZ = softfloat_propagateNaNF16UI( uiA, uiB ); + goto uiZ; + invalid: + softfloat_raiseFlags( softfloat_flag_invalid ); + uiZ = defaultNaNF16UI; + uiZ: + uZ.ui = uiZ; + return uZ.f; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f16_roundToInt.c b/vendor/riscv/riscv-isa-sim/softfloat/f16_roundToInt.c new file mode 100644 index 0000000000..9bbd47eb2d --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f16_roundToInt.c @@ -0,0 +1,112 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +float16_t f16_roundToInt( float16_t a, uint_fast8_t roundingMode, bool exact ) +{ + union ui16_f16 uA; + uint_fast16_t uiA; + int_fast8_t exp; + uint_fast16_t uiZ, lastBitMask, roundBitsMask; + union ui16_f16 uZ; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uA.f = a; + uiA = uA.ui; + exp = expF16UI( uiA ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( exp <= 0xE ) { + if ( ! (uint16_t) (uiA<<1) ) return a; + if ( exact ) softfloat_exceptionFlags |= softfloat_flag_inexact; + uiZ = uiA & packToF16UI( 1, 0, 0 ); + switch ( roundingMode ) { + case softfloat_round_near_even: + if ( ! fracF16UI( uiA ) ) break; + case softfloat_round_near_maxMag: + if ( exp == 0xE ) uiZ |= packToF16UI( 0, 0xF, 0 ); + break; + case softfloat_round_min: + if ( uiZ ) uiZ = packToF16UI( 1, 0xF, 0 ); + break; + case softfloat_round_max: + if ( ! uiZ ) uiZ = packToF16UI( 0, 0xF, 0 ); + break; + } + goto uiZ; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( 0x19 <= exp ) { + if ( (exp == 0x1F) && fracF16UI( uiA ) ) { + uiZ = softfloat_propagateNaNF16UI( uiA, 0 ); + goto uiZ; + } + return a; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uiZ = uiA; + lastBitMask = (uint_fast16_t) 1<<(0x19 - exp); + roundBitsMask = lastBitMask - 1; + if ( roundingMode == softfloat_round_near_maxMag ) { + uiZ += lastBitMask>>1; + } else if ( roundingMode == softfloat_round_near_even ) { + uiZ += lastBitMask>>1; + if ( ! (uiZ & roundBitsMask) ) uiZ &= ~lastBitMask; + } else if ( + roundingMode + == (signF16UI( uiZ ) ? softfloat_round_min : softfloat_round_max) + ) { + uiZ += roundBitsMask; + } + uiZ &= ~roundBitsMask; + if ( exact && (uiZ != uiA) ) { + softfloat_exceptionFlags |= softfloat_flag_inexact; + } + uiZ: + uZ.ui = uiZ; + return uZ.f; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f16_sqrt.c b/vendor/riscv/riscv-isa-sim/softfloat/f16_sqrt.c new file mode 100644 index 0000000000..7ff292392e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f16_sqrt.c @@ -0,0 +1,136 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +extern const uint16_t softfloat_approxRecipSqrt_1k0s[]; +extern const uint16_t softfloat_approxRecipSqrt_1k1s[]; + +float16_t f16_sqrt( float16_t a ) +{ + union ui16_f16 uA; + uint_fast16_t uiA; + bool signA; + int_fast8_t expA; + uint_fast16_t sigA, uiZ; + struct exp8_sig16 normExpSig; + int_fast8_t expZ; + int index; + uint_fast16_t r0; + uint_fast32_t ESqrR0; + uint16_t sigma0; + uint_fast16_t recipSqrt16, sigZ, shiftedSigZ; + uint16_t negRem; + union ui16_f16 uZ; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uA.f = a; + uiA = uA.ui; + signA = signF16UI( uiA ); + expA = expF16UI( uiA ); + sigA = fracF16UI( uiA ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( expA == 0x1F ) { + if ( sigA ) { + uiZ = softfloat_propagateNaNF16UI( uiA, 0 ); + goto uiZ; + } + if ( ! signA ) return a; + goto invalid; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( signA ) { + if ( ! (expA | sigA) ) return a; + goto invalid; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( ! expA ) { + if ( ! sigA ) return a; + normExpSig = softfloat_normSubnormalF16Sig( sigA ); + expA = normExpSig.exp; + sigA = normExpSig.sig; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + expZ = ((expA - 0xF)>>1) + 0xE; + expA &= 1; + sigA |= 0x0400; + index = (sigA>>6 & 0xE) + expA; + r0 = softfloat_approxRecipSqrt_1k0s[index] + - (((uint_fast32_t) softfloat_approxRecipSqrt_1k1s[index] + * (sigA & 0x7F)) + >>11); + ESqrR0 = ((uint_fast32_t) r0 * r0)>>1; + if ( expA ) ESqrR0 >>= 1; + sigma0 = ~(uint_fast16_t) ((ESqrR0 * sigA)>>16); + recipSqrt16 = r0 + (((uint_fast32_t) r0 * sigma0)>>25); + if ( ! (recipSqrt16 & 0x8000) ) recipSqrt16 = 0x8000; + sigZ = ((uint_fast32_t) (sigA<<5) * recipSqrt16)>>16; + if ( expA ) sigZ >>= 1; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + ++sigZ; + if ( ! (sigZ & 7) ) { + shiftedSigZ = sigZ>>1; + negRem = shiftedSigZ * shiftedSigZ; + sigZ &= ~1; + if ( negRem & 0x8000 ) { + sigZ |= 1; + } else { + if ( negRem ) --sigZ; + } + } + return softfloat_roundPackToF16( 0, expZ, sigZ ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + invalid: + softfloat_raiseFlags( softfloat_flag_invalid ); + uiZ = defaultNaNF16UI; + uiZ: + uZ.ui = uiZ; + return uZ.f; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f16_sub.c b/vendor/riscv/riscv-isa-sim/softfloat/f16_sub.c new file mode 100644 index 0000000000..811f239f10 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f16_sub.c @@ -0,0 +1,70 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "softfloat.h" + +float16_t f16_sub( float16_t a, float16_t b ) +{ + union ui16_f16 uA; + uint_fast16_t uiA; + union ui16_f16 uB; + uint_fast16_t uiB; +#if ! defined INLINE_LEVEL || (INLINE_LEVEL < 1) + float16_t (*magsFuncPtr)( uint_fast16_t, uint_fast16_t ); +#endif + + uA.f = a; + uiA = uA.ui; + uB.f = b; + uiB = uB.ui; +#if defined INLINE_LEVEL && (1 <= INLINE_LEVEL) + if ( signF16UI( uiA ^ uiB ) ) { + return softfloat_addMagsF16( uiA, uiB ); + } else { + return softfloat_subMagsF16( uiA, uiB ); + } +#else + magsFuncPtr = + signF16UI( uiA ^ uiB ) ? softfloat_addMagsF16 : softfloat_subMagsF16; + return (*magsFuncPtr)( uiA, uiB ); +#endif + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f16_to_f128.c b/vendor/riscv/riscv-isa-sim/softfloat/f16_to_f128.c new file mode 100644 index 0000000000..961cdaaf17 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f16_to_f128.c @@ -0,0 +1,96 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +float128_t f16_to_f128( float16_t a ) +{ + union ui16_f16 uA; + uint_fast16_t uiA; + bool sign; + int_fast8_t exp; + uint_fast16_t frac; + struct commonNaN commonNaN; + struct uint128 uiZ; + struct exp8_sig16 normExpSig; + union ui128_f128 uZ; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uA.f = a; + uiA = uA.ui; + sign = signF16UI( uiA ); + exp = expF16UI( uiA ); + frac = fracF16UI( uiA ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( exp == 0x1F ) { + if ( frac ) { + softfloat_f16UIToCommonNaN( uiA, &commonNaN ); + uiZ = softfloat_commonNaNToF128UI( &commonNaN ); + } else { + uiZ.v64 = packToF128UI64( sign, 0x7FFF, 0 ); + uiZ.v0 = 0; + } + goto uiZ; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( ! exp ) { + if ( ! frac ) { + uiZ.v64 = packToF128UI64( sign, 0, 0 ); + uiZ.v0 = 0; + goto uiZ; + } + normExpSig = softfloat_normSubnormalF16Sig( frac ); + exp = normExpSig.exp - 1; + frac = normExpSig.sig; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uiZ.v64 = packToF128UI64( sign, exp + 0x3FF0, (uint_fast64_t) frac<<38 ); + uiZ.v0 = 0; + uiZ: + uZ.ui = uiZ; + return uZ.f; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f16_to_f32.c b/vendor/riscv/riscv-isa-sim/softfloat/f16_to_f32.c new file mode 100644 index 0000000000..fb8b3819d1 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f16_to_f32.c @@ -0,0 +1,93 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +float32_t f16_to_f32( float16_t a ) +{ + union ui16_f16 uA; + uint_fast16_t uiA; + bool sign; + int_fast8_t exp; + uint_fast16_t frac; + struct commonNaN commonNaN; + uint_fast32_t uiZ; + struct exp8_sig16 normExpSig; + union ui32_f32 uZ; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uA.f = a; + uiA = uA.ui; + sign = signF16UI( uiA ); + exp = expF16UI( uiA ); + frac = fracF16UI( uiA ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( exp == 0x1F ) { + if ( frac ) { + softfloat_f16UIToCommonNaN( uiA, &commonNaN ); + uiZ = softfloat_commonNaNToF32UI( &commonNaN ); + } else { + uiZ = packToF32UI( sign, 0xFF, 0 ); + } + goto uiZ; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( ! exp ) { + if ( ! frac ) { + uiZ = packToF32UI( sign, 0, 0 ); + goto uiZ; + } + normExpSig = softfloat_normSubnormalF16Sig( frac ); + exp = normExpSig.exp - 1; + frac = normExpSig.sig; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uiZ = packToF32UI( sign, exp + 0x70, (uint_fast32_t) frac<<13 ); + uiZ: + uZ.ui = uiZ; + return uZ.f; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f16_to_f64.c b/vendor/riscv/riscv-isa-sim/softfloat/f16_to_f64.c new file mode 100644 index 0000000000..4ab27ba0b5 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f16_to_f64.c @@ -0,0 +1,93 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +float64_t f16_to_f64( float16_t a ) +{ + union ui16_f16 uA; + uint_fast16_t uiA; + bool sign; + int_fast8_t exp; + uint_fast16_t frac; + struct commonNaN commonNaN; + uint_fast64_t uiZ; + struct exp8_sig16 normExpSig; + union ui64_f64 uZ; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uA.f = a; + uiA = uA.ui; + sign = signF16UI( uiA ); + exp = expF16UI( uiA ); + frac = fracF16UI( uiA ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( exp == 0x1F ) { + if ( frac ) { + softfloat_f16UIToCommonNaN( uiA, &commonNaN ); + uiZ = softfloat_commonNaNToF64UI( &commonNaN ); + } else { + uiZ = packToF64UI( sign, 0x7FF, 0 ); + } + goto uiZ; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( ! exp ) { + if ( ! frac ) { + uiZ = packToF64UI( sign, 0, 0 ); + goto uiZ; + } + normExpSig = softfloat_normSubnormalF16Sig( frac ); + exp = normExpSig.exp - 1; + frac = normExpSig.sig; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uiZ = packToF64UI( sign, exp + 0x3F0, (uint_fast64_t) frac<<42 ); + uiZ: + uZ.ui = uiZ; + return uZ.f; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f16_to_i16.c b/vendor/riscv/riscv-isa-sim/softfloat/f16_to_i16.c new file mode 100644 index 0000000000..b0fbb7cc75 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f16_to_i16.c @@ -0,0 +1,57 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the +University of California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "specialize.h" +#include "softfloat.h" + +int_fast16_t f16_to_i16( float16_t a, uint_fast8_t roundingMode, bool exact ) +{ + uint_fast8_t old_flags = softfloat_exceptionFlags; + + int_fast32_t sig32 = f16_to_i32(a, roundingMode, exact); + + if (sig32 > INT16_MAX) { + softfloat_exceptionFlags = old_flags | softfloat_flag_invalid; + return i16_fromPosOverflow; + } else if (sig32 < INT16_MIN) { + softfloat_exceptionFlags = old_flags | softfloat_flag_invalid; + return i16_fromNegOverflow; + } else { + return sig32; + } +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f16_to_i32.c b/vendor/riscv/riscv-isa-sim/softfloat/f16_to_i32.c new file mode 100644 index 0000000000..24b19846d0 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f16_to_i32.c @@ -0,0 +1,87 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the +University of California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +int_fast32_t f16_to_i32( float16_t a, uint_fast8_t roundingMode, bool exact ) +{ + union ui16_f16 uA; + uint_fast16_t uiA; + bool sign; + int_fast8_t exp; + uint_fast16_t frac; + int_fast32_t sig32; + int_fast8_t shiftDist; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uA.f = a; + uiA = uA.ui; + sign = signF16UI( uiA ); + exp = expF16UI( uiA ); + frac = fracF16UI( uiA ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( exp == 0x1F ) { + softfloat_raiseFlags( softfloat_flag_invalid ); + return + frac ? i32_fromNaN + : sign ? i32_fromNegOverflow : i32_fromPosOverflow; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + sig32 = frac; + if ( exp ) { + sig32 |= 0x0400; + shiftDist = exp - 0x19; + if ( 0 <= shiftDist ) { + sig32 <<= shiftDist; + return sign ? -sig32 : sig32; + } + shiftDist = exp - 0x0D; + if ( 0 < shiftDist ) sig32 <<= shiftDist; + } + return + softfloat_roundToI32( + sign, (uint_fast32_t) sig32, roundingMode, exact ); + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f16_to_i32_r_minMag.c b/vendor/riscv/riscv-isa-sim/softfloat/f16_to_i32_r_minMag.c new file mode 100644 index 0000000000..ebb4965ca6 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f16_to_i32_r_minMag.c @@ -0,0 +1,88 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +int_fast32_t f16_to_i32_r_minMag( float16_t a, bool exact ) +{ + union ui16_f16 uA; + uint_fast16_t uiA; + int_fast8_t exp; + uint_fast16_t frac; + int_fast8_t shiftDist; + bool sign; + int_fast32_t alignedSig; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uA.f = a; + uiA = uA.ui; + exp = expF16UI( uiA ); + frac = fracF16UI( uiA ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + shiftDist = exp - 0x0F; + if ( shiftDist < 0 ) { + if ( exact && (exp | frac) ) { + softfloat_exceptionFlags |= softfloat_flag_inexact; + } + return 0; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + sign = signF16UI( uiA ); + if ( exp == 0x1F ) { + softfloat_raiseFlags( softfloat_flag_invalid ); + return + (exp == 0x1F) && frac ? i32_fromNaN + : sign ? i32_fromNegOverflow : i32_fromPosOverflow; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + alignedSig = (int_fast32_t) (frac | 0x0400)<<shiftDist; + if ( exact && (alignedSig & 0x3FF) ) { + softfloat_exceptionFlags |= softfloat_flag_inexact; + } + alignedSig >>= 10; + return sign ? -alignedSig : alignedSig; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f16_to_i64.c b/vendor/riscv/riscv-isa-sim/softfloat/f16_to_i64.c new file mode 100644 index 0000000000..c241745640 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f16_to_i64.c @@ -0,0 +1,87 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the +University of California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +int_fast64_t f16_to_i64( float16_t a, uint_fast8_t roundingMode, bool exact ) +{ + union ui16_f16 uA; + uint_fast16_t uiA; + bool sign; + int_fast8_t exp; + uint_fast16_t frac; + int_fast32_t sig32; + int_fast8_t shiftDist; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uA.f = a; + uiA = uA.ui; + sign = signF16UI( uiA ); + exp = expF16UI( uiA ); + frac = fracF16UI( uiA ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( exp == 0x1F ) { + softfloat_raiseFlags( softfloat_flag_invalid ); + return + frac ? i64_fromNaN + : sign ? i64_fromNegOverflow : i64_fromPosOverflow; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + sig32 = frac; + if ( exp ) { + sig32 |= 0x0400; + shiftDist = exp - 0x19; + if ( 0 <= shiftDist ) { + sig32 <<= shiftDist; + return sign ? -sig32 : sig32; + } + shiftDist = exp - 0x0D; + if ( 0 < shiftDist ) sig32 <<= shiftDist; + } + return + softfloat_roundToI32( + sign, (uint_fast32_t) sig32, roundingMode, exact ); + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f16_to_i64_r_minMag.c b/vendor/riscv/riscv-isa-sim/softfloat/f16_to_i64_r_minMag.c new file mode 100644 index 0000000000..dc9a8d37f2 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f16_to_i64_r_minMag.c @@ -0,0 +1,88 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +int_fast64_t f16_to_i64_r_minMag( float16_t a, bool exact ) +{ + union ui16_f16 uA; + uint_fast16_t uiA; + int_fast8_t exp; + uint_fast16_t frac; + int_fast8_t shiftDist; + bool sign; + int_fast32_t alignedSig; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uA.f = a; + uiA = uA.ui; + exp = expF16UI( uiA ); + frac = fracF16UI( uiA ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + shiftDist = exp - 0x0F; + if ( shiftDist < 0 ) { + if ( exact && (exp | frac) ) { + softfloat_exceptionFlags |= softfloat_flag_inexact; + } + return 0; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + sign = signF16UI( uiA ); + if ( exp == 0x1F ) { + softfloat_raiseFlags( softfloat_flag_invalid ); + return + (exp == 0x1F) && frac ? i64_fromNaN + : sign ? i64_fromNegOverflow : i64_fromPosOverflow; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + alignedSig = (int_fast32_t) (frac | 0x0400)<<shiftDist; + if ( exact && (alignedSig & 0x3FF) ) { + softfloat_exceptionFlags |= softfloat_flag_inexact; + } + alignedSig >>= 10; + return sign ? -alignedSig : alignedSig; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f16_to_i8.c b/vendor/riscv/riscv-isa-sim/softfloat/f16_to_i8.c new file mode 100644 index 0000000000..23638cc102 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f16_to_i8.c @@ -0,0 +1,57 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the +University of California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "specialize.h" +#include "softfloat.h" + +int_fast8_t f16_to_i8( float16_t a, uint_fast8_t roundingMode, bool exact ) +{ + uint_fast8_t old_flags = softfloat_exceptionFlags; + + int_fast32_t sig32 = f16_to_i32(a, roundingMode, exact); + + if (sig32 > INT8_MAX) { + softfloat_exceptionFlags = old_flags | softfloat_flag_invalid; + return i8_fromPosOverflow; + } else if (sig32 < INT8_MIN) { + softfloat_exceptionFlags = old_flags | softfloat_flag_invalid; + return i8_fromNegOverflow; + } else { + return sig32; + } +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f16_to_ui16.c b/vendor/riscv/riscv-isa-sim/softfloat/f16_to_ui16.c new file mode 100644 index 0000000000..81c4f8d9e0 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f16_to_ui16.c @@ -0,0 +1,54 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the +University of California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "specialize.h" +#include "softfloat.h" + +uint_fast16_t f16_to_ui16( float16_t a, uint_fast8_t roundingMode, bool exact ) +{ + uint_fast8_t old_flags = softfloat_exceptionFlags; + + uint_fast32_t sig32 = f16_to_ui32(a, roundingMode, exact); + + if (sig32 > UINT16_MAX) { + softfloat_exceptionFlags = old_flags | softfloat_flag_invalid; + return ui16_fromPosOverflow; + } else { + return sig32; + } +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f16_to_ui32.c b/vendor/riscv/riscv-isa-sim/softfloat/f16_to_ui32.c new file mode 100644 index 0000000000..c99af39c67 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f16_to_ui32.c @@ -0,0 +1,84 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the +University of California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +uint_fast32_t f16_to_ui32( float16_t a, uint_fast8_t roundingMode, bool exact ) +{ + union ui16_f16 uA; + uint_fast16_t uiA; + bool sign; + int_fast8_t exp; + uint_fast16_t frac; + uint_fast32_t sig32; + int_fast8_t shiftDist; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uA.f = a; + uiA = uA.ui; + sign = signF16UI( uiA ); + exp = expF16UI( uiA ); + frac = fracF16UI( uiA ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( exp == 0x1F ) { + softfloat_raiseFlags( softfloat_flag_invalid ); + return + frac ? ui32_fromNaN + : sign ? ui32_fromNegOverflow : ui32_fromPosOverflow; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + sig32 = frac; + if ( exp ) { + sig32 |= 0x0400; + shiftDist = exp - 0x19; + if ( (0 <= shiftDist) && ! sign ) { + return sig32<<shiftDist; + } + shiftDist = exp - 0x0D; + if ( 0 < shiftDist ) sig32 <<= shiftDist; + } + return softfloat_roundToUI32( sign, sig32, roundingMode, exact ); + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f16_to_ui32_r_minMag.c b/vendor/riscv/riscv-isa-sim/softfloat/f16_to_ui32_r_minMag.c new file mode 100644 index 0000000000..f63e05abc6 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f16_to_ui32_r_minMag.c @@ -0,0 +1,87 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +uint_fast32_t f16_to_ui32_r_minMag( float16_t a, bool exact ) +{ + union ui16_f16 uA; + uint_fast16_t uiA; + int_fast8_t exp; + uint_fast16_t frac; + int_fast8_t shiftDist; + bool sign; + uint_fast32_t alignedSig; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uA.f = a; + uiA = uA.ui; + exp = expF16UI( uiA ); + frac = fracF16UI( uiA ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + shiftDist = exp - 0x0F; + if ( shiftDist < 0 ) { + if ( exact && (exp | frac) ) { + softfloat_exceptionFlags |= softfloat_flag_inexact; + } + return 0; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + sign = signF16UI( uiA ); + if ( sign || (exp == 0x1F) ) { + softfloat_raiseFlags( softfloat_flag_invalid ); + return + (exp == 0x1F) && frac ? ui32_fromNaN + : sign ? ui32_fromNegOverflow : ui32_fromPosOverflow; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + alignedSig = (uint_fast32_t) (frac | 0x0400)<<shiftDist; + if ( exact && (alignedSig & 0x3FF) ) { + softfloat_exceptionFlags |= softfloat_flag_inexact; + } + return alignedSig>>10; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f16_to_ui64.c b/vendor/riscv/riscv-isa-sim/softfloat/f16_to_ui64.c new file mode 100644 index 0000000000..dd260eae8b --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f16_to_ui64.c @@ -0,0 +1,84 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the +University of California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +uint_fast64_t f16_to_ui64( float16_t a, uint_fast8_t roundingMode, bool exact ) +{ + union ui16_f16 uA; + uint_fast16_t uiA; + bool sign; + int_fast8_t exp; + uint_fast16_t frac; + uint_fast32_t sig32; + int_fast8_t shiftDist; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uA.f = a; + uiA = uA.ui; + sign = signF16UI( uiA ); + exp = expF16UI( uiA ); + frac = fracF16UI( uiA ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( exp == 0x1F ) { + softfloat_raiseFlags( softfloat_flag_invalid ); + return + frac ? ui64_fromNaN + : sign ? ui64_fromNegOverflow : ui64_fromPosOverflow; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + sig32 = frac; + if ( exp ) { + sig32 |= 0x0400; + shiftDist = exp - 0x19; + if ( (0 <= shiftDist) && ! sign ) { + return sig32<<shiftDist; + } + shiftDist = exp - 0x0D; + if ( 0 < shiftDist ) sig32 <<= shiftDist; + } + return softfloat_roundToUI32( sign, sig32, roundingMode, exact ); + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f16_to_ui64_r_minMag.c b/vendor/riscv/riscv-isa-sim/softfloat/f16_to_ui64_r_minMag.c new file mode 100644 index 0000000000..a57b422928 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f16_to_ui64_r_minMag.c @@ -0,0 +1,87 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +uint_fast64_t f16_to_ui64_r_minMag( float16_t a, bool exact ) +{ + union ui16_f16 uA; + uint_fast16_t uiA; + int_fast8_t exp; + uint_fast16_t frac; + int_fast8_t shiftDist; + bool sign; + uint_fast32_t alignedSig; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uA.f = a; + uiA = uA.ui; + exp = expF16UI( uiA ); + frac = fracF16UI( uiA ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + shiftDist = exp - 0x0F; + if ( shiftDist < 0 ) { + if ( exact && (exp | frac) ) { + softfloat_exceptionFlags |= softfloat_flag_inexact; + } + return 0; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + sign = signF16UI( uiA ); + if ( sign || (exp == 0x1F) ) { + softfloat_raiseFlags( softfloat_flag_invalid ); + return + (exp == 0x1F) && frac ? ui64_fromNaN + : sign ? ui64_fromNegOverflow : ui64_fromPosOverflow; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + alignedSig = (uint_fast32_t) (frac | 0x0400)<<shiftDist; + if ( exact && (alignedSig & 0x3FF) ) { + softfloat_exceptionFlags |= softfloat_flag_inexact; + } + return alignedSig>>10; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f16_to_ui8.c b/vendor/riscv/riscv-isa-sim/softfloat/f16_to_ui8.c new file mode 100644 index 0000000000..96124e1275 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f16_to_ui8.c @@ -0,0 +1,54 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the +University of California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "specialize.h" +#include "softfloat.h" + +uint_fast8_t f16_to_ui8( float16_t a, uint_fast8_t roundingMode, bool exact ) +{ + uint_fast8_t old_flags = softfloat_exceptionFlags; + + uint_fast32_t sig32 = f16_to_ui32(a, roundingMode, exact); + + if (sig32 > UINT8_MAX) { + softfloat_exceptionFlags = old_flags | softfloat_flag_invalid; + return ui8_fromPosOverflow; + } else { + return sig32; + } +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f32_add.c b/vendor/riscv/riscv-isa-sim/softfloat/f32_add.c new file mode 100644 index 0000000000..4a51eccf68 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f32_add.c @@ -0,0 +1,70 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "softfloat.h" + +float32_t f32_add( float32_t a, float32_t b ) +{ + union ui32_f32 uA; + uint_fast32_t uiA; + union ui32_f32 uB; + uint_fast32_t uiB; +#if ! defined INLINE_LEVEL || (INLINE_LEVEL < 1) + float32_t (*magsFuncPtr)( uint_fast32_t, uint_fast32_t ); +#endif + + uA.f = a; + uiA = uA.ui; + uB.f = b; + uiB = uB.ui; +#if defined INLINE_LEVEL && (1 <= INLINE_LEVEL) + if ( signF32UI( uiA ^ uiB ) ) { + return softfloat_subMagsF32( uiA, uiB ); + } else { + return softfloat_addMagsF32( uiA, uiB ); + } +#else + magsFuncPtr = + signF32UI( uiA ^ uiB ) ? softfloat_subMagsF32 : softfloat_addMagsF32; + return (*magsFuncPtr)( uiA, uiB ); +#endif + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f32_classify.c b/vendor/riscv/riscv-isa-sim/softfloat/f32_classify.c new file mode 100755 index 0000000000..83fad878aa --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f32_classify.c @@ -0,0 +1,36 @@ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +uint_fast16_t f32_classify( float32_t a ) +{ + union ui32_f32 uA; + uint_fast32_t uiA; + + uA.f = a; + uiA = uA.ui; + + uint_fast16_t infOrNaN = expF32UI( uiA ) == 0xFF; + uint_fast16_t subnormalOrZero = expF32UI( uiA ) == 0; + bool sign = signF32UI( uiA ); + bool fracZero = fracF32UI( uiA ) == 0; + bool isNaN = isNaNF32UI( uiA ); + bool isSNaN = softfloat_isSigNaNF32UI( uiA ); + + return + ( sign && infOrNaN && fracZero ) << 0 | + ( sign && !infOrNaN && !subnormalOrZero ) << 1 | + ( sign && subnormalOrZero && !fracZero ) << 2 | + ( sign && subnormalOrZero && fracZero ) << 3 | + ( !sign && infOrNaN && fracZero ) << 7 | + ( !sign && !infOrNaN && !subnormalOrZero ) << 6 | + ( !sign && subnormalOrZero && !fracZero ) << 5 | + ( !sign && subnormalOrZero && fracZero ) << 4 | + ( isNaN && isSNaN ) << 8 | + ( isNaN && !isSNaN ) << 9; +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f32_div.c b/vendor/riscv/riscv-isa-sim/softfloat/f32_div.c new file mode 100644 index 0000000000..9d101254b1 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f32_div.c @@ -0,0 +1,180 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +float32_t f32_div( float32_t a, float32_t b ) +{ + union ui32_f32 uA; + uint_fast32_t uiA; + bool signA; + int_fast16_t expA; + uint_fast32_t sigA; + union ui32_f32 uB; + uint_fast32_t uiB; + bool signB; + int_fast16_t expB; + uint_fast32_t sigB; + bool signZ; + struct exp16_sig32 normExpSig; + int_fast16_t expZ; +#ifdef SOFTFLOAT_FAST_DIV64TO32 + uint_fast64_t sig64A; + uint_fast32_t sigZ; +#else + uint_fast32_t sigZ; + uint_fast64_t rem; +#endif + uint_fast32_t uiZ; + union ui32_f32 uZ; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uA.f = a; + uiA = uA.ui; + signA = signF32UI( uiA ); + expA = expF32UI( uiA ); + sigA = fracF32UI( uiA ); + uB.f = b; + uiB = uB.ui; + signB = signF32UI( uiB ); + expB = expF32UI( uiB ); + sigB = fracF32UI( uiB ); + signZ = signA ^ signB; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( expA == 0xFF ) { + if ( sigA ) goto propagateNaN; + if ( expB == 0xFF ) { + if ( sigB ) goto propagateNaN; + goto invalid; + } + goto infinity; + } + if ( expB == 0xFF ) { + if ( sigB ) goto propagateNaN; + goto zero; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( ! expB ) { + if ( ! sigB ) { + if ( ! (expA | sigA) ) goto invalid; + softfloat_raiseFlags( softfloat_flag_infinite ); + goto infinity; + } + normExpSig = softfloat_normSubnormalF32Sig( sigB ); + expB = normExpSig.exp; + sigB = normExpSig.sig; + } + if ( ! expA ) { + if ( ! sigA ) goto zero; + normExpSig = softfloat_normSubnormalF32Sig( sigA ); + expA = normExpSig.exp; + sigA = normExpSig.sig; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + expZ = expA - expB + 0x7E; + sigA |= 0x00800000; + sigB |= 0x00800000; +#ifdef SOFTFLOAT_FAST_DIV64TO32 + if ( sigA < sigB ) { + --expZ; + sig64A = (uint_fast64_t) sigA<<31; + } else { + sig64A = (uint_fast64_t) sigA<<30; + } + sigZ = sig64A / sigB; + if ( ! (sigZ & 0x3F) ) sigZ |= ((uint_fast64_t) sigB * sigZ != sig64A); +#else + if ( sigA < sigB ) { + --expZ; + sigA <<= 8; + } else { + sigA <<= 7; + } + sigB <<= 8; + sigZ = ((uint_fast64_t) sigA * softfloat_approxRecip32_1( sigB ))>>32; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + sigZ += 2; + if ( (sigZ & 0x3F) < 2 ) { + sigZ &= ~3; +#ifdef SOFTFLOAT_FAST_INT64 + rem = ((uint_fast64_t) sigA<<31) - (uint_fast64_t) sigZ * sigB; +#else + rem = ((uint_fast64_t) sigA<<32) - (uint_fast64_t) (sigZ<<1) * sigB; +#endif + if ( rem & UINT64_C( 0x8000000000000000 ) ) { + sigZ -= 4; + } else { + if ( rem ) sigZ |= 1; + } + } +#endif + return softfloat_roundPackToF32( signZ, expZ, sigZ ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + propagateNaN: + uiZ = softfloat_propagateNaNF32UI( uiA, uiB ); + goto uiZ; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + invalid: + softfloat_raiseFlags( softfloat_flag_invalid ); + uiZ = defaultNaNF32UI; + goto uiZ; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + infinity: + uiZ = packToF32UI( signZ, 0xFF, 0 ); + goto uiZ; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + zero: + uiZ = packToF32UI( signZ, 0, 0 ); + uiZ: + uZ.ui = uiZ; + return uZ.f; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f32_eq.c b/vendor/riscv/riscv-isa-sim/softfloat/f32_eq.c new file mode 100644 index 0000000000..5f07eee300 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f32_eq.c @@ -0,0 +1,66 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +bool f32_eq( float32_t a, float32_t b ) +{ + union ui32_f32 uA; + uint_fast32_t uiA; + union ui32_f32 uB; + uint_fast32_t uiB; + + uA.f = a; + uiA = uA.ui; + uB.f = b; + uiB = uB.ui; + if ( isNaNF32UI( uiA ) || isNaNF32UI( uiB ) ) { + if ( + softfloat_isSigNaNF32UI( uiA ) || softfloat_isSigNaNF32UI( uiB ) + ) { + softfloat_raiseFlags( softfloat_flag_invalid ); + } + return false; + } + return (uiA == uiB) || ! (uint32_t) ((uiA | uiB)<<1); + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f32_eq_signaling.c b/vendor/riscv/riscv-isa-sim/softfloat/f32_eq_signaling.c new file mode 100644 index 0000000000..f5fcc8242c --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f32_eq_signaling.c @@ -0,0 +1,61 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "softfloat.h" + +bool f32_eq_signaling( float32_t a, float32_t b ) +{ + union ui32_f32 uA; + uint_fast32_t uiA; + union ui32_f32 uB; + uint_fast32_t uiB; + + uA.f = a; + uiA = uA.ui; + uB.f = b; + uiB = uB.ui; + if ( isNaNF32UI( uiA ) || isNaNF32UI( uiB ) ) { + softfloat_raiseFlags( softfloat_flag_invalid ); + return false; + } + return (uiA == uiB) || ! (uint32_t) ((uiA | uiB)<<1); + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f32_isSignalingNaN.c b/vendor/riscv/riscv-isa-sim/softfloat/f32_isSignalingNaN.c new file mode 100644 index 0000000000..5004a5aae4 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f32_isSignalingNaN.c @@ -0,0 +1,51 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +bool f32_isSignalingNaN( float32_t a ) +{ + union ui32_f32 uA; + + uA.f = a; + return softfloat_isSigNaNF32UI( uA.ui ); + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f32_le.c b/vendor/riscv/riscv-isa-sim/softfloat/f32_le.c new file mode 100644 index 0000000000..77595fbbcf --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f32_le.c @@ -0,0 +1,66 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "softfloat.h" + +bool f32_le( float32_t a, float32_t b ) +{ + union ui32_f32 uA; + uint_fast32_t uiA; + union ui32_f32 uB; + uint_fast32_t uiB; + bool signA, signB; + + uA.f = a; + uiA = uA.ui; + uB.f = b; + uiB = uB.ui; + if ( isNaNF32UI( uiA ) || isNaNF32UI( uiB ) ) { + softfloat_raiseFlags( softfloat_flag_invalid ); + return false; + } + signA = signF32UI( uiA ); + signB = signF32UI( uiB ); + return + (signA != signB) ? signA || ! (uint32_t) ((uiA | uiB)<<1) + : (uiA == uiB) || (signA ^ (uiA < uiB)); + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f32_le_quiet.c b/vendor/riscv/riscv-isa-sim/softfloat/f32_le_quiet.c new file mode 100644 index 0000000000..1ec9101070 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f32_le_quiet.c @@ -0,0 +1,71 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +bool f32_le_quiet( float32_t a, float32_t b ) +{ + union ui32_f32 uA; + uint_fast32_t uiA; + union ui32_f32 uB; + uint_fast32_t uiB; + bool signA, signB; + + uA.f = a; + uiA = uA.ui; + uB.f = b; + uiB = uB.ui; + if ( isNaNF32UI( uiA ) || isNaNF32UI( uiB ) ) { + if ( + softfloat_isSigNaNF32UI( uiA ) || softfloat_isSigNaNF32UI( uiB ) + ) { + softfloat_raiseFlags( softfloat_flag_invalid ); + } + return false; + } + signA = signF32UI( uiA ); + signB = signF32UI( uiB ); + return + (signA != signB) ? signA || ! (uint32_t) ((uiA | uiB)<<1) + : (uiA == uiB) || (signA ^ (uiA < uiB)); + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f32_lt.c b/vendor/riscv/riscv-isa-sim/softfloat/f32_lt.c new file mode 100644 index 0000000000..9e12843fbd --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f32_lt.c @@ -0,0 +1,66 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "softfloat.h" + +bool f32_lt( float32_t a, float32_t b ) +{ + union ui32_f32 uA; + uint_fast32_t uiA; + union ui32_f32 uB; + uint_fast32_t uiB; + bool signA, signB; + + uA.f = a; + uiA = uA.ui; + uB.f = b; + uiB = uB.ui; + if ( isNaNF32UI( uiA ) || isNaNF32UI( uiB ) ) { + softfloat_raiseFlags( softfloat_flag_invalid ); + return false; + } + signA = signF32UI( uiA ); + signB = signF32UI( uiB ); + return + (signA != signB) ? signA && ((uint32_t) ((uiA | uiB)<<1) != 0) + : (uiA != uiB) && (signA ^ (uiA < uiB)); + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f32_lt_quiet.c b/vendor/riscv/riscv-isa-sim/softfloat/f32_lt_quiet.c new file mode 100644 index 0000000000..9f83b81056 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f32_lt_quiet.c @@ -0,0 +1,71 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +bool f32_lt_quiet( float32_t a, float32_t b ) +{ + union ui32_f32 uA; + uint_fast32_t uiA; + union ui32_f32 uB; + uint_fast32_t uiB; + bool signA, signB; + + uA.f = a; + uiA = uA.ui; + uB.f = b; + uiB = uB.ui; + if ( isNaNF32UI( uiA ) || isNaNF32UI( uiB ) ) { + if ( + softfloat_isSigNaNF32UI( uiA ) || softfloat_isSigNaNF32UI( uiB ) + ) { + softfloat_raiseFlags( softfloat_flag_invalid ); + } + return false; + } + signA = signF32UI( uiA ); + signB = signF32UI( uiB ); + return + (signA != signB) ? signA && ((uint32_t) ((uiA | uiB)<<1) != 0) + : (uiA != uiB) && (signA ^ (uiA < uiB)); + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f32_mul.c b/vendor/riscv/riscv-isa-sim/softfloat/f32_mul.c new file mode 100644 index 0000000000..a2a673f1c0 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f32_mul.c @@ -0,0 +1,137 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +float32_t f32_mul( float32_t a, float32_t b ) +{ + union ui32_f32 uA; + uint_fast32_t uiA; + bool signA; + int_fast16_t expA; + uint_fast32_t sigA; + union ui32_f32 uB; + uint_fast32_t uiB; + bool signB; + int_fast16_t expB; + uint_fast32_t sigB; + bool signZ; + uint_fast32_t magBits; + struct exp16_sig32 normExpSig; + int_fast16_t expZ; + uint_fast32_t sigZ, uiZ; + union ui32_f32 uZ; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uA.f = a; + uiA = uA.ui; + signA = signF32UI( uiA ); + expA = expF32UI( uiA ); + sigA = fracF32UI( uiA ); + uB.f = b; + uiB = uB.ui; + signB = signF32UI( uiB ); + expB = expF32UI( uiB ); + sigB = fracF32UI( uiB ); + signZ = signA ^ signB; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( expA == 0xFF ) { + if ( sigA || ((expB == 0xFF) && sigB) ) goto propagateNaN; + magBits = expB | sigB; + goto infArg; + } + if ( expB == 0xFF ) { + if ( sigB ) goto propagateNaN; + magBits = expA | sigA; + goto infArg; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( ! expA ) { + if ( ! sigA ) goto zero; + normExpSig = softfloat_normSubnormalF32Sig( sigA ); + expA = normExpSig.exp; + sigA = normExpSig.sig; + } + if ( ! expB ) { + if ( ! sigB ) goto zero; + normExpSig = softfloat_normSubnormalF32Sig( sigB ); + expB = normExpSig.exp; + sigB = normExpSig.sig; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + expZ = expA + expB - 0x7F; + sigA = (sigA | 0x00800000)<<7; + sigB = (sigB | 0x00800000)<<8; + sigZ = softfloat_shortShiftRightJam64( (uint_fast64_t) sigA * sigB, 32 ); + if ( sigZ < 0x40000000 ) { + --expZ; + sigZ <<= 1; + } + return softfloat_roundPackToF32( signZ, expZ, sigZ ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + propagateNaN: + uiZ = softfloat_propagateNaNF32UI( uiA, uiB ); + goto uiZ; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + infArg: + if ( ! magBits ) { + softfloat_raiseFlags( softfloat_flag_invalid ); + uiZ = defaultNaNF32UI; + } else { + uiZ = packToF32UI( signZ, 0xFF, 0 ); + } + goto uiZ; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + zero: + uiZ = packToF32UI( signZ, 0, 0 ); + uiZ: + uZ.ui = uiZ; + return uZ.f; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f32_mulAdd.c b/vendor/riscv/riscv-isa-sim/softfloat/f32_mulAdd.c new file mode 100644 index 0000000000..e98021b75b --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f32_mulAdd.c @@ -0,0 +1,60 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "softfloat.h" + +float32_t f32_mulAdd( float32_t a, float32_t b, float32_t c ) +{ + union ui32_f32 uA; + uint_fast32_t uiA; + union ui32_f32 uB; + uint_fast32_t uiB; + union ui32_f32 uC; + uint_fast32_t uiC; + + uA.f = a; + uiA = uA.ui; + uB.f = b; + uiB = uB.ui; + uC.f = c; + uiC = uC.ui; + return softfloat_mulAddF32( uiA, uiB, uiC, 0 ); + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f32_rem.c b/vendor/riscv/riscv-isa-sim/softfloat/f32_rem.c new file mode 100644 index 0000000000..771b1b94cb --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f32_rem.c @@ -0,0 +1,168 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +float32_t f32_rem( float32_t a, float32_t b ) +{ + union ui32_f32 uA; + uint_fast32_t uiA; + bool signA; + int_fast16_t expA; + uint_fast32_t sigA; + union ui32_f32 uB; + uint_fast32_t uiB; + int_fast16_t expB; + uint_fast32_t sigB; + struct exp16_sig32 normExpSig; + uint32_t rem; + int_fast16_t expDiff; + uint32_t q, recip32, altRem, meanRem; + bool signRem; + uint_fast32_t uiZ; + union ui32_f32 uZ; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uA.f = a; + uiA = uA.ui; + signA = signF32UI( uiA ); + expA = expF32UI( uiA ); + sigA = fracF32UI( uiA ); + uB.f = b; + uiB = uB.ui; + expB = expF32UI( uiB ); + sigB = fracF32UI( uiB ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( expA == 0xFF ) { + if ( sigA || ((expB == 0xFF) && sigB) ) goto propagateNaN; + goto invalid; + } + if ( expB == 0xFF ) { + if ( sigB ) goto propagateNaN; + return a; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( ! expB ) { + if ( ! sigB ) goto invalid; + normExpSig = softfloat_normSubnormalF32Sig( sigB ); + expB = normExpSig.exp; + sigB = normExpSig.sig; + } + if ( ! expA ) { + if ( ! sigA ) return a; + normExpSig = softfloat_normSubnormalF32Sig( sigA ); + expA = normExpSig.exp; + sigA = normExpSig.sig; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + rem = sigA | 0x00800000; + sigB |= 0x00800000; + expDiff = expA - expB; + if ( expDiff < 1 ) { + if ( expDiff < -1 ) return a; + sigB <<= 6; + if ( expDiff ) { + rem <<= 5; + q = 0; + } else { + rem <<= 6; + q = (sigB <= rem); + if ( q ) rem -= sigB; + } + } else { + recip32 = softfloat_approxRecip32_1( sigB<<8 ); + /*-------------------------------------------------------------------- + | Changing the shift of `rem' here requires also changing the initial + | subtraction from `expDiff'. + *--------------------------------------------------------------------*/ + rem <<= 7; + expDiff -= 31; + /*-------------------------------------------------------------------- + | The scale of `sigB' affects how many bits are obtained during each + | cycle of the loop. Currently this is 29 bits per loop iteration, + | which is believed to be the maximum possible. + *--------------------------------------------------------------------*/ + sigB <<= 6; + for (;;) { + q = (rem * (uint_fast64_t) recip32)>>32; + if ( expDiff < 0 ) break; + rem = -(q * (uint32_t) sigB); + expDiff -= 29; + } + /*-------------------------------------------------------------------- + | (`expDiff' cannot be less than -30 here.) + *--------------------------------------------------------------------*/ + q >>= ~expDiff & 31; + rem = (rem<<(expDiff + 30)) - q * (uint32_t) sigB; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + do { + altRem = rem; + ++q; + rem -= sigB; + } while ( ! (rem & 0x80000000) ); + meanRem = rem + altRem; + if ( (meanRem & 0x80000000) || (! meanRem && (q & 1)) ) rem = altRem; + signRem = signA; + if ( 0x80000000 <= rem ) { + signRem = ! signRem; + rem = -rem; + } + return softfloat_normRoundPackToF32( signRem, expB, rem ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + propagateNaN: + uiZ = softfloat_propagateNaNF32UI( uiA, uiB ); + goto uiZ; + invalid: + softfloat_raiseFlags( softfloat_flag_invalid ); + uiZ = defaultNaNF32UI; + uiZ: + uZ.ui = uiZ; + return uZ.f; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f32_roundToInt.c b/vendor/riscv/riscv-isa-sim/softfloat/f32_roundToInt.c new file mode 100644 index 0000000000..0861b84054 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f32_roundToInt.c @@ -0,0 +1,112 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +float32_t f32_roundToInt( float32_t a, uint_fast8_t roundingMode, bool exact ) +{ + union ui32_f32 uA; + uint_fast32_t uiA; + int_fast16_t exp; + uint_fast32_t uiZ, lastBitMask, roundBitsMask; + union ui32_f32 uZ; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uA.f = a; + uiA = uA.ui; + exp = expF32UI( uiA ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( exp <= 0x7E ) { + if ( ! (uint32_t) (uiA<<1) ) return a; + if ( exact ) softfloat_exceptionFlags |= softfloat_flag_inexact; + uiZ = uiA & packToF32UI( 1, 0, 0 ); + switch ( roundingMode ) { + case softfloat_round_near_even: + if ( ! fracF32UI( uiA ) ) break; + case softfloat_round_near_maxMag: + if ( exp == 0x7E ) uiZ |= packToF32UI( 0, 0x7F, 0 ); + break; + case softfloat_round_min: + if ( uiZ ) uiZ = packToF32UI( 1, 0x7F, 0 ); + break; + case softfloat_round_max: + if ( ! uiZ ) uiZ = packToF32UI( 0, 0x7F, 0 ); + break; + } + goto uiZ; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( 0x96 <= exp ) { + if ( (exp == 0xFF) && fracF32UI( uiA ) ) { + uiZ = softfloat_propagateNaNF32UI( uiA, 0 ); + goto uiZ; + } + return a; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uiZ = uiA; + lastBitMask = (uint_fast32_t) 1<<(0x96 - exp); + roundBitsMask = lastBitMask - 1; + if ( roundingMode == softfloat_round_near_maxMag ) { + uiZ += lastBitMask>>1; + } else if ( roundingMode == softfloat_round_near_even ) { + uiZ += lastBitMask>>1; + if ( ! (uiZ & roundBitsMask) ) uiZ &= ~lastBitMask; + } else if ( + roundingMode + == (signF32UI( uiZ ) ? softfloat_round_min : softfloat_round_max) + ) { + uiZ += roundBitsMask; + } + uiZ &= ~roundBitsMask; + if ( exact && (uiZ != uiA) ) { + softfloat_exceptionFlags |= softfloat_flag_inexact; + } + uiZ: + uZ.ui = uiZ; + return uZ.f; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f32_sqrt.c b/vendor/riscv/riscv-isa-sim/softfloat/f32_sqrt.c new file mode 100644 index 0000000000..5ef659e4f2 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f32_sqrt.c @@ -0,0 +1,121 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +float32_t f32_sqrt( float32_t a ) +{ + union ui32_f32 uA; + uint_fast32_t uiA; + bool signA; + int_fast16_t expA; + uint_fast32_t sigA, uiZ; + struct exp16_sig32 normExpSig; + int_fast16_t expZ; + uint_fast32_t sigZ, shiftedSigZ; + uint32_t negRem; + union ui32_f32 uZ; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uA.f = a; + uiA = uA.ui; + signA = signF32UI( uiA ); + expA = expF32UI( uiA ); + sigA = fracF32UI( uiA ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( expA == 0xFF ) { + if ( sigA ) { + uiZ = softfloat_propagateNaNF32UI( uiA, 0 ); + goto uiZ; + } + if ( ! signA ) return a; + goto invalid; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( signA ) { + if ( ! (expA | sigA) ) return a; + goto invalid; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( ! expA ) { + if ( ! sigA ) return a; + normExpSig = softfloat_normSubnormalF32Sig( sigA ); + expA = normExpSig.exp; + sigA = normExpSig.sig; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + expZ = ((expA - 0x7F)>>1) + 0x7E; + expA &= 1; + sigA = (sigA | 0x00800000)<<8; + sigZ = + ((uint_fast64_t) sigA * softfloat_approxRecipSqrt32_1( expA, sigA )) + >>32; + if ( expA ) sigZ >>= 1; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + sigZ += 2; + if ( (sigZ & 0x3F) < 2 ) { + shiftedSigZ = sigZ>>2; + negRem = shiftedSigZ * shiftedSigZ; + sigZ &= ~3; + if ( negRem & 0x80000000 ) { + sigZ |= 1; + } else { + if ( negRem ) --sigZ; + } + } + return softfloat_roundPackToF32( 0, expZ, sigZ ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + invalid: + softfloat_raiseFlags( softfloat_flag_invalid ); + uiZ = defaultNaNF32UI; + uiZ: + uZ.ui = uiZ; + return uZ.f; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f32_sub.c b/vendor/riscv/riscv-isa-sim/softfloat/f32_sub.c new file mode 100644 index 0000000000..d8307381da --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f32_sub.c @@ -0,0 +1,70 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "softfloat.h" + +float32_t f32_sub( float32_t a, float32_t b ) +{ + union ui32_f32 uA; + uint_fast32_t uiA; + union ui32_f32 uB; + uint_fast32_t uiB; +#if ! defined INLINE_LEVEL || (INLINE_LEVEL < 1) + float32_t (*magsFuncPtr)( uint_fast32_t, uint_fast32_t ); +#endif + + uA.f = a; + uiA = uA.ui; + uB.f = b; + uiB = uB.ui; +#if defined INLINE_LEVEL && (1 <= INLINE_LEVEL) + if ( signF32UI( uiA ^ uiB ) ) { + return softfloat_addMagsF32( uiA, uiB ); + } else { + return softfloat_subMagsF32( uiA, uiB ); + } +#else + magsFuncPtr = + signF32UI( uiA ^ uiB ) ? softfloat_addMagsF32 : softfloat_subMagsF32; + return (*magsFuncPtr)( uiA, uiB ); +#endif + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f32_to_f128.c b/vendor/riscv/riscv-isa-sim/softfloat/f32_to_f128.c new file mode 100644 index 0000000000..bf51926461 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f32_to_f128.c @@ -0,0 +1,96 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +float128_t f32_to_f128( float32_t a ) +{ + union ui32_f32 uA; + uint_fast32_t uiA; + bool sign; + int_fast16_t exp; + uint_fast32_t frac; + struct commonNaN commonNaN; + struct uint128 uiZ; + struct exp16_sig32 normExpSig; + union ui128_f128 uZ; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uA.f = a; + uiA = uA.ui; + sign = signF32UI( uiA ); + exp = expF32UI( uiA ); + frac = fracF32UI( uiA ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( exp == 0xFF ) { + if ( frac ) { + softfloat_f32UIToCommonNaN( uiA, &commonNaN ); + uiZ = softfloat_commonNaNToF128UI( &commonNaN ); + } else { + uiZ.v64 = packToF128UI64( sign, 0x7FFF, 0 ); + uiZ.v0 = 0; + } + goto uiZ; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( ! exp ) { + if ( ! frac ) { + uiZ.v64 = packToF128UI64( sign, 0, 0 ); + uiZ.v0 = 0; + goto uiZ; + } + normExpSig = softfloat_normSubnormalF32Sig( frac ); + exp = normExpSig.exp - 1; + frac = normExpSig.sig; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uiZ.v64 = packToF128UI64( sign, exp + 0x3F80, (uint_fast64_t) frac<<25 ); + uiZ.v0 = 0; + uiZ: + uZ.ui = uiZ; + return uZ.f; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f32_to_f16.c b/vendor/riscv/riscv-isa-sim/softfloat/f32_to_f16.c new file mode 100644 index 0000000000..7a97158995 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f32_to_f16.c @@ -0,0 +1,88 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +float16_t f32_to_f16( float32_t a ) +{ + union ui32_f32 uA; + uint_fast32_t uiA; + bool sign; + int_fast16_t exp; + uint_fast32_t frac; + struct commonNaN commonNaN; + uint_fast16_t uiZ, frac16; + union ui16_f16 uZ; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uA.f = a; + uiA = uA.ui; + sign = signF32UI( uiA ); + exp = expF32UI( uiA ); + frac = fracF32UI( uiA ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( exp == 0xFF ) { + if ( frac ) { + softfloat_f32UIToCommonNaN( uiA, &commonNaN ); + uiZ = softfloat_commonNaNToF16UI( &commonNaN ); + } else { + uiZ = packToF16UI( sign, 0x1F, 0 ); + } + goto uiZ; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + frac16 = frac>>9 | ((frac & 0x1FF) != 0); + if ( ! (exp | frac16) ) { + uiZ = packToF16UI( sign, 0, 0 ); + goto uiZ; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + return softfloat_roundPackToF16( sign, exp - 0x71, frac16 | 0x4000 ); + uiZ: + uZ.ui = uiZ; + return uZ.f; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f32_to_f64.c b/vendor/riscv/riscv-isa-sim/softfloat/f32_to_f64.c new file mode 100644 index 0000000000..f9e02f2277 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f32_to_f64.c @@ -0,0 +1,93 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +float64_t f32_to_f64( float32_t a ) +{ + union ui32_f32 uA; + uint_fast32_t uiA; + bool sign; + int_fast16_t exp; + uint_fast32_t frac; + struct commonNaN commonNaN; + uint_fast64_t uiZ; + struct exp16_sig32 normExpSig; + union ui64_f64 uZ; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uA.f = a; + uiA = uA.ui; + sign = signF32UI( uiA ); + exp = expF32UI( uiA ); + frac = fracF32UI( uiA ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( exp == 0xFF ) { + if ( frac ) { + softfloat_f32UIToCommonNaN( uiA, &commonNaN ); + uiZ = softfloat_commonNaNToF64UI( &commonNaN ); + } else { + uiZ = packToF64UI( sign, 0x7FF, 0 ); + } + goto uiZ; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( ! exp ) { + if ( ! frac ) { + uiZ = packToF64UI( sign, 0, 0 ); + goto uiZ; + } + normExpSig = softfloat_normSubnormalF32Sig( frac ); + exp = normExpSig.exp - 1; + frac = normExpSig.sig; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uiZ = packToF64UI( sign, exp + 0x380, (uint_fast64_t) frac<<29 ); + uiZ: + uZ.ui = uiZ; + return uZ.f; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f32_to_i16.c b/vendor/riscv/riscv-isa-sim/softfloat/f32_to_i16.c new file mode 100644 index 0000000000..bde4c76c9a --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f32_to_i16.c @@ -0,0 +1,57 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the +University of California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "specialize.h" +#include "softfloat.h" + +int_fast16_t f32_to_i16( float32_t a, uint_fast8_t roundingMode, bool exact ) +{ + uint_fast8_t old_flags = softfloat_exceptionFlags; + + int_fast32_t sig32 = f32_to_i32(a, roundingMode, exact); + + if (sig32 > INT16_MAX) { + softfloat_exceptionFlags = old_flags | softfloat_flag_invalid; + return i16_fromPosOverflow; + } else if (sig32 < INT16_MIN) { + softfloat_exceptionFlags = old_flags | softfloat_flag_invalid; + return i16_fromNegOverflow; + } else { + return sig32; + } +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f32_to_i32.c b/vendor/riscv/riscv-isa-sim/softfloat/f32_to_i32.c new file mode 100644 index 0000000000..c9f2cf9b39 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f32_to_i32.c @@ -0,0 +1,84 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the +University of California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +int_fast32_t f32_to_i32( float32_t a, uint_fast8_t roundingMode, bool exact ) +{ + union ui32_f32 uA; + uint_fast32_t uiA; + bool sign; + int_fast16_t exp; + uint_fast32_t sig; + uint_fast64_t sig64; + int_fast16_t shiftDist; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uA.f = a; + uiA = uA.ui; + sign = signF32UI( uiA ); + exp = expF32UI( uiA ); + sig = fracF32UI( uiA ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ +#if (i32_fromNaN != i32_fromPosOverflow) || (i32_fromNaN != i32_fromNegOverflow) + if ( (exp == 0xFF) && sig ) { +#if (i32_fromNaN == i32_fromPosOverflow) + sign = 0; +#elif (i32_fromNaN == i32_fromNegOverflow) + sign = 1; +#else + softfloat_raiseFlags( softfloat_flag_invalid ); + return i32_fromNaN; +#endif + } +#endif + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( exp ) sig |= 0x00800000; + sig64 = (uint_fast64_t) sig<<32; + shiftDist = 0xAA - exp; + if ( 0 < shiftDist ) sig64 = softfloat_shiftRightJam64( sig64, shiftDist ); + return softfloat_roundToI32( sign, sig64, roundingMode, exact ); + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f32_to_i32_r_minMag.c b/vendor/riscv/riscv-isa-sim/softfloat/f32_to_i32_r_minMag.c new file mode 100644 index 0000000000..1a94dcc680 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f32_to_i32_r_minMag.c @@ -0,0 +1,89 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +int_fast32_t f32_to_i32_r_minMag( float32_t a, bool exact ) +{ + union ui32_f32 uA; + uint_fast32_t uiA; + int_fast16_t exp; + uint_fast32_t sig; + int_fast16_t shiftDist; + bool sign; + int_fast32_t absZ; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uA.f = a; + uiA = uA.ui; + exp = expF32UI( uiA ); + sig = fracF32UI( uiA ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + shiftDist = 0x9E - exp; + if ( 32 <= shiftDist ) { + if ( exact && (exp | sig) ) { + softfloat_exceptionFlags |= softfloat_flag_inexact; + } + return 0; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + sign = signF32UI( uiA ); + if ( shiftDist <= 0 ) { + if ( uiA == packToF32UI( 1, 0x9E, 0 ) ) return -0x7FFFFFFF - 1; + softfloat_raiseFlags( softfloat_flag_invalid ); + return + (exp == 0xFF) && sig ? i32_fromNaN + : sign ? i32_fromNegOverflow : i32_fromPosOverflow; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + sig = (sig | 0x00800000)<<8; + absZ = sig>>shiftDist; + if ( exact && ((uint_fast32_t) absZ<<shiftDist != sig) ) { + softfloat_exceptionFlags |= softfloat_flag_inexact; + } + return sign ? -absZ : absZ; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f32_to_i64.c b/vendor/riscv/riscv-isa-sim/softfloat/f32_to_i64.c new file mode 100644 index 0000000000..48ab46fd9a --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f32_to_i64.c @@ -0,0 +1,96 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the +University of California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +int_fast64_t f32_to_i64( float32_t a, uint_fast8_t roundingMode, bool exact ) +{ + union ui32_f32 uA; + uint_fast32_t uiA; + bool sign; + int_fast16_t exp; + uint_fast32_t sig; + int_fast16_t shiftDist; +#ifdef SOFTFLOAT_FAST_INT64 + uint_fast64_t sig64, extra; + struct uint64_extra sig64Extra; +#else + uint32_t extSig[3]; +#endif + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uA.f = a; + uiA = uA.ui; + sign = signF32UI( uiA ); + exp = expF32UI( uiA ); + sig = fracF32UI( uiA ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + shiftDist = 0xBE - exp; + if ( shiftDist < 0 ) { + softfloat_raiseFlags( softfloat_flag_invalid ); + return + (exp == 0xFF) && sig ? i64_fromNaN + : sign ? i64_fromNegOverflow : i64_fromPosOverflow; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( exp ) sig |= 0x00800000; +#ifdef SOFTFLOAT_FAST_INT64 + sig64 = (uint_fast64_t) sig<<40; + extra = 0; + if ( shiftDist ) { + sig64Extra = softfloat_shiftRightJam64Extra( sig64, 0, shiftDist ); + sig64 = sig64Extra.v; + extra = sig64Extra.extra; + } + return softfloat_roundToI64( sign, sig64, extra, roundingMode, exact ); +#else + extSig[indexWord( 3, 2 )] = sig<<8; + extSig[indexWord( 3, 1 )] = 0; + extSig[indexWord( 3, 0 )] = 0; + if ( shiftDist ) softfloat_shiftRightJam96M( extSig, shiftDist, extSig ); + return softfloat_roundMToI64( sign, extSig, roundingMode, exact ); +#endif + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f32_to_i64_r_minMag.c b/vendor/riscv/riscv-isa-sim/softfloat/f32_to_i64_r_minMag.c new file mode 100644 index 0000000000..7d336a47bf --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f32_to_i64_r_minMag.c @@ -0,0 +1,94 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +int_fast64_t f32_to_i64_r_minMag( float32_t a, bool exact ) +{ + union ui32_f32 uA; + uint_fast32_t uiA; + int_fast16_t exp; + uint_fast32_t sig; + int_fast16_t shiftDist; + bool sign; + uint_fast64_t sig64; + int_fast64_t absZ; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uA.f = a; + uiA = uA.ui; + exp = expF32UI( uiA ); + sig = fracF32UI( uiA ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + shiftDist = 0xBE - exp; + if ( 64 <= shiftDist ) { + if ( exact && (exp | sig) ) { + softfloat_exceptionFlags |= softfloat_flag_inexact; + } + return 0; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + sign = signF32UI( uiA ); + if ( shiftDist <= 0 ) { + if ( uiA == packToF32UI( 1, 0xBE, 0 ) ) { + return -INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1; + } + softfloat_raiseFlags( softfloat_flag_invalid ); + return + (exp == 0xFF) && sig ? i64_fromNaN + : sign ? i64_fromNegOverflow : i64_fromPosOverflow; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + sig |= 0x00800000; + sig64 = (uint_fast64_t) sig<<40; + absZ = sig64>>shiftDist; + shiftDist = 40 - shiftDist; + if ( exact && (shiftDist < 0) && (uint32_t) (sig<<(shiftDist & 31)) ) { + softfloat_exceptionFlags |= softfloat_flag_inexact; + } + return sign ? -absZ : absZ; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f32_to_ui16.c b/vendor/riscv/riscv-isa-sim/softfloat/f32_to_ui16.c new file mode 100644 index 0000000000..073492bfaa --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f32_to_ui16.c @@ -0,0 +1,53 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the +University of California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "specialize.h" +#include "softfloat.h" + +uint_fast16_t f32_to_ui16( float32_t a, uint_fast8_t roundingMode, bool exact ) +{ + uint_fast8_t old_flags = softfloat_exceptionFlags; + + uint_fast32_t sig32 = f32_to_ui32(a, roundingMode, exact); + + if (sig32 > UINT16_MAX) { + softfloat_exceptionFlags = old_flags | softfloat_flag_invalid; + return ui16_fromPosOverflow; + } else { + return sig32; + } +} diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f32_to_ui32.c b/vendor/riscv/riscv-isa-sim/softfloat/f32_to_ui32.c new file mode 100644 index 0000000000..5ec279ba64 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f32_to_ui32.c @@ -0,0 +1,84 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the +University of California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +uint_fast32_t f32_to_ui32( float32_t a, uint_fast8_t roundingMode, bool exact ) +{ + union ui32_f32 uA; + uint_fast32_t uiA; + bool sign; + int_fast16_t exp; + uint_fast32_t sig; + uint_fast64_t sig64; + int_fast16_t shiftDist; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uA.f = a; + uiA = uA.ui; + sign = signF32UI( uiA ); + exp = expF32UI( uiA ); + sig = fracF32UI( uiA ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ +#if (ui32_fromNaN != ui32_fromPosOverflow) || (ui32_fromNaN != ui32_fromNegOverflow) + if ( (exp == 0xFF) && sig ) { +#if (ui32_fromNaN == ui32_fromPosOverflow) + sign = 0; +#elif (ui32_fromNaN == ui32_fromNegOverflow) + sign = 1; +#else + softfloat_raiseFlags( softfloat_flag_invalid ); + return ui32_fromNaN; +#endif + } +#endif + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( exp ) sig |= 0x00800000; + sig64 = (uint_fast64_t) sig<<32; + shiftDist = 0xAA - exp; + if ( 0 < shiftDist ) sig64 = softfloat_shiftRightJam64( sig64, shiftDist ); + return softfloat_roundToUI32( sign, sig64, roundingMode, exact ); + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f32_to_ui32_r_minMag.c b/vendor/riscv/riscv-isa-sim/softfloat/f32_to_ui32_r_minMag.c new file mode 100644 index 0000000000..12f72619bf --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f32_to_ui32_r_minMag.c @@ -0,0 +1,88 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +uint_fast32_t f32_to_ui32_r_minMag( float32_t a, bool exact ) +{ + union ui32_f32 uA; + uint_fast32_t uiA; + int_fast16_t exp; + uint_fast32_t sig; + int_fast16_t shiftDist; + bool sign; + uint_fast32_t z; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uA.f = a; + uiA = uA.ui; + exp = expF32UI( uiA ); + sig = fracF32UI( uiA ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + shiftDist = 0x9E - exp; + if ( 32 <= shiftDist ) { + if ( exact && (exp | sig) ) { + softfloat_exceptionFlags |= softfloat_flag_inexact; + } + return 0; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + sign = signF32UI( uiA ); + if ( sign || (shiftDist < 0) ) { + softfloat_raiseFlags( softfloat_flag_invalid ); + return + (exp == 0xFF) && sig ? ui32_fromNaN + : sign ? ui32_fromNegOverflow : ui32_fromPosOverflow; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + sig = (sig | 0x00800000)<<8; + z = sig>>shiftDist; + if ( exact && (z<<shiftDist != sig) ) { + softfloat_exceptionFlags |= softfloat_flag_inexact; + } + return z; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f32_to_ui64.c b/vendor/riscv/riscv-isa-sim/softfloat/f32_to_ui64.c new file mode 100644 index 0000000000..11c7b4b67d --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f32_to_ui64.c @@ -0,0 +1,96 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the +University of California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +uint_fast64_t f32_to_ui64( float32_t a, uint_fast8_t roundingMode, bool exact ) +{ + union ui32_f32 uA; + uint_fast32_t uiA; + bool sign; + int_fast16_t exp; + uint_fast32_t sig; + int_fast16_t shiftDist; +#ifdef SOFTFLOAT_FAST_INT64 + uint_fast64_t sig64, extra; + struct uint64_extra sig64Extra; +#else + uint32_t extSig[3]; +#endif + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uA.f = a; + uiA = uA.ui; + sign = signF32UI( uiA ); + exp = expF32UI( uiA ); + sig = fracF32UI( uiA ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + shiftDist = 0xBE - exp; + if ( shiftDist < 0 ) { + softfloat_raiseFlags( softfloat_flag_invalid ); + return + (exp == 0xFF) && sig ? ui64_fromNaN + : sign ? ui64_fromNegOverflow : ui64_fromPosOverflow; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( exp ) sig |= 0x00800000; +#ifdef SOFTFLOAT_FAST_INT64 + sig64 = (uint_fast64_t) sig<<40; + extra = 0; + if ( shiftDist ) { + sig64Extra = softfloat_shiftRightJam64Extra( sig64, 0, shiftDist ); + sig64 = sig64Extra.v; + extra = sig64Extra.extra; + } + return softfloat_roundToUI64( sign, sig64, extra, roundingMode, exact ); +#else + extSig[indexWord( 3, 2 )] = sig<<8; + extSig[indexWord( 3, 1 )] = 0; + extSig[indexWord( 3, 0 )] = 0; + if ( shiftDist ) softfloat_shiftRightJam96M( extSig, shiftDist, extSig ); + return softfloat_roundMToUI64( sign, extSig, roundingMode, exact ); +#endif + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f32_to_ui64_r_minMag.c b/vendor/riscv/riscv-isa-sim/softfloat/f32_to_ui64_r_minMag.c new file mode 100644 index 0000000000..f96f3e1fe6 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f32_to_ui64_r_minMag.c @@ -0,0 +1,90 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +uint_fast64_t f32_to_ui64_r_minMag( float32_t a, bool exact ) +{ + union ui32_f32 uA; + uint_fast32_t uiA; + int_fast16_t exp; + uint_fast32_t sig; + int_fast16_t shiftDist; + bool sign; + uint_fast64_t sig64, z; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uA.f = a; + uiA = uA.ui; + exp = expF32UI( uiA ); + sig = fracF32UI( uiA ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + shiftDist = 0xBE - exp; + if ( 64 <= shiftDist ) { + if ( exact && (exp | sig) ) { + softfloat_exceptionFlags |= softfloat_flag_inexact; + } + return 0; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + sign = signF32UI( uiA ); + if ( sign || (shiftDist < 0) ) { + softfloat_raiseFlags( softfloat_flag_invalid ); + return + (exp == 0xFF) && sig ? ui64_fromNaN + : sign ? ui64_fromNegOverflow : ui64_fromPosOverflow; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + sig |= 0x00800000; + sig64 = (uint_fast64_t) sig<<40; + z = sig64>>shiftDist; + shiftDist = 40 - shiftDist; + if ( exact && (shiftDist < 0) && (uint32_t) (sig<<(shiftDist & 31)) ) { + softfloat_exceptionFlags |= softfloat_flag_inexact; + } + return z; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f64_add.c b/vendor/riscv/riscv-isa-sim/softfloat/f64_add.c new file mode 100644 index 0000000000..e9880ddfcd --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f64_add.c @@ -0,0 +1,74 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "softfloat.h" + +float64_t f64_add( float64_t a, float64_t b ) +{ + union ui64_f64 uA; + uint_fast64_t uiA; + bool signA; + union ui64_f64 uB; + uint_fast64_t uiB; + bool signB; +#if ! defined INLINE_LEVEL || (INLINE_LEVEL < 2) + float64_t (*magsFuncPtr)( uint_fast64_t, uint_fast64_t, bool ); +#endif + + uA.f = a; + uiA = uA.ui; + signA = signF64UI( uiA ); + uB.f = b; + uiB = uB.ui; + signB = signF64UI( uiB ); +#if defined INLINE_LEVEL && (2 <= INLINE_LEVEL) + if ( signA == signB ) { + return softfloat_addMagsF64( uiA, uiB, signA ); + } else { + return softfloat_subMagsF64( uiA, uiB, signA ); + } +#else + magsFuncPtr = + (signA == signB) ? softfloat_addMagsF64 : softfloat_subMagsF64; + return (*magsFuncPtr)( uiA, uiB, signA ); +#endif + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f64_classify.c b/vendor/riscv/riscv-isa-sim/softfloat/f64_classify.c new file mode 100755 index 0000000000..180abde3cb --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f64_classify.c @@ -0,0 +1,36 @@ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +uint_fast16_t f64_classify( float64_t a ) +{ + union ui64_f64 uA; + uint_fast64_t uiA; + + uA.f = a; + uiA = uA.ui; + + uint_fast16_t infOrNaN = expF64UI( uiA ) == 0x7FF; + uint_fast16_t subnormalOrZero = expF64UI( uiA ) == 0; + bool sign = signF64UI( uiA ); + bool fracZero = fracF64UI( uiA ) == 0; + bool isNaN = isNaNF64UI( uiA ); + bool isSNaN = softfloat_isSigNaNF64UI( uiA ); + + return + ( sign && infOrNaN && fracZero ) << 0 | + ( sign && !infOrNaN && !subnormalOrZero ) << 1 | + ( sign && subnormalOrZero && !fracZero ) << 2 | + ( sign && subnormalOrZero && fracZero ) << 3 | + ( !sign && infOrNaN && fracZero ) << 7 | + ( !sign && !infOrNaN && !subnormalOrZero ) << 6 | + ( !sign && subnormalOrZero && !fracZero ) << 5 | + ( !sign && subnormalOrZero && fracZero ) << 4 | + ( isNaN && isSNaN ) << 8 | + ( isNaN && !isSNaN ) << 9; +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f64_div.c b/vendor/riscv/riscv-isa-sim/softfloat/f64_div.c new file mode 100644 index 0000000000..c5a2d4fe34 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f64_div.c @@ -0,0 +1,172 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +float64_t f64_div( float64_t a, float64_t b ) +{ + union ui64_f64 uA; + uint_fast64_t uiA; + bool signA; + int_fast16_t expA; + uint_fast64_t sigA; + union ui64_f64 uB; + uint_fast64_t uiB; + bool signB; + int_fast16_t expB; + uint_fast64_t sigB; + bool signZ; + struct exp16_sig64 normExpSig; + int_fast16_t expZ; + uint32_t recip32, sig32Z, doubleTerm; + uint_fast64_t rem; + uint32_t q; + uint_fast64_t sigZ; + uint_fast64_t uiZ; + union ui64_f64 uZ; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uA.f = a; + uiA = uA.ui; + signA = signF64UI( uiA ); + expA = expF64UI( uiA ); + sigA = fracF64UI( uiA ); + uB.f = b; + uiB = uB.ui; + signB = signF64UI( uiB ); + expB = expF64UI( uiB ); + sigB = fracF64UI( uiB ); + signZ = signA ^ signB; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( expA == 0x7FF ) { + if ( sigA ) goto propagateNaN; + if ( expB == 0x7FF ) { + if ( sigB ) goto propagateNaN; + goto invalid; + } + goto infinity; + } + if ( expB == 0x7FF ) { + if ( sigB ) goto propagateNaN; + goto zero; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( ! expB ) { + if ( ! sigB ) { + if ( ! (expA | sigA) ) goto invalid; + softfloat_raiseFlags( softfloat_flag_infinite ); + goto infinity; + } + normExpSig = softfloat_normSubnormalF64Sig( sigB ); + expB = normExpSig.exp; + sigB = normExpSig.sig; + } + if ( ! expA ) { + if ( ! sigA ) goto zero; + normExpSig = softfloat_normSubnormalF64Sig( sigA ); + expA = normExpSig.exp; + sigA = normExpSig.sig; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + expZ = expA - expB + 0x3FE; + sigA |= UINT64_C( 0x0010000000000000 ); + sigB |= UINT64_C( 0x0010000000000000 ); + if ( sigA < sigB ) { + --expZ; + sigA <<= 11; + } else { + sigA <<= 10; + } + sigB <<= 11; + recip32 = softfloat_approxRecip32_1( sigB>>32 ) - 2; + sig32Z = ((uint32_t) (sigA>>32) * (uint_fast64_t) recip32)>>32; + doubleTerm = sig32Z<<1; + rem = + ((sigA - (uint_fast64_t) doubleTerm * (uint32_t) (sigB>>32))<<28) + - (uint_fast64_t) doubleTerm * ((uint32_t) sigB>>4); + q = (((uint32_t) (rem>>32) * (uint_fast64_t) recip32)>>32) + 4; + sigZ = ((uint_fast64_t) sig32Z<<32) + ((uint_fast64_t) q<<4); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( (sigZ & 0x1FF) < 4<<4 ) { + q &= ~7; + sigZ &= ~(uint_fast64_t) 0x7F; + doubleTerm = q<<1; + rem = + ((rem - (uint_fast64_t) doubleTerm * (uint32_t) (sigB>>32))<<28) + - (uint_fast64_t) doubleTerm * ((uint32_t) sigB>>4); + if ( rem & UINT64_C( 0x8000000000000000 ) ) { + sigZ -= 1<<7; + } else { + if ( rem ) sigZ |= 1; + } + } + return softfloat_roundPackToF64( signZ, expZ, sigZ ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + propagateNaN: + uiZ = softfloat_propagateNaNF64UI( uiA, uiB ); + goto uiZ; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + invalid: + softfloat_raiseFlags( softfloat_flag_invalid ); + uiZ = defaultNaNF64UI; + goto uiZ; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + infinity: + uiZ = packToF64UI( signZ, 0x7FF, 0 ); + goto uiZ; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + zero: + uiZ = packToF64UI( signZ, 0, 0 ); + uiZ: + uZ.ui = uiZ; + return uZ.f; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f64_eq.c b/vendor/riscv/riscv-isa-sim/softfloat/f64_eq.c new file mode 100644 index 0000000000..ccb602a382 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f64_eq.c @@ -0,0 +1,66 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +bool f64_eq( float64_t a, float64_t b ) +{ + union ui64_f64 uA; + uint_fast64_t uiA; + union ui64_f64 uB; + uint_fast64_t uiB; + + uA.f = a; + uiA = uA.ui; + uB.f = b; + uiB = uB.ui; + if ( isNaNF64UI( uiA ) || isNaNF64UI( uiB ) ) { + if ( + softfloat_isSigNaNF64UI( uiA ) || softfloat_isSigNaNF64UI( uiB ) + ) { + softfloat_raiseFlags( softfloat_flag_invalid ); + } + return false; + } + return (uiA == uiB) || ! ((uiA | uiB) & UINT64_C( 0x7FFFFFFFFFFFFFFF )); + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f64_eq_signaling.c b/vendor/riscv/riscv-isa-sim/softfloat/f64_eq_signaling.c new file mode 100644 index 0000000000..ee5a4414f7 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f64_eq_signaling.c @@ -0,0 +1,61 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "softfloat.h" + +bool f64_eq_signaling( float64_t a, float64_t b ) +{ + union ui64_f64 uA; + uint_fast64_t uiA; + union ui64_f64 uB; + uint_fast64_t uiB; + + uA.f = a; + uiA = uA.ui; + uB.f = b; + uiB = uB.ui; + if ( isNaNF64UI( uiA ) || isNaNF64UI( uiB ) ) { + softfloat_raiseFlags( softfloat_flag_invalid ); + return false; + } + return (uiA == uiB) || ! ((uiA | uiB) & UINT64_C( 0x7FFFFFFFFFFFFFFF )); + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f64_isSignalingNaN.c b/vendor/riscv/riscv-isa-sim/softfloat/f64_isSignalingNaN.c new file mode 100644 index 0000000000..f55acb4a02 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f64_isSignalingNaN.c @@ -0,0 +1,51 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +bool f64_isSignalingNaN( float64_t a ) +{ + union ui64_f64 uA; + + uA.f = a; + return softfloat_isSigNaNF64UI( uA.ui ); + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f64_le.c b/vendor/riscv/riscv-isa-sim/softfloat/f64_le.c new file mode 100644 index 0000000000..91fc994abe --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f64_le.c @@ -0,0 +1,67 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "softfloat.h" + +bool f64_le( float64_t a, float64_t b ) +{ + union ui64_f64 uA; + uint_fast64_t uiA; + union ui64_f64 uB; + uint_fast64_t uiB; + bool signA, signB; + + uA.f = a; + uiA = uA.ui; + uB.f = b; + uiB = uB.ui; + if ( isNaNF64UI( uiA ) || isNaNF64UI( uiB ) ) { + softfloat_raiseFlags( softfloat_flag_invalid ); + return false; + } + signA = signF64UI( uiA ); + signB = signF64UI( uiB ); + return + (signA != signB) + ? signA || ! ((uiA | uiB) & UINT64_C( 0x7FFFFFFFFFFFFFFF )) + : (uiA == uiB) || (signA ^ (uiA < uiB)); + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f64_le_quiet.c b/vendor/riscv/riscv-isa-sim/softfloat/f64_le_quiet.c new file mode 100644 index 0000000000..a5d332a5b0 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f64_le_quiet.c @@ -0,0 +1,72 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +bool f64_le_quiet( float64_t a, float64_t b ) +{ + union ui64_f64 uA; + uint_fast64_t uiA; + union ui64_f64 uB; + uint_fast64_t uiB; + bool signA, signB; + + uA.f = a; + uiA = uA.ui; + uB.f = b; + uiB = uB.ui; + if ( isNaNF64UI( uiA ) || isNaNF64UI( uiB ) ) { + if ( + softfloat_isSigNaNF64UI( uiA ) || softfloat_isSigNaNF64UI( uiB ) + ) { + softfloat_raiseFlags( softfloat_flag_invalid ); + } + return false; + } + signA = signF64UI( uiA ); + signB = signF64UI( uiB ); + return + (signA != signB) + ? signA || ! ((uiA | uiB) & UINT64_C( 0x7FFFFFFFFFFFFFFF )) + : (uiA == uiB) || (signA ^ (uiA < uiB)); + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f64_lt.c b/vendor/riscv/riscv-isa-sim/softfloat/f64_lt.c new file mode 100644 index 0000000000..abf62fd3d5 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f64_lt.c @@ -0,0 +1,67 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "softfloat.h" + +bool f64_lt( float64_t a, float64_t b ) +{ + union ui64_f64 uA; + uint_fast64_t uiA; + union ui64_f64 uB; + uint_fast64_t uiB; + bool signA, signB; + + uA.f = a; + uiA = uA.ui; + uB.f = b; + uiB = uB.ui; + if ( isNaNF64UI( uiA ) || isNaNF64UI( uiB ) ) { + softfloat_raiseFlags( softfloat_flag_invalid ); + return false; + } + signA = signF64UI( uiA ); + signB = signF64UI( uiB ); + return + (signA != signB) + ? signA && ((uiA | uiB) & UINT64_C( 0x7FFFFFFFFFFFFFFF )) + : (uiA != uiB) && (signA ^ (uiA < uiB)); + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f64_lt_quiet.c b/vendor/riscv/riscv-isa-sim/softfloat/f64_lt_quiet.c new file mode 100644 index 0000000000..6531f577e6 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f64_lt_quiet.c @@ -0,0 +1,72 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +bool f64_lt_quiet( float64_t a, float64_t b ) +{ + union ui64_f64 uA; + uint_fast64_t uiA; + union ui64_f64 uB; + uint_fast64_t uiB; + bool signA, signB; + + uA.f = a; + uiA = uA.ui; + uB.f = b; + uiB = uB.ui; + if ( isNaNF64UI( uiA ) || isNaNF64UI( uiB ) ) { + if ( + softfloat_isSigNaNF64UI( uiA ) || softfloat_isSigNaNF64UI( uiB ) + ) { + softfloat_raiseFlags( softfloat_flag_invalid ); + } + return false; + } + signA = signF64UI( uiA ); + signB = signF64UI( uiB ); + return + (signA != signB) + ? signA && ((uiA | uiB) & UINT64_C( 0x7FFFFFFFFFFFFFFF )) + : (uiA != uiB) && (signA ^ (uiA < uiB)); + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f64_mul.c b/vendor/riscv/riscv-isa-sim/softfloat/f64_mul.c new file mode 100644 index 0000000000..86f6654587 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f64_mul.c @@ -0,0 +1,150 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +float64_t f64_mul( float64_t a, float64_t b ) +{ + union ui64_f64 uA; + uint_fast64_t uiA; + bool signA; + int_fast16_t expA; + uint_fast64_t sigA; + union ui64_f64 uB; + uint_fast64_t uiB; + bool signB; + int_fast16_t expB; + uint_fast64_t sigB; + bool signZ; + uint_fast64_t magBits; + struct exp16_sig64 normExpSig; + int_fast16_t expZ; +#ifdef SOFTFLOAT_FAST_INT64 + struct uint128 sig128Z; +#else + uint32_t sig128Z[4]; +#endif + uint_fast64_t sigZ, uiZ; + union ui64_f64 uZ; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uA.f = a; + uiA = uA.ui; + signA = signF64UI( uiA ); + expA = expF64UI( uiA ); + sigA = fracF64UI( uiA ); + uB.f = b; + uiB = uB.ui; + signB = signF64UI( uiB ); + expB = expF64UI( uiB ); + sigB = fracF64UI( uiB ); + signZ = signA ^ signB; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( expA == 0x7FF ) { + if ( sigA || ((expB == 0x7FF) && sigB) ) goto propagateNaN; + magBits = expB | sigB; + goto infArg; + } + if ( expB == 0x7FF ) { + if ( sigB ) goto propagateNaN; + magBits = expA | sigA; + goto infArg; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( ! expA ) { + if ( ! sigA ) goto zero; + normExpSig = softfloat_normSubnormalF64Sig( sigA ); + expA = normExpSig.exp; + sigA = normExpSig.sig; + } + if ( ! expB ) { + if ( ! sigB ) goto zero; + normExpSig = softfloat_normSubnormalF64Sig( sigB ); + expB = normExpSig.exp; + sigB = normExpSig.sig; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + expZ = expA + expB - 0x3FF; + sigA = (sigA | UINT64_C( 0x0010000000000000 ))<<10; + sigB = (sigB | UINT64_C( 0x0010000000000000 ))<<11; +#ifdef SOFTFLOAT_FAST_INT64 + sig128Z = softfloat_mul64To128( sigA, sigB ); + sigZ = sig128Z.v64 | (sig128Z.v0 != 0); +#else + softfloat_mul64To128M( sigA, sigB, sig128Z ); + sigZ = + (uint64_t) sig128Z[indexWord( 4, 3 )]<<32 | sig128Z[indexWord( 4, 2 )]; + if ( sig128Z[indexWord( 4, 1 )] || sig128Z[indexWord( 4, 0 )] ) sigZ |= 1; +#endif + if ( sigZ < UINT64_C( 0x4000000000000000 ) ) { + --expZ; + sigZ <<= 1; + } + return softfloat_roundPackToF64( signZ, expZ, sigZ ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + propagateNaN: + uiZ = softfloat_propagateNaNF64UI( uiA, uiB ); + goto uiZ; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + infArg: + if ( ! magBits ) { + softfloat_raiseFlags( softfloat_flag_invalid ); + uiZ = defaultNaNF64UI; + } else { + uiZ = packToF64UI( signZ, 0x7FF, 0 ); + } + goto uiZ; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + zero: + uiZ = packToF64UI( signZ, 0, 0 ); + uiZ: + uZ.ui = uiZ; + return uZ.f; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f64_mulAdd.c b/vendor/riscv/riscv-isa-sim/softfloat/f64_mulAdd.c new file mode 100644 index 0000000000..67fc44d38e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f64_mulAdd.c @@ -0,0 +1,60 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "softfloat.h" + +float64_t f64_mulAdd( float64_t a, float64_t b, float64_t c ) +{ + union ui64_f64 uA; + uint_fast64_t uiA; + union ui64_f64 uB; + uint_fast64_t uiB; + union ui64_f64 uC; + uint_fast64_t uiC; + + uA.f = a; + uiA = uA.ui; + uB.f = b; + uiB = uB.ui; + uC.f = c; + uiC = uC.ui; + return softfloat_mulAddF64( uiA, uiB, uiC, 0 ); + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f64_rem.c b/vendor/riscv/riscv-isa-sim/softfloat/f64_rem.c new file mode 100644 index 0000000000..e917455421 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f64_rem.c @@ -0,0 +1,189 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +float64_t f64_rem( float64_t a, float64_t b ) +{ + union ui64_f64 uA; + uint_fast64_t uiA; + bool signA; + int_fast16_t expA; + uint_fast64_t sigA; + union ui64_f64 uB; + uint_fast64_t uiB; + int_fast16_t expB; + uint_fast64_t sigB; + struct exp16_sig64 normExpSig; + uint64_t rem; + int_fast16_t expDiff; + uint32_t q, recip32; + uint_fast64_t q64; + uint64_t altRem, meanRem; + bool signRem; + uint_fast64_t uiZ; + union ui64_f64 uZ; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uA.f = a; + uiA = uA.ui; + signA = signF64UI( uiA ); + expA = expF64UI( uiA ); + sigA = fracF64UI( uiA ); + uB.f = b; + uiB = uB.ui; + expB = expF64UI( uiB ); + sigB = fracF64UI( uiB ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( expA == 0x7FF ) { + if ( sigA || ((expB == 0x7FF) && sigB) ) goto propagateNaN; + goto invalid; + } + if ( expB == 0x7FF ) { + if ( sigB ) goto propagateNaN; + return a; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( expA < expB - 1 ) return a; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( ! expB ) { + if ( ! sigB ) goto invalid; + normExpSig = softfloat_normSubnormalF64Sig( sigB ); + expB = normExpSig.exp; + sigB = normExpSig.sig; + } + if ( ! expA ) { + if ( ! sigA ) return a; + normExpSig = softfloat_normSubnormalF64Sig( sigA ); + expA = normExpSig.exp; + sigA = normExpSig.sig; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + rem = sigA | UINT64_C( 0x0010000000000000 ); + sigB |= UINT64_C( 0x0010000000000000 ); + expDiff = expA - expB; + if ( expDiff < 1 ) { + if ( expDiff < -1 ) return a; + sigB <<= 9; + if ( expDiff ) { + rem <<= 8; + q = 0; + } else { + rem <<= 9; + q = (sigB <= rem); + if ( q ) rem -= sigB; + } + } else { + recip32 = softfloat_approxRecip32_1( sigB>>21 ); + /*-------------------------------------------------------------------- + | Changing the shift of `rem' here requires also changing the initial + | subtraction from `expDiff'. + *--------------------------------------------------------------------*/ + rem <<= 9; + expDiff -= 30; + /*-------------------------------------------------------------------- + | The scale of `sigB' affects how many bits are obtained during each + | cycle of the loop. Currently this is 29 bits per loop iteration, + | the maximum possible. + *--------------------------------------------------------------------*/ + sigB <<= 9; + for (;;) { + q64 = (uint32_t) (rem>>32) * (uint_fast64_t) recip32; + if ( expDiff < 0 ) break; + q = (q64 + 0x80000000)>>32; +#ifdef SOFTFLOAT_FAST_INT64 + rem <<= 29; +#else + rem = (uint_fast64_t) (uint32_t) (rem>>3)<<32; +#endif + rem -= q * (uint64_t) sigB; + if ( rem & UINT64_C( 0x8000000000000000 ) ) rem += sigB; + expDiff -= 29; + } + /*-------------------------------------------------------------------- + | (`expDiff' cannot be less than -29 here.) + *--------------------------------------------------------------------*/ + q = (uint32_t) (q64>>32)>>(~expDiff & 31); + rem = (rem<<(expDiff + 30)) - q * (uint64_t) sigB; + if ( rem & UINT64_C( 0x8000000000000000 ) ) { + altRem = rem + sigB; + goto selectRem; + } + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + do { + altRem = rem; + ++q; + rem -= sigB; + } while ( ! (rem & UINT64_C( 0x8000000000000000 )) ); + selectRem: + meanRem = rem + altRem; + if ( + (meanRem & UINT64_C( 0x8000000000000000 )) || (! meanRem && (q & 1)) + ) { + rem = altRem; + } + signRem = signA; + if ( rem & UINT64_C( 0x8000000000000000 ) ) { + signRem = ! signRem; + rem = -rem; + } + return softfloat_normRoundPackToF64( signRem, expB, rem ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + propagateNaN: + uiZ = softfloat_propagateNaNF64UI( uiA, uiB ); + goto uiZ; + invalid: + softfloat_raiseFlags( softfloat_flag_invalid ); + uiZ = defaultNaNF64UI; + uiZ: + uZ.ui = uiZ; + return uZ.f; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f64_roundToInt.c b/vendor/riscv/riscv-isa-sim/softfloat/f64_roundToInt.c new file mode 100644 index 0000000000..7f81007082 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f64_roundToInt.c @@ -0,0 +1,112 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +float64_t f64_roundToInt( float64_t a, uint_fast8_t roundingMode, bool exact ) +{ + union ui64_f64 uA; + uint_fast64_t uiA; + int_fast16_t exp; + uint_fast64_t uiZ, lastBitMask, roundBitsMask; + union ui64_f64 uZ; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uA.f = a; + uiA = uA.ui; + exp = expF64UI( uiA ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( exp <= 0x3FE ) { + if ( ! (uiA & UINT64_C( 0x7FFFFFFFFFFFFFFF )) ) return a; + if ( exact ) softfloat_exceptionFlags |= softfloat_flag_inexact; + uiZ = uiA & packToF64UI( 1, 0, 0 ); + switch ( roundingMode ) { + case softfloat_round_near_even: + if ( ! fracF64UI( uiA ) ) break; + case softfloat_round_near_maxMag: + if ( exp == 0x3FE ) uiZ |= packToF64UI( 0, 0x3FF, 0 ); + break; + case softfloat_round_min: + if ( uiZ ) uiZ = packToF64UI( 1, 0x3FF, 0 ); + break; + case softfloat_round_max: + if ( ! uiZ ) uiZ = packToF64UI( 0, 0x3FF, 0 ); + break; + } + goto uiZ; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( 0x433 <= exp ) { + if ( (exp == 0x7FF) && fracF64UI( uiA ) ) { + uiZ = softfloat_propagateNaNF64UI( uiA, 0 ); + goto uiZ; + } + return a; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uiZ = uiA; + lastBitMask = (uint_fast64_t) 1<<(0x433 - exp); + roundBitsMask = lastBitMask - 1; + if ( roundingMode == softfloat_round_near_maxMag ) { + uiZ += lastBitMask>>1; + } else if ( roundingMode == softfloat_round_near_even ) { + uiZ += lastBitMask>>1; + if ( ! (uiZ & roundBitsMask) ) uiZ &= ~lastBitMask; + } else if ( + roundingMode + == (signF64UI( uiZ ) ? softfloat_round_min : softfloat_round_max) + ) { + uiZ += roundBitsMask; + } + uiZ &= ~roundBitsMask; + if ( exact && (uiZ != uiA) ) { + softfloat_exceptionFlags |= softfloat_flag_inexact; + } + uiZ: + uZ.ui = uiZ; + return uZ.f; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f64_sqrt.c b/vendor/riscv/riscv-isa-sim/softfloat/f64_sqrt.c new file mode 100644 index 0000000000..9a06cfad3d --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f64_sqrt.c @@ -0,0 +1,133 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +float64_t f64_sqrt( float64_t a ) +{ + union ui64_f64 uA; + uint_fast64_t uiA; + bool signA; + int_fast16_t expA; + uint_fast64_t sigA, uiZ; + struct exp16_sig64 normExpSig; + int_fast16_t expZ; + uint32_t sig32A, recipSqrt32, sig32Z; + uint_fast64_t rem; + uint32_t q; + uint_fast64_t sigZ, shiftedSigZ; + union ui64_f64 uZ; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uA.f = a; + uiA = uA.ui; + signA = signF64UI( uiA ); + expA = expF64UI( uiA ); + sigA = fracF64UI( uiA ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( expA == 0x7FF ) { + if ( sigA ) { + uiZ = softfloat_propagateNaNF64UI( uiA, 0 ); + goto uiZ; + } + if ( ! signA ) return a; + goto invalid; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( signA ) { + if ( ! (expA | sigA) ) return a; + goto invalid; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( ! expA ) { + if ( ! sigA ) return a; + normExpSig = softfloat_normSubnormalF64Sig( sigA ); + expA = normExpSig.exp; + sigA = normExpSig.sig; + } + /*------------------------------------------------------------------------ + | (`sig32Z' is guaranteed to be a lower bound on the square root of + | `sig32A', which makes `sig32Z' also a lower bound on the square root of + | `sigA'.) + *------------------------------------------------------------------------*/ + expZ = ((expA - 0x3FF)>>1) + 0x3FE; + expA &= 1; + sigA |= UINT64_C( 0x0010000000000000 ); + sig32A = sigA>>21; + recipSqrt32 = softfloat_approxRecipSqrt32_1( expA, sig32A ); + sig32Z = ((uint_fast64_t) sig32A * recipSqrt32)>>32; + if ( expA ) { + sigA <<= 8; + sig32Z >>= 1; + } else { + sigA <<= 9; + } + rem = sigA - (uint_fast64_t) sig32Z * sig32Z; + q = ((uint32_t) (rem>>2) * (uint_fast64_t) recipSqrt32)>>32; + sigZ = ((uint_fast64_t) sig32Z<<32 | 1<<5) + ((uint_fast64_t) q<<3); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( (sigZ & 0x1FF) < 0x22 ) { + sigZ &= ~(uint_fast64_t) 0x3F; + shiftedSigZ = sigZ>>6; + rem = (sigA<<52) - shiftedSigZ * shiftedSigZ; + if ( rem & UINT64_C( 0x8000000000000000 ) ) { + --sigZ; + } else { + if ( rem ) sigZ |= 1; + } + } + return softfloat_roundPackToF64( 0, expZ, sigZ ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + invalid: + softfloat_raiseFlags( softfloat_flag_invalid ); + uiZ = defaultNaNF64UI; + uiZ: + uZ.ui = uiZ; + return uZ.f; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f64_sub.c b/vendor/riscv/riscv-isa-sim/softfloat/f64_sub.c new file mode 100644 index 0000000000..0e990cd135 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f64_sub.c @@ -0,0 +1,74 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "softfloat.h" + +float64_t f64_sub( float64_t a, float64_t b ) +{ + union ui64_f64 uA; + uint_fast64_t uiA; + bool signA; + union ui64_f64 uB; + uint_fast64_t uiB; + bool signB; +#if ! defined INLINE_LEVEL || (INLINE_LEVEL < 2) + float64_t (*magsFuncPtr)( uint_fast64_t, uint_fast64_t, bool ); +#endif + + uA.f = a; + uiA = uA.ui; + signA = signF64UI( uiA ); + uB.f = b; + uiB = uB.ui; + signB = signF64UI( uiB ); +#if defined INLINE_LEVEL && (2 <= INLINE_LEVEL) + if ( signA == signB ) { + return softfloat_subMagsF64( uiA, uiB, signA ); + } else { + return softfloat_addMagsF64( uiA, uiB, signA ); + } +#else + magsFuncPtr = + (signA == signB) ? softfloat_subMagsF64 : softfloat_addMagsF64; + return (*magsFuncPtr)( uiA, uiB, signA ); +#endif + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f64_to_f128.c b/vendor/riscv/riscv-isa-sim/softfloat/f64_to_f128.c new file mode 100644 index 0000000000..92c2d56016 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f64_to_f128.c @@ -0,0 +1,98 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +float128_t f64_to_f128( float64_t a ) +{ + union ui64_f64 uA; + uint_fast64_t uiA; + bool sign; + int_fast16_t exp; + uint_fast64_t frac; + struct commonNaN commonNaN; + struct uint128 uiZ; + struct exp16_sig64 normExpSig; + struct uint128 frac128; + union ui128_f128 uZ; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uA.f = a; + uiA = uA.ui; + sign = signF64UI( uiA ); + exp = expF64UI( uiA ); + frac = fracF64UI( uiA ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( exp == 0x7FF ) { + if ( frac ) { + softfloat_f64UIToCommonNaN( uiA, &commonNaN ); + uiZ = softfloat_commonNaNToF128UI( &commonNaN ); + } else { + uiZ.v64 = packToF128UI64( sign, 0x7FFF, 0 ); + uiZ.v0 = 0; + } + goto uiZ; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( ! exp ) { + if ( ! frac ) { + uiZ.v64 = packToF128UI64( sign, 0, 0 ); + uiZ.v0 = 0; + goto uiZ; + } + normExpSig = softfloat_normSubnormalF64Sig( frac ); + exp = normExpSig.exp - 1; + frac = normExpSig.sig; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + frac128 = softfloat_shortShiftLeft128( 0, frac, 60 ); + uiZ.v64 = packToF128UI64( sign, exp + 0x3C00, frac128.v64 ); + uiZ.v0 = frac128.v0; + uiZ: + uZ.ui = uiZ; + return uZ.f; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f64_to_f16.c b/vendor/riscv/riscv-isa-sim/softfloat/f64_to_f16.c new file mode 100644 index 0000000000..325788c663 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f64_to_f16.c @@ -0,0 +1,88 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +float16_t f64_to_f16( float64_t a ) +{ + union ui64_f64 uA; + uint_fast64_t uiA; + bool sign; + int_fast16_t exp; + uint_fast64_t frac; + struct commonNaN commonNaN; + uint_fast16_t uiZ, frac16; + union ui16_f16 uZ; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uA.f = a; + uiA = uA.ui; + sign = signF64UI( uiA ); + exp = expF64UI( uiA ); + frac = fracF64UI( uiA ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( exp == 0x7FF ) { + if ( frac ) { + softfloat_f64UIToCommonNaN( uiA, &commonNaN ); + uiZ = softfloat_commonNaNToF16UI( &commonNaN ); + } else { + uiZ = packToF16UI( sign, 0x1F, 0 ); + } + goto uiZ; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + frac16 = softfloat_shortShiftRightJam64( frac, 38 ); + if ( ! (exp | frac16) ) { + uiZ = packToF16UI( sign, 0, 0 ); + goto uiZ; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + return softfloat_roundPackToF16( sign, exp - 0x3F1, frac16 | 0x4000 ); + uiZ: + uZ.ui = uiZ; + return uZ.f; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f64_to_f32.c b/vendor/riscv/riscv-isa-sim/softfloat/f64_to_f32.c new file mode 100644 index 0000000000..99b13dda47 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f64_to_f32.c @@ -0,0 +1,88 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +float32_t f64_to_f32( float64_t a ) +{ + union ui64_f64 uA; + uint_fast64_t uiA; + bool sign; + int_fast16_t exp; + uint_fast64_t frac; + struct commonNaN commonNaN; + uint_fast32_t uiZ, frac32; + union ui32_f32 uZ; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uA.f = a; + uiA = uA.ui; + sign = signF64UI( uiA ); + exp = expF64UI( uiA ); + frac = fracF64UI( uiA ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( exp == 0x7FF ) { + if ( frac ) { + softfloat_f64UIToCommonNaN( uiA, &commonNaN ); + uiZ = softfloat_commonNaNToF32UI( &commonNaN ); + } else { + uiZ = packToF32UI( sign, 0xFF, 0 ); + } + goto uiZ; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + frac32 = softfloat_shortShiftRightJam64( frac, 22 ); + if ( ! (exp | frac32) ) { + uiZ = packToF32UI( sign, 0, 0 ); + goto uiZ; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + return softfloat_roundPackToF32( sign, exp - 0x381, frac32 | 0x40000000 ); + uiZ: + uZ.ui = uiZ; + return uZ.f; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f64_to_i32.c b/vendor/riscv/riscv-isa-sim/softfloat/f64_to_i32.c new file mode 100644 index 0000000000..8712c0ac56 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f64_to_i32.c @@ -0,0 +1,82 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the +University of California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +int_fast32_t f64_to_i32( float64_t a, uint_fast8_t roundingMode, bool exact ) +{ + union ui64_f64 uA; + uint_fast64_t uiA; + bool sign; + int_fast16_t exp; + uint_fast64_t sig; + int_fast16_t shiftDist; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uA.f = a; + uiA = uA.ui; + sign = signF64UI( uiA ); + exp = expF64UI( uiA ); + sig = fracF64UI( uiA ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ +#if (i32_fromNaN != i32_fromPosOverflow) || (i32_fromNaN != i32_fromNegOverflow) + if ( (exp == 0x7FF) && sig ) { +#if (i32_fromNaN == i32_fromPosOverflow) + sign = 0; +#elif (i32_fromNaN == i32_fromNegOverflow) + sign = 1; +#else + softfloat_raiseFlags( softfloat_flag_invalid ); + return i32_fromNaN; +#endif + } +#endif + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( exp ) sig |= UINT64_C( 0x0010000000000000 ); + shiftDist = 0x427 - exp; + if ( 0 < shiftDist ) sig = softfloat_shiftRightJam64( sig, shiftDist ); + return softfloat_roundToI32( sign, sig, roundingMode, exact ); + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f64_to_i32_r_minMag.c b/vendor/riscv/riscv-isa-sim/softfloat/f64_to_i32_r_minMag.c new file mode 100644 index 0000000000..b7e1e03054 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f64_to_i32_r_minMag.c @@ -0,0 +1,96 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +int_fast32_t f64_to_i32_r_minMag( float64_t a, bool exact ) +{ + union ui64_f64 uA; + uint_fast64_t uiA; + int_fast16_t exp; + uint_fast64_t sig; + int_fast16_t shiftDist; + bool sign; + int_fast32_t absZ; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uA.f = a; + uiA = uA.ui; + exp = expF64UI( uiA ); + sig = fracF64UI( uiA ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + shiftDist = 0x433 - exp; + if ( 53 <= shiftDist ) { + if ( exact && (exp | sig) ) { + softfloat_exceptionFlags |= softfloat_flag_inexact; + } + return 0; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + sign = signF64UI( uiA ); + if ( shiftDist < 22 ) { + if ( + sign && (exp == 0x41E) && (sig < UINT64_C( 0x0000000000200000 )) + ) { + if ( exact && sig ) { + softfloat_exceptionFlags |= softfloat_flag_inexact; + } + return -0x7FFFFFFF - 1; + } + softfloat_raiseFlags( softfloat_flag_invalid ); + return + (exp == 0x7FF) && sig ? i32_fromNaN + : sign ? i32_fromNegOverflow : i32_fromPosOverflow; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + sig |= UINT64_C( 0x0010000000000000 ); + absZ = sig>>shiftDist; + if ( exact && ((uint_fast64_t) (uint_fast32_t) absZ<<shiftDist != sig) ) { + softfloat_exceptionFlags |= softfloat_flag_inexact; + } + return sign ? -absZ : absZ; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f64_to_i64.c b/vendor/riscv/riscv-isa-sim/softfloat/f64_to_i64.c new file mode 100644 index 0000000000..4f48843c0a --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f64_to_i64.c @@ -0,0 +1,103 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the +University of California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +int_fast64_t f64_to_i64( float64_t a, uint_fast8_t roundingMode, bool exact ) +{ + union ui64_f64 uA; + uint_fast64_t uiA; + bool sign; + int_fast16_t exp; + uint_fast64_t sig; + int_fast16_t shiftDist; +#ifdef SOFTFLOAT_FAST_INT64 + struct uint64_extra sigExtra; +#else + uint32_t extSig[3]; +#endif + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uA.f = a; + uiA = uA.ui; + sign = signF64UI( uiA ); + exp = expF64UI( uiA ); + sig = fracF64UI( uiA ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( exp ) sig |= UINT64_C( 0x0010000000000000 ); + shiftDist = 0x433 - exp; +#ifdef SOFTFLOAT_FAST_INT64 + if ( shiftDist <= 0 ) { + if ( shiftDist < -11 ) goto invalid; + sigExtra.v = sig<<-shiftDist; + sigExtra.extra = 0; + } else { + sigExtra = softfloat_shiftRightJam64Extra( sig, 0, shiftDist ); + } + return + softfloat_roundToI64( + sign, sigExtra.v, sigExtra.extra, roundingMode, exact ); +#else + extSig[indexWord( 3, 0 )] = 0; + if ( shiftDist <= 0 ) { + if ( shiftDist < -11 ) goto invalid; + sig <<= -shiftDist; + extSig[indexWord( 3, 2 )] = sig>>32; + extSig[indexWord( 3, 1 )] = sig; + } else { + extSig[indexWord( 3, 2 )] = sig>>32; + extSig[indexWord( 3, 1 )] = sig; + softfloat_shiftRightJam96M( extSig, shiftDist, extSig ); + } + return softfloat_roundMToI64( sign, extSig, roundingMode, exact ); +#endif + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + invalid: + softfloat_raiseFlags( softfloat_flag_invalid ); + return + (exp == 0x7FF) && fracF64UI( uiA ) ? i64_fromNaN + : sign ? i64_fromNegOverflow : i64_fromPosOverflow; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f64_to_i64_r_minMag.c b/vendor/riscv/riscv-isa-sim/softfloat/f64_to_i64_r_minMag.c new file mode 100644 index 0000000000..3822606db3 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f64_to_i64_r_minMag.c @@ -0,0 +1,100 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +int_fast64_t f64_to_i64_r_minMag( float64_t a, bool exact ) +{ + union ui64_f64 uA; + uint_fast64_t uiA; + bool sign; + int_fast16_t exp; + uint_fast64_t sig; + int_fast16_t shiftDist; + int_fast64_t absZ; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uA.f = a; + uiA = uA.ui; + sign = signF64UI( uiA ); + exp = expF64UI( uiA ); + sig = fracF64UI( uiA ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + shiftDist = 0x433 - exp; + if ( shiftDist <= 0 ) { + /*-------------------------------------------------------------------- + *--------------------------------------------------------------------*/ + if ( shiftDist < -10 ) { + if ( uiA == packToF64UI( 1, 0x43E, 0 ) ) { + return -INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1; + } + softfloat_raiseFlags( softfloat_flag_invalid ); + return + (exp == 0x7FF) && sig ? i64_fromNaN + : sign ? i64_fromNegOverflow : i64_fromPosOverflow; + } + /*-------------------------------------------------------------------- + *--------------------------------------------------------------------*/ + sig |= UINT64_C( 0x0010000000000000 ); + absZ = sig<<-shiftDist; + } else { + /*-------------------------------------------------------------------- + *--------------------------------------------------------------------*/ + if ( 53 <= shiftDist ) { + if ( exact && (exp | sig) ) { + softfloat_exceptionFlags |= softfloat_flag_inexact; + } + return 0; + } + /*-------------------------------------------------------------------- + *--------------------------------------------------------------------*/ + sig |= UINT64_C( 0x0010000000000000 ); + absZ = sig>>shiftDist; + if ( exact && (absZ<<shiftDist != sig) ) { + softfloat_exceptionFlags |= softfloat_flag_inexact; + } + } + return sign ? -absZ : absZ; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f64_to_ui32.c b/vendor/riscv/riscv-isa-sim/softfloat/f64_to_ui32.c new file mode 100644 index 0000000000..67e4d05881 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f64_to_ui32.c @@ -0,0 +1,82 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the +University of California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +uint_fast32_t f64_to_ui32( float64_t a, uint_fast8_t roundingMode, bool exact ) +{ + union ui64_f64 uA; + uint_fast64_t uiA; + bool sign; + int_fast16_t exp; + uint_fast64_t sig; + int_fast16_t shiftDist; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uA.f = a; + uiA = uA.ui; + sign = signF64UI( uiA ); + exp = expF64UI( uiA ); + sig = fracF64UI( uiA ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ +#if (ui32_fromNaN != ui32_fromPosOverflow) || (ui32_fromNaN != ui32_fromNegOverflow) + if ( (exp == 0x7FF) && sig ) { +#if (ui32_fromNaN == ui32_fromPosOverflow) + sign = 0; +#elif (ui32_fromNaN == ui32_fromNegOverflow) + sign = 1; +#else + softfloat_raiseFlags( softfloat_flag_invalid ); + return ui32_fromNaN; +#endif + } +#endif + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( exp ) sig |= UINT64_C( 0x0010000000000000 ); + shiftDist = 0x427 - exp; + if ( 0 < shiftDist ) sig = softfloat_shiftRightJam64( sig, shiftDist ); + return softfloat_roundToUI32( sign, sig, roundingMode, exact ); + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f64_to_ui32_r_minMag.c b/vendor/riscv/riscv-isa-sim/softfloat/f64_to_ui32_r_minMag.c new file mode 100644 index 0000000000..11f0b0501e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f64_to_ui32_r_minMag.c @@ -0,0 +1,88 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +uint_fast32_t f64_to_ui32_r_minMag( float64_t a, bool exact ) +{ + union ui64_f64 uA; + uint_fast64_t uiA; + int_fast16_t exp; + uint_fast64_t sig; + int_fast16_t shiftDist; + bool sign; + uint_fast32_t z; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uA.f = a; + uiA = uA.ui; + exp = expF64UI( uiA ); + sig = fracF64UI( uiA ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + shiftDist = 0x433 - exp; + if ( 53 <= shiftDist ) { + if ( exact && (exp | sig) ) { + softfloat_exceptionFlags |= softfloat_flag_inexact; + } + return 0; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + sign = signF64UI( uiA ); + if ( sign || (shiftDist < 21) ) { + softfloat_raiseFlags( softfloat_flag_invalid ); + return + (exp == 0x7FF) && sig ? ui32_fromNaN + : sign ? ui32_fromNegOverflow : ui32_fromPosOverflow; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + sig |= UINT64_C( 0x0010000000000000 ); + z = sig>>shiftDist; + if ( exact && ((uint_fast64_t) z<<shiftDist != sig) ) { + softfloat_exceptionFlags |= softfloat_flag_inexact; + } + return z; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f64_to_ui64.c b/vendor/riscv/riscv-isa-sim/softfloat/f64_to_ui64.c new file mode 100644 index 0000000000..e92d605e52 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f64_to_ui64.c @@ -0,0 +1,103 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the +University of California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +uint_fast64_t f64_to_ui64( float64_t a, uint_fast8_t roundingMode, bool exact ) +{ + union ui64_f64 uA; + uint_fast64_t uiA; + bool sign; + int_fast16_t exp; + uint_fast64_t sig; + int_fast16_t shiftDist; +#ifdef SOFTFLOAT_FAST_INT64 + struct uint64_extra sigExtra; +#else + uint32_t extSig[3]; +#endif + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uA.f = a; + uiA = uA.ui; + sign = signF64UI( uiA ); + exp = expF64UI( uiA ); + sig = fracF64UI( uiA ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( exp ) sig |= UINT64_C( 0x0010000000000000 ); + shiftDist = 0x433 - exp; +#ifdef SOFTFLOAT_FAST_INT64 + if ( shiftDist <= 0 ) { + if ( shiftDist < -11 ) goto invalid; + sigExtra.v = sig<<-shiftDist; + sigExtra.extra = 0; + } else { + sigExtra = softfloat_shiftRightJam64Extra( sig, 0, shiftDist ); + } + return + softfloat_roundToUI64( + sign, sigExtra.v, sigExtra.extra, roundingMode, exact ); +#else + extSig[indexWord( 3, 0 )] = 0; + if ( shiftDist <= 0 ) { + if ( shiftDist < -11 ) goto invalid; + sig <<= -shiftDist; + extSig[indexWord( 3, 2 )] = sig>>32; + extSig[indexWord( 3, 1 )] = sig; + } else { + extSig[indexWord( 3, 2 )] = sig>>32; + extSig[indexWord( 3, 1 )] = sig; + softfloat_shiftRightJam96M( extSig, shiftDist, extSig ); + } + return softfloat_roundMToUI64( sign, extSig, roundingMode, exact ); +#endif + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + invalid: + softfloat_raiseFlags( softfloat_flag_invalid ); + return + (exp == 0x7FF) && fracF64UI( uiA ) ? ui64_fromNaN + : sign ? ui64_fromNegOverflow : ui64_fromPosOverflow; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/f64_to_ui64_r_minMag.c b/vendor/riscv/riscv-isa-sim/softfloat/f64_to_ui64_r_minMag.c new file mode 100644 index 0000000000..25918c486d --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/f64_to_ui64_r_minMag.c @@ -0,0 +1,93 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +uint_fast64_t f64_to_ui64_r_minMag( float64_t a, bool exact ) +{ + union ui64_f64 uA; + uint_fast64_t uiA; + int_fast16_t exp; + uint_fast64_t sig; + int_fast16_t shiftDist; + bool sign; + uint_fast64_t z; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + uA.f = a; + uiA = uA.ui; + exp = expF64UI( uiA ); + sig = fracF64UI( uiA ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + shiftDist = 0x433 - exp; + if ( 53 <= shiftDist ) { + if ( exact && (exp | sig) ) { + softfloat_exceptionFlags |= softfloat_flag_inexact; + } + return 0; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + sign = signF64UI( uiA ); + if ( sign ) goto invalid; + if ( shiftDist <= 0 ) { + if ( shiftDist < -11 ) goto invalid; + z = (sig | UINT64_C( 0x0010000000000000 ))<<-shiftDist; + } else { + sig |= UINT64_C( 0x0010000000000000 ); + z = sig>>shiftDist; + if ( exact && (uint64_t) (sig<<(-shiftDist & 63)) ) { + softfloat_exceptionFlags |= softfloat_flag_inexact; + } + } + return z; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + invalid: + softfloat_raiseFlags( softfloat_flag_invalid ); + return + (exp == 0x7FF) && sig ? ui64_fromNaN + : sign ? ui64_fromNegOverflow : ui64_fromPosOverflow; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/fall_maxmin.c b/vendor/riscv/riscv-isa-sim/softfloat/fall_maxmin.c new file mode 100644 index 0000000000..32a9ade59e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/fall_maxmin.c @@ -0,0 +1,81 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdio.h> +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +#define COMPARE_MAX(a, b, bits) \ +float ## bits ## _t f ## bits ## _max( float ## bits ## _t a, float ## bits ## _t b ) \ +{ \ + bool greater = f ## bits ## _lt_quiet(b, a) || \ + (f ## bits ## _eq(b, a) && signF ## bits ## UI(b.v)); \ + \ + if (isNaNF ## bits ## UI(a.v) && isNaNF ## bits ## UI(b.v)) { \ + union ui ## bits ## _f ## bits ui; \ + ui.ui = defaultNaNF ## bits ## UI; \ + return ui.f; \ + } else { \ + return greater || isNaNF ## bits ## UI((b).v) ? a : b; \ + } \ +} + +#define COMPARE_MIN(a, b, bits) \ +float ## bits ## _t f ## bits ## _min( float ## bits ## _t a, float ## bits ## _t b ) \ +{ \ + bool less = f ## bits ## _lt_quiet(a, b) || \ + (f ## bits ## _eq(a, b) && signF ## bits ## UI(a.v)); \ + \ + if (isNaNF ## bits ## UI(a.v) && isNaNF ## bits ## UI(b.v)) { \ + union ui ## bits ## _f ## bits ui; \ + ui.ui = defaultNaNF ## bits ## UI; \ + return ui.f; \ + } else { \ + return less || isNaNF ## bits ## UI((b).v) ? a : b; \ + } \ +} + +COMPARE_MAX(a, b, 16); +COMPARE_MAX(a, b, 32); +COMPARE_MAX(a, b, 64); + +COMPARE_MIN(a, b, 16); +COMPARE_MIN(a, b, 32); +COMPARE_MIN(a, b, 64); diff --git a/vendor/riscv/riscv-isa-sim/softfloat/fall_reciprocal.c b/vendor/riscv/riscv-isa-sim/softfloat/fall_reciprocal.c new file mode 100644 index 0000000000..1c96458935 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/fall_reciprocal.c @@ -0,0 +1,392 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <assert.h> +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +static inline uint64_t extract64(uint64_t val, int pos, int len) +{ + assert(pos >= 0 && len > 0 && len <= 64 - pos); + return (val >> pos) & (~UINT64_C(0) >> (64 - len)); +} + +static inline uint64_t make_mask64(int pos, int len) +{ + assert(pos >= 0 && len > 0 && pos < 64 && len <= 64); + return (UINT64_MAX >> (64 - len)) << pos; +} + +//user needs to truncate output to required length +static inline uint64_t rsqrte7(uint64_t val, int e, int s, bool sub) { + uint64_t exp = extract64(val, s, e); + uint64_t sig = extract64(val, 0, s); + uint64_t sign = extract64(val, s + e, 1); + const int p = 7; + + static const uint8_t table[] = { + 52, 51, 50, 48, 47, 46, 44, 43, + 42, 41, 40, 39, 38, 36, 35, 34, + 33, 32, 31, 30, 30, 29, 28, 27, + 26, 25, 24, 23, 23, 22, 21, 20, + 19, 19, 18, 17, 16, 16, 15, 14, + 14, 13, 12, 12, 11, 10, 10, 9, + 9, 8, 7, 7, 6, 6, 5, 4, + 4, 3, 3, 2, 2, 1, 1, 0, + 127, 125, 123, 121, 119, 118, 116, 114, + 113, 111, 109, 108, 106, 105, 103, 102, + 100, 99, 97, 96, 95, 93, 92, 91, + 90, 88, 87, 86, 85, 84, 83, 82, + 80, 79, 78, 77, 76, 75, 74, 73, + 72, 71, 70, 70, 69, 68, 67, 66, + 65, 64, 63, 63, 62, 61, 60, 59, + 59, 58, 57, 56, 56, 55, 54, 53}; + + if (sub) { + while (extract64(sig, s - 1, 1) == 0) + exp--, sig <<= 1; + + sig = (sig << 1) & make_mask64(0 ,s); + } + + int idx = ((exp & 1) << (p-1)) | (sig >> (s-p+1)); + uint64_t out_sig = (uint64_t)(table[idx]) << (s-p); + uint64_t out_exp = (3 * make_mask64(0, e - 1) + ~exp) / 2; + + return (sign << (s+e)) | (out_exp << s) | out_sig; +} + +float16_t f16_rsqrte7(float16_t in) +{ + union ui16_f16 uA; + + uA.f = in; + unsigned int ret = f16_classify(in); + bool sub = false; + switch(ret) { + case 0x001: // -inf + case 0x002: // -normal + case 0x004: // -subnormal + case 0x100: // sNaN + softfloat_exceptionFlags |= softfloat_flag_invalid; + case 0x200: //qNaN + uA.ui = defaultNaNF16UI; + break; + case 0x008: // -0 + uA.ui = 0xfc00; + softfloat_exceptionFlags |= softfloat_flag_infinite; + break; + case 0x010: // +0 + uA.ui = 0x7c00; + softfloat_exceptionFlags |= softfloat_flag_infinite; + break; + case 0x080: //+inf + uA.ui = 0x0; + break; + case 0x020: //+ sub + sub = true; + default: // +num + uA.ui = rsqrte7(uA.ui, 5, 10, sub); + break; + } + + return uA.f; +} + +float32_t f32_rsqrte7(float32_t in) +{ + union ui32_f32 uA; + + uA.f = in; + unsigned int ret = f32_classify(in); + bool sub = false; + switch(ret) { + case 0x001: // -inf + case 0x002: // -normal + case 0x004: // -subnormal + case 0x100: // sNaN + softfloat_exceptionFlags |= softfloat_flag_invalid; + case 0x200: //qNaN + uA.ui = defaultNaNF32UI; + break; + case 0x008: // -0 + uA.ui = 0xff800000; + softfloat_exceptionFlags |= softfloat_flag_infinite; + break; + case 0x010: // +0 + uA.ui = 0x7f800000; + softfloat_exceptionFlags |= softfloat_flag_infinite; + break; + case 0x080: //+inf + uA.ui = 0x0; + break; + case 0x020: //+ sub + sub = true; + default: // +num + uA.ui = rsqrte7(uA.ui, 8, 23, sub); + break; + } + + return uA.f; +} + +float64_t f64_rsqrte7(float64_t in) +{ + union ui64_f64 uA; + + uA.f = in; + unsigned int ret = f64_classify(in); + bool sub = false; + switch(ret) { + case 0x001: // -inf + case 0x002: // -normal + case 0x004: // -subnormal + case 0x100: // sNaN + softfloat_exceptionFlags |= softfloat_flag_invalid; + case 0x200: //qNaN + uA.ui = defaultNaNF64UI; + break; + case 0x008: // -0 + uA.ui = 0xfff0000000000000ul; + softfloat_exceptionFlags |= softfloat_flag_infinite; + break; + case 0x010: // +0 + uA.ui = 0x7ff0000000000000ul; + softfloat_exceptionFlags |= softfloat_flag_infinite; + break; + case 0x080: //+inf + uA.ui = 0x0; + break; + case 0x020: //+ sub + sub = true; + default: // +num + uA.ui = rsqrte7(uA.ui, 11, 52, sub); + break; + } + + return uA.f; +} + +//user needs to truncate output to required length +static inline uint64_t recip7(uint64_t val, int e, int s, int rm, bool sub, + bool *round_abnormal) +{ + uint64_t exp = extract64(val, s, e); + uint64_t sig = extract64(val, 0, s); + uint64_t sign = extract64(val, s + e, 1); + const int p = 7; + + static const uint8_t table[] = { + 127, 125, 123, 121, 119, 117, 116, 114, + 112, 110, 109, 107, 105, 104, 102, 100, + 99, 97, 96, 94, 93, 91, 90, 88, + 87, 85, 84, 83, 81, 80, 79, 77, + 76, 75, 74, 72, 71, 70, 69, 68, + 66, 65, 64, 63, 62, 61, 60, 59, + 58, 57, 56, 55, 54, 53, 52, 51, + 50, 49, 48, 47, 46, 45, 44, 43, + 42, 41, 40, 40, 39, 38, 37, 36, + 35, 35, 34, 33, 32, 31, 31, 30, + 29, 28, 28, 27, 26, 25, 25, 24, + 23, 23, 22, 21, 21, 20, 19, 19, + 18, 17, 17, 16, 15, 15, 14, 14, + 13, 12, 12, 11, 11, 10, 9, 9, + 8, 8, 7, 7, 6, 5, 5, 4, + 4, 3, 3, 2, 2, 1, 1, 0}; + + if (sub) { + while (extract64(sig, s - 1, 1) == 0) + exp--, sig <<= 1; + + sig = (sig << 1) & make_mask64(0 ,s); + + if (exp != 0 && exp != UINT64_MAX) { + *round_abnormal = true; + if (rm == 1 || + (rm == 2 && !sign) || + (rm == 3 && sign)) + return ((sign << (s+e)) | make_mask64(s, e)) - 1; + else + return (sign << (s+e)) | make_mask64(s, e); + } + } + + int idx = sig >> (s-p); + uint64_t out_sig = (uint64_t)(table[idx]) << (s-p); + uint64_t out_exp = 2 * make_mask64(0, e - 1) + ~exp; + if (out_exp == 0 || out_exp == UINT64_MAX) { + out_sig = (out_sig >> 1) | make_mask64(s - 1, 1); + if (out_exp == UINT64_MAX) { + out_sig >>= 1; + out_exp = 0; + } + } + + return (sign << (s+e)) | (out_exp << s) | out_sig; +} + +float16_t f16_recip7(float16_t in) +{ + union ui16_f16 uA; + + uA.f = in; + unsigned int ret = f16_classify(in); + bool sub = false; + bool round_abnormal = false; + switch(ret) { + case 0x001: // -inf + uA.ui = 0x8000; + break; + case 0x080: //+inf + uA.ui = 0x0; + break; + case 0x008: // -0 + uA.ui = 0xfc00; + softfloat_exceptionFlags |= softfloat_flag_infinite; + break; + case 0x010: // +0 + uA.ui = 0x7c00; + softfloat_exceptionFlags |= softfloat_flag_infinite; + break; + case 0x100: // sNaN + softfloat_exceptionFlags |= softfloat_flag_invalid; + case 0x200: //qNaN + uA.ui = defaultNaNF16UI; + break; + case 0x004: // -subnormal + case 0x020: //+ sub + sub = true; + default: // +- normal + uA.ui = recip7(uA.ui, 5, 10, + softfloat_roundingMode, sub, &round_abnormal); + if (round_abnormal) + softfloat_exceptionFlags |= softfloat_flag_inexact | + softfloat_flag_overflow; + break; + } + + return uA.f; +} + +float32_t f32_recip7(float32_t in) +{ + union ui32_f32 uA; + + uA.f = in; + unsigned int ret = f32_classify(in); + bool sub = false; + bool round_abnormal = false; + switch(ret) { + case 0x001: // -inf + uA.ui = 0x80000000; + break; + case 0x080: //+inf + uA.ui = 0x0; + break; + case 0x008: // -0 + uA.ui = 0xff800000; + softfloat_exceptionFlags |= softfloat_flag_infinite; + break; + case 0x010: // +0 + uA.ui = 0x7f800000; + softfloat_exceptionFlags |= softfloat_flag_infinite; + break; + case 0x100: // sNaN + softfloat_exceptionFlags |= softfloat_flag_invalid; + case 0x200: //qNaN + uA.ui = defaultNaNF32UI; + break; + case 0x004: // -subnormal + case 0x020: //+ sub + sub = true; + default: // +- normal + uA.ui = recip7(uA.ui, 8, 23, + softfloat_roundingMode, sub, &round_abnormal); + if (round_abnormal) + softfloat_exceptionFlags |= softfloat_flag_inexact | + softfloat_flag_overflow; + break; + } + + return uA.f; +} + +float64_t f64_recip7(float64_t in) +{ + union ui64_f64 uA; + + uA.f = in; + unsigned int ret = f64_classify(in); + bool sub = false; + bool round_abnormal = false; + switch(ret) { + case 0x001: // -inf + uA.ui = 0x8000000000000000; + break; + case 0x080: //+inf + uA.ui = 0x0; + break; + case 0x008: // -0 + uA.ui = 0xfff0000000000000; + softfloat_exceptionFlags |= softfloat_flag_infinite; + break; + case 0x010: // +0 + uA.ui = 0x7ff0000000000000; + softfloat_exceptionFlags |= softfloat_flag_infinite; + break; + case 0x100: // sNaN + softfloat_exceptionFlags |= softfloat_flag_invalid; + case 0x200: //qNaN + uA.ui = defaultNaNF64UI; + break; + case 0x004: // -subnormal + case 0x020: //+ sub + sub = true; + default: // +- normal + uA.ui = recip7(uA.ui, 11, 52, + softfloat_roundingMode, sub, &round_abnormal); + if (round_abnormal) + softfloat_exceptionFlags |= softfloat_flag_inexact | + softfloat_flag_overflow; + break; + } + + return uA.f; +} diff --git a/vendor/riscv/riscv-isa-sim/softfloat/i32_to_f128.c b/vendor/riscv/riscv-isa-sim/softfloat/i32_to_f128.c new file mode 100644 index 0000000000..af7268aede --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/i32_to_f128.c @@ -0,0 +1,64 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "softfloat.h" + +float128_t i32_to_f128( int32_t a ) +{ + uint_fast64_t uiZ64; + bool sign; + uint_fast32_t absA; + int_fast8_t shiftDist; + union ui128_f128 uZ; + + uiZ64 = 0; + if ( a ) { + sign = (a < 0); + absA = sign ? -(uint_fast32_t) a : (uint_fast32_t) a; + shiftDist = softfloat_countLeadingZeros32( absA ) + 17; + uiZ64 = + packToF128UI64( + sign, 0x402E - shiftDist, (uint_fast64_t) absA<<shiftDist ); + } + uZ.ui.v64 = uiZ64; + uZ.ui.v0 = 0; + return uZ.f; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/i32_to_f16.c b/vendor/riscv/riscv-isa-sim/softfloat/i32_to_f16.c new file mode 100644 index 0000000000..7442972812 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/i32_to_f16.c @@ -0,0 +1,71 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "softfloat.h" + +float16_t i32_to_f16( int32_t a ) +{ + bool sign; + uint_fast32_t absA; + int_fast8_t shiftDist; + union ui16_f16 u; + uint_fast16_t sig; + + sign = (a < 0); + absA = sign ? -(uint_fast32_t) a : (uint_fast32_t) a; + shiftDist = softfloat_countLeadingZeros32( absA ) - 21; + if ( 0 <= shiftDist ) { + u.ui = + a ? packToF16UI( + sign, 0x18 - shiftDist, (uint_fast16_t) absA<<shiftDist ) + : 0; + return u.f; + } else { + shiftDist += 4; + sig = + (shiftDist < 0) + ? absA>>(-shiftDist) + | ((uint32_t) (absA<<(shiftDist & 31)) != 0) + : (uint_fast16_t) absA<<shiftDist; + return softfloat_roundPackToF16( sign, 0x1C - shiftDist, sig ); + } + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/i32_to_f32.c b/vendor/riscv/riscv-isa-sim/softfloat/i32_to_f32.c new file mode 100644 index 0000000000..b1aedbacf9 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/i32_to_f32.c @@ -0,0 +1,58 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "softfloat.h" + +float32_t i32_to_f32( int32_t a ) +{ + bool sign; + union ui32_f32 uZ; + uint_fast32_t absA; + + sign = (a < 0); + if ( ! (a & 0x7FFFFFFF) ) { + uZ.ui = sign ? packToF32UI( 1, 0x9E, 0 ) : 0; + return uZ.f; + } + absA = sign ? -(uint_fast32_t) a : (uint_fast32_t) a; + return softfloat_normRoundPackToF32( sign, 0x9C, absA ); + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/i32_to_f64.c b/vendor/riscv/riscv-isa-sim/softfloat/i32_to_f64.c new file mode 100644 index 0000000000..d3901eb4af --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/i32_to_f64.c @@ -0,0 +1,65 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "softfloat.h" + +float64_t i32_to_f64( int32_t a ) +{ + uint_fast64_t uiZ; + bool sign; + uint_fast32_t absA; + int_fast8_t shiftDist; + union ui64_f64 uZ; + + if ( ! a ) { + uiZ = 0; + } else { + sign = (a < 0); + absA = sign ? -(uint_fast32_t) a : (uint_fast32_t) a; + shiftDist = softfloat_countLeadingZeros32( absA ) + 21; + uiZ = + packToF64UI( + sign, 0x432 - shiftDist, (uint_fast64_t) absA<<shiftDist ); + } + uZ.ui = uiZ; + return uZ.f; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/i64_to_f128.c b/vendor/riscv/riscv-isa-sim/softfloat/i64_to_f128.c new file mode 100644 index 0000000000..8eddbae2d7 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/i64_to_f128.c @@ -0,0 +1,72 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "softfloat.h" + +float128_t i64_to_f128( int64_t a ) +{ + uint_fast64_t uiZ64, uiZ0; + bool sign; + uint_fast64_t absA; + int_fast8_t shiftDist; + struct uint128 zSig; + union ui128_f128 uZ; + + if ( ! a ) { + uiZ64 = 0; + uiZ0 = 0; + } else { + sign = (a < 0); + absA = sign ? -(uint_fast64_t) a : (uint_fast64_t) a; + shiftDist = softfloat_countLeadingZeros64( absA ) + 49; + if ( 64 <= shiftDist ) { + zSig.v64 = absA<<(shiftDist - 64); + zSig.v0 = 0; + } else { + zSig = softfloat_shortShiftLeft128( 0, absA, shiftDist ); + } + uiZ64 = packToF128UI64( sign, 0x406E - shiftDist, zSig.v64 ); + uiZ0 = zSig.v0; + } + uZ.ui.v64 = uiZ64; + uZ.ui.v0 = uiZ0; + return uZ.f; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/i64_to_f16.c b/vendor/riscv/riscv-isa-sim/softfloat/i64_to_f16.c new file mode 100644 index 0000000000..56f0191287 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/i64_to_f16.c @@ -0,0 +1,70 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "softfloat.h" + +float16_t i64_to_f16( int64_t a ) +{ + bool sign; + uint_fast64_t absA; + int_fast8_t shiftDist; + union ui16_f16 u; + uint_fast16_t sig; + + sign = (a < 0); + absA = sign ? -(uint_fast64_t) a : (uint_fast64_t) a; + shiftDist = softfloat_countLeadingZeros64( absA ) - 53; + if ( 0 <= shiftDist ) { + u.ui = + a ? packToF16UI( + sign, 0x18 - shiftDist, (uint_fast16_t) absA<<shiftDist ) + : 0; + return u.f; + } else { + shiftDist += 4; + sig = + (shiftDist < 0) + ? softfloat_shortShiftRightJam64( absA, -shiftDist ) + : (uint_fast16_t) absA<<shiftDist; + return softfloat_roundPackToF16( sign, 0x1C - shiftDist, sig ); + } + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/i64_to_f32.c b/vendor/riscv/riscv-isa-sim/softfloat/i64_to_f32.c new file mode 100644 index 0000000000..e8a3494cc9 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/i64_to_f32.c @@ -0,0 +1,70 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "softfloat.h" + +float32_t i64_to_f32( int64_t a ) +{ + bool sign; + uint_fast64_t absA; + int_fast8_t shiftDist; + union ui32_f32 u; + uint_fast32_t sig; + + sign = (a < 0); + absA = sign ? -(uint_fast64_t) a : (uint_fast64_t) a; + shiftDist = softfloat_countLeadingZeros64( absA ) - 40; + if ( 0 <= shiftDist ) { + u.ui = + a ? packToF32UI( + sign, 0x95 - shiftDist, (uint_fast32_t) absA<<shiftDist ) + : 0; + return u.f; + } else { + shiftDist += 7; + sig = + (shiftDist < 0) + ? softfloat_shortShiftRightJam64( absA, -shiftDist ) + : (uint_fast32_t) absA<<shiftDist; + return softfloat_roundPackToF32( sign, 0x9C - shiftDist, sig ); + } + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/i64_to_f64.c b/vendor/riscv/riscv-isa-sim/softfloat/i64_to_f64.c new file mode 100644 index 0000000000..392fef9dcd --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/i64_to_f64.c @@ -0,0 +1,58 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "softfloat.h" + +float64_t i64_to_f64( int64_t a ) +{ + bool sign; + union ui64_f64 uZ; + uint_fast64_t absA; + + sign = (a < 0); + if ( ! (a & UINT64_C( 0x7FFFFFFFFFFFFFFF )) ) { + uZ.ui = sign ? packToF64UI( 1, 0x43E, 0 ) : 0; + return uZ.f; + } + absA = sign ? -(uint_fast64_t) a : (uint_fast64_t) a; + return softfloat_normRoundPackToF64( sign, 0x43C, absA ); + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/internals.h b/vendor/riscv/riscv-isa-sim/softfloat/internals.h new file mode 100644 index 0000000000..55585e967e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/internals.h @@ -0,0 +1,286 @@ + +/*============================================================================ + +This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the +University of California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#ifndef internals_h +#define internals_h 1 + +#include <stdbool.h> +#include <stdint.h> +#include "primitives.h" +#include "softfloat_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +union ui16_f16 { uint16_t ui; float16_t f; }; +union ui32_f32 { uint32_t ui; float32_t f; }; +union ui64_f64 { uint64_t ui; float64_t f; }; + +#ifdef SOFTFLOAT_FAST_INT64 +union extF80M_extF80 { struct extFloat80M fM; extFloat80_t f; }; +union ui128_f128 { struct uint128 ui; float128_t f; }; +#endif + +enum { + softfloat_mulAdd_subC = 1, + softfloat_mulAdd_subProd = 2 +}; + +/*---------------------------------------------------------------------------- +*----------------------------------------------------------------------------*/ +uint_fast32_t softfloat_roundToUI32( bool, uint_fast64_t, uint_fast8_t, bool ); + +#ifdef SOFTFLOAT_FAST_INT64 +uint_fast64_t + softfloat_roundToUI64( + bool, uint_fast64_t, uint_fast64_t, uint_fast8_t, bool ); +#else +uint_fast64_t softfloat_roundMToUI64( bool, uint32_t *, uint_fast8_t, bool ); +#endif + +int_fast32_t softfloat_roundToI32( bool, uint_fast64_t, uint_fast8_t, bool ); + +#ifdef SOFTFLOAT_FAST_INT64 +int_fast64_t + softfloat_roundToI64( + bool, uint_fast64_t, uint_fast64_t, uint_fast8_t, bool ); +#else +int_fast64_t softfloat_roundMToI64( bool, uint32_t *, uint_fast8_t, bool ); +#endif + +/*---------------------------------------------------------------------------- +*----------------------------------------------------------------------------*/ +#define signF16UI( a ) ((bool) ((uint16_t) (a)>>15)) +#define expF16UI( a ) ((int_fast8_t) ((a)>>10) & 0x1F) +#define fracF16UI( a ) ((a) & 0x03FF) +#define packToF16UI( sign, exp, sig ) (((uint16_t) (sign)<<15) + ((uint16_t) (exp)<<10) + (sig)) + +#define isNaNF16UI( a ) (((~(a) & 0x7C00) == 0) && ((a) & 0x03FF)) + +struct exp8_sig16 { int_fast8_t exp; uint_fast16_t sig; }; +struct exp8_sig16 softfloat_normSubnormalF16Sig( uint_fast16_t ); + +float16_t softfloat_roundPackToF16( bool, int_fast16_t, uint_fast16_t ); +float16_t softfloat_normRoundPackToF16( bool, int_fast16_t, uint_fast16_t ); + +float16_t softfloat_addMagsF16( uint_fast16_t, uint_fast16_t ); +float16_t softfloat_subMagsF16( uint_fast16_t, uint_fast16_t ); +float16_t + softfloat_mulAddF16( + uint_fast16_t, uint_fast16_t, uint_fast16_t, uint_fast8_t ); + +/*---------------------------------------------------------------------------- +*----------------------------------------------------------------------------*/ +#define signF32UI( a ) ((bool) ((uint32_t) (a)>>31)) +#define expF32UI( a ) ((int_fast16_t) ((a)>>23) & 0xFF) +#define fracF32UI( a ) ((a) & 0x007FFFFF) +#define packToF32UI( sign, exp, sig ) (((uint32_t) (sign)<<31) + ((uint32_t) (exp)<<23) + (sig)) + +#define isNaNF32UI( a ) (((~(a) & 0x7F800000) == 0) && ((a) & 0x007FFFFF)) + +struct exp16_sig32 { int_fast16_t exp; uint_fast32_t sig; }; +struct exp16_sig32 softfloat_normSubnormalF32Sig( uint_fast32_t ); + +float32_t softfloat_roundPackToF32( bool, int_fast16_t, uint_fast32_t ); +float32_t softfloat_normRoundPackToF32( bool, int_fast16_t, uint_fast32_t ); + +float32_t softfloat_addMagsF32( uint_fast32_t, uint_fast32_t ); +float32_t softfloat_subMagsF32( uint_fast32_t, uint_fast32_t ); +float32_t + softfloat_mulAddF32( + uint_fast32_t, uint_fast32_t, uint_fast32_t, uint_fast8_t ); + +/*---------------------------------------------------------------------------- +*----------------------------------------------------------------------------*/ +#define signF64UI( a ) ((bool) ((uint64_t) (a)>>63)) +#define expF64UI( a ) ((int_fast16_t) ((a)>>52) & 0x7FF) +#define fracF64UI( a ) ((a) & UINT64_C( 0x000FFFFFFFFFFFFF )) +#define packToF64UI( sign, exp, sig ) ((uint64_t) (((uint_fast64_t) (sign)<<63) + ((uint_fast64_t) (exp)<<52) + (sig))) + +#define isNaNF64UI( a ) (((~(a) & UINT64_C( 0x7FF0000000000000 )) == 0) && ((a) & UINT64_C( 0x000FFFFFFFFFFFFF ))) + +struct exp16_sig64 { int_fast16_t exp; uint_fast64_t sig; }; +struct exp16_sig64 softfloat_normSubnormalF64Sig( uint_fast64_t ); + +float64_t softfloat_roundPackToF64( bool, int_fast16_t, uint_fast64_t ); +float64_t softfloat_normRoundPackToF64( bool, int_fast16_t, uint_fast64_t ); + +float64_t softfloat_addMagsF64( uint_fast64_t, uint_fast64_t, bool ); +float64_t softfloat_subMagsF64( uint_fast64_t, uint_fast64_t, bool ); +float64_t + softfloat_mulAddF64( + uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast8_t ); + +/*---------------------------------------------------------------------------- +*----------------------------------------------------------------------------*/ +#define signExtF80UI64( a64 ) ((bool) ((uint16_t) (a64)>>15)) +#define expExtF80UI64( a64 ) ((a64) & 0x7FFF) +#define packToExtF80UI64( sign, exp ) ((uint_fast16_t) (sign)<<15 | (exp)) + +#define isNaNExtF80UI( a64, a0 ) ((((a64) & 0x7FFF) == 0x7FFF) && ((a0) & UINT64_C( 0x7FFFFFFFFFFFFFFF ))) + +#ifdef SOFTFLOAT_FAST_INT64 + +/*---------------------------------------------------------------------------- +*----------------------------------------------------------------------------*/ + +struct exp32_sig64 { int_fast32_t exp; uint64_t sig; }; +struct exp32_sig64 softfloat_normSubnormalExtF80Sig( uint_fast64_t ); + +extFloat80_t + softfloat_roundPackToExtF80( + bool, int_fast32_t, uint_fast64_t, uint_fast64_t, uint_fast8_t ); +extFloat80_t + softfloat_normRoundPackToExtF80( + bool, int_fast32_t, uint_fast64_t, uint_fast64_t, uint_fast8_t ); + +extFloat80_t + softfloat_addMagsExtF80( + uint_fast16_t, uint_fast64_t, uint_fast16_t, uint_fast64_t, bool ); +extFloat80_t + softfloat_subMagsExtF80( + uint_fast16_t, uint_fast64_t, uint_fast16_t, uint_fast64_t, bool ); + +/*---------------------------------------------------------------------------- +*----------------------------------------------------------------------------*/ +#define signF128UI64( a64 ) ((bool) ((uint64_t) (a64)>>63)) +#define expF128UI64( a64 ) ((int_fast32_t) ((a64)>>48) & 0x7FFF) +#define fracF128UI64( a64 ) ((a64) & UINT64_C( 0x0000FFFFFFFFFFFF )) +#define packToF128UI64( sign, exp, sig64 ) (((uint_fast64_t) (sign)<<63) + ((uint_fast64_t) (exp)<<48) + (sig64)) + +#define isNaNF128UI( a64, a0 ) (((~(a64) & UINT64_C( 0x7FFF000000000000 )) == 0) && (a0 || ((a64) & UINT64_C( 0x0000FFFFFFFFFFFF )))) + +struct exp32_sig128 { int_fast32_t exp; struct uint128 sig; }; +struct exp32_sig128 + softfloat_normSubnormalF128Sig( uint_fast64_t, uint_fast64_t ); + +float128_t + softfloat_roundPackToF128( + bool, int_fast32_t, uint_fast64_t, uint_fast64_t, uint_fast64_t ); +float128_t + softfloat_normRoundPackToF128( + bool, int_fast32_t, uint_fast64_t, uint_fast64_t ); + +float128_t + softfloat_addMagsF128( + uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast64_t, bool ); +float128_t + softfloat_subMagsF128( + uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast64_t, bool ); +float128_t + softfloat_mulAddF128( + uint_fast64_t, + uint_fast64_t, + uint_fast64_t, + uint_fast64_t, + uint_fast64_t, + uint_fast64_t, + uint_fast8_t + ); + +#else + +/*---------------------------------------------------------------------------- +*----------------------------------------------------------------------------*/ + +bool + softfloat_tryPropagateNaNExtF80M( + const struct extFloat80M *, + const struct extFloat80M *, + struct extFloat80M * + ); +void softfloat_invalidExtF80M( struct extFloat80M * ); + +int softfloat_normExtF80SigM( uint64_t * ); + +void + softfloat_roundPackMToExtF80M( + bool, int32_t, uint32_t *, uint_fast8_t, struct extFloat80M * ); +void + softfloat_normRoundPackMToExtF80M( + bool, int32_t, uint32_t *, uint_fast8_t, struct extFloat80M * ); + +void + softfloat_addExtF80M( + const struct extFloat80M *, + const struct extFloat80M *, + struct extFloat80M *, + bool + ); + +int + softfloat_compareNonnormExtF80M( + const struct extFloat80M *, const struct extFloat80M * ); + +/*---------------------------------------------------------------------------- +*----------------------------------------------------------------------------*/ +#define signF128UI96( a96 ) ((bool) ((uint32_t) (a96)>>31)) +#define expF128UI96( a96 ) ((int32_t) ((a96)>>16) & 0x7FFF) +#define fracF128UI96( a96 ) ((a96) & 0x0000FFFF) +#define packToF128UI96( sign, exp, sig96 ) (((uint32_t) (sign)<<31) + ((uint32_t) (exp)<<16) + (sig96)) + +bool softfloat_isNaNF128M( const uint32_t * ); + +bool + softfloat_tryPropagateNaNF128M( + const uint32_t *, const uint32_t *, uint32_t * ); +void softfloat_invalidF128M( uint32_t * ); + +int softfloat_shiftNormSigF128M( const uint32_t *, uint_fast8_t, uint32_t * ); + +void softfloat_roundPackMToF128M( bool, int32_t, uint32_t *, uint32_t * ); +void softfloat_normRoundPackMToF128M( bool, int32_t, uint32_t *, uint32_t * ); + +void + softfloat_addF128M( const uint32_t *, const uint32_t *, uint32_t *, bool ); +void + softfloat_mulAddF128M( + const uint32_t *, + const uint32_t *, + const uint32_t *, + uint32_t *, + uint_fast8_t + ); + +#endif + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/platform.h b/vendor/riscv/riscv-isa-sim/softfloat/platform.h new file mode 100644 index 0000000000..55de1941a7 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/platform.h @@ -0,0 +1,52 @@ + +/*============================================================================ + +This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3a, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +/*---------------------------------------------------------------------------- +*----------------------------------------------------------------------------*/ +#include "config.h" +#ifndef WORDS_BIGENDIAN +#define LITTLEENDIAN 1 +#endif + +#define INLINE_LEVEL 5 +#define SOFTFLOAT_FAST_INT64 +#define SOFTFLOAT_FAST_DIV64TO32 +#define SOFTFLOAT_ROUND_ODD + +/*---------------------------------------------------------------------------- +*----------------------------------------------------------------------------*/ +#define INLINE static inline + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/primitiveTypes.h b/vendor/riscv/riscv-isa-sim/softfloat/primitiveTypes.h new file mode 100644 index 0000000000..b112049193 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/primitiveTypes.h @@ -0,0 +1,86 @@ + +/*============================================================================ + +This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3a, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#ifndef primitiveTypes_h +#define primitiveTypes_h 1 + +#include <stdint.h> +#include "platform.h" + +#ifdef SOFTFLOAT_FAST_INT64 + +#ifdef LITTLEENDIAN +struct uint128 { uint64_t v0, v64; }; +struct uint64_extra { uint64_t extra, v; }; +struct uint128_extra { uint64_t extra; struct uint128 v; }; +#else +struct uint128 { uint64_t v64, v0; }; +struct uint64_extra { uint64_t v, extra; }; +struct uint128_extra { struct uint128 v; uint64_t extra; }; +#endif + +#endif + +/*---------------------------------------------------------------------------- +| These macros are used to isolate the differences in word order between big- +| endian and little-endian platforms. +*----------------------------------------------------------------------------*/ +#ifdef LITTLEENDIAN +#define wordIncr 1 +#define indexWord( total, n ) (n) +#define indexWordHi( total ) ((total) - 1) +#define indexWordLo( total ) 0 +#define indexMultiword( total, m, n ) (n) +#define indexMultiwordHi( total, n ) ((total) - (n)) +#define indexMultiwordLo( total, n ) 0 +#define indexMultiwordHiBut( total, n ) (n) +#define indexMultiwordLoBut( total, n ) 0 +#define INIT_UINTM4( v3, v2, v1, v0 ) { v0, v1, v2, v3 } +#else +#define wordIncr -1 +#define indexWord( total, n ) ((total) - 1 - (n)) +#define indexWordHi( total ) 0 +#define indexWordLo( total ) ((total) - 1) +#define indexMultiword( total, m, n ) ((total) - 1 - (m)) +#define indexMultiwordHi( total, n ) 0 +#define indexMultiwordLo( total, n ) ((total) - (n)) +#define indexMultiwordHiBut( total, n ) 0 +#define indexMultiwordLoBut( total, n ) (n) +#define INIT_UINTM4( v3, v2, v1, v0 ) { v3, v2, v1, v0 } +#endif + +#endif + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/primitives.h b/vendor/riscv/riscv-isa-sim/softfloat/primitives.h new file mode 100644 index 0000000000..1acc8a8ae1 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/primitives.h @@ -0,0 +1,1168 @@ + +/*============================================================================ + +This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the +University of California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#ifndef primitives_h +#define primitives_h 1 + +#include <stdbool.h> +#include <stdint.h> +#include "primitiveTypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef softfloat_shortShiftRightJam64 +/*---------------------------------------------------------------------------- +| Shifts 'a' right by the number of bits given in 'dist', which must be in +| the range 1 to 63. If any nonzero bits are shifted off, they are "jammed" +| into the least-significant bit of the shifted value by setting the least- +| significant bit to 1. This shifted-and-jammed value is returned. +*----------------------------------------------------------------------------*/ +#if defined INLINE_LEVEL && (2 <= INLINE_LEVEL) +INLINE +uint64_t softfloat_shortShiftRightJam64( uint64_t a, uint_fast8_t dist ) + { return a>>dist | ((a & (((uint_fast64_t) 1<<dist) - 1)) != 0); } +#else +uint64_t softfloat_shortShiftRightJam64( uint64_t a, uint_fast8_t dist ); +#endif +#endif + +#ifndef softfloat_shiftRightJam32 +/*---------------------------------------------------------------------------- +| Shifts 'a' right by the number of bits given in 'dist', which must not +| be zero. If any nonzero bits are shifted off, they are "jammed" into the +| least-significant bit of the shifted value by setting the least-significant +| bit to 1. This shifted-and-jammed value is returned. +| The value of 'dist' can be arbitrarily large. In particular, if 'dist' is +| greater than 32, the result will be either 0 or 1, depending on whether 'a' +| is zero or nonzero. +*----------------------------------------------------------------------------*/ +#if defined INLINE_LEVEL && (2 <= INLINE_LEVEL) +INLINE uint32_t softfloat_shiftRightJam32( uint32_t a, uint_fast16_t dist ) +{ + return + (dist < 31) ? a>>dist | ((uint32_t) (a<<(-dist & 31)) != 0) : (a != 0); +} +#else +uint32_t softfloat_shiftRightJam32( uint32_t a, uint_fast16_t dist ); +#endif +#endif + +#ifndef softfloat_shiftRightJam64 +/*---------------------------------------------------------------------------- +| Shifts 'a' right by the number of bits given in 'dist', which must not +| be zero. If any nonzero bits are shifted off, they are "jammed" into the +| least-significant bit of the shifted value by setting the least-significant +| bit to 1. This shifted-and-jammed value is returned. +| The value of 'dist' can be arbitrarily large. In particular, if 'dist' is +| greater than 64, the result will be either 0 or 1, depending on whether 'a' +| is zero or nonzero. +*----------------------------------------------------------------------------*/ +#if defined INLINE_LEVEL && (3 <= INLINE_LEVEL) +INLINE uint64_t softfloat_shiftRightJam64( uint64_t a, uint_fast32_t dist ) +{ + return + (dist < 63) ? a>>dist | ((uint64_t) (a<<(-dist & 63)) != 0) : (a != 0); +} +#else +uint64_t softfloat_shiftRightJam64( uint64_t a, uint_fast32_t dist ); +#endif +#endif + +/*---------------------------------------------------------------------------- +| A constant table that translates an 8-bit unsigned integer (the array index) +| into the number of leading 0 bits before the most-significant 1 of that +| integer. For integer zero (index 0), the corresponding table element is 8. +*----------------------------------------------------------------------------*/ +extern const uint_least8_t softfloat_countLeadingZeros8[256]; + +#ifndef softfloat_countLeadingZeros16 +/*---------------------------------------------------------------------------- +| Returns the number of leading 0 bits before the most-significant 1 bit of +| 'a'. If 'a' is zero, 16 is returned. +*----------------------------------------------------------------------------*/ +#if defined INLINE_LEVEL && (2 <= INLINE_LEVEL) +INLINE uint_fast8_t softfloat_countLeadingZeros16( uint16_t a ) +{ + uint_fast8_t count = 8; + if ( 0x100 <= a ) { + count = 0; + a >>= 8; + } + count += softfloat_countLeadingZeros8[a]; + return count; +} +#else +uint_fast8_t softfloat_countLeadingZeros16( uint16_t a ); +#endif +#endif + +#ifndef softfloat_countLeadingZeros32 +/*---------------------------------------------------------------------------- +| Returns the number of leading 0 bits before the most-significant 1 bit of +| 'a'. If 'a' is zero, 32 is returned. +*----------------------------------------------------------------------------*/ +#if defined INLINE_LEVEL && (3 <= INLINE_LEVEL) +INLINE uint_fast8_t softfloat_countLeadingZeros32( uint32_t a ) +{ + uint_fast8_t count = 0; + if ( a < 0x10000 ) { + count = 16; + a <<= 16; + } + if ( a < 0x1000000 ) { + count += 8; + a <<= 8; + } + count += softfloat_countLeadingZeros8[a>>24]; + return count; +} +#else +uint_fast8_t softfloat_countLeadingZeros32( uint32_t a ); +#endif +#endif + +#ifndef softfloat_countLeadingZeros64 +/*---------------------------------------------------------------------------- +| Returns the number of leading 0 bits before the most-significant 1 bit of +| 'a'. If 'a' is zero, 64 is returned. +*----------------------------------------------------------------------------*/ +uint_fast8_t softfloat_countLeadingZeros64( uint64_t a ); +#endif + +extern const uint16_t softfloat_approxRecip_1k0s[16]; +extern const uint16_t softfloat_approxRecip_1k1s[16]; + +#ifndef softfloat_approxRecip32_1 +/*---------------------------------------------------------------------------- +| Returns an approximation to the reciprocal of the number represented by 'a', +| where 'a' is interpreted as an unsigned fixed-point number with one integer +| bit and 31 fraction bits. The 'a' input must be "normalized", meaning that +| its most-significant bit (bit 31) must be 1. Thus, if A is the value of +| the fixed-point interpretation of 'a', then 1 <= A < 2. The returned value +| is interpreted as a pure unsigned fraction, having no integer bits and 32 +| fraction bits. The approximation returned is never greater than the true +| reciprocal 1/A, and it differs from the true reciprocal by at most 2.006 ulp +| (units in the last place). +*----------------------------------------------------------------------------*/ +#ifdef SOFTFLOAT_FAST_DIV64TO32 +#define softfloat_approxRecip32_1( a ) ((uint32_t) (UINT64_C( 0x7FFFFFFFFFFFFFFF ) / (uint32_t) (a))) +#else +uint32_t softfloat_approxRecip32_1( uint32_t a ); +#endif +#endif + +extern const uint16_t softfloat_approxRecipSqrt_1k0s[16]; +extern const uint16_t softfloat_approxRecipSqrt_1k1s[16]; + +#ifndef softfloat_approxRecipSqrt32_1 +/*---------------------------------------------------------------------------- +| Returns an approximation to the reciprocal of the square root of the number +| represented by 'a', where 'a' is interpreted as an unsigned fixed-point +| number either with one integer bit and 31 fraction bits or with two integer +| bits and 30 fraction bits. The format of 'a' is determined by 'oddExpA', +| which must be either 0 or 1. If 'oddExpA' is 1, 'a' is interpreted as +| having one integer bit, and if 'oddExpA' is 0, 'a' is interpreted as having +| two integer bits. The 'a' input must be "normalized", meaning that its +| most-significant bit (bit 31) must be 1. Thus, if A is the value of the +| fixed-point interpretation of 'a', it follows that 1 <= A < 2 when 'oddExpA' +| is 1, and 2 <= A < 4 when 'oddExpA' is 0. +| The returned value is interpreted as a pure unsigned fraction, having +| no integer bits and 32 fraction bits. The approximation returned is never +| greater than the true reciprocal 1/sqrt(A), and it differs from the true +| reciprocal by at most 2.06 ulp (units in the last place). The approximation +| returned is also always within the range 0.5 to 1; thus, the most- +| significant bit of the result is always set. +*----------------------------------------------------------------------------*/ +uint32_t softfloat_approxRecipSqrt32_1( unsigned int oddExpA, uint32_t a ); +#endif + +#ifdef SOFTFLOAT_FAST_INT64 + +/*---------------------------------------------------------------------------- +| The following functions are needed only when 'SOFTFLOAT_FAST_INT64' is +| defined. +*----------------------------------------------------------------------------*/ + +#ifndef softfloat_eq128 +/*---------------------------------------------------------------------------- +| Returns true if the 128-bit unsigned integer formed by concatenating 'a64' +| and 'a0' is equal to the 128-bit unsigned integer formed by concatenating +| 'b64' and 'b0'. +*----------------------------------------------------------------------------*/ +#if defined INLINE_LEVEL && (1 <= INLINE_LEVEL) +INLINE +bool softfloat_eq128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 ) + { return (a64 == b64) && (a0 == b0); } +#else +bool softfloat_eq128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 ); +#endif +#endif + +#ifndef softfloat_le128 +/*---------------------------------------------------------------------------- +| Returns true if the 128-bit unsigned integer formed by concatenating 'a64' +| and 'a0' is less than or equal to the 128-bit unsigned integer formed by +| concatenating 'b64' and 'b0'. +*----------------------------------------------------------------------------*/ +#if defined INLINE_LEVEL && (2 <= INLINE_LEVEL) +INLINE +bool softfloat_le128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 ) + { return (a64 < b64) || ((a64 == b64) && (a0 <= b0)); } +#else +bool softfloat_le128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 ); +#endif +#endif + +#ifndef softfloat_lt128 +/*---------------------------------------------------------------------------- +| Returns true if the 128-bit unsigned integer formed by concatenating 'a64' +| and 'a0' is less than the 128-bit unsigned integer formed by concatenating +| 'b64' and 'b0'. +*----------------------------------------------------------------------------*/ +#if defined INLINE_LEVEL && (2 <= INLINE_LEVEL) +INLINE +bool softfloat_lt128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 ) + { return (a64 < b64) || ((a64 == b64) && (a0 < b0)); } +#else +bool softfloat_lt128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 ); +#endif +#endif + +#ifndef softfloat_shortShiftLeft128 +/*---------------------------------------------------------------------------- +| Shifts the 128 bits formed by concatenating 'a64' and 'a0' left by the +| number of bits given in 'dist', which must be in the range 1 to 63. +*----------------------------------------------------------------------------*/ +#if defined INLINE_LEVEL && (2 <= INLINE_LEVEL) +INLINE +struct uint128 + softfloat_shortShiftLeft128( uint64_t a64, uint64_t a0, uint_fast8_t dist ) +{ + struct uint128 z; + z.v64 = a64<<dist | a0>>(-dist & 63); + z.v0 = a0<<dist; + return z; +} +#else +struct uint128 + softfloat_shortShiftLeft128( uint64_t a64, uint64_t a0, uint_fast8_t dist ); +#endif +#endif + +#ifndef softfloat_shortShiftRight128 +/*---------------------------------------------------------------------------- +| Shifts the 128 bits formed by concatenating 'a64' and 'a0' right by the +| number of bits given in 'dist', which must be in the range 1 to 63. +*----------------------------------------------------------------------------*/ +#if defined INLINE_LEVEL && (2 <= INLINE_LEVEL) +INLINE +struct uint128 + softfloat_shortShiftRight128( uint64_t a64, uint64_t a0, uint_fast8_t dist ) +{ + struct uint128 z; + z.v64 = a64>>dist; + z.v0 = a64<<(-dist & 63) | a0>>dist; + return z; +} +#else +struct uint128 + softfloat_shortShiftRight128( uint64_t a64, uint64_t a0, uint_fast8_t dist ); +#endif +#endif + +#ifndef softfloat_shortShiftRightJam64Extra +/*---------------------------------------------------------------------------- +| This function is the same as 'softfloat_shiftRightJam64Extra' (below), +| except that 'dist' must be in the range 1 to 63. +*----------------------------------------------------------------------------*/ +#if defined INLINE_LEVEL && (2 <= INLINE_LEVEL) +INLINE +struct uint64_extra + softfloat_shortShiftRightJam64Extra( + uint64_t a, uint64_t extra, uint_fast8_t dist ) +{ + struct uint64_extra z; + z.v = a>>dist; + z.extra = a<<(-dist & 63) | (extra != 0); + return z; +} +#else +struct uint64_extra + softfloat_shortShiftRightJam64Extra( + uint64_t a, uint64_t extra, uint_fast8_t dist ); +#endif +#endif + +#ifndef softfloat_shortShiftRightJam128 +/*---------------------------------------------------------------------------- +| Shifts the 128 bits formed by concatenating 'a64' and 'a0' right by the +| number of bits given in 'dist', which must be in the range 1 to 63. If any +| nonzero bits are shifted off, they are "jammed" into the least-significant +| bit of the shifted value by setting the least-significant bit to 1. This +| shifted-and-jammed value is returned. +*----------------------------------------------------------------------------*/ +#if defined INLINE_LEVEL && (3 <= INLINE_LEVEL) +INLINE +struct uint128 + softfloat_shortShiftRightJam128( + uint64_t a64, uint64_t a0, uint_fast8_t dist ) +{ + uint_fast8_t negDist = -dist; + struct uint128 z; + z.v64 = a64>>dist; + z.v0 = + a64<<(negDist & 63) | a0>>dist + | ((uint64_t) (a0<<(negDist & 63)) != 0); + return z; +} +#else +struct uint128 + softfloat_shortShiftRightJam128( + uint64_t a64, uint64_t a0, uint_fast8_t dist ); +#endif +#endif + +#ifndef softfloat_shortShiftRightJam128Extra +/*---------------------------------------------------------------------------- +| This function is the same as 'softfloat_shiftRightJam128Extra' (below), +| except that 'dist' must be in the range 1 to 63. +*----------------------------------------------------------------------------*/ +#if defined INLINE_LEVEL && (3 <= INLINE_LEVEL) +INLINE +struct uint128_extra + softfloat_shortShiftRightJam128Extra( + uint64_t a64, uint64_t a0, uint64_t extra, uint_fast8_t dist ) +{ + uint_fast8_t negDist = -dist; + struct uint128_extra z; + z.v.v64 = a64>>dist; + z.v.v0 = a64<<(negDist & 63) | a0>>dist; + z.extra = a0<<(negDist & 63) | (extra != 0); + return z; +} +#else +struct uint128_extra + softfloat_shortShiftRightJam128Extra( + uint64_t a64, uint64_t a0, uint64_t extra, uint_fast8_t dist ); +#endif +#endif + +#ifndef softfloat_shiftRightJam64Extra +/*---------------------------------------------------------------------------- +| Shifts the 128 bits formed by concatenating 'a' and 'extra' right by 64 +| _plus_ the number of bits given in 'dist', which must not be zero. This +| shifted value is at most 64 nonzero bits and is returned in the 'v' field +| of the 'struct uint64_extra' result. The 64-bit 'extra' field of the result +| contains a value formed as follows from the bits that were shifted off: The +| _last_ bit shifted off is the most-significant bit of the 'extra' field, and +| the other 63 bits of the 'extra' field are all zero if and only if _all_but_ +| _the_last_ bits shifted off were all zero. +| (This function makes more sense if 'a' and 'extra' are considered to form +| an unsigned fixed-point number with binary point between 'a' and 'extra'. +| This fixed-point value is shifted right by the number of bits given in +| 'dist', and the integer part of this shifted value is returned in the 'v' +| field of the result. The fractional part of the shifted value is modified +| as described above and returned in the 'extra' field of the result.) +*----------------------------------------------------------------------------*/ +#if defined INLINE_LEVEL && (4 <= INLINE_LEVEL) +INLINE +struct uint64_extra + softfloat_shiftRightJam64Extra( + uint64_t a, uint64_t extra, uint_fast32_t dist ) +{ + struct uint64_extra z; + if ( dist < 64 ) { + z.v = a>>dist; + z.extra = a<<(-dist & 63); + } else { + z.v = 0; + z.extra = (dist == 64) ? a : (a != 0); + } + z.extra |= (extra != 0); + return z; +} +#else +struct uint64_extra + softfloat_shiftRightJam64Extra( + uint64_t a, uint64_t extra, uint_fast32_t dist ); +#endif +#endif + +#ifndef softfloat_shiftRightJam128 +/*---------------------------------------------------------------------------- +| Shifts the 128 bits formed by concatenating 'a64' and 'a0' right by the +| number of bits given in 'dist', which must not be zero. If any nonzero bits +| are shifted off, they are "jammed" into the least-significant bit of the +| shifted value by setting the least-significant bit to 1. This shifted-and- +| jammed value is returned. +| The value of 'dist' can be arbitrarily large. In particular, if 'dist' is +| greater than 128, the result will be either 0 or 1, depending on whether the +| original 128 bits are all zeros. +*----------------------------------------------------------------------------*/ +struct uint128 + softfloat_shiftRightJam128( uint64_t a64, uint64_t a0, uint_fast32_t dist ); +#endif + +#ifndef softfloat_shiftRightJam128Extra +/*---------------------------------------------------------------------------- +| Shifts the 192 bits formed by concatenating 'a64', 'a0', and 'extra' right +| by 64 _plus_ the number of bits given in 'dist', which must not be zero. +| This shifted value is at most 128 nonzero bits and is returned in the 'v' +| field of the 'struct uint128_extra' result. The 64-bit 'extra' field of the +| result contains a value formed as follows from the bits that were shifted +| off: The _last_ bit shifted off is the most-significant bit of the 'extra' +| field, and the other 63 bits of the 'extra' field are all zero if and only +| if _all_but_the_last_ bits shifted off were all zero. +| (This function makes more sense if 'a64', 'a0', and 'extra' are considered +| to form an unsigned fixed-point number with binary point between 'a0' and +| 'extra'. This fixed-point value is shifted right by the number of bits +| given in 'dist', and the integer part of this shifted value is returned +| in the 'v' field of the result. The fractional part of the shifted value +| is modified as described above and returned in the 'extra' field of the +| result.) +*----------------------------------------------------------------------------*/ +struct uint128_extra + softfloat_shiftRightJam128Extra( + uint64_t a64, uint64_t a0, uint64_t extra, uint_fast32_t dist ); +#endif + +#ifndef softfloat_shiftRightJam256M +/*---------------------------------------------------------------------------- +| Shifts the 256-bit unsigned integer pointed to by 'aPtr' right by the number +| of bits given in 'dist', which must not be zero. If any nonzero bits are +| shifted off, they are "jammed" into the least-significant bit of the shifted +| value by setting the least-significant bit to 1. This shifted-and-jammed +| value is stored at the location pointed to by 'zPtr'. Each of 'aPtr' and +| 'zPtr' points to an array of four 64-bit elements that concatenate in the +| platform's normal endian order to form a 256-bit integer. +| The value of 'dist' can be arbitrarily large. In particular, if 'dist' +| is greater than 256, the stored result will be either 0 or 1, depending on +| whether the original 256 bits are all zeros. +*----------------------------------------------------------------------------*/ +void + softfloat_shiftRightJam256M( + const uint64_t *aPtr, uint_fast32_t dist, uint64_t *zPtr ); +#endif + +#ifndef softfloat_add128 +/*---------------------------------------------------------------------------- +| Returns the sum of the 128-bit integer formed by concatenating 'a64' and +| 'a0' and the 128-bit integer formed by concatenating 'b64' and 'b0'. The +| addition is modulo 2^128, so any carry out is lost. +*----------------------------------------------------------------------------*/ +#if defined INLINE_LEVEL && (2 <= INLINE_LEVEL) +INLINE +struct uint128 + softfloat_add128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 ) +{ + struct uint128 z; + z.v0 = a0 + b0; + z.v64 = a64 + b64 + (z.v0 < a0); + return z; +} +#else +struct uint128 + softfloat_add128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 ); +#endif +#endif + +#ifndef softfloat_add256M +/*---------------------------------------------------------------------------- +| Adds the two 256-bit integers pointed to by 'aPtr' and 'bPtr'. The addition +| is modulo 2^256, so any carry out is lost. The sum is stored at the +| location pointed to by 'zPtr'. Each of 'aPtr', 'bPtr', and 'zPtr' points to +| an array of four 64-bit elements that concatenate in the platform's normal +| endian order to form a 256-bit integer. +*----------------------------------------------------------------------------*/ +void + softfloat_add256M( + const uint64_t *aPtr, const uint64_t *bPtr, uint64_t *zPtr ); +#endif + +#ifndef softfloat_sub128 +/*---------------------------------------------------------------------------- +| Returns the difference of the 128-bit integer formed by concatenating 'a64' +| and 'a0' and the 128-bit integer formed by concatenating 'b64' and 'b0'. +| The subtraction is modulo 2^128, so any borrow out (carry out) is lost. +*----------------------------------------------------------------------------*/ +#if defined INLINE_LEVEL && (2 <= INLINE_LEVEL) +INLINE +struct uint128 + softfloat_sub128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 ) +{ + struct uint128 z; + z.v0 = a0 - b0; + z.v64 = a64 - b64; + z.v64 -= (a0 < b0); + return z; +} +#else +struct uint128 + softfloat_sub128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 ); +#endif +#endif + +#ifndef softfloat_sub256M +/*---------------------------------------------------------------------------- +| Subtracts the 256-bit integer pointed to by 'bPtr' from the 256-bit integer +| pointed to by 'aPtr'. The addition is modulo 2^256, so any borrow out +| (carry out) is lost. The difference is stored at the location pointed to +| by 'zPtr'. Each of 'aPtr', 'bPtr', and 'zPtr' points to an array of four +| 64-bit elements that concatenate in the platform's normal endian order to +| form a 256-bit integer. +*----------------------------------------------------------------------------*/ +void + softfloat_sub256M( + const uint64_t *aPtr, const uint64_t *bPtr, uint64_t *zPtr ); +#endif + +#ifndef softfloat_mul64ByShifted32To128 +/*---------------------------------------------------------------------------- +| Returns the 128-bit product of 'a', 'b', and 2^32. +*----------------------------------------------------------------------------*/ +#if defined INLINE_LEVEL && (3 <= INLINE_LEVEL) +INLINE struct uint128 softfloat_mul64ByShifted32To128( uint64_t a, uint32_t b ) +{ + uint_fast64_t mid; + struct uint128 z; + mid = (uint_fast64_t) (uint32_t) a * b; + z.v0 = mid<<32; + z.v64 = (uint_fast64_t) (uint32_t) (a>>32) * b + (mid>>32); + return z; +} +#else +struct uint128 softfloat_mul64ByShifted32To128( uint64_t a, uint32_t b ); +#endif +#endif + +#ifndef softfloat_mul64To128 +/*---------------------------------------------------------------------------- +| Returns the 128-bit product of 'a' and 'b'. +*----------------------------------------------------------------------------*/ +struct uint128 softfloat_mul64To128( uint64_t a, uint64_t b ); +#endif + +#ifndef softfloat_mul128By32 +/*---------------------------------------------------------------------------- +| Returns the product of the 128-bit integer formed by concatenating 'a64' and +| 'a0', multiplied by 'b'. The multiplication is modulo 2^128; any overflow +| bits are discarded. +*----------------------------------------------------------------------------*/ +#if defined INLINE_LEVEL && (4 <= INLINE_LEVEL) +INLINE +struct uint128 softfloat_mul128By32( uint64_t a64, uint64_t a0, uint32_t b ) +{ + struct uint128 z; + uint_fast64_t mid; + uint_fast32_t carry; + z.v0 = a0 * b; + mid = (uint_fast64_t) (uint32_t) (a0>>32) * b; + carry = (uint32_t) ((uint_fast32_t) (z.v0>>32) - (uint_fast32_t) mid); + z.v64 = a64 * b + (uint_fast32_t) ((mid + carry)>>32); + return z; +} +#else +struct uint128 softfloat_mul128By32( uint64_t a64, uint64_t a0, uint32_t b ); +#endif +#endif + +#ifndef softfloat_mul128To256M +/*---------------------------------------------------------------------------- +| Multiplies the 128-bit unsigned integer formed by concatenating 'a64' and +| 'a0' by the 128-bit unsigned integer formed by concatenating 'b64' and +| 'b0'. The 256-bit product is stored at the location pointed to by 'zPtr'. +| Argument 'zPtr' points to an array of four 64-bit elements that concatenate +| in the platform's normal endian order to form a 256-bit integer. +*----------------------------------------------------------------------------*/ +void + softfloat_mul128To256M( + uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0, uint64_t *zPtr ); +#endif + +#else + +/*---------------------------------------------------------------------------- +| The following functions are needed only when 'SOFTFLOAT_FAST_INT64' is not +| defined. +*----------------------------------------------------------------------------*/ + +#ifndef softfloat_compare96M +/*---------------------------------------------------------------------------- +| Compares the two 96-bit unsigned integers pointed to by 'aPtr' and 'bPtr'. +| Returns -1 if the first integer (A) is less than the second (B); returns 0 +| if the two integers are equal; and returns +1 if the first integer (A) +| is greater than the second (B). (The result is thus the signum of A - B.) +| Each of 'aPtr' and 'bPtr' points to an array of three 32-bit elements that +| concatenate in the platform's normal endian order to form a 96-bit integer. +*----------------------------------------------------------------------------*/ +int_fast8_t softfloat_compare96M( const uint32_t *aPtr, const uint32_t *bPtr ); +#endif + +#ifndef softfloat_compare128M +/*---------------------------------------------------------------------------- +| Compares the two 128-bit unsigned integers pointed to by 'aPtr' and 'bPtr'. +| Returns -1 if the first integer (A) is less than the second (B); returns 0 +| if the two integers are equal; and returns +1 if the first integer (A) +| is greater than the second (B). (The result is thus the signum of A - B.) +| Each of 'aPtr' and 'bPtr' points to an array of four 32-bit elements that +| concatenate in the platform's normal endian order to form a 128-bit integer. +*----------------------------------------------------------------------------*/ +int_fast8_t + softfloat_compare128M( const uint32_t *aPtr, const uint32_t *bPtr ); +#endif + +#ifndef softfloat_shortShiftLeft64To96M +/*---------------------------------------------------------------------------- +| Extends 'a' to 96 bits and shifts the value left by the number of bits given +| in 'dist', which must be in the range 1 to 31. The result is stored at the +| location pointed to by 'zPtr'. Argument 'zPtr' points to an array of three +| 32-bit elements that concatenate in the platform's normal endian order to +| form a 96-bit integer. +*----------------------------------------------------------------------------*/ +#if defined INLINE_LEVEL && (2 <= INLINE_LEVEL) +INLINE +void + softfloat_shortShiftLeft64To96M( + uint64_t a, uint_fast8_t dist, uint32_t *zPtr ) +{ + zPtr[indexWord( 3, 0 )] = (uint32_t) a<<dist; + a >>= 32 - dist; + zPtr[indexWord( 3, 2 )] = a>>32; + zPtr[indexWord( 3, 1 )] = a; +} +#else +void + softfloat_shortShiftLeft64To96M( + uint64_t a, uint_fast8_t dist, uint32_t *zPtr ); +#endif +#endif + +#ifndef softfloat_shortShiftLeftM +/*---------------------------------------------------------------------------- +| Shifts the N-bit unsigned integer pointed to by 'aPtr' left by the number +| of bits given in 'dist', where N = 'size_words' * 32. The value of 'dist' +| must be in the range 1 to 31. Any nonzero bits shifted off are lost. The +| shifted N-bit result is stored at the location pointed to by 'zPtr'. Each +| of 'aPtr' and 'zPtr' points to a 'size_words'-long array of 32-bit elements +| that concatenate in the platform's normal endian order to form an N-bit +| integer. +*----------------------------------------------------------------------------*/ +void + softfloat_shortShiftLeftM( + uint_fast8_t size_words, + const uint32_t *aPtr, + uint_fast8_t dist, + uint32_t *zPtr + ); +#endif + +#ifndef softfloat_shortShiftLeft96M +/*---------------------------------------------------------------------------- +| This function or macro is the same as 'softfloat_shortShiftLeftM' with +| 'size_words' = 3 (N = 96). +*----------------------------------------------------------------------------*/ +#define softfloat_shortShiftLeft96M( aPtr, dist, zPtr ) softfloat_shortShiftLeftM( 3, aPtr, dist, zPtr ) +#endif + +#ifndef softfloat_shortShiftLeft128M +/*---------------------------------------------------------------------------- +| This function or macro is the same as 'softfloat_shortShiftLeftM' with +| 'size_words' = 4 (N = 128). +*----------------------------------------------------------------------------*/ +#define softfloat_shortShiftLeft128M( aPtr, dist, zPtr ) softfloat_shortShiftLeftM( 4, aPtr, dist, zPtr ) +#endif + +#ifndef softfloat_shortShiftLeft160M +/*---------------------------------------------------------------------------- +| This function or macro is the same as 'softfloat_shortShiftLeftM' with +| 'size_words' = 5 (N = 160). +*----------------------------------------------------------------------------*/ +#define softfloat_shortShiftLeft160M( aPtr, dist, zPtr ) softfloat_shortShiftLeftM( 5, aPtr, dist, zPtr ) +#endif + +#ifndef softfloat_shiftLeftM +/*---------------------------------------------------------------------------- +| Shifts the N-bit unsigned integer pointed to by 'aPtr' left by the number +| of bits given in 'dist', where N = 'size_words' * 32. The value of 'dist' +| must not be zero. Any nonzero bits shifted off are lost. The shifted +| N-bit result is stored at the location pointed to by 'zPtr'. Each of 'aPtr' +| and 'zPtr' points to a 'size_words'-long array of 32-bit elements that +| concatenate in the platform's normal endian order to form an N-bit integer. +| The value of 'dist' can be arbitrarily large. In particular, if 'dist' is +| greater than N, the stored result will be 0. +*----------------------------------------------------------------------------*/ +void + softfloat_shiftLeftM( + uint_fast8_t size_words, + const uint32_t *aPtr, + uint32_t dist, + uint32_t *zPtr + ); +#endif + +#ifndef softfloat_shiftLeft96M +/*---------------------------------------------------------------------------- +| This function or macro is the same as 'softfloat_shiftLeftM' with +| 'size_words' = 3 (N = 96). +*----------------------------------------------------------------------------*/ +#define softfloat_shiftLeft96M( aPtr, dist, zPtr ) softfloat_shiftLeftM( 3, aPtr, dist, zPtr ) +#endif + +#ifndef softfloat_shiftLeft128M +/*---------------------------------------------------------------------------- +| This function or macro is the same as 'softfloat_shiftLeftM' with +| 'size_words' = 4 (N = 128). +*----------------------------------------------------------------------------*/ +#define softfloat_shiftLeft128M( aPtr, dist, zPtr ) softfloat_shiftLeftM( 4, aPtr, dist, zPtr ) +#endif + +#ifndef softfloat_shiftLeft160M +/*---------------------------------------------------------------------------- +| This function or macro is the same as 'softfloat_shiftLeftM' with +| 'size_words' = 5 (N = 160). +*----------------------------------------------------------------------------*/ +#define softfloat_shiftLeft160M( aPtr, dist, zPtr ) softfloat_shiftLeftM( 5, aPtr, dist, zPtr ) +#endif + +#ifndef softfloat_shortShiftRightM +/*---------------------------------------------------------------------------- +| Shifts the N-bit unsigned integer pointed to by 'aPtr' right by the number +| of bits given in 'dist', where N = 'size_words' * 32. The value of 'dist' +| must be in the range 1 to 31. Any nonzero bits shifted off are lost. The +| shifted N-bit result is stored at the location pointed to by 'zPtr'. Each +| of 'aPtr' and 'zPtr' points to a 'size_words'-long array of 32-bit elements +| that concatenate in the platform's normal endian order to form an N-bit +| integer. +*----------------------------------------------------------------------------*/ +void + softfloat_shortShiftRightM( + uint_fast8_t size_words, + const uint32_t *aPtr, + uint_fast8_t dist, + uint32_t *zPtr + ); +#endif + +#ifndef softfloat_shortShiftRight128M +/*---------------------------------------------------------------------------- +| This function or macro is the same as 'softfloat_shortShiftRightM' with +| 'size_words' = 4 (N = 128). +*----------------------------------------------------------------------------*/ +#define softfloat_shortShiftRight128M( aPtr, dist, zPtr ) softfloat_shortShiftRightM( 4, aPtr, dist, zPtr ) +#endif + +#ifndef softfloat_shortShiftRight160M +/*---------------------------------------------------------------------------- +| This function or macro is the same as 'softfloat_shortShiftRightM' with +| 'size_words' = 5 (N = 160). +*----------------------------------------------------------------------------*/ +#define softfloat_shortShiftRight160M( aPtr, dist, zPtr ) softfloat_shortShiftRightM( 5, aPtr, dist, zPtr ) +#endif + +#ifndef softfloat_shortShiftRightJamM +/*---------------------------------------------------------------------------- +| Shifts the N-bit unsigned integer pointed to by 'aPtr' right by the number +| of bits given in 'dist', where N = 'size_words' * 32. The value of 'dist' +| must be in the range 1 to 31. If any nonzero bits are shifted off, they are +| "jammed" into the least-significant bit of the shifted value by setting the +| least-significant bit to 1. This shifted-and-jammed N-bit result is stored +| at the location pointed to by 'zPtr'. Each of 'aPtr' and 'zPtr' points +| to a 'size_words'-long array of 32-bit elements that concatenate in the +| platform's normal endian order to form an N-bit integer. +*----------------------------------------------------------------------------*/ +void + softfloat_shortShiftRightJamM( + uint_fast8_t, const uint32_t *, uint_fast8_t, uint32_t * ); +#endif + +#ifndef softfloat_shortShiftRightJam160M +/*---------------------------------------------------------------------------- +| This function or macro is the same as 'softfloat_shortShiftRightJamM' with +| 'size_words' = 5 (N = 160). +*----------------------------------------------------------------------------*/ +#define softfloat_shortShiftRightJam160M( aPtr, dist, zPtr ) softfloat_shortShiftRightJamM( 5, aPtr, dist, zPtr ) +#endif + +#ifndef softfloat_shiftRightM +/*---------------------------------------------------------------------------- +| Shifts the N-bit unsigned integer pointed to by 'aPtr' right by the number +| of bits given in 'dist', where N = 'size_words' * 32. The value of 'dist' +| must not be zero. Any nonzero bits shifted off are lost. The shifted +| N-bit result is stored at the location pointed to by 'zPtr'. Each of 'aPtr' +| and 'zPtr' points to a 'size_words'-long array of 32-bit elements that +| concatenate in the platform's normal endian order to form an N-bit integer. +| The value of 'dist' can be arbitrarily large. In particular, if 'dist' is +| greater than N, the stored result will be 0. +*----------------------------------------------------------------------------*/ +void + softfloat_shiftRightM( + uint_fast8_t size_words, + const uint32_t *aPtr, + uint32_t dist, + uint32_t *zPtr + ); +#endif + +#ifndef softfloat_shiftRight96M +/*---------------------------------------------------------------------------- +| This function or macro is the same as 'softfloat_shiftRightM' with +| 'size_words' = 3 (N = 96). +*----------------------------------------------------------------------------*/ +#define softfloat_shiftRight96M( aPtr, dist, zPtr ) softfloat_shiftRightM( 3, aPtr, dist, zPtr ) +#endif + +#ifndef softfloat_shiftRightJamM +/*---------------------------------------------------------------------------- +| Shifts the N-bit unsigned integer pointed to by 'aPtr' right by the number +| of bits given in 'dist', where N = 'size_words' * 32. The value of 'dist' +| must not be zero. If any nonzero bits are shifted off, they are "jammed" +| into the least-significant bit of the shifted value by setting the least- +| significant bit to 1. This shifted-and-jammed N-bit result is stored +| at the location pointed to by 'zPtr'. Each of 'aPtr' and 'zPtr' points +| to a 'size_words'-long array of 32-bit elements that concatenate in the +| platform's normal endian order to form an N-bit integer. +| The value of 'dist' can be arbitrarily large. In particular, if 'dist' +| is greater than N, the stored result will be either 0 or 1, depending on +| whether the original N bits are all zeros. +*----------------------------------------------------------------------------*/ +void + softfloat_shiftRightJamM( + uint_fast8_t size_words, + const uint32_t *aPtr, + uint32_t dist, + uint32_t *zPtr + ); +#endif + +#ifndef softfloat_shiftRightJam96M +/*---------------------------------------------------------------------------- +| This function or macro is the same as 'softfloat_shiftRightJamM' with +| 'size_words' = 3 (N = 96). +*----------------------------------------------------------------------------*/ +#define softfloat_shiftRightJam96M( aPtr, dist, zPtr ) softfloat_shiftRightJamM( 3, aPtr, dist, zPtr ) +#endif + +#ifndef softfloat_shiftRightJam128M +/*---------------------------------------------------------------------------- +| This function or macro is the same as 'softfloat_shiftRightJamM' with +| 'size_words' = 4 (N = 128). +*----------------------------------------------------------------------------*/ +#define softfloat_shiftRightJam128M( aPtr, dist, zPtr ) softfloat_shiftRightJamM( 4, aPtr, dist, zPtr ) +#endif + +#ifndef softfloat_shiftRightJam160M +/*---------------------------------------------------------------------------- +| This function or macro is the same as 'softfloat_shiftRightJamM' with +| 'size_words' = 5 (N = 160). +*----------------------------------------------------------------------------*/ +#define softfloat_shiftRightJam160M( aPtr, dist, zPtr ) softfloat_shiftRightJamM( 5, aPtr, dist, zPtr ) +#endif + +#ifndef softfloat_addM +/*---------------------------------------------------------------------------- +| Adds the two N-bit integers pointed to by 'aPtr' and 'bPtr', where N = +| 'size_words' * 32. The addition is modulo 2^N, so any carry out is lost. +| The N-bit sum is stored at the location pointed to by 'zPtr'. Each of +| 'aPtr', 'bPtr', and 'zPtr' points to a 'size_words'-long array of 32-bit +| elements that concatenate in the platform's normal endian order to form an +| N-bit integer. +*----------------------------------------------------------------------------*/ +void + softfloat_addM( + uint_fast8_t size_words, + const uint32_t *aPtr, + const uint32_t *bPtr, + uint32_t *zPtr + ); +#endif + +#ifndef softfloat_add96M +/*---------------------------------------------------------------------------- +| This function or macro is the same as 'softfloat_addM' with 'size_words' +| = 3 (N = 96). +*----------------------------------------------------------------------------*/ +#define softfloat_add96M( aPtr, bPtr, zPtr ) softfloat_addM( 3, aPtr, bPtr, zPtr ) +#endif + +#ifndef softfloat_add128M +/*---------------------------------------------------------------------------- +| This function or macro is the same as 'softfloat_addM' with 'size_words' +| = 4 (N = 128). +*----------------------------------------------------------------------------*/ +#define softfloat_add128M( aPtr, bPtr, zPtr ) softfloat_addM( 4, aPtr, bPtr, zPtr ) +#endif + +#ifndef softfloat_add160M +/*---------------------------------------------------------------------------- +| This function or macro is the same as 'softfloat_addM' with 'size_words' +| = 5 (N = 160). +*----------------------------------------------------------------------------*/ +#define softfloat_add160M( aPtr, bPtr, zPtr ) softfloat_addM( 5, aPtr, bPtr, zPtr ) +#endif + +#ifndef softfloat_addCarryM +/*---------------------------------------------------------------------------- +| Adds the two N-bit unsigned integers pointed to by 'aPtr' and 'bPtr', where +| N = 'size_words' * 32, plus 'carry', which must be either 0 or 1. The N-bit +| sum (modulo 2^N) is stored at the location pointed to by 'zPtr', and any +| carry out is returned as the result. Each of 'aPtr', 'bPtr', and 'zPtr' +| points to a 'size_words'-long array of 32-bit elements that concatenate in +| the platform's normal endian order to form an N-bit integer. +*----------------------------------------------------------------------------*/ +uint_fast8_t + softfloat_addCarryM( + uint_fast8_t size_words, + const uint32_t *aPtr, + const uint32_t *bPtr, + uint_fast8_t carry, + uint32_t *zPtr + ); +#endif + +#ifndef softfloat_addComplCarryM +/*---------------------------------------------------------------------------- +| This function or macro is the same as 'softfloat_addCarryM', except that +| the value of the unsigned integer pointed to by 'bPtr' is bit-wise completed +| before the addition. +*----------------------------------------------------------------------------*/ +uint_fast8_t + softfloat_addComplCarryM( + uint_fast8_t size_words, + const uint32_t *aPtr, + const uint32_t *bPtr, + uint_fast8_t carry, + uint32_t *zPtr + ); +#endif + +#ifndef softfloat_addComplCarry96M +/*---------------------------------------------------------------------------- +| This function or macro is the same as 'softfloat_addComplCarryM' with +| 'size_words' = 3 (N = 96). +*----------------------------------------------------------------------------*/ +#define softfloat_addComplCarry96M( aPtr, bPtr, carry, zPtr ) softfloat_addComplCarryM( 3, aPtr, bPtr, carry, zPtr ) +#endif + +#ifndef softfloat_negXM +/*---------------------------------------------------------------------------- +| Replaces the N-bit unsigned integer pointed to by 'zPtr' by the +| 2s-complement of itself, where N = 'size_words' * 32. Argument 'zPtr' +| points to a 'size_words'-long array of 32-bit elements that concatenate in +| the platform's normal endian order to form an N-bit integer. +*----------------------------------------------------------------------------*/ +void softfloat_negXM( uint_fast8_t size_words, uint32_t *zPtr ); +#endif + +#ifndef softfloat_negX96M +/*---------------------------------------------------------------------------- +| This function or macro is the same as 'softfloat_negXM' with 'size_words' +| = 3 (N = 96). +*----------------------------------------------------------------------------*/ +#define softfloat_negX96M( zPtr ) softfloat_negXM( 3, zPtr ) +#endif + +#ifndef softfloat_negX128M +/*---------------------------------------------------------------------------- +| This function or macro is the same as 'softfloat_negXM' with 'size_words' +| = 4 (N = 128). +*----------------------------------------------------------------------------*/ +#define softfloat_negX128M( zPtr ) softfloat_negXM( 4, zPtr ) +#endif + +#ifndef softfloat_negX160M +/*---------------------------------------------------------------------------- +| This function or macro is the same as 'softfloat_negXM' with 'size_words' +| = 5 (N = 160). +*----------------------------------------------------------------------------*/ +#define softfloat_negX160M( zPtr ) softfloat_negXM( 5, zPtr ) +#endif + +#ifndef softfloat_negX256M +/*---------------------------------------------------------------------------- +| This function or macro is the same as 'softfloat_negXM' with 'size_words' +| = 8 (N = 256). +*----------------------------------------------------------------------------*/ +#define softfloat_negX256M( zPtr ) softfloat_negXM( 8, zPtr ) +#endif + +#ifndef softfloat_sub1XM +/*---------------------------------------------------------------------------- +| Subtracts 1 from the N-bit integer pointed to by 'zPtr', where N = +| 'size_words' * 32. The subtraction is modulo 2^N, so any borrow out (carry +| out) is lost. Argument 'zPtr' points to a 'size_words'-long array of 32-bit +| elements that concatenate in the platform's normal endian order to form an +| N-bit integer. +*----------------------------------------------------------------------------*/ +void softfloat_sub1XM( uint_fast8_t size_words, uint32_t *zPtr ); +#endif + +#ifndef softfloat_sub1X96M +/*---------------------------------------------------------------------------- +| This function or macro is the same as 'softfloat_sub1XM' with 'size_words' +| = 3 (N = 96). +*----------------------------------------------------------------------------*/ +#define softfloat_sub1X96M( zPtr ) softfloat_sub1XM( 3, zPtr ) +#endif + +#ifndef softfloat_sub1X160M +/*---------------------------------------------------------------------------- +| This function or macro is the same as 'softfloat_sub1XM' with 'size_words' +| = 5 (N = 160). +*----------------------------------------------------------------------------*/ +#define softfloat_sub1X160M( zPtr ) softfloat_sub1XM( 5, zPtr ) +#endif + +#ifndef softfloat_subM +/*---------------------------------------------------------------------------- +| Subtracts the two N-bit integers pointed to by 'aPtr' and 'bPtr', where N = +| 'size_words' * 32. The subtraction is modulo 2^N, so any borrow out (carry +| out) is lost. The N-bit difference is stored at the location pointed to by +| 'zPtr'. Each of 'aPtr', 'bPtr', and 'zPtr' points to a 'size_words'-long +| array of 32-bit elements that concatenate in the platform's normal endian +| order to form an N-bit integer. +*----------------------------------------------------------------------------*/ +void + softfloat_subM( + uint_fast8_t size_words, + const uint32_t *aPtr, + const uint32_t *bPtr, + uint32_t *zPtr + ); +#endif + +#ifndef softfloat_sub96M +/*---------------------------------------------------------------------------- +| This function or macro is the same as 'softfloat_subM' with 'size_words' +| = 3 (N = 96). +*----------------------------------------------------------------------------*/ +#define softfloat_sub96M( aPtr, bPtr, zPtr ) softfloat_subM( 3, aPtr, bPtr, zPtr ) +#endif + +#ifndef softfloat_sub128M +/*---------------------------------------------------------------------------- +| This function or macro is the same as 'softfloat_subM' with 'size_words' +| = 4 (N = 128). +*----------------------------------------------------------------------------*/ +#define softfloat_sub128M( aPtr, bPtr, zPtr ) softfloat_subM( 4, aPtr, bPtr, zPtr ) +#endif + +#ifndef softfloat_sub160M +/*---------------------------------------------------------------------------- +| This function or macro is the same as 'softfloat_subM' with 'size_words' +| = 5 (N = 160). +*----------------------------------------------------------------------------*/ +#define softfloat_sub160M( aPtr, bPtr, zPtr ) softfloat_subM( 5, aPtr, bPtr, zPtr ) +#endif + +#ifndef softfloat_mul64To128M +/*---------------------------------------------------------------------------- +| Multiplies 'a' and 'b' and stores the 128-bit product at the location +| pointed to by 'zPtr'. Argument 'zPtr' points to an array of four 32-bit +| elements that concatenate in the platform's normal endian order to form a +| 128-bit integer. +*----------------------------------------------------------------------------*/ +void softfloat_mul64To128M( uint64_t a, uint64_t b, uint32_t *zPtr ); +#endif + +#ifndef softfloat_mul128MTo256M +/*---------------------------------------------------------------------------- +| Multiplies the two 128-bit unsigned integers pointed to by 'aPtr' and +| 'bPtr', and stores the 256-bit product at the location pointed to by 'zPtr'. +| Each of 'aPtr' and 'bPtr' points to an array of four 32-bit elements that +| concatenate in the platform's normal endian order to form a 128-bit integer. +| Argument 'zPtr' points to an array of eight 32-bit elements that concatenate +| to form a 256-bit integer. +*----------------------------------------------------------------------------*/ +void + softfloat_mul128MTo256M( + const uint32_t *aPtr, const uint32_t *bPtr, uint32_t *zPtr ); +#endif + +#ifndef softfloat_remStepMBy32 +/*---------------------------------------------------------------------------- +| Performs a "remainder reduction step" as follows: Arguments 'remPtr' and +| 'bPtr' both point to N-bit unsigned integers, where N = 'size_words' * 32. +| Defining R and B as the values of those integers, the expression (R<<'dist') +| - B * q is computed modulo 2^N, and the N-bit result is stored at the +| location pointed to by 'zPtr'. Each of 'remPtr', 'bPtr', and 'zPtr' points +| to a 'size_words'-long array of 32-bit elements that concatenate in the +| platform's normal endian order to form an N-bit integer. +*----------------------------------------------------------------------------*/ +void + softfloat_remStepMBy32( + uint_fast8_t size_words, + const uint32_t *remPtr, + uint_fast8_t dist, + const uint32_t *bPtr, + uint32_t q, + uint32_t *zPtr + ); +#endif + +#ifndef softfloat_remStep96MBy32 +/*---------------------------------------------------------------------------- +| This function or macro is the same as 'softfloat_remStepMBy32' with +| 'size_words' = 3 (N = 96). +*----------------------------------------------------------------------------*/ +#define softfloat_remStep96MBy32( remPtr, dist, bPtr, q, zPtr ) softfloat_remStepMBy32( 3, remPtr, dist, bPtr, q, zPtr ) +#endif + +#ifndef softfloat_remStep128MBy32 +/*---------------------------------------------------------------------------- +| This function or macro is the same as 'softfloat_remStepMBy32' with +| 'size_words' = 4 (N = 128). +*----------------------------------------------------------------------------*/ +#define softfloat_remStep128MBy32( remPtr, dist, bPtr, q, zPtr ) softfloat_remStepMBy32( 4, remPtr, dist, bPtr, q, zPtr ) +#endif + +#ifndef softfloat_remStep160MBy32 +/*---------------------------------------------------------------------------- +| This function or macro is the same as 'softfloat_remStepMBy32' with +| 'size_words' = 5 (N = 160). +*----------------------------------------------------------------------------*/ +#define softfloat_remStep160MBy32( remPtr, dist, bPtr, q, zPtr ) softfloat_remStepMBy32( 5, remPtr, dist, bPtr, q, zPtr ) +#endif + +#endif + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_add128.c b/vendor/riscv/riscv-isa-sim/softfloat/s_add128.c new file mode 100644 index 0000000000..8065656a76 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_add128.c @@ -0,0 +1,55 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "platform.h" +#include "primitiveTypes.h" + +#ifndef softfloat_add128 + +struct uint128 + softfloat_add128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 ) +{ + struct uint128 z; + + z.v0 = a0 + b0; + z.v64 = a64 + b64 + (z.v0 < a0); + return z; + +} + +#endif + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_add256M.c b/vendor/riscv/riscv-isa-sim/softfloat/s_add256M.c new file mode 100644 index 0000000000..d07b0046a4 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_add256M.c @@ -0,0 +1,65 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "platform.h" +#include "primitiveTypes.h" + +#ifndef softfloat_add256M + +void + softfloat_add256M( + const uint64_t *aPtr, const uint64_t *bPtr, uint64_t *zPtr ) +{ + unsigned int index; + uint_fast8_t carry; + uint64_t wordA, wordZ; + + index = indexWordLo( 4 ); + carry = 0; + for (;;) { + wordA = aPtr[index]; + wordZ = wordA + bPtr[index] + carry; + zPtr[index] = wordZ; + if ( index == indexWordHi( 4 ) ) break; + if ( wordZ != wordA ) carry = (wordZ < wordA); + index += wordIncr; + } + +} + +#endif + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_addCarryM.c b/vendor/riscv/riscv-isa-sim/softfloat/s_addCarryM.c new file mode 100644 index 0000000000..fae1db4981 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_addCarryM.c @@ -0,0 +1,70 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "platform.h" +#include "primitiveTypes.h" + +#ifndef softfloat_addCarryM + +uint_fast8_t + softfloat_addCarryM( + uint_fast8_t size_words, + const uint32_t *aPtr, + const uint32_t *bPtr, + uint_fast8_t carry, + uint32_t *zPtr + ) +{ + unsigned int index, lastIndex; + uint32_t wordA, wordZ; + + index = indexWordLo( size_words ); + lastIndex = indexWordHi( size_words ); + for (;;) { + wordA = aPtr[index]; + wordZ = wordA + bPtr[index] + carry; + zPtr[index] = wordZ; + if ( wordZ != wordA ) carry = (wordZ < wordA); + if ( index == lastIndex ) break; + index += wordIncr; + } + return carry; + +} + +#endif + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_addComplCarryM.c b/vendor/riscv/riscv-isa-sim/softfloat/s_addComplCarryM.c new file mode 100644 index 0000000000..02f2bce431 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_addComplCarryM.c @@ -0,0 +1,70 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "platform.h" +#include "primitiveTypes.h" + +#ifndef softfloat_addComplCarryM + +uint_fast8_t + softfloat_addComplCarryM( + uint_fast8_t size_words, + const uint32_t *aPtr, + const uint32_t *bPtr, + uint_fast8_t carry, + uint32_t *zPtr + ) +{ + unsigned int index, lastIndex; + uint32_t wordA, wordZ; + + index = indexWordLo( size_words ); + lastIndex = indexWordHi( size_words ); + for (;;) { + wordA = aPtr[index]; + wordZ = wordA + ~bPtr[index] + carry; + zPtr[index] = wordZ; + if ( wordZ != wordA ) carry = (wordZ < wordA); + if ( index == lastIndex ) break; + index += wordIncr; + } + return carry; + +} + +#endif + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_addM.c b/vendor/riscv/riscv-isa-sim/softfloat/s_addM.c new file mode 100644 index 0000000000..a06eda65ac --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_addM.c @@ -0,0 +1,70 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "platform.h" +#include "primitiveTypes.h" + +#ifndef softfloat_addM + +void + softfloat_addM( + uint_fast8_t size_words, + const uint32_t *aPtr, + const uint32_t *bPtr, + uint32_t *zPtr + ) +{ + unsigned int index, lastIndex; + uint_fast8_t carry; + uint32_t wordA, wordZ; + + index = indexWordLo( size_words ); + lastIndex = indexWordHi( size_words ); + carry = 0; + for (;;) { + wordA = aPtr[index]; + wordZ = wordA + bPtr[index] + carry; + zPtr[index] = wordZ; + if ( index == lastIndex ) break; + if ( wordZ != wordA ) carry = (wordZ < wordA); + index += wordIncr; + } + +} + +#endif + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_addMagsF128.c b/vendor/riscv/riscv-isa-sim/softfloat/s_addMagsF128.c new file mode 100644 index 0000000000..292f0aa5fc --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_addMagsF128.c @@ -0,0 +1,154 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" + +float128_t + softfloat_addMagsF128( + uint_fast64_t uiA64, + uint_fast64_t uiA0, + uint_fast64_t uiB64, + uint_fast64_t uiB0, + bool signZ + ) +{ + int_fast32_t expA; + struct uint128 sigA; + int_fast32_t expB; + struct uint128 sigB; + int_fast32_t expDiff; + struct uint128 uiZ, sigZ; + int_fast32_t expZ; + uint_fast64_t sigZExtra; + struct uint128_extra sig128Extra; + union ui128_f128 uZ; + + expA = expF128UI64( uiA64 ); + sigA.v64 = fracF128UI64( uiA64 ); + sigA.v0 = uiA0; + expB = expF128UI64( uiB64 ); + sigB.v64 = fracF128UI64( uiB64 ); + sigB.v0 = uiB0; + expDiff = expA - expB; + if ( ! expDiff ) { + if ( expA == 0x7FFF ) { + if ( sigA.v64 | sigA.v0 | sigB.v64 | sigB.v0 ) goto propagateNaN; + uiZ.v64 = uiA64; + uiZ.v0 = uiA0; + goto uiZ; + } + sigZ = softfloat_add128( sigA.v64, sigA.v0, sigB.v64, sigB.v0 ); + if ( ! expA ) { + uiZ.v64 = packToF128UI64( signZ, 0, sigZ.v64 ); + uiZ.v0 = sigZ.v0; + goto uiZ; + } + expZ = expA; + sigZ.v64 |= UINT64_C( 0x0002000000000000 ); + sigZExtra = 0; + goto shiftRight1; + } + if ( expDiff < 0 ) { + if ( expB == 0x7FFF ) { + if ( sigB.v64 | sigB.v0 ) goto propagateNaN; + uiZ.v64 = packToF128UI64( signZ, 0x7FFF, 0 ); + uiZ.v0 = 0; + goto uiZ; + } + expZ = expB; + if ( expA ) { + sigA.v64 |= UINT64_C( 0x0001000000000000 ); + } else { + ++expDiff; + sigZExtra = 0; + if ( ! expDiff ) goto newlyAligned; + } + sig128Extra = + softfloat_shiftRightJam128Extra( sigA.v64, sigA.v0, 0, -expDiff ); + sigA = sig128Extra.v; + sigZExtra = sig128Extra.extra; + } else { + if ( expA == 0x7FFF ) { + if ( sigA.v64 | sigA.v0 ) goto propagateNaN; + uiZ.v64 = uiA64; + uiZ.v0 = uiA0; + goto uiZ; + } + expZ = expA; + if ( expB ) { + sigB.v64 |= UINT64_C( 0x0001000000000000 ); + } else { + --expDiff; + sigZExtra = 0; + if ( ! expDiff ) goto newlyAligned; + } + sig128Extra = + softfloat_shiftRightJam128Extra( sigB.v64, sigB.v0, 0, expDiff ); + sigB = sig128Extra.v; + sigZExtra = sig128Extra.extra; + } + newlyAligned: + sigZ = + softfloat_add128( + sigA.v64 | UINT64_C( 0x0001000000000000 ), + sigA.v0, + sigB.v64, + sigB.v0 + ); + --expZ; + if ( sigZ.v64 < UINT64_C( 0x0002000000000000 ) ) goto roundAndPack; + ++expZ; + shiftRight1: + sig128Extra = + softfloat_shortShiftRightJam128Extra( + sigZ.v64, sigZ.v0, sigZExtra, 1 ); + sigZ = sig128Extra.v; + sigZExtra = sig128Extra.extra; + roundAndPack: + return + softfloat_roundPackToF128( signZ, expZ, sigZ.v64, sigZ.v0, sigZExtra ); + propagateNaN: + uiZ = softfloat_propagateNaNF128UI( uiA64, uiA0, uiB64, uiB0 ); + uiZ: + uZ.ui = uiZ; + return uZ.f; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_addMagsF16.c b/vendor/riscv/riscv-isa-sim/softfloat/s_addMagsF16.c new file mode 100644 index 0000000000..4204c1e029 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_addMagsF16.c @@ -0,0 +1,183 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the +University of California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +float16_t softfloat_addMagsF16( uint_fast16_t uiA, uint_fast16_t uiB ) +{ + int_fast8_t expA; + uint_fast16_t sigA; + int_fast8_t expB; + uint_fast16_t sigB; + int_fast8_t expDiff; + uint_fast16_t uiZ; + bool signZ; + int_fast8_t expZ; + uint_fast16_t sigZ; + uint_fast16_t sigX, sigY; + int_fast8_t shiftDist; + uint_fast32_t sig32Z; + int_fast8_t roundingMode; + union ui16_f16 uZ; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + expA = expF16UI( uiA ); + sigA = fracF16UI( uiA ); + expB = expF16UI( uiB ); + sigB = fracF16UI( uiB ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + expDiff = expA - expB; + if ( ! expDiff ) { + /*-------------------------------------------------------------------- + *--------------------------------------------------------------------*/ + if ( ! expA ) { + uiZ = uiA + sigB; + goto uiZ; + } + if ( expA == 0x1F ) { + if ( sigA | sigB ) goto propagateNaN; + uiZ = uiA; + goto uiZ; + } + signZ = signF16UI( uiA ); + expZ = expA; + sigZ = 0x0800 + sigA + sigB; + if ( ! (sigZ & 1) && (expZ < 0x1E) ) { + sigZ >>= 1; + goto pack; + } + sigZ <<= 3; + } else { + /*-------------------------------------------------------------------- + *--------------------------------------------------------------------*/ + signZ = signF16UI( uiA ); + if ( expDiff < 0 ) { + /*---------------------------------------------------------------- + *----------------------------------------------------------------*/ + if ( expB == 0x1F ) { + if ( sigB ) goto propagateNaN; + uiZ = packToF16UI( signZ, 0x1F, 0 ); + goto uiZ; + } + if ( expDiff <= -13 ) { + uiZ = packToF16UI( signZ, expB, sigB ); + if ( expA | sigA ) goto addEpsilon; + goto uiZ; + } + expZ = expB; + sigX = sigB | 0x0400; + sigY = sigA + (expA ? 0x0400 : sigA); + shiftDist = 19 + expDiff; + } else { + /*---------------------------------------------------------------- + *----------------------------------------------------------------*/ + uiZ = uiA; + if ( expA == 0x1F ) { + if ( sigA ) goto propagateNaN; + goto uiZ; + } + if ( 13 <= expDiff ) { + if ( expB | sigB ) goto addEpsilon; + goto uiZ; + } + expZ = expA; + sigX = sigA | 0x0400; + sigY = sigB + (expB ? 0x0400 : sigB); + shiftDist = 19 - expDiff; + } + sig32Z = + ((uint_fast32_t) sigX<<19) + ((uint_fast32_t) sigY<<shiftDist); + if ( sig32Z < 0x40000000 ) { + --expZ; + sig32Z <<= 1; + } + sigZ = sig32Z>>16; + if ( sig32Z & 0xFFFF ) { + sigZ |= 1; + } else { + if ( ! (sigZ & 0xF) && (expZ < 0x1E) ) { + sigZ >>= 4; + goto pack; + } + } + } + return softfloat_roundPackToF16( signZ, expZ, sigZ ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + propagateNaN: + uiZ = softfloat_propagateNaNF16UI( uiA, uiB ); + goto uiZ; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + addEpsilon: + roundingMode = softfloat_roundingMode; + if ( roundingMode != softfloat_round_near_even ) { + if ( + roundingMode + == (signF16UI( uiZ ) ? softfloat_round_min + : softfloat_round_max) + ) { + ++uiZ; + if ( (uint16_t) (uiZ<<1) == 0xF800 ) { + softfloat_raiseFlags( + softfloat_flag_overflow | softfloat_flag_inexact ); + } + } +#ifdef SOFTFLOAT_ROUND_ODD + else if ( roundingMode == softfloat_round_odd ) { + uiZ |= 1; + } +#endif + } + softfloat_exceptionFlags |= softfloat_flag_inexact; + goto uiZ; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + pack: + uiZ = packToF16UI( signZ, expZ, sigZ ); + uiZ: + uZ.ui = uiZ; + return uZ.f; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_addMagsF32.c b/vendor/riscv/riscv-isa-sim/softfloat/s_addMagsF32.c new file mode 100644 index 0000000000..ba647814d7 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_addMagsF32.c @@ -0,0 +1,126 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" + +float32_t softfloat_addMagsF32( uint_fast32_t uiA, uint_fast32_t uiB ) +{ + int_fast16_t expA; + uint_fast32_t sigA; + int_fast16_t expB; + uint_fast32_t sigB; + int_fast16_t expDiff; + uint_fast32_t uiZ; + bool signZ; + int_fast16_t expZ; + uint_fast32_t sigZ; + union ui32_f32 uZ; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + expA = expF32UI( uiA ); + sigA = fracF32UI( uiA ); + expB = expF32UI( uiB ); + sigB = fracF32UI( uiB ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + expDiff = expA - expB; + if ( ! expDiff ) { + /*-------------------------------------------------------------------- + *--------------------------------------------------------------------*/ + if ( ! expA ) { + uiZ = uiA + sigB; + goto uiZ; + } + if ( expA == 0xFF ) { + if ( sigA | sigB ) goto propagateNaN; + uiZ = uiA; + goto uiZ; + } + signZ = signF32UI( uiA ); + expZ = expA; + sigZ = 0x01000000 + sigA + sigB; + if ( ! (sigZ & 1) && (expZ < 0xFE) ) { + uiZ = packToF32UI( signZ, expZ, sigZ>>1 ); + goto uiZ; + } + sigZ <<= 6; + } else { + /*-------------------------------------------------------------------- + *--------------------------------------------------------------------*/ + signZ = signF32UI( uiA ); + sigA <<= 6; + sigB <<= 6; + if ( expDiff < 0 ) { + if ( expB == 0xFF ) { + if ( sigB ) goto propagateNaN; + uiZ = packToF32UI( signZ, 0xFF, 0 ); + goto uiZ; + } + expZ = expB; + sigA += expA ? 0x20000000 : sigA; + sigA = softfloat_shiftRightJam32( sigA, -expDiff ); + } else { + if ( expA == 0xFF ) { + if ( sigA ) goto propagateNaN; + uiZ = uiA; + goto uiZ; + } + expZ = expA; + sigB += expB ? 0x20000000 : sigB; + sigB = softfloat_shiftRightJam32( sigB, expDiff ); + } + sigZ = 0x20000000 + sigA + sigB; + if ( sigZ < 0x40000000 ) { + --expZ; + sigZ <<= 1; + } + } + return softfloat_roundPackToF32( signZ, expZ, sigZ ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + propagateNaN: + uiZ = softfloat_propagateNaNF32UI( uiA, uiB ); + uiZ: + uZ.ui = uiZ; + return uZ.f; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_addMagsF64.c b/vendor/riscv/riscv-isa-sim/softfloat/s_addMagsF64.c new file mode 100644 index 0000000000..63e1afe9d4 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_addMagsF64.c @@ -0,0 +1,128 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" + +float64_t + softfloat_addMagsF64( uint_fast64_t uiA, uint_fast64_t uiB, bool signZ ) +{ + int_fast16_t expA; + uint_fast64_t sigA; + int_fast16_t expB; + uint_fast64_t sigB; + int_fast16_t expDiff; + uint_fast64_t uiZ; + int_fast16_t expZ; + uint_fast64_t sigZ; + union ui64_f64 uZ; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + expA = expF64UI( uiA ); + sigA = fracF64UI( uiA ); + expB = expF64UI( uiB ); + sigB = fracF64UI( uiB ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + expDiff = expA - expB; + if ( ! expDiff ) { + /*-------------------------------------------------------------------- + *--------------------------------------------------------------------*/ + if ( ! expA ) { + uiZ = uiA + sigB; + goto uiZ; + } + if ( expA == 0x7FF ) { + if ( sigA | sigB ) goto propagateNaN; + uiZ = uiA; + goto uiZ; + } + expZ = expA; + sigZ = UINT64_C( 0x0020000000000000 ) + sigA + sigB; + sigZ <<= 9; + } else { + /*-------------------------------------------------------------------- + *--------------------------------------------------------------------*/ + sigA <<= 9; + sigB <<= 9; + if ( expDiff < 0 ) { + if ( expB == 0x7FF ) { + if ( sigB ) goto propagateNaN; + uiZ = packToF64UI( signZ, 0x7FF, 0 ); + goto uiZ; + } + expZ = expB; + if ( expA ) { + sigA += UINT64_C( 0x2000000000000000 ); + } else { + sigA <<= 1; + } + sigA = softfloat_shiftRightJam64( sigA, -expDiff ); + } else { + if ( expA == 0x7FF ) { + if ( sigA ) goto propagateNaN; + uiZ = uiA; + goto uiZ; + } + expZ = expA; + if ( expB ) { + sigB += UINT64_C( 0x2000000000000000 ); + } else { + sigB <<= 1; + } + sigB = softfloat_shiftRightJam64( sigB, expDiff ); + } + sigZ = UINT64_C( 0x2000000000000000 ) + sigA + sigB; + if ( sigZ < UINT64_C( 0x4000000000000000 ) ) { + --expZ; + sigZ <<= 1; + } + } + return softfloat_roundPackToF64( signZ, expZ, sigZ ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + propagateNaN: + uiZ = softfloat_propagateNaNF64UI( uiA, uiB ); + uiZ: + uZ.ui = uiZ; + return uZ.f; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_approxRecip32_1.c b/vendor/riscv/riscv-isa-sim/softfloat/s_approxRecip32_1.c new file mode 100644 index 0000000000..a06192ed5b --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_approxRecip32_1.c @@ -0,0 +1,66 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "platform.h" + +#ifndef softfloat_approxRecip32_1 + +extern const uint16_t softfloat_approxRecip_1k0s[16]; +extern const uint16_t softfloat_approxRecip_1k1s[16]; + +uint32_t softfloat_approxRecip32_1( uint32_t a ) +{ + int index; + uint16_t eps, r0; + uint32_t sigma0; + uint_fast32_t r; + uint32_t sqrSigma0; + + index = a>>27 & 0xF; + eps = (uint16_t) (a>>11); + r0 = softfloat_approxRecip_1k0s[index] + - ((softfloat_approxRecip_1k1s[index] * (uint_fast32_t) eps)>>20); + sigma0 = ~(uint_fast32_t) ((r0 * (uint_fast64_t) a)>>7); + r = ((uint_fast32_t) r0<<16) + ((r0 * (uint_fast64_t) sigma0)>>24); + sqrSigma0 = ((uint_fast64_t) sigma0 * sigma0)>>32; + r += ((uint32_t) r * (uint_fast64_t) sqrSigma0)>>48; + return r; + +} + +#endif + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_approxRecipSqrt32_1.c b/vendor/riscv/riscv-isa-sim/softfloat/s_approxRecipSqrt32_1.c new file mode 100644 index 0000000000..2ab71a25a6 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_approxRecipSqrt32_1.c @@ -0,0 +1,73 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "platform.h" + +#ifndef softfloat_approxRecipSqrt32_1 + +extern const uint16_t softfloat_approxRecipSqrt_1k0s[]; +extern const uint16_t softfloat_approxRecipSqrt_1k1s[]; + +uint32_t softfloat_approxRecipSqrt32_1( unsigned int oddExpA, uint32_t a ) +{ + int index; + uint16_t eps, r0; + uint_fast32_t ESqrR0; + uint32_t sigma0; + uint_fast32_t r; + uint32_t sqrSigma0; + + index = (a>>27 & 0xE) + oddExpA; + eps = (uint16_t) (a>>12); + r0 = softfloat_approxRecipSqrt_1k0s[index] + - ((softfloat_approxRecipSqrt_1k1s[index] * (uint_fast32_t) eps) + >>20); + ESqrR0 = (uint_fast32_t) r0 * r0; + if ( ! oddExpA ) ESqrR0 <<= 1; + sigma0 = ~(uint_fast32_t) (((uint32_t) ESqrR0 * (uint_fast64_t) a)>>23); + r = ((uint_fast32_t) r0<<16) + ((r0 * (uint_fast64_t) sigma0)>>25); + sqrSigma0 = ((uint_fast64_t) sigma0 * sigma0)>>32; + r += ((uint32_t) ((r>>1) + (r>>3) - ((uint_fast32_t) r0<<14)) + * (uint_fast64_t) sqrSigma0) + >>48; + if ( ! (r & 0x80000000) ) r = 0x80000000; + return r; + +} + +#endif + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_approxRecipSqrt_1Ks.c b/vendor/riscv/riscv-isa-sim/softfloat/s_approxRecipSqrt_1Ks.c new file mode 100644 index 0000000000..a60cf82557 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_approxRecipSqrt_1Ks.c @@ -0,0 +1,49 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "platform.h" +#include "primitives.h" + +const uint16_t softfloat_approxRecipSqrt_1k0s[16] = { + 0xB4C9, 0xFFAB, 0xAA7D, 0xF11C, 0xA1C5, 0xE4C7, 0x9A43, 0xDA29, + 0x93B5, 0xD0E5, 0x8DED, 0xC8B7, 0x88C6, 0xC16D, 0x8424, 0xBAE1 +}; +const uint16_t softfloat_approxRecipSqrt_1k1s[16] = { + 0xA5A5, 0xEA42, 0x8C21, 0xC62D, 0x788F, 0xAA7F, 0x6928, 0x94B6, + 0x5CC7, 0x8335, 0x52A6, 0x74E2, 0x4A3E, 0x68FE, 0x432B, 0x5EFD +}; + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_approxRecip_1Ks.c b/vendor/riscv/riscv-isa-sim/softfloat/s_approxRecip_1Ks.c new file mode 100644 index 0000000000..1108fcbe81 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_approxRecip_1Ks.c @@ -0,0 +1,49 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "platform.h" +#include "primitives.h" + +const uint16_t softfloat_approxRecip_1k0s[16] = { + 0xFFC4, 0xF0BE, 0xE363, 0xD76F, 0xCCAD, 0xC2F0, 0xBA16, 0xB201, + 0xAA97, 0xA3C6, 0x9D7A, 0x97A6, 0x923C, 0x8D32, 0x887E, 0x8417 +}; +const uint16_t softfloat_approxRecip_1k1s[16] = { + 0xF0F1, 0xD62C, 0xBFA1, 0xAC77, 0x9C0A, 0x8DDB, 0x8185, 0x76BA, + 0x6D3B, 0x64D4, 0x5D5C, 0x56B1, 0x50B6, 0x4B55, 0x4679, 0x4211 +}; + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_commonNaNToF128UI.c b/vendor/riscv/riscv-isa-sim/softfloat/s_commonNaNToF128UI.c new file mode 100644 index 0000000000..9b97f3437d --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_commonNaNToF128UI.c @@ -0,0 +1,56 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include "platform.h" +#include "primitiveTypes.h" + +#define softfloat_commonNaNToF128UI softfloat_commonNaNToF128UI +#include "specialize.h" + +/*---------------------------------------------------------------------------- +| Converts the common NaN pointed to by `aPtr' into a 128-bit floating-point +| NaN, and returns the bit pattern of this value as an unsigned integer. +*----------------------------------------------------------------------------*/ +struct uint128 softfloat_commonNaNToF128UI( const struct commonNaN *aPtr ) +{ + struct uint128 uiZ; + + uiZ.v64 = defaultNaNF128UI64; + uiZ.v0 = defaultNaNF128UI0; + return uiZ; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_commonNaNToF16UI.c b/vendor/riscv/riscv-isa-sim/softfloat/s_commonNaNToF16UI.c new file mode 100644 index 0000000000..861b269658 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_commonNaNToF16UI.c @@ -0,0 +1,5 @@ + +/*---------------------------------------------------------------------------- +| This file intentionally contains no code. +*----------------------------------------------------------------------------*/ + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_commonNaNToF32UI.c b/vendor/riscv/riscv-isa-sim/softfloat/s_commonNaNToF32UI.c new file mode 100644 index 0000000000..861b269658 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_commonNaNToF32UI.c @@ -0,0 +1,5 @@ + +/*---------------------------------------------------------------------------- +| This file intentionally contains no code. +*----------------------------------------------------------------------------*/ + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_commonNaNToF64UI.c b/vendor/riscv/riscv-isa-sim/softfloat/s_commonNaNToF64UI.c new file mode 100644 index 0000000000..861b269658 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_commonNaNToF64UI.c @@ -0,0 +1,5 @@ + +/*---------------------------------------------------------------------------- +| This file intentionally contains no code. +*----------------------------------------------------------------------------*/ + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_compare128M.c b/vendor/riscv/riscv-isa-sim/softfloat/s_compare128M.c new file mode 100644 index 0000000000..c2819e20d2 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_compare128M.c @@ -0,0 +1,62 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "platform.h" +#include "primitiveTypes.h" + +#ifndef softfloat_compare128M + +int_fast8_t softfloat_compare128M( const uint32_t *aPtr, const uint32_t *bPtr ) +{ + unsigned int index, lastIndex; + uint32_t wordA, wordB; + + index = indexWordHi( 4 ); + lastIndex = indexWordLo( 4 ); + for (;;) { + wordA = aPtr[index]; + wordB = bPtr[index]; + if ( wordA != wordB ) return (wordA < wordB) ? -1 : 1; + if ( index == lastIndex ) break; + index -= wordIncr; + } + return 0; + +} + +#endif + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_compare96M.c b/vendor/riscv/riscv-isa-sim/softfloat/s_compare96M.c new file mode 100644 index 0000000000..0dc39f5dba --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_compare96M.c @@ -0,0 +1,62 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "platform.h" +#include "primitiveTypes.h" + +#ifndef softfloat_compare96M + +int_fast8_t softfloat_compare96M( const uint32_t *aPtr, const uint32_t *bPtr ) +{ + unsigned int index, lastIndex; + uint32_t wordA, wordB; + + index = indexWordHi( 3 ); + lastIndex = indexWordLo( 3 ); + for (;;) { + wordA = aPtr[index]; + wordB = bPtr[index]; + if ( wordA != wordB ) return (wordA < wordB) ? -1 : 1; + if ( index == lastIndex ) break; + index -= wordIncr; + } + return 0; + +} + +#endif + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_countLeadingZeros16.c b/vendor/riscv/riscv-isa-sim/softfloat/s_countLeadingZeros16.c new file mode 100644 index 0000000000..950db6c84c --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_countLeadingZeros16.c @@ -0,0 +1,60 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "platform.h" + +#ifndef softfloat_countLeadingZeros16 + +#define softfloat_countLeadingZeros16 softfloat_countLeadingZeros16 +#include "primitives.h" + +uint_fast8_t softfloat_countLeadingZeros16( uint16_t a ) +{ + uint_fast8_t count; + + count = 8; + if ( 0x100 <= a ) { + count = 0; + a >>= 8; + } + count += softfloat_countLeadingZeros8[a]; + return count; + +} + +#endif + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_countLeadingZeros32.c b/vendor/riscv/riscv-isa-sim/softfloat/s_countLeadingZeros32.c new file mode 100644 index 0000000000..fbf8ab6afb --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_countLeadingZeros32.c @@ -0,0 +1,64 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "platform.h" + +#ifndef softfloat_countLeadingZeros32 + +#define softfloat_countLeadingZeros32 softfloat_countLeadingZeros32 +#include "primitives.h" + +uint_fast8_t softfloat_countLeadingZeros32( uint32_t a ) +{ + uint_fast8_t count; + + count = 0; + if ( a < 0x10000 ) { + count = 16; + a <<= 16; + } + if ( a < 0x1000000 ) { + count += 8; + a <<= 8; + } + count += softfloat_countLeadingZeros8[a>>24]; + return count; + +} + +#endif + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_countLeadingZeros64.c b/vendor/riscv/riscv-isa-sim/softfloat/s_countLeadingZeros64.c new file mode 100644 index 0000000000..00457418be --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_countLeadingZeros64.c @@ -0,0 +1,73 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "platform.h" + +#ifndef softfloat_countLeadingZeros64 + +#define softfloat_countLeadingZeros64 softfloat_countLeadingZeros64 +#include "primitives.h" + +uint_fast8_t softfloat_countLeadingZeros64( uint64_t a ) +{ + uint_fast8_t count; + uint32_t a32; + + count = 0; + a32 = a>>32; + if ( ! a32 ) { + count = 32; + a32 = a; + } + /*------------------------------------------------------------------------ + | From here, result is current count + count leading zeros of `a32'. + *------------------------------------------------------------------------*/ + if ( a32 < 0x10000 ) { + count += 16; + a32 <<= 16; + } + if ( a32 < 0x1000000 ) { + count += 8; + a32 <<= 8; + } + count += softfloat_countLeadingZeros8[a32>>24]; + return count; + +} + +#endif + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_countLeadingZeros8.c b/vendor/riscv/riscv-isa-sim/softfloat/s_countLeadingZeros8.c new file mode 100644 index 0000000000..1158d01c31 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_countLeadingZeros8.c @@ -0,0 +1,59 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "platform.h" +#include "primitives.h" + +const uint_least8_t softfloat_countLeadingZeros8[256] = { + 8, 7, 6, 6, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, + 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_eq128.c b/vendor/riscv/riscv-isa-sim/softfloat/s_eq128.c new file mode 100644 index 0000000000..625ef002dd --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_eq128.c @@ -0,0 +1,51 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" + +#ifndef softfloat_eq128 + +bool softfloat_eq128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 ) +{ + + return (a64 == b64) && (a0 == b0); + +} + +#endif + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_f128UIToCommonNaN.c b/vendor/riscv/riscv-isa-sim/softfloat/s_f128UIToCommonNaN.c new file mode 100644 index 0000000000..861b269658 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_f128UIToCommonNaN.c @@ -0,0 +1,5 @@ + +/*---------------------------------------------------------------------------- +| This file intentionally contains no code. +*----------------------------------------------------------------------------*/ + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_f16UIToCommonNaN.c b/vendor/riscv/riscv-isa-sim/softfloat/s_f16UIToCommonNaN.c new file mode 100644 index 0000000000..861b269658 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_f16UIToCommonNaN.c @@ -0,0 +1,5 @@ + +/*---------------------------------------------------------------------------- +| This file intentionally contains no code. +*----------------------------------------------------------------------------*/ + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_f32UIToCommonNaN.c b/vendor/riscv/riscv-isa-sim/softfloat/s_f32UIToCommonNaN.c new file mode 100644 index 0000000000..861b269658 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_f32UIToCommonNaN.c @@ -0,0 +1,5 @@ + +/*---------------------------------------------------------------------------- +| This file intentionally contains no code. +*----------------------------------------------------------------------------*/ + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_f64UIToCommonNaN.c b/vendor/riscv/riscv-isa-sim/softfloat/s_f64UIToCommonNaN.c new file mode 100644 index 0000000000..861b269658 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_f64UIToCommonNaN.c @@ -0,0 +1,5 @@ + +/*---------------------------------------------------------------------------- +| This file intentionally contains no code. +*----------------------------------------------------------------------------*/ + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_le128.c b/vendor/riscv/riscv-isa-sim/softfloat/s_le128.c new file mode 100644 index 0000000000..7261012f34 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_le128.c @@ -0,0 +1,51 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" + +#ifndef softfloat_le128 + +bool softfloat_le128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 ) +{ + + return (a64 < b64) || ((a64 == b64) && (a0 <= b0)); + +} + +#endif + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_lt128.c b/vendor/riscv/riscv-isa-sim/softfloat/s_lt128.c new file mode 100644 index 0000000000..0d461c363e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_lt128.c @@ -0,0 +1,51 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" + +#ifndef softfloat_lt128 + +bool softfloat_lt128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 ) +{ + + return (a64 < b64) || ((a64 == b64) && (a0 < b0)); + +} + +#endif + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_mul128By32.c b/vendor/riscv/riscv-isa-sim/softfloat/s_mul128By32.c new file mode 100644 index 0000000000..6e71dd0c53 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_mul128By32.c @@ -0,0 +1,58 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "platform.h" +#include "primitiveTypes.h" + +#ifndef softfloat_mul128By32 + +struct uint128 softfloat_mul128By32( uint64_t a64, uint64_t a0, uint32_t b ) +{ + struct uint128 z; + uint_fast64_t mid; + uint_fast32_t carry; + + z.v0 = a0 * b; + mid = (uint_fast64_t) (uint32_t) (a0>>32) * b; + carry = (uint32_t) ((uint_fast32_t) (z.v0>>32) - (uint_fast32_t) mid); + z.v64 = a64 * b + (uint_fast32_t) ((mid + carry)>>32); + return z; + +} + +#endif + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_mul128MTo256M.c b/vendor/riscv/riscv-isa-sim/softfloat/s_mul128MTo256M.c new file mode 100644 index 0000000000..49a1d294d6 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_mul128MTo256M.c @@ -0,0 +1,100 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "platform.h" +#include "primitiveTypes.h" + +#ifndef softfloat_mul128MTo256M + +void + softfloat_mul128MTo256M( + const uint32_t *aPtr, const uint32_t *bPtr, uint32_t *zPtr ) +{ + uint32_t *lastZPtr, wordB; + uint64_t dwordProd; + uint32_t wordZ; + uint_fast8_t carry; + + bPtr += indexWordLo( 4 ); + lastZPtr = zPtr + indexMultiwordHi( 8, 5 ); + zPtr += indexMultiwordLo( 8, 5 ); + wordB = *bPtr; + dwordProd = (uint64_t) aPtr[indexWord( 4, 0 )] * wordB; + zPtr[indexWord( 5, 0 )] = dwordProd; + dwordProd = (uint64_t) aPtr[indexWord( 4, 1 )] * wordB + (dwordProd>>32); + zPtr[indexWord( 5, 1 )] = dwordProd; + dwordProd = (uint64_t) aPtr[indexWord( 4, 2 )] * wordB + (dwordProd>>32); + zPtr[indexWord( 5, 2 )] = dwordProd; + dwordProd = (uint64_t) aPtr[indexWord( 4, 3 )] * wordB + (dwordProd>>32); + zPtr[indexWord( 5, 3 )] = dwordProd; + zPtr[indexWord( 5, 4 )] = dwordProd>>32; + do { + bPtr += wordIncr; + zPtr += wordIncr; + wordB = *bPtr; + dwordProd = (uint64_t) aPtr[indexWord( 4, 0 )] * wordB; + wordZ = zPtr[indexWord( 5, 0 )] + (uint32_t) dwordProd; + zPtr[indexWord( 5, 0 )] = wordZ; + carry = (wordZ < (uint32_t) dwordProd); + dwordProd = + (uint64_t) aPtr[indexWord( 4, 1 )] * wordB + (dwordProd>>32); + wordZ = zPtr[indexWord( 5, 1 )] + (uint32_t) dwordProd + carry; + zPtr[indexWord( 5, 1 )] = wordZ; + if ( wordZ != (uint32_t) dwordProd ) { + carry = (wordZ < (uint32_t) dwordProd); + } + dwordProd = + (uint64_t) aPtr[indexWord( 4, 2 )] * wordB + (dwordProd>>32); + wordZ = zPtr[indexWord( 5, 2 )] + (uint32_t) dwordProd + carry; + zPtr[indexWord( 5, 2 )] = wordZ; + if ( wordZ != (uint32_t) dwordProd ) { + carry = (wordZ < (uint32_t) dwordProd); + } + dwordProd = + (uint64_t) aPtr[indexWord( 4, 3 )] * wordB + (dwordProd>>32); + wordZ = zPtr[indexWord( 5, 3 )] + (uint32_t) dwordProd + carry; + zPtr[indexWord( 5, 3 )] = wordZ; + if ( wordZ != (uint32_t) dwordProd ) { + carry = (wordZ < (uint32_t) dwordProd); + } + zPtr[indexWord( 5, 4 )] = (dwordProd>>32) + carry; + } while ( zPtr != lastZPtr ); + +} + +#endif + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_mul128To256M.c b/vendor/riscv/riscv-isa-sim/softfloat/s_mul128To256M.c new file mode 100644 index 0000000000..fccc2a698d --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_mul128To256M.c @@ -0,0 +1,71 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "platform.h" + +#ifndef softfloat_mul128To256M + +#define softfloat_mul128To256M softfloat_mul128To256M +#include "primitives.h" + +void + softfloat_mul128To256M( + uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0, uint64_t *zPtr ) +{ + struct uint128 p0, p64, p128; + uint_fast64_t z64, z128, z192; + + p0 = softfloat_mul64To128( a0, b0 ); + zPtr[indexWord( 4, 0 )] = p0.v0; + p64 = softfloat_mul64To128( a64, b0 ); + z64 = p64.v0 + p0.v64; + z128 = p64.v64 + (z64 < p64.v0); + p128 = softfloat_mul64To128( a64, b64 ); + z128 += p128.v0; + z192 = p128.v64 + (z128 < p128.v0); + p64 = softfloat_mul64To128( a0, b64 ); + z64 += p64.v0; + zPtr[indexWord( 4, 1 )] = z64; + p64.v64 += (z64 < p64.v0); + z128 += p64.v64; + zPtr[indexWord( 4, 2 )] = z128; + zPtr[indexWord( 4, 3 )] = z192 + (z128 < p64.v64); + +} + +#endif + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_mul64ByShifted32To128.c b/vendor/riscv/riscv-isa-sim/softfloat/s_mul64ByShifted32To128.c new file mode 100644 index 0000000000..f7e7104ea5 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_mul64ByShifted32To128.c @@ -0,0 +1,56 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "platform.h" +#include "primitiveTypes.h" + +#ifndef softfloat_mul64ByShifted32To128 + +struct uint128 softfloat_mul64ByShifted32To128( uint64_t a, uint32_t b ) +{ + uint_fast64_t mid; + struct uint128 z; + + mid = (uint_fast64_t) (uint32_t) a * b; + z.v0 = mid<<32; + z.v64 = (uint_fast64_t) (uint32_t) (a>>32) * b + (mid>>32); + return z; + +} + +#endif + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_mul64To128.c b/vendor/riscv/riscv-isa-sim/softfloat/s_mul64To128.c new file mode 100644 index 0000000000..6620a20bc1 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_mul64To128.c @@ -0,0 +1,66 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "platform.h" +#include "primitiveTypes.h" + +#ifndef softfloat_mul64To128 + +struct uint128 softfloat_mul64To128( uint64_t a, uint64_t b ) +{ + uint32_t a32, a0, b32, b0; + struct uint128 z; + uint64_t mid1, mid; + + a32 = a>>32; + a0 = a; + b32 = b>>32; + b0 = b; + z.v0 = (uint_fast64_t) a0 * b0; + mid1 = (uint_fast64_t) a32 * b0; + mid = mid1 + (uint_fast64_t) a0 * b32; + z.v64 = (uint_fast64_t) a32 * b32; + z.v64 += (uint_fast64_t) (mid < mid1)<<32 | mid>>32; + mid <<= 32; + z.v0 += mid; + z.v64 += (z.v0 < mid); + return z; + +} + +#endif + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_mul64To128M.c b/vendor/riscv/riscv-isa-sim/softfloat/s_mul64To128M.c new file mode 100644 index 0000000000..e3f9a481eb --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_mul64To128M.c @@ -0,0 +1,68 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "platform.h" +#include "primitiveTypes.h" + +#ifndef softfloat_mul64To128M + +void softfloat_mul64To128M( uint64_t a, uint64_t b, uint32_t *zPtr ) +{ + uint32_t a32, a0, b32, b0; + uint64_t z0, mid1, z64, mid; + + a32 = a>>32; + a0 = a; + b32 = b>>32; + b0 = b; + z0 = (uint64_t) a0 * b0; + mid1 = (uint64_t) a32 * b0; + mid = mid1 + (uint64_t) a0 * b32; + z64 = (uint64_t) a32 * b32; + z64 += (uint64_t) (mid < mid1)<<32 | mid>>32; + mid <<= 32; + z0 += mid; + zPtr[indexWord( 4, 1 )] = z0>>32; + zPtr[indexWord( 4, 0 )] = z0; + z64 += (z0 < mid); + zPtr[indexWord( 4, 3 )] = z64>>32; + zPtr[indexWord( 4, 2 )] = z64; + +} + +#endif + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_mulAddF128.c b/vendor/riscv/riscv-isa-sim/softfloat/s_mulAddF128.c new file mode 100644 index 0000000000..877b33d231 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_mulAddF128.c @@ -0,0 +1,350 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +float128_t + softfloat_mulAddF128( + uint_fast64_t uiA64, + uint_fast64_t uiA0, + uint_fast64_t uiB64, + uint_fast64_t uiB0, + uint_fast64_t uiC64, + uint_fast64_t uiC0, + uint_fast8_t op + ) +{ + bool signA; + int_fast32_t expA; + struct uint128 sigA; + bool signB; + int_fast32_t expB; + struct uint128 sigB; + bool signC; + int_fast32_t expC; + struct uint128 sigC; + bool signZ; + uint_fast64_t magBits; + struct uint128 uiZ; + struct exp32_sig128 normExpSig; + int_fast32_t expZ; + uint64_t sig256Z[4]; + struct uint128 sigZ; + int_fast32_t shiftDist, expDiff; + struct uint128 x128; + uint64_t sig256C[4]; + static uint64_t zero256[4] = INIT_UINTM4( 0, 0, 0, 0 ); + uint_fast64_t sigZExtra, sig256Z0; + union ui128_f128 uZ; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + signA = signF128UI64( uiA64 ); + expA = expF128UI64( uiA64 ); + sigA.v64 = fracF128UI64( uiA64 ); + sigA.v0 = uiA0; + signB = signF128UI64( uiB64 ); + expB = expF128UI64( uiB64 ); + sigB.v64 = fracF128UI64( uiB64 ); + sigB.v0 = uiB0; + signC = signF128UI64( uiC64 ) ^ (op == softfloat_mulAdd_subC); + expC = expF128UI64( uiC64 ); + sigC.v64 = fracF128UI64( uiC64 ); + sigC.v0 = uiC0; + signZ = signA ^ signB ^ (op == softfloat_mulAdd_subProd); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( expA == 0x7FFF ) { + if ( + (sigA.v64 | sigA.v0) || ((expB == 0x7FFF) && (sigB.v64 | sigB.v0)) + ) { + goto propagateNaN_ABC; + } + magBits = expB | sigB.v64 | sigB.v0; + goto infProdArg; + } + if ( expB == 0x7FFF ) { + if ( sigB.v64 | sigB.v0 ) goto propagateNaN_ABC; + magBits = expA | sigA.v64 | sigA.v0; + goto infProdArg; + } + if ( expC == 0x7FFF ) { + if ( sigC.v64 | sigC.v0 ) { + uiZ.v64 = 0; + uiZ.v0 = 0; + goto propagateNaN_ZC; + } + uiZ.v64 = uiC64; + uiZ.v0 = uiC0; + goto uiZ; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( ! expA ) { + if ( ! (sigA.v64 | sigA.v0) ) goto zeroProd; + normExpSig = softfloat_normSubnormalF128Sig( sigA.v64, sigA.v0 ); + expA = normExpSig.exp; + sigA = normExpSig.sig; + } + if ( ! expB ) { + if ( ! (sigB.v64 | sigB.v0) ) goto zeroProd; + normExpSig = softfloat_normSubnormalF128Sig( sigB.v64, sigB.v0 ); + expB = normExpSig.exp; + sigB = normExpSig.sig; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + expZ = expA + expB - 0x3FFE; + sigA.v64 |= UINT64_C( 0x0001000000000000 ); + sigB.v64 |= UINT64_C( 0x0001000000000000 ); + sigA = softfloat_shortShiftLeft128( sigA.v64, sigA.v0, 8 ); + sigB = softfloat_shortShiftLeft128( sigB.v64, sigB.v0, 15 ); + softfloat_mul128To256M( sigA.v64, sigA.v0, sigB.v64, sigB.v0, sig256Z ); + sigZ.v64 = sig256Z[indexWord( 4, 3 )]; + sigZ.v0 = sig256Z[indexWord( 4, 2 )]; + shiftDist = 0; + if ( ! (sigZ.v64 & UINT64_C( 0x0100000000000000 )) ) { + --expZ; + shiftDist = -1; + } + if ( ! expC ) { + if ( ! (sigC.v64 | sigC.v0) ) { + shiftDist += 8; + goto sigZ; + } + normExpSig = softfloat_normSubnormalF128Sig( sigC.v64, sigC.v0 ); + expC = normExpSig.exp; + sigC = normExpSig.sig; + } + sigC.v64 |= UINT64_C( 0x0001000000000000 ); + sigC = softfloat_shortShiftLeft128( sigC.v64, sigC.v0, 8 ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + expDiff = expZ - expC; + if ( expDiff < 0 ) { + expZ = expC; + if ( (signZ == signC) || (expDiff < -1) ) { + shiftDist -= expDiff; + if ( shiftDist ) { + sigZ = + softfloat_shiftRightJam128( sigZ.v64, sigZ.v0, shiftDist ); + } + } else { + if ( ! shiftDist ) { + x128 = + softfloat_shortShiftRight128( + sig256Z[indexWord( 4, 1 )], sig256Z[indexWord( 4, 0 )], + 1 + ); + sig256Z[indexWord( 4, 1 )] = (sigZ.v0<<63) | x128.v64; + sig256Z[indexWord( 4, 0 )] = x128.v0; + sigZ = softfloat_shortShiftRight128( sigZ.v64, sigZ.v0, 1 ); + sig256Z[indexWord( 4, 3 )] = sigZ.v64; + sig256Z[indexWord( 4, 2 )] = sigZ.v0; + } + } + } else { + if ( shiftDist ) softfloat_add256M( sig256Z, sig256Z, sig256Z ); + if ( ! expDiff ) { + sigZ.v64 = sig256Z[indexWord( 4, 3 )]; + sigZ.v0 = sig256Z[indexWord( 4, 2 )]; + } else { + sig256C[indexWord( 4, 3 )] = sigC.v64; + sig256C[indexWord( 4, 2 )] = sigC.v0; + sig256C[indexWord( 4, 1 )] = 0; + sig256C[indexWord( 4, 0 )] = 0; + softfloat_shiftRightJam256M( sig256C, expDiff, sig256C ); + } + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + shiftDist = 8; + if ( signZ == signC ) { + /*-------------------------------------------------------------------- + *--------------------------------------------------------------------*/ + if ( expDiff <= 0 ) { + sigZ = softfloat_add128( sigC.v64, sigC.v0, sigZ.v64, sigZ.v0 ); + } else { + softfloat_add256M( sig256Z, sig256C, sig256Z ); + sigZ.v64 = sig256Z[indexWord( 4, 3 )]; + sigZ.v0 = sig256Z[indexWord( 4, 2 )]; + } + if ( sigZ.v64 & UINT64_C( 0x0200000000000000 ) ) { + ++expZ; + shiftDist = 9; + } + } else { + /*-------------------------------------------------------------------- + *--------------------------------------------------------------------*/ + if ( expDiff < 0 ) { + signZ = signC; + if ( expDiff < -1 ) { + sigZ = + softfloat_sub128( sigC.v64, sigC.v0, sigZ.v64, sigZ.v0 ); + sigZExtra = + sig256Z[indexWord( 4, 1 )] | sig256Z[indexWord( 4, 0 )]; + if ( sigZExtra ) { + sigZ = softfloat_sub128( sigZ.v64, sigZ.v0, 0, 1 ); + } + if ( ! (sigZ.v64 & UINT64_C( 0x0100000000000000 )) ) { + --expZ; + shiftDist = 7; + } + goto shiftRightRoundPack; + } else { + sig256C[indexWord( 4, 3 )] = sigC.v64; + sig256C[indexWord( 4, 2 )] = sigC.v0; + sig256C[indexWord( 4, 1 )] = 0; + sig256C[indexWord( 4, 0 )] = 0; + softfloat_sub256M( sig256C, sig256Z, sig256Z ); + } + } else if ( ! expDiff ) { + sigZ = softfloat_sub128( sigZ.v64, sigZ.v0, sigC.v64, sigC.v0 ); + if ( + ! (sigZ.v64 | sigZ.v0) && ! sig256Z[indexWord( 4, 1 )] + && ! sig256Z[indexWord( 4, 0 )] + ) { + goto completeCancellation; + } + sig256Z[indexWord( 4, 3 )] = sigZ.v64; + sig256Z[indexWord( 4, 2 )] = sigZ.v0; + if ( sigZ.v64 & UINT64_C( 0x8000000000000000 ) ) { + signZ = ! signZ; + softfloat_sub256M( zero256, sig256Z, sig256Z ); + } + } else { + softfloat_sub256M( sig256Z, sig256C, sig256Z ); + if ( 1 < expDiff ) { + sigZ.v64 = sig256Z[indexWord( 4, 3 )]; + sigZ.v0 = sig256Z[indexWord( 4, 2 )]; + if ( ! (sigZ.v64 & UINT64_C( 0x0100000000000000 )) ) { + --expZ; + shiftDist = 7; + } + goto sigZ; + } + } + /*-------------------------------------------------------------------- + *--------------------------------------------------------------------*/ + sigZ.v64 = sig256Z[indexWord( 4, 3 )]; + sigZ.v0 = sig256Z[indexWord( 4, 2 )]; + sigZExtra = sig256Z[indexWord( 4, 1 )]; + sig256Z0 = sig256Z[indexWord( 4, 0 )]; + if ( sigZ.v64 ) { + if ( sig256Z0 ) sigZExtra |= 1; + } else { + expZ -= 64; + sigZ.v64 = sigZ.v0; + sigZ.v0 = sigZExtra; + sigZExtra = sig256Z0; + if ( ! sigZ.v64 ) { + expZ -= 64; + sigZ.v64 = sigZ.v0; + sigZ.v0 = sigZExtra; + sigZExtra = 0; + if ( ! sigZ.v64 ) { + expZ -= 64; + sigZ.v64 = sigZ.v0; + sigZ.v0 = 0; + } + } + } + shiftDist = softfloat_countLeadingZeros64( sigZ.v64 ); + expZ += 7 - shiftDist; + shiftDist = 15 - shiftDist; + if ( 0 < shiftDist ) goto shiftRightRoundPack; + if ( shiftDist ) { + shiftDist = -shiftDist; + sigZ = softfloat_shortShiftLeft128( sigZ.v64, sigZ.v0, shiftDist ); + x128 = softfloat_shortShiftLeft128( 0, sigZExtra, shiftDist ); + sigZ.v0 |= x128.v64; + sigZExtra = x128.v0; + } + goto roundPack; + } + sigZ: + sigZExtra = sig256Z[indexWord( 4, 1 )] | sig256Z[indexWord( 4, 0 )]; + shiftRightRoundPack: + sigZExtra = (uint64_t) (sigZ.v0<<(64 - shiftDist)) | (sigZExtra != 0); + sigZ = softfloat_shortShiftRight128( sigZ.v64, sigZ.v0, shiftDist ); + roundPack: + return + softfloat_roundPackToF128( + signZ, expZ - 1, sigZ.v64, sigZ.v0, sigZExtra ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + propagateNaN_ABC: + uiZ = softfloat_propagateNaNF128UI( uiA64, uiA0, uiB64, uiB0 ); + goto propagateNaN_ZC; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + infProdArg: + if ( magBits ) { + uiZ.v64 = packToF128UI64( signZ, 0x7FFF, 0 ); + uiZ.v0 = 0; + if ( expC != 0x7FFF ) goto uiZ; + if ( sigC.v64 | sigC.v0 ) goto propagateNaN_ZC; + if ( signZ == signC ) goto uiZ; + } + softfloat_raiseFlags( softfloat_flag_invalid ); + uiZ.v64 = defaultNaNF128UI64; + uiZ.v0 = defaultNaNF128UI0; + propagateNaN_ZC: + uiZ = softfloat_propagateNaNF128UI( uiZ.v64, uiZ.v0, uiC64, uiC0 ); + goto uiZ; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + zeroProd: + uiZ.v64 = uiC64; + uiZ.v0 = uiC0; + if ( ! (expC | sigC.v64 | sigC.v0) && (signZ != signC) ) { + completeCancellation: + uiZ.v64 = + packToF128UI64( + (softfloat_roundingMode == softfloat_round_min), 0, 0 ); + uiZ.v0 = 0; + } + uiZ: + uZ.ui = uiZ; + return uZ.f; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_mulAddF16.c b/vendor/riscv/riscv-isa-sim/softfloat/s_mulAddF16.c new file mode 100644 index 0000000000..b604007232 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_mulAddF16.c @@ -0,0 +1,226 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +float16_t + softfloat_mulAddF16( + uint_fast16_t uiA, uint_fast16_t uiB, uint_fast16_t uiC, uint_fast8_t op ) +{ + bool signA; + int_fast8_t expA; + uint_fast16_t sigA; + bool signB; + int_fast8_t expB; + uint_fast16_t sigB; + bool signC; + int_fast8_t expC; + uint_fast16_t sigC; + bool signProd; + uint_fast16_t magBits, uiZ; + struct exp8_sig16 normExpSig; + int_fast8_t expProd; + uint_fast32_t sigProd; + bool signZ; + int_fast8_t expZ; + uint_fast16_t sigZ; + int_fast8_t expDiff; + uint_fast32_t sig32Z, sig32C; + int_fast8_t shiftDist; + union ui16_f16 uZ; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + signA = signF16UI( uiA ); + expA = expF16UI( uiA ); + sigA = fracF16UI( uiA ); + signB = signF16UI( uiB ); + expB = expF16UI( uiB ); + sigB = fracF16UI( uiB ); + signC = signF16UI( uiC ) ^ (op == softfloat_mulAdd_subC); + expC = expF16UI( uiC ); + sigC = fracF16UI( uiC ); + signProd = signA ^ signB ^ (op == softfloat_mulAdd_subProd); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( expA == 0x1F ) { + if ( sigA || ((expB == 0x1F) && sigB) ) goto propagateNaN_ABC; + magBits = expB | sigB; + goto infProdArg; + } + if ( expB == 0x1F ) { + if ( sigB ) goto propagateNaN_ABC; + magBits = expA | sigA; + goto infProdArg; + } + if ( expC == 0x1F ) { + if ( sigC ) { + uiZ = 0; + goto propagateNaN_ZC; + } + uiZ = uiC; + goto uiZ; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( ! expA ) { + if ( ! sigA ) goto zeroProd; + normExpSig = softfloat_normSubnormalF16Sig( sigA ); + expA = normExpSig.exp; + sigA = normExpSig.sig; + } + if ( ! expB ) { + if ( ! sigB ) goto zeroProd; + normExpSig = softfloat_normSubnormalF16Sig( sigB ); + expB = normExpSig.exp; + sigB = normExpSig.sig; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + expProd = expA + expB - 0xE; + sigA = (sigA | 0x0400)<<4; + sigB = (sigB | 0x0400)<<4; + sigProd = (uint_fast32_t) sigA * sigB; + if ( sigProd < 0x20000000 ) { + --expProd; + sigProd <<= 1; + } + signZ = signProd; + if ( ! expC ) { + if ( ! sigC ) { + expZ = expProd - 1; + sigZ = sigProd>>15 | ((sigProd & 0x7FFF) != 0); + goto roundPack; + } + normExpSig = softfloat_normSubnormalF16Sig( sigC ); + expC = normExpSig.exp; + sigC = normExpSig.sig; + } + sigC = (sigC | 0x0400)<<3; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + expDiff = expProd - expC; + if ( signProd == signC ) { + /*-------------------------------------------------------------------- + *--------------------------------------------------------------------*/ + if ( expDiff <= 0 ) { + expZ = expC; + sigZ = sigC + softfloat_shiftRightJam32( sigProd, 16 - expDiff ); + } else { + expZ = expProd; + sig32Z = + sigProd + + softfloat_shiftRightJam32( + (uint_fast32_t) sigC<<16, expDiff ); + sigZ = sig32Z>>16 | ((sig32Z & 0xFFFF) != 0 ); + } + if ( sigZ < 0x4000 ) { + --expZ; + sigZ <<= 1; + } + } else { + /*-------------------------------------------------------------------- + *--------------------------------------------------------------------*/ + sig32C = (uint_fast32_t) sigC<<16; + if ( expDiff < 0 ) { + signZ = signC; + expZ = expC; + sig32Z = sig32C - softfloat_shiftRightJam32( sigProd, -expDiff ); + } else if ( ! expDiff ) { + expZ = expProd; + sig32Z = sigProd - sig32C; + if ( ! sig32Z ) goto completeCancellation; + if ( sig32Z & 0x80000000 ) { + signZ = ! signZ; + sig32Z = -sig32Z; + } + } else { + expZ = expProd; + sig32Z = sigProd - softfloat_shiftRightJam32( sig32C, expDiff ); + } + shiftDist = softfloat_countLeadingZeros32( sig32Z ) - 1; + expZ -= shiftDist; + shiftDist -= 16; + if ( shiftDist < 0 ) { + sigZ = + sig32Z>>(-shiftDist) + | ((uint32_t) (sig32Z<<(shiftDist & 31)) != 0); + } else { + sigZ = (uint_fast16_t) sig32Z<<shiftDist; + } + } + roundPack: + return softfloat_roundPackToF16( signZ, expZ, sigZ ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + propagateNaN_ABC: + uiZ = softfloat_propagateNaNF16UI( uiA, uiB ); + goto propagateNaN_ZC; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + infProdArg: + if ( magBits ) { + uiZ = packToF16UI( signProd, 0x1F, 0 ); + if ( expC != 0x1F ) goto uiZ; + if ( sigC ) goto propagateNaN_ZC; + if ( signProd == signC ) goto uiZ; + } + softfloat_raiseFlags( softfloat_flag_invalid ); + uiZ = defaultNaNF16UI; + propagateNaN_ZC: + uiZ = softfloat_propagateNaNF16UI( uiZ, uiC ); + goto uiZ; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + zeroProd: + uiZ = uiC; + if ( ! (expC | sigC) && (signProd != signC) ) { + completeCancellation: + uiZ = + packToF16UI( + (softfloat_roundingMode == softfloat_round_min), 0, 0 ); + } + uiZ: + uZ.ui = uiZ; + return uZ.f; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_mulAddF32.c b/vendor/riscv/riscv-isa-sim/softfloat/s_mulAddF32.c new file mode 100644 index 0000000000..d163ea02ed --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_mulAddF32.c @@ -0,0 +1,224 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +float32_t + softfloat_mulAddF32( + uint_fast32_t uiA, uint_fast32_t uiB, uint_fast32_t uiC, uint_fast8_t op ) +{ + bool signA; + int_fast16_t expA; + uint_fast32_t sigA; + bool signB; + int_fast16_t expB; + uint_fast32_t sigB; + bool signC; + int_fast16_t expC; + uint_fast32_t sigC; + bool signProd; + uint_fast32_t magBits, uiZ; + struct exp16_sig32 normExpSig; + int_fast16_t expProd; + uint_fast64_t sigProd; + bool signZ; + int_fast16_t expZ; + uint_fast32_t sigZ; + int_fast16_t expDiff; + uint_fast64_t sig64Z, sig64C; + int_fast8_t shiftDist; + union ui32_f32 uZ; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + signA = signF32UI( uiA ); + expA = expF32UI( uiA ); + sigA = fracF32UI( uiA ); + signB = signF32UI( uiB ); + expB = expF32UI( uiB ); + sigB = fracF32UI( uiB ); + signC = signF32UI( uiC ) ^ (op == softfloat_mulAdd_subC); + expC = expF32UI( uiC ); + sigC = fracF32UI( uiC ); + signProd = signA ^ signB ^ (op == softfloat_mulAdd_subProd); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( expA == 0xFF ) { + if ( sigA || ((expB == 0xFF) && sigB) ) goto propagateNaN_ABC; + magBits = expB | sigB; + goto infProdArg; + } + if ( expB == 0xFF ) { + if ( sigB ) goto propagateNaN_ABC; + magBits = expA | sigA; + goto infProdArg; + } + if ( expC == 0xFF ) { + if ( sigC ) { + uiZ = 0; + goto propagateNaN_ZC; + } + uiZ = uiC; + goto uiZ; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( ! expA ) { + if ( ! sigA ) goto zeroProd; + normExpSig = softfloat_normSubnormalF32Sig( sigA ); + expA = normExpSig.exp; + sigA = normExpSig.sig; + } + if ( ! expB ) { + if ( ! sigB ) goto zeroProd; + normExpSig = softfloat_normSubnormalF32Sig( sigB ); + expB = normExpSig.exp; + sigB = normExpSig.sig; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + expProd = expA + expB - 0x7E; + sigA = (sigA | 0x00800000)<<7; + sigB = (sigB | 0x00800000)<<7; + sigProd = (uint_fast64_t) sigA * sigB; + if ( sigProd < UINT64_C( 0x2000000000000000 ) ) { + --expProd; + sigProd <<= 1; + } + signZ = signProd; + if ( ! expC ) { + if ( ! sigC ) { + expZ = expProd - 1; + sigZ = softfloat_shortShiftRightJam64( sigProd, 31 ); + goto roundPack; + } + normExpSig = softfloat_normSubnormalF32Sig( sigC ); + expC = normExpSig.exp; + sigC = normExpSig.sig; + } + sigC = (sigC | 0x00800000)<<6; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + expDiff = expProd - expC; + if ( signProd == signC ) { + /*-------------------------------------------------------------------- + *--------------------------------------------------------------------*/ + if ( expDiff <= 0 ) { + expZ = expC; + sigZ = sigC + softfloat_shiftRightJam64( sigProd, 32 - expDiff ); + } else { + expZ = expProd; + sig64Z = + sigProd + + softfloat_shiftRightJam64( + (uint_fast64_t) sigC<<32, expDiff ); + sigZ = softfloat_shortShiftRightJam64( sig64Z, 32 ); + } + if ( sigZ < 0x40000000 ) { + --expZ; + sigZ <<= 1; + } + } else { + /*-------------------------------------------------------------------- + *--------------------------------------------------------------------*/ + sig64C = (uint_fast64_t) sigC<<32; + if ( expDiff < 0 ) { + signZ = signC; + expZ = expC; + sig64Z = sig64C - softfloat_shiftRightJam64( sigProd, -expDiff ); + } else if ( ! expDiff ) { + expZ = expProd; + sig64Z = sigProd - sig64C; + if ( ! sig64Z ) goto completeCancellation; + if ( sig64Z & UINT64_C( 0x8000000000000000 ) ) { + signZ = ! signZ; + sig64Z = -sig64Z; + } + } else { + expZ = expProd; + sig64Z = sigProd - softfloat_shiftRightJam64( sig64C, expDiff ); + } + shiftDist = softfloat_countLeadingZeros64( sig64Z ) - 1; + expZ -= shiftDist; + shiftDist -= 32; + if ( shiftDist < 0 ) { + sigZ = softfloat_shortShiftRightJam64( sig64Z, -shiftDist ); + } else { + sigZ = (uint_fast32_t) sig64Z<<shiftDist; + } + } + roundPack: + return softfloat_roundPackToF32( signZ, expZ, sigZ ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + propagateNaN_ABC: + uiZ = softfloat_propagateNaNF32UI( uiA, uiB ); + goto propagateNaN_ZC; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + infProdArg: + if ( magBits ) { + uiZ = packToF32UI( signProd, 0xFF, 0 ); + if ( expC != 0xFF ) goto uiZ; + if ( sigC ) goto propagateNaN_ZC; + if ( signProd == signC ) goto uiZ; + } + softfloat_raiseFlags( softfloat_flag_invalid ); + uiZ = defaultNaNF32UI; + propagateNaN_ZC: + uiZ = softfloat_propagateNaNF32UI( uiZ, uiC ); + goto uiZ; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + zeroProd: + uiZ = uiC; + if ( ! (expC | sigC) && (signProd != signC) ) { + completeCancellation: + uiZ = + packToF32UI( + (softfloat_roundingMode == softfloat_round_min), 0, 0 ); + } + uiZ: + uZ.ui = uiZ; + return uZ.f; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_mulAddF64.c b/vendor/riscv/riscv-isa-sim/softfloat/s_mulAddF64.c new file mode 100644 index 0000000000..484ac586d8 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_mulAddF64.c @@ -0,0 +1,496 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +#ifdef SOFTFLOAT_FAST_INT64 + +float64_t + softfloat_mulAddF64( + uint_fast64_t uiA, uint_fast64_t uiB, uint_fast64_t uiC, uint_fast8_t op ) +{ + bool signA; + int_fast16_t expA; + uint_fast64_t sigA; + bool signB; + int_fast16_t expB; + uint_fast64_t sigB; + bool signC; + int_fast16_t expC; + uint_fast64_t sigC; + bool signZ; + uint_fast64_t magBits, uiZ; + struct exp16_sig64 normExpSig; + int_fast16_t expZ; + struct uint128 sig128Z; + uint_fast64_t sigZ; + int_fast16_t expDiff; + struct uint128 sig128C; + int_fast8_t shiftDist; + union ui64_f64 uZ; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + signA = signF64UI( uiA ); + expA = expF64UI( uiA ); + sigA = fracF64UI( uiA ); + signB = signF64UI( uiB ); + expB = expF64UI( uiB ); + sigB = fracF64UI( uiB ); + signC = signF64UI( uiC ) ^ (op == softfloat_mulAdd_subC); + expC = expF64UI( uiC ); + sigC = fracF64UI( uiC ); + signZ = signA ^ signB ^ (op == softfloat_mulAdd_subProd); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( expA == 0x7FF ) { + if ( sigA || ((expB == 0x7FF) && sigB) ) goto propagateNaN_ABC; + magBits = expB | sigB; + goto infProdArg; + } + if ( expB == 0x7FF ) { + if ( sigB ) goto propagateNaN_ABC; + magBits = expA | sigA; + goto infProdArg; + } + if ( expC == 0x7FF ) { + if ( sigC ) { + uiZ = 0; + goto propagateNaN_ZC; + } + uiZ = uiC; + goto uiZ; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( ! expA ) { + if ( ! sigA ) goto zeroProd; + normExpSig = softfloat_normSubnormalF64Sig( sigA ); + expA = normExpSig.exp; + sigA = normExpSig.sig; + } + if ( ! expB ) { + if ( ! sigB ) goto zeroProd; + normExpSig = softfloat_normSubnormalF64Sig( sigB ); + expB = normExpSig.exp; + sigB = normExpSig.sig; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + expZ = expA + expB - 0x3FE; + sigA = (sigA | UINT64_C( 0x0010000000000000 ))<<10; + sigB = (sigB | UINT64_C( 0x0010000000000000 ))<<10; + sig128Z = softfloat_mul64To128( sigA, sigB ); + if ( sig128Z.v64 < UINT64_C( 0x2000000000000000 ) ) { + --expZ; + sig128Z = + softfloat_add128( + sig128Z.v64, sig128Z.v0, sig128Z.v64, sig128Z.v0 ); + } + if ( ! expC ) { + if ( ! sigC ) { + --expZ; + sigZ = sig128Z.v64<<1 | (sig128Z.v0 != 0); + goto roundPack; + } + normExpSig = softfloat_normSubnormalF64Sig( sigC ); + expC = normExpSig.exp; + sigC = normExpSig.sig; + } + sigC = (sigC | UINT64_C( 0x0010000000000000 ))<<9; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + expDiff = expZ - expC; + if ( expDiff < 0 ) { + expZ = expC; + if ( (signZ == signC) || (expDiff < -1) ) { + sig128Z.v64 = softfloat_shiftRightJam64( sig128Z.v64, -expDiff ); + } else { + sig128Z = + softfloat_shortShiftRightJam128( sig128Z.v64, sig128Z.v0, 1 ); + } + } else if ( expDiff ) { + sig128C = softfloat_shiftRightJam128( sigC, 0, expDiff ); + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( signZ == signC ) { + /*-------------------------------------------------------------------- + *--------------------------------------------------------------------*/ + if ( expDiff <= 0 ) { + sigZ = (sigC + sig128Z.v64) | (sig128Z.v0 != 0); + } else { + sig128Z = + softfloat_add128( + sig128Z.v64, sig128Z.v0, sig128C.v64, sig128C.v0 ); + sigZ = sig128Z.v64 | (sig128Z.v0 != 0); + } + if ( sigZ < UINT64_C( 0x4000000000000000 ) ) { + --expZ; + sigZ <<= 1; + } + } else { + /*-------------------------------------------------------------------- + *--------------------------------------------------------------------*/ + if ( expDiff < 0 ) { + signZ = signC; + sig128Z = softfloat_sub128( sigC, 0, sig128Z.v64, sig128Z.v0 ); + } else if ( ! expDiff ) { + sig128Z.v64 = sig128Z.v64 - sigC; + if ( ! (sig128Z.v64 | sig128Z.v0) ) goto completeCancellation; + if ( sig128Z.v64 & UINT64_C( 0x8000000000000000 ) ) { + signZ = ! signZ; + sig128Z = softfloat_sub128( 0, 0, sig128Z.v64, sig128Z.v0 ); + } + } else { + sig128Z = + softfloat_sub128( + sig128Z.v64, sig128Z.v0, sig128C.v64, sig128C.v0 ); + } + /*-------------------------------------------------------------------- + *--------------------------------------------------------------------*/ + if ( ! sig128Z.v64 ) { + expZ -= 64; + sig128Z.v64 = sig128Z.v0; + sig128Z.v0 = 0; + } + shiftDist = softfloat_countLeadingZeros64( sig128Z.v64 ) - 1; + expZ -= shiftDist; + if ( shiftDist < 0 ) { + sigZ = softfloat_shortShiftRightJam64( sig128Z.v64, -shiftDist ); + } else { + sig128Z = + softfloat_shortShiftLeft128( + sig128Z.v64, sig128Z.v0, shiftDist ); + sigZ = sig128Z.v64; + } + sigZ |= (sig128Z.v0 != 0); + } + roundPack: + return softfloat_roundPackToF64( signZ, expZ, sigZ ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + propagateNaN_ABC: + uiZ = softfloat_propagateNaNF64UI( uiA, uiB ); + goto propagateNaN_ZC; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + infProdArg: + if ( magBits ) { + uiZ = packToF64UI( signZ, 0x7FF, 0 ); + if ( expC != 0x7FF ) goto uiZ; + if ( sigC ) goto propagateNaN_ZC; + if ( signZ == signC ) goto uiZ; + } + softfloat_raiseFlags( softfloat_flag_invalid ); + uiZ = defaultNaNF64UI; + propagateNaN_ZC: + uiZ = softfloat_propagateNaNF64UI( uiZ, uiC ); + goto uiZ; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + zeroProd: + uiZ = uiC; + if ( ! (expC | sigC) && (signZ != signC) ) { + completeCancellation: + uiZ = + packToF64UI( + (softfloat_roundingMode == softfloat_round_min), 0, 0 ); + } + uiZ: + uZ.ui = uiZ; + return uZ.f; + +} + +#else + +float64_t + softfloat_mulAddF64( + uint_fast64_t uiA, uint_fast64_t uiB, uint_fast64_t uiC, uint_fast8_t op ) +{ + bool signA; + int_fast16_t expA; + uint64_t sigA; + bool signB; + int_fast16_t expB; + uint64_t sigB; + bool signC; + int_fast16_t expC; + uint64_t sigC; + bool signZ; + uint64_t magBits, uiZ; + struct exp16_sig64 normExpSig; + int_fast16_t expZ; + uint32_t sig128Z[4]; + uint64_t sigZ; + int_fast16_t shiftDist, expDiff; + uint32_t sig128C[4]; + union ui64_f64 uZ; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + signA = signF64UI( uiA ); + expA = expF64UI( uiA ); + sigA = fracF64UI( uiA ); + signB = signF64UI( uiB ); + expB = expF64UI( uiB ); + sigB = fracF64UI( uiB ); + signC = signF64UI( uiC ) ^ (op == softfloat_mulAdd_subC); + expC = expF64UI( uiC ); + sigC = fracF64UI( uiC ); + signZ = signA ^ signB ^ (op == softfloat_mulAdd_subProd); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( expA == 0x7FF ) { + if ( sigA || ((expB == 0x7FF) && sigB) ) goto propagateNaN_ABC; + magBits = expB | sigB; + goto infProdArg; + } + if ( expB == 0x7FF ) { + if ( sigB ) goto propagateNaN_ABC; + magBits = expA | sigA; + goto infProdArg; + } + if ( expC == 0x7FF ) { + if ( sigC ) { + uiZ = 0; + goto propagateNaN_ZC; + } + uiZ = uiC; + goto uiZ; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( ! expA ) { + if ( ! sigA ) goto zeroProd; + normExpSig = softfloat_normSubnormalF64Sig( sigA ); + expA = normExpSig.exp; + sigA = normExpSig.sig; + } + if ( ! expB ) { + if ( ! sigB ) goto zeroProd; + normExpSig = softfloat_normSubnormalF64Sig( sigB ); + expB = normExpSig.exp; + sigB = normExpSig.sig; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + expZ = expA + expB - 0x3FE; + sigA = (sigA | UINT64_C( 0x0010000000000000 ))<<10; + sigB = (sigB | UINT64_C( 0x0010000000000000 ))<<11; + softfloat_mul64To128M( sigA, sigB, sig128Z ); + sigZ = + (uint64_t) sig128Z[indexWord( 4, 3 )]<<32 | sig128Z[indexWord( 4, 2 )]; + shiftDist = 0; + if ( ! (sigZ & UINT64_C( 0x4000000000000000 )) ) { + --expZ; + shiftDist = -1; + } + if ( ! expC ) { + if ( ! sigC ) { + if ( shiftDist ) sigZ <<= 1; + goto sigZ; + } + normExpSig = softfloat_normSubnormalF64Sig( sigC ); + expC = normExpSig.exp; + sigC = normExpSig.sig; + } + sigC = (sigC | UINT64_C( 0x0010000000000000 ))<<10; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + expDiff = expZ - expC; + if ( expDiff < 0 ) { + expZ = expC; + if ( (signZ == signC) || (expDiff < -1) ) { + shiftDist -= expDiff; + if ( shiftDist) { + sigZ = softfloat_shiftRightJam64( sigZ, shiftDist ); + } + } else { + if ( ! shiftDist ) { + softfloat_shortShiftRight128M( sig128Z, 1, sig128Z ); + } + } + } else { + if ( shiftDist ) softfloat_add128M( sig128Z, sig128Z, sig128Z ); + if ( ! expDiff ) { + sigZ = + (uint64_t) sig128Z[indexWord( 4, 3 )]<<32 + | sig128Z[indexWord( 4, 2 )]; + } else { + sig128C[indexWord( 4, 3 )] = sigC>>32; + sig128C[indexWord( 4, 2 )] = sigC; + sig128C[indexWord( 4, 1 )] = 0; + sig128C[indexWord( 4, 0 )] = 0; + softfloat_shiftRightJam128M( sig128C, expDiff, sig128C ); + } + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( signZ == signC ) { + /*-------------------------------------------------------------------- + *--------------------------------------------------------------------*/ + if ( expDiff <= 0 ) { + sigZ += sigC; + } else { + softfloat_add128M( sig128Z, sig128C, sig128Z ); + sigZ = + (uint64_t) sig128Z[indexWord( 4, 3 )]<<32 + | sig128Z[indexWord( 4, 2 )]; + } + if ( sigZ & UINT64_C( 0x8000000000000000 ) ) { + ++expZ; + sigZ = softfloat_shortShiftRightJam64( sigZ, 1 ); + } + } else { + /*-------------------------------------------------------------------- + *--------------------------------------------------------------------*/ + if ( expDiff < 0 ) { + signZ = signC; + if ( expDiff < -1 ) { + sigZ = sigC - sigZ; + if ( + sig128Z[indexWord( 4, 1 )] || sig128Z[indexWord( 4, 0 )] + ) { + sigZ = (sigZ - 1) | 1; + } + if ( ! (sigZ & UINT64_C( 0x4000000000000000 )) ) { + --expZ; + sigZ <<= 1; + } + goto roundPack; + } else { + sig128C[indexWord( 4, 3 )] = sigC>>32; + sig128C[indexWord( 4, 2 )] = sigC; + sig128C[indexWord( 4, 1 )] = 0; + sig128C[indexWord( 4, 0 )] = 0; + softfloat_sub128M( sig128C, sig128Z, sig128Z ); + } + } else if ( ! expDiff ) { + sigZ -= sigC; + if ( + ! sigZ && ! sig128Z[indexWord( 4, 1 )] + && ! sig128Z[indexWord( 4, 0 )] + ) { + goto completeCancellation; + } + sig128Z[indexWord( 4, 3 )] = sigZ>>32; + sig128Z[indexWord( 4, 2 )] = sigZ; + if ( sigZ & UINT64_C( 0x8000000000000000 ) ) { + signZ = ! signZ; + softfloat_negX128M( sig128Z ); + } + } else { + softfloat_sub128M( sig128Z, sig128C, sig128Z ); + if ( 1 < expDiff ) { + sigZ = + (uint64_t) sig128Z[indexWord( 4, 3 )]<<32 + | sig128Z[indexWord( 4, 2 )]; + if ( ! (sigZ & UINT64_C( 0x4000000000000000 )) ) { + --expZ; + sigZ <<= 1; + } + goto sigZ; + } + } + /*-------------------------------------------------------------------- + *--------------------------------------------------------------------*/ + shiftDist = 0; + sigZ = + (uint64_t) sig128Z[indexWord( 4, 3 )]<<32 + | sig128Z[indexWord( 4, 2 )]; + if ( ! sigZ ) { + shiftDist = 64; + sigZ = + (uint64_t) sig128Z[indexWord( 4, 1 )]<<32 + | sig128Z[indexWord( 4, 0 )]; + } + shiftDist += softfloat_countLeadingZeros64( sigZ ) - 1; + if ( shiftDist ) { + expZ -= shiftDist; + softfloat_shiftLeft128M( sig128Z, shiftDist, sig128Z ); + sigZ = + (uint64_t) sig128Z[indexWord( 4, 3 )]<<32 + | sig128Z[indexWord( 4, 2 )]; + } + } + sigZ: + if ( sig128Z[indexWord( 4, 1 )] || sig128Z[indexWord( 4, 0 )] ) sigZ |= 1; + roundPack: + return softfloat_roundPackToF64( signZ, expZ - 1, sigZ ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + propagateNaN_ABC: + uiZ = softfloat_propagateNaNF64UI( uiA, uiB ); + goto propagateNaN_ZC; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + infProdArg: + if ( magBits ) { + uiZ = packToF64UI( signZ, 0x7FF, 0 ); + if ( expC != 0x7FF ) goto uiZ; + if ( sigC ) goto propagateNaN_ZC; + if ( signZ == signC ) goto uiZ; + } + softfloat_raiseFlags( softfloat_flag_invalid ); + uiZ = defaultNaNF64UI; + propagateNaN_ZC: + uiZ = softfloat_propagateNaNF64UI( uiZ, uiC ); + goto uiZ; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + zeroProd: + uiZ = uiC; + if ( ! (expC | sigC) && (signZ != signC) ) { + completeCancellation: + uiZ = + packToF64UI( + (softfloat_roundingMode == softfloat_round_min), 0, 0 ); + } + uiZ: + uZ.ui = uiZ; + return uZ.f; + +} + +#endif + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_negXM.c b/vendor/riscv/riscv-isa-sim/softfloat/s_negXM.c new file mode 100644 index 0000000000..76f110c1cf --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_negXM.c @@ -0,0 +1,63 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "platform.h" +#include "primitiveTypes.h" + +#ifndef softfloat_negXM + +void softfloat_negXM( uint_fast8_t size_words, uint32_t *zPtr ) +{ + unsigned int index, lastIndex; + uint_fast8_t carry; + uint32_t word; + + index = indexWordLo( size_words ); + lastIndex = indexWordHi( size_words ); + carry = 1; + for (;;) { + word = ~zPtr[index] + carry; + zPtr[index] = word; + if ( index == lastIndex ) break; + index += wordIncr; + if ( word ) carry = 0; + } + +} + +#endif + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_normRoundPackToF128.c b/vendor/riscv/riscv-isa-sim/softfloat/s_normRoundPackToF128.c new file mode 100644 index 0000000000..148cb2c80c --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_normRoundPackToF128.c @@ -0,0 +1,81 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" + +float128_t + softfloat_normRoundPackToF128( + bool sign, int_fast32_t exp, uint_fast64_t sig64, uint_fast64_t sig0 ) +{ + int_fast8_t shiftDist; + struct uint128 sig128; + union ui128_f128 uZ; + uint_fast64_t sigExtra; + struct uint128_extra sig128Extra; + + if ( ! sig64 ) { + exp -= 64; + sig64 = sig0; + sig0 = 0; + } + shiftDist = softfloat_countLeadingZeros64( sig64 ) - 15; + exp -= shiftDist; + if ( 0 <= shiftDist ) { + if ( shiftDist ) { + sig128 = softfloat_shortShiftLeft128( sig64, sig0, shiftDist ); + sig64 = sig128.v64; + sig0 = sig128.v0; + } + if ( (uint32_t) exp < 0x7FFD ) { + uZ.ui.v64 = packToF128UI64( sign, sig64 | sig0 ? exp : 0, sig64 ); + uZ.ui.v0 = sig0; + return uZ.f; + } + sigExtra = 0; + } else { + sig128Extra = + softfloat_shortShiftRightJam128Extra( sig64, sig0, 0, -shiftDist ); + sig64 = sig128Extra.v.v64; + sig0 = sig128Extra.v.v0; + sigExtra = sig128Extra.extra; + } + return softfloat_roundPackToF128( sign, exp, sig64, sig0, sigExtra ); + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_normRoundPackToF16.c b/vendor/riscv/riscv-isa-sim/softfloat/s_normRoundPackToF16.c new file mode 100644 index 0000000000..6788f2e14a --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_normRoundPackToF16.c @@ -0,0 +1,58 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" + +float16_t + softfloat_normRoundPackToF16( bool sign, int_fast16_t exp, uint_fast16_t sig ) +{ + int_fast8_t shiftDist; + union ui16_f16 uZ; + + shiftDist = softfloat_countLeadingZeros16( sig ) - 1; + exp -= shiftDist; + if ( (4 <= shiftDist) && ((unsigned int) exp < 0x1D) ) { + uZ.ui = packToF16UI( sign, sig ? exp : 0, sig<<(shiftDist - 4) ); + return uZ.f; + } else { + return softfloat_roundPackToF16( sign, exp, sig<<shiftDist ); + } + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_normRoundPackToF32.c b/vendor/riscv/riscv-isa-sim/softfloat/s_normRoundPackToF32.c new file mode 100644 index 0000000000..14e08116b9 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_normRoundPackToF32.c @@ -0,0 +1,58 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" + +float32_t + softfloat_normRoundPackToF32( bool sign, int_fast16_t exp, uint_fast32_t sig ) +{ + int_fast8_t shiftDist; + union ui32_f32 uZ; + + shiftDist = softfloat_countLeadingZeros32( sig ) - 1; + exp -= shiftDist; + if ( (7 <= shiftDist) && ((unsigned int) exp < 0xFD) ) { + uZ.ui = packToF32UI( sign, sig ? exp : 0, sig<<(shiftDist - 7) ); + return uZ.f; + } else { + return softfloat_roundPackToF32( sign, exp, sig<<shiftDist ); + } + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_normRoundPackToF64.c b/vendor/riscv/riscv-isa-sim/softfloat/s_normRoundPackToF64.c new file mode 100644 index 0000000000..7f5d6a22fc --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_normRoundPackToF64.c @@ -0,0 +1,58 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" + +float64_t + softfloat_normRoundPackToF64( bool sign, int_fast16_t exp, uint_fast64_t sig ) +{ + int_fast8_t shiftDist; + union ui64_f64 uZ; + + shiftDist = softfloat_countLeadingZeros64( sig ) - 1; + exp -= shiftDist; + if ( (10 <= shiftDist) && ((unsigned int) exp < 0x7FD) ) { + uZ.ui = packToF64UI( sign, sig ? exp : 0, sig<<(shiftDist - 10) ); + return uZ.f; + } else { + return softfloat_roundPackToF64( sign, exp, sig<<shiftDist ); + } + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_normSubnormalF128Sig.c b/vendor/riscv/riscv-isa-sim/softfloat/s_normSubnormalF128Sig.c new file mode 100644 index 0000000000..cf02e10228 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_normSubnormalF128Sig.c @@ -0,0 +1,65 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "platform.h" +#include "internals.h" + +struct exp32_sig128 + softfloat_normSubnormalF128Sig( uint_fast64_t sig64, uint_fast64_t sig0 ) +{ + int_fast8_t shiftDist; + struct exp32_sig128 z; + + if ( ! sig64 ) { + shiftDist = softfloat_countLeadingZeros64( sig0 ) - 15; + z.exp = -63 - shiftDist; + if ( shiftDist < 0 ) { + z.sig.v64 = sig0>>-shiftDist; + z.sig.v0 = sig0<<(shiftDist & 63); + } else { + z.sig.v64 = sig0<<shiftDist; + z.sig.v0 = 0; + } + } else { + shiftDist = softfloat_countLeadingZeros64( sig64 ) - 15; + z.exp = 1 - shiftDist; + z.sig = softfloat_shortShiftLeft128( sig64, sig0, shiftDist ); + } + return z; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_normSubnormalF16Sig.c b/vendor/riscv/riscv-isa-sim/softfloat/s_normSubnormalF16Sig.c new file mode 100644 index 0000000000..e612a9eb6d --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_normSubnormalF16Sig.c @@ -0,0 +1,52 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "platform.h" +#include "internals.h" + +struct exp8_sig16 softfloat_normSubnormalF16Sig( uint_fast16_t sig ) +{ + int_fast8_t shiftDist; + struct exp8_sig16 z; + + shiftDist = softfloat_countLeadingZeros16( sig ) - 5; + z.exp = 1 - shiftDist; + z.sig = sig<<shiftDist; + return z; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_normSubnormalF32Sig.c b/vendor/riscv/riscv-isa-sim/softfloat/s_normSubnormalF32Sig.c new file mode 100644 index 0000000000..e3e8ce44c8 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_normSubnormalF32Sig.c @@ -0,0 +1,52 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "platform.h" +#include "internals.h" + +struct exp16_sig32 softfloat_normSubnormalF32Sig( uint_fast32_t sig ) +{ + int_fast8_t shiftDist; + struct exp16_sig32 z; + + shiftDist = softfloat_countLeadingZeros32( sig ) - 8; + z.exp = 1 - shiftDist; + z.sig = sig<<shiftDist; + return z; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_normSubnormalF64Sig.c b/vendor/riscv/riscv-isa-sim/softfloat/s_normSubnormalF64Sig.c new file mode 100644 index 0000000000..fddfc32262 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_normSubnormalF64Sig.c @@ -0,0 +1,52 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "platform.h" +#include "internals.h" + +struct exp16_sig64 softfloat_normSubnormalF64Sig( uint_fast64_t sig ) +{ + int_fast8_t shiftDist; + struct exp16_sig64 z; + + shiftDist = softfloat_countLeadingZeros64( sig ) - 11; + z.exp = 1 - shiftDist; + z.sig = sig<<shiftDist; + return z; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_propagateNaNF128UI.c b/vendor/riscv/riscv-isa-sim/softfloat/s_propagateNaNF128UI.c new file mode 100644 index 0000000000..ad7e83b0fa --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_propagateNaNF128UI.c @@ -0,0 +1,73 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "platform.h" +#include "primitiveTypes.h" +#include "specialize.h" +#include "softfloat.h" + +/*---------------------------------------------------------------------------- +| Interpreting the unsigned integer formed from concatenating `uiA64' and +| `uiA0' as a 128-bit floating-point value, and likewise interpreting the +| unsigned integer formed from concatenating `uiB64' and `uiB0' as another +| 128-bit floating-point value, and assuming at least on of these floating- +| point values is a NaN, returns the bit pattern of the combined NaN result. +| If either original floating-point value is a signaling NaN, the invalid +| exception is raised. +*----------------------------------------------------------------------------*/ +struct uint128 + softfloat_propagateNaNF128UI( + uint_fast64_t uiA64, + uint_fast64_t uiA0, + uint_fast64_t uiB64, + uint_fast64_t uiB0 + ) +{ + struct uint128 uiZ; + + if ( + softfloat_isSigNaNF128UI( uiA64, uiA0 ) + || softfloat_isSigNaNF128UI( uiB64, uiB0 ) + ) { + softfloat_raiseFlags( softfloat_flag_invalid ); + } + uiZ.v64 = defaultNaNF128UI64; + uiZ.v0 = defaultNaNF128UI0; + return uiZ; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_propagateNaNF16UI.c b/vendor/riscv/riscv-isa-sim/softfloat/s_propagateNaNF16UI.c new file mode 100644 index 0000000000..3ecd4c9825 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_propagateNaNF16UI.c @@ -0,0 +1,58 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "platform.h" +#include "specialize.h" +#include "softfloat.h" + +/*---------------------------------------------------------------------------- +| Interpreting `uiA' and `uiB' as the bit patterns of two 16-bit floating- +| point values, at least one of which is a NaN, returns the bit pattern of +| the combined NaN result. If either `uiA' or `uiB' has the pattern of a +| signaling NaN, the invalid exception is raised. +*----------------------------------------------------------------------------*/ +uint_fast16_t + softfloat_propagateNaNF16UI( uint_fast16_t uiA, uint_fast16_t uiB ) +{ + + if ( softfloat_isSigNaNF16UI( uiA ) || softfloat_isSigNaNF16UI( uiB ) ) { + softfloat_raiseFlags( softfloat_flag_invalid ); + } + return defaultNaNF16UI; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_propagateNaNF32UI.c b/vendor/riscv/riscv-isa-sim/softfloat/s_propagateNaNF32UI.c new file mode 100644 index 0000000000..b97fa41458 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_propagateNaNF32UI.c @@ -0,0 +1,58 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "platform.h" +#include "specialize.h" +#include "softfloat.h" + +/*---------------------------------------------------------------------------- +| Interpreting `uiA' and `uiB' as the bit patterns of two 32-bit floating- +| point values, at least one of which is a NaN, returns the bit pattern of +| the combined NaN result. If either `uiA' or `uiB' has the pattern of a +| signaling NaN, the invalid exception is raised. +*----------------------------------------------------------------------------*/ +uint_fast32_t + softfloat_propagateNaNF32UI( uint_fast32_t uiA, uint_fast32_t uiB ) +{ + + if ( softfloat_isSigNaNF32UI( uiA ) || softfloat_isSigNaNF32UI( uiB ) ) { + softfloat_raiseFlags( softfloat_flag_invalid ); + } + return defaultNaNF32UI; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_propagateNaNF64UI.c b/vendor/riscv/riscv-isa-sim/softfloat/s_propagateNaNF64UI.c new file mode 100644 index 0000000000..9c2d359831 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_propagateNaNF64UI.c @@ -0,0 +1,58 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "platform.h" +#include "specialize.h" +#include "softfloat.h" + +/*---------------------------------------------------------------------------- +| Interpreting `uiA' and `uiB' as the bit patterns of two 64-bit floating- +| point values, at least one of which is a NaN, returns the bit pattern of +| the combined NaN result. If either `uiA' or `uiB' has the pattern of a +| signaling NaN, the invalid exception is raised. +*----------------------------------------------------------------------------*/ +uint_fast64_t + softfloat_propagateNaNF64UI( uint_fast64_t uiA, uint_fast64_t uiB ) +{ + + if ( softfloat_isSigNaNF64UI( uiA ) || softfloat_isSigNaNF64UI( uiB ) ) { + softfloat_raiseFlags( softfloat_flag_invalid ); + } + return defaultNaNF64UI; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_remStepMBy32.c b/vendor/riscv/riscv-isa-sim/softfloat/s_remStepMBy32.c new file mode 100644 index 0000000000..fe787a4305 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_remStepMBy32.c @@ -0,0 +1,86 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "platform.h" +#include "primitiveTypes.h" + +#ifndef softfloat_remStepMBy32 + +void + softfloat_remStepMBy32( + uint_fast8_t size_words, + const uint32_t *remPtr, + uint_fast8_t dist, + const uint32_t *bPtr, + uint32_t q, + uint32_t *zPtr + ) +{ + unsigned int index, lastIndex; + uint64_t dwordProd; + uint32_t wordRem, wordShiftedRem, wordProd; + uint_fast8_t uNegDist, borrow; + + index = indexWordLo( size_words ); + lastIndex = indexWordHi( size_words ); + dwordProd = (uint64_t) bPtr[index] * q; + wordRem = remPtr[index]; + wordShiftedRem = wordRem<<dist; + wordProd = dwordProd; + zPtr[index] = wordShiftedRem - wordProd; + if ( index != lastIndex ) { + uNegDist = -dist; + borrow = (wordShiftedRem < wordProd); + for (;;) { + wordShiftedRem = wordRem>>(uNegDist & 31); + index += wordIncr; + dwordProd = (uint64_t) bPtr[index] * q + (dwordProd>>32); + wordRem = remPtr[index]; + wordShiftedRem |= wordRem<<dist; + wordProd = dwordProd; + zPtr[index] = wordShiftedRem - wordProd - borrow; + if ( index == lastIndex ) break; + borrow = + borrow ? (wordShiftedRem <= wordProd) + : (wordShiftedRem < wordProd); + } + } + +} + +#endif + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_roundMToI64.c b/vendor/riscv/riscv-isa-sim/softfloat/s_roundMToI64.c new file mode 100644 index 0000000000..a73f7f8032 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_roundMToI64.c @@ -0,0 +1,88 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the +University of California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +int_fast64_t + softfloat_roundMToI64( + bool sign, uint32_t *extSigPtr, uint_fast8_t roundingMode, bool exact ) +{ + bool roundNearEven; + uint32_t sigExtra; + bool doIncrement; + uint64_t sig; + union { uint64_t ui; int64_t i; } uZ; + int64_t z; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + roundNearEven = (roundingMode == softfloat_round_near_even); + sigExtra = extSigPtr[indexWordLo( 3 )]; + doIncrement = (0x80000000 <= sigExtra); + if ( ! roundNearEven && (roundingMode != softfloat_round_near_maxMag) ) { + doIncrement = + (roundingMode + == (sign ? softfloat_round_min : softfloat_round_max)) + && sigExtra; + } + sig = + (uint64_t) extSigPtr[indexWord( 3, 2 )]<<32 + | extSigPtr[indexWord( 3, 1 )]; + if ( doIncrement ) { + ++sig; + if ( ! sig ) goto invalid; + if ( ! (sigExtra & 0x7FFFFFFF) && roundNearEven ) sig &= ~1; + } + uZ.ui = sign ? -sig : sig; + z = uZ.i; + if ( z && ((z < 0) ^ sign) ) goto invalid; + if ( exact && sigExtra ) { + softfloat_exceptionFlags |= softfloat_flag_inexact; + } + return z; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + invalid: + softfloat_raiseFlags( softfloat_flag_invalid ); + return sign ? i64_fromNegOverflow : i64_fromPosOverflow; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_roundMToUI64.c b/vendor/riscv/riscv-isa-sim/softfloat/s_roundMToUI64.c new file mode 100644 index 0000000000..0377c5bb6b --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_roundMToUI64.c @@ -0,0 +1,84 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the +University of California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +uint_fast64_t + softfloat_roundMToUI64( + bool sign, uint32_t *extSigPtr, uint_fast8_t roundingMode, bool exact ) +{ + bool roundNearEven; + uint32_t sigExtra; + bool doIncrement; + uint64_t sig; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + roundNearEven = (roundingMode == softfloat_round_near_even); + sigExtra = extSigPtr[indexWordLo( 3 )]; + doIncrement = (0x80000000 <= sigExtra); + if ( ! roundNearEven && (roundingMode != softfloat_round_near_maxMag) ) { + doIncrement = + (roundingMode + == (sign ? softfloat_round_min : softfloat_round_max)) + && sigExtra; + } + sig = + (uint64_t) extSigPtr[indexWord( 3, 2 )]<<32 + | extSigPtr[indexWord( 3, 1 )]; + if ( doIncrement ) { + ++sig; + if ( ! sig ) goto invalid; + if ( ! (sigExtra & 0x7FFFFFFF) && roundNearEven ) sig &= ~1; + } + if ( sign && sig ) goto invalid; + if ( exact && sigExtra ) { + softfloat_exceptionFlags |= softfloat_flag_inexact; + } + return sig; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + invalid: + softfloat_raiseFlags( softfloat_flag_invalid ); + return sign ? ui64_fromNegOverflow : ui64_fromPosOverflow; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_roundPackMToI64.c b/vendor/riscv/riscv-isa-sim/softfloat/s_roundPackMToI64.c new file mode 100644 index 0000000000..4d5efbb725 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_roundPackMToI64.c @@ -0,0 +1,88 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3a+, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +int_fast64_t + softfloat_roundPackMToI64( + bool sign, uint32_t *extSigPtr, uint_fast8_t roundingMode, bool exact ) +{ + bool roundNearEven; + uint32_t sigExtra; + bool doIncrement; + uint64_t sig; + union { uint64_t ui; int64_t i; } uZ; + int64_t z; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + roundNearEven = (roundingMode == softfloat_round_near_even); + sigExtra = extSigPtr[indexWordLo( 3 )]; + doIncrement = (0x80000000 <= sigExtra); + if ( ! roundNearEven && (roundingMode != softfloat_round_near_maxMag) ) { + doIncrement = + (roundingMode + == (sign ? softfloat_round_min : softfloat_round_max)) + && sigExtra; + } + sig = + (uint64_t) extSigPtr[indexWord( 3, 2 )]<<32 + | extSigPtr[indexWord( 3, 1 )]; + if ( doIncrement ) { + ++sig; + if ( ! sig ) goto invalid; + if ( ! (sigExtra & 0x7FFFFFFF) && roundNearEven ) sig &= ~1; + } + uZ.ui = sign ? -sig : sig; + z = uZ.i; + if ( z && ((z < 0) ^ sign) ) goto invalid; + if ( exact && sigExtra ) { + softfloat_exceptionFlags |= softfloat_flag_inexact; + } + return z; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + invalid: + softfloat_raiseFlags( softfloat_flag_invalid ); + return sign ? i64_fromNegOverflow : i64_fromPosOverflow; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_roundPackMToUI64.c b/vendor/riscv/riscv-isa-sim/softfloat/s_roundPackMToUI64.c new file mode 100644 index 0000000000..1a64fdf98d --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_roundPackMToUI64.c @@ -0,0 +1,84 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3a+, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +uint_fast64_t + softfloat_roundPackMToUI64( + bool sign, uint32_t *extSigPtr, uint_fast8_t roundingMode, bool exact ) +{ + bool roundNearEven; + uint32_t sigExtra; + bool doIncrement; + uint64_t sig; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + roundNearEven = (roundingMode == softfloat_round_near_even); + sigExtra = extSigPtr[indexWordLo( 3 )]; + doIncrement = (0x80000000 <= sigExtra); + if ( ! roundNearEven && (roundingMode != softfloat_round_near_maxMag) ) { + doIncrement = + (roundingMode + == (sign ? softfloat_round_min : softfloat_round_max)) + && sigExtra; + } + sig = + (uint64_t) extSigPtr[indexWord( 3, 2 )]<<32 + | extSigPtr[indexWord( 3, 1 )]; + if ( doIncrement ) { + ++sig; + if ( ! sig ) goto invalid; + if ( ! (sigExtra & 0x7FFFFFFF) && roundNearEven ) sig &= ~1; + } + if ( sign && sig ) goto invalid; + if ( exact && sigExtra ) { + softfloat_exceptionFlags |= softfloat_flag_inexact; + } + return sig; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + invalid: + softfloat_raiseFlags( softfloat_flag_invalid ); + return sign ? ui64_fromNegOverflow : ui64_fromPosOverflow; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_roundPackToF128.c b/vendor/riscv/riscv-isa-sim/softfloat/s_roundPackToF128.c new file mode 100644 index 0000000000..eaaa375c9b --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_roundPackToF128.c @@ -0,0 +1,171 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "softfloat.h" + +float128_t + softfloat_roundPackToF128( + bool sign, + int_fast32_t exp, + uint_fast64_t sig64, + uint_fast64_t sig0, + uint_fast64_t sigExtra + ) +{ + uint_fast8_t roundingMode; + bool roundNearEven, doIncrement, isTiny; + struct uint128_extra sig128Extra; + uint_fast64_t uiZ64, uiZ0; + struct uint128 sig128; + union ui128_f128 uZ; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + roundingMode = softfloat_roundingMode; + roundNearEven = (roundingMode == softfloat_round_near_even); + doIncrement = (UINT64_C( 0x8000000000000000 ) <= sigExtra); + if ( ! roundNearEven && (roundingMode != softfloat_round_near_maxMag) ) { + doIncrement = + (roundingMode + == (sign ? softfloat_round_min : softfloat_round_max)) + && sigExtra; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( 0x7FFD <= (uint32_t) exp ) { + if ( exp < 0 ) { + /*---------------------------------------------------------------- + *----------------------------------------------------------------*/ + isTiny = + (softfloat_detectTininess + == softfloat_tininess_beforeRounding) + || (exp < -1) + || ! doIncrement + || softfloat_lt128( + sig64, + sig0, + UINT64_C( 0x0001FFFFFFFFFFFF ), + UINT64_C( 0xFFFFFFFFFFFFFFFF ) + ); + sig128Extra = + softfloat_shiftRightJam128Extra( sig64, sig0, sigExtra, -exp ); + sig64 = sig128Extra.v.v64; + sig0 = sig128Extra.v.v0; + sigExtra = sig128Extra.extra; + exp = 0; + if ( isTiny && sigExtra ) { + softfloat_raiseFlags( softfloat_flag_underflow ); + } + doIncrement = (UINT64_C( 0x8000000000000000 ) <= sigExtra); + if ( + ! roundNearEven + && (roundingMode != softfloat_round_near_maxMag) + ) { + doIncrement = + (roundingMode + == (sign ? softfloat_round_min : softfloat_round_max)) + && sigExtra; + } + } else if ( + (0x7FFD < exp) + || ((exp == 0x7FFD) + && softfloat_eq128( + sig64, + sig0, + UINT64_C( 0x0001FFFFFFFFFFFF ), + UINT64_C( 0xFFFFFFFFFFFFFFFF ) + ) + && doIncrement) + ) { + /*---------------------------------------------------------------- + *----------------------------------------------------------------*/ + softfloat_raiseFlags( + softfloat_flag_overflow | softfloat_flag_inexact ); + if ( + roundNearEven + || (roundingMode == softfloat_round_near_maxMag) + || (roundingMode + == (sign ? softfloat_round_min : softfloat_round_max)) + ) { + uiZ64 = packToF128UI64( sign, 0x7FFF, 0 ); + uiZ0 = 0; + } else { + uiZ64 = + packToF128UI64( + sign, 0x7FFE, UINT64_C( 0x0000FFFFFFFFFFFF ) ); + uiZ0 = UINT64_C( 0xFFFFFFFFFFFFFFFF ); + } + goto uiZ; + } + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( sigExtra ) { + softfloat_exceptionFlags |= softfloat_flag_inexact; +#ifdef SOFTFLOAT_ROUND_ODD + if ( roundingMode == softfloat_round_odd ) { + sig0 |= 1; + goto packReturn; + } +#endif + } + if ( doIncrement ) { + sig128 = softfloat_add128( sig64, sig0, 0, 1 ); + sig64 = sig128.v64; + sig0 = + sig128.v0 + & ~(uint64_t) + (! (sigExtra & UINT64_C( 0x7FFFFFFFFFFFFFFF )) + & roundNearEven); + } else { + if ( ! (sig64 | sig0) ) exp = 0; + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + packReturn: + uiZ64 = packToF128UI64( sign, exp, sig64 ); + uiZ0 = sig0; + uiZ: + uZ.ui.v64 = uiZ64; + uZ.ui.v0 = uiZ0; + return uZ.f; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_roundPackToF16.c b/vendor/riscv/riscv-isa-sim/softfloat/s_roundPackToF16.c new file mode 100644 index 0000000000..0eaa73a5f0 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_roundPackToF16.c @@ -0,0 +1,113 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "softfloat.h" + +float16_t + softfloat_roundPackToF16( bool sign, int_fast16_t exp, uint_fast16_t sig ) +{ + uint_fast8_t roundingMode; + bool roundNearEven; + uint_fast8_t roundIncrement, roundBits; + bool isTiny; + uint_fast16_t uiZ; + union ui16_f16 uZ; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + roundingMode = softfloat_roundingMode; + roundNearEven = (roundingMode == softfloat_round_near_even); + roundIncrement = 0x8; + if ( ! roundNearEven && (roundingMode != softfloat_round_near_maxMag) ) { + roundIncrement = + (roundingMode + == (sign ? softfloat_round_min : softfloat_round_max)) + ? 0xF + : 0; + } + roundBits = sig & 0xF; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( 0x1D <= (unsigned int) exp ) { + if ( exp < 0 ) { + /*---------------------------------------------------------------- + *----------------------------------------------------------------*/ + isTiny = + (softfloat_detectTininess == softfloat_tininess_beforeRounding) + || (exp < -1) || (sig + roundIncrement < 0x8000); + sig = softfloat_shiftRightJam32( sig, -exp ); + exp = 0; + roundBits = sig & 0xF; + if ( isTiny && roundBits ) { + softfloat_raiseFlags( softfloat_flag_underflow ); + } + } else if ( (0x1D < exp) || (0x8000 <= sig + roundIncrement) ) { + /*---------------------------------------------------------------- + *----------------------------------------------------------------*/ + softfloat_raiseFlags( + softfloat_flag_overflow | softfloat_flag_inexact ); + uiZ = packToF16UI( sign, 0x1F, 0 ) - ! roundIncrement; + goto uiZ; + } + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + sig = (sig + roundIncrement)>>4; + if ( roundBits ) { + softfloat_exceptionFlags |= softfloat_flag_inexact; +#ifdef SOFTFLOAT_ROUND_ODD + if ( roundingMode == softfloat_round_odd ) { + sig |= 1; + goto packReturn; + } +#endif + } + sig &= ~(uint_fast16_t) (! (roundBits ^ 8) & roundNearEven); + if ( ! sig ) exp = 0; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + packReturn: + uiZ = packToF16UI( sign, exp, sig ); + uiZ: + uZ.ui = uiZ; + return uZ.f; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_roundPackToF32.c b/vendor/riscv/riscv-isa-sim/softfloat/s_roundPackToF32.c new file mode 100644 index 0000000000..cc34508570 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_roundPackToF32.c @@ -0,0 +1,113 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "softfloat.h" + +float32_t + softfloat_roundPackToF32( bool sign, int_fast16_t exp, uint_fast32_t sig ) +{ + uint_fast8_t roundingMode; + bool roundNearEven; + uint_fast8_t roundIncrement, roundBits; + bool isTiny; + uint_fast32_t uiZ; + union ui32_f32 uZ; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + roundingMode = softfloat_roundingMode; + roundNearEven = (roundingMode == softfloat_round_near_even); + roundIncrement = 0x40; + if ( ! roundNearEven && (roundingMode != softfloat_round_near_maxMag) ) { + roundIncrement = + (roundingMode + == (sign ? softfloat_round_min : softfloat_round_max)) + ? 0x7F + : 0; + } + roundBits = sig & 0x7F; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( 0xFD <= (unsigned int) exp ) { + if ( exp < 0 ) { + /*---------------------------------------------------------------- + *----------------------------------------------------------------*/ + isTiny = + (softfloat_detectTininess == softfloat_tininess_beforeRounding) + || (exp < -1) || (sig + roundIncrement < 0x80000000); + sig = softfloat_shiftRightJam32( sig, -exp ); + exp = 0; + roundBits = sig & 0x7F; + if ( isTiny && roundBits ) { + softfloat_raiseFlags( softfloat_flag_underflow ); + } + } else if ( (0xFD < exp) || (0x80000000 <= sig + roundIncrement) ) { + /*---------------------------------------------------------------- + *----------------------------------------------------------------*/ + softfloat_raiseFlags( + softfloat_flag_overflow | softfloat_flag_inexact ); + uiZ = packToF32UI( sign, 0xFF, 0 ) - ! roundIncrement; + goto uiZ; + } + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + sig = (sig + roundIncrement)>>7; + if ( roundBits ) { + softfloat_exceptionFlags |= softfloat_flag_inexact; +#ifdef SOFTFLOAT_ROUND_ODD + if ( roundingMode == softfloat_round_odd ) { + sig |= 1; + goto packReturn; + } +#endif + } + sig &= ~(uint_fast32_t) (! (roundBits ^ 0x40) & roundNearEven); + if ( ! sig ) exp = 0; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + packReturn: + uiZ = packToF32UI( sign, exp, sig ); + uiZ: + uZ.ui = uiZ; + return uZ.f; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_roundPackToF64.c b/vendor/riscv/riscv-isa-sim/softfloat/s_roundPackToF64.c new file mode 100644 index 0000000000..aaff008c1d --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_roundPackToF64.c @@ -0,0 +1,117 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "softfloat.h" + +float64_t + softfloat_roundPackToF64( bool sign, int_fast16_t exp, uint_fast64_t sig ) +{ + uint_fast8_t roundingMode; + bool roundNearEven; + uint_fast16_t roundIncrement, roundBits; + bool isTiny; + uint_fast64_t uiZ; + union ui64_f64 uZ; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + roundingMode = softfloat_roundingMode; + roundNearEven = (roundingMode == softfloat_round_near_even); + roundIncrement = 0x200; + if ( ! roundNearEven && (roundingMode != softfloat_round_near_maxMag) ) { + roundIncrement = + (roundingMode + == (sign ? softfloat_round_min : softfloat_round_max)) + ? 0x3FF + : 0; + } + roundBits = sig & 0x3FF; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + if ( 0x7FD <= (uint16_t) exp ) { + if ( exp < 0 ) { + /*---------------------------------------------------------------- + *----------------------------------------------------------------*/ + isTiny = + (softfloat_detectTininess == softfloat_tininess_beforeRounding) + || (exp < -1) + || (sig + roundIncrement < UINT64_C( 0x8000000000000000 )); + sig = softfloat_shiftRightJam64( sig, -exp ); + exp = 0; + roundBits = sig & 0x3FF; + if ( isTiny && roundBits ) { + softfloat_raiseFlags( softfloat_flag_underflow ); + } + } else if ( + (0x7FD < exp) + || (UINT64_C( 0x8000000000000000 ) <= sig + roundIncrement) + ) { + /*---------------------------------------------------------------- + *----------------------------------------------------------------*/ + softfloat_raiseFlags( + softfloat_flag_overflow | softfloat_flag_inexact ); + uiZ = packToF64UI( sign, 0x7FF, 0 ) - ! roundIncrement; + goto uiZ; + } + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + sig = (sig + roundIncrement)>>10; + if ( roundBits ) { + softfloat_exceptionFlags |= softfloat_flag_inexact; +#ifdef SOFTFLOAT_ROUND_ODD + if ( roundingMode == softfloat_round_odd ) { + sig |= 1; + goto packReturn; + } +#endif + } + sig &= ~(uint_fast64_t) (! (roundBits ^ 0x200) & roundNearEven); + if ( ! sig ) exp = 0; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + packReturn: + uiZ = packToF64UI( sign, exp, sig ); + uiZ: + uZ.ui = uiZ; + return uZ.f; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_roundPackToI32.c b/vendor/riscv/riscv-isa-sim/softfloat/s_roundPackToI32.c new file mode 100644 index 0000000000..3ece8f052e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_roundPackToI32.c @@ -0,0 +1,84 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3a+, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +int_fast32_t + softfloat_roundPackToI32( + bool sign, uint_fast64_t sig, uint_fast8_t roundingMode, bool exact ) +{ + bool roundNearEven; + uint_fast8_t roundIncrement, roundBits; + uint_fast32_t sig32; + union { uint32_t ui; int32_t i; } uZ; + int_fast32_t z; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + roundNearEven = (roundingMode == softfloat_round_near_even); + roundIncrement = 0x40; + if ( ! roundNearEven && (roundingMode != softfloat_round_near_maxMag) ) { + roundIncrement = + (roundingMode + == (sign ? softfloat_round_min : softfloat_round_max)) + ? 0x7F + : 0; + } + roundBits = sig & 0x7F; + sig += roundIncrement; + if ( sig & UINT64_C( 0xFFFFFF8000000000 ) ) goto invalid; + sig32 = sig>>7; + sig32 &= ~(uint_fast32_t) (! (roundBits ^ 0x40) & roundNearEven); + uZ.ui = sign ? -sig32 : sig32; + z = uZ.i; + if ( z && ((z < 0) ^ sign) ) goto invalid; + if ( exact && roundBits ) { + softfloat_exceptionFlags |= softfloat_flag_inexact; + } + return z; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + invalid: + softfloat_raiseFlags( softfloat_flag_invalid ); + return sign ? i32_fromNegOverflow : i32_fromPosOverflow; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_roundPackToI64.c b/vendor/riscv/riscv-isa-sim/softfloat/s_roundPackToI64.c new file mode 100644 index 0000000000..ebef7f3647 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_roundPackToI64.c @@ -0,0 +1,89 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3a+, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +int_fast64_t + softfloat_roundPackToI64( + bool sign, + uint_fast64_t sig, + uint_fast64_t sigExtra, + uint_fast8_t roundingMode, + bool exact + ) +{ + bool roundNearEven, doIncrement; + union { uint64_t ui; int64_t i; } uZ; + int_fast64_t z; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + roundNearEven = (roundingMode == softfloat_round_near_even); + doIncrement = (UINT64_C( 0x8000000000000000 ) <= sigExtra); + if ( ! roundNearEven && (roundingMode != softfloat_round_near_maxMag) ) { + doIncrement = + (roundingMode + == (sign ? softfloat_round_min : softfloat_round_max)) + && sigExtra; + } + if ( doIncrement ) { + ++sig; + if ( ! sig ) goto invalid; + sig &= + ~(uint_fast64_t) + (! (sigExtra & UINT64_C( 0x7FFFFFFFFFFFFFFF )) + & roundNearEven); + } + uZ.ui = sign ? -sig : sig; + z = uZ.i; + if ( z && ((z < 0) ^ sign) ) goto invalid; + if ( exact && sigExtra ) { + softfloat_exceptionFlags |= softfloat_flag_inexact; + } + return z; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + invalid: + softfloat_raiseFlags( softfloat_flag_invalid ); + return sign ? i64_fromNegOverflow : i64_fromPosOverflow; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_roundPackToUI32.c b/vendor/riscv/riscv-isa-sim/softfloat/s_roundPackToUI32.c new file mode 100644 index 0000000000..f0021fe54c --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_roundPackToUI32.c @@ -0,0 +1,80 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3a+, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +uint_fast32_t + softfloat_roundPackToUI32( + bool sign, uint_fast64_t sig, uint_fast8_t roundingMode, bool exact ) +{ + bool roundNearEven; + uint_fast8_t roundIncrement, roundBits; + uint_fast32_t z; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + roundNearEven = (roundingMode == softfloat_round_near_even); + roundIncrement = 0x40; + if ( ! roundNearEven && (roundingMode != softfloat_round_near_maxMag) ) { + roundIncrement = + (roundingMode + == (sign ? softfloat_round_min : softfloat_round_max)) + ? 0x7F + : 0; + } + roundBits = sig & 0x7F; + sig += roundIncrement; + if ( sig & UINT64_C( 0xFFFFFF8000000000 ) ) goto invalid; + z = sig>>7; + z &= ~(uint_fast32_t) (! (roundBits ^ 0x40) & roundNearEven); + if ( sign && z ) goto invalid; + if ( exact && roundBits ) { + softfloat_exceptionFlags |= softfloat_flag_inexact; + } + return z; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + invalid: + softfloat_raiseFlags( softfloat_flag_invalid ); + return sign ? ui32_fromNegOverflow : ui32_fromPosOverflow; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_roundPackToUI64.c b/vendor/riscv/riscv-isa-sim/softfloat/s_roundPackToUI64.c new file mode 100644 index 0000000000..fada1840c6 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_roundPackToUI64.c @@ -0,0 +1,85 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3a+, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +uint_fast64_t + softfloat_roundPackToUI64( + bool sign, + uint_fast64_t sig, + uint_fast64_t sigExtra, + uint_fast8_t roundingMode, + bool exact + ) +{ + bool roundNearEven, doIncrement; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + roundNearEven = (roundingMode == softfloat_round_near_even); + doIncrement = (UINT64_C( 0x8000000000000000 ) <= sigExtra); + if ( ! roundNearEven && (roundingMode != softfloat_round_near_maxMag) ) { + doIncrement = + (roundingMode + == (sign ? softfloat_round_min : softfloat_round_max)) + && sigExtra; + } + if ( doIncrement ) { + ++sig; + if ( ! sig ) goto invalid; + sig &= + ~(uint_fast64_t) + (! (sigExtra & UINT64_C( 0x7FFFFFFFFFFFFFFF )) + & roundNearEven); + } + if ( sign && sig ) goto invalid; + if ( exact && sigExtra ) { + softfloat_exceptionFlags |= softfloat_flag_inexact; + } + return sig; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + invalid: + softfloat_raiseFlags( softfloat_flag_invalid ); + return sign ? ui64_fromNegOverflow : ui64_fromPosOverflow; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_roundToI32.c b/vendor/riscv/riscv-isa-sim/softfloat/s_roundToI32.c new file mode 100644 index 0000000000..20a3ff4f65 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_roundToI32.c @@ -0,0 +1,84 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the +University of California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +int_fast32_t + softfloat_roundToI32( + bool sign, uint_fast64_t sig, uint_fast8_t roundingMode, bool exact ) +{ + bool roundNearEven; + uint_fast16_t roundIncrement, roundBits; + uint_fast32_t sig32; + union { uint32_t ui; int32_t i; } uZ; + int_fast32_t z; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + roundNearEven = (roundingMode == softfloat_round_near_even); + roundIncrement = 0x800; + if ( ! roundNearEven && (roundingMode != softfloat_round_near_maxMag) ) { + roundIncrement = + (roundingMode + == (sign ? softfloat_round_min : softfloat_round_max)) + ? 0xFFF + : 0; + } + roundBits = sig & 0xFFF; + sig += roundIncrement; + if ( sig & UINT64_C( 0xFFFFF00000000000 ) ) goto invalid; + sig32 = sig>>12; + sig32 &= ~(uint_fast32_t) (! (roundBits ^ 0x800) & roundNearEven); + uZ.ui = sign ? -sig32 : sig32; + z = uZ.i; + if ( z && ((z < 0) ^ sign) ) goto invalid; + if ( exact && roundBits ) { + softfloat_exceptionFlags |= softfloat_flag_inexact; + } + return z; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + invalid: + softfloat_raiseFlags( softfloat_flag_invalid ); + return sign ? i32_fromNegOverflow : i32_fromPosOverflow; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_roundToI64.c b/vendor/riscv/riscv-isa-sim/softfloat/s_roundToI64.c new file mode 100644 index 0000000000..fcddbc2785 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_roundToI64.c @@ -0,0 +1,89 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the +University of California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +int_fast64_t + softfloat_roundToI64( + bool sign, + uint_fast64_t sig, + uint_fast64_t sigExtra, + uint_fast8_t roundingMode, + bool exact + ) +{ + bool roundNearEven, doIncrement; + union { uint64_t ui; int64_t i; } uZ; + int_fast64_t z; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + roundNearEven = (roundingMode == softfloat_round_near_even); + doIncrement = (UINT64_C( 0x8000000000000000 ) <= sigExtra); + if ( ! roundNearEven && (roundingMode != softfloat_round_near_maxMag) ) { + doIncrement = + (roundingMode + == (sign ? softfloat_round_min : softfloat_round_max)) + && sigExtra; + } + if ( doIncrement ) { + ++sig; + if ( ! sig ) goto invalid; + sig &= + ~(uint_fast64_t) + (! (sigExtra & UINT64_C( 0x7FFFFFFFFFFFFFFF )) + & roundNearEven); + } + uZ.ui = sign ? -sig : sig; + z = uZ.i; + if ( z && ((z < 0) ^ sign) ) goto invalid; + if ( exact && sigExtra ) { + softfloat_exceptionFlags |= softfloat_flag_inexact; + } + return z; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + invalid: + softfloat_raiseFlags( softfloat_flag_invalid ); + return sign ? i64_fromNegOverflow : i64_fromPosOverflow; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_roundToUI32.c b/vendor/riscv/riscv-isa-sim/softfloat/s_roundToUI32.c new file mode 100644 index 0000000000..180899bd85 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_roundToUI32.c @@ -0,0 +1,80 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the +University of California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +uint_fast32_t + softfloat_roundToUI32( + bool sign, uint_fast64_t sig, uint_fast8_t roundingMode, bool exact ) +{ + bool roundNearEven; + uint_fast16_t roundIncrement, roundBits; + uint_fast32_t z; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + roundNearEven = (roundingMode == softfloat_round_near_even); + roundIncrement = 0x800; + if ( ! roundNearEven && (roundingMode != softfloat_round_near_maxMag) ) { + roundIncrement = + (roundingMode + == (sign ? softfloat_round_min : softfloat_round_max)) + ? 0xFFF + : 0; + } + roundBits = sig & 0xFFF; + sig += roundIncrement; + if ( sig & UINT64_C( 0xFFFFF00000000000 ) ) goto invalid; + z = sig>>12; + z &= ~(uint_fast32_t) (! (roundBits ^ 0x800) & roundNearEven); + if ( sign && z ) goto invalid; + if ( exact && roundBits ) { + softfloat_exceptionFlags |= softfloat_flag_inexact; + } + return z; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + invalid: + softfloat_raiseFlags( softfloat_flag_invalid ); + return sign ? ui32_fromNegOverflow : ui32_fromPosOverflow; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_roundToUI64.c b/vendor/riscv/riscv-isa-sim/softfloat/s_roundToUI64.c new file mode 100644 index 0000000000..de35b5eb0e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_roundToUI64.c @@ -0,0 +1,85 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the +University of California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +uint_fast64_t + softfloat_roundToUI64( + bool sign, + uint_fast64_t sig, + uint_fast64_t sigExtra, + uint_fast8_t roundingMode, + bool exact + ) +{ + bool roundNearEven, doIncrement; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + roundNearEven = (roundingMode == softfloat_round_near_even); + doIncrement = (UINT64_C( 0x8000000000000000 ) <= sigExtra); + if ( ! roundNearEven && (roundingMode != softfloat_round_near_maxMag) ) { + doIncrement = + (roundingMode + == (sign ? softfloat_round_min : softfloat_round_max)) + && sigExtra; + } + if ( doIncrement ) { + ++sig; + if ( ! sig ) goto invalid; + sig &= + ~(uint_fast64_t) + (! (sigExtra & UINT64_C( 0x7FFFFFFFFFFFFFFF )) + & roundNearEven); + } + if ( sign && sig ) goto invalid; + if ( exact && sigExtra ) { + softfloat_exceptionFlags |= softfloat_flag_inexact; + } + return sig; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + invalid: + softfloat_raiseFlags( softfloat_flag_invalid ); + return sign ? ui64_fromNegOverflow : ui64_fromPosOverflow; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_shiftRightJam128.c b/vendor/riscv/riscv-isa-sim/softfloat/s_shiftRightJam128.c new file mode 100644 index 0000000000..8d2b91e87d --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_shiftRightJam128.c @@ -0,0 +1,69 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "platform.h" +#include "primitiveTypes.h" + +#ifndef softfloat_shiftRightJam128 + +struct uint128 + softfloat_shiftRightJam128( uint64_t a64, uint64_t a0, uint_fast32_t dist ) +{ + uint_fast8_t u8NegDist; + struct uint128 z; + + if ( dist < 64 ) { + u8NegDist = -dist; + z.v64 = a64>>dist; + z.v0 = + a64<<(u8NegDist & 63) | a0>>dist + | ((uint64_t) (a0<<(u8NegDist & 63)) != 0); + } else { + z.v64 = 0; + z.v0 = + (dist < 127) + ? a64>>(dist & 63) + | (((a64 & (((uint_fast64_t) 1<<(dist & 63)) - 1)) | a0) + != 0) + : ((a64 | a0) != 0); + } + return z; + +} + +#endif + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_shiftRightJam128Extra.c b/vendor/riscv/riscv-isa-sim/softfloat/s_shiftRightJam128Extra.c new file mode 100644 index 0000000000..4e1293c74a --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_shiftRightJam128Extra.c @@ -0,0 +1,77 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "platform.h" +#include "primitiveTypes.h" + +#ifndef softfloat_shiftRightJam128Extra + +struct uint128_extra + softfloat_shiftRightJam128Extra( + uint64_t a64, uint64_t a0, uint64_t extra, uint_fast32_t dist ) +{ + uint_fast8_t u8NegDist; + struct uint128_extra z; + + u8NegDist = -dist; + if ( dist < 64 ) { + z.v.v64 = a64>>dist; + z.v.v0 = a64<<(u8NegDist & 63) | a0>>dist; + z.extra = a0<<(u8NegDist & 63); + } else { + z.v.v64 = 0; + if ( dist == 64 ) { + z.v.v0 = a64; + z.extra = a0; + } else { + extra |= a0; + if ( dist < 128 ) { + z.v.v0 = a64>>(dist & 63); + z.extra = a64<<(u8NegDist & 63); + } else { + z.v.v0 = 0; + z.extra = (dist == 128) ? a64 : (a64 != 0); + } + } + } + z.extra |= (extra != 0); + return z; + +} + +#endif + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_shiftRightJam256M.c b/vendor/riscv/riscv-isa-sim/softfloat/s_shiftRightJam256M.c new file mode 100644 index 0000000000..04cd1e5084 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_shiftRightJam256M.c @@ -0,0 +1,126 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "platform.h" +#include "primitiveTypes.h" + +#ifndef softfloat_shiftRightJam256M + +static + void + softfloat_shortShiftRightJamM( + uint_fast8_t size_words, + const uint64_t *aPtr, + uint_fast8_t dist, + uint64_t *zPtr + ) +{ + uint_fast8_t uNegDist; + unsigned int index, lastIndex; + uint64_t partWordZ, wordA; + + uNegDist = -dist; + index = indexWordLo( size_words ); + lastIndex = indexWordHi( size_words ); + wordA = aPtr[index]; + partWordZ = wordA>>dist; + if ( partWordZ<<dist != wordA ) partWordZ |= 1; + while ( index != lastIndex ) { + wordA = aPtr[index + wordIncr]; + zPtr[index] = wordA<<(uNegDist & 63) | partWordZ; + index += wordIncr; + partWordZ = wordA>>dist; + } + zPtr[index] = partWordZ; + +} + +void + softfloat_shiftRightJam256M( + const uint64_t *aPtr, uint_fast32_t dist, uint64_t *zPtr ) +{ + uint64_t wordJam; + uint_fast32_t wordDist; + uint64_t *ptr; + uint_fast8_t i, innerDist; + + wordJam = 0; + wordDist = dist>>6; + if ( wordDist ) { + if ( 4 < wordDist ) wordDist = 4; + ptr = (uint64_t *) (aPtr + indexMultiwordLo( 4, wordDist )); + i = wordDist; + do { + wordJam = *ptr++; + if ( wordJam ) break; + --i; + } while ( i ); + ptr = zPtr; + } + if ( wordDist < 4 ) { + aPtr += indexMultiwordHiBut( 4, wordDist ); + innerDist = dist & 63; + if ( innerDist ) { + softfloat_shortShiftRightJamM( + 4 - wordDist, + aPtr, + innerDist, + zPtr + indexMultiwordLoBut( 4, wordDist ) + ); + if ( ! wordDist ) goto wordJam; + } else { + aPtr += indexWordLo( 4 - wordDist ); + ptr = zPtr + indexWordLo( 4 ); + for ( i = 4 - wordDist; i; --i ) { + *ptr = *aPtr; + aPtr += wordIncr; + ptr += wordIncr; + } + } + ptr = zPtr + indexMultiwordHi( 4, wordDist ); + } + do { + *ptr++ = 0; + --wordDist; + } while ( wordDist ); + wordJam: + if ( wordJam ) zPtr[indexWordLo( 4 )] |= 1; + +} + +#endif + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_shiftRightJam32.c b/vendor/riscv/riscv-isa-sim/softfloat/s_shiftRightJam32.c new file mode 100644 index 0000000000..fbc3aa0110 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_shiftRightJam32.c @@ -0,0 +1,51 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "platform.h" + +#ifndef softfloat_shiftRightJam32 + +uint32_t softfloat_shiftRightJam32( uint32_t a, uint_fast16_t dist ) +{ + + return + (dist < 31) ? a>>dist | ((uint32_t) (a<<(-dist & 31)) != 0) : (a != 0); + +} + +#endif + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_shiftRightJam64.c b/vendor/riscv/riscv-isa-sim/softfloat/s_shiftRightJam64.c new file mode 100644 index 0000000000..34edd7bf8f --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_shiftRightJam64.c @@ -0,0 +1,51 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "platform.h" + +#ifndef softfloat_shiftRightJam64 + +uint64_t softfloat_shiftRightJam64( uint64_t a, uint_fast32_t dist ) +{ + + return + (dist < 63) ? a>>dist | ((uint64_t) (a<<(-dist & 63)) != 0) : (a != 0); + +} + +#endif + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_shiftRightJam64Extra.c b/vendor/riscv/riscv-isa-sim/softfloat/s_shiftRightJam64Extra.c new file mode 100644 index 0000000000..4d7871226e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_shiftRightJam64Extra.c @@ -0,0 +1,62 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "platform.h" +#include "primitiveTypes.h" + +#ifndef softfloat_shiftRightJam64Extra + +struct uint64_extra + softfloat_shiftRightJam64Extra( + uint64_t a, uint64_t extra, uint_fast32_t dist ) +{ + struct uint64_extra z; + + if ( dist < 64 ) { + z.v = a>>dist; + z.extra = a<<(-dist & 63); + } else { + z.v = 0; + z.extra = (dist == 64) ? a : (a != 0); + } + z.extra |= (extra != 0); + return z; + +} + +#endif + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_shortShiftLeft128.c b/vendor/riscv/riscv-isa-sim/softfloat/s_shortShiftLeft128.c new file mode 100644 index 0000000000..9b7c06726a --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_shortShiftLeft128.c @@ -0,0 +1,55 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "platform.h" +#include "primitiveTypes.h" + +#ifndef softfloat_shortShiftLeft128 + +struct uint128 + softfloat_shortShiftLeft128( uint64_t a64, uint64_t a0, uint_fast8_t dist ) +{ + struct uint128 z; + + z.v64 = a64<<dist | a0>>(-dist & 63); + z.v0 = a0<<dist; + return z; + +} + +#endif + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_shortShiftLeft64To96M.c b/vendor/riscv/riscv-isa-sim/softfloat/s_shortShiftLeft64To96M.c new file mode 100644 index 0000000000..4caf4b9d6e --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_shortShiftLeft64To96M.c @@ -0,0 +1,56 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "platform.h" +#include "primitiveTypes.h" + +#ifndef softfloat_shortShiftLeft64To96M + +void + softfloat_shortShiftLeft64To96M( + uint64_t a, uint_fast8_t dist, uint32_t *zPtr ) +{ + + zPtr[indexWord( 3, 0 )] = (uint32_t) a<<dist; + a >>= 32 - dist; + zPtr[indexWord( 3, 2 )] = a>>32; + zPtr[indexWord( 3, 1 )] = a; + +} + +#endif + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_shortShiftRight128.c b/vendor/riscv/riscv-isa-sim/softfloat/s_shortShiftRight128.c new file mode 100644 index 0000000000..28c39bb273 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_shortShiftRight128.c @@ -0,0 +1,55 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "platform.h" +#include "primitiveTypes.h" + +#ifndef softfloat_shortShiftRight128 + +struct uint128 + softfloat_shortShiftRight128( uint64_t a64, uint64_t a0, uint_fast8_t dist ) +{ + struct uint128 z; + + z.v64 = a64>>dist; + z.v0 = a64<<(-dist & 63) | a0>>dist; + return z; + +} + +#endif + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_shortShiftRightExtendM.c b/vendor/riscv/riscv-isa-sim/softfloat/s_shortShiftRightExtendM.c new file mode 100644 index 0000000000..309188c356 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_shortShiftRightExtendM.c @@ -0,0 +1,73 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "platform.h" +#include "primitiveTypes.h" + +#ifndef softfloat_shortShiftRightExtendM + +void + softfloat_shortShiftRightExtendM( + uint_fast8_t size_words, + const uint32_t *aPtr, + uint_fast8_t dist, + uint32_t *zPtr + ) +{ + uint_fast8_t uNegDist; + unsigned int indexA, lastIndexA; + uint32_t partWordZ, wordA; + + uNegDist = -dist; + indexA = indexWordLo( size_words ); + lastIndexA = indexWordHi( size_words ); + zPtr += indexWordLo( size_words + 1 ); + partWordZ = 0; + for (;;) { + wordA = aPtr[indexA]; + *zPtr = wordA<<(uNegDist & 31) | partWordZ; + zPtr += wordIncr; + partWordZ = wordA>>dist; + if ( indexA == lastIndexA ) break; + indexA += wordIncr; + } + *zPtr = partWordZ; + +} + +#endif + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_shortShiftRightJam128.c b/vendor/riscv/riscv-isa-sim/softfloat/s_shortShiftRightJam128.c new file mode 100644 index 0000000000..3eb0dd4006 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_shortShiftRightJam128.c @@ -0,0 +1,60 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "platform.h" +#include "primitiveTypes.h" + +#ifndef softfloat_shortShiftRightJam128 + +struct uint128 + softfloat_shortShiftRightJam128( + uint64_t a64, uint64_t a0, uint_fast8_t dist ) +{ + uint_fast8_t uNegDist; + struct uint128 z; + + uNegDist = -dist; + z.v64 = a64>>dist; + z.v0 = + a64<<(uNegDist & 63) | a0>>dist + | ((uint64_t) (a0<<(uNegDist & 63)) != 0); + return z; + +} + +#endif + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_shortShiftRightJam128Extra.c b/vendor/riscv/riscv-isa-sim/softfloat/s_shortShiftRightJam128Extra.c new file mode 100644 index 0000000000..13692a0d60 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_shortShiftRightJam128Extra.c @@ -0,0 +1,59 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "platform.h" +#include "primitiveTypes.h" + +#ifndef softfloat_shortShiftRightJam128Extra + +struct uint128_extra + softfloat_shortShiftRightJam128Extra( + uint64_t a64, uint64_t a0, uint64_t extra, uint_fast8_t dist ) +{ + uint_fast8_t uNegDist; + struct uint128_extra z; + + uNegDist = -dist; + z.v.v64 = a64>>dist; + z.v.v0 = a64<<(uNegDist & 63) | a0>>dist; + z.extra = a0<<(uNegDist & 63) | (extra != 0); + return z; + +} + +#endif + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_shortShiftRightJam64.c b/vendor/riscv/riscv-isa-sim/softfloat/s_shortShiftRightJam64.c new file mode 100644 index 0000000000..7e93cd4fbd --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_shortShiftRightJam64.c @@ -0,0 +1,50 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "platform.h" + +#ifndef softfloat_shortShiftRightJam64 + +uint64_t softfloat_shortShiftRightJam64( uint64_t a, uint_fast8_t dist ) +{ + + return a>>dist | ((a & (((uint_fast64_t) 1<<dist) - 1)) != 0); + +} + +#endif + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_shortShiftRightJam64Extra.c b/vendor/riscv/riscv-isa-sim/softfloat/s_shortShiftRightJam64Extra.c new file mode 100644 index 0000000000..25d23f4b94 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_shortShiftRightJam64Extra.c @@ -0,0 +1,56 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "platform.h" +#include "primitiveTypes.h" + +#ifndef softfloat_shortShiftRightJam64Extra + +struct uint64_extra + softfloat_shortShiftRightJam64Extra( + uint64_t a, uint64_t extra, uint_fast8_t dist ) +{ + struct uint64_extra z; + + z.v = a>>dist; + z.extra = a<<(-dist & 63) | (extra != 0); + return z; + +} + +#endif + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_shortShiftRightM.c b/vendor/riscv/riscv-isa-sim/softfloat/s_shortShiftRightM.c new file mode 100644 index 0000000000..308ad59c57 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_shortShiftRightM.c @@ -0,0 +1,70 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "platform.h" +#include "primitiveTypes.h" + +#ifndef softfloat_shortShiftRightM + +void + softfloat_shortShiftRightM( + uint_fast8_t size_words, + const uint32_t *aPtr, + uint_fast8_t dist, + uint32_t *zPtr + ) +{ + uint_fast8_t uNegDist; + unsigned int index, lastIndex; + uint32_t partWordZ, wordA; + + uNegDist = -dist; + index = indexWordLo( size_words ); + lastIndex = indexWordHi( size_words ); + partWordZ = aPtr[index]>>dist; + while ( index != lastIndex ) { + wordA = aPtr[index + wordIncr]; + zPtr[index] = wordA<<(uNegDist & 31) | partWordZ; + index += wordIncr; + partWordZ = wordA>>dist; + } + zPtr[index] = partWordZ; + +} + +#endif + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_sub128.c b/vendor/riscv/riscv-isa-sim/softfloat/s_sub128.c new file mode 100644 index 0000000000..ed86e10005 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_sub128.c @@ -0,0 +1,55 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "platform.h" +#include "primitiveTypes.h" + +#ifndef softfloat_sub128 + +struct uint128 + softfloat_sub128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 ) +{ + struct uint128 z; + + z.v0 = a0 - b0; + z.v64 = a64 - b64 - (a0 < b0); + return z; + +} + +#endif + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_sub1XM.c b/vendor/riscv/riscv-isa-sim/softfloat/s_sub1XM.c new file mode 100644 index 0000000000..73773e5b03 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_sub1XM.c @@ -0,0 +1,60 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "platform.h" +#include "primitiveTypes.h" + +#ifndef softfloat_sub1XM + +void softfloat_sub1XM( uint_fast8_t size_words, uint32_t *zPtr ) +{ + unsigned int index, lastIndex; + uint32_t wordA; + + index = indexWordLo( size_words ); + lastIndex = indexWordHi( size_words ); + for (;;) { + wordA = zPtr[index]; + zPtr[index] = wordA - 1; + if ( wordA || (index == lastIndex) ) break; + index += wordIncr; + } + +} + +#endif + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_sub256M.c b/vendor/riscv/riscv-isa-sim/softfloat/s_sub256M.c new file mode 100644 index 0000000000..c07b45eae9 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_sub256M.c @@ -0,0 +1,65 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "platform.h" +#include "primitiveTypes.h" + +#ifndef softfloat_sub256M + +void + softfloat_sub256M( + const uint64_t *aPtr, const uint64_t *bPtr, uint64_t *zPtr ) +{ + unsigned int index; + uint_fast8_t borrow; + uint64_t wordA, wordB; + + index = indexWordLo( 4 ); + borrow = 0; + for (;;) { + wordA = aPtr[index]; + wordB = bPtr[index]; + zPtr[index] = wordA - wordB - borrow; + if ( index == indexWordHi( 4 ) ) break; + borrow = borrow ? (wordA <= wordB) : (wordA < wordB); + index += wordIncr; + } + +} + +#endif + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_subM.c b/vendor/riscv/riscv-isa-sim/softfloat/s_subM.c new file mode 100644 index 0000000000..003f699f14 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_subM.c @@ -0,0 +1,70 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "platform.h" +#include "primitiveTypes.h" + +#ifndef softfloat_subM + +void + softfloat_subM( + uint_fast8_t size_words, + const uint32_t *aPtr, + const uint32_t *bPtr, + uint32_t *zPtr + ) +{ + unsigned int index, lastIndex; + uint_fast8_t borrow; + uint32_t wordA, wordB; + + index = indexWordLo( size_words ); + lastIndex = indexWordHi( size_words ); + borrow = 0; + for (;;) { + wordA = aPtr[index]; + wordB = bPtr[index]; + zPtr[index] = wordA - wordB - borrow; + if ( index == lastIndex ) break; + borrow = borrow ? (wordA <= wordB) : (wordA < wordB); + index += wordIncr; + } + +} + +#endif + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_subMagsF128.c b/vendor/riscv/riscv-isa-sim/softfloat/s_subMagsF128.c new file mode 100644 index 0000000000..c4264d542b --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_subMagsF128.c @@ -0,0 +1,139 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +float128_t + softfloat_subMagsF128( + uint_fast64_t uiA64, + uint_fast64_t uiA0, + uint_fast64_t uiB64, + uint_fast64_t uiB0, + bool signZ + ) +{ + int_fast32_t expA; + struct uint128 sigA; + int_fast32_t expB; + struct uint128 sigB, sigZ; + int_fast32_t expDiff, expZ; + struct uint128 uiZ; + union ui128_f128 uZ; + + expA = expF128UI64( uiA64 ); + sigA.v64 = fracF128UI64( uiA64 ); + sigA.v0 = uiA0; + expB = expF128UI64( uiB64 ); + sigB.v64 = fracF128UI64( uiB64 ); + sigB.v0 = uiB0; + sigA = softfloat_shortShiftLeft128( sigA.v64, sigA.v0, 4 ); + sigB = softfloat_shortShiftLeft128( sigB.v64, sigB.v0, 4 ); + expDiff = expA - expB; + if ( 0 < expDiff ) goto expABigger; + if ( expDiff < 0 ) goto expBBigger; + if ( expA == 0x7FFF ) { + if ( sigA.v64 | sigA.v0 | sigB.v64 | sigB.v0 ) goto propagateNaN; + softfloat_raiseFlags( softfloat_flag_invalid ); + uiZ.v64 = defaultNaNF128UI64; + uiZ.v0 = defaultNaNF128UI0; + goto uiZ; + } + expZ = expA; + if ( ! expZ ) expZ = 1; + if ( sigB.v64 < sigA.v64 ) goto aBigger; + if ( sigA.v64 < sigB.v64 ) goto bBigger; + if ( sigB.v0 < sigA.v0 ) goto aBigger; + if ( sigA.v0 < sigB.v0 ) goto bBigger; + uiZ.v64 = + packToF128UI64( + (softfloat_roundingMode == softfloat_round_min), 0, 0 ); + uiZ.v0 = 0; + goto uiZ; + expBBigger: + if ( expB == 0x7FFF ) { + if ( sigB.v64 | sigB.v0 ) goto propagateNaN; + uiZ.v64 = packToF128UI64( signZ ^ 1, 0x7FFF, 0 ); + uiZ.v0 = 0; + goto uiZ; + } + if ( expA ) { + sigA.v64 |= UINT64_C( 0x0010000000000000 ); + } else { + ++expDiff; + if ( ! expDiff ) goto newlyAlignedBBigger; + } + sigA = softfloat_shiftRightJam128( sigA.v64, sigA.v0, -expDiff ); + newlyAlignedBBigger: + expZ = expB; + sigB.v64 |= UINT64_C( 0x0010000000000000 ); + bBigger: + signZ = ! signZ; + sigZ = softfloat_sub128( sigB.v64, sigB.v0, sigA.v64, sigA.v0 ); + goto normRoundPack; + expABigger: + if ( expA == 0x7FFF ) { + if ( sigA.v64 | sigA.v0 ) goto propagateNaN; + uiZ.v64 = uiA64; + uiZ.v0 = uiA0; + goto uiZ; + } + if ( expB ) { + sigB.v64 |= UINT64_C( 0x0010000000000000 ); + } else { + --expDiff; + if ( ! expDiff ) goto newlyAlignedABigger; + } + sigB = softfloat_shiftRightJam128( sigB.v64, sigB.v0, expDiff ); + newlyAlignedABigger: + expZ = expA; + sigA.v64 |= UINT64_C( 0x0010000000000000 ); + aBigger: + sigZ = softfloat_sub128( sigA.v64, sigA.v0, sigB.v64, sigB.v0 ); + normRoundPack: + return softfloat_normRoundPackToF128( signZ, expZ - 5, sigZ.v64, sigZ.v0 ); + propagateNaN: + uiZ = softfloat_propagateNaNF128UI( uiA64, uiA0, uiB64, uiB0 ); + uiZ: + uZ.ui = uiZ; + return uZ.f; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_subMagsF16.c b/vendor/riscv/riscv-isa-sim/softfloat/s_subMagsF16.c new file mode 100644 index 0000000000..5ec579e882 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_subMagsF16.c @@ -0,0 +1,187 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the +University of California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +float16_t softfloat_subMagsF16( uint_fast16_t uiA, uint_fast16_t uiB ) +{ + int_fast8_t expA; + uint_fast16_t sigA; + int_fast8_t expB; + uint_fast16_t sigB; + int_fast8_t expDiff; + uint_fast16_t uiZ; + int_fast16_t sigDiff; + bool signZ; + int_fast8_t shiftDist, expZ; + uint_fast16_t sigZ, sigX, sigY; + uint_fast32_t sig32Z; + int_fast8_t roundingMode; + union ui16_f16 uZ; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + expA = expF16UI( uiA ); + sigA = fracF16UI( uiA ); + expB = expF16UI( uiB ); + sigB = fracF16UI( uiB ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + expDiff = expA - expB; + if ( ! expDiff ) { + /*-------------------------------------------------------------------- + *--------------------------------------------------------------------*/ + if ( expA == 0x1F ) { + if ( sigA | sigB ) goto propagateNaN; + softfloat_raiseFlags( softfloat_flag_invalid ); + uiZ = defaultNaNF16UI; + goto uiZ; + } + sigDiff = sigA - sigB; + if ( ! sigDiff ) { + uiZ = + packToF16UI( + (softfloat_roundingMode == softfloat_round_min), 0, 0 ); + goto uiZ; + } + if ( expA ) --expA; + signZ = signF16UI( uiA ); + if ( sigDiff < 0 ) { + signZ = ! signZ; + sigDiff = -sigDiff; + } + shiftDist = softfloat_countLeadingZeros16( sigDiff ) - 5; + expZ = expA - shiftDist; + if ( expZ < 0 ) { + shiftDist = expA; + expZ = 0; + } + sigZ = sigDiff<<shiftDist; + goto pack; + } else { + /*-------------------------------------------------------------------- + *--------------------------------------------------------------------*/ + signZ = signF16UI( uiA ); + if ( expDiff < 0 ) { + /*---------------------------------------------------------------- + *----------------------------------------------------------------*/ + signZ = ! signZ; + if ( expB == 0x1F ) { + if ( sigB ) goto propagateNaN; + uiZ = packToF16UI( signZ, 0x1F, 0 ); + goto uiZ; + } + if ( expDiff <= -13 ) { + uiZ = packToF16UI( signZ, expB, sigB ); + if ( expA | sigA ) goto subEpsilon; + goto uiZ; + } + expZ = expA + 19; + sigX = sigB | 0x0400; + sigY = sigA + (expA ? 0x0400 : sigA); + expDiff = -expDiff; + } else { + /*---------------------------------------------------------------- + *----------------------------------------------------------------*/ + uiZ = uiA; + if ( expA == 0x1F ) { + if ( sigA ) goto propagateNaN; + goto uiZ; + } + if ( 13 <= expDiff ) { + if ( expB | sigB ) goto subEpsilon; + goto uiZ; + } + expZ = expB + 19; + sigX = sigA | 0x0400; + sigY = sigB + (expB ? 0x0400 : sigB); + } + sig32Z = ((uint_fast32_t) sigX<<expDiff) - sigY; + shiftDist = softfloat_countLeadingZeros32( sig32Z ) - 1; + sig32Z <<= shiftDist; + expZ -= shiftDist; + sigZ = sig32Z>>16; + if ( sig32Z & 0xFFFF ) { + sigZ |= 1; + } else { + if ( ! (sigZ & 0xF) && ((unsigned int) expZ < 0x1E) ) { + sigZ >>= 4; + goto pack; + } + } + return softfloat_roundPackToF16( signZ, expZ, sigZ ); + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + propagateNaN: + uiZ = softfloat_propagateNaNF16UI( uiA, uiB ); + goto uiZ; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + subEpsilon: + roundingMode = softfloat_roundingMode; + if ( roundingMode != softfloat_round_near_even ) { + if ( + (roundingMode == softfloat_round_minMag) + || (roundingMode + == (signF16UI( uiZ ) ? softfloat_round_max + : softfloat_round_min)) + ) { + --uiZ; + } +#ifdef SOFTFLOAT_ROUND_ODD + else if ( roundingMode == softfloat_round_odd ) { + uiZ = (uiZ - 1) | 1; + } +#endif + } + softfloat_exceptionFlags |= softfloat_flag_inexact; + goto uiZ; + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + pack: + uiZ = packToF16UI( signZ, expZ, sigZ ); + uiZ: + uZ.ui = uiZ; + return uZ.f; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_subMagsF32.c b/vendor/riscv/riscv-isa-sim/softfloat/s_subMagsF32.c new file mode 100644 index 0000000000..86e89f2ec3 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_subMagsF32.c @@ -0,0 +1,143 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +float32_t softfloat_subMagsF32( uint_fast32_t uiA, uint_fast32_t uiB ) +{ + int_fast16_t expA; + uint_fast32_t sigA; + int_fast16_t expB; + uint_fast32_t sigB; + int_fast16_t expDiff; + uint_fast32_t uiZ; + int_fast32_t sigDiff; + bool signZ; + int_fast8_t shiftDist; + int_fast16_t expZ; + uint_fast32_t sigX, sigY; + union ui32_f32 uZ; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + expA = expF32UI( uiA ); + sigA = fracF32UI( uiA ); + expB = expF32UI( uiB ); + sigB = fracF32UI( uiB ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + expDiff = expA - expB; + if ( ! expDiff ) { + /*-------------------------------------------------------------------- + *--------------------------------------------------------------------*/ + if ( expA == 0xFF ) { + if ( sigA | sigB ) goto propagateNaN; + softfloat_raiseFlags( softfloat_flag_invalid ); + uiZ = defaultNaNF32UI; + goto uiZ; + } + sigDiff = sigA - sigB; + if ( ! sigDiff ) { + uiZ = + packToF32UI( + (softfloat_roundingMode == softfloat_round_min), 0, 0 ); + goto uiZ; + } + if ( expA ) --expA; + signZ = signF32UI( uiA ); + if ( sigDiff < 0 ) { + signZ = ! signZ; + sigDiff = -sigDiff; + } + shiftDist = softfloat_countLeadingZeros32( sigDiff ) - 8; + expZ = expA - shiftDist; + if ( expZ < 0 ) { + shiftDist = expA; + expZ = 0; + } + uiZ = packToF32UI( signZ, expZ, sigDiff<<shiftDist ); + goto uiZ; + } else { + /*-------------------------------------------------------------------- + *--------------------------------------------------------------------*/ + signZ = signF32UI( uiA ); + sigA <<= 7; + sigB <<= 7; + if ( expDiff < 0 ) { + /*---------------------------------------------------------------- + *----------------------------------------------------------------*/ + signZ = ! signZ; + if ( expB == 0xFF ) { + if ( sigB ) goto propagateNaN; + uiZ = packToF32UI( signZ, 0xFF, 0 ); + goto uiZ; + } + expZ = expB - 1; + sigX = sigB | 0x40000000; + sigY = sigA + (expA ? 0x40000000 : sigA); + expDiff = -expDiff; + } else { + /*---------------------------------------------------------------- + *----------------------------------------------------------------*/ + if ( expA == 0xFF ) { + if ( sigA ) goto propagateNaN; + uiZ = uiA; + goto uiZ; + } + expZ = expA - 1; + sigX = sigA | 0x40000000; + sigY = sigB + (expB ? 0x40000000 : sigB); + } + return + softfloat_normRoundPackToF32( + signZ, expZ, sigX - softfloat_shiftRightJam32( sigY, expDiff ) + ); + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + propagateNaN: + uiZ = softfloat_propagateNaNF32UI( uiA, uiB ); + uiZ: + uZ.ui = uiZ; + return uZ.f; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/s_subMagsF64.c b/vendor/riscv/riscv-isa-sim/softfloat/s_subMagsF64.c new file mode 100644 index 0000000000..5ef9ea446a --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/s_subMagsF64.c @@ -0,0 +1,141 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdbool.h> +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +float64_t + softfloat_subMagsF64( uint_fast64_t uiA, uint_fast64_t uiB, bool signZ ) +{ + int_fast16_t expA; + uint_fast64_t sigA; + int_fast16_t expB; + uint_fast64_t sigB; + int_fast16_t expDiff; + uint_fast64_t uiZ; + int_fast64_t sigDiff; + int_fast8_t shiftDist; + int_fast16_t expZ; + uint_fast64_t sigZ; + union ui64_f64 uZ; + + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + expA = expF64UI( uiA ); + sigA = fracF64UI( uiA ); + expB = expF64UI( uiB ); + sigB = fracF64UI( uiB ); + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + expDiff = expA - expB; + if ( ! expDiff ) { + /*-------------------------------------------------------------------- + *--------------------------------------------------------------------*/ + if ( expA == 0x7FF ) { + if ( sigA | sigB ) goto propagateNaN; + softfloat_raiseFlags( softfloat_flag_invalid ); + uiZ = defaultNaNF64UI; + goto uiZ; + } + sigDiff = sigA - sigB; + if ( ! sigDiff ) { + uiZ = + packToF64UI( + (softfloat_roundingMode == softfloat_round_min), 0, 0 ); + goto uiZ; + } + if ( expA ) --expA; + if ( sigDiff < 0 ) { + signZ = ! signZ; + sigDiff = -sigDiff; + } + shiftDist = softfloat_countLeadingZeros64( sigDiff ) - 11; + expZ = expA - shiftDist; + if ( expZ < 0 ) { + shiftDist = expA; + expZ = 0; + } + uiZ = packToF64UI( signZ, expZ, sigDiff<<shiftDist ); + goto uiZ; + } else { + /*-------------------------------------------------------------------- + *--------------------------------------------------------------------*/ + sigA <<= 10; + sigB <<= 10; + if ( expDiff < 0 ) { + /*---------------------------------------------------------------- + *----------------------------------------------------------------*/ + signZ = ! signZ; + if ( expB == 0x7FF ) { + if ( sigB ) goto propagateNaN; + uiZ = packToF64UI( signZ, 0x7FF, 0 ); + goto uiZ; + } + sigA += expA ? UINT64_C( 0x4000000000000000 ) : sigA; + sigA = softfloat_shiftRightJam64( sigA, -expDiff ); + sigB |= UINT64_C( 0x4000000000000000 ); + expZ = expB; + sigZ = sigB - sigA; + } else { + /*---------------------------------------------------------------- + *----------------------------------------------------------------*/ + if ( expA == 0x7FF ) { + if ( sigA ) goto propagateNaN; + uiZ = uiA; + goto uiZ; + } + sigB += expB ? UINT64_C( 0x4000000000000000 ) : sigB; + sigB = softfloat_shiftRightJam64( sigB, expDiff ); + sigA |= UINT64_C( 0x4000000000000000 ); + expZ = expA; + sigZ = sigA - sigB; + } + return softfloat_normRoundPackToF64( signZ, expZ - 1, sigZ ); + } + /*------------------------------------------------------------------------ + *------------------------------------------------------------------------*/ + propagateNaN: + uiZ = softfloat_propagateNaNF64UI( uiA, uiB ); + uiZ: + uZ.ui = uiZ; + return uZ.f; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/softfloat.ac b/vendor/riscv/riscv-isa-sim/softfloat/softfloat.ac new file mode 100644 index 0000000000..e69de29bb2 diff --git a/vendor/riscv/riscv-isa-sim/softfloat/softfloat.h b/vendor/riscv/riscv-isa-sim/softfloat/softfloat.h new file mode 100644 index 0000000000..bdac1be263 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/softfloat.h @@ -0,0 +1,402 @@ + +/*============================================================================ + +This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the +University of California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + + +/*============================================================================ +| Note: If SoftFloat is made available as a general library for programs to +| use, it is strongly recommended that a platform-specific version of this +| header, "softfloat.h", be created that folds in "softfloat_types.h" and that +| eliminates all dependencies on compile-time macros. +*============================================================================*/ + + +#ifndef softfloat_h +#define softfloat_h 1 + +#include <stdbool.h> +#include <stdint.h> +#include "softfloat_types.h" + +#ifndef THREAD_LOCAL +#define THREAD_LOCAL +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/*---------------------------------------------------------------------------- +| Software floating-point underflow tininess-detection mode. +*----------------------------------------------------------------------------*/ +extern THREAD_LOCAL uint_fast8_t softfloat_detectTininess; +enum { + softfloat_tininess_beforeRounding = 0, + softfloat_tininess_afterRounding = 1 +}; + +/*---------------------------------------------------------------------------- +| Software floating-point rounding mode. (Mode "odd" is supported only if +| SoftFloat is compiled with macro 'SOFTFLOAT_ROUND_ODD' defined.) +*----------------------------------------------------------------------------*/ +extern THREAD_LOCAL uint_fast8_t softfloat_roundingMode; +enum { + softfloat_round_near_even = 0, + softfloat_round_minMag = 1, + softfloat_round_min = 2, + softfloat_round_max = 3, + softfloat_round_near_maxMag = 4, + softfloat_round_odd = 5 +}; + +/*---------------------------------------------------------------------------- +| Software floating-point exception flags. +*----------------------------------------------------------------------------*/ +extern THREAD_LOCAL uint_fast8_t softfloat_exceptionFlags; +enum { + softfloat_flag_inexact = 1, + softfloat_flag_underflow = 2, + softfloat_flag_overflow = 4, + softfloat_flag_infinite = 8, + softfloat_flag_invalid = 16 +}; + +/*---------------------------------------------------------------------------- +| Routine to raise any or all of the software floating-point exception flags. +*----------------------------------------------------------------------------*/ +void softfloat_raiseFlags( uint_fast8_t ); + +/*---------------------------------------------------------------------------- +| Integer-to-floating-point conversion routines. +*----------------------------------------------------------------------------*/ +float16_t ui32_to_f16( uint32_t ); +float32_t ui32_to_f32( uint32_t ); +float64_t ui32_to_f64( uint32_t ); +#ifdef SOFTFLOAT_FAST_INT64 +extFloat80_t ui32_to_extF80( uint32_t ); +float128_t ui32_to_f128( uint32_t ); +#endif +void ui32_to_extF80M( uint32_t, extFloat80_t * ); +void ui32_to_f128M( uint32_t, float128_t * ); +float16_t ui64_to_f16( uint64_t ); +float32_t ui64_to_f32( uint64_t ); +float64_t ui64_to_f64( uint64_t ); +#ifdef SOFTFLOAT_FAST_INT64 +extFloat80_t ui64_to_extF80( uint64_t ); +float128_t ui64_to_f128( uint64_t ); +#endif +void ui64_to_extF80M( uint64_t, extFloat80_t * ); +void ui64_to_f128M( uint64_t, float128_t * ); +float16_t i32_to_f16( int32_t ); +float32_t i32_to_f32( int32_t ); +float64_t i32_to_f64( int32_t ); +#ifdef SOFTFLOAT_FAST_INT64 +extFloat80_t i32_to_extF80( int32_t ); +float128_t i32_to_f128( int32_t ); +#endif +void i32_to_extF80M( int32_t, extFloat80_t * ); +void i32_to_f128M( int32_t, float128_t * ); +float16_t i64_to_f16( int64_t ); +float32_t i64_to_f32( int64_t ); +float64_t i64_to_f64( int64_t ); +#ifdef SOFTFLOAT_FAST_INT64 +extFloat80_t i64_to_extF80( int64_t ); +float128_t i64_to_f128( int64_t ); +#endif +void i64_to_extF80M( int64_t, extFloat80_t * ); +void i64_to_f128M( int64_t, float128_t * ); + +/*---------------------------------------------------------------------------- +| 16-bit (half-precision) floating-point operations. +*----------------------------------------------------------------------------*/ +uint_fast8_t f16_to_ui8( float16_t, uint_fast8_t, bool ); +uint_fast16_t f16_to_ui16( float16_t, uint_fast8_t, bool ); +uint_fast32_t f16_to_ui32( float16_t, uint_fast8_t, bool ); +uint_fast64_t f16_to_ui64( float16_t, uint_fast8_t, bool ); +int_fast8_t f16_to_i8( float16_t, uint_fast8_t, bool ); +int_fast16_t f16_to_i16( float16_t, uint_fast8_t, bool ); +int_fast32_t f16_to_i32( float16_t, uint_fast8_t, bool ); +int_fast64_t f16_to_i64( float16_t, uint_fast8_t, bool ); +uint_fast32_t f16_to_ui32_r_minMag( float16_t, bool ); +uint_fast64_t f16_to_ui64_r_minMag( float16_t, bool ); +int_fast32_t f16_to_i32_r_minMag( float16_t, bool ); +int_fast64_t f16_to_i64_r_minMag( float16_t, bool ); +float32_t f16_to_f32( float16_t ); +float64_t f16_to_f64( float16_t ); +#ifdef SOFTFLOAT_FAST_INT64 +extFloat80_t f16_to_extF80( float16_t ); +float128_t f16_to_f128( float16_t ); +#endif +void f16_to_extF80M( float16_t, extFloat80_t * ); +void f16_to_f128M( float16_t, float128_t * ); +float16_t f16_roundToInt( float16_t, uint_fast8_t, bool ); +float16_t f16_add( float16_t, float16_t ); +float16_t f16_sub( float16_t, float16_t ); +float16_t f16_max( float16_t, float16_t ); +float16_t f16_min( float16_t, float16_t ); +float16_t f16_mul( float16_t, float16_t ); +float16_t f16_mulAdd( float16_t, float16_t, float16_t ); +float16_t f16_div( float16_t, float16_t ); +float16_t f16_rem( float16_t, float16_t ); +float16_t f16_sqrt( float16_t ); +bool f16_eq( float16_t, float16_t ); +bool f16_le( float16_t, float16_t ); +bool f16_lt( float16_t, float16_t ); +bool f16_eq_signaling( float16_t, float16_t ); +bool f16_le_quiet( float16_t, float16_t ); +bool f16_lt_quiet( float16_t, float16_t ); +bool f16_isSignalingNaN( float16_t ); +uint_fast16_t f16_classify( float16_t ); +float16_t f16_rsqrte7( float16_t ); +float16_t f16_recip7( float16_t ); + +/*---------------------------------------------------------------------------- +| 32-bit (single-precision) floating-point operations. +*----------------------------------------------------------------------------*/ +uint_fast16_t f32_to_ui16( float32_t, uint_fast8_t, bool ); +uint_fast32_t f32_to_ui32( float32_t, uint_fast8_t, bool ); +uint_fast64_t f32_to_ui64( float32_t, uint_fast8_t, bool ); +int_fast16_t f32_to_i16( float32_t, uint_fast8_t, bool ); +int_fast32_t f32_to_i32( float32_t, uint_fast8_t, bool ); +int_fast64_t f32_to_i64( float32_t, uint_fast8_t, bool ); +uint_fast32_t f32_to_ui32_r_minMag( float32_t, bool ); +uint_fast64_t f32_to_ui64_r_minMag( float32_t, bool ); +int_fast32_t f32_to_i32_r_minMag( float32_t, bool ); +int_fast64_t f32_to_i64_r_minMag( float32_t, bool ); +float16_t f32_to_f16( float32_t ); +float64_t f32_to_f64( float32_t ); +#ifdef SOFTFLOAT_FAST_INT64 +extFloat80_t f32_to_extF80( float32_t ); +float128_t f32_to_f128( float32_t ); +#endif +void f32_to_extF80M( float32_t, extFloat80_t * ); +void f32_to_f128M( float32_t, float128_t * ); +float32_t f32_roundToInt( float32_t, uint_fast8_t, bool ); +float32_t f32_add( float32_t, float32_t ); +float32_t f32_sub( float32_t, float32_t ); +float32_t f32_max( float32_t, float32_t ); +float32_t f32_min( float32_t, float32_t ); +float32_t f32_mul( float32_t, float32_t ); +float32_t f32_mulAdd( float32_t, float32_t, float32_t ); +float32_t f32_div( float32_t, float32_t ); +float32_t f32_rem( float32_t, float32_t ); +float32_t f32_sqrt( float32_t ); +bool f32_eq( float32_t, float32_t ); +bool f32_le( float32_t, float32_t ); +bool f32_lt( float32_t, float32_t ); +bool f32_eq_signaling( float32_t, float32_t ); +bool f32_le_quiet( float32_t, float32_t ); +bool f32_lt_quiet( float32_t, float32_t ); +bool f32_isSignalingNaN( float32_t ); +uint_fast16_t f32_classify( float32_t ); +float32_t f32_rsqrte7( float32_t ); +float32_t f32_recip7( float32_t ); + +/*---------------------------------------------------------------------------- +| 64-bit (double-precision) floating-point operations. +*----------------------------------------------------------------------------*/ +uint_fast32_t f64_to_ui32( float64_t, uint_fast8_t, bool ); +uint_fast64_t f64_to_ui64( float64_t, uint_fast8_t, bool ); +int_fast32_t f64_to_i32( float64_t, uint_fast8_t, bool ); +int_fast64_t f64_to_i64( float64_t, uint_fast8_t, bool ); +uint_fast32_t f64_to_ui32_r_minMag( float64_t, bool ); +uint_fast64_t f64_to_ui64_r_minMag( float64_t, bool ); +int_fast32_t f64_to_i32_r_minMag( float64_t, bool ); +int_fast64_t f64_to_i64_r_minMag( float64_t, bool ); +float16_t f64_to_f16( float64_t ); +float32_t f64_to_f32( float64_t ); +#ifdef SOFTFLOAT_FAST_INT64 +extFloat80_t f64_to_extF80( float64_t ); +float128_t f64_to_f128( float64_t ); +#endif +void f64_to_extF80M( float64_t, extFloat80_t * ); +void f64_to_f128M( float64_t, float128_t * ); +float64_t f64_roundToInt( float64_t, uint_fast8_t, bool ); +float64_t f64_add( float64_t, float64_t ); +float64_t f64_sub( float64_t, float64_t ); +float64_t f64_max( float64_t, float64_t ); +float64_t f64_min( float64_t, float64_t ); +float64_t f64_mul( float64_t, float64_t ); +float64_t f64_mulAdd( float64_t, float64_t, float64_t ); +float64_t f64_div( float64_t, float64_t ); +float64_t f64_rem( float64_t, float64_t ); +float64_t f64_sqrt( float64_t ); +bool f64_eq( float64_t, float64_t ); +bool f64_le( float64_t, float64_t ); +bool f64_lt( float64_t, float64_t ); +bool f64_eq_signaling( float64_t, float64_t ); +bool f64_le_quiet( float64_t, float64_t ); +bool f64_lt_quiet( float64_t, float64_t ); +bool f64_isSignalingNaN( float64_t ); +uint_fast16_t f64_classify( float64_t ); +float64_t f64_rsqrte7( float64_t ); +float64_t f64_recip7( float64_t ); + +/*---------------------------------------------------------------------------- +| Rounding precision for 80-bit extended double-precision floating-point. +| Valid values are 32, 64, and 80. +*----------------------------------------------------------------------------*/ +extern THREAD_LOCAL uint_fast8_t extF80_roundingPrecision; + +/*---------------------------------------------------------------------------- +| 80-bit extended double-precision floating-point operations. +*----------------------------------------------------------------------------*/ +#ifdef SOFTFLOAT_FAST_INT64 +uint_fast32_t extF80_to_ui32( extFloat80_t, uint_fast8_t, bool ); +uint_fast64_t extF80_to_ui64( extFloat80_t, uint_fast8_t, bool ); +int_fast32_t extF80_to_i32( extFloat80_t, uint_fast8_t, bool ); +int_fast64_t extF80_to_i64( extFloat80_t, uint_fast8_t, bool ); +uint_fast32_t extF80_to_ui32_r_minMag( extFloat80_t, bool ); +uint_fast64_t extF80_to_ui64_r_minMag( extFloat80_t, bool ); +int_fast32_t extF80_to_i32_r_minMag( extFloat80_t, bool ); +int_fast64_t extF80_to_i64_r_minMag( extFloat80_t, bool ); +float16_t extF80_to_f16( extFloat80_t ); +float32_t extF80_to_f32( extFloat80_t ); +float64_t extF80_to_f64( extFloat80_t ); +float128_t extF80_to_f128( extFloat80_t ); +extFloat80_t extF80_roundToInt( extFloat80_t, uint_fast8_t, bool ); +extFloat80_t extF80_add( extFloat80_t, extFloat80_t ); +extFloat80_t extF80_sub( extFloat80_t, extFloat80_t ); +extFloat80_t extF80_mul( extFloat80_t, extFloat80_t ); +extFloat80_t extF80_div( extFloat80_t, extFloat80_t ); +extFloat80_t extF80_rem( extFloat80_t, extFloat80_t ); +extFloat80_t extF80_sqrt( extFloat80_t ); +bool extF80_eq( extFloat80_t, extFloat80_t ); +bool extF80_le( extFloat80_t, extFloat80_t ); +bool extF80_lt( extFloat80_t, extFloat80_t ); +bool extF80_eq_signaling( extFloat80_t, extFloat80_t ); +bool extF80_le_quiet( extFloat80_t, extFloat80_t ); +bool extF80_lt_quiet( extFloat80_t, extFloat80_t ); +bool extF80_isSignalingNaN( extFloat80_t ); +#endif +uint_fast32_t extF80M_to_ui32( const extFloat80_t *, uint_fast8_t, bool ); +uint_fast64_t extF80M_to_ui64( const extFloat80_t *, uint_fast8_t, bool ); +int_fast32_t extF80M_to_i32( const extFloat80_t *, uint_fast8_t, bool ); +int_fast64_t extF80M_to_i64( const extFloat80_t *, uint_fast8_t, bool ); +uint_fast32_t extF80M_to_ui32_r_minMag( const extFloat80_t *, bool ); +uint_fast64_t extF80M_to_ui64_r_minMag( const extFloat80_t *, bool ); +int_fast32_t extF80M_to_i32_r_minMag( const extFloat80_t *, bool ); +int_fast64_t extF80M_to_i64_r_minMag( const extFloat80_t *, bool ); +float16_t extF80M_to_f16( const extFloat80_t * ); +float32_t extF80M_to_f32( const extFloat80_t * ); +float64_t extF80M_to_f64( const extFloat80_t * ); +void extF80M_to_f128M( const extFloat80_t *, float128_t * ); +void + extF80M_roundToInt( + const extFloat80_t *, uint_fast8_t, bool, extFloat80_t * ); +void extF80M_add( const extFloat80_t *, const extFloat80_t *, extFloat80_t * ); +void extF80M_sub( const extFloat80_t *, const extFloat80_t *, extFloat80_t * ); +void extF80M_mul( const extFloat80_t *, const extFloat80_t *, extFloat80_t * ); +void extF80M_div( const extFloat80_t *, const extFloat80_t *, extFloat80_t * ); +void extF80M_rem( const extFloat80_t *, const extFloat80_t *, extFloat80_t * ); +void extF80M_sqrt( const extFloat80_t *, extFloat80_t * ); +bool extF80M_eq( const extFloat80_t *, const extFloat80_t * ); +bool extF80M_le( const extFloat80_t *, const extFloat80_t * ); +bool extF80M_lt( const extFloat80_t *, const extFloat80_t * ); +bool extF80M_eq_signaling( const extFloat80_t *, const extFloat80_t * ); +bool extF80M_le_quiet( const extFloat80_t *, const extFloat80_t * ); +bool extF80M_lt_quiet( const extFloat80_t *, const extFloat80_t * ); +bool extF80M_isSignalingNaN( const extFloat80_t * ); + +/*---------------------------------------------------------------------------- +| 128-bit (quadruple-precision) floating-point operations. +*----------------------------------------------------------------------------*/ +#ifdef SOFTFLOAT_FAST_INT64 +uint_fast32_t f128_to_ui32( float128_t, uint_fast8_t, bool ); +uint_fast64_t f128_to_ui64( float128_t, uint_fast8_t, bool ); +int_fast32_t f128_to_i32( float128_t, uint_fast8_t, bool ); +int_fast64_t f128_to_i64( float128_t, uint_fast8_t, bool ); +uint_fast32_t f128_to_ui32_r_minMag( float128_t, bool ); +uint_fast64_t f128_to_ui64_r_minMag( float128_t, bool ); +int_fast32_t f128_to_i32_r_minMag( float128_t, bool ); +int_fast64_t f128_to_i64_r_minMag( float128_t, bool ); +float16_t f128_to_f16( float128_t ); +float32_t f128_to_f32( float128_t ); +float64_t f128_to_f64( float128_t ); +extFloat80_t f128_to_extF80( float128_t ); +float128_t f128_roundToInt( float128_t, uint_fast8_t, bool ); +float128_t f128_add( float128_t, float128_t ); +float128_t f128_sub( float128_t, float128_t ); +float128_t f128_mul( float128_t, float128_t ); +float128_t f128_mulAdd( float128_t, float128_t, float128_t ); +float128_t f128_div( float128_t, float128_t ); +float128_t f128_rem( float128_t, float128_t ); +float128_t f128_sqrt( float128_t ); +bool f128_eq( float128_t, float128_t ); +bool f128_le( float128_t, float128_t ); +bool f128_lt( float128_t, float128_t ); +bool f128_eq_signaling( float128_t, float128_t ); +bool f128_le_quiet( float128_t, float128_t ); +bool f128_lt_quiet( float128_t, float128_t ); +bool f128_isSignalingNaN( float128_t ); +uint_fast16_t f128_classify( float128_t ); +#endif +uint_fast32_t f128M_to_ui32( const float128_t *, uint_fast8_t, bool ); +uint_fast64_t f128M_to_ui64( const float128_t *, uint_fast8_t, bool ); +int_fast32_t f128M_to_i32( const float128_t *, uint_fast8_t, bool ); +int_fast64_t f128M_to_i64( const float128_t *, uint_fast8_t, bool ); +uint_fast32_t f128M_to_ui32_r_minMag( const float128_t *, bool ); +uint_fast64_t f128M_to_ui64_r_minMag( const float128_t *, bool ); +int_fast32_t f128M_to_i32_r_minMag( const float128_t *, bool ); +int_fast64_t f128M_to_i64_r_minMag( const float128_t *, bool ); +float16_t f128M_to_f16( const float128_t * ); +float32_t f128M_to_f32( const float128_t * ); +float64_t f128M_to_f64( const float128_t * ); +void f128M_to_extF80M( const float128_t *, extFloat80_t * ); +void f128M_roundToInt( const float128_t *, uint_fast8_t, bool, float128_t * ); +void f128M_add( const float128_t *, const float128_t *, float128_t * ); +void f128M_sub( const float128_t *, const float128_t *, float128_t * ); +void f128M_mul( const float128_t *, const float128_t *, float128_t * ); +void + f128M_mulAdd( + const float128_t *, const float128_t *, const float128_t *, float128_t * + ); +void f128M_div( const float128_t *, const float128_t *, float128_t * ); +void f128M_rem( const float128_t *, const float128_t *, float128_t * ); +void f128M_sqrt( const float128_t *, float128_t * ); +bool f128M_eq( const float128_t *, const float128_t * ); +bool f128M_le( const float128_t *, const float128_t * ); +bool f128M_lt( const float128_t *, const float128_t * ); +bool f128M_eq_signaling( const float128_t *, const float128_t * ); +bool f128M_le_quiet( const float128_t *, const float128_t * ); +bool f128M_lt_quiet( const float128_t *, const float128_t * ); +bool f128M_isSignalingNaN( const float128_t * ); + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/softfloat.mk.in b/vendor/riscv/riscv-isa-sim/softfloat/softfloat.mk.in new file mode 100644 index 0000000000..e7f4a3e415 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/softfloat.mk.in @@ -0,0 +1,239 @@ +softfloat_subproject_deps = + +softfloat_c_srcs = \ + f128_add.c \ + f128_classify.c \ + f128_div.c \ + f128_eq.c \ + f128_eq_signaling.c \ + f128_isSignalingNaN.c \ + f128_le.c \ + f128_le_quiet.c \ + f128_lt.c \ + f128_lt_quiet.c \ + f128_mulAdd.c \ + f128_mul.c \ + f128_rem.c \ + f128_roundToInt.c \ + f128_sqrt.c \ + f128_sub.c \ + f128_to_f16.c \ + f128_to_f32.c \ + f128_to_f64.c \ + f128_to_i32.c \ + f128_to_i32_r_minMag.c \ + f128_to_i64.c \ + f128_to_i64_r_minMag.c \ + f128_to_ui32.c \ + f128_to_ui32_r_minMag.c \ + f128_to_ui64.c \ + f128_to_ui64_r_minMag.c \ + f16_add.c \ + f16_classify.c \ + f16_div.c \ + f16_eq.c \ + f16_eq_signaling.c \ + f16_isSignalingNaN.c \ + f16_le.c \ + f16_le_quiet.c \ + f16_lt.c \ + f16_lt_quiet.c \ + f16_mulAdd.c \ + f16_mul.c \ + f16_rem.c \ + f16_roundToInt.c \ + f16_sqrt.c \ + f16_sub.c \ + f16_to_f128.c \ + f16_to_f32.c \ + f16_to_f64.c \ + f16_to_i8.c \ + f16_to_i16.c \ + f16_to_i32.c \ + f16_to_i32_r_minMag.c \ + f16_to_i64.c \ + f16_to_i64_r_minMag.c \ + f16_to_ui8.c \ + f16_to_ui16.c \ + f16_to_ui32.c \ + f16_to_ui32_r_minMag.c \ + f16_to_ui64.c \ + f16_to_ui64_r_minMag.c \ + f32_add.c \ + f32_classify.c \ + f32_div.c \ + f32_eq.c \ + f32_eq_signaling.c \ + f32_isSignalingNaN.c \ + f32_le.c \ + f32_le_quiet.c \ + f32_lt.c \ + f32_lt_quiet.c \ + f32_mulAdd.c \ + f32_mul.c \ + f32_rem.c \ + f32_roundToInt.c \ + f32_sqrt.c \ + f32_sub.c \ + f32_to_f128.c \ + f32_to_f16.c \ + f32_to_f64.c \ + f32_to_i16.c \ + f32_to_i32.c \ + f32_to_i32_r_minMag.c \ + f32_to_i64.c \ + f32_to_i64_r_minMag.c \ + f32_to_ui16.c \ + f32_to_ui32.c \ + f32_to_ui32_r_minMag.c \ + f32_to_ui64.c \ + f32_to_ui64_r_minMag.c \ + f64_add.c \ + f64_classify.c \ + f64_div.c \ + f64_eq.c \ + f64_eq_signaling.c \ + f64_isSignalingNaN.c \ + f64_le.c \ + f64_le_quiet.c \ + f64_lt.c \ + f64_lt_quiet.c \ + f64_mulAdd.c \ + f64_mul.c \ + f64_rem.c \ + f64_roundToInt.c \ + f64_sqrt.c \ + f64_sub.c \ + f64_to_f128.c \ + f64_to_f16.c \ + f64_to_f32.c \ + f64_to_i32.c \ + f64_to_i32_r_minMag.c \ + f64_to_i64.c \ + f64_to_i64_r_minMag.c \ + f64_to_ui32.c \ + f64_to_ui32_r_minMag.c \ + f64_to_ui64.c \ + f64_to_ui64_r_minMag.c \ + fall_maxmin.c \ + fall_reciprocal.c \ + i32_to_f128.c \ + i32_to_f16.c \ + i32_to_f32.c \ + i32_to_f64.c \ + i64_to_f128.c \ + i64_to_f16.c \ + i64_to_f32.c \ + i64_to_f64.c \ + s_add128.c \ + s_add256M.c \ + s_addCarryM.c \ + s_addComplCarryM.c \ + s_addMagsF128.c \ + s_addMagsF16.c \ + s_addMagsF32.c \ + s_addMagsF64.c \ + s_addM.c \ + s_approxRecip_1Ks.c \ + s_approxRecip32_1.c \ + s_approxRecipSqrt_1Ks.c \ + s_approxRecipSqrt32_1.c \ + s_commonNaNToF32UI.c \ + s_commonNaNToF64UI.c \ + s_compare128M.c \ + s_compare96M.c \ + s_countLeadingZeros16.c \ + s_countLeadingZeros32.c \ + s_countLeadingZeros64.c \ + s_countLeadingZeros8.c \ + s_eq128.c \ + s_f32UIToCommonNaN.c \ + s_f64UIToCommonNaN.c \ + s_le128.c \ + s_lt128.c \ + s_mul128By32.c \ + s_mul128MTo256M.c \ + s_mul128To256M.c \ + s_mul64ByShifted32To128.c \ + s_mul64To128.c \ + s_mul64To128M.c \ + s_mulAddF128.c \ + s_mulAddF16.c \ + s_mulAddF32.c \ + s_mulAddF64.c \ + s_negXM.c \ + s_normRoundPackToF128.c \ + s_normRoundPackToF16.c \ + s_normRoundPackToF32.c \ + s_normRoundPackToF64.c \ + s_normSubnormalF128Sig.c \ + s_normSubnormalF16Sig.c \ + s_normSubnormalF32Sig.c \ + s_normSubnormalF64Sig.c \ + softfloat_raiseFlags.c \ + softfloat_state.c \ + s_propagateNaNF16UI.c \ + s_propagateNaNF32UI.c \ + s_propagateNaNF64UI.c \ + s_propagateNaNF128UI.c \ + s_remStepMBy32.c \ + s_roundMToI64.c \ + s_roundMToUI64.c \ + s_roundPackMToI64.c \ + s_roundPackMToUI64.c \ + s_roundPackToF128.c \ + s_roundPackToF16.c \ + s_roundPackToF32.c \ + s_roundPackToF64.c \ + s_roundPackToI32.c \ + s_roundPackToI64.c \ + s_roundPackToUI32.c \ + s_roundPackToUI64.c \ + s_roundToI32.c \ + s_roundToI64.c \ + s_roundToUI32.c \ + s_roundToUI64.c \ + s_shiftRightJam128.c \ + s_shiftRightJam128Extra.c \ + s_shiftRightJam256M.c \ + s_shiftRightJam32.c \ + s_shiftRightJam64.c \ + s_shiftRightJam64Extra.c \ + s_shortShiftLeft128.c \ + s_shortShiftLeft64To96M.c \ + s_shortShiftRight128.c \ + s_shortShiftRightExtendM.c \ + s_shortShiftRightJam128.c \ + s_shortShiftRightJam128Extra.c \ + s_shortShiftRightJam64.c \ + s_shortShiftRightJam64Extra.c \ + s_shortShiftRightM.c \ + s_sub128.c \ + s_sub1XM.c \ + s_sub256M.c \ + s_subMagsF128.c \ + s_subMagsF16.c \ + s_subMagsF32.c \ + s_subMagsF64.c \ + s_subM.c \ + ui32_to_f128.c \ + ui32_to_f16.c \ + ui32_to_f32.c \ + ui32_to_f64.c \ + ui64_to_f128.c \ + ui64_to_f16.c \ + ui64_to_f32.c \ + ui64_to_f64.c \ + +softfloat_install_shared_lib = yes + +softfloat_test_srcs = + +softfloat_install_hdrs = \ + softfloat.h \ + softfloat_types.h \ + primitives.h \ + internals.h \ + platform.h \ + primitiveTypes.h \ + specialize.h \ diff --git a/vendor/riscv/riscv-isa-sim/softfloat/softfloat_raiseFlags.c b/vendor/riscv/riscv-isa-sim/softfloat/softfloat_raiseFlags.c new file mode 100644 index 0000000000..f2c25adeea --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/softfloat_raiseFlags.c @@ -0,0 +1,52 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include "platform.h" +#include "softfloat.h" + +/*---------------------------------------------------------------------------- +| Raises the exceptions specified by `flags'. Floating-point traps can be +| defined here if desired. It is currently not possible for such a trap +| to substitute a result value. If traps are not implemented, this routine +| should be simply `softfloat_exceptionFlags |= flags;'. +*----------------------------------------------------------------------------*/ +void softfloat_raiseFlags( uint_fast8_t flags ) +{ + + softfloat_exceptionFlags |= flags; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/softfloat_state.c b/vendor/riscv/riscv-isa-sim/softfloat/softfloat_state.c new file mode 100644 index 0000000000..a105e6f647 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/softfloat_state.c @@ -0,0 +1,52 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All Rights Reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +#ifndef THREAD_LOCAL +#define THREAD_LOCAL +#endif + +THREAD_LOCAL uint_fast8_t softfloat_roundingMode = softfloat_round_near_even; +THREAD_LOCAL uint_fast8_t softfloat_detectTininess = init_detectTininess; +THREAD_LOCAL uint_fast8_t softfloat_exceptionFlags = 0; + +THREAD_LOCAL uint_fast8_t extF80_roundingPrecision = 80; + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/softfloat_types.h b/vendor/riscv/riscv-isa-sim/softfloat/softfloat_types.h new file mode 100644 index 0000000000..af1888f9b9 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/softfloat_types.h @@ -0,0 +1,81 @@ + +/*============================================================================ + +This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#ifndef softfloat_types_h +#define softfloat_types_h 1 + +#include <stdint.h> + +/*---------------------------------------------------------------------------- +| Types used to pass 16-bit, 32-bit, 64-bit, and 128-bit floating-point +| arguments and results to/from functions. These types must be exactly +| 16 bits, 32 bits, 64 bits, and 128 bits in size, respectively. Where a +| platform has "native" support for IEEE-Standard floating-point formats, +| the types below may, if desired, be defined as aliases for the native types +| (typically 'float' and 'double', and possibly 'long double'). +*----------------------------------------------------------------------------*/ +typedef struct { uint16_t v; } float16_t; +typedef struct { uint32_t v; } float32_t; +typedef struct { uint64_t v; } float64_t; +typedef struct { uint64_t v[2]; } float128_t; + +/*---------------------------------------------------------------------------- +| The format of an 80-bit extended floating-point number in memory. This +| structure must contain a 16-bit field named 'signExp' and a 64-bit field +| named 'signif'. +*----------------------------------------------------------------------------*/ +#ifdef LITTLEENDIAN +struct extFloat80M { uint64_t signif; uint16_t signExp; }; +#else +struct extFloat80M { uint16_t signExp; uint64_t signif; }; +#endif + +/*---------------------------------------------------------------------------- +| The type used to pass 80-bit extended floating-point arguments and +| results to/from functions. This type must have size identical to +| 'struct extFloat80M'. Type 'extFloat80_t' can be defined as an alias for +| 'struct extFloat80M'. Alternatively, if a platform has "native" support +| for IEEE-Standard 80-bit extended floating-point, it may be possible, +| if desired, to define 'extFloat80_t' as an alias for the native type +| (presumably either 'long double' or a nonstandard compiler-intrinsic type). +| In that case, the 'signif' and 'signExp' fields of 'struct extFloat80M' +| must align exactly with the locations in memory of the sign, exponent, and +| significand of the native type. +*----------------------------------------------------------------------------*/ +typedef struct extFloat80M extFloat80_t; + +#endif + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/specialize.h b/vendor/riscv/riscv-isa-sim/softfloat/specialize.h new file mode 100644 index 0000000000..19504b6b62 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/specialize.h @@ -0,0 +1,435 @@ + +/*============================================================================ + +This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#ifndef specialize_h +#define specialize_h 1 + +#include <stdbool.h> +#include <stdint.h> +#include "primitiveTypes.h" +#include "softfloat.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/*---------------------------------------------------------------------------- +| Default value for `softfloat_detectTininess'. +*----------------------------------------------------------------------------*/ +#define init_detectTininess softfloat_tininess_afterRounding + +/*---------------------------------------------------------------------------- +| The values to return on conversions to 32-bit integer formats that raise an +| invalid exception. +*----------------------------------------------------------------------------*/ +#define ui8_fromPosOverflow 0xFF +#define ui8_fromNegOverflow 0 +#define ui8_fromNaN 0xFF +#define i8_fromPosOverflow 0x7F +#define i8_fromNegOverflow (-0x7F - 1) +#define i8_fromNaN 0x7F + +#define ui16_fromPosOverflow 0xFFFF +#define ui16_fromNegOverflow 0 +#define ui16_fromNaN 0xFFFF +#define i16_fromPosOverflow 0x7FFF +#define i16_fromNegOverflow (-0x7FFF - 1) +#define i16_fromNaN 0x7FFF + +#define ui32_fromPosOverflow 0xFFFFFFFF +#define ui32_fromNegOverflow 0 +#define ui32_fromNaN 0xFFFFFFFF +#define i32_fromPosOverflow 0x7FFFFFFF +#define i32_fromNegOverflow (-0x7FFFFFFF - 1) +#define i32_fromNaN 0x7FFFFFFF + +/*---------------------------------------------------------------------------- +| The values to return on conversions to 64-bit integer formats that raise an +| invalid exception. +*----------------------------------------------------------------------------*/ +#define ui64_fromPosOverflow UINT64_C( 0xFFFFFFFFFFFFFFFF ) +#define ui64_fromNegOverflow 0 +#define ui64_fromNaN UINT64_C( 0xFFFFFFFFFFFFFFFF ) +#define i64_fromPosOverflow UINT64_C( 0x7FFFFFFFFFFFFFFF ) +#define i64_fromNegOverflow (-UINT64_C( 0x7FFFFFFFFFFFFFFF ) - 1) +#define i64_fromNaN UINT64_C( 0x7FFFFFFFFFFFFFFF ) + +/*---------------------------------------------------------------------------- +| "Common NaN" structure, used to transfer NaN representations from one format +| to another. +*----------------------------------------------------------------------------*/ +struct commonNaN { char _unused; }; + +/*---------------------------------------------------------------------------- +| The bit pattern for a default generated 16-bit floating-point NaN. +*----------------------------------------------------------------------------*/ +#define defaultNaNF16UI 0x7E00 + +/*---------------------------------------------------------------------------- +| Returns true when 16-bit unsigned integer `uiA' has the bit pattern of a +| 16-bit floating-point signaling NaN. +| Note: This macro evaluates its argument more than once. +*----------------------------------------------------------------------------*/ +#define softfloat_isSigNaNF16UI( uiA ) ((((uiA) & 0x7E00) == 0x7C00) && ((uiA) & 0x01FF)) + +/*---------------------------------------------------------------------------- +| Assuming `uiA' has the bit pattern of a 16-bit floating-point NaN, converts +| this NaN to the common NaN form, and stores the resulting common NaN at the +| location pointed to by `zPtr'. If the NaN is a signaling NaN, the invalid +| exception is raised. +*----------------------------------------------------------------------------*/ +#define softfloat_f16UIToCommonNaN( uiA, zPtr ) if ( ! ((uiA) & 0x0200) ) (void) (zPtr), softfloat_raiseFlags( softfloat_flag_invalid ) + +/*---------------------------------------------------------------------------- +| Converts the common NaN pointed to by `aPtr' into a 16-bit floating-point +| NaN, and returns the bit pattern of this value as an unsigned integer. +*----------------------------------------------------------------------------*/ +#define softfloat_commonNaNToF16UI( aPtr ) ((uint_fast16_t) defaultNaNF16UI) + +/*---------------------------------------------------------------------------- +| Interpreting `uiA' and `uiB' as the bit patterns of two 16-bit floating- +| point values, at least one of which is a NaN, returns the bit pattern of +| the combined NaN result. If either `uiA' or `uiB' has the pattern of a +| signaling NaN, the invalid exception is raised. +*----------------------------------------------------------------------------*/ +uint_fast16_t + softfloat_propagateNaNF16UI( uint_fast16_t uiA, uint_fast16_t uiB ); + +/*---------------------------------------------------------------------------- +| The bit pattern for a default generated 32-bit floating-point NaN. +*----------------------------------------------------------------------------*/ +#define defaultNaNF32UI 0x7FC00000 + +/*---------------------------------------------------------------------------- +| Returns true when 32-bit unsigned integer `uiA' has the bit pattern of a +| 32-bit floating-point signaling NaN. +| Note: This macro evaluates its argument more than once. +*----------------------------------------------------------------------------*/ +#define softfloat_isSigNaNF32UI( uiA ) ((((uiA) & 0x7FC00000) == 0x7F800000) && ((uiA) & 0x003FFFFF)) + +/*---------------------------------------------------------------------------- +| Assuming `uiA' has the bit pattern of a 32-bit floating-point NaN, converts +| this NaN to the common NaN form, and stores the resulting common NaN at the +| location pointed to by `zPtr'. If the NaN is a signaling NaN, the invalid +| exception is raised. +*----------------------------------------------------------------------------*/ +#define softfloat_f32UIToCommonNaN( uiA, zPtr ) if ( ! ((uiA) & 0x00400000) ) (void) (zPtr), softfloat_raiseFlags( softfloat_flag_invalid ) + +/*---------------------------------------------------------------------------- +| Converts the common NaN pointed to by `aPtr' into a 32-bit floating-point +| NaN, and returns the bit pattern of this value as an unsigned integer. +*----------------------------------------------------------------------------*/ +#define softfloat_commonNaNToF32UI( aPtr ) ((uint_fast32_t) defaultNaNF32UI) + +/*---------------------------------------------------------------------------- +| Interpreting `uiA' and `uiB' as the bit patterns of two 32-bit floating- +| point values, at least one of which is a NaN, returns the bit pattern of +| the combined NaN result. If either `uiA' or `uiB' has the pattern of a +| signaling NaN, the invalid exception is raised. +*----------------------------------------------------------------------------*/ +uint_fast32_t + softfloat_propagateNaNF32UI( uint_fast32_t uiA, uint_fast32_t uiB ); + +/*---------------------------------------------------------------------------- +| The bit pattern for a default generated 64-bit floating-point NaN. +*----------------------------------------------------------------------------*/ +#define defaultNaNF64UI UINT64_C( 0x7FF8000000000000 ) + +/*---------------------------------------------------------------------------- +| Returns true when 64-bit unsigned integer `uiA' has the bit pattern of a +| 64-bit floating-point signaling NaN. +| Note: This macro evaluates its argument more than once. +*----------------------------------------------------------------------------*/ +#define softfloat_isSigNaNF64UI( uiA ) ((((uiA) & UINT64_C( 0x7FF8000000000000 )) == UINT64_C( 0x7FF0000000000000 )) && ((uiA) & UINT64_C( 0x0007FFFFFFFFFFFF ))) + +/*---------------------------------------------------------------------------- +| Assuming `uiA' has the bit pattern of a 64-bit floating-point NaN, converts +| this NaN to the common NaN form, and stores the resulting common NaN at the +| location pointed to by `zPtr'. If the NaN is a signaling NaN, the invalid +| exception is raised. +*----------------------------------------------------------------------------*/ +#define softfloat_f64UIToCommonNaN( uiA, zPtr ) if ( ! ((uiA) & UINT64_C( 0x0008000000000000 )) ) (void) (zPtr), softfloat_raiseFlags( softfloat_flag_invalid ) + +/*---------------------------------------------------------------------------- +| Converts the common NaN pointed to by `aPtr' into a 64-bit floating-point +| NaN, and returns the bit pattern of this value as an unsigned integer. +*----------------------------------------------------------------------------*/ +#define softfloat_commonNaNToF64UI( aPtr ) ((uint_fast64_t) defaultNaNF64UI) + +/*---------------------------------------------------------------------------- +| Interpreting `uiA' and `uiB' as the bit patterns of two 64-bit floating- +| point values, at least one of which is a NaN, returns the bit pattern of +| the combined NaN result. If either `uiA' or `uiB' has the pattern of a +| signaling NaN, the invalid exception is raised. +*----------------------------------------------------------------------------*/ +uint_fast64_t + softfloat_propagateNaNF64UI( uint_fast64_t uiA, uint_fast64_t uiB ); + +/*---------------------------------------------------------------------------- +| The bit pattern for a default generated 80-bit extended floating-point NaN. +*----------------------------------------------------------------------------*/ +#define defaultNaNExtF80UI64 0x7FFF +#define defaultNaNExtF80UI0 UINT64_C( 0xC000000000000000 ) + +/*---------------------------------------------------------------------------- +| Returns true when the 80-bit unsigned integer formed from concatenating +| 16-bit `uiA64' and 64-bit `uiA0' has the bit pattern of an 80-bit extended +| floating-point signaling NaN. +| Note: This macro evaluates its arguments more than once. +*----------------------------------------------------------------------------*/ +#define softfloat_isSigNaNExtF80UI( uiA64, uiA0 ) ((((uiA64) & 0x7FFF) == 0x7FFF) && ! ((uiA0) & UINT64_C( 0x4000000000000000 )) && ((uiA0) & UINT64_C( 0x3FFFFFFFFFFFFFFF ))) + +#ifdef SOFTFLOAT_FAST_INT64 + +/*---------------------------------------------------------------------------- +| The following functions are needed only when `SOFTFLOAT_FAST_INT64' is +| defined. +*----------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------- +| Assuming the unsigned integer formed from concatenating `uiA64' and `uiA0' +| has the bit pattern of an 80-bit extended floating-point NaN, converts +| this NaN to the common NaN form, and stores the resulting common NaN at the +| location pointed to by `zPtr'. If the NaN is a signaling NaN, the invalid +| exception is raised. +*----------------------------------------------------------------------------*/ +#define softfloat_extF80UIToCommonNaN( uiA64, uiA0, zPtr ) if ( ! ((uiA0) & UINT64_C( 0x4000000000000000 )) ) softfloat_raiseFlags( softfloat_flag_invalid ) + +/*---------------------------------------------------------------------------- +| Converts the common NaN pointed to by `aPtr' into an 80-bit extended +| floating-point NaN, and returns the bit pattern of this value as an unsigned +| integer. +*----------------------------------------------------------------------------*/ +#if defined INLINE && ! defined softfloat_commonNaNToExtF80UI +INLINE +struct uint128 softfloat_commonNaNToExtF80UI( const struct commonNaN *aPtr ) +{ + struct uint128 uiZ; + + (void) aPtr; + + uiZ.v64 = defaultNaNExtF80UI64; + uiZ.v0 = defaultNaNExtF80UI0; + return uiZ; +} +#else +struct uint128 softfloat_commonNaNToExtF80UI( const struct commonNaN *aPtr ); +#endif + +/*---------------------------------------------------------------------------- +| Interpreting the unsigned integer formed from concatenating `uiA64' and +| `uiA0' as an 80-bit extended floating-point value, and likewise interpreting +| the unsigned integer formed from concatenating `uiB64' and `uiB0' as another +| 80-bit extended floating-point value, and assuming at least on of these +| floating-point values is a NaN, returns the bit pattern of the combined NaN +| result. If either original floating-point value is a signaling NaN, the +| invalid exception is raised. +*----------------------------------------------------------------------------*/ +struct uint128 + softfloat_propagateNaNExtF80UI( + uint_fast16_t uiA64, + uint_fast64_t uiA0, + uint_fast16_t uiB64, + uint_fast64_t uiB0 + ); + +/*---------------------------------------------------------------------------- +| The bit pattern for a default generated 128-bit floating-point NaN. +*----------------------------------------------------------------------------*/ +#define defaultNaNF128UI64 UINT64_C( 0x7FFF800000000000 ) +#define defaultNaNF128UI0 UINT64_C( 0 ) + +/*---------------------------------------------------------------------------- +| Returns true when the 128-bit unsigned integer formed from concatenating +| 64-bit `uiA64' and 64-bit `uiA0' has the bit pattern of a 128-bit floating- +| point signaling NaN. +| Note: This macro evaluates its arguments more than once. +*----------------------------------------------------------------------------*/ +#define softfloat_isSigNaNF128UI( uiA64, uiA0 ) ((((uiA64) & UINT64_C( 0x7FFF800000000000 )) == UINT64_C( 0x7FFF000000000000 )) && ((uiA0) || ((uiA64) & UINT64_C( 0x00007FFFFFFFFFFF )))) + +/*---------------------------------------------------------------------------- +| Assuming the unsigned integer formed from concatenating `uiA64' and `uiA0' +| has the bit pattern of a 128-bit floating-point NaN, converts this NaN to +| the common NaN form, and stores the resulting common NaN at the location +| pointed to by `zPtr'. If the NaN is a signaling NaN, the invalid exception +| is raised. +*----------------------------------------------------------------------------*/ +#define softfloat_f128UIToCommonNaN( uiA64, uiA0, zPtr ) if ( ! ((uiA64) & UINT64_C( 0x0000800000000000 )) ) (void) (zPtr), softfloat_raiseFlags( softfloat_flag_invalid ) + +/*---------------------------------------------------------------------------- +| Converts the common NaN pointed to by `aPtr' into a 128-bit floating-point +| NaN, and returns the bit pattern of this value as an unsigned integer. +*----------------------------------------------------------------------------*/ +#if defined INLINE && ! defined softfloat_commonNaNToF128UI +INLINE +struct uint128 softfloat_commonNaNToF128UI( const struct commonNaN *aPtr ) +{ + struct uint128 uiZ; + + (void) aPtr; + + uiZ.v64 = defaultNaNF128UI64; + uiZ.v0 = defaultNaNF128UI0; + return uiZ; +} +#else +struct uint128 softfloat_commonNaNToF128UI( const struct commonNaN * ); +#endif + +/*---------------------------------------------------------------------------- +| Interpreting the unsigned integer formed from concatenating `uiA64' and +| `uiA0' as a 128-bit floating-point value, and likewise interpreting the +| unsigned integer formed from concatenating `uiB64' and `uiB0' as another +| 128-bit floating-point value, and assuming at least on of these floating- +| point values is a NaN, returns the bit pattern of the combined NaN result. +| If either original floating-point value is a signaling NaN, the invalid +| exception is raised. +*----------------------------------------------------------------------------*/ +struct uint128 + softfloat_propagateNaNF128UI( + uint_fast64_t uiA64, + uint_fast64_t uiA0, + uint_fast64_t uiB64, + uint_fast64_t uiB0 + ); + +#else + +/*---------------------------------------------------------------------------- +| The following functions are needed only when `SOFTFLOAT_FAST_INT64' is not +| defined. +*----------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------- +| Assuming the 80-bit extended floating-point value pointed to by `aSPtr' is +| a NaN, converts this NaN to the common NaN form, and stores the resulting +| common NaN at the location pointed to by `zPtr'. If the NaN is a signaling +| NaN, the invalid exception is raised. +*----------------------------------------------------------------------------*/ +#define softfloat_extF80MToCommonNaN( aSPtr, zPtr ) if ( ! ((aSPtr)->signif & UINT64_C( 0x4000000000000000 )) ) softfloat_raiseFlags( softfloat_flag_invalid ) + +/*---------------------------------------------------------------------------- +| Converts the common NaN pointed to by `aPtr' into an 80-bit extended +| floating-point NaN, and stores this NaN at the location pointed to by +| `zSPtr'. +*----------------------------------------------------------------------------*/ +#if defined INLINE && ! defined softfloat_commonNaNToExtF80M +INLINE +void + softfloat_commonNaNToExtF80M( + const struct commonNaN *aPtr, struct extFloat80M *zSPtr ) +{ + zSPtr->signExp = defaultNaNExtF80UI64; + zSPtr->signif = defaultNaNExtF80UI0; +} +#else +void + softfloat_commonNaNToExtF80M( + const struct commonNaN *aPtr, struct extFloat80M *zSPtr ); +#endif + +/*---------------------------------------------------------------------------- +| Assuming at least one of the two 80-bit extended floating-point values +| pointed to by `aSPtr' and `bSPtr' is a NaN, stores the combined NaN result +| at the location pointed to by `zSPtr'. If either original floating-point +| value is a signaling NaN, the invalid exception is raised. +*----------------------------------------------------------------------------*/ +void + softfloat_propagateNaNExtF80M( + const struct extFloat80M *aSPtr, + const struct extFloat80M *bSPtr, + struct extFloat80M *zSPtr + ); + +/*---------------------------------------------------------------------------- +| The bit pattern for a default generated 128-bit floating-point NaN. +*----------------------------------------------------------------------------*/ +#define defaultNaNF128UI96 0x7FFF8000 +#define defaultNaNF128UI64 0 +#define defaultNaNF128UI32 0 +#define defaultNaNF128UI0 0 + +/*---------------------------------------------------------------------------- +| Assuming the 128-bit floating-point value pointed to by `aWPtr' is a NaN, +| converts this NaN to the common NaN form, and stores the resulting common +| NaN at the location pointed to by `zPtr'. If the NaN is a signaling NaN, +| the invalid exception is raised. Argument `aWPtr' points to an array of +| four 32-bit elements that concatenate in the platform's normal endian order +| to form a 128-bit floating-point value. +*----------------------------------------------------------------------------*/ +#define softfloat_f128MToCommonNaN( aWPtr, zPtr ) if ( ! ((aWPtr)[indexWordHi( 4 )] & UINT64_C( 0x0000800000000000 )) ) softfloat_raiseFlags( softfloat_flag_invalid ) + +/*---------------------------------------------------------------------------- +| Converts the common NaN pointed to by `aPtr' into a 128-bit floating-point +| NaN, and stores this NaN at the location pointed to by `zWPtr'. Argument +| `zWPtr' points to an array of four 32-bit elements that concatenate in the +| platform's normal endian order to form a 128-bit floating-point value. +*----------------------------------------------------------------------------*/ +#if defined INLINE && ! defined softfloat_commonNaNToF128M +INLINE +void + softfloat_commonNaNToF128M( const struct commonNaN *aPtr, uint32_t *zWPtr ) +{ + zWPtr[indexWord( 4, 3 )] = defaultNaNF128UI96; + zWPtr[indexWord( 4, 2 )] = defaultNaNF128UI64; + zWPtr[indexWord( 4, 1 )] = defaultNaNF128UI32; + zWPtr[indexWord( 4, 0 )] = defaultNaNF128UI0; +} +#else +void + softfloat_commonNaNToF128M( const struct commonNaN *aPtr, uint32_t *zWPtr ); +#endif + +/*---------------------------------------------------------------------------- +| Assuming at least one of the two 128-bit floating-point values pointed to by +| `aWPtr' and `bWPtr' is a NaN, stores the combined NaN result at the location +| pointed to by `zWPtr'. If either original floating-point value is a +| signaling NaN, the invalid exception is raised. Each of `aWPtr', `bWPtr', +| and `zWPtr' points to an array of four 32-bit elements that concatenate in +| the platform's normal endian order to form a 128-bit floating-point value. +*----------------------------------------------------------------------------*/ +void + softfloat_propagateNaNF128M( + const uint32_t *aWPtr, const uint32_t *bWPtr, uint32_t *zWPtr ); + +#endif + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/ui32_to_f128.c b/vendor/riscv/riscv-isa-sim/softfloat/ui32_to_f128.c new file mode 100644 index 0000000000..78d3eb64c6 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/ui32_to_f128.c @@ -0,0 +1,60 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All Rights Reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "softfloat.h" + +float128_t ui32_to_f128( uint32_t a ) +{ + uint_fast64_t uiZ64; + int_fast8_t shiftDist; + union ui128_f128 uZ; + + uiZ64 = 0; + if ( a ) { + shiftDist = softfloat_countLeadingZeros32( a ) + 17; + uiZ64 = + packToF128UI64( + 0, 0x402E - shiftDist, (uint_fast64_t) a<<shiftDist ); + } + uZ.ui.v64 = uiZ64; + uZ.ui.v0 = 0; + return uZ.f; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/ui32_to_f16.c b/vendor/riscv/riscv-isa-sim/softfloat/ui32_to_f16.c new file mode 100644 index 0000000000..09dcc8c3fa --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/ui32_to_f16.c @@ -0,0 +1,65 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All Rights Reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "softfloat.h" + +float16_t ui32_to_f16( uint32_t a ) +{ + int_fast8_t shiftDist; + union ui16_f16 u; + uint_fast16_t sig; + + shiftDist = softfloat_countLeadingZeros32( a ) - 21; + if ( 0 <= shiftDist ) { + u.ui = + a ? packToF16UI( + 0, 0x18 - shiftDist, (uint_fast16_t) a<<shiftDist ) + : 0; + return u.f; + } else { + shiftDist += 4; + sig = + (shiftDist < 0) + ? a>>(-shiftDist) | ((uint32_t) (a<<(shiftDist & 31)) != 0) + : (uint_fast16_t) a<<shiftDist; + return softfloat_roundPackToF16( 0, 0x1C - shiftDist, sig ); + } + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/ui32_to_f32.c b/vendor/riscv/riscv-isa-sim/softfloat/ui32_to_f32.c new file mode 100644 index 0000000000..7e5ece68ae --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/ui32_to_f32.c @@ -0,0 +1,57 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. +All Rights Reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "softfloat.h" + +float32_t ui32_to_f32( uint32_t a ) +{ + union ui32_f32 uZ; + + if ( ! a ) { + uZ.ui = 0; + return uZ.f; + } + if ( a & 0x80000000 ) { + return softfloat_roundPackToF32( 0, 0x9D, a>>1 | (a & 1) ); + } else { + return softfloat_normRoundPackToF32( 0, 0x9C, a ); + } + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/ui32_to_f64.c b/vendor/riscv/riscv-isa-sim/softfloat/ui32_to_f64.c new file mode 100644 index 0000000000..5e5f843aff --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/ui32_to_f64.c @@ -0,0 +1,59 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All Rights Reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "softfloat.h" + +float64_t ui32_to_f64( uint32_t a ) +{ + uint_fast64_t uiZ; + int_fast8_t shiftDist; + union ui64_f64 uZ; + + if ( ! a ) { + uiZ = 0; + } else { + shiftDist = softfloat_countLeadingZeros32( a ) + 21; + uiZ = + packToF64UI( 0, 0x432 - shiftDist, (uint_fast64_t) a<<shiftDist ); + } + uZ.ui = uiZ; + return uZ.f; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/ui64_to_f128.c b/vendor/riscv/riscv-isa-sim/softfloat/ui64_to_f128.c new file mode 100644 index 0000000000..0124bc5a60 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/ui64_to_f128.c @@ -0,0 +1,68 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All Rights Reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "softfloat.h" + +float128_t ui64_to_f128( uint64_t a ) +{ + uint_fast64_t uiZ64, uiZ0; + int_fast8_t shiftDist; + struct uint128 zSig; + union ui128_f128 uZ; + + if ( ! a ) { + uiZ64 = 0; + uiZ0 = 0; + } else { + shiftDist = softfloat_countLeadingZeros64( a ) + 49; + if ( 64 <= shiftDist ) { + zSig.v64 = a<<(shiftDist - 64); + zSig.v0 = 0; + } else { + zSig = softfloat_shortShiftLeft128( 0, a, shiftDist ); + } + uiZ64 = packToF128UI64( 0, 0x406E - shiftDist, zSig.v64 ); + uiZ0 = zSig.v0; + } + uZ.ui.v64 = uiZ64; + uZ.ui.v0 = uiZ0; + return uZ.f; + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/ui64_to_f16.c b/vendor/riscv/riscv-isa-sim/softfloat/ui64_to_f16.c new file mode 100644 index 0000000000..ecca02bc45 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/ui64_to_f16.c @@ -0,0 +1,64 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All Rights Reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "softfloat.h" + +float16_t ui64_to_f16( uint64_t a ) +{ + int_fast8_t shiftDist; + union ui16_f16 u; + uint_fast16_t sig; + + shiftDist = softfloat_countLeadingZeros64( a ) - 53; + if ( 0 <= shiftDist ) { + u.ui = + a ? packToF16UI( + 0, 0x18 - shiftDist, (uint_fast16_t) a<<shiftDist ) + : 0; + return u.f; + } else { + shiftDist += 4; + sig = + (shiftDist < 0) ? softfloat_shortShiftRightJam64( a, -shiftDist ) + : (uint_fast16_t) a<<shiftDist; + return softfloat_roundPackToF16( 0, 0x1C - shiftDist, sig ); + } + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/ui64_to_f32.c b/vendor/riscv/riscv-isa-sim/softfloat/ui64_to_f32.c new file mode 100644 index 0000000000..2d946c2fe4 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/ui64_to_f32.c @@ -0,0 +1,64 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of +California. All Rights Reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "softfloat.h" + +float32_t ui64_to_f32( uint64_t a ) +{ + int_fast8_t shiftDist; + union ui32_f32 u; + uint_fast32_t sig; + + shiftDist = softfloat_countLeadingZeros64( a ) - 40; + if ( 0 <= shiftDist ) { + u.ui = + a ? packToF32UI( + 0, 0x95 - shiftDist, (uint_fast32_t) a<<shiftDist ) + : 0; + return u.f; + } else { + shiftDist += 7; + sig = + (shiftDist < 0) ? softfloat_shortShiftRightJam64( a, -shiftDist ) + : (uint_fast32_t) a<<shiftDist; + return softfloat_roundPackToF32( 0, 0x9C - shiftDist, sig ); + } + +} + diff --git a/vendor/riscv/riscv-isa-sim/softfloat/ui64_to_f64.c b/vendor/riscv/riscv-isa-sim/softfloat/ui64_to_f64.c new file mode 100644 index 0000000000..57102a74b6 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/softfloat/ui64_to_f64.c @@ -0,0 +1,59 @@ + +/*============================================================================ + +This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3d, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. +All Rights Reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#include <stdint.h> +#include "platform.h" +#include "internals.h" +#include "softfloat.h" + +float64_t ui64_to_f64( uint64_t a ) +{ + union ui64_f64 uZ; + + if ( ! a ) { + uZ.ui = 0; + return uZ.f; + } + if ( a & UINT64_C( 0x8000000000000000 ) ) { + return + softfloat_roundPackToF64( + 0, 0x43D, softfloat_shortShiftRightJam64( a, 1 ) ); + } else { + return softfloat_normRoundPackToF64( 0, 0x43C, a ); + } + +} + diff --git a/vendor/riscv/riscv-isa-sim/spike_dasm/spike-dasm.cc b/vendor/riscv/riscv-isa-sim/spike_dasm/spike-dasm.cc new file mode 100644 index 0000000000..3e42df5b44 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/spike_dasm/spike-dasm.cc @@ -0,0 +1,67 @@ +// See LICENSE for license details. + +// This little program finds occurrences of strings like +// DASM(ffabc013) +// in its input, then replaces them with the disassembly +// enclosed hexadecimal number, interpreted as a RISC-V +// instruction. + +#include "config.h" +#include "disasm.h" +#include "extension.h" +#include <iostream> +#include <string> +#include <cstdint> +#include <fesvr/option_parser.h> +using namespace std; + +int main(int UNUSED argc, char** argv) +{ + string s; + const char* isa = DEFAULT_ISA; + + std::function<extension_t*()> extension; + option_parser_t parser; +#ifdef HAVE_DLOPEN + parser.option(0, "extension", 1, [&](const char* s){extension = find_extension(s);}); +#endif + parser.option(0, "isa", 1, [&](const char* s){isa = s;}); + parser.parse(argv); + + isa_parser_t isa_parser(isa, DEFAULT_PRIV); + disassembler_t* disassembler = new disassembler_t(&isa_parser); + if (extension) { + for (auto disasm_insn : extension()->get_disasms()) { + disassembler->add_insn(disasm_insn); + } + } + + while (getline(cin, s)) + { + for (size_t pos = 0; (pos = s.find("DASM(", pos)) != string::npos; ) + { + size_t start = pos; + + pos += strlen("DASM("); + + if (s[pos] == '0' && (s[pos+1] == 'x' || s[pos+1] == 'X')) + pos += 2; + + if (!isxdigit(s[pos])) + continue; + + char* endp; + insn_bits_t bits = strtoull(&s[pos], &endp, 16); + if (*endp != ')') + continue; + + string dis = disassembler->disassemble(bits); + s = s.substr(0, start) + dis + s.substr(endp - &s[0] + 1); + pos = start + dis.length(); + } + + cout << s << '\n'; + } + + return 0; +} diff --git a/vendor/riscv/riscv-isa-sim/spike_dasm/spike_dasm.ac b/vendor/riscv/riscv-isa-sim/spike_dasm/spike_dasm.ac new file mode 100644 index 0000000000..e69de29bb2 diff --git a/vendor/riscv/riscv-isa-sim/spike_dasm/spike_dasm.mk.in b/vendor/riscv/riscv-isa-sim/spike_dasm/spike_dasm.mk.in new file mode 100644 index 0000000000..1003a79930 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/spike_dasm/spike_dasm.mk.in @@ -0,0 +1,10 @@ +spike_dasm_subproject_deps = \ + disasm \ + softfloat \ + riscv \ + +spike_dasm_srcs = \ + spike_dasm_option_parser.cc \ + +spike_dasm_install_prog_srcs = \ + spike-dasm.cc \ diff --git a/vendor/riscv/riscv-isa-sim/spike_dasm/spike_dasm_option_parser.cc b/vendor/riscv/riscv-isa-sim/spike_dasm/spike_dasm_option_parser.cc new file mode 100644 index 0000000000..72daec40ef --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/spike_dasm/spike_dasm_option_parser.cc @@ -0,0 +1,51 @@ +// See LICENSE for license details. + +#include "option_parser.h" +#include <cstdio> +#include <cstdlib> +#include <cstring> +#include <cassert> + +void option_parser_t::option(char c, const char* s, int arg, std::function<void(const char*)> action) +{ + opts.push_back(option_t(c, s, arg, action)); +} + +const char* const* option_parser_t::parse(const char* const* argv0) +{ + assert(argv0); + const char* const* argv = argv0 + 1; + for (const char* opt; (opt = *argv) != NULL && opt[0] == '-'; argv++) + { + bool found = false; + for (auto it = opts.begin(); !found && it != opts.end(); it++) + { + size_t slen = it->str ? strlen(it->str) : 0; + bool chr_match = opt[1] != '-' && it->chr && opt[1] == it->chr; + bool str_match = opt[1] == '-' && slen && strncmp(opt+2, it->str, slen) == 0; + if (chr_match || (str_match && (opt[2+slen] == '=' || opt[2+slen] == '\0'))) + { + const char* optarg = + chr_match ? (opt[2] ? &opt[2] : NULL) : + opt[2+slen] ? &opt[3+slen] : + it->arg ? *(++argv) : NULL; + if (optarg && !it->arg) + error("no argument allowed for option", *argv0, opt); + if (!optarg && it->arg) + error("argument required for option", *argv0, opt); + it->func(optarg); + found = true; + } + } + if (!found) + error("unrecognized option", *argv0, opt); + } + return argv; +} + +void option_parser_t::error(const char* msg, const char* argv0, const char* arg) +{ + fprintf(stderr, "%s: %s %s\n", argv0, msg, arg ? arg : ""); + if (helpmsg) helpmsg(); + exit(1); +} diff --git a/vendor/riscv/riscv-isa-sim/spike_main/spike-log-parser.cc b/vendor/riscv/riscv-isa-sim/spike_main/spike-log-parser.cc new file mode 100644 index 0000000000..9bea5c51c3 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/spike_main/spike-log-parser.cc @@ -0,0 +1,75 @@ +// See LICENSE for license details. + +// This little program finds occurrences of strings like +// core 0: 0x000000008000c36c (0xfe843783) ld a5, -24(s0) +// in its inputs, then output the RISC-V instruction with the disassembly +// enclosed hexadecimal number. + +#include "config.h" +#include <iostream> +#include <string> +#include <cstdint> +#include <regex> +#include "fesvr/option_parser.h" + +#include "disasm.h" +#include "extension.h" + +using namespace std; + +int main(int UNUSED argc, char** argv) +{ + string s; + const char* isa_string = DEFAULT_ISA; + + std::function<extension_t*()> extension; + option_parser_t parser; + parser.option(0, "extension", 1, [&](const char* s){extension = find_extension(s);}); + parser.option(0, "isa", 1, [&](const char* s){isa_string = s;}); + parser.parse(argv); + + cfg_t cfg(/*default_initrd_bounds=*/std::make_pair((reg_t)0, (reg_t)0), + /*default_bootargs=*/nullptr, + /*default_isa=*/DEFAULT_ISA, + /*default_priv=*/DEFAULT_PRIV, + /*default_varch=*/DEFAULT_VARCH, + /*default_misaligned=*/false, + /*default_endianness*/endianness_little, + /*default_pmpregions=*/16, + /*default_mem_layout=*/std::vector<mem_cfg_t>(), + /*default_hartids=*/std::vector<size_t>(), + /*default_real_time_clint=*/false, + /*default_trigger_count=*/4); + + isa_parser_t isa(isa_string, DEFAULT_PRIV); + processor_t p(&isa, &cfg, 0, 0, false, nullptr, cerr); + if (extension) { + p.register_extension(extension()); + } + + std::regex reg("^core\\s+\\d+:\\s+0x[0-9a-f]+\\s+\\(0x([0-9a-f]+)\\)", std::regex_constants::icase); + std::smatch m; + std::ssub_match sm ; + + while (getline(cin,s)){ + if (regex_search(s, m, reg)){ + // the opcode string + string op = m[1].str(); + uint32_t bit_num = op.size() * 4; + uint64_t opcode = strtoull(op.c_str(), nullptr, 16); + + if (bit_num<64){ + opcode = opcode << (64-bit_num) >> (64-bit_num); + } + + const disasm_insn_t* disasm = p.get_disassembler()->lookup(opcode); + if (disasm) { + cout << disasm->get_name() << '\n'; + } else { + cout << "unknown_op\n"; + } + } + } + + return 0; +} diff --git a/vendor/riscv/riscv-isa-sim/spike_main/spike.cc b/vendor/riscv/riscv-isa-sim/spike_main/spike.cc new file mode 100644 index 0000000000..dc3fc34874 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/spike_main/spike.cc @@ -0,0 +1,619 @@ +// See LICENSE for license details. + +#include "config.h" +#include "cfg.h" +#include "sim.h" +#include "mmu.h" +#include "arith.h" +#include "remote_bitbang.h" +#include "cachesim.h" +#include "extension.h" +#include <dlfcn.h> +#include <fesvr/option_parser.h> +#include <stdio.h> +#include <stdlib.h> +#include <vector> +#include <string> +#include <memory> +#include <fstream> +#include <limits> +#include <cinttypes> +#include "../VERSION" + +static void help(int exit_code = 1) +{ + fprintf(stderr, "Spike RISC-V ISA Simulator " SPIKE_VERSION "\n\n"); + fprintf(stderr, "usage: spike [host options] <target program> [target options]\n"); + fprintf(stderr, "Host Options:\n"); + fprintf(stderr, " -p<n> Simulate <n> processors [default 1]\n"); + fprintf(stderr, " -m<n> Provide <n> MiB of target memory [default 2048]\n"); + fprintf(stderr, " -m<a:m,b:n,...> Provide memory regions of size m and n bytes\n"); + fprintf(stderr, " at base addresses a and b (with 4 KiB alignment)\n"); + fprintf(stderr, " -d Interactive debug mode\n"); + fprintf(stderr, " -g Track histogram of PCs\n"); + fprintf(stderr, " -l Generate a log of execution\n"); +#ifdef HAVE_BOOST_ASIO + fprintf(stderr, " -s Command I/O via socket (use with -d)\n"); +#endif + fprintf(stderr, " -h, --help Print this help message\n"); + fprintf(stderr, " -H Start halted, allowing a debugger to connect\n"); + fprintf(stderr, " --log=<name> File name for option -l\n"); + fprintf(stderr, " --debug-cmd=<name> Read commands from file (use with -d)\n"); + fprintf(stderr, " --isa=<name> RISC-V ISA string [default %s]\n", DEFAULT_ISA); + fprintf(stderr, " --pmpregions=<n> Number of PMP regions [default 16]\n"); + fprintf(stderr, " --priv=<m|mu|msu> RISC-V privilege modes supported [default %s]\n", DEFAULT_PRIV); + fprintf(stderr, " --varch=<name> RISC-V Vector uArch string [default %s]\n", DEFAULT_VARCH); + fprintf(stderr, " --pc=<address> Override ELF entry point\n"); + fprintf(stderr, " --hartids=<a,b,...> Explicitly specify hartids, default is 0,1,...\n"); + fprintf(stderr, " --ic=<S>:<W>:<B> Instantiate a cache model with S sets,\n"); + fprintf(stderr, " --dc=<S>:<W>:<B> W ways, and B-byte blocks (with S and\n"); + fprintf(stderr, " --l2=<S>:<W>:<B> B both powers of 2).\n"); + fprintf(stderr, " --big-endian Use a big-endian memory system.\n"); + fprintf(stderr, " --misaligned Support misaligned memory accesses\n"); + fprintf(stderr, " --device=<P,B,A> Attach MMIO plugin device from an --extlib library\n"); + fprintf(stderr, " P -- Name of the MMIO plugin\n"); + fprintf(stderr, " B -- Base memory address of the device\n"); + fprintf(stderr, " A -- String arguments to pass to the plugin\n"); + fprintf(stderr, " This flag can be used multiple times.\n"); + fprintf(stderr, " The extlib flag for the library must come first.\n"); + fprintf(stderr, " --log-cache-miss Generate a log of cache miss\n"); + fprintf(stderr, " --log-commits Generate a log of commits info\n"); + fprintf(stderr, " --extension=<name> Specify RoCC Extension\n"); + fprintf(stderr, " This flag can be used multiple times.\n"); + fprintf(stderr, " --extlib=<name> Shared library to load\n"); + fprintf(stderr, " This flag can be used multiple times.\n"); + fprintf(stderr, " --rbb-port=<port> Listen on <port> for remote bitbang connection\n"); + fprintf(stderr, " --dump-dts Print device tree string and exit\n"); + fprintf(stderr, " --dtb=<path> Use specified device tree blob [default: auto-generate]\n"); + fprintf(stderr, " --disable-dtb Don't write the device tree blob into memory\n"); + fprintf(stderr, " --kernel=<path> Load kernel flat image into memory\n"); + fprintf(stderr, " --initrd=<path> Load kernel initrd into memory\n"); + fprintf(stderr, " --bootargs=<args> Provide custom bootargs for kernel [default: %s]\n", + DEFAULT_KERNEL_BOOTARGS); + fprintf(stderr, " --real-time-clint Increment clint time at real-time rate\n"); + fprintf(stderr, " --triggers=<n> Number of supported triggers [default 4]\n"); + fprintf(stderr, " --dm-progsize=<words> Progsize for the debug module [default 2]\n"); + fprintf(stderr, " --dm-sba=<bits> Debug system bus access supports up to " + "<bits> wide accesses [default 0]\n"); + fprintf(stderr, " --dm-auth Debug module requires debugger to authenticate\n"); + fprintf(stderr, " --dmi-rti=<n> Number of Run-Test/Idle cycles " + "required for a DMI access [default 0]\n"); + fprintf(stderr, " --dm-abstract-rti=<n> Number of Run-Test/Idle cycles " + "required for an abstract command to execute [default 0]\n"); + fprintf(stderr, " --dm-no-hasel Debug module supports hasel\n"); + fprintf(stderr, " --dm-no-abstract-csr Debug module won't support abstract CSR access\n"); + fprintf(stderr, " --dm-no-abstract-fpr Debug module won't support abstract FPR access\n"); + fprintf(stderr, " --dm-no-halt-groups Debug module won't support halt groups\n"); + fprintf(stderr, " --dm-no-impebreak Debug module won't support implicit ebreak in program buffer\n"); + fprintf(stderr, " --blocksz=<size> Cache block size (B) for CMO operations(powers of 2) [default 64]\n"); + fprintf(stderr, " --steps=<n> Stop simulation after reaching specified number of steps " + "(default: unlimited)\n"); + fprintf(stderr, " --nb_register_source=<n> Set the number of register source usable(2 or 3)\n"); + + exit(exit_code); +} + +static void suggest_help() +{ + fprintf(stderr, "Try 'spike --help' for more information.\n"); + exit(1); +} + +static bool check_file_exists(const char *fileName) +{ + std::ifstream infile(fileName); + return infile.good(); +} + +static std::ifstream::pos_type get_file_size(const char *filename) +{ + std::ifstream in(filename, std::ios::ate | std::ios::binary); + return in.tellg(); +} + +static void read_file_bytes(const char *filename,size_t fileoff, + mem_t* mem, size_t memoff, size_t read_sz) +{ + std::ifstream in(filename, std::ios::in | std::ios::binary); + in.seekg(fileoff, std::ios::beg); + + std::vector<char> read_buf(read_sz, 0); + in.read(&read_buf[0], read_sz); + mem->store(memoff, read_sz, (uint8_t*)&read_buf[0]); +} + +bool sort_mem_region(const mem_cfg_t &a, const mem_cfg_t &b) +{ + if (a.get_base() == b.get_base()) + return (a.get_size() < b.get_size()); + else + return (a.get_base() < b.get_base()); +} + +static bool check_mem_overlap(const mem_cfg_t& L, const mem_cfg_t& R) +{ + return std::max(L.get_base(), R.get_base()) <= std::min(L.get_inclusive_end(), R.get_inclusive_end()); +} + +static bool check_if_merge_covers_64bit_space(const mem_cfg_t& L, + const mem_cfg_t& R) +{ + if (!check_mem_overlap(L, R)) + return false; + + auto start = std::min(L.get_base(), R.get_base()); + auto end = std::max(L.get_inclusive_end(), R.get_inclusive_end()); + + return (start == 0ull) && (end == std::numeric_limits<uint64_t>::max()); +} + +static mem_cfg_t merge_mem_regions(const mem_cfg_t& L, const mem_cfg_t& R) +{ + // one can merge only intersecting regions + assert(check_mem_overlap(L, R)); + + const auto merged_base = std::min(L.get_base(), R.get_base()); + const auto merged_end_incl = std::max(L.get_inclusive_end(), R.get_inclusive_end()); + const auto merged_size = merged_end_incl - merged_base + 1; + + return mem_cfg_t(merged_base, merged_size); +} + +// check the user specified memory regions and merge the overlapping or +// eliminate the containing parts +static std::vector<mem_cfg_t> +merge_overlapping_memory_regions(std::vector<mem_cfg_t> mems) +{ + if (mems.empty()) + return {}; + + std::sort(mems.begin(), mems.end(), sort_mem_region); + + std::vector<mem_cfg_t> merged_mem; + merged_mem.push_back(mems.front()); + + for (auto mem_it = std::next(mems.begin()); mem_it != mems.end(); ++mem_it) { + const auto& mem_int = *mem_it; + if (!check_mem_overlap(merged_mem.back(), mem_int)) { + merged_mem.push_back(mem_int); + continue; + } + // there is a weird corner case preventing two memory regions from being + // merged: if the resulting size of a region is 2^64 bytes - currently, + // such regions are not representable by mem_cfg_t class (because the + // actual size field is effectively a 64 bit value) + // so we create two smaller memory regions that total for 2^64 bytes as + // a workaround + if (check_if_merge_covers_64bit_space(merged_mem.back(), mem_int)) { + merged_mem.clear(); + merged_mem.push_back(mem_cfg_t(0ull, 0ull - PGSIZE)); + merged_mem.push_back(mem_cfg_t(0ull - PGSIZE, PGSIZE)); + break; + } + merged_mem.back() = merge_mem_regions(merged_mem.back(), mem_int); + } + + return merged_mem; +} + +static std::vector<mem_cfg_t> parse_mem_layout(const char* arg) +{ + std::vector<mem_cfg_t> res; + + // handle legacy mem argument + char* p; + auto mb = strtoull(arg, &p, 0); + if (*p == 0) { + reg_t size = reg_t(mb) << 20; + if (size != (size_t)size) + throw std::runtime_error("Size would overflow size_t"); + res.push_back(mem_cfg_t(reg_t(DRAM_BASE), size)); + return res; + } + + // handle base/size tuples + while (true) { + auto base = strtoull(arg, &p, 0); + if (!*p || *p != ':') + help(); + auto size = strtoull(p + 1, &p, 0); + + // page-align base and size + auto base0 = base, size0 = size; + size += base0 % PGSIZE; + base -= base0 % PGSIZE; + if (size % PGSIZE != 0) + size += PGSIZE - size % PGSIZE; + + if (size != size0) { + fprintf(stderr, "Warning: the memory at [0x%llX, 0x%llX] has been realigned\n" + "to the %ld KiB page size: [0x%llX, 0x%llX]\n", + base0, base0 + size0 - 1, long(PGSIZE / 1024), base, base + size - 1); + } + + if (!mem_cfg_t::check_if_supported(base, size)) { + fprintf(stderr, "Unsupported memory region " + "{base = 0x%llX, size = 0x%llX} specified\n", + base, size); + exit(EXIT_FAILURE); + } + + const unsigned long long max_allowed_pa = (1ull << MAX_PADDR_BITS) - 1ull; + assert(max_allowed_pa <= std::numeric_limits<reg_t>::max()); + mem_cfg_t mem_region(base, size); + if (mem_region.get_inclusive_end() > max_allowed_pa) { + int bits_required = 64 - clz(mem_region.get_inclusive_end()); + fprintf(stderr, "Unsupported memory region " + "{base = 0x%" PRIX64 ", size = 0x%" PRIX64 "} specified," + " which requires %d bits of physical address\n" + " The largest accessible physical address " + "is 0x%llX (defined by MAX_PADDR_BITS constant, which is %d)\n", + mem_region.get_base(), mem_region.get_size(), bits_required, + max_allowed_pa, MAX_PADDR_BITS); + exit(EXIT_FAILURE); + } + + res.push_back(mem_region); + + if (!*p) + break; + if (*p != ',') + help(); + arg = p + 1; + } + + auto merged_mem = merge_overlapping_memory_regions(res); + + assert(!merged_mem.empty()); + return merged_mem; +} + +static std::vector<std::pair<reg_t, mem_t*>> make_mems(const std::vector<mem_cfg_t> &layout) +{ + std::vector<std::pair<reg_t, mem_t*>> mems; + mems.reserve(layout.size()); + for (const auto &cfg : layout) { + mems.push_back(std::make_pair(cfg.get_base(), new mem_t(cfg.get_size()))); + } + return mems; +} + +static unsigned long atoul_safe(const char* s) +{ + char* e; + auto res = strtoul(s, &e, 10); + if (*e) + help(); + return res; +} + +static unsigned long atoul_nonzero_safe(const char* s) +{ + auto res = atoul_safe(s); + if (!res) + help(); + return res; +} + +static std::vector<size_t> parse_hartids(const char *s) +{ + std::string const str(s); + std::stringstream stream(str); + std::vector<size_t> hartids; + + int n; + while (stream >> n) { + if (n < 0) { + fprintf(stderr, "Negative hart ID %d is unsupported\n", n); + exit(-1); + } + + hartids.push_back(n); + if (stream.peek() == ',') stream.ignore(); + } + + if (hartids.empty()) { + fprintf(stderr, "No hart IDs specified\n"); + exit(-1); + } + + std::sort(hartids.begin(), hartids.end()); + + const auto dup = std::adjacent_find(hartids.begin(), hartids.end()); + if (dup != hartids.end()) { + fprintf(stderr, "Duplicate hart ID %zu\n", *dup); + exit(-1); + } + + return hartids; +} + +int main(int argc, char** argv) +{ + uint8_t number_register_source = 2; + bool debug = false; + bool halted = false; + bool histogram = false; + bool log = false; + bool UNUSED socket = false; // command line option -s + bool dump_dts = false; + bool dtb_enabled = true; + const char* kernel = NULL; + reg_t kernel_offset, kernel_size; + std::vector<std::pair<reg_t, abstract_device_t*>> plugin_devices; + std::unique_ptr<icache_sim_t> ic; + std::unique_ptr<dcache_sim_t> dc; + std::unique_ptr<cache_sim_t> l2; + bool log_cache = false; + bool log_commits = false; + const char *log_path = nullptr; + std::vector<std::function<extension_t*()>> extensions; + const char* initrd = NULL; + const char* dtb_file = NULL; + uint16_t rbb_port = 0; + bool use_rbb = false; + unsigned dmi_rti = 0; + reg_t blocksz = 64; + debug_module_config_t dm_config = { + .progbufsize = 2, + .max_sba_data_width = 0, + .require_authentication = false, + .abstract_rti = 0, + .support_hasel = true, + .support_abstract_csr_access = true, + .support_abstract_fpr_access = true, + .support_haltgroups = true, + .support_impebreak = true + }; + size_t max_steps = 0; + cfg_arg_t<size_t> nprocs(1); + + cfg_t cfg(/*default_initrd_bounds=*/std::make_pair((reg_t)0, (reg_t)0), + /*default_bootargs=*/nullptr, + /*default_isa=*/DEFAULT_ISA, + /*default_priv=*/DEFAULT_PRIV, + /*default_varch=*/DEFAULT_VARCH, + /*default_misaligned=*/false, + /*default_endianness*/endianness_little, + /*default_pmpregions=*/16, + /*default_mem_layout=*/parse_mem_layout("2048"), + /*default_hartids=*/std::vector<size_t>(), + /*default_real_time_clint=*/false, + /*default_trigger_count=*/4); + + auto const device_parser = [&plugin_devices](const char *s) { + const std::string str(s); + std::istringstream stream(str); + + // We are parsing a string like name,base,args. + + // Parse the name, which is simply all of the characters leading up to the + // first comma. The validity of the plugin name will be checked later. + std::string name; + std::getline(stream, name, ','); + if (name.empty()) { + throw std::runtime_error("Plugin name is empty."); + } + + // Parse the base address. First, get all of the characters up to the next + // comma (or up to the end of the string if there is no comma). Then try to + // parse that string as an integer according to the rules of strtoull. It + // could be in decimal, hex, or octal. Fail if we were able to parse a + // number but there were garbage characters after the valid number. We must + // consume the entire string between the commas. + std::string base_str; + std::getline(stream, base_str, ','); + if (base_str.empty()) { + throw std::runtime_error("Device base address is empty."); + } + char* end; + reg_t base = static_cast<reg_t>(strtoull(base_str.c_str(), &end, 0)); + if (end != &*base_str.cend()) { + throw std::runtime_error("Error parsing device base address."); + } + + // The remainder of the string is the arguments. We could use getline, but + // that could ignore newline characters in the arguments. That should be + // rare and discouraged, but handle it here anyway with this weird in_avail + // technique. The arguments are optional, so if there were no arguments + // specified we could end up with an empty string here. That's okay. + auto avail = stream.rdbuf()->in_avail(); + std::string args(avail, '\0'); + stream.readsome(&args[0], avail); + + plugin_devices.emplace_back(base, new mmio_plugin_device_t(name, args)); + }; + + option_parser_t parser; + parser.help(&suggest_help); + parser.option('h', "help", 0, [&](const char UNUSED *s){help(0);}); + parser.option('d', 0, 0, [&](const char UNUSED *s){debug = true;}); + parser.option('g', 0, 0, [&](const char UNUSED *s){histogram = true;}); + parser.option('l', 0, 0, [&](const char UNUSED *s){log = true;}); +#ifdef HAVE_BOOST_ASIO + parser.option('s', 0, 0, [&](const char UNUSED *s){socket = true;}); +#endif + parser.option('p', 0, 1, [&](const char* s){nprocs = atoul_nonzero_safe(s);}); + parser.option('m', 0, 1, [&](const char* s){cfg.mem_layout = parse_mem_layout(s);}); + // I wanted to use --halted, but for some reason that doesn't work. + parser.option('H', 0, 0, [&](const char UNUSED *s){halted = true;}); + parser.option(0, "rbb-port", 1, [&](const char* s){use_rbb = true; rbb_port = atoul_safe(s);}); + parser.option(0, "pc", 1, [&](const char* s){cfg.start_pc = strtoull(s, 0, 0);}); + parser.option(0, "hartids", 1, [&](const char* s){ + cfg.hartids = parse_hartids(s); + cfg.explicit_hartids = true; + }); + parser.option(0, "ic", 1, [&](const char* s){ic.reset(new icache_sim_t(s));}); + parser.option(0, "dc", 1, [&](const char* s){dc.reset(new dcache_sim_t(s));}); + parser.option(0, "l2", 1, [&](const char* s){l2.reset(cache_sim_t::construct(s, "L2$"));}); + parser.option(0, "big-endian", 0, [&](const char UNUSED *s){cfg.endianness = endianness_big;}); + parser.option(0, "misaligned", 0, [&](const char UNUSED *s){cfg.misaligned = true;}); + parser.option(0, "log-cache-miss", 0, [&](const char UNUSED *s){log_cache = true;}); + parser.option(0, "isa", 1, [&](const char* s){cfg.isa = s;}); + parser.option(0, "pmpregions", 1, [&](const char* s){cfg.pmpregions = atoul_safe(s);}); + parser.option(0, "priv", 1, [&](const char* s){cfg.priv = s;}); + parser.option(0, "varch", 1, [&](const char* s){cfg.varch = s;}); + parser.option(0, "device", 1, device_parser); + parser.option(0, "extension", 1, [&](const char* s){extensions.push_back(find_extension(s));}); + parser.option(0, "dump-dts", 0, [&](const char UNUSED *s){dump_dts = true;}); + parser.option(0, "disable-dtb", 0, [&](const char UNUSED *s){dtb_enabled = false;}); + parser.option(0, "dtb", 1, [&](const char *s){dtb_file = s;}); + parser.option(0, "kernel", 1, [&](const char* s){kernel = s;}); + parser.option(0, "initrd", 1, [&](const char* s){initrd = s;}); + parser.option(0, "bootargs", 1, [&](const char* s){cfg.bootargs = s;}); + parser.option(0, "real-time-clint", 0, [&](const char UNUSED *s){cfg.real_time_clint = true;}); + parser.option(0, "triggers", 1, [&](const char *s){cfg.trigger_count = atoul_safe(s);}); + parser.option(0, "extlib", 1, [&](const char *s){ + void *lib = dlopen(s, RTLD_NOW | RTLD_GLOBAL); + if (lib == NULL) { + fprintf(stderr, "Unable to load extlib '%s': %s\n", s, dlerror()); + exit(-1); + } + }); + parser.option(0, "steps", 1, [&](const char* s){max_steps = strtoull(s, 0, 0);}); + parser.option(0, "dm-progsize", 1, + [&](const char* s){dm_config.progbufsize = atoul_safe(s);}); + parser.option(0, "dm-no-impebreak", 0, + [&](const char UNUSED *s){dm_config.support_impebreak = false;}); + parser.option(0, "dm-sba", 1, + [&](const char* s){dm_config.max_sba_data_width = atoul_safe(s);}); + parser.option(0, "dm-auth", 0, + [&](const char UNUSED *s){dm_config.require_authentication = true;}); + parser.option(0, "dmi-rti", 1, + [&](const char* s){dmi_rti = atoul_safe(s);}); + parser.option(0, "dm-abstract-rti", 1, + [&](const char* s){dm_config.abstract_rti = atoul_safe(s);}); + parser.option(0, "dm-no-hasel", 0, + [&](const char UNUSED *s){dm_config.support_hasel = false;}); + parser.option(0, "dm-no-abstract-csr", 0, + [&](const char UNUSED *s){dm_config.support_abstract_csr_access = false;}); + parser.option(0, "dm-no-abstract-fpr", 0, + [&](const char UNUSED *s){dm_config.support_abstract_fpr_access = false;}); + parser.option(0, "dm-no-halt-groups", 0, + [&](const char UNUSED *s){dm_config.support_haltgroups = false;}); + parser.option(0, "log-commits", 0, + [&](const char UNUSED *s){log_commits = true;}); + parser.option(0, "log", 1, + [&](const char* s){log_path = s;}); + FILE *cmd_file = NULL; + parser.option(0, "debug-cmd", 1, [&](const char* s){ + if ((cmd_file = fopen(s, "r"))==NULL) { + fprintf(stderr, "Unable to open command file '%s'\n", s); + exit(-1); + } + }); + parser.option(0, "blocksz", 1, [&](const char* s){ + blocksz = strtoull(s, 0, 0); + const unsigned min_blocksz = 16; + const unsigned max_blocksz = PGSIZE; + if (blocksz < min_blocksz || blocksz > max_blocksz || ((blocksz & (blocksz - 1))) != 0) { + fprintf(stderr, "--blocksz must be a power of 2 between %u and %u\n", + min_blocksz, max_blocksz); + exit(-1); + } + }); + parser.option(0, "nb_register_source", 1, [&](const char* s){ + number_register_source = (uint8_t)atoi(s); + }); + + auto argv1 = parser.parse(argv); + std::vector<std::string> htif_args(argv1, (const char*const*)argv + argc); + + if (!*argv1) + help(); + + std::vector<std::pair<reg_t, mem_t*>> mems = make_mems(cfg.mem_layout()); + + if (kernel && check_file_exists(kernel)) { + const char *isa = cfg.isa(); + kernel_size = get_file_size(kernel); + if (isa[2] == '6' && isa[3] == '4') + kernel_offset = 0x200000; + else + kernel_offset = 0x400000; + for (auto& m : mems) { + if (kernel_size && (kernel_offset + kernel_size) < m.second->size()) { + read_file_bytes(kernel, 0, m.second, kernel_offset, kernel_size); + break; + } + } + } + + if (initrd && check_file_exists(initrd)) { + size_t initrd_size = get_file_size(initrd); + for (auto& m : mems) { + if (initrd_size && (initrd_size + 0x1000) < m.second->size()) { + reg_t initrd_end = m.first + m.second->size() - 0x1000; + reg_t initrd_start = initrd_end - initrd_size; + cfg.initrd_bounds = std::make_pair(initrd_start, initrd_end); + read_file_bytes(initrd, 0, m.second, initrd_start - m.first, initrd_size); + break; + } + } + } + + if (cfg.explicit_hartids) { + if (nprocs.overridden() && (nprocs() != cfg.nprocs())) { + std::cerr << "Number of specified hartids (" + << cfg.nprocs() + << ") doesn't match specified number of processors (" + << nprocs() << ").\n"; + exit(1); + } + } else { + // Set default set of hartids based on nprocs, but don't set the + // explicit_hartids flag (which means that downstream code can know that + // we've only set the number of harts, not explicitly chosen their IDs). + std::vector<size_t> default_hartids; + default_hartids.reserve(nprocs()); + for (size_t i = 0; i < nprocs(); ++i) { + default_hartids.push_back(i); + } + cfg.hartids = default_hartids; + } + + sim_t s(&cfg, halted, + mems, plugin_devices, htif_args, dm_config, log_path, dtb_enabled, dtb_file, + socket, + cmd_file, max_steps); + std::unique_ptr<remote_bitbang_t> remote_bitbang((remote_bitbang_t *) NULL); + std::unique_ptr<jtag_dtm_t> jtag_dtm( + new jtag_dtm_t(&s.debug_module, dmi_rti)); + if (use_rbb) { + remote_bitbang.reset(new remote_bitbang_t(rbb_port, &(*jtag_dtm))); + s.set_remote_bitbang(&(*remote_bitbang)); + } + + if (dump_dts) { + printf("%s", s.get_dts()); + return 0; + } + + if (ic && l2) ic->set_miss_handler(&*l2); + if (dc && l2) dc->set_miss_handler(&*l2); + if (ic) ic->set_log(log_cache); + if (dc) dc->set_log(log_cache); + for (size_t i = 0; i < cfg.nprocs(); i++) + { + s.get_core(i)->set_nb_register_source(number_register_source); + if (ic) s.get_core(i)->get_mmu()->register_memtracer(&*ic); + if (dc) s.get_core(i)->get_mmu()->register_memtracer(&*dc); + for (auto e : extensions) + s.get_core(i)->register_extension(e()); + s.get_core(i)->get_mmu()->set_cache_blocksz(blocksz); + } + + s.set_debug(debug); + s.configure_log(log, log_commits); + s.set_histogram(histogram); + + auto return_code = s.run(); + + for (auto& mem : mems) + delete mem.second; + + for (auto& plugin_device : plugin_devices) + delete plugin_device.second; + + return return_code; +} diff --git a/vendor/riscv/riscv-isa-sim/spike_main/spike_main.ac b/vendor/riscv/riscv-isa-sim/spike_main/spike_main.ac new file mode 100644 index 0000000000..e69de29bb2 diff --git a/vendor/riscv/riscv-isa-sim/spike_main/spike_main.mk.in b/vendor/riscv/riscv-isa-sim/spike_main/spike_main.mk.in new file mode 100644 index 0000000000..25a7a6c61c --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/spike_main/spike_main.mk.in @@ -0,0 +1,16 @@ +spike_main_subproject_deps = \ + fdt \ + fesvr \ + softfloat \ + disasm \ + riscv \ + +spike_main_install_prog_srcs = \ + spike.cc \ + spike-log-parser.cc \ + xspike.cc \ + termios-xspike.cc \ + +spike_main_srcs = \ + +spike_main_CFLAGS = -fPIC diff --git a/vendor/riscv/riscv-isa-sim/spike_main/termios-xspike.cc b/vendor/riscv/riscv-isa-sim/spike_main/termios-xspike.cc new file mode 100644 index 0000000000..e533933bf5 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/spike_main/termios-xspike.cc @@ -0,0 +1,29 @@ +// See LICENSE for license details. + +// termios-xspike sets up a canonical terminal and blocks forever. +// It allows us to send Ctrl-C etc. to the target machine. + +#include <unistd.h> +#include <termios.h> +#include <signal.h> +#include <assert.h> +#include <stdlib.h> +#include <stdio.h> + +int main() +{ + struct termios old_tios; + if (tcgetattr(0, &old_tios) < 0) + return -1; + + signal(SIGTERM, [](int) { }); + + struct termios new_tios = old_tios; + new_tios.c_lflag &= ~(ICANON | ECHO | ISIG); + if (tcsetattr(0, TCSANOW, &new_tios) < 0) + return -1; + + pause(); + + return tcsetattr(0, TCSANOW, &old_tios); +} diff --git a/vendor/riscv/riscv-isa-sim/spike_main/xspike.cc b/vendor/riscv/riscv-isa-sim/spike_main/xspike.cc new file mode 100644 index 0000000000..661a2067d6 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/spike_main/xspike.cc @@ -0,0 +1,103 @@ +// See LICENSE for license details. + +// xspike forks an xterm for spike's target machine console, +// preserving the current terminal for debugging. + +#include "common.h" +#include <unistd.h> +#include <fcntl.h> +#include <signal.h> +#include <sys/wait.h> +#include <cstdio> +#include <climits> +#include <cstring> +#include <stdexcept> + +static pid_t fork_spike(int tty_fd, char** argv); +static pid_t fork_xterm(int* tty_fd); + +int main(int UNUSED argc, char** argv) +{ + int tty_fd, wait_status, ret = -1; + pid_t xterm, spike; + + static bool signal_exit = false; + auto handle_signal = [](int) { signal_exit = true; }; + + if ((xterm = fork_xterm(&tty_fd)) < 0) + { + fprintf(stderr, "could not open xterm\n"); + goto out; + } + + signal(SIGINT, handle_signal); + + if ((spike = fork_spike(tty_fd, argv)) < 0) + { + fprintf(stderr, "could not open spike\n"); + goto close_xterm; + } + + while ((ret = waitpid(spike, &wait_status, 0)) < 0) + if (signal_exit) + break; + + if (ret < 0) // signal_exit + kill(spike, SIGTERM); + else + ret = WIFEXITED(wait_status) ? WEXITSTATUS(wait_status) : -1; + +close_xterm: + kill(-xterm, SIGTERM); +out: + return ret; +} + +static pid_t fork_spike(int tty_fd, char** argv) +{ + pid_t pid = fork(); + if (pid < 0) + return -1; + + if (pid == 0) + { + if (dup2(tty_fd, STDIN_FILENO) < 0 || dup2(tty_fd, STDOUT_FILENO) < 0) + return -1; + execvp("spike", argv); + return -1; + } + + return pid; +} + +static pid_t fork_xterm(int* tty_fd) +{ + static const char cmd[] = "3>&1 xterm -title xspike -e sh -c 'tty 1>&3; termios-xspike'"; + + int fds[2]; + if (pipe(fds) < 0) + return -1; + + pid_t pid = fork(); + if (pid < 0) + return -1; + + if (pid == 0) + { + setpgid(0, 0); + if (dup2(fds[1], STDOUT_FILENO) < 0) + return -1; + execl("/bin/sh", "sh", "-c", cmd, NULL); + return -1; + } + + char tty[PATH_MAX]; + ssize_t ttylen = read(fds[0], tty, sizeof(tty)); + if (ttylen <= 1 || tty[ttylen-1] != '\n') + return -1; + tty[ttylen-1] = '\0'; + if ((*tty_fd = open(tty, O_RDWR)) < 0) + return -1; + + return pid; +} diff --git a/vendor/riscv/riscv-isa-sim/tests/ebreak.py b/vendor/riscv/riscv-isa-sim/tests/ebreak.py new file mode 100755 index 0000000000..dd7e65878b --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/tests/ebreak.py @@ -0,0 +1,26 @@ +#!/usr/bin/python + +import os +import testlib +import unittest +import tempfile +import time + +class EbreakTest(unittest.TestCase): + def setUp(self): + self.binary = testlib.compile("ebreak.s") + + def test_noport(self): + """Make sure that we can run past ebreak when --gdb-port isn't used.""" + spike = testlib.Spike(self.binary, with_gdb=False, timeout=10) + result = spike.wait() + self.assertEqual(result, 0) + + def test_nogdb(self): + """Make sure that we can run past ebreak when gdb isn't attached.""" + spike = testlib.Spike(self.binary, timeout=10) + result = spike.wait() + self.assertEqual(result, 0) + +if __name__ == '__main__': + unittest.main() diff --git a/vendor/riscv/riscv-isa-sim/tests/ebreak.s b/vendor/riscv/riscv-isa-sim/tests/ebreak.s new file mode 100644 index 0000000000..99f3e07ccd --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/tests/ebreak.s @@ -0,0 +1,5 @@ + .global main +main: + li a0, 0 + ebreak + ret diff --git a/vendor/riscv/riscv-isa-sim/tests/testlib.py b/vendor/riscv/riscv-isa-sim/tests/testlib.py new file mode 100644 index 0000000000..d5e8d795c9 --- /dev/null +++ b/vendor/riscv/riscv-isa-sim/tests/testlib.py @@ -0,0 +1,116 @@ +import os.path +import pexpect +import subprocess +import tempfile +import testlib +import unittest + +# Note that gdb comes with its own testsuite. I was unable to figure out how to +# run that testsuite against the spike simulator. + +def find_file(path): + for directory in (os.getcwd(), os.path.dirname(testlib.__file__)): + fullpath = os.path.join(directory, path) + if os.path.exists(fullpath): + return fullpath + return None + +def compile(*args): + """Compile a single .c file into a binary.""" + dst = os.path.splitext(args[0])[0] + cc = os.path.expandvars("$RISCV/bin/riscv64-unknown-elf-gcc") + cmd = [cc, "-g", "-O", "-o", dst] + for arg in args: + found = find_file(arg) + if found: + cmd.append(found) + else: + cmd.append(arg) + cmd = " ".join(cmd) + result = os.system(cmd) + assert result == 0, "%r failed" % cmd + return dst + +def unused_port(): + # http://stackoverflow.com/questions/2838244/get-open-tcp-port-in-python/2838309#2838309 + import socket + s = socket.socket(socket.AF_INET, socket.SOCK_STREAM) + s.bind(("",0)) + port = s.getsockname()[1] + s.close() + return port + +class Spike(object): + def __init__(self, binary, halted=False, with_gdb=True, timeout=None): + """Launch spike. Return tuple of its process and the port it's running on.""" + cmd = [] + if timeout: + cmd += ["timeout", str(timeout)] + + cmd += [find_file("spike")] + if halted: + cmd.append('-H') + if with_gdb: + self.port = unused_port() + cmd += ['--gdb-port', str(self.port)] + cmd.append('pk') + if binary: + cmd.append(binary) + logfile = open("spike.log", "w") + self.process = subprocess.Popen(cmd, stdin=subprocess.PIPE, stdout=logfile, + stderr=logfile) + + def __del__(self): + try: + self.process.kill() + self.process.wait() + except OSError: + pass + + def wait(self, *args, **kwargs): + return self.process.wait(*args, **kwargs) + +class Gdb(object): + def __init__(self): + path = os.path.expandvars("$RISCV/bin/riscv64-unknown-elf-gdb") + self.child = pexpect.spawn(path) + self.child.logfile = file("gdb.log", "w") + self.wait() + self.command("set width 0") + self.command("set height 0") + # Force consistency. + self.command("set print entry-values no") + + def wait(self): + """Wait for prompt.""" + self.child.expect("\(gdb\)") + + def command(self, command, timeout=-1): + self.child.sendline(command) + self.child.expect("\n", timeout=timeout) + self.child.expect("\(gdb\)", timeout=timeout) + return self.child.before.strip() + + def c(self, wait=True): + if wait: + return self.command("c") + else: + self.child.sendline("c") + self.child.expect("Continuing") + + def interrupt(self): + self.child.send("\003"); + self.child.expect("\(gdb\)") + + def x(self, address, size='w'): + output = self.command("x/%s %s" % (size, address)) + value = int(output.split(':')[1].strip(), 0) + return value + + def p(self, obj): + output = self.command("p %s" % obj) + value = int(output.split('=')[-1].strip()) + return value + + def stepi(self): + return self.command("stepi") diff --git a/vendor/riscv_riscv-isa-sim.lock.hjson b/vendor/riscv_riscv-isa-sim.lock.hjson new file mode 100644 index 0000000000..90c711408e --- /dev/null +++ b/vendor/riscv_riscv-isa-sim.lock.hjson @@ -0,0 +1,14 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This file is generated by the util/vendor script. Please do not modify it +// manually. + +{ + upstream: + { + url: https://github.com/riscv/riscv-isa-sim.git + rev: fcbdbe7946079650d0e656fa3d353e3f652d471f + } +} diff --git a/vendor/riscv_riscv-isa-sim.vendor.hjson b/vendor/riscv_riscv-isa-sim.vendor.hjson new file mode 100644 index 0000000000..981f11b940 --- /dev/null +++ b/vendor/riscv_riscv-isa-sim.vendor.hjson @@ -0,0 +1,29 @@ +// -*- coding: utf-8 -*- +// Copyright (C) 2022 Thales DIS France SAS +// SPDX-License-Identifier: Apache-2.0. +// Original Author: Zbigniew Chamski (Thales) + +{ + // Name of the project + name: "riscv-isa-sim", + + // Target directory: relative to the location of this script. + target_dir: "riscv/riscv-isa-sim", + + // Upstream repository + upstream: { + // URL + url: "https://github.com/riscv/riscv-isa-sim.git", + // revision + rev: "fcbdbe7946079650d0e656fa3d353e3f652d471f", + } + + // Patch dir for local changes + patch_dir: "patches/riscv/riscv-isa-sim", + + // Exclusions from upstream content + exclude_from_upstream: [ + ".github", + "ci-tests", + ] +} diff --git a/verif/.gitignore b/verif/.gitignore new file mode 100644 index 0000000000..993df2a7b3 --- /dev/null +++ b/verif/.gitignore @@ -0,0 +1,71 @@ +*~ +*.nm +*.elf +*.hex +*.itb +*.map +*.o +*.objdump +*.readelf +*.gtkw +*.vcd +*.vsif +*.sve +*.sdb +test_build +dsim.env +dsim.log +dsim_results +metrics.db +metrics_history.db +xrun_results +vsim_results +vmgr_sessions +__pycache__ +*.swp +/.cproject +/.project +.dvt/ +dvt_build.log +xrun.history +xrun.log +xrun.key +xcelium.d/ +waves.shm/ +*.log +stdout.txt +.vscode +tests/riscv-compliance/ +tests/riscv-arch-test/ +tests/riscv-tests/ +tests/riscv-isa-sim/ +sim/dv/ +sim/vcs_results +sim/verilator_work +sim/out_* +sim/Mem_init.txt +sim/*.txt +sim/trace* +sim/simv* +sim/ucli.key +sim/.inter* +sim/.vcs* +sim/inter* +sim/novas* +sim/verdiLog +sim/Verdi.ses* +riviera_results/ +*/vendor_lib/dpi_dasm_spike/ +*/vendor_lib/verilab/svlib/ +work* +vsim.dbg +*.wlf +transcript +.lib-rtl +.opt-rtl +tools/spike +tools/verilator* +*_results/ +*.signature_output +ucli.key +vcs.cmd diff --git a/verif/README.md b/verif/README.md new file mode 100644 index 0000000000..a2185c009e --- /dev/null +++ b/verif/README.md @@ -0,0 +1,92 @@ +# CVA6: Verification Environment for the CVA6 CORE-V processor core + +- [Directories](#directories) +- [Prerequisites](#prerequisites) +- [Test execution](#test-execution) +- [Environment variables](#environment-variables) +- [32-bit configuration](#32-bit-configuration) + +## Directories: +- **bsp**: board support package for test-programs compiled/assembled/linked for the CVA6. +This BSP is used by both `core` testbench and `uvmt_cva6` UVM verification environment. +- **regress**: scripts to install tools, test suites, CVA6 code and to execute tests +- **sim**: simulation environment (e.g. riscv-dv) +- **tb**: testbench module instancing the core +- **tests**: source of test cases and test lists + +There are README files in each directory with additional information. + +## Prerequisites +To execute tests on CVA6 core, you need a RISC-V toolchain. + +Be aware that only gcc 11.1.0 or newer are supported in core-v-verif repository. +To build and install riscv gcc compiler in local, you can use the following commands : + +- `git clone https://github.com/riscv-collab/riscv-gnu-toolchain` +- `cd riscv-gnu-toolchain` +- `git clone https://github.com/gcc-mirror/gcc -b releases/gcc-13 gcc-13` +- ```./configure –prefix:/path/to/installation/directory --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" --with-gcc-src=`pwd`/gcc-13``` +- `make –j32` + +These commands will install the riscv gcc 13.1.0 compiler which is the latest version. +Once running the previous commands, your environment must be updated with : + +- `export RISCV=/path/to/installation/directory` +- `export RISCV_PREFIX=/path/to/installation/directory/bin/riscv64-unknown-` +- `export RISCV_GCC=/path/to/installation/directory/bin/riscv64-unknown-gcc` +- `export CV_SW_PREFIX=riscv64-unknown-elf-` + +This 4 variables will ensure you use correctly the new gcc compiler you have just installed. +You will now be able to run the test scripts. + +## Test execution +Run one of the shell scripts: + +- `source cva6/regress/dv-riscv-compliance.sh`: +[riscv-compliance](https://github.com/riscv/riscv-compliance) test suite, +- `source cva6/regress/dv-riscv-tests.sh`: +[riscv-tests](https://github.com/riscv/riscv-tests) test suite. + +These tests are using [riscv-dv](https://github.com/google/riscv-dv) +as environment. + +## Environment variables +Other environment variables can be set to overload default values +provided in the different scripts. + +The default values are: + +- `RISCV_GCC`: `$RISCV/bin/riscv-none-elf-gcc` +- `RISCV_OBJCOPY`: `$RISCV/bin/riscv-none-elf-objcopy` +- `VERILATOR_ROOT`: `../tools/verilator-4.110` to install in core-v-verif/tools +- `SPIKE_ROOT`: `../tools/spike` to install in core-v-verif/tools + +- `CVA6_REPO`: `https://github.com/openhwgroup/cva6.git` +- `CVA6_BRANCH`: `master` +- `CVA6_HASH`: see value in `regress/install-cva6.sh` +- `CVA6_PATCH`: no default value +- `COMPLIANCE_REPO`: `https://github.com/riscv/riscv-compliance.git` +- `COMPLIANCE_BRANCH`: `master` +- `COMPLIANCE_HASH`: `220e78542da4510e40eac31e31fdd4e77cdae437` +- `COMPLIANCE_PATCH`: no default value +- `TESTS_REPO`: `https://github.com/riscv/riscv-tests.git` +- `TESTS_BRANCH`: `master` +- `TESTS_HASH`: `f92842f91644092960ac7946a61ec2895e543cec` +- `DV_REPO`: `https://github.com/google/riscv-dv.git` +- `DV_BRANCH`: `master` +- `DV_HASH`: `0ce85d3187689855cd2b3b9e3fae21ca32de2248` +- `DV_PATCH`: no default value +- `DV_TARGET`: `cv64a6_imafdc_sv39` +- `DV_SIMULATORS`: `veri-core,spike` +- `DV_TESTLISTS`: `../tests/testlist_riscv-tests-$DV_TARGET-p.yaml +../tests/testlist_riscv-tests-$DV_TARGET-v.yaml` +- `DV_OPTS`: no default value + +## 32-bit configuration +To test the CVA6 in 32-bit configuration, use `DV_TARGET` with +a 32-bit variant (e.g. `cv32a6_imac_sv0`). + +The following environment variables have to be modified before executing +test script. + +- `DV_TARGET`: `cv32a6_imac_sv0` diff --git a/verif/bsp/.gitignore b/verif/bsp/.gitignore new file mode 100644 index 0000000000..c0a1f349c4 --- /dev/null +++ b/verif/bsp/.gitignore @@ -0,0 +1 @@ +libcv-verif.a diff --git a/verif/bsp/Makefile b/verif/bsp/Makefile new file mode 100644 index 0000000000..17ead027d0 --- /dev/null +++ b/verif/bsp/Makefile @@ -0,0 +1,32 @@ +CV_SW_TOOLCHAIN ?= /opt/riscv +RISCV ?= $(CV_SW_TOOLCHAIN) +RISCV_EXE_PREFIX ?= $(RISCV)/bin/riscv32-unknown-elf- +RISCV_GCC = $(RISCV_EXE_PREFIX)gcc +RISCV_AR = $(RISCV_EXE_PREFIX)ar +SRC = crt0.S handlers.S syscalls.c vectors.S +OBJ = crt0.o handlers.o syscalls.o vectors.o +LIBCV-VERIF = libcv-verif.a +CFLAGS ?= -Os -g -static -mabi=ilp32 -march=rv32imc -Wall -pedantic + +all: $(LIBCV-VERIF) + +$(LIBCV-VERIF): $(OBJ) + $(RISCV_AR) rcs $@ $(OBJ) + +%.o : %.c + $(RISCV_GCC) $(CFLAGS) -c $< -o $@ + +%.o : %.S + $(RISCV_GCC) $(CFLAGS) -c $< -o $@ + +clean: + rm -f $(OBJ) $(LIBCV-VERIF) + + +vars: + @echo "make bsp variables:" + @echo " CV_SW_TOOLCHAIN = $(CV_SW_TOOLCHAIN)" + @echo " RISCV = $(RISCV)" + @echo " RISCV_EXE_PREFIX = $(RISCV_EXE_PREFIX)" + @echo " RISCV_GCC = $(RISCV_GCC)" + diff --git a/verif/bsp/README.md b/verif/bsp/README.md new file mode 100644 index 0000000000..8e6d5d44c6 --- /dev/null +++ b/verif/bsp/README.md @@ -0,0 +1,166 @@ +Board Support Package (BSP) for CV32 Verification +================================================= + +This BSP provides the code to support running programs on the CV32 verification +target. It performs initialization tasks (`crt0.S`), handles +interrupts/exceptions (`vectors.S`, `handlers.S`), provides syscall +implementations (`syscalls.c`) and includes a linker script (`link.ld`) to +control the placement of sections in the binary. + +Each file is described in more detail below followed by instructions for +building and using the BSP. + +C Runtime Initialization +------------------------ + +The C Runtime file `crt0.S` provides the `_start` function which is the entry +point of the program and performs the following tasks: + * Initialize global and stack pointer. + * Store the address of `vector_table` in `mtvec`, setting the lower two bits + to `0x2` to select vectored interrupt mode. + * Zero the BSS section. + * Invoke initialization of C constructors and set destructors to be called on + exit. + * Zero `argc` and `argv` (the stack is not initialized, so these are zeroed + to prevent uninitialized values causing a mismatch against the reference + result). + * Call `main`. + * If `main` returns, call `exit` with its return code. + +Interrupt and Exception Handling +-------------------------------- + +When a RISC-V core traps on an interrupt/exception, the `pc` is stored in `mepc` +and the reason for the trap is stored in `mcause`. The `MSB` of `mcause` +is set to `0` for an exception and `1` for an interrupt; the remaining bits +`mcause[MXLEN-2:0]` contain the exception code. The table of `mcause` values is +defined in Table 3.6 of the [RISC-V Instruction Set Manual Volume II: Privileged +Architecture Version 20190608-Priv-MSU-Ratified](https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMFDQC-and-Priv-v1.11/riscv-privileged-20190608.pdf). + +The core jumps to a location in the vector table according to the `BASE` address +of the vector table stored in `mtvec` and the value of the exception code in +`mcause`. In vectored mode, all exceptions jump to `BASE` and interrupts jump to +`BASE+4*mcause[XLEN-2:0]`. Note that because user software interrupts have +exception code `0`, they jump to the same location as exceptions, therefore the +user software interrupt handler must also handle exceptions. + +The vector table is defined in `vectors.S` and may jump to one of the +following interrupt request handlers in `handlers.S`: + * `u_sw_irq_handler` - handles user software interrupts and all exceptions. + Saves all caller saved registers then checks `mcause` and jumps to the + appropriate handler as follows: + - Breakpoint: jump to `handle_ebreak`. + - Illegal instruction: jump to `handle_illegal`. + - Environment call from M-mode: jump to `handle_ecall`. + - Any other exception or user software interrupt: jump to `handle_unknown`. + * `m_software_irq_handler` - handles machine-mode software interrupts + - Currently jumps to `__no_irq_handler`. Behavior to be defined in future commit. + * `m_timer_irq_handler` - handles machine-mode timer interrupts + - Currently jumps to `__no_irq_handler`. Behavior to be defined in future commit. + * `m_external_irq_handler` - handles machine-mode external interrupts + - Currently jumps to `__no_irq_handler`. Behavior to be defined in future commit. + * `m_fast0_irq_handler` - handles machine-mode fast external interrupts (platform extension for CV32) + - Currently jumps to `__no_irq_handler`. Behavior to be defined in future commit. + * `m_fast1_irq_handler` - handles machine-mode fast external interrupts (platform extension for CV32) + - Currently jumps to `__no_irq_handler`. Behavior to be defined in future commit. + * `m_fast2_irq_handler` - handles machine-mode fast external interrupts (platform extension for CV32) + - Currently jumps to `__no_irq_handler`. Behavior to be defined in future commit. + * `m_fast3_irq_handler` - handles machine-mode fast external interrupts (platform extension for CV32) + - Currently jumps to `__no_irq_handler`. Behavior to be defined in future commit. + * `m_fast4_irq_handler` - handles machine-mode fast external interrupts (platform extension for CV32) + - Currently jumps to `__no_irq_handler`. Behavior to be defined in future commit. + * `m_fast5_irq_handler` - handles machine-mode fast external interrupts (platform extension for CV32) + - Currently jumps to `__no_irq_handler`. Behavior to be defined in future commit. + * `m_fast6_irq_handler` - handles machine-mode fast external interrupts (platform extension for CV32) + - Currently jumps to `__no_irq_handler`. Behavior to be defined in future commit. + * `m_fast7_irq_handler` - handles machine-mode fast external interrupts (platform extension for CV32) + - Currently jumps to `__no_irq_handler`. Behavior to be defined in future commit. + * `m_fast8_irq_handler` - handles machine-mode fast external interrupts (platform extension for CV32) + - Currently jumps to `__no_irq_handler`. Behavior to be defined in future commit. + * `m_fast9_irq_handler` - handles machine-mode fast external interrupts (platform extension for CV32) + - Currently jumps to `__no_irq_handler`. Behavior to be defined in future commit. + * `m_fast10_irq_handler` - handles machine-mode fast external interrupts (platform extension for CV32) + - Currently jumps to `__no_irq_handler`. Behavior to be defined in future commit. + * `m_fast11_irq_handler` - handles machine-mode fast external interrupts (platform extension for CV32) + - Currently jumps to `__no_irq_handler`. Behavior to be defined in future commit. + * `m_fast12_irq_handler` - handles machine-mode fast external interrupts (platform extension for CV32) + - Currently jumps to `__no_irq_handler`. Behavior to be defined in future commit. + * `m_fast13_irq_handler` - handles machine-mode fast external interrupts (platform extension for CV32) + - Currently jumps to `__no_irq_handler`. Behavior to be defined in future commit. + * `m_fast14_irq_handler` - handles machine-mode fast external interrupts (platform extension for CV32) + - Currently jumps to `__no_irq_handler`. Behavior to be defined in future commit. + * `m_fast15_irq_handler` - handles machine-mode fast external interrupts (platform extension for CV32) + - Currently jumps to `__no_irq_handler`. Behavior to be defined in future commit. + * `__no_irq_handler` - loops printing "no exception handler installed". + +The following exception handlers may be called from `u_sw_irq_handler`: + * `handle_ecall` - calls `handle_syscall` which checks the syscall number and + calls the corresponding syscall function. + * `handle_ebreak` - currently just prints "ebreak exception handler entered" + * `handle_illegal_insn` - prints "illegal instruction exception handler + entered" + * `unknown_handler` - called when there is no handler for the interrupt/ + exception. This is the only case where `mepc` is not incremented, because we + do not know the appropiate action to take. + +Returning from the `u_sw_irq_handler`. All handlers called by `u_sw_irq_handler` +increment `mepc` before calling `mret`, except for `unknown_handler`. Handlers +that require `mepc` to be incremented jump to `end_handler_incr_mepc` otherwise +they jump to `end_handler_ret`. All caller saved registers are restored before +finally calling `mret`. + +Some test cases require the ability to override the default handlers. In future, +these handlers will be made overridable by defining their labels as `.weak` +symbols. Test cases can then provide their own handlers where necessary. + +System Calls +------------ + +On a bare-metal system there is no OS to handle system calls, therefore, we +define our own system calls in `syscalls.c`. For example, the implementation of +`_write` outputs a byte at a time to the virtual printer peripheral. Many of the +functions provide minimal implementations that simply fail gracefully due to +lack of necessary OS support e.g. no file system. + +The [RISC-V Instruction Set Manual Volume I: Unprivileged ISA Version 20191213]( +https://content.riscv.org/wp-content/uploads/2019/06/riscv-spec.pdf) states that +for an `ecall` the "ABI for the system will define how parameters for the +environment request are passed". This BSP follows the convention used for RISC-V +in `newlib`. Parameters are passed in registers `a0` to `a5` and system call ID +in `a7` (`t0` on RV32E). When handling an `ecall`, `handle_ecall` calls +`handle_syscall` which then calls the appropriate function that implements the +system call, passing parameters as necessary. + +Linker Script +------------- + +The linker script defines the memory layout and controls the mapping of input +sections from object files to output sections in the output binary. + +The `link.ld` script is based on the standard upstream RV32 linker script, with +some changes required for CV32: + * Memory layout is defined as follows: + * `ram` start=0x0, length=4MB + * `dbg` start=0x1A110800, length=2KB + * Changes to output section placement are as follows: + - `.vectors` start=ORIGIN(`ram`) + - `.init` start=0x80 + - `.heap` starts at end of data and grows upwards + - `.stack` starts at the end of `ram` and grows downwards + - `.debugger` start=ORIGIN(`dbg`) + - `.debugger_exception` start=0x1A110C00 + - `.debugger_stack` follows `.debugger_exception` + +Building and using the BSP Library +---------------------------------- + +The BSP can be built in this directory as follows: +``` +make +``` +This produces libcv-verif.a which can then be linked with a test program as +follows: + +``` +gcc test-program.c -nostartfiles -T/path/to/bsp/link.ld -L/path/to/bsp/ -lcv-verif +``` diff --git a/verif/bsp/crt0.S b/verif/bsp/crt0.S new file mode 100644 index 0000000000..302da07ce3 --- /dev/null +++ b/verif/bsp/crt0.S @@ -0,0 +1,72 @@ +/* Copyright (c) 2017 SiFive Inc. All rights reserved. + * Copyright (c) 2019 ETH Zürich and University of Bologna + * This copyrighted material is made available to anyone wishing to use, + * modify, copy, or redistribute it subject to the terms and conditions + * of the FreeBSD License. This program is distributed in the hope that + * it will be useful, but WITHOUT ANY WARRANTY expressed or implied, + * including the implied warranties of MERCHANTABILITY or FITNESS FOR + * A PARTICULAR PURPOSE. A copy of this license is available at + * http://www.opensource.org/licenses. + */ +/* Make sure the vector table gets linked into the binary. */ +.global vector_table + +/* Entry point for bare metal programs */ +.section .text.start +.global _start +.type _start, @function + +_start: +/* initialize global pointer */ +.option push +.option norelax +1: auipc gp, %pcrel_hi(__global_pointer$) + addi gp, gp, %pcrel_lo(1b) +.option pop + +/* initialize stack pointer */ + la sp, __stack_end + +/* set vector table address */ + la a0, __vector_start + ori a0, a0, 1 /*vector mode = vectored */ + csrw mtvec, a0 + +/* clear the bss segment */ + la a0, _edata + la a2, _end + sub a2, a2, a0 + li a1, 0 + call memset + +/* new-style constructors and destructors */ + la a0, __libc_fini_array + call atexit + call __libc_init_array + +/* call main */ +// lw a0, 0(sp) /* a0 = argc */ +// addi a1, sp, __SIZEOF_POINTER__ /* a1 = argv */ +// li a2, 0 /* a2 = envp = NULL */ +// Initialize these variables to 0. Cannot use argc or argv +// since the stack is not initialized + li a0, 0 + li a1, 0 + li a2, 0 + + call main + tail exit + +.size _start, .-_start + +.global _init +.type _init, @function +.global _fini +.type _fini, @function +_init: +_fini: + /* These don't have to do anything since we use init_array/fini_array. Prevent + missing symbol error */ + ret +.size _init, .-_init +.size _fini, .-_fini diff --git a/verif/bsp/handlers.S b/verif/bsp/handlers.S new file mode 100644 index 0000000000..6068105276 --- /dev/null +++ b/verif/bsp/handlers.S @@ -0,0 +1,223 @@ +/* +* Copyright 2019 ETH Zürich and University of Bologna +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*/ + +/* Exception codes */ +#define EXCEPTION_ILLEGAL_INSN 2 +#define EXCEPTION_BREAKPOINT 3 +#define EXCEPTION_ECALL_M 11 + +.section .text.handlers +.global __no_irq_handler +.global u_sw_irq_handler +.global m_software_irq_handler +.global m_timer_irq_handler +.global m_external_irq_handler +.global m_fast0_irq_handler +.global m_fast1_irq_handler +.global m_fast2_irq_handler +.global m_fast3_irq_handler +.global m_fast4_irq_handler +.global m_fast5_irq_handler +.global m_fast6_irq_handler +.global m_fast7_irq_handler +.global m_fast8_irq_handler +.global m_fast9_irq_handler +.global m_fast10_irq_handler +.global m_fast11_irq_handler +.global m_fast12_irq_handler +.global m_fast13_irq_handler +.global m_fast14_irq_handler +.global m_fast15_irq_handler + +.weak u_sw_irq_handler +.weak m_software_irq_handler +.weak m_timer_irq_handler +.weak m_external_irq_handler +.weak m_fast0_irq_handler +.weak m_fast1_irq_handler +.weak m_fast2_irq_handler +.weak m_fast3_irq_handler +.weak m_fast4_irq_handler +.weak m_fast5_irq_handler +.weak m_fast6_irq_handler +.weak m_fast7_irq_handler +.weak m_fast8_irq_handler +.weak m_fast9_irq_handler +.weak m_fast10_irq_handler +.weak m_fast11_irq_handler +.weak m_fast12_irq_handler +.weak m_fast13_irq_handler +.weak m_fast14_irq_handler +.weak m_fast15_irq_handler + + +/* exception handling */ +__no_irq_handler: + la a0, no_exception_handler_msg + jal ra, puts + j __no_irq_handler + +m_software_irq_handler: + j __no_irq_handler + +m_timer_irq_handler: + j __no_irq_handler + +m_external_irq_handler: + j __no_irq_handler + +m_fast0_irq_handler: + j __no_irq_handler + +m_fast1_irq_handler: + j __no_irq_handler + +m_fast2_irq_handler: + j __no_irq_handler + +m_fast3_irq_handler: + j __no_irq_handler + +m_fast4_irq_handler: + j __no_irq_handler + +m_fast5_irq_handler: + j __no_irq_handler + +m_fast6_irq_handler: + j __no_irq_handler + +m_fast7_irq_handler: + j __no_irq_handler + +m_fast8_irq_handler: + j __no_irq_handler + +m_fast9_irq_handler: + j __no_irq_handler + +m_fast10_irq_handler: + j __no_irq_handler + +m_fast11_irq_handler: + j __no_irq_handler + +m_fast12_irq_handler: + j __no_irq_handler + +m_fast13_irq_handler: + j __no_irq_handler + +m_fast14_irq_handler: + j __no_irq_handler + +m_fast15_irq_handler: + j __no_irq_handler + +u_sw_irq_handler: + /* While we are still using puts in handlers, save all caller saved + regs. Eventually, some of these saves could be deferred. */ + addi sp,sp,-64 + sw ra, 0(sp) + sw a0, 4(sp) + sw a1, 8(sp) + sw a2, 12(sp) + sw a3, 16(sp) + sw a4, 20(sp) + sw a5, 24(sp) + sw a6, 28(sp) + sw a7, 32(sp) + sw t0, 36(sp) + sw t1, 40(sp) + sw t2, 44(sp) + sw t3, 48(sp) + sw t4, 52(sp) + sw t5, 56(sp) + sw t6, 60(sp) + csrr t0, mcause + li t1, EXCEPTION_ILLEGAL_INSN + beq t0, t1, handle_illegal_insn + li t1, EXCEPTION_ECALL_M + beq t0, t1, handle_ecall + li t1, EXCEPTION_BREAKPOINT + beq t0, t1, handle_ebreak + j handle_unknown + +handle_ecall: + jal ra, handle_syscall + j end_handler_incr_mepc + +handle_ebreak: + /* TODO support debug handling requirements. */ + la a0, ebreak_msg + jal ra, puts + j end_handler_incr_mepc + +handle_illegal_insn: + la a0, illegal_insn_msg + jal ra, puts + j end_handler_incr_mepc + +handle_unknown: + la a0, unknown_msg + jal ra, puts + /* We don't know what interrupt/exception is being handled, so don't + increment mepc. */ + j end_handler_ret + +end_handler_incr_mepc: + csrr t0, mepc + lb t1, 0(t0) + li a0, 0x3 + and t1, t1, a0 + /* Increment mepc by 2 or 4 depending on whether the instruction at mepc + is compressed or not. */ + bne t1, a0, end_handler_incr_mepc2 + addi t0, t0, 2 +end_handler_incr_mepc2: + addi t0, t0, 2 + csrw mepc, t0 +end_handler_ret: + lw ra, 0(sp) + lw a0, 4(sp) + lw a1, 8(sp) + lw a2, 12(sp) + lw a3, 16(sp) + lw a4, 20(sp) + lw a5, 24(sp) + lw a6, 28(sp) + lw a7, 32(sp) + lw t0, 36(sp) + lw t1, 40(sp) + lw t2, 44(sp) + lw t3, 48(sp) + lw t4, 52(sp) + lw t5, 56(sp) + lw t6, 60(sp) + addi sp,sp,64 + mret + +.section .rodata +illegal_insn_msg: + .string "CV32E40P BSP: illegal instruction exception handler entered\n" +ecall_msg: + .string "CV32E40P BSP: ecall exception handler entered\n" +ebreak_msg: + .string "CV32E40P BSP: ebreak exception handler entered\n" +unknown_msg: + .string "CV32E40P BSP: unknown exception handler entered\n" +no_exception_handler_msg: + .string "CV32E40P BSP: no exception handler installed\n" diff --git a/verif/bsp/link.ld b/verif/bsp/link.ld new file mode 100644 index 0000000000..9ea197dbf5 --- /dev/null +++ b/verif/bsp/link.ld @@ -0,0 +1,311 @@ +/* Script for -z combreloc */ +/* Copyright (C) 2014-2020 Free Software Foundation, Inc. + Copyright (C) 2019 ETH Zürich and University of Bologna + Copyright (C) 2020 OpenHW Group + Copying and distribution of this script, with or without modification, + are permitted in any medium without royalty provided the copyright + notice and this notice are preserved. */ + +/* This linker script is adapted from the default linker script for upstream + RISC-V GCC. It has been modified for use in verification of CORE-V cores. +*/ + +OUTPUT_FORMAT("elf32-littleriscv", "elf32-littleriscv", + "elf32-littleriscv") +OUTPUT_ARCH(riscv) +ENTRY(_start) + +/* CORE-V */ +MEMORY +{ + /* Our testbench is a bit weird in that we initialize the RAM (thus + allowing initialized sections to be placed there). Infact we dump all + sections to ram. */ + + ram (rwxai) : ORIGIN = 0x00000000, LENGTH = 0x400000 + dbg (rwxai) : ORIGIN = 0x1A110800, LENGTH = 0x1000 +} + +SECTIONS +{ + /* CORE-V Debugger Code: This section address must be the same as the + DM_HaltAddress parameter in the RTL */ + .debugger (ORIGIN(dbg)): + { + KEEP(*(.debugger)); + } >dbg + .debugger_exception (0x1A111000): + { + KEEP(*(.debugger_exception)); + } >dbg + /* Debugger Stack*/ + .debugger_stack : ALIGN(16) + { + PROVIDE(__debugger_stack_start = .); + . = 0x80; + } >dbg + + /* CORE-V: we want a fixed entry point */ + PROVIDE(__boot_address = 0x80); + + /* CORE-V: interrupt vectors */ + .vectors (ORIGIN(ram)): + { + PROVIDE(__vector_start = .); + KEEP(*(.vectors)); + } >ram + + /* CORE-V: crt0 init code */ + .init (__boot_address): + { + KEEP (*(SORT_NONE(.init))) + KEEP (*(.text.start)) + } >ram + + /* Read-only sections, merged into text segment: */ + PROVIDE (__executable_start = SEGMENT_START("text-segment", 0x10000)); . = SEGMENT_START("text-segment", 0x10000) + SIZEOF_HEADERS; + .interp : { *(.interp) } >ram + .note.gnu.build-id : { *(.note.gnu.build-id) } >ram + .hash : { *(.hash) } >ram + .gnu.hash : { *(.gnu.hash) } >ram + .dynsym : { *(.dynsym) } >ram + .dynstr : { *(.dynstr) } >ram + .gnu.version : { *(.gnu.version) } >ram + .gnu.version_d : { *(.gnu.version_d) } >ram + .gnu.version_r : { *(.gnu.version_r) } >ram + .rela.dyn : + { + *(.rela.init) + *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) + *(.rela.fini) + *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) + *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) + *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) + *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) + *(.rela.ctors) + *(.rela.dtors) + *(.rela.got) + *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*) + *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*) + *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*) + *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*) + *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) + PROVIDE_HIDDEN (__rela_iplt_start = .); + *(.rela.iplt) + PROVIDE_HIDDEN (__rela_iplt_end = .); + } >ram + .rela.plt : + { + *(.rela.plt) + } >ram + + .plt : { *(.plt) } + .iplt : { *(.iplt) } + .text : + { + *(.text.unlikely .text.*_unlikely .text.unlikely.*) + *(.text.exit .text.exit.*) + *(.text.startup .text.startup.*) + *(.text.hot .text.hot.*) + *(SORT(.text.sorted.*)) + *(.text .stub .text.* .gnu.linkonce.t.*) + /* .gnu.warning sections are handled specially by elf.em. */ + *(.gnu.warning) + } >ram + .fini : + { + KEEP (*(SORT_NONE(.fini))) + } >ram + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + .rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) } >ram + .rodata1 : { *(.rodata1) } >ram + .sdata2 : + { + *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) + } >ram + .sbss2 : { *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*) } >ram + .eh_frame_hdr : { *(.eh_frame_hdr) *(.eh_frame_entry .eh_frame_entry.*) } >ram + .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) *(.eh_frame.*) } >ram + .gcc_except_table : ONLY_IF_RO { *(.gcc_except_table .gcc_except_table.*) } >ram + .gnu_extab : ONLY_IF_RO { *(.gnu_extab*) } >ram + /* These sections are generated by the Sun/Oracle C++ compiler. */ + .exception_ranges : ONLY_IF_RO { *(.exception_ranges*) } + /* Adjust the address for the data segment. We want to adjust up to + the same address within the page on the next page up. */ + . = DATA_SEGMENT_ALIGN (CONSTANT (MAXPAGESIZE), CONSTANT (COMMONPAGESIZE)); + /* Exception handling */ + .eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) *(.eh_frame.*) } >ram + .gnu_extab : ONLY_IF_RW { *(.gnu_extab) } >ram + .gcc_except_table : ONLY_IF_RW { *(.gcc_except_table .gcc_except_table.*) } >ram + .exception_ranges : ONLY_IF_RW { *(.exception_ranges*) } >ram + /* Thread Local Storage sections */ + .tdata : + { + PROVIDE_HIDDEN (__tdata_start = .); + *(.tdata .tdata.* .gnu.linkonce.td.*) + } >ram + .tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >ram + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >ram + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >ram + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >ram + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >ram + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >ram + .jcr : { KEEP (*(.jcr)) } + .data.rel.ro : { *(.data.rel.ro.local* .gnu.linkonce.d.rel.ro.local.*) *(.data.rel.ro .data.rel.ro.* .gnu.linkonce.d.rel.ro.*) } + .dynamic : { *(.dynamic) } + . = DATA_SEGMENT_RELRO_END (0, .); + .data : + { + __DATA_BEGIN__ = .; + *(.data .data.* .gnu.linkonce.d.*) + SORT(CONSTRUCTORS) + } >ram + .data1 : { *(.data1) } >ram + .got : { *(.got.plt) *(.igot.plt) *(.got) *(.igot) } + /* We want the small data sections together, so single-instruction offsets + can access them all, and initialized data all before uninitialized, so + we can shorten the on-disk segment size. */ + .sdata : + { + __SDATA_BEGIN__ = .; + *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) + *(.sdata .sdata.* .gnu.linkonce.s.*) + } >ram + _edata = .; PROVIDE (edata = .); + . = .; + __bss_start = .; + .sbss : + { + *(.dynsbss) + *(.sbss .sbss.* .gnu.linkonce.sb.*) + *(.scommon) + } >ram + .bss : + { + *(.dynbss) + *(.bss .bss.* .gnu.linkonce.b.*) + *(COMMON) + /* Align here to ensure that the .bss section occupies space up to + _end. Align after .bss to ensure correct alignment even if the + .bss section disappears because there are no input sections. + FIXME: Why do we need it? When there is no .bss section, we do not + pad the .data section. */ + . = ALIGN(. != 0 ? 32 / 8 : 1); + } >ram + . = ALIGN(32 / 8); + . = SEGMENT_START("ldata-segment", .); + . = ALIGN(32 / 8); + __bss_end = .; + __global_pointer$ = MIN(__SDATA_BEGIN__ + 0x800, + MAX(__DATA_BEGIN__ + 0x800, __bss_end - 0x800)); + _end = .; PROVIDE (end = .); + . = DATA_SEGMENT_END (.); + + /* Heap grows upward towards end of ram */ + .heap : ALIGN(16) + { + PROVIDE(__heap_start = .); + /* If end of ram is not 16-byte aligned, align to previous 16-byte + boundary */ + PROVIDE(__heap_end = ALIGN(ORIGIN(ram) + LENGTH(ram) - __heap_start - 15, 16)); + . = __heap_end; + } >ram + + /* Stack grows downward from end of ram */ + .stack (__heap_start) : ALIGN(16) /* this is a requirement of the ABI(?) */ + { + PROVIDE(__stack_start = __heap_start); + . = __heap_end; + PROVIDE(__stack_end = .); + } >ram + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .gnu.build.attributes : { *(.gnu.build.attributes .gnu.build.attributes.*) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line .debug_line.* .debug_line_end) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + /* DWARF 3 */ + .debug_pubtypes 0 : { *(.debug_pubtypes) } + .debug_ranges 0 : { *(.debug_ranges) } + /* DWARF Extension. */ + .debug_macro 0 : { *(.debug_macro) } + .debug_addr 0 : { *(.debug_addr) } + .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) } + /DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) } +} + diff --git a/verif/bsp/syscalls.c b/verif/bsp/syscalls.c new file mode 100644 index 0000000000..36ffac37da --- /dev/null +++ b/verif/bsp/syscalls.c @@ -0,0 +1,376 @@ +/* An extremely minimalist syscalls.c for newlib + * Based on riscv newlib libgloss/riscv/sys_*.c + * + * Copyright 2019 Claire Wolf + * Copyright 2019 ETH Zürich and University of Bologna + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#include <sys/stat.h> +#include <sys/timeb.h> +#include <sys/times.h> +#include <sys/utime.h> +#include <newlib.h> +#include <unistd.h> +#include <errno.h> +#include <machine/syscall.h> +#include <assert.h> +#undef errno +extern int errno; + +/* write to this reg for outputting strings */ +#define STDOUT_REG 0x10000000 +/* write test result of program to this reg */ +#define RESULT_REG 0x20000000 +/* write exit value of program to this reg */ +#define EXIT_REG 0x20000004 + +#define STDOUT_FILENO 1 + +/* It turns out that older newlib versions use different symbol names which goes + * against newlib recommendations. Anyway this is fixed in later version. + */ +#if __NEWLIB__ <= 2 && __NEWLIB_MINOR__ <= 5 +#define _sbrk sbrk +#define _write write +#define _close close +#define _lseek lseek +#define _read read +#define _fstat fstat +#define _isatty isatty +#endif +/* Upstream newlib now defines this in libgloss/riscv/internal_syscall.h. */ +long +__syscall_error(long a0) +{ + errno = -a0; + return -1; +} + +void unimplemented_syscall() +{ + const char *p = "BSP: Unimplemented system call called!\n"; + while (*p) + *(volatile int *)STDOUT_REG = *(p++); +} + +int nanosleep(const struct timespec *rqtp, struct timespec *rmtp) +{ + errno = ENOSYS; + return -1; +} + +int _access(const char *file, int mode) +{ + errno = ENOSYS; + return -1; +} + +int _chdir(const char *path) +{ + errno = ENOSYS; + return -1; +} + +int _chmod(const char *path, mode_t mode) +{ + errno = ENOSYS; + return -1; +} + +int _chown(const char *path, uid_t owner, gid_t group) +{ + errno = ENOSYS; + return -1; +} + +int _close(int file) +{ + return -1; +} + +int _execve(const char *name, char *const argv[], char *const env[]) +{ + errno = ENOMEM; + return -1; +} + +void _exit(int exit_status) +{ + *(volatile int *)EXIT_REG = exit_status; + asm volatile("wfi"); + /* _exit should not return */ + while (1) {}; +} + +int _faccessat(int dirfd, const char *file, int mode, int flags) +{ + errno = ENOSYS; + return -1; +} + +int _fork(void) +{ + errno = EAGAIN; + return -1; +} + +int _fstat(int file, struct stat *st) +{ + st->st_mode = S_IFCHR; + return 0; + // errno = -ENOSYS; + // return -1; +} + +int _fstatat(int dirfd, const char *file, struct stat *st, int flags) +{ + errno = ENOSYS; + return -1; +} + +int _ftime(struct timeb *tp) +{ + errno = ENOSYS; + return -1; +} + +char *_getcwd(char *buf, size_t size) +{ + errno = -ENOSYS; + return NULL; +} + +int _getpid() +{ + return 1; +} + +int _gettimeofday(struct timeval *tp, void *tzp) +{ + errno = -ENOSYS; + return -1; +} + +int _isatty(int file) +{ + return (file == STDOUT_FILENO); +} + +int _kill(int pid, int sig) +{ + errno = EINVAL; + return -1; +} + +int _link(const char *old_name, const char *new_name) +{ + errno = EMLINK; + return -1; +} + +off_t _lseek(int file, off_t ptr, int dir) +{ + return 0; +} + +int _lstat(const char *file, struct stat *st) +{ + errno = ENOSYS; + return -1; +} + +int _open(const char *name, int flags, int mode) +{ + return -1; +} + +int _openat(int dirfd, const char *name, int flags, int mode) +{ + errno = ENOSYS; + return -1; +} + +ssize_t _read(int file, void *ptr, size_t len) +{ + return 0; +} + +int _stat(const char *file, struct stat *st) +{ + st->st_mode = S_IFCHR; + return 0; + // errno = ENOSYS; + // return -1; +} + +long _sysconf(int name) +{ + + return -1; +} + +clock_t _times(struct tms *buf) +{ + return -1; +} + +int _unlink(const char *name) +{ + errno = ENOENT; + return -1; +} + +int _utime(const char *path, const struct utimbuf *times) +{ + errno = ENOSYS; + return -1; +} + +int _wait(int *status) +{ + errno = ECHILD; + return -1; +} + +ssize_t _write(int file, const void *ptr, size_t len) +{ + const char *cptr = (char *)ptr; + if (file != STDOUT_FILENO) + { + errno = ENOSYS; + return -1; + } + + const void *eptr = cptr + len; + while (cptr != eptr) + *(volatile int *)STDOUT_REG = *cptr++; + return len; +} + +extern char __heap_start[]; +extern char __heap_end[]; +static char *brk = __heap_start; + +int _brk(void *addr) +{ + brk = addr; + return 0; +} + +void *_sbrk(ptrdiff_t incr) +{ + char *old_brk = brk; + register long sp asm("sp"); + + char *new_brk = brk += incr; + if (new_brk < (char *) sp && new_brk < __heap_end) + { + brk = new_brk; + + return old_brk; + } + else + { + errno = ENOMEM; + return (void *) -1; + } +} + +void handle_syscall (long a0, + long a1, + long a2, + long a3, + __attribute__((unused)) long a4, + __attribute__((unused)) long a5, + __attribute__((unused)) long a6, + long a7) { + #ifdef __riscv_32e + register long syscall_id asm("t0"); + #else + long syscall_id = a7; + #endif + + switch (syscall_id) { + case SYS_exit: + _exit (a0); + break; + case SYS_read: + _read (a0, (void *) a1, a2); + break; + case SYS_write: + _write (a0, (const void *) a1, a2); + break; + case SYS_getpid: + _getpid (); + break; + case SYS_kill: + _kill (a0, a1); + break; + case SYS_open: + _open ((const char *) a0, a1, a2); + break; + case SYS_openat: + _openat (a0, (const char *) a1, a2, a3); + break; + case SYS_close: + _close (a0); + break; + case SYS_lseek: + _lseek (a0, a1, a2); + break; + case SYS_brk: + _brk ((void *) a0); + break; + case SYS_link: + _link ((const char *) a0, (const char *) a1); + break; + case SYS_unlink: + _unlink ((const char *) a0); + break; + case SYS_chdir: + _chdir ((const char *) a0); + break; + case SYS_getcwd: + _getcwd ((char *) a0, a1); + break; + case SYS_stat: + _stat ((const char *) a0, (struct stat *) a1); + break; + case SYS_fstat: + _fstat (a0, (struct stat *) a1); + break; + case SYS_lstat: + _lstat ((const char *) a0, (struct stat *) a1); + break; + case SYS_fstatat: + _fstatat (a0, (const char *) a1, (struct stat *) a2, a3); + break; + case SYS_access: + _access ((const char *) a0, a1); + break; + case SYS_faccessat: + _faccessat (a0, (const char *) a1, a2, a3); + break; + case SYS_gettimeofday: + _gettimeofday ((struct timeval *) a0, (void *) a1); + break; + case SYS_times: + _times ((struct tms *) a0); + break; + default: + unimplemented_syscall (); + break; + } +} diff --git a/verif/bsp/useful_sites.txt b/verif/bsp/useful_sites.txt new file mode 100644 index 0000000000..c674db240d --- /dev/null +++ b/verif/bsp/useful_sites.txt @@ -0,0 +1,2 @@ +Google "RISC-V startup code" +https://twilco.github.io/riscv-from-scratch/2019/04/27/riscv-from-scratch-2.html diff --git a/verif/bsp/vectors.S b/verif/bsp/vectors.S new file mode 100644 index 0000000000..08af4128ae --- /dev/null +++ b/verif/bsp/vectors.S @@ -0,0 +1,54 @@ +/* +* Copyright 2019 ETH Zürich and University of Bologna +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*/ + +.section .vectors, "ax" +.option norvc +.global vector_table + +vector_table: + j u_sw_irq_handler + j __no_irq_handler + j __no_irq_handler + j m_software_irq_handler + j __no_irq_handler + j __no_irq_handler + j __no_irq_handler + j m_timer_irq_handler + j __no_irq_handler + j __no_irq_handler + j __no_irq_handler + j m_external_irq_handler + j __no_irq_handler + j __no_irq_handler + j __no_irq_handler + j __no_irq_handler + j m_fast0_irq_handler + j m_fast1_irq_handler + j m_fast2_irq_handler + j m_fast3_irq_handler + j m_fast4_irq_handler + j m_fast5_irq_handler + j m_fast6_irq_handler + j m_fast7_irq_handler + j m_fast8_irq_handler + j m_fast9_irq_handler + j m_fast10_irq_handler + j m_fast11_irq_handler + j m_fast12_irq_handler + j m_fast13_irq_handler + j m_fast14_irq_handler + j m_fast15_irq_handler + diff --git a/verif/core-v-verif b/verif/core-v-verif new file mode 160000 index 0000000000..d5e2c2206c --- /dev/null +++ b/verif/core-v-verif @@ -0,0 +1 @@ +Subproject commit d5e2c2206c3fead5478fb4e09fb8446146b24b08 diff --git a/verif/docs/UVM_verif_env.md b/verif/docs/UVM_verif_env.md new file mode 100644 index 0000000000..cbd638e45a --- /dev/null +++ b/verif/docs/UVM_verif_env.md @@ -0,0 +1,222 @@ +<!--_ Copyright (c) 2023 10x-Engineers + SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + --> +# The CVA6 UVM Verification Environment + + +This document describes the uvm verification environment of the CVA6 core. This environment is intended to be able to verify the CVA6 core and run different test cases by the minimal modification to the environment itself. The environment is shown below: + +![alt_text](images/CVA6_env.drawio.drawio.png "image_tooltip") + +*** + +This environment consist of the following + +1. Simple two uvm agents for the uvma_clknrst_if and uvma_cvxif_intf . +2. Result checking capability is built into the environment so the test cases do not need to determine and check for the pass/fail criteria. + +The environment consists of disjoint components. When a user invokes a command to run a test case a set of scripts and makefile rules are invoked to compile the environment and tests, run the simulation and check the results. On running a particular test it generates a .bin file which then is loaded into the main memory in the tb_top at the Boot_address of the core and the instructions are then start executing. + +## uvmt_cva6_tb + +In this module we instantiate the agent interfaces and the `uvmt_cva6_dut_wrap` module. We set the interfaces for the uvma_clknrst and uvma_cvxif using the configuration database set method. In this module we get the `sim_finished` database object set in the `uvmt_cva6_base_test_c` class. To check whether the simulation passed or failed we check the `err_count` and `fatal_count` along with `sim_finished`. + +## uvmt_cva6_base_test_c + +This class extends from `uvm_test`. It randomise the `uvmt_cva6_test_cfg_c` and `uvme_cva6_cfg_c` objects. The class's build_phase, connect_phase functions handle the setup and configuration of the testbench environment, connecting it to the CVA6, and executing the test. We start the `uvme_cva6_reset_vseq_c` sequence in the reset phase on the `uvme_cva6_vsqr_c` sequencer. + +## uvme_cva6_env_c + +This class extends from the `uvm_env` class. The class's build_phase,connect_phase functions handle the setup and configuration of the `uvma_clknrst_agent_c`,`uvma_cvxif_agent_c` agents.The class's run_phase task start the `cvxif_seq` sequence on the uvma_cvxif_agent sequencer. We get the configuration and context information for the environment in this class using the get method. + +### Environment_objects + +There are two uvm_objects that are `uvme_cva6_cfg_c` and `uvme_cva6_cntxt_c`. The Objects contain configuration and context information for the environment. + +### uvme_cva6_cfg_c + +This class extends from the `uvm_object` class. The object encapsulates all parameters for creating, connecting and running CVA6 environment (`uvme_cva6_env_c`) components. This class also includes a constraint block that defines default values for some of its fields and other constraints on its fields such as, `enabled` and `is_active` fields are set to 0 and 'UVM_PASSIVE' respectively by default. `clknrst_cfg.enabled` and `clknrst_cfg.is_active` are set to 1 if `enabled` and `is_active` fields are set to 1. `clknrst_cfg.trn_log_enabled` is set to 1 if `trn_log_enabled` is set to 1. `cvxif_cfg.cov_model_enabled` is set to 1 if `cov_model_enabled` is set to 1. + +<table> + <tr> + <td><strong>signal</strong> + </td> + <td><strong>Description</strong> + </td> + </tr> + <tr> + <td>enabled + </td> + <td> is set to 1, the environment is enabled and the components within the environment can be instantiated, built, and connected. + </td> + </tr> + <tr> + <td>is_active + </td> + <td>This is set to UVM_PASSIVE. + </td> + </tr> + <tr> + <td>scoreboarding_enabled + </td> + <td> It enables the scoreboard and predictor in the environment class. + </td> + </tr> + <tr> + <td>cov_model_enabled + </td> + <td> It enables the coverage collection for environment and cvxif_agent. + </td> + </tr> + <tr> + <td>trn_log_enabled + </td> + <td> It enables the trace log for the clk_rst_agent + </td> + </tr> +</table> + +### uvme_cva6_cntxt_c + +The class uvme_cva6_cntxt_c is an object that encapsulates all state variables for CVA6 environment (`uvme_cva6_env_c`) components. It inherits from the `uvm_object` base class.It also contains two events, `sample_cfg_e` and `sample_cntxt_e`, that can be used to synchronize the sampling of configuration and context information. + +### uvme_cva6_vsqr_c + +This class extends from the `uvm_sequencer` base class. It also has two sequencer handles, "clknrst_sequencer" and "cvxif_sequencer" of the types `uvma_clknrst_sqr_c` and `uvma_cvxif_sqr_c`, respectively. This class is used to start the virtual sequence. + +### uvme_cva6_reset_vseq_c + +This class `uvme_cva6_reset_vseq_c` extends a class called `uvme_cva6_base_vseq_c`. The purpose of this sequence is to start the system clock and issue the initial reset pulse to the Device Under Test (DUT). The class has three random variables, `num_clk_before_reset`, `rst_deassert_period`, and `post_rst_wait`. These variables are used to specify the number of clock cycles between the start of the clock and the reset assert.The class has a default constructor and a virtual task called "body" which is responsible for starting the clock, waiting for a specified amount of time, and then resetting the DUT. + +## Clock & Reset Agent + + This agent controls the clock and reset signal of the CVA6 core. + +### uvma_clknrst_if + +The `uvma_clknrst_if` interface has two logic signals, `clk` and `reset_n`. The `clk` signal represents the system clock, while the `reset_n` signal is the active-low reset signal.The interface includes an initial block that contains a forever loop that generates the clock signal, based on the value of `clk_active` and `clk_period`. If `clk_active` is set to 1 and `clk_period` is 0, the function will raise a fatal error. The interface also includes three functions: set_period, which sets the value of `clk_period`; start_clk, which sets `clk_active` to 1; and stop_clk, which sets `clk_active` to 0. + +<table> + <tr> + <td><strong>signal</strong> + </td> + <td><strong>Description</strong> + </td> + </tr> + <tr> + <td>clk + </td> + <td>Controls the Clock fed to the design under test. + </td> + </tr> + <tr> + <td>reset_n + </td> + <td>Control the reset state of the design under test. + </td> + </tr> +</table> + +### uvma_clknrst_uvm_objects + +The uvm_objects `uvma_clknrst_cfg_c` , `uvma_clknrst_cntxt_c` contain the configuration and context information of the uvma_clknrst_agent. + +### uvma_clknrst_seq_item_c + +The class represents an object created by Clock & Reset agent sequences that extend the `uvma_clknrst_seq_base_c` class. + +The class contains several randomized variables: + +* `action` is an enumerated variable of type "uvma_clknrst_seq_item_action_enum" that represents the operation to perform (e.g. start clock, stop clock, assert reset, de-assert reset). +* `initial_value` is an enumerated variable of type "uvma_clknrst_seq_item_initial_value_enum" that represents the initial value of the signals (if starting or asserting). +* `clk_period` is an unsigned 32-bit integer variable representing the period of the clock signal. +* `rst_deassert_period` is an unsigned 32-bit integer variable representing the amount of time (in picoseconds) after which to de-assert reset. +* The class also includes a constraint "default_cons" which sets the default values for `clk_period` to 0 and `rst_deassert_period` to a value defined by `uvma_clknrst_default_rst_deassert_period` + +The class has a default constructor which calls the superclass constructor. + +### uvma_clknrst_Sequence + +It consists of two main sequences: `uvma_clknrst_stop_clk_seq_c` and `uvma_clknrst_restart_clk_seq_c`. + +* The `uvma_clknrst_stop_clk_seq_c` create an instance of the `uvma_clknrst_seq_item_c` and set the its action to the `UVMA_CLKNRST_SEQ_ITEM_ACTION_STOP_CLK` and start and finish the item. + +* The `uvma_clknrst_restart_clk_seq_c` create an instance of the `uvma_clknrst_seq_item_c` and set the its action to the `UVMA_CLKNRST_SEQ_ITEM_ACTION_RESTART_CLK` and start and finish the item. + +### uvma_clknrst_drv_c + +This class `uvma_clknrst_drv_c` is used for driving the interface of the clknrst agent. It get reqs from the sequence item port and calls the `drv_req` task. The `drv_req` task drives the virtual interface's (`cntxt.vif`) signals using req's contents. And then call the write method for the analysis port to send the req transaction to the coverage model. + +### uvma_clknrst_mon_c + +This class `uvma_clknrst_mon_c` is used for monitoring the virtual interface of the Clock & Reset agent. The class extends the `uvm_monitor` class and contains objects for configuration (cfg) and context (cntxt), as well as an analysis port (ap) for transaction analysis.The run_phase() task in the `uvma_clknrst_mon_c` class is responsible for overseeing the monitoring process of the Clock and Reset virtual interface. It does this by executing the monitor_clk() and monitor_reset() tasks in parallel forks. + +### uvma_clknrst_cov_model_c + +This class `uvma_clknrst_cov_model_c` extends from the `uvm_component` base class. The overall functionality of this class is to provide the coverage model for the clknrst_agent. It contains objects for configuration, context, monitor transaction, and sequence item, as well as two analysis FIFOs for holding transactions coming from the monitor and sequence item respectively. This section is in progress. + +### uvma_clknrst_agent_c + + This class `uvma_clknrst_agent_c` extends from `uvm_agent` base class. This class encapsulates ,builds and connects all the other components for driving and monitoring a Clock & reset interface. This class gets the `cfg` , `cntxt` using configuration database get method. It creates a driver,monitor,cov_model and sequencer. This class connects the driver with a sequencer. + +## Cvxif Agent + +Cv-xif agent supports custom instructions. Upon receiving the issue request it drives the response one clock cycle after the issue request. + +### uvma_cvxif_intf + +The interface includes inputs for clock and reset_n signal, as well as two data input/output called `cvxif_req_i` and `cvxif_resp_o`. It includes a clocking block for the monitor `monitor_cb` to sample the `cvxif_req_i` and `cvxif_resp_o` signal at the rising edge of the clock. +<table> + <tr> + <td><strong>Enum Variable</strong> + </td> + <td><strong>Description</strong> + </td> + </tr> + <tr> + <td> Cvxif_req_i + </td> + <td>The request is send to get a response + </td> + </tr> + <tr> + <td>Cvxif_resp_o + </td> + <td>The response is generated according to the request. + </td> + </tr> +</table> + +### uvma_cvxif_uvm_objects + +There are two uvm_objects `uvma_cvxif_cfg_c` and `uvma_cvxif_cntxt_c`. `uvma_cvxif_cfg_c` encapsulates all the parameters for creating ,connecting and running the `uvma_cvxif_agent_c` agent . `uvma_cvxif_cntxt_c` confine all the state variables for all the CVXIF agent components. + +### uvma_cvxif_Sequence_items + +Cvxif agent has two sequence items one `uvma_cvxif_req_item_c`and `uvma_cvxif_resp_item_c` for the request and response transaction. + +### uvma_cvxif_sqr_c + +`uvma_cvxif_sqr_c` class extends from `uvm_sequencer` base class. It is a typical sequencer. This class instantiates a FIFO to receive the `uvma_cvxif_req_item_c`. + +### uvma_cvxif_sequences + +* `uvma_cvxif_base_seq_c` class extends from `uvm_sequence` . This class simply implements a decode function that checks whether the instructions are legal or illegal. + +* `uvma_cvxif_seq_c` class extends from `uvma_cvxif_base_seq_c` class. This class gets the `uvma_cvxif_req_item_c` from the FIFO in sequencer using the p_sequencer handle. In this sequence class, we send the response according to the request item received . If we receive an instruction from the req_item that is illegal then we drive zero's on the response signals. Otherwise we drive response accordingly. + +### uvma_cvxif_drv_c + +This class `uvma_cvxif_drv_c` extends from the `uvm_driver` class. This class has several tasks that perform different actions such as generating a random ready signal, getting response_item, driving an issue response to the `VIF` , driving results in order and out of order fashion, and de-asserting signals. + +### uvma_cvxif_mon_c + +`uvma_cvxif_mon_c` class extends from the `uvm_monitor` . It monitors the virtual interface `vif`. It monitors transaction requests and responses, and sends transaction requests to `uvma_cvxif_sqr_c` and responses to the coverage model. It has several fields, including objects for configuration and context, and analysis ports for transaction requests and responses. + +### uvma_cvxif_cov_model_c + +`uvma_cvxif_cov_model_c` is derived from the `uvm_component` class. This class defines various objects and covergroups with different coverpoints, and it also uses the UVM library to sample these coverpoints and measure coverage.The main purpose of this class is to measure the functional coverage of a specific interface in the design and ensure that it has been fully tested. + +### uvma_cvxif_agent_c + +`uvma_cvxif_agent_c` class extends from `uvm_agent` class. This class represents an agent that is responsible for the test execution and communication between the virtual interface (VIF) and the testbench components. The main role of this class is to create and connect the different components of the testbench and manage the communication between them and the virtual interface (VIF) during the test execution. \ No newline at end of file diff --git a/verif/docs/VerifPlans/AXI/VP_IP005.yml b/verif/docs/VerifPlans/AXI/VP_IP005.yml new file mode 100644 index 0000000000..05353b0253 --- /dev/null +++ b/verif/docs/VerifPlans/AXI/VP_IP005.yml @@ -0,0 +1,104 @@ +!Feature +next_elt_id: 2 +name: Burst +id: 5 +display_order: 5 +subfeatures: !!omap +- 000_Control_Signals: !Subfeature + name: 000_Control_Signals + tag: VP_IP005_P000 + next_elt_id: 12 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_1_F005_S000_I000 + description: All transaction performed by CVA6 are of type INCR. AxBURST = + 0b01 + reqt_doc: AXI Design doc - Address structure + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Ensure that AxBURST == 0b01 is always true while AX_VALID is + asserted. + pfc: 4 + test_type: 3 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_1_F005_S000_I001 + description: All Read transaction performed by CVA6 are of burst lenght less + or equal to 2. ARLEN = 0b01 + reqt_doc: AXI Design doc - Address structure + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Ensure that ARLEN == 0b01 is always true while AR_VALID is asserted. + pfc: 4 + test_type: 3 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_1_F005_S000_I002 + description: All write transaction performed by CVA6 are of burst lenght equal + to 1. AWLEN = 0b00 + reqt_doc: AXI Design doc - Address structure + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Ensure that AWLEN == 0b00 is always true while AW_VALID is asserted. + pfc: 4 + test_type: 3 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_1_F005_S000_I003 + description: The size of a read transfer does not exceed the width of the + data interface. The maximum value can be taking by AxSIZE is 3. + reqt_doc: https://developer.arm.com/documentation/ihi0022/hc - (Section A3.4.1) + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Ensure that AxSIZE <= log2(AXI_DATA_WIDTH/8) is always true while + AR_VALID is asserted. + pfc: 4 + test_type: 3 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' + - '007': !VerifItem + name: '007' + tag: VP_1_F005_S000_I007 + description: Exclusive access transactions cannot have a length greater than + 16 beats + reqt_doc: https://developer.arm.com/documentation/ihi0022/hc - (Section A7.2.4) + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Ensure that AxLOCK && AxLEN <= 15 is always true while AX_VALID + is asserted. + pfc: 4 + test_type: 3 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: 03047594b4818fcbd06a40669e637081ff1d4fb9 $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/verif/docs/VerifPlans/AXI/VP_IP006.yml b/verif/docs/VerifPlans/AXI/VP_IP006.yml new file mode 100644 index 0000000000..768ff95603 --- /dev/null +++ b/verif/docs/VerifPlans/AXI/VP_IP006.yml @@ -0,0 +1,179 @@ +!Feature +next_elt_id: 9 +name: Signals +id: 6 +display_order: 6 +subfeatures: !!omap +- 000_ID: !Subfeature + name: 000_ID + tag: VP_IP006_P000 + next_elt_id: 3 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_1_F006_S000_I000 + description: The CVA6 identify read transaction with an ID equal to 0 or 1 + reqt_doc: AXI Design doc - Transaction Identifiers + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Ensure that ARID == 0b01 || ARID == 0b00 is always true while + AR_VALID is asserted. + pfc: 4 + test_type: 3 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_1_F006_S000_I001 + description: The CVA6 identify write transaction with an ID equal to 1 + reqt_doc: AXI Design doc - Transaction Identifiers + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Ensure that AWID == 0b01 is always true while AW_VALID is asserted. + pfc: 4 + test_type: 3 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' +- 001_User: !Subfeature + name: 001_User + tag: VP_IP006_P001 + next_elt_id: 2 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_1_F006_S001_I000 + description: User-defined extension for the write and read address channel + is not supported. AxUSER = 0b00 + reqt_doc: AXI Design doc - (table 2.2 and 2.5) + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Ensure that AxUSER = 0b00 is always true while AX_VALID is asserted. + pfc: 4 + test_type: 3 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_1_F006_S001_I001 + description: User-defined extension for the write response channel is not + supported. + reqt_doc: AXI Design doc - (table 2.4) + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Ensure that BUSER = 0b00 is always true while B_VALID is asserted. + pfc: 4 + test_type: 3 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' +- 002_Quality_of_Service: !Subfeature + name: 002_Quality_of_Service + tag: VP_IP006_P002 + next_elt_id: 2 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_1_F006_S002_I000 + description: Quality of Service identifier is not supported. AxQOS = 0b0000 + reqt_doc: AXI Design doc - (table 2.2 and 2.5) + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Ensure that AxQOS = 0b0000 is always true while AX_VALID is asserted. + pfc: 4 + test_type: 3 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' +- 003_Cache: !Subfeature + name: 003_Cache + tag: VP_IP006_P003 + next_elt_id: 2 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_1_F006_S003_I000 + description: AxCACHE always take 0b0000. + reqt_doc: 'AXI Design Doc - Transaction Attributes: Memory types' + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Ensure that AxCACHE = 0b0000 is always true while AX_VALID is + asserted. + pfc: 4 + test_type: 3 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' +- 004_Protection: !Subfeature + name: 004_Protection + tag: VP_IP006_P004 + next_elt_id: 1 + display_order: 4 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_1_F006_S004_I000 + description: Protection attributes always take the 0b000 + reqt_doc: AXI Design Doc - (Table 2.2 and 2.5) + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Ensure that AxPROT = 0b000 is always true while AX_VALID is asserted. + pfc: 4 + test_type: 3 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' +- 008_Region: !Subfeature + name: 008_Region + tag: VP_IP006_P008 + next_elt_id: 1 + display_order: 8 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_1_F006_S008_I000 + description: Region indicator is not supported. AxREGION = 0b0000 + reqt_doc: AXI Design doc - (table 2.2 and 2.5) + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Ensure that AxREGION = 0b0000 is always true while AX_VALID is + asserted. + pfc: 4 + test_type: 3 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: 03047594b4818fcbd06a40669e637081ff1d4fb9 $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/verif/docs/VerifPlans/AXI/VP_IP007.yml b/verif/docs/VerifPlans/AXI/VP_IP007.yml new file mode 100644 index 0000000000..202bd170bb --- /dev/null +++ b/verif/docs/VerifPlans/AXI/VP_IP007.yml @@ -0,0 +1,64 @@ +!Feature +next_elt_id: 1 +name: Clock and Reset +id: 7 +display_order: 7 +subfeatures: !!omap +- 000_Signals_Value: !Subfeature + name: 000_Signals_Value + tag: VP_IP007_P000 + next_elt_id: 3 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_1_F007_S000_I000 + description: A value of X on [Ax | x]VALID is not permitted when not in reset + reqt_doc: https://developer.arm.com/documentation/ihi0022/hc - (Section A3.1.2) + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Ensure that reset && [Ax | x]VALID != X is always true + pfc: 4 + test_type: 4 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_1_F007_S000_I001 + description: A value of X on [Ax | x]READY is not permitted when not in reset + reqt_doc: https://developer.arm.com/documentation/ihi0022/hc - (Section A3.1.2) + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Ensure that reset && [Ax | x]READY != X is always true + pfc: 4 + test_type: 4 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_1_F007_S000_I002 + description: '[Ax | x]VALID is LOW for the first cycle after RESET goes HIGH' + reqt_doc: https://developer.arm.com/documentation/ihi0022/hc - (Figure A3-1) + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Ensure that [Ax | x]VALID is low the first cycle after RESET + pfc: 4 + test_type: 4 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: 03047594b4818fcbd06a40669e637081ff1d4fb9 $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/verif/docs/VerifPlans/AXI/VP_IP008.yml b/verif/docs/VerifPlans/AXI/VP_IP008.yml new file mode 100644 index 0000000000..642c70531f --- /dev/null +++ b/verif/docs/VerifPlans/AXI/VP_IP008.yml @@ -0,0 +1,141 @@ +!Feature +next_elt_id: 3 +name: Handshake_Process +id: 8 +display_order: 8 +subfeatures: !!omap +- '000_Stability ': !Subfeature + name: '000_Stability ' + tag: VP_IP008_P000 + next_elt_id: 2 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_1_F008_S000_I000 + description: All signals must remain stable when [Ax | x]VALID is asserted + and [Ax | x]READY is LOW + reqt_doc: https://developer.arm.com/documentation/ihi0022/hc - (Section A3.2.2) + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Ensure that all the signals does not change while [Ax | x]VALID + is asserted and [Ax | x]READY not yet asserted. + pfc: 4 + test_type: 4 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_1_F008_S000_I001 + description: '[Ax | x]VALID must remain asserted until [Ax | x]READY is HIGH' + reqt_doc: https://developer.arm.com/documentation/ihi0022/hc - (Section A3.2.1) + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Ensure that [Ax | x]VALID does not change while [Ax | x]READY + is low. + pfc: 4 + test_type: 4 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' +- 001_Timing: !Subfeature + name: 001_Timing + tag: VP_IP008_P001 + next_elt_id: 8 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_1_F008_S001_I000 + description: The Manager must not wait for the Subordinate to assert ARREADY + before asserting ARVALID + reqt_doc: https://developer.arm.com/documentation/ihi0022/hc - (Section A3.3.1) + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Ensure that no errors are encountered as the testbench injects\ + \ random Ready-to-Valid delays. There are two cases to consider:\n\nARREADY\ + \ is asserted on or after same cycle as ARVALID\nARREADY is asserted and\ + \ deasserted during an interval when ARVALID is de-asserted" + pfc: 0 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_1_F008_S001_I002 + description: The Manager must not wait for the Subordinate to assert AWREADY + before asserting AWVALID or WVALID. + reqt_doc: https://developer.arm.com/documentation/ihi0022/hc - (Section A3.3.1) + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Ensure that no errors are encountered as the testbench injects\ + \ random Ready-to-Valid delays. There are four cases to consider: \n \ + \ \nAWREADY is asserted on or after\ + \ same cycle as AWVALID and WVALID is de-asserted\nAWREADY is asserted on\ + \ or after same cycle as WVALID and AWVALID is de-asserted\nAWREADY is\ + \ asserted on or after same cycle as AWVALID and WVALID\nAWREADY is asserted\ + \ and deasserted during an interval when AWVALID and WVALID is de-asserted" + pfc: 0 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_1_F008_S001_I003 + description: The Manager must not wait for the Subordinate to assert WREADY + before asserting AWVALID or WVALID. + reqt_doc: https://developer.arm.com/documentation/ihi0022/hc - (Section A3.3.1) + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Ensure that no errors are encountered as the testbench injects\ + \ random Ready-to-Valid delays. There are four cases to consider: \n \ + \ \nWREADY is asserted on or\ + \ after same cycle as AWVALID and WVALID is de-asserted\nWREADY is asserted\ + \ on or after same cycle as WVALID and AWVALID is de-asserted\nWREADY is\ + \ asserted on or after same cycle as AWVALID and WVALID\nWREADY is asserted\ + \ and deasserted during an interval when AWVALID and WVALID is de-asserted" + pfc: 0 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '005': !VerifItem + name: '005' + tag: VP_1_F008_S001_I005 + description: The Subordinate must not wait for the Manager to assert [B | + R]READY before asserting [B | R]VALID + reqt_doc: https://developer.arm.com/documentation/ihi0022/hc - (Section A3.3.1) + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: No specific “observable checks” to be made in simulation. Testbench + will always provide response data independently of [B | R]READY. + pfc: 0 + test_type: 10 + cov_method: 10 + cores: 56 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: 03047594b4818fcbd06a40669e637081ff1d4fb9 $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/verif/docs/VerifPlans/AXI/runme.sh b/verif/docs/VerifPlans/AXI/runme.sh new file mode 100644 index 0000000000..e2cfd351f7 --- /dev/null +++ b/verif/docs/VerifPlans/AXI/runme.sh @@ -0,0 +1,34 @@ +############################################################################# +# Copyright (C) 2022 Thales DIS France SAS +# +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0. +# +# Original Author: Zbigniew Chamski (zbigniew.chamski@thalesgroup.com) +############################################################################# +#!/bin/sh + +# Location of project-specific directories +ROOTDIR=`readlink -f $(dirname "${BASH_SOURCE[0]}")` + +# Set up platform location. It can be anywhere but should contain +# a valid `vp_config.py` file in `vptool` directory. +# Here we use the verification tree from the example directory. +export PLATFORM_TOP_DIR="$ROOTDIR" + +# Set the printable name for the project that will be used +# in the human-readable documentation. +export PROJECT_NAME="AXI" + +# Set the alphanumerical identifier of the project that +# will be used to construct file names etc. +export PROJECT_IDENT="AXI" + +# Set the destination directory of Markdown files for this project. +# Since it will be used by VPTOOL, it shall NOT be a relative path. +export MARKDOWN_OUTPUT_DIR=`readlink -f "$ROOTDIR/../source"` + +# Run VPTOOL overriding the default theme from Yaml config with 'winxpblue'. +# FIXME: Introduce a suitably named shell variable that points to the root +# directory of the tool set (TOOL_TOP etc.) +# FORNOW use a hardcoded relative path. +sh $ROOTDIR/../../../../tools/vptool/vptool.sh $* diff --git a/verif/docs/VerifPlans/CVXIF/VP_IP000.yml b/verif/docs/VerifPlans/CVXIF/VP_IP000.yml new file mode 100644 index 0000000000..994ed44bba --- /dev/null +++ b/verif/docs/VerifPlans/CVXIF/VP_IP000.yml @@ -0,0 +1,285 @@ +!Feature +next_elt_id: 9 +name: Issue Interface +id: 0 +display_order: 0 +subfeatures: !!omap +- 000_issue_req signals stable: !Subfeature + name: 000_issue_req signals stable + tag: VP_CVXIF_F000_S000 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_CVXIF_F000_S000_I000 + description: The “instr” and “mode” signals remain stable during an Issue + request transaction. + reqt_doc: https://github.com/openhwgroup/core-v-xif/blob/43dc03563e0c79cc55922f653406a9f122f61e80/docs/source/x_ext.rst + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Check that “mode” and “instr” are stable during an issue transaction + (cannot be modified by an instruction when transaction issue is in process) + pfc: 4 + test_type: 3 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' +- 001_mode signal value: !Subfeature + name: 001_mode signal value + tag: VP_CVXIF_F000_S001 + next_elt_id: 2 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_CVXIF_F000_S001_I000 + description: When issue transaction starts, instruction and current CPU mode + are provided + reqt_doc: https://github.com/openhwgroup/core-v-xif/blob/43dc03563e0c79cc55922f653406a9f122f61e80/docs/source/x_ext.rst + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Check that a mode modification coming from execution of a first + instruction is well provided to the following offloaded instruction + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_CVXIF_F000_S001_I001 + description: Check “mode” signal values. + reqt_doc: https://github.com/openhwgroup/core-v-xif/blob/43dc03563e0c79cc55922f653406a9f122f61e80/docs/source/x_ext.rst + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Check that mode take a value that the CPU supports : Privilege\ + \ level (2’b00 = User, 2’b01 = Supervisor, 2’b10 = Reserved,\n 2’b11 = Machine)." + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 56 + coverage_loc: '' + comments: '' +- 002_rs_valid signal transition order: !Subfeature + name: 002_rs_valid signal transition order + tag: VP_CVXIF_F000_S002 + next_elt_id: 1 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_CVXIF_F000_S002_I000 + description: During a transaction, each bit of “rs_valid” can transition from + 0 to 1 but are not allowed to transition back to 0. + reqt_doc: https://github.com/openhwgroup/core-v-xif/blob/43dc03563e0c79cc55922f653406a9f122f61e80/docs/source/x_ext.rst + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: For issue transaction which lasts more than one cycle, check + that asserted “rs_valid” signals do not transition back to 0.(for i in [0;2] + if rs_valid[i] = 1 then rs_valid[i] → 0 cannot happen) + pfc: 4 + test_type: 3 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' +- 003_rs signal value: !Subfeature + name: 003_rs signal value + tag: VP_CVXIF_F000_S003 + next_elt_id: 3 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_CVXIF_F000_S003_I000 + description: If XLEN = X_RFR_WIDTH, then rs[X_NUM_RS-1:0] correspond to rs1 + and rs2 CPU registers (and rs3 if X_NUM_RS = 3). + reqt_doc: https://github.com/openhwgroup/core-v-xif/blob/43dc03563e0c79cc55922f653406a9f122f61e80/docs/source/x_ext.rst + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: For every issue transaction check that rs signal correspond to + rs1,rs2(rs3) value in CPU register file. + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_CVXIF_F000_S003_I001 + description: rs signals are only required to be stable during the part of + a transaction in which these signals are considered to be valid. + reqt_doc: https://github.com/openhwgroup/core-v-xif/blob/43dc03563e0c79cc55922f653406a9f122f61e80/docs/source/x_ext.rst + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Check that rs signals are stable when issue_valid==1 && the corresponding + bit in rs_valid is 1. + pfc: 4 + test_type: -1 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_CVXIF_F000_S003_I002 + description: If XLEN != X_RFR_WIDTH , then rs[X_NUM_RS-1:0] correspond to + even/odd register pair with rs1, rs2, (rs3) are even register and even register + is provided in the 32 lower bits of rs signal. + reqt_doc: https://github.com/openhwgroup/core-v-xif/blob/43dc03563e0c79cc55922f653406a9f122f61e80/docs/source/x_ext.rst + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "For every issue transaction check that rs signal correspond\ + \ to the concatenation of rs1/rs1+1,rs2/rs2+1, (rs3/rs3+1) value in CPU\ + \ register file and even register is in the 32 lower bits of rs.\n\nCan't\ + \ be check XLEN == X_RFR_WIDTH" + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 56 + coverage_loc: '' + comments: '' +- 004_Default value for unaccepted instruction: !Subfeature + name: 004_Default value for unaccepted instruction + tag: VP_CVXIF_F000_S004 + next_elt_id: 1 + display_order: 4 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_CVXIF_F000_S004_I000 + description: "If accept == 0 :\nWriteback == 0; dualwrite == 0; dualread ==\ + \ 0; loadstore == 0; exc = 0." + reqt_doc: https://github.com/openhwgroup/core-v-xif/blob/43dc03563e0c79cc55922f653406a9f122f61e80/docs/source/x_ext.rst + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Check that for writeback; dualwrite; dualread; loadstore; exc + signals if accept == 0 then all those signals are 0. + pfc: 4 + test_type: 3 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' +- 005_Illegal Instruction causes: !Subfeature + name: 005_Illegal Instruction causes + tag: VP_CVXIF_F000_S005 + next_elt_id: 1 + display_order: 5 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_CVXIF_F000_S005_I000 + description: "The CPU shall cause an illegal instruction if:\n- an instruction\ + \ is considered to be valid by the CPU and accepted by the coprocessor (accept\ + \ = 1)\n- neither to be valid by the CPU nor accepted by the coprocessor\ + \ (accept = 0)" + reqt_doc: https://github.com/openhwgroup/core-v-xif/blob/43dc03563e0c79cc55922f653406a9f122f61e80/docs/source/x_ext.rst + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "- CPU causes illegal instruction for instruction accepted by\ + \ the core and the coprocessor.\n- CPU causes illegal instruction exception\ + \ for instruction that are not valid for coprocessor and CPU" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 006_issue uniquness: !Subfeature + name: 006_issue uniquness + tag: VP_CVXIF_F000_S006 + next_elt_id: 1 + display_order: 6 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_CVXIF_F000_S006_I000 + description: Check for issue id validity. + reqt_doc: https://github.com/openhwgroup/core-v-xif/blob/43dc03563e0c79cc55922f653406a9f122f61e80/docs/source/x_ext.rst + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Check that the issue interface doesn't issue an "id" that isn't + legal to be used (has not fully completed). + pfc: 11 + test_type: 3 + cov_method: 10 + cores: 56 + coverage_loc: '' + comments: '' +- 007_coprocessor decoding: !Subfeature + name: 007_coprocessor decoding + tag: VP_CVXIF_F000_S007 + next_elt_id: 1 + display_order: 7 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_CVXIF_F000_S007_I000 + description: "Accept = 1 if: \n- coprocessor can handle the instruction based\ + \ on decoding “instr” and \"mode\".\n- “issue_valid” == 1 and required bit(s)\ + \ of “rs_valid” are 1." + reqt_doc: https://github.com/openhwgroup/core-v-xif/blob/43dc03563e0c79cc55922f653406a9f122f61e80/docs/source/x_ext.rst + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: To be checked in coprocessor. + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 008_Transaction definition: !Subfeature + name: 008_Transaction definition + tag: VP_CVXIF_F000_S008 + next_elt_id: 1 + display_order: 8 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_CVXIF_F000_S008_I000 + description: "“issue_resp” signals and “issue_req” signals are accepted when\ + \ “issue_valid” == “issue_ready” == 1\n“issue_resp” is valid when \"valid==ready==1\"\ + .\n“issue_req” is valid when \"valid==1\"" + reqt_doc: https://github.com/openhwgroup/core-v-xif/blob/43dc03563e0c79cc55922f653406a9f122f61e80/docs/source/x_ext.rst + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "The definition of a transaction. \nNot to be verified." + pfc: 11 + test_type: 10 + cov_method: 10 + cores: 56 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/verif/docs/VerifPlans/CVXIF/VP_IP001.yml b/verif/docs/VerifPlans/CVXIF/VP_IP001.yml new file mode 100644 index 0000000000..7f4013abc3 --- /dev/null +++ b/verif/docs/VerifPlans/CVXIF/VP_IP001.yml @@ -0,0 +1,110 @@ +!Feature +next_elt_id: 4 +name: Commit Interface +id: 1 +display_order: 1 +subfeatures: !!omap +- 000_commit_valid pulse: !Subfeature + name: 000_commit_valid pulse + tag: VP_CVXIF_F001_S000 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_CVXIF_F001_S000_I000 + description: The “commit_valid” == 1 exactly one clk cycle for every offloaded Instruction + by the coprocessor (whether accepted or not). + reqt_doc: https://github.com/openhwgroup/core-v-xif/blob/43dc03563e0c79cc55922f653406a9f122f61e80/docs/source/x_ext.rst + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: For every offloaded instruction, check that commit_valid is + asserted exactly one clk cycle ( is a pulse ). + pfc: 4 + test_type: 3 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' +- 001_commit transaction uniquness: !Subfeature + name: 001_commit transaction uniquness + tag: VP_CVXIF_F001_S001 + next_elt_id: 1 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_CVXIF_F001_S001_I000 + description: There is a unique commit transaction for every issue transaction + (unique until an instruction has "fully completed" = its result has been + submitted). + reqt_doc: https://github.com/openhwgroup/core-v-xif/blob/43dc03563e0c79cc55922f653406a9f122f61e80/docs/source/x_ext.rst + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Check that the commit interface doesn't commit an "id" that isn't + legal to be used (hasn't been seen in earlier stages, or has not fully completed). + pfc: 1 + test_type: 10 + cov_method: 10 + cores: 56 + coverage_loc: '' + comments: '' +- 002_commit transaction for every issue transaction: !Subfeature + name: 002_commit transaction for every issue transaction + tag: VP_CVXIF_F001_S002 + next_elt_id: 1 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_CVXIF_F001_S002_I000 + description: "- The CPU shall perform a commit transaction for every issue\ + \ transaction, independent of the accept value of the issue transaction.\n\ + - For each offloaded and accepted instruction the core is guaranteed to\ + \ (eventually) signal that such an instruction is either no longer speculative\ + \ and can be committed (commit_valid is 1 and commit_kill is 0) or that\ + \ the instruction must be killed (commit_valid is 1 and commit_kill is 1)." + reqt_doc: https://github.com/openhwgroup/core-v-xif/blob/43dc03563e0c79cc55922f653406a9f122f61e80/docs/source/x_ext.rst + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Check that for each issue transaction, the commit transaction + is sent at the same clock cycle than the issue transaction, or at any clock + cycle after the issue transaction. + pfc: 4 + test_type: 3 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' +- 003_Transaction definition: !Subfeature + name: 003_Transaction definition + tag: VP_CVXIF_F001_S003 + next_elt_id: 1 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_CVXIF_F001_S003_I000 + description: The signals in commit are valid when commit_valid is 1. + reqt_doc: https://github.com/openhwgroup/core-v-xif/blob/43dc03563e0c79cc55922f653406a9f122f61e80/docs/source/x_ext.rst + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "The definition of a transaction.\nNot to be verified." + pfc: 11 + test_type: -1 + cov_method: 10 + cores: 56 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/verif/docs/VerifPlans/CVXIF/VP_IP002.yml b/verif/docs/VerifPlans/CVXIF/VP_IP002.yml new file mode 100644 index 0000000000..56709f3749 --- /dev/null +++ b/verif/docs/VerifPlans/CVXIF/VP_IP002.yml @@ -0,0 +1,238 @@ +!Feature +next_elt_id: 8 +name: Result Interface +id: 2 +display_order: 2 +subfeatures: !!omap +- 000_no speculative result transaction: !Subfeature + name: 000_no speculative result transaction + tag: VP_CVXIF_F002_S000 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_CVXIF_F002_S000_I000 + description: A coprocessor is not allowed to perform speculative result transactions. + reqt_doc: https://github.com/openhwgroup/core-v-xif/blob/43dc03563e0c79cc55922f653406a9f122f61e80/docs/source/x_ext.rst + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: There is no result transaction for instructions that haven't + been committed. Check that Result valid is only asserted for instructions + that were committed (commit_valid == 1 && commit_kill == 0). + pfc: 11 + test_type: 10 + cov_method: 10 + cores: 56 + coverage_loc: '' + comments: '' +- 001_out of order result transaction: !Subfeature + name: 001_out of order result transaction + tag: VP_CVXIF_F002_S001 + next_elt_id: 1 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_CVXIF_F002_S001_I000 + description: A coprocessor is allowed to provide results to the core in an + out of order fashion. + reqt_doc: https://github.com/openhwgroup/core-v-xif/blob/43dc03563e0c79cc55922f653406a9f122f61e80/docs/source/x_ext.rst + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Check that the CPU is able to receive the result in an out of + order fashion. + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 002_result transaction uniquness: !Subfeature + name: 002_result transaction uniquness + tag: VP_CVXIF_F002_S002 + next_elt_id: 1 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_CVXIF_F002_S002_I000 + description: Each accepted offloaded (committed and not killed) instruction + shall have exactly one result group transaction (even if no data needs to + be written back to the CPU’s register file). + reqt_doc: https://github.com/openhwgroup/core-v-xif/blob/43dc03563e0c79cc55922f653406a9f122f61e80/docs/source/x_ext.rst + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: There is an unique result transaction for every accepted and + commit instruction. + pfc: 11 + test_type: 10 + cov_method: 10 + cores: 56 + coverage_loc: '' + comments: '' +- 003_result packet stability: !Subfeature + name: 003_result packet stability + tag: VP_CVXIF_F002_S003 + next_elt_id: 1 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_CVXIF_F002_S003_I000 + description: The signals in result shall remain stable during a result transaction + (except data ...) + reqt_doc: https://github.com/openhwgroup/core-v-xif/blob/43dc03563e0c79cc55922f653406a9f122f61e80/docs/source/x_ext.rst + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Check that result signals (except data) are stable during result + transaction (result_valid==1 jusqu'à valid==ready ==1) + pfc: 4 + test_type: 3 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' +- 004_data stability: !Subfeature + name: 004_data stability + tag: VP_CVXIF_F002_S004 + next_elt_id: 1 + display_order: 4 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_CVXIF_F002_S004_I000 + description: Data is only required to remain stable during result transactions + in which "we" is not 0. + reqt_doc: https://github.com/openhwgroup/core-v-xif/blob/43dc03563e0c79cc55922f653406a9f122f61e80/docs/source/x_ext.rst + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Check that "data" remains stable when we==1. + pfc: 4 + test_type: 3 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' +- 005_synchronous exception: !Subfeature + name: 005_synchronous exception + tag: VP_CVXIF_F002_S005 + next_elt_id: 3 + display_order: 5 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_CVXIF_F002_S005_I000 + description: The exc is used to signal synchronous exceptions. A synchronous + exception will lead to a trap in CPU unless the corresponding instruction + is killed. + reqt_doc: https://github.com/openhwgroup/core-v-xif/blob/43dc03563e0c79cc55922f653406a9f122f61e80/docs/source/x_ext.rst + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Check that synchronous exception (exc ==1) leads to a trap in + the CPU if the instruction is committed. + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_CVXIF_F002_S005_I001 + description: exccode provides the least significant bits of the exception + code bitfield of the mcause CSR. + reqt_doc: https://github.com/openhwgroup/core-v-xif/blob/43dc03563e0c79cc55922f653406a9f122f61e80/docs/source/x_ext.rst + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Check that exccode signal is the value of the mcause CSR when + exc == 1. + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_CVXIF_F002_S005_I002 + description: '"we" shall be driven to 0 by the coprocessor for synchronous + exceptions.' + reqt_doc: https://github.com/openhwgroup/core-v-xif/blob/43dc03563e0c79cc55922f653406a9f122f61e80/docs/source/x_ext.rst + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Check that "we" signal == 0 when exc == 1. + pfc: 4 + test_type: -1 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' +- 006_"we" value when dualwrite: !Subfeature + name: 006_"we" value when dualwrite + tag: VP_CVXIF_F002_S006 + next_elt_id: 1 + display_order: 6 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_CVXIF_F002_S006_I000 + description: we is 2 bits wide when XLEN = 32 and X_RFW_WIDTH = 64, and 1 + bit wide otherwise. If "we" is 2 bits wide, then we[1] is only allowed to + be 1 if we[0] is 1 as well (i.e. for dual writeback). + reqt_doc: https://github.com/openhwgroup/core-v-xif/blob/43dc03563e0c79cc55922f653406a9f122f61e80/docs/source/x_ext.rst + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "For dualwrite instruction, check that we[1]==1 is only allowed\ + \ if we[0] == 1.\n\nDualwrite not supported (for now)" + pfc: 4 + test_type: 3 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' +- 007_proper result transaction: !Subfeature + name: 007_proper result transaction + tag: VP_CVXIF_F002_S007 + next_elt_id: 1 + display_order: 7 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_CVXIF_F002_S007_I000 + description: Result transaction starts in the cycle that result_valid = 1 + and ends in the cycle that both result_valid == result_ready == 1. + reqt_doc: https://github.com/openhwgroup/core-v-xif/blob/43dc03563e0c79cc55922f653406a9f122f61e80/docs/source/x_ext.rst + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Check that result transaction ends properly. + pfc: 4 + test_type: 3 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/verif/docs/VerifPlans/CVXIF/VP_IP003.yml b/verif/docs/VerifPlans/CVXIF/VP_IP003.yml new file mode 100644 index 0000000000..216492f497 --- /dev/null +++ b/verif/docs/VerifPlans/CVXIF/VP_IP003.yml @@ -0,0 +1,402 @@ +!Feature +next_elt_id: 8 +name: Custom Instructions +id: 3 +display_order: 3 +subfeatures: !!omap +- 000_CUS_ADD: !Subfeature + name: 000_CUS_ADD + tag: VP_CVXIF_F003_S000 + next_elt_id: 4 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_CVXIF_F003_S000_I000 + description: "cus_add rd, rs1, rs2\nrd = rs1 + rs2\ncus_add works in all privilege\ + \ modes" + reqt_doc: ./custom_instruction.rst + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_CVXIF_F003_S000_I001 + description: "cus_add rd, rs1, rs2\nrd = rs1 + rs2\ncus_add works in all privilege\ + \ modes" + reqt_doc: ./custom_instruction.rst + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nrs2 value\ + \ is +ve, -ve and zero\nAll combinations of rs1 and rs2 +ve, -ve, and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled" + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_CVXIF_F003_S000_I002 + description: "cus_add rd, rs1, rs2\nrd = rs1 + rs2\ncus_add works in all privilege\ + \ modes" + reqt_doc: ./custom_instruction.rst + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 56 + coverage_loc: '' + comments: '' +- 001_CUS_NOP: !Subfeature + name: 001_CUS_NOP + tag: VP_CVXIF_F003_S001 + next_elt_id: 1 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_CVXIF_F003_S001_I000 + description: No operation Instruction + reqt_doc: ./custom_instruction.rst + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Instruction executed + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 003_CUS_S_ADD: !Subfeature + name: 003_CUS_S_ADD + tag: VP_CVXIF_F003_S003 + next_elt_id: 3 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_CVXIF_F003_S003_I000 + description: "cus_s_add rd, rs1, rs2\nrd = rs1 + rs2\ncus_s_add works in supervisor\ + \ privilege mode" + reqt_doc: ./custom_instruction.rst + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nif (mode == s)\nAll possible rs1 registers\ + \ are used.\nAll possible rs2 registers are used.\nAll possible rd registers\ + \ are used.\nAll possible register combinations where rs1 == rd are used\n\ + All possible register combinations where rs2 == rd are used\n\nelse if (mode\ + \ != s)\nillegal exception raised on hte CPU" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_CVXIF_F003_S003_I001 + description: "cus_s_add rd, rs1, rs2\nrd = rs1 + rs2\ncus_s_add works in supervisor\ + \ privilege mode" + reqt_doc: ./custom_instruction.rst + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nif (mode == s)\nrs1 value is +ve, -ve and\ + \ zero\nrs2 value is +ve, -ve and zero\nAll combinations of rs1 and rs2\ + \ +ve, -ve, and zero values are used\nAll bits of rs1 are toggled\nAll bits\ + \ of rs2 are toggled\n\nelse if (mode != s)\nillegal exception raised on\ + \ the CPU" + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_CVXIF_F003_S003_I002 + description: "cus_s_add rd, rs1, rs2\nrd = rs1 + rs2\ncus_s_add works in supervisor\ + \ privilege mode" + reqt_doc: ./custom_instruction.rst + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output operands:\n\nif (mode == s)\nrd value is +ve, -ve and\ + \ zero\nAll bits of rd are toggled\n\nelse if (mode != s)\nillegal exception\ + \ raised on the CPU" + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 56 + coverage_loc: '' + comments: '' +- 004_CUS_U_ADD: !Subfeature + name: 004_CUS_U_ADD + tag: VP_CVXIF_F003_S004 + next_elt_id: 3 + display_order: 4 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_CVXIF_F003_S004_I000 + description: "cus_u_add rd, rs1, rs2\nrd = rs1 + rs2\ncus_u_add works in User\ + \ privilege mode" + reqt_doc: ./custom_instruction.rst + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nif (mode == u)\nAll possible rs1 registers\ + \ are used.\nAll possible rs2 registers are used.\nAll possible rd registers\ + \ are used.\nAll possible register combinations where rs1 == rd are used\n\ + All possible register combinations where rs2 == rd are used\n\nelse if (mode\ + \ != u)\nillegal exception raised on hte CPU" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_CVXIF_F003_S004_I001 + description: "cus_u_add rd, rs1, rs2\nrd = rs1 + rs2\ncus_u_add works in User\ + \ privilege mode" + reqt_doc: ./custom_instruction.rst + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nif (mode == u)\nrs1 value is +ve, -ve and\ + \ zero\nrs2 value is +ve, -ve and zero\nAll combinations of rs1 and rs2\ + \ +ve, -ve, and zero values are used\nAll bits of rs1 are toggled\nAll bits\ + \ of rs2 are toggled\n\nelse if (mode != u)\nillegal exception raised on\ + \ the CPU" + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_CVXIF_F003_S004_I002 + description: "cus_u_add rd, rs1, rs2\nrd = rs1 + rs2\ncus_u_add works in User\ + \ privilege mode" + reqt_doc: ./custom_instruction.rst + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output operands:\n\nif (mode == u)\nrd value is +ve, -ve and\ + \ zero\nAll bits of rd are toggled\n\nelse if (mode != u)\nillegal exception\ + \ raised on the CPU" + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 56 + coverage_loc: '' + comments: '' +- 005_CUS_ADD_MULTI: !Subfeature + name: 005_CUS_ADD_MULTI + tag: VP_CVXIF_F003_S005 + next_elt_id: 4 + display_order: 5 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_CVXIF_F003_S005_I000 + description: "cus_add_multi rd, rs1, rs2\nrd = rs1 + rs2\ncus_add_multi works\ + \ in all privilege modes" + reqt_doc: ./custom_instruction.rst + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_CVXIF_F003_S005_I001 + description: "cus_add_multi rd, rs1, rs2\nrd = rs1 + rs2\ncus_add_multi works\ + \ in all privilege modes" + reqt_doc: ./custom_instruction.rst + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nrs2 value\ + \ is +ve, -ve and zero\nAll combinations of rs1 and rs2 +ve, -ve, and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled" + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_CVXIF_F003_S005_I002 + description: "cus_add_multi rd, rs1, rs2\nrd = rs1 + rs2\ncus_add_multi works\ + \ in all privilege modes" + reqt_doc: ./custom_instruction.rst + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 56 + coverage_loc: '' + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_CVXIF_F003_S005_I003 + description: "cus_add_multi rd, rs1, rs2\nrd = rs1 + rs2\ncus_add_multi works\ + \ in all privilege modes" + reqt_doc: ./custom_instruction.rst + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Check all delays from min to max + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 006_CUS_EXC: !Subfeature + name: 006_CUS_EXC + tag: VP_CVXIF_F003_S006 + next_elt_id: 1 + display_order: 6 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_CVXIF_F003_S006_I000 + description: "cus_exc imm[5:0]\nmcause[5:0] = imm[5:0]\ncus_exc raise an exception\ + \ on the CPU base on the imm value" + reqt_doc: ./custom_instruction.rst + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Check all possible imm value + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 56 + coverage_loc: '' + comments: '' +- 007_CUS_ADD_RS3: !Subfeature + name: 007_CUS_ADD_RS3 + tag: VP_CVXIF_F003_S007 + next_elt_id: 3 + display_order: 7 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_CVXIF_F003_S007_I000 + description: "cus_add_rs3 rd, rs1, rs2, rs3\nrd = rs1 + rs2 + rs3\ncus_add_rs3\ + \ works in all privilege modes\n\nX_NUM_RS == 3" + reqt_doc: ./custom_instruction.rst + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nif (X_NUM_RS == 3)\nAll possible rs1 registers\ + \ are used.\nAll possible rs2 registers are used.\nAll possible rs3 registers\ + \ are used.\nAll possible rd registers are used.\nAll possible register\ + \ combinations where rs1 == rd are used\nAll possible register combinations\ + \ where rs2 == rd are used\nAll possible register combinations where rs3\ + \ == rd are used\n\n\nelse if (X_NUM_RS != 3)\nillegal exception raised\ + \ on the CPU" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_CVXIF_F003_S007_I001 + description: "cus_add_rs3 rd, rs1, rs2, rs3\nrd = rs1 + rs2 + rs3\ncus_add_rs3\ + \ works in all privilege modes\n\nX_NUM_RS == 3" + reqt_doc: ./custom_instruction.rst + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nif (X_NUS_RS == 3)\nrs1 value is +ve, -ve\ + \ and zero\nrs2 value is +ve, -ve and zero\nrs3 value is +ve, -ve and zero\n\ + All combinations of rs1, rs2 and rs3 +ve, -ve, and zero values are used\n\ + All bits of rs1 are toggled\nAll bits of rs2 are toggled\nAll bits of rs3\ + \ are toggled\n\nelse if (X_NUM_RS != 3)\nillegal exception raised on the\ + \ CPU" + pfc: -1 + test_type: -1 + cov_method: -1 + cores: -1 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_CVXIF_F003_S007_I002 + description: "cus_add_rs3 rd, rs1, rs2, rs3\nrd = rs1 + rs2 + rs3\ncus_add_rs3\ + \ works in all privilege modes\n\nX_NUM_RS == 3" + reqt_doc: ./custom_instruction.rst + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output operands:\n\nif (X_NUM_RS == 3)\nrd value is +ve, -ve\ + \ and zero\nAll bits of rd are toggled\n\nelse if (X_NUM_RS != 3)\nillegal\ + \ exception raised on the CPU" + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 56 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/verif/docs/VerifPlans/CVXIF/custom_instruction.rst b/verif/docs/VerifPlans/CVXIF/custom_instruction.rst new file mode 100644 index 0000000000..49f739d9d0 --- /dev/null +++ b/verif/docs/VerifPlans/CVXIF/custom_instruction.rst @@ -0,0 +1,100 @@ +.. + Copyright (c) 2023 OpenHW Group + + Copyright (c) 2023 Thales DIS SAS + + + SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + +.. + +Custom Instruction to challenge CV-X-IF protocol +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +This section describes some custom instruction, for stress or challenge the CV-X-IF protocol for the 3 implemented interfaces, it's just to interact with the cvxif agent. +All instructions use opcode `CUSTOM_3`(0x7b, 0b111_1011). + +- **CUS_ADD**: Custom Add + + **Format**: cus_add rd, rs1, rs2 -> |0000000|rs2|rs1|001|rd|111_1011| + + **Description**: add register rs1 to rs2, and store the result in rd (works for all privilege modes). + + **Pseudocode**: x[rd] = x[rs1] + x[rs2] + + **Invalid values**: NONE + + **Exception raised**: Illegal instruction exception is raised if rs_valid != 2'b11 && rs_valid != 3'b111. + +- **CUS_NOP**: Custom No Operation + + **Format**: cus_nop -> |0000000000000000000000000|111_1011| + + **Description**: do nothing, it's just a hint instruction. + + **Pseudocode**: cus_nop + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **CUS_ADD_RS3**: Custom Add + + **Format**: cus_add_rs3 rd, rs1, rs2, rs3 -> |rs3|01|rs2|rs1|000|rd|111_1011| + + **Description**: add register rs1 to rs2 then the result to rs3, and store the result in register rd (works for all privilege modes). + + **Pseudocode**: x[rd] = x[rs1] + x[rs2] + x[rs3] + + **Invalid values**: NONE + + **Exception raised**: Illegal instruction exception is raised if rs_valid != 3'b111. + +- **CUS_S_ADD**: Custom Supervisor Add + + **Format**: add rd, rs1, rs2 -> |0000110|rs2|rs1|000|rd|111_1011| + + **Description**: add register rs1 to rs2, and store the result in register rd (works only in Supervisor mode). + + **Pseudocode**: x[rd] = x[rs1] + x[rs2] + + **Invalid values**: NONE + + **Exception raised**: Illegal instruction exception is raised if the privilege mode isn't Supervisor mode, or rs_valid != 2'b11 && rs_valid != 3'b111. + +- **CUS_U_ADD**: Custom User Add + + **Format**: add rd, rs1, rs2 -> |0000010|rs2|rs1|000|rd|111_1011| + + **Description**: add register rs1 to rs2, and store the result in register rd (works only in User mode). + + **Pseudocode**: x[rd] = x[rs1] + x[rs2] + + **Invalid values**: NONE + + **Exception raised**: Illegal instruction exception is raised if the privilege mode isn't User mode, or rs_valid != 2'b11 && rs_valid != 3'b111. + +- **CUS_ADD_MULTI**: Custom Multicycle Add + + **Format**: addi rd, rs1, rs2 -> |0001000|rs2|rs1|000|rd|111_1011| + + **Description**: add register rs1 to rs2, and store the result in rd (works for all privilege mode). + + **Pseudocode**: x[rd] = x[rs1] + x[rs2] + + **Invalid values**: NONE + + **Exception raised**: Illegal instruction exception is raised if rs_valid != 2'b11 && rs_valid != 3'b111. + +- **CUS_EXC**: Custom Exception + + **Format**: cus_exc imm[5:0] -> |1100000|000000000001|imm|111_1011| + + **Description**: raise an exception. + + **Pseudocode**: mcause[5:0] = imm[5:0] + + **Invalid values**: NONE + + **Exception raised**: raise an exception based on the value on the immediate field. + +When a CV-X-IF exception is raised, mcause[5:0] of the corresponding CORE-V hart is assumed set to exccode[5:0] of CV-X-IF. diff --git a/verif/docs/VerifPlans/CVXIF/runme.sh b/verif/docs/VerifPlans/CVXIF/runme.sh new file mode 100644 index 0000000000..1701a0ebef --- /dev/null +++ b/verif/docs/VerifPlans/CVXIF/runme.sh @@ -0,0 +1,34 @@ +############################################################################# +# Copyright (C) 2022 Thales DIS France SAS +# +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0. +# +# Original Author: Zbigniew Chamski (zbigniew.chamski@thalesgroup.com) +############################################################################# +#!/bin/sh + +# Location of project-specific directories +ROOTDIR=`readlink -f $(dirname "${BASH_SOURCE[0]}")` + +# Set up platform location. It can be anywhere but should contain +# a valid `vp_config.py` file in `vptool` directory. +# Here we use the verification tree from the example directory. +export PLATFORM_TOP_DIR="$ROOTDIR" + +# Set the printable name for the project that will be used +# in the human-readable documentation. +export PROJECT_NAME="CVXIF" + +# Set the alphanumerical identifier of the project that +# will be used to construct file names etc. +export PROJECT_IDENT="CVXIF" + +# Set the destination directory of Markdown files for this project. +# Since it will be used by VPTOOL, it shall NOT be a relative path. +export MARKDOWN_OUTPUT_DIR=`readlink -f "$ROOTDIR/../source"` + +# Run VPTOOL overriding the default theme from Yaml config with 'winxpblue'. +# FIXME: Introduce a suitably named shell variable that points to the root +# directory of the tool set (TOOL_TOP etc.) +# FORNOW use a hardcoded relative path. +sh $ROOTDIR/../../../../tools/vptool/vptool.sh $* diff --git a/verif/docs/VerifPlans/FENCEI/VP_IP000.yml b/verif/docs/VerifPlans/FENCEI/VP_IP000.yml new file mode 100644 index 0000000000..aa8e965051 --- /dev/null +++ b/verif/docs/VerifPlans/FENCEI/VP_IP000.yml @@ -0,0 +1,35 @@ +!Feature +next_elt_id: 1 +name: 'Fetching ' +id: 0 +display_order: 0 +subfeatures: !!omap +- 000_Fetching: !Subfeature + name: 000_Fetching + tag: VP_FENCEI_F000_S000 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FENCEI_F000_S000_I000 + description: Instruction data for the next PC must be fetched after the fence.i + instruction has executed (because only then can data-side stores have completed + and caches have been updated). + reqt_doc: CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fence + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Check that after a fence.i instruction retires then instr-side + obi fetches the next instruction to be executed. + pfc: 4 + test_type: 4 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/verif/docs/VerifPlans/FENCEI/VP_IP001.yml b/verif/docs/VerifPlans/FENCEI/VP_IP001.yml new file mode 100644 index 0000000000..b779d36153 --- /dev/null +++ b/verif/docs/VerifPlans/FENCEI/VP_IP001.yml @@ -0,0 +1,104 @@ +!Feature +next_elt_id: 1 +name: StoresVisible +id: 1 +display_order: 1 +subfeatures: !!omap +- 000_StoresVisible: !Subfeature + name: 000_StoresVisible + tag: VP_FENCEI_F001_S000 + next_elt_id: 4 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FENCEI_F001_S000_I000 + description: After a fence.i instruction has been executed, all preceding + store instructions shall have their effects visible to the instruction fetch + of the instructions that are to be executed after the fence.i instruction. + reqt_doc: "The RISC-V Instruction Set Manual\nVolume I: Unprivileged ISA\n\ + Document Version 20191213\nhttps://riscv.org/wp-content/uploads/2019/12/riscv-spec-20191213.pdf" + ref_mode: section + ref_page: '31' + ref_section: Chapter 3 + ref_viewer: firefox + verif_goals: Do a fencei, but right before the fencei do a store to the instruction + following the fencei, then see that the newly stored value is executed instead + of the old instruction (e.g. change addi to use a different immediate). + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: TODO must be added to regression lists! + - '001': !VerifItem + name: '001' + tag: VP_FENCEI_F001_S000_I001 + description: After a fence.i instruction has been executed, all preceding + store instructions shall have their effects visible to the instruction fetch + of the instructions that are to be executed after the fence.i instruction. + reqt_doc: "The RISC-V Instruction Set Manual\nVolume I: Unprivileged ISA\n\ + Document Version 20191213\nhttps://riscv.org/wp-content/uploads/2019/12/riscv-spec-20191213.pdf" + ref_mode: section + ref_page: '31' + ref_section: Chapter 3 + ref_viewer: firefox + verif_goals: Do a fencei followed by any instruction, but let the environment + detect when the fencei is being executed and change the memory holding the + next instruction, then see that the old instruction is not executed. + pfc: -1 + test_type: 2 + cov_method: -1 + cores: 56 + coverage_loc: '' + comments: TODO missing cover! + - '002': !VerifItem + name: '002' + tag: VP_FENCEI_F001_S000_I002 + description: After a fence.i instruction has been executed, all preceding + store instructions shall have their effects visible to the instruction fetch + of the instructions that are to be executed after the fence.i instruction. + reqt_doc: "The RISC-V Instruction Set Manual\nVolume I: Unprivileged ISA\n\ + Document Version 20191213\nhttps://riscv.org/wp-content/uploads/2019/12/riscv-spec-20191213.pdf" + ref_mode: section + ref_page: '31' + ref_section: Chapter 3 + ref_viewer: firefox + verif_goals: Let the instruction right before a fence.i write a different + instruction to the address following the fence.i, then observe that the + written instruction is executed instead of the original one and that no + side-effects (csr updates or otherwise) occur (can possibly mix 16bit/32bit + instructions to force a noticable difference). + pfc: 1 + test_type: 1 + cov_method: 0 + cores: 56 + coverage_loc: '' + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_FENCEI_F001_S000_I003 + description: After a fence.i instruction has been executed, all preceding + store instructions shall have their effects visible to the instruction fetch + of the instructions that are to be executed after the fence.i instruction. + reqt_doc: "The RISC-V Instruction Set Manual\nVolume I: Unprivileged ISA\n\ + Document Version 20191213\nhttps://riscv.org/wp-content/uploads/2019/12/riscv-spec-20191213.pdf" + ref_mode: section + ref_page: '31' + ref_section: Chapter 3 + ref_viewer: firefox + verif_goals: Check that after having read one value from an address, then + after storing a value to that same address, if executing that address then + the value shall always be that which was written (should work well in both + sim/formal). + pfc: 4 + test_type: 4 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: TODO missing assert. (Note was ignored because of the difficulty + of writing this as an assert for fv.)! +vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/verif/docs/VerifPlans/FENCEI/VP_IP002.yml b/verif/docs/VerifPlans/FENCEI/VP_IP002.yml new file mode 100644 index 0000000000..5d43857753 --- /dev/null +++ b/verif/docs/VerifPlans/FENCEI/VP_IP002.yml @@ -0,0 +1,279 @@ +!Feature +next_elt_id: 10 +name: ExternalHandshake +id: 2 +display_order: 2 +subfeatures: !!omap +- 000_ReqHigh: !Subfeature + name: 000_ReqHigh + tag: VP_FENCEI_F002_S000 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FENCEI_F002_S000_I000 + description: When executing a fence.i instruction, fencei_flush_req_o shall + rise sometime before executing the next instruction. + reqt_doc: CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fence + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Check that when executing a fence.i instruction there will be + a rising req before has retired. + pfc: 4 + test_type: 4 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' +- 001_ReqWaitLsu: !Subfeature + name: 001_ReqWaitLsu + tag: VP_FENCEI_F002_S001 + next_elt_id: 1 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FENCEI_F002_S001_I000 + description: When executing a fence.i instruction, if there is an ongoing + store instruction (not limited to rv32i) that has not completed (data_rvalid_i + clocked in as 1), then fencei_flush_req_o shall be low. + reqt_doc: CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fenceThis + is a pointer to the source Requirements document of the Features in question. The + pointer should state the version of the target document. It is free-form, + so it can also indicate the specific section/page/paragraph. + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Make sure a store instruction is run right before a fence.i, + and (possibly using obi stalls) ensure that the fence.i is pending retirement + but holds off until the store's data_rvalid_i is clocked in and that fencei_flush_req_o + was low until this point where it now goes high. + pfc: 4 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: TODO missing cover! +- 002_ReqWaitWritebuffer: !Subfeature + name: 002_ReqWaitWritebuffer + tag: VP_FENCEI_F002_S002 + next_elt_id: 1 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FENCEI_F002_S002_I000 + description: When executing a fence.i instruction, if the write buffer is + not empty, then fencei_flush_req_o shall be low until the write buffer has + been emptied and the corresponding data_rvalid_i have been clocked in as + 1. + reqt_doc: CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fence + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Fill up the write buffer prior to executing a fence.i and ensure + that fencei_flush_req_o holds off going high until the write buffer to has + been emptied. + pfc: 4 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: TODO missing cover! +- 003_ReqWaitXinterface: !Subfeature + name: 003_ReqWaitXinterface + tag: VP_FENCEI_F002_S003 + next_elt_id: 1 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FENCEI_F002_S003_I000 + description: When executing a fence.i instruction, if the X interface is busy + with any store operations, then fencei_flush_req_o shall be low until all + the store operations are done + reqt_doc: CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fence + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Issue one or more store instructions that uses the X interface + and ensure that fencei_flush_req_o waits until the stores have all completed + before going high. + pfc: 4 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 004_ReqWaitObi: !Subfeature + name: 004_ReqWaitObi + tag: VP_FENCEI_F002_S004 + next_elt_id: 1 + display_order: 4 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FENCEI_F002_S004_I000 + description: fencei_flush_req_o shall not go high while there are outstanding + stores on the obi bus. + reqt_doc: CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fenceThis + is a pointer to the source Requirements document of the Features in question. The + pointer should state the version of the target document. It is free-form, + so it can also indicate the specific section/page/paragraph. + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Check vs the OBI monitors that there are no outstanding stores + at the time fencei_flush_req_o goes high. + pfc: 4 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 005_ReqLow: !Subfeature + name: 005_ReqLow + tag: VP_FENCEI_F002_S005 + next_elt_id: 1 + display_order: 5 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FENCEI_F002_S005_I000 + description: When fencei_flush_req_o is high, it shall stay high until fencei_flush_req_o + and fencei_flush_ack_i has been sampled high simultaneously, and then then + it shall go low. + reqt_doc: CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fenceThis + is a pointer to the source Requirements document of the Features in question. The + pointer should state the version of the target document. It is free-form, + so it can also indicate the specific section/page/paragraph. + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Check that when fencei_flush_req_o is high, then it behaves correctly + with regards to fencei_flush_ack_i. + pfc: 4 + test_type: 4 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' +- 006_AckChange: !Subfeature + name: 006_AckChange + tag: VP_FENCEI_F002_S006 + next_elt_id: 1 + display_order: 6 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FENCEI_F002_S006_I000 + description: 'fencei_flush_ack_i is allowed to change freely on any clock + cycle: It can be permanently high, go high without fence.i and retract, + go high at the same cycle as the req, it can delay arbitrarily after req + and then go high, etc' + reqt_doc: CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fenceThis + is a pointer to the source Requirements document of the Features in question. The + pointer should state the version of the target document. It is free-form, + so it can also indicate the specific section/page/paragraph. + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Drive ack to test all permutations of rising/falling before/after/on + req, acking without req, retracting an early ack, delaying ack after req, + etc. + pfc: 0 + test_type: 4 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 007_AckWithold: !Subfeature + name: 007_AckWithold + tag: VP_FENCEI_F002_S007 + next_elt_id: 1 + display_order: 7 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FENCEI_F002_S007_I000 + description: If req is high, but ack never comes, then the core keeps on stalling + and the fence.i is blocked from completing. + reqt_doc: CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fence + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Upon a req, try witholding ack for a long time and see that the + fence.i can be stalled arbitrarily long (should have covers for ack delays + of at least {[0:5]}). + pfc: 4 + test_type: 4 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 008_BranchInitiated: !Subfeature + name: 008_BranchInitiated + tag: VP_FENCEI_F002_S008 + next_elt_id: 1 + display_order: 8 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FENCEI_F002_S008_I000 + description: After req and ack has been sampled simultaneously high and when + req is low again, then the core takes a branch to the instruction after + the fence.i instruction. + reqt_doc: CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fenceThis + is a pointer to the source Requirements document of the Features in question. The + pointer should state the version of the target document. It is free-form, + so it can also indicate the specific section/page/paragraph. + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Check that the branch is taken at the point after req and ack + has been simultaneously high. + pfc: 4 + test_type: 4 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 009_ShadowingBranch: !Subfeature + name: 009_ShadowingBranch + tag: VP_FENCEI_F002_S009 + next_elt_id: 1 + display_order: 9 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FENCEI_F002_S009_I000 + description: If the fence.i ends up not retiring because it was preceeded + by a taken branch or a jump, then the fencei_flush_req_o shall not go high + reqt_doc: CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fence + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Take a branch or do a jump to skip a fence.i, and ensure that + fencei_flush_req_o doesn't go high. + pfc: 4 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/verif/docs/VerifPlans/FENCEI/VP_IP003.yml b/verif/docs/VerifPlans/FENCEI/VP_IP003.yml new file mode 100644 index 0000000000..86c8993b5c --- /dev/null +++ b/verif/docs/VerifPlans/FENCEI/VP_IP003.yml @@ -0,0 +1,35 @@ +!Feature +next_elt_id: 1 +name: MultiCycle +id: 3 +display_order: 3 +subfeatures: !!omap +- 000_MultiCycle: !Subfeature + name: 000_MultiCycle + tag: VP_FENCEI_F003_S000 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FENCEI_F003_S000_I000 + description: Given zero stalls on neither instr-side and data-side obi nor + on fencei_flush_ack_i, then the execution of fence.i takes a fixed number + of cycles. + reqt_doc: CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fence + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Check that, given ideal conditions, the cycle count of fence.i + is as expected. + pfc: 4 + test_type: 4 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/verif/docs/VerifPlans/FENCEI/VP_IP004.yml b/verif/docs/VerifPlans/FENCEI/VP_IP004.yml new file mode 100644 index 0000000000..00b4775d3c --- /dev/null +++ b/verif/docs/VerifPlans/FENCEI/VP_IP004.yml @@ -0,0 +1,69 @@ +!Feature +next_elt_id: 2 +name: StoresComplete +id: 4 +display_order: 4 +subfeatures: !!omap +- 000_StoresComplete: !Subfeature + name: 000_StoresComplete + tag: VP_FENCEI_F004_S000 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FENCEI_F004_S000_I000 + description: Any store instruction that is successfully executed before a + fence.i will fully complete and have its effect visible (this is not about + syncronization with instruction fetch, but rather seeing that the stores + are not aborted). + reqt_doc: CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fenceThis + is a pointer to the source Requirements document of the Features in question. The + pointer should state the version of the target document. It is free-form, + so it can also indicate the specific section/page/paragraph. + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Check that all stores (either to next pc or other places) preceding + a fence.i will complete on the bus (excluding exceptions/interrupts/etc) + and be readable afterwards (particularly, ensure that the write buffer isn't + just purged). + pfc: 1 + test_type: 1 + cov_method: 0 + cores: 56 + coverage_loc: '' + comments: '' +- 001_StoresComplete: !Subfeature + name: 001_StoresComplete + tag: VP_FENCEI_F004_S001 + next_elt_id: 1 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FENCEI_F004_S001_I000 + description: Any store instruction that is successfully executed before a + fence.i will fully complete and have its effect visible (this is not about + syncronization with instruction fetch, but rather seeing that the stores + are not aborted). + reqt_doc: CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fence + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Check that all stores (either to next pc or other places) preceding + a fence.i will complete on the bus (excluding exceptions/interrupts/etc) + and be readable afterwards (particularly, ensure that the write buffer isn't + just purged). + pfc: 3 + test_type: 3 + cov_method: 0 + cores: 56 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/verif/docs/VerifPlans/FENCEI/VP_IP005.yml b/verif/docs/VerifPlans/FENCEI/VP_IP005.yml new file mode 100644 index 0000000000..65fe3432fe --- /dev/null +++ b/verif/docs/VerifPlans/FENCEI/VP_IP005.yml @@ -0,0 +1,37 @@ +!Feature +next_elt_id: 1 +name: Flush +id: 5 +display_order: 5 +subfeatures: !!omap +- 000_Flush: !Subfeature + name: 000_Flush + tag: VP_FENCEI_F005_S000 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FENCEI_F005_S000_I000 + description: When fence.i is executed, then any prefetched instructions shall + be flushed; meaning that pipeline stages are flushed, prefetcher is flushed, + write buffer is flushed, and data_req_o is eventually supressed. + reqt_doc: CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fence + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Check that a fence.i will cause flushing of the pipeline, prefetcher, + write buffer, and data_req_o. + pfc: 4 + test_type: 4 + cov_method: 2 + cores: 56 + coverage_loc: '' + comments: TODO missing assert. (Have not checked/covered that the pipeline/writebuffer + content is actually purged. Or that any memory change WILL be the next instr + word.)! +vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/verif/docs/VerifPlans/FENCEI/VP_IP006.yml b/verif/docs/VerifPlans/FENCEI/VP_IP006.yml new file mode 100644 index 0000000000..76415753b0 --- /dev/null +++ b/verif/docs/VerifPlans/FENCEI/VP_IP006.yml @@ -0,0 +1,35 @@ +!Feature +next_elt_id: 1 +name: UnusedFields +id: 6 +display_order: 6 +subfeatures: !!omap +- 000_UnusedFields: !Subfeature + name: 000_UnusedFields + tag: VP_FENCEI_F006_S000 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FENCEI_F006_S000_I000 + description: imm[11:0], rs1, rd are reserved for future extensions, and implementations + shall ignore them + reqt_doc: "The RISC-V Instruction Set Manual\nVolume I: Unprivileged ISA\n\ + Document Version 20191213\nhttps://riscv.org/wp-content/uploads/2019/12/riscv-spec-20191213.pdf" + ref_mode: section + ref_page: '31' + ref_section: Chapter 3 + ref_viewer: firefox + verif_goals: Try giving random values in those fields and see that all else + works as expected + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/verif/docs/VerifPlans/FENCEI/runme.sh b/verif/docs/VerifPlans/FENCEI/runme.sh new file mode 100644 index 0000000000..1a172b8aed --- /dev/null +++ b/verif/docs/VerifPlans/FENCEI/runme.sh @@ -0,0 +1,34 @@ +############################################################################# +# Copyright (C) 2022 Thales DIS France SAS +# +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0. +# +# Original Author: Zbigniew Chamski (zbigniew.chamski@thalesgroup.com) +############################################################################# +#!/bin/sh + +# Location of project-specific directories +ROOTDIR=`readlink -f $(dirname "${BASH_SOURCE[0]}")` + +# Set up platform location. It can be anywhere but should contain +# a valid `vp_config.py` file in `vptool` directory. +# Here we use the verification tree from the example directory. +export PLATFORM_TOP_DIR="$ROOTDIR" + +# Set the printable name for the project that will be used +# in the human-readable documentation. +export PROJECT_NAME="FENCEI" + +# Set the alphanumerical identifier of the project that +# will be used to construct file names etc. +export PROJECT_IDENT="FENCEI" + +# Set the destination directory of Markdown files for this project. +# Since it will be used by VPTOOL, it shall NOT be a relative path. +export MARKDOWN_OUTPUT_DIR=`readlink -f "$ROOTDIR/../source"` + +# Run VPTOOL overriding the default theme from Yaml config with 'winxpblue'. +# FIXME: Introduce a suitably named shell variable that points to the root +# directory of the tool set (TOOL_TOP etc.) +# FORNOW use a hardcoded relative path. +sh $ROOTDIR/../../../../tools/vptool/vptool.sh $* diff --git a/verif/docs/VerifPlans/FRONTEND/VP_IP003.yml b/verif/docs/VerifPlans/FRONTEND/VP_IP003.yml new file mode 100644 index 0000000000..83439bc394 --- /dev/null +++ b/verif/docs/VerifPlans/FRONTEND/VP_IP003.yml @@ -0,0 +1,422 @@ +!Feature +next_elt_id: 10 +name: PC generation stage +id: 3 +display_order: 3 +subfeatures: !!omap +- 001_BTB: !Subfeature + name: 001_BTB + tag: VP_IP003_P001 + next_elt_id: 6 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F003_S001_I000 + description: If instruction is a JALR and BTB (Branch Target Buffer) returns + a valid address, next PC is predicted by BTB. Else JALR is not considered + as a control flow instruction, which will generate a mispredict. + reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Branch Predict + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Execute a JALR instruction with a valid address in BTB which + is not a misprediction. Check that instruction queue is not flushed. + pfc: 4 + test_type: 0 + cov_method: 1 + cores: 16 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_FRONTEND_F003_S001_I001 + description: If instruction is a JALR and BTB (Branch Target Buffer) returns + a valid address, next PC is predicted by BTB. Else JALR is not considered + as a control flow instruction, which will generate a mispredict. + reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Branch Predict + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Execute a JALR instruction with a valid address in BTB which + is a misprediction. + pfc: 3 + test_type: 0 + cov_method: 1 + cores: 16 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_FRONTEND_F003_S001_I002 + description: "If instruction is a JALR and BTB (Branch Target Buffer) returns\ + \ a valid address, next PC is predicted by BTB.\n\nElse JALR is not considered\ + \ as a control flow instruction, which will generate a mispredict." + reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Branch Predict + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: 'Execute test with JALR instructions. Functional cov: JALR is + executed and BTB output is not valid.' + pfc: 3 + test_type: 0 + cov_method: 1 + cores: 8 + coverage_loc: '' + comments: '' +- 002_BHT: !Subfeature + name: 002_BHT + tag: VP_IP003_P002 + next_elt_id: 4 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F003_S002_I000 + description: If instruction is a branch and BTH (Branch History table) returns + a valid address, next PC is predicted by BHT. Else branch is not considered + as an control flow instruction, which will generate a mispredict when branch + is taken. + reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Branch Predict + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Execute a BRANCH instruction with a valid address in BHT which + is not a misprediction. Check that instruction queue is not flushed. + pfc: 4 + test_type: 0 + cov_method: 1 + cores: 16 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_FRONTEND_F003_S002_I001 + description: If instruction is a branch and BTH (Branch History table) returns + a valid address, next PC is predicted by BHT. Else branch is not considered + as an control flow instruction, which will generate a mispredict when branch + is taken. + reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Branch Predict + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Execute a BRANCH instruction with a valid address in BHT which + is a misprediction. + pfc: 3 + test_type: 0 + cov_method: 1 + cores: 16 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_FRONTEND_F003_S002_I002 + description: If instruction is a branch and BTH (Branch History table) returns + a valid address, next PC is predicted by BHT. Else branch is not considered + as an control flow instruction, which will generate a mispredict when branch + is taken. + reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Branch Predict + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: 'Execute test with BRANCH instructions. Functional cov: a BRANCH + is executed, BTB output is not valid and the branch is taken.' + pfc: 3 + test_type: 0 + cov_method: 1 + cores: 8 + coverage_loc: '' + comments: '' +- 003_RAS: !Subfeature + name: 003_RAS + tag: VP_IP003_P003 + next_elt_id: 4 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F003_S003_I000 + description: If instruction is a RET and RAS (Return Address Stack) returns + a valid address and RET has already been consummed by instruction queue. + Else RET is considered as a control flow instruction but next PC is not + predicted. A mispredict wil be generated. + reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Branch Predict + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Execute a RET instruction with a valid address in RAS. Check + that instruction queue is not flushed. + pfc: 3 + test_type: 0 + cov_method: 1 + cores: 16 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_FRONTEND_F003_S003_I001 + description: If instruction is a RET and RAS (Return Address Stack) returns + a valid address and RET has already been consummed by instruction queue. + Else RET is considered as a control flow instruction but next PC is not + predicted. A mispredict wil be generated. + reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Branch Predict + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Execute a RET instruction with a valid address in RAS which is + a misprediction. + pfc: 3 + test_type: 0 + cov_method: 1 + cores: 16 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_FRONTEND_F003_S003_I002 + description: If instruction is a RET and RAS (Return Address Stack) returns + a valid address and RET has already been consummed by instruction queue. + Else RET is considered as a control flow instruction but next PC is not + predicted. A mispredict wil be generated. + reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Branch Predict + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: 'Execute test with RET instructions. Functional cov: RET is executed + and RAS output is not valid.' + pfc: 3 + test_type: 0 + cov_method: 1 + cores: 8 + coverage_loc: '' + comments: '' +- 004_Return from environment call: !Subfeature + name: 004_Return from environment call + tag: VP_IP003_P004 + next_elt_id: 2 + display_order: 4 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F003_S004_I000 + description: When CSR asks a return from an environment call, the PC is assigned + to the successive PC to the one stored in the CSR [m-s]epc register. + reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Return from + env call + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Set two different addresses for mepc and sepc in CSR registers.\ + \ Use a arc_test returning from machine env call.\n\n* Check by assertion\ + \ that when machine return occurs the mepc address is fetched.\n* Functional\ + \ cov: execute a machine return." + pfc: 4 + test_type: 0 + cov_method: 1 + cores: 8 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_FRONTEND_F003_S004_I001 + description: When CSR asks a return from an environment call, the PC is assigned + to the successive PC to the one stored in the CSR [m-s]epc register. + reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Return from + env call + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Set two different addresses for mepc and sepc in CSR registers.\ + \ Use a returning from supervisor env call.\n\n* Check by assertion that\ + \ when supervisor return occurs the sepc address is fetched.\n* Functional\ + \ cov: execute a supervisor return." + pfc: 4 + test_type: 0 + cov_method: 1 + cores: 24 + coverage_loc: '' + comments: '' +- 005_Exception/Interrupt: !Subfeature + name: 005_Exception/Interrupt + tag: VP_IP003_P005 + next_elt_id: 2 + display_order: 5 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F003_S005_I000 + description: If an exception (or interrupt, which is in the context of RISC-V + systems quite similar) is triggered by the COMMIT, the next PC Gen is assigned + to the CSR trap vector base address. The trap vector base address can be + different depending on whether the exception traps to S-Mode or M-Mode (user + mode exceptions are currently not supported) + reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Exception + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: 'Set two different addresses for machine and supervisor handlers + in CSR registers. Use a test which executes in machine mode and generates + a machine exception by UVM. Check by assertion that when machine exception + occurs the machine address is fetched. Functional cov: exception occurs + in machine mode.' + pfc: 4 + test_type: 0 + cov_method: 1 + cores: 8 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_FRONTEND_F003_S005_I001 + description: If an exception (or interrupt, which is in the context of RISC-V + systems quite similar) is triggered by the COMMIT, the next PC Gen is assigned + to the CSR trap vector base address. The trap vector base address can be + different depending on whether the exception traps to S-Mode or M-Mode (user + mode exceptions are currently not supported) + reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Exception + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: 'Set two different addresses for machine and supervisor handlers + in CSR registers. Use a test which executes in supervisor mode and generates + a supervisor exception by UVM. Check by assertion that when supervisor exception + occurs the supervisor address is fetched. functional cov: exception occurs + in supervisor mode.' + pfc: 3 + test_type: 0 + cov_method: 1 + cores: 16 + coverage_loc: '' + comments: '' +- 006_Pipeline flush: !Subfeature + name: 006_Pipeline flush + tag: VP_IP003_P006 + next_elt_id: 2 + display_order: 6 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F003_S006_I000 + description: FRONTEND starts fetching from the next instruction again in order + to take the up-dated information into account + reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Pipeline flush + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: '[no need to verify this point]' + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 8 + coverage_loc: '' + comments: '' +- 007_Debug: !Subfeature + name: 007_Debug + tag: VP_IP003_P007 + next_elt_id: 1 + display_order: 7 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F003_S007_I000 + description: The debug jump is requested by CSR. The address to be jumped + into is HW coded. + reqt_doc: FRONTEND sub-system/functionality/PC generation stage/Debug + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: 'UVM generates a debug request to jump into debug handler. Check + by assertion that the HW coded debug address is fetched. Functional cov: + debug mode occurs' + pfc: 4 + test_type: 0 + cov_method: 1 + cores: 32 + coverage_loc: '' + comments: '' +- 008_Address mapping change: !Subfeature + name: 008_Address mapping change + tag: VP_IP003_P008 + next_elt_id: 1 + display_order: 8 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F003_S008_I000 + description: All program counters are logical addressed. If the logical to + physical mapping changes a fence.vm instruction should used to flush the + pipeline and TLBs + reqt_doc: FRONTEND sub-system/functionality/PC generation stage + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Execute a address mapping change, then execute a fence.vm instruction, + and continue the execution. + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 16 + coverage_loc: '' + comments: '' +- 009_Pc gen priority: !Subfeature + name: 009_Pc gen priority + tag: VP_IP003_P009 + next_elt_id: 3 + display_order: 9 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F003_S009_I000 + description: The next PC can originate from the following sources (listed + in order of precedence) + reqt_doc: FRONTEND sub-system/functionality/PC generation stage + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: 'Use arc_test executing return from env call and generate Exceptions + by UVM during reset, Branch predict, default, mispredict, replay and return + from env call. Functional cov: monitor the 6 events' + pfc: 3 + test_type: 0 + cov_method: 1 + cores: 8 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_FRONTEND_F003_S009_I002 + description: The next PC can originate from the following sources (listed + in order of precedence) + reqt_doc: FRONTEND sub-system/functionality/PC generation stage + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: '[other cases to be elaborated]' + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 8 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/verif/docs/VerifPlans/FRONTEND/VP_IP004.yml b/verif/docs/VerifPlans/FRONTEND/VP_IP004.yml new file mode 100644 index 0000000000..9b39ea709e --- /dev/null +++ b/verif/docs/VerifPlans/FRONTEND/VP_IP004.yml @@ -0,0 +1,104 @@ +!Feature +next_elt_id: 4 +name: BTB +id: 4 +display_order: 4 +subfeatures: !!omap +- 000_flush: !Subfeature + name: 000_flush + tag: VP_IP004_P000 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F004_S000_I000 + description: The BTB is never flushed. + reqt_doc: FRONTEND sub-system/Architecture and Modules/BTB + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "NA\n\n[Does it make sense?]" + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 0 + coverage_loc: '' + comments: '' +- 001_table depth: !Subfeature + name: 001_table depth + tag: VP_IP004_P001 + next_elt_id: 1 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F004_S001_I000 + description: The information is stored in a 8 entry table. + reqt_doc: FRONTEND sub-system/Architecture and Modules/BTB + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Confirm that the best configuration for BTB entry number is 8 + by monitoring the Coremark performance and silicon footprint, the configuration + without BTB is to be challenged too. + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 16 + coverage_loc: '' + comments: '' +- 002_Table update: !Subfeature + name: 002_Table update + tag: VP_IP004_P002 + next_elt_id: 1 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F004_S002_I000 + description: When a unconditional jumps to a register (JALR instruction) is + mispredicted by the EXECUTE, the relative information is stored into the + BTB, that is to say the JALR PC and the target address. + reqt_doc: FRONTEND sub-system/Architecture and Modules/BTB + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: When a mis predict occurs caused by JALR, check that info is + stored in BTB + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 16 + coverage_loc: '' + comments: '' +- 003_debug is not intrusive: !Subfeature + name: 003_debug is not intrusive + tag: VP_IP004_P003 + next_elt_id: 1 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F004_S003_I000 + description: The BTB is not updated if processor is in debug mode. + reqt_doc: FRONTEND sub-system/Architecture and Modules/BTB + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Execute a debug session, check that the table content is not + modified + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 32 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/verif/docs/VerifPlans/FRONTEND/VP_IP005.yml b/verif/docs/VerifPlans/FRONTEND/VP_IP005.yml new file mode 100644 index 0000000000..df4babd4dd --- /dev/null +++ b/verif/docs/VerifPlans/FRONTEND/VP_IP005.yml @@ -0,0 +1,152 @@ +!Feature +next_elt_id: 6 +name: BHT +id: 5 +display_order: 5 +subfeatures: !!omap +- 000_flush: !Subfeature + name: 000_flush + tag: VP_IP005_P000 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F005_S000_I000 + description: The BTB is never flushed. + reqt_doc: FRONTEND sub-system/Architecture and Modules/BHT + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "NA\n\n[Does it make sense?]" + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 0 + coverage_loc: '' + comments: '' +- 002_table update: !Subfeature + name: 002_table update + tag: VP_IP005_P002 + next_elt_id: 1 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F005_S002_I000 + description: When a branch instruction is resolved by the EXECUTE, the relative + information is stored in the Branch History Table. + reqt_doc: FRONTEND sub-system/Architecture and Modules/BHT + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: When a mis predict occurs caused by BRANCH, check that info is + stored in BHT + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 16 + coverage_loc: '' + comments: '' +- 003_saturation: !Subfeature + name: 003_saturation + tag: VP_IP005_P003 + next_elt_id: 2 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F005_S003_I000 + description: The Branch History table is a two-bit saturation counter that + takes the virtual address of the current fetched instruction by the CACHE. + It states whether the current branch request should be taken or not. The + two bit counter is updated by the successive execution of the current instructions + as shown in the following figure. + reqt_doc: FRONTEND sub-system/Architecture and Modules/BHT + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Execute a serie of taken and not taken branch to check the saturation + mechanism + pfc: -1 + test_type: -1 + cov_method: -1 + cores: -1 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_FRONTEND_F005_S003_I001 + description: The Branch History table is a two-bit saturation counter that + takes the virtual address of the current fetched instruction by the CACHE. + It states whether the current branch request should be taken or not. The + two bit counter is updated by the successive execution of the current instructions + as shown in the following figure. + reqt_doc: FRONTEND sub-system/Architecture and Modules/BHT + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Verify the saturation mechnism is optimal. Modify the saturation + mechanism by removing/adding one stage, and check the Coremark performance + evolution + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 16 + coverage_loc: '' + comments: '' +- 004_Table depth: !Subfeature + name: 004_Table depth + tag: VP_IP005_P004 + next_elt_id: 1 + display_order: 4 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F005_S004_I000 + description: The information is stored in a 1024 entry table. + reqt_doc: FRONTEND sub-system/Architecture and Modules/BHT + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Confirm that the best configuration for BHT entry number is 1024 + by monitoring the Coremark performance and silicon footprint, the configuration + without BHT is to be challenged too. + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 16 + coverage_loc: '' + comments: '' +- 005_Debug is not intrusive: !Subfeature + name: 005_Debug is not intrusive + tag: VP_IP005_P005 + next_elt_id: 1 + display_order: 5 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F005_S005_I000 + description: The BHT is not updated if processor is in debug mode. + reqt_doc: FRONTEND sub-system/Architecture and Modules/BHT + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Execute a debug session, check that the table content is not + modified + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 32 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/verif/docs/VerifPlans/FRONTEND/VP_IP006.yml b/verif/docs/VerifPlans/FRONTEND/VP_IP006.yml new file mode 100644 index 0000000000..76b06d4982 --- /dev/null +++ b/verif/docs/VerifPlans/FRONTEND/VP_IP006.yml @@ -0,0 +1,104 @@ +!Feature +next_elt_id: 4 +name: RAS +id: 6 +display_order: 6 +subfeatures: !!omap +- 000_flush: !Subfeature + name: 000_flush + tag: VP_IP006_P000 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F006_S000_I000 + description: The RAS is never flushed. + reqt_doc: FRONTEND sub-system/Architecture and Modules/RAS + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "NA\n\n[Does it make sense?]" + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 0 + coverage_loc: '' + comments: '' +- 001_table depth: !Subfeature + name: 001_table depth + tag: VP_IP006_P001 + next_elt_id: 1 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F006_S001_I000 + description: The RAS FIFO depth is 2. + reqt_doc: FRONTEND sub-system/Architecture and Modules/RAS + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Confirm that the best configuration for RAS entry number is 2 + by monitoring the Coremark performance and silicon footprint, the configuration + without RAS is to be challenged too. + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 16 + coverage_loc: '' + comments: '' +- 002_Table update: !Subfeature + name: 002_Table update + tag: VP_IP006_P002 + next_elt_id: 1 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F006_S002_I000 + description: When an unconditional jumps to a known target address (JAL instruction) + is consummed by the instr_queue, the next pc after the JAL instruction and + the return address are stored into a FIFO. + reqt_doc: FRONTEND sub-system/Architecture and Modules/RAS + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: When a JAL instruction is executed, check that info is stored + in RAS + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 16 + coverage_loc: '' + comments: '' +- 003_Debug is not intrusive: !Subfeature + name: 003_Debug is not intrusive + tag: VP_IP006_P003 + next_elt_id: 1 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F006_S003_I000 + description: No dedicated specification + reqt_doc: FRONTEND sub-system/Architecture and Modules/RAS + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Execute a debug session, check that the table content is not + modified + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 32 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/verif/docs/VerifPlans/FRONTEND/VP_IP007.yml b/verif/docs/VerifPlans/FRONTEND/VP_IP007.yml new file mode 100644 index 0000000000..365f818e39 --- /dev/null +++ b/verif/docs/VerifPlans/FRONTEND/VP_IP007.yml @@ -0,0 +1,66 @@ +!Feature +next_elt_id: 2 +name: Instr_realign +id: 7 +display_order: 7 +subfeatures: !!omap +- 000_C extension: !Subfeature + name: 000_C extension + tag: VP_IP007_P000 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F007_S000_I000 + description: The 32-bit aligned block coming from the CACHE sub-system enters + the instr_realign module. This module extracts the instructions from the + 32-bit blocks, up to two instructions because it is possible to fetch two + instructions when C extension is used. If the instructions are not compressed, + it is possible that the instruction is not aligned on the block size but + rather interleaved with two cache blocks. In that case, two cache accesses + are needed. The instr_realign module provides at maximum one instruction + per cycle. Not complete instruction is stored in instr_realign module before + being provided in the next cycles. + reqt_doc: FRONTEND sub-system/Architecture and Modules/Instr_realign + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Execute program compiled with C extension. Cover the case when\ + \ 2 instructions are fetched in the same cache block and when an instruction\ + \ is interleaved with two cache block\n\n[NO NEED TO VERIFY THIS CASE]" + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 0 + coverage_loc: '' + comments: '' +- 001_Flush: !Subfeature + name: 001_Flush + tag: VP_IP007_P001 + next_elt_id: 1 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F007_S001_I000 + description: In case of mispredict, flush, replay or branch predict, the instr_realign + is re-initialized, the internal register storing the instruction alignment + state is reset. + reqt_doc: FRONTEND sub-system/Architecture and Modules/Instr_realign + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: '[NO NEED TO VERIFY THIS CASE]' + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 0 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/verif/docs/VerifPlans/FRONTEND/VP_IP008.yml b/verif/docs/VerifPlans/FRONTEND/VP_IP008.yml new file mode 100644 index 0000000000..0559c2d9d1 --- /dev/null +++ b/verif/docs/VerifPlans/FRONTEND/VP_IP008.yml @@ -0,0 +1,80 @@ +!Feature +next_elt_id: 3 +name: Instr_queue +id: 8 +display_order: 8 +subfeatures: !!omap +- 000_FIFO depth: !Subfeature + name: 000_FIFO depth + tag: VP_IP008_P000 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F008_S000_I000 + description: The instruction queue contains max 4 instructions. + reqt_doc: FRONTEND sub-system/Architecture and Modules/Instr_queue + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Confirm that the best configuration for instruction queue entry + number is 4 by monitoring the Coremark performance and silicon footprint + pfc: 11 + test_type: 10 + cov_method: 10 + cores: 8 + coverage_loc: '' + comments: '' +- 001_Page fault exception: !Subfeature + name: 001_Page fault exception + tag: VP_IP008_P001 + next_elt_id: 1 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F008_S001_I000 + description: In instruction queue, exception can only correspond to page-fault + exception. + reqt_doc: FRONTEND sub-system/Architecture and Modules/Instr_queue + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: 'Execute following exception and check that only page-fault can + be stored in instruction queue: bus errors, invalid accesses or instruction + page faults.' + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 16 + coverage_loc: '' + comments: '' +- 002_Flush: !Subfeature + name: 002_Flush + tag: VP_IP008_P002 + next_elt_id: 1 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F008_S002_I000 + description: The instruction queue can be flushed by CONTROLLER. + reqt_doc: FRONTEND sub-system/Architecture and Modules/Instr_queue + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: '[NO NEED TO VERIFY THIS CASE]' + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 0 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/verif/docs/VerifPlans/FRONTEND/VP_IP009.yml b/verif/docs/VerifPlans/FRONTEND/VP_IP009.yml new file mode 100644 index 0000000000..6ec7a33b7e --- /dev/null +++ b/verif/docs/VerifPlans/FRONTEND/VP_IP009.yml @@ -0,0 +1,10 @@ +!Feature +next_elt_id: 0 +name: Instr_scan +id: 9 +display_order: 9 +subfeatures: !!omap [] +vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/verif/docs/VerifPlans/FRONTEND/VP_IP010.yml b/verif/docs/VerifPlans/FRONTEND/VP_IP010.yml new file mode 100644 index 0000000000..fe95149ac9 --- /dev/null +++ b/verif/docs/VerifPlans/FRONTEND/VP_IP010.yml @@ -0,0 +1,114 @@ +!Feature +next_elt_id: 3 +name: Fetch stage +id: 10 +display_order: 10 +subfeatures: !!omap +- 001_MMU translation: !Subfeature + name: 001_MMU translation + tag: VP_IP010_P001 + next_elt_id: 2 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F010_S001_I000 + description: The Fetch stage asks the MMU to translate the requested address. + reqt_doc: FRONTEND sub-system/functionality/Fetch stage + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Execute a program with virtual PC + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 16 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_FRONTEND_F010_S001_I001 + description: The Fetch stage asks the MMU to translate the requested address. + reqt_doc: FRONTEND sub-system/functionality/Fetch stage + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Check the translation does not impact execution time by executing + Coremark in pphysical and virtual modes. + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 16 + coverage_loc: '' + comments: '' +- 002_Exceptions: !Subfeature + name: 002_Exceptions + tag: VP_IP010_P002 + next_elt_id: 4 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_FRONTEND_F010_S002_I000 + description: Memory and MMU (MMU is not enabled in CV32A6-step1) can feedback + potential exceptions generated by the memory fetch request. They can be + bus errors, invalid accesses or instruction page faults. + reqt_doc: FRONTEND sub-system/functionality/Fetch stage + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: 'Generate a bus error exception by UVM or by test (to be decided) + and check that the exception address is fetched. Functional cov: a bus error + exception occurs.' + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 8 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_FRONTEND_F010_S002_I002 + description: Memory and MMU (MMU is not enabled in CV32A6-step1) can feedback + potential exceptions generated by the memory fetch request. They can be + bus errors, invalid accesses or instruction page faults. + reqt_doc: FRONTEND sub-system/functionality/Fetch stage + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: 'Generate an invalid access exception by UVM or by test (to be + decided) and check that the exception address is fetched. Functional cov: + an invalid access exception occurs.' + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 8 + coverage_loc: '' + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_FRONTEND_F010_S002_I003 + description: Memory and MMU (MMU is not enabled in CV32A6-step1) can feedback + potential exceptions generated by the memory fetch request. They can be + bus errors, invalid accesses or instruction page faults. + reqt_doc: FRONTEND sub-system/functionality/Fetch stage + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Generate an instruction page faults and check that the exception + is triggered + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 16 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: 755afe774cedc2d4910aa802ee20a1f485c1236e $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/verif/docs/VerifPlans/FRONTEND/runme.sh b/verif/docs/VerifPlans/FRONTEND/runme.sh new file mode 100644 index 0000000000..b808624f88 --- /dev/null +++ b/verif/docs/VerifPlans/FRONTEND/runme.sh @@ -0,0 +1,34 @@ +############################################################################# +# Copyright (C) 2022 Thales DIS France SAS +# +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0. +# +# Original Author: Zbigniew Chamski (zbigniew.chamski@thalesgroup.com) +############################################################################# +#!/bin/sh + +# Location of project-specific directories +ROOTDIR=`readlink -f $(dirname "${BASH_SOURCE[0]}")` + +# Set up platform location. It can be anywhere but should contain +# a valid `vp_config.py` file in `vptool` directory. +# Here we use the verification tree from the example directory. +export PLATFORM_TOP_DIR="$ROOTDIR" + +# Set the printable name for the project that will be used +# in the human-readable documentation. +export PROJECT_NAME="FRONTEND" + +# Set the alphanumerical identifier of the project that +# will be used to construct file names etc. +export PROJECT_IDENT="FRONTEND" + +# Set the destination directory of Markdown files for this project. +# Since it will be used by VPTOOL, it shall NOT be a relative path. +export MARKDOWN_OUTPUT_DIR=`readlink -f "$ROOTDIR/../source"` + +# Run VPTOOL overriding the default theme from Yaml config with 'winxpblue'. +# FIXME: Introduce a suitably named shell variable that points to the root +# directory of the tool set (TOOL_TOP etc.) +# FORNOW use a hardcoded relative path. +sh $ROOTDIR/../../../../tools/vptool/vptool.sh $* diff --git a/verif/docs/VerifPlans/ISA_RV32/RISCV_Instructions.rst b/verif/docs/VerifPlans/ISA_RV32/RISCV_Instructions.rst new file mode 100644 index 0000000000..bb463b7134 --- /dev/null +++ b/verif/docs/VerifPlans/ISA_RV32/RISCV_Instructions.rst @@ -0,0 +1,1365 @@ +.. + Copyright (c) 2023 OpenHW Group + Copyright (c) 2023 Thales DIS design services SAS + + SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + +.. Level 1 + ======= + + Level 2 + ------- + + Level 3 + ~~~~~~~ + + Level 4 + ^^^^^^^ + +.. _cva6_riscv_instructions: + +RISC-V Instructions +=================== + +Introduction +------------------ + +In this document, we present ISA (Instruction Set Architecture) for C32VA6_v5.0.0, illustrating different supported instructions, the Base Integer Instruction set RV32I, and also other instructions in some extensions supported by the core as: + +* RV32M – Standard Extension for Integer Multiplication and Division Instructions +* RV32A – Standard Extension for Atomic Instructions +* RV32C – Standard Extension for Compressed Instructions +* RV32Zicsr – Standard Extension for CSR Instructions +* RV32Zifencei – Standard Extension for Instruction-Fetch Fence + +The base RISC-V ISA has fixed-length 32-bit instructions or 16-bit instructions (the C32VA6_v5.0.0 support C extension), so that must be naturally aligned on 4-byte boundary or 2-byte boundary. +The C32VA6_v5.0.0 supports: + +* Only 1 hart, +* No misaligned memory accesses. + +General purpose registers +-------------------------- + +As shown in the Table 1.1, there are 31 general-purpose registers x1–x31, which hold integer values. Register x0 is hardwired to the constant 0. There is no hardwired subroutine return address link register, but the standard software calling convention uses register x1 to hold the return address on a call. For C32VA6_v5.0.0, the x registers are 32 bits wide. There is one additional register also 32 bits wide: the program counter pc holds the address of the current instruction. + +Table 1.1 shows the general-purpose registers : + +.. list-table:: + :widths: 20 20 15 15 20 + :header-rows: 1 + + * - **5-bit Encoding (rx)** + - **3-bit Compressed Encoding (rx')** + - **Register (ISA name)** + - **Register (ABI name)** + - **Description** + * - 0 + - + - x0 + - zero + - Hardwired zero + * - 1 + - + - x1 + - ra + - Return address (link register) + * - 2 + - + - x2 + - sp + - Stack pointer + * - 3 + - + - x3 + - gp + - Global pointer + * - 4 + - + - x4 + - tp + - Thread pointer + * - 5 + - + - x5 + - t0 + - Temporaries/alternate link register + * - 6 - 7 + - + - x6 - x7 + - t1 - t2 + - Temporaries + * - 8 + - 0 + - x8 + - s0/fp + - Saved register/frame pointer + * - 9 + - 1 + - x9 + - s1 + - Saved registers + * - 10 - 11 + - 2 - 3 + - x10 - x11 + - a0 - a1 + - Function arguments/return value + * - 12 - 15 + - 4 - 7 + - x12 - x15 + - a2 - a5 + - Function arguments + * - 16 - 17 + - + - x16 - x17 + - a6 - a7 + - Function arguments + * - 18 - 27 + - + - x18 - x27 + - s2 - s11 + - Saved registers + * - 28 - 31 + - + - x28 - x31 + - t3 - t6 + - Temporaries + +Conventions and Terminology +----------------------------- + +- **sext(val)**: Sign Extension is the operation of increasing the number of bits of a binary number while preserving the number's sign (positive(0)/negative(1)) and value. this is done by appending digits to the most significant side of the number. + +- **zext(val)**: Zero Extension is the operation of increasing the number of bits of a binary number with zeros. this is done by appending digits to the most significant side of the number. + +- **<u**: Comparison operation (less than) of 2 unsigned values. + +- **>>s**: Right shift of 2 signed values. + +- **>>u**: Right shift of 2 unsigned values. + +- **M[address]**: Value existe in the address of the memory. + +- **/s**: Division of 2 signed values. + +- **/u**: Division of 2 unsigned values. + +- **%s**: Remainder of the Division of 2 signed values. + +- **%u**: Remainder of the Division of 2 unsigned values. + +- **AMO32**: Atomic Memory Operation (word). + +- **rx'**: rd', rs1' or rs2', stand for the 3-bit Compressed Encoding registers. + +RV32I Base Integer Instruction Set +----------------------------------- + +This section describes the RV32I base integer instruction set. + +Integer Register-Immediate Instructions +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +- **ADDI**: Add Immediate + + **Format**: addi rd, rs1, imm[11:0] + + **Description**: add sign-extended 12-bit immediate to register rs1, and store the result in register rd. + + **Pseudocode**: x[rd] = x[rs1] + sext(imm[11:0]) + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **ANDI**: AND Immediate + + **Format**: andi rd, rs1, imm[11:0] + + **Description**: perform bitwise AND on register rs1 and the sign-extended 12-bit immediate and place the result in rd. + + **Pseudocode**: x[rd] = x[rs1] & sext(imm[11:0]) + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **ORI**: OR Immediate + + **Format**: ori rd, rs1, imm[11:0] + + **Description**: perform bitwise OR on register rs1 and the sign-extended 12-bit immediate and place the result in rd. + + **Pseudocode**: x[rd] = x[rs1] | sext(imm[11:0]) + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **XORI**: XOR Immediate + + **Format**: xori rd, rs1, imm[11:0] + + **Description**: perform bitwise XOR on register rs1 and the sign-extended 12-bit immediate and place the result in rd. + + **Pseudocode**: x[rd] = x[rs1] ^ sext(imm[11:0]) + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **SLTI**: Set Less Then Immediate + + **Format**: slti rd, rs1, imm[11:0] + + **Description**: set register rd to 1 if register rs1 is less than the sign extended immediate when both are treated as signed numbers, else 0 is written to rd. + + **Pseudocode**: if (x[rs1] < sext(imm[11:0]) x[rd] = 1 else x[rd] = 0 + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **SLTIU**: Set Less Then Immediate Unsigned + + **Format**: sltiu rd, rs1, imm[11:0] + + **Description**: set register rd to 1 if register rs1 is less than the sign extended immediate when both are treated as unsigned numbers, else 0 is written to rd. + + **Pseudocode**: if (x[rs1] <u sext(imm[11:0]) x[rd] = 1 else x[rd] = 0 + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **SLLI**: Shift Left Logic Immediate + + **Format**: slli rd, rs1, imm[4:0] + + **Description**: logical left shift (zeros are shifted into the lower bits). + + **Pseudocode**: x[rd] = x[rs1] << imm[4:0] + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **SRLI**: Shift Right Logic Immediate + + **Format**: srli rd, rs1, imm[4:0] + + **Description**: logical right shift (zeros are shifted into the upper bits). + + **Pseudocode**: x[rd] = x[rs1] >> imm[4:0] + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **SRAI**: Shift Right Arithmetic Immediate + + **Format**: srai rd, rs1, imm[4:0] + + **Description**: arithmetic right shift (the original sign bit is copied into the vacated upper bits). + + **Pseudocode**: x[rd] = x[rs1] >>s imm[4:0] + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **LUI**: Load Upper Immediate + + **Format**: lui rd, imm[19:0] + + **Description**: place the immediate value in the top 20 bits of the destination register rd, filling in the lowest 12 bits with zeros. + + **Pseudocode**: x[rd] = sext(imm[31:12] << 12) + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **AUIPC**: Add Upper Immediate to PC + + **Format**: auipc rd, imm[19:0] + + **Description**: form a 32-bit offset from the 20-bit immediate, filling in the lowest 12 bits with zeros, adds this offset to the pc, then place the result in register rd. + + **Pseudocode**: x[rd] = pc + sext(immediate[31:12] << 12) + + **Invalid values**: NONE + + **Exception raised**: NONE + +Integer Register-Register Instructions +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +- **ADD**: Addition + + **Format**: add rd, rs1, rs2 + + **Description**: add rs2 to register rs1, and store the result in register rd. + + **Pseudocode**: x[rd] = x[rs1] + x[rs2] + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **SUB**: Subtraction + + **Format**: sub rd, rs1, rs2 + + **Description**: subtract rs2 from register rs1, and store the result in register rd. + + **Pseudocode**: x[rd] = x[rs1] - x[rs2] + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **AND**: AND logical operator + + **Format**: and rd, rs1, rs2 + + **Description**: perform bitwise AND on register rs1 and rs2 and place the result in rd. + + **Pseudocode**: x[rd] = x[rs1] & x[rs2] + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **OR**: OR logical operator + + **Format**: or rd, rs1, rs2 + + **Description**: perform bitwise OR on register rs1 and rs2 and place the result in rd. + + **Pseudocode**: x[rd] = x[rs1] | x[rs2] + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **XOR**: XOR logical operator + + **Format**: xor rd, rs1, rs2 + + **Description**: perform bitwise XOR on register rs1 and rs2 and place the result in rd. + + **Pseudocode**: x[rd] = x[rs1] ^ x[rs2] + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **SLT**: Set Less Then + + **Format**: slt rd, rs1, rs2 + + **Description**: set register rd to 1 if register rs1 is less than rs2 when both are treated as signed numbers, else 0 is written to rd. + + **Pseudocode**: if (x[rs1] < x[rs2]) x[rd] = 1 else x[rd] = 0 + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **SLTU**: Set Less Then Unsigned + + **Format**: sltu rd, rs1, rs2 + + **Description**: set register rd to 1 if register rs1 is less than rs2 when both are treated as unsigned numbers, else 0 is written to rd. + + **Pseudocode**: if (x[rs1] <u x[rs2]) x[rd] = 1 else x[rd] = 0 + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **SLL**: Shift Left Logic + + **Format**: sll rd, rs1, rs2 + + **Description**: logical left shift (zeros are shifted into the lower bits). + + **Pseudocode**: x[rd] = x[rs1] << x[rs2] + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **SRL**: Shift Right Logic + + **Format**: srl rd, rs1, rs2 + + **Description**: logical right shift (zeros are shifted into the upper bits). + + **Pseudocode**: x[rd] = x[rs1] >> x[rs2] + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **SRA**: Shift Right Arithmetic + + **Format**: sra rd, rs1, rs2 + + **Description**: arithmetic right shift (the original sign bit is copied into the vacated upper bits). + + **Pseudocode**: x[rd] = x[rs1] >>s x[rs2] + + **Invalid values**: NONE + + **Exception raised**: NONE + +Control Transfer Instructions +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +**Unconditional Jumps** + +- **JAL**: Jump and Link + + **Format**: jal rd, imm[20:1] + + **Description**: offset is sign-extended and added to the pc to form the jump target address (pc is calculated using signed arithmetic), then setting the least-significant bit of the result to zero, and store the address of instruction following the jump (pc+4) into register rd. + + **Pseudocode**: x[rd] = pc+4; pc += sext(imm[20:1]) + + **Invalid values**: NONE + + **Exception raised**: jumps to an unaligned address (4-byte or 2-byte boundary) will usually raise an exception. + +- **JALR**: Jump and Link Register + + **Format**: jalr rd, rs1, imm[11:0] + + **Description**: target address is obtained by adding the 12-bit signed immediate to the register rs1 (pc is calculated using signed arithmetic), then setting the least-significant bit of the result to zero, and store the address of instruction following the jump (pc+4) into register rd. + + **Pseudocode**: t = pc+4; pc = (x[rs1]+sext(imm[11:0]))&∼1 ; x[rd] = t + + **Invalid values**: NONE + + **Exception raised**: jumps to an unaligned address (4-byte or 2-byte boundary) will usually raise an exception. + +**Conditional Branches** + +- **BEQ**: Branch Equal + + **Format**: beq rs1, rs2, imm[12:1] + + **Description**: takes the branch (pc is calculated using signed arithmetic) if registers rs1 and rs2 are equal. + + **Pseudocode**: if (x[rs1] == x[rs2]) pc += sext({imm[12:1], 1’b0}) else pc += 4 + + **Invalid values**: NONE + + **Exception raised**: no instruction fetch misaligned exception is generated for a conditional branch that is not taken. An Instruction address misaligned exception is raised if the target address is not aligned on 4-byte or 2-byte boundary, because the core supports compressed instructions. + +- **BNE**: Branch Not Equal + + **Format**: bne rs1, rs2, imm[12:1] + + **Description**: takes the branch (pc is calculated using signed arithmetic) if registers rs1 and rs2 are not equal. + + **Pseudocode**: if (x[rs1] != x[rs2]) pc += sext({imm[12:1], 1’b0}) else pc += 4 + + **Invalid values**: NONE + + **Exception raised**: no instruction fetch misaligned exception is generated for a conditional branch that is not taken. An Instruction address misaligned exception is raised if the target address is not aligned on 4-byte or 2-byte boundary, because the core supports compressed instructions. + +- **BLT**: Branch Less Than + + **Format**: blt rs1, rs2, imm[12:1] + + **Description**: takes the branch (pc is calculated using signed arithmetic) if registers rs1 less than rs2 (using signed comparison). + + **Pseudocode**: if (x[rs1] < x[rs2]) pc += sext({imm[12:1], 1’b0}) else pc += 4 + + **Invalid values**: NONE + + **Exception raised**: no instruction fetch misaligned exception is generated for a conditional branch that is not taken. An Instruction address misaligned exception is raised if the target address is not aligned on 4-byte or 2-byte boundary, because the core supports compressed instructions. + +- **BLTU**: Branch Less Than Unsigned + + **Format**: bltu rs1, rs2, imm[12:1] + + **Description**: takes the branch (pc is calculated using signed arithmetic) if registers rs1 less than rs2 (using unsigned comparison). + + **Pseudocode**: if (x[rs1] <u x[rs2]) pc += sext({imm[12:1], 1’b0}) else pc += 4 + + **Invalid values**: NONE + + **Exception raised**: no instruction fetch misaligned exception is generated for a conditional branch that is not taken. An Instruction address misaligned exception is raised if the target address is not aligned on 4-byte or 2-byte boundary, because the core supports compressed instructions. + +- **BGE**: Branch Greater or Equal + + **Format**: bge rs1, rs2, imm[12:1] + + **Description**: takes the branch (pc is calculated using signed arithmetic) if registers rs1 is greater than or equal rs2 (using signed comparison). + + **Pseudocode**: if (x[rs1] >= x[rs2]) pc += sext({imm[12:1], 1’b0}) else pc += 4 + + **Invalid values**: NONE + + **Exception raised**: no instruction fetch misaligned exception is generated for a conditional branch that is not taken. An Instruction address misaligned exception is raised if the target address is not aligned on 4-byte or 2-byte boundary, because the core supports compressed instructions. + +- **BGEU**: Branch Greater or Equal Unsigned + + **Format**: bgeu rs1, rs2, imm[12:1] + + **Description**: takes the branch (pc is calculated using signed arithmetic) if registers rs1 is greater than or equal rs2 (using unsigned comparison). + + **Pseudocode**: if (x[rs1] >=u x[rs2]) pc += sext({imm[12:1], 1’b0}) else pc += 4 + + **Invalid values**: NONE + + **Exception raised**: no instruction fetch misaligned exception is generated for a conditional branch that is not taken. An Instruction address misaligned exception is raised if the target address is not aligned on 4-byte or 2-byte boundary, because the core supports compressed instructions. + +Load and Store Instructions +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +- **LB**: Load Byte + + **Format**: lb rd, imm(rs1) + + **Description**: loads a 8-bit value from memory, then sign-extends to 32-bit before storing in rd (rd is calculated using signed arithmetic), the effective address is obtained by adding register rs1 to the sign-extended 12-bit offset. + + **Pseudocode**: x[rd] = sext(M[x[rs1] + sext(imm[11:0])][7:0]) + + **Invalid values**: NONE + + **Exception raised**: loads with a destination of x0 must still raise any exceptions and action any other side effects even though the load value is discarded. + +- **LH**: Load Halfword + + **Format**: lh rd, imm(rs1) + + **Description**: loads a 16-bit value from memory, then sign-extends to 32-bit before storing in rd (rd is calculated using signed arithmetic), the effective address is obtained by adding register rs1 to the sign-extended 12-bit offset. + + **Pseudocode**: x[rd] = sext(M[x[rs1] + sext(imm[11:0])][15:0]) + + **Invalid values**: NONE + + **Exception raised**: loads with a destination of x0 must still raise any exceptions and action any other side effects even though the load value is discarded, also an exception is raised if the memory address isn't aligned (2-byte boundary). + +- **LW**: Load Word + + **Format**: lw rd, imm(rs1) + + **Description**: loads a 32-bit value from memory, then storing in rd (rd is calculated using signed arithmetic). The effective address is obtained by adding register rs1 to the sign-extended 12-bit offset. + + **Pseudocode**: x[rd] = sext(M[x[rs1] + sext(imm[11:0])][31:0]) + + **Invalid values**: NONE + + **Exception raised**: loads with a destination of x0 must still raise any exceptions and action any other side effects even though the load value is discarded, also an exception is raised if the memory address isn't aligned (4-byte boundary). + +- **LBU**: Load Byte Unsigned + + **Format**: lbu rd, imm(rs1) + + **Description**: loads a 8-bit value from memory, then zero-extends to 32-bit before storing in rd (rd is calculated using unsigned arithmetic), the effective address is obtained by adding register rs1 to the sign-extended 12-bit offset. + + **Pseudocode**: x[rd] = zext(M[x[rs1] + sext(imm[11:0])][7:0]) + + **Invalid values**: NONE + + **Exception raised**: loads with a destination of x0 must still raise any exceptions and action any other side effects even though the load value is discarded. + +- **LHU**: Load Halfword Unsigned + + **Format**: lhu rd, imm(rs1) + + **Description**: loads a 16-bit value from memory, then zero-extends to 32-bit before storing in rd (rd is calculated using unsigned arithmetic), the effective address is obtained by adding register rs1 to the sign-extended 12-bit offset. + + **Pseudocode**: x[rd] = zext(M[x[rs1] + sext(imm[11:0])][15:0]) + + **Invalid values**: NONE + + **Exception raised**: loads with a destination of x0 must still raise any exceptions and action any other side effects even though the load value is discarded, also an exception is raised if the memory address isn't aligned (2-byte boundary). + +- **SB**: Store Byte + + **Format**: sb rs2, imm(rs1) + + **Description**: stores a 8-bit value from the low bits of register rs2 to memory, the effective address is obtained by adding register rs1 to the sign-extended 12-bit offset. + + **Pseudocode**: M[x[rs1] + sext(imm[11:0])][7:0] = x[rs2][7:0] + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **SH**: Store Halfword + + **Format**: sh rs2, imm(rs1) + + **Description**: stores a 16-bit value from the low bits of register rs2 to memory, the effective address is obtained by adding register rs1 to the sign-extended 12-bit offset. + + **Pseudocode**: M[x[rs1] + sext(imm[11:0])][15:0] = x[rs2][15:0] + + **Invalid values**: NONE + + **Exception raised**: an exception is raised if the memory address isn't aligned (2-byte boundary). + +- **SW**: Store Word + + **Format**: sw rs2, imm(rs1) + + **Description**: stores a 32-bit value from register rs2 to memory, the effective address is obtained by adding register rs1 to the sign-extended 12-bit offset. + + **Pseudocode**: M[x[rs1] + sext(imm[11:0])][31:0] = x[rs2][31:0] + + **Invalid values**: NONE + + **Exception raised**: an exception is raised if the memory address isn't aligned (4-byte boundary). + +Memory Ordering +^^^^^^^^^^^^^^^^^^ + +- **FENCE**: Fence Instruction + + **Format**: fence pre, succ + + **Description**: order device I/O and memory accesses as viewed by other RISC-V harts and external devices or coprocessors. Any combination of device input (I), device output (O), memory reads (R), and memory writes (W) may be ordered with respect to any combination of the same. Informally, no other RISC-V hart or external device can observe any operation in the successor set following a FENCE before any operation in the predecessor set preceding the FENCE, as the core support 1 hart, the fence instruction has no effect so we can considerate it as a nop instruction. + + **Pseudocode**: No operation (nop) + + **Invalid values**: NONE + + **Exception raised**: NONE + +Environment Call and Breakpoints +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +- **ECALL**: Environment Call + + **Format**: ecall + + **Description**: make a request to the supporting execution environment, which is usually an operating system. The ABI for the system will define how parameters for the environment request are passed, but usually these will be in defined locations in the integer register file. + + **Pseudocode**: RaiseException(EnvironmentCall) + + **Invalid values**: NONE + + **Exception raised**: Raise an Environment Call exception. + +- **EBREAK**:Environment Break + + **Format**: ebreak + + **Description**: cause control to be transferred back to a debugging environment. + + **Pseudocode**: RaiseException(Breakpoint) + + **Invalid values**: NONE + + **Exception raised**: Raise a Breakpoint exception. + +RV32M Multiplication and Division Instructions +------------------------------------------------------ + +This chapter describes the standard integer multiplication and division instruction extension, which +is named “M” and contains instructions that multiply or divide values held in two integer registers. + +Multiplication Operations +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +- **MUL**: Multiplication + + **Format**: mul rd, rs1, rs2 + + **Description**: performs a 32-bit × 32-bit multiplication and places the lower 32 bits in the destination register (Both rs1 and rs2 treated as signed numbers). + + **Pseudocode**: x[rd] = x[rs1] * x[rs2] + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **MULH**: Multiplication Higher + + **Format**: mulh rd, rs1, rs2 + + **Description**: performs a 32-bit × 32-bit multiplication and places the upper 32 bits in the destination register of the 64-bit product (Both rs1 and rs2 treated as signed numbers). + + **Pseudocode**: x[rd] = (x[rs1] s*s x[rs2]) >>s 32 + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **MULHU**: Multiplication Higher Unsigned + + **Format**: mulhu rd, rs1, rs2 + + **Description**: performs a 32-bit × 32-bit multiplication and places the upper 32 bits in the destination register of the 64-bit product (Both rs1 and rs2 treated as unsigned numbers). + + **Pseudocode**: x[rd] = (x[rs1] u*u x[rs2]) >>u 32 + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **MULHSU**: Multiplication Higher Signed Unsigned + + **Format**: mulhsu rd, rs1, rs2 + + **Description**: performs a 32-bit × 32-bit multiplication and places the upper 32 bits in the destination register of the 64-bit product (rs1 treated as signed number, rs2 treated as unsigned number). + + **Pseudocode**: x[rd] = (x[rs1] s*u x[rs2]) >>s 32 + + **Invalid values**: NONE + + **Exception raised**: NONE + +Division Operations +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +- **DIV**: Division + + **Format**: div rd, rs1, rs2 + + **Description**: perform signed integer division of 32 bits by 32 bits (rounding towards zero). + + **Pseudocode**: x[rd] = x[rs1] /s x[rs2] + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **DIVU**: Division Unsigned + + **Format**: divu rd, rs1, rs2 + + **Description**: perform unsigned integer division of 32 bits by 32 bits (rounding towards zero). + + **Pseudocode**: x[rd] = x[rs1] /u x[rs2] + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **REM**: Remain + + **Format**: rem rd, rs1, rs2 + + **Description**: provide the remainder of the corresponding division operation DIV (the sign of rd equals the sign of rs1). + + **Pseudocode**: x[rd] = x[rs1] %s x[rs2] + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **REMU**: Remain Unsigned + + **Format**: rem rd, rs1, rs2 + + **Description**: provide the remainder of the corresponding division operation DIVU. + + **Pseudocode**: x[rd] = x[rs1] %u x[rs2] + + **Invalid values**: NONE + + **Exception raised**: NONE + + +RV32A Atomic Instructions +-------------------------------- + +The standard atomic instruction extension is denoted by instruction subset name “A”, and contains instructions that atomically read-modify-write memory to support synchronization between +multiple RISC-V harts running in the same memory space. The two forms of atomic instruction +provided are load-reserved/store-conditional instructions and atomic fetch-and-op memory instructions. Both types of atomic instruction support various memory consistency orderings including +unordered, acquire, release, and sequentially consistent semantics. + +Load-Reserved/Store-Conditional Instructions +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +- **LR.W**: Load-Reserved Word + + **Format**: lr.w rd, (rs1) + + **Description**: LR loads a word from the address in rs1, places the sign-extended value in rd, and registers a reservation on the memory address. + + **Pseudocode**: x[rd] = LoadReserved32(M[x[rs1]]) + + **Invalid values**: NONE + + **Exception raised**: If the address is not naturally aligned (4-byte boundary), a Load/AMO address misaligned exception will be generated. + +- **SC.W**: Store-Conditional Word + + **Format**: sc.w rd, rs2, (rs1) + + **Description**: SC writes a word in rs2 to the address in rs1, provided a valid reservation still exists on that address. SC writes zero to rd on success or a nonzero code on failure. + + **Pseudocode**: x[rd] = StoreConditional32(M[x[rs1]], x[rs2]) + + **Invalid values**: NONE + + **Exception raised**: If the address is not naturally aligned (4-byte boundary), a Store/AMO address misaligned exception will be generated. + +Atomic Memory Operations +^^^^^^^^^^^^^^^^^^^^^^^^^^ + +- **AMOADD.W**: Atomic Memory Operation: Add Word + + **Format**: amoadd.w rd, rs2, (rs1) + + **Description**: AMOADD.W atomically loads a data value from the address in rs1, places the value into register rd, then adds the loaded value and the original value in rs2, then stores the result back to the address in rs1. + + **Pseudocode**: x[rd] = AMO32(M[x[rs1]] + x[rs2]) + + **Invalid values**: NONE + + **Exception raised**: If the address is not naturally aligned (4-byte boundary), a misaligned address exception will be generated. + +- **AMOAND.W**: Atomic Memory Operation: And Word + + **Format**: amoand.w rd, rs2, (rs1) + + **Description**: AMOAND.W atomically loads a data value from the address in rs1, places the value into register rd, then performs an AND between the loaded value and the original value in rs2, then stores the result back to the address in rs1. + + **Pseudocode**: x[rd] = AMO32(M[x[rs1]] & x[rs2]) + + **Invalid values**: NONE + + **Exception raised**: If the address is not naturally aligned (4-byte boundary), a misaligned address exception will be generated. + +- **AMOOR.W**: Atomic Memory Operation: Or Word + + **Format**: amoor.w rd, rs2, (rs1) + + **Description**: AMOOR.W atomically loads a data value from the address in rs1, places the value into register rd, then performs an OR between the loaded value and the original value in rs2, then stores the result back to the address in rs1. + + **Pseudocode**: x[rd] = AMO32(M[x[rs1]] | x[rs2]) + + **Invalid values**: NONE + + **Exception raised**: If the address is not naturally aligned (4-byte boundary), a misaligned address exception will be generated. + +- **AMOXOR.W**: Atomic Memory Operation: Xor Word + + **Format**: amoxor.w rd, rs2, (rs1) + + **Description**: AMOXOR.W atomically loads a data value from the address in rs1, places the value into register rd, then performs a XOR between the loaded value and the original value in rs2, then stores the result back to the address in rs1. + + **Pseudocode**: x[rd] = AMO32(M[x[rs1]] ^ x[rs2]) + + **Invalid values**: NONE + + **Exception raised**: If the address is not naturally aligned (4-byte boundary), a misaligned address exception will be generated. + +- **AMOSWAP.W**: Atomic Memory Operation: Swap Word + + **Format**: amoswap.w rd, rs2, (rs1) + + **Description**: AMOSWAP.W atomically loads a data value from the address in rs1, places the value into register rd, then performs a SWAP between the loaded value and the original value in rs2, then stores the result back to the address in rs1. + + **Pseudocode**: x[rd] = AMO32(M[x[rs1]] SWAP x[rs2]) + + **Invalid values**: NONE + + **Exception raised**: If the address is not naturally aligned (4-byte boundary), a misaligned address exception will be generated. + +- **AMOMIN.W**: Atomic Memory Operation: Minimum Word + + **Format**: amomin.d rd, rs2, (rs1) + + **Description**: AMOMIN.W atomically loads a data value from the address in rs1, places the value into register rd, then choses the minimum between the loaded value and the original value in rs2, then stores the result back to the address in rs1. + + **Pseudocode**: x[rd] = AMO32(M[x[rs1]] MIN x[rs2]) + + **Invalid values**: NONE + + **Exception raised**: If the address is not naturally aligned (4-byte boundary), a misaligned address exception will be generated. + +- **AMOMINU.W**: Atomic Memory Operation: Minimum Word, Unsigned + + **Format**: amominu.d rd, rs2, (rs1) + + **Description**: AMOMINU.W atomically loads a data value from the address in rs1, places the value into register rd, then choses the minimum (the values treated as unsigned) between the loaded value and the original value in rs2, then stores the result back to the address in rs1. + + **Pseudocode**: x[rd] = AMO32(M[x[rs1]] MINU x[rs2]) + + **Invalid values**: NONE + + **Exception raised**: If the address is not naturally aligned (4-byte boundary), a misaligned address exception will be generated. + +- **AMOMAX.W**: Atomic Memory Operation: Maximum Word, Unsigned + + **Format**: amomax.d rd, rs2, (rs1) + + **Description**: AMOMAX.W atomically loads a data value from the address in rs1, places the value into register rd, then choses the maximum between the loaded value and the original value in rs2, then stores the result back to the address in rs1. + + **Pseudocode**: x[rd] = AMO32(M[x[rs1]] MAX x[rs2]) + + **Invalid values**: NONE + + **Exception raised**: If the address is not naturally aligned (4-byte boundary), a misaligned address exception will be generated. + +- **AMOMAXU.W**: Atomic Memory Operation: Maximum Word, Unsigned + + **Format**: amomaxu.d rd, rs2, (rs1) + + **Description**: AMOMAXU.W atomically loads a data value from the address in rs1, places the value into register rd, then choses the maximum (the values treated as unsigned) between the loaded value and the original value in rs2, then stores the result back to the address in rs1. + + **Pseudocode**: x[rd] = AMO32(M[x[rs1]] MAXU x[rs2]) + + **Invalid values**: NONE + + **Exception raised**: If the address is not naturally aligned (4-byte boundary), a misaligned address exception will be generated. + +RV32C Compressed Instructions +-------------------------------- + +RVC uses a simple compression scheme that offers shorter 16-bit versions of common 32-bit RISC-V +instructions when: + + • the immediate or address offset is small; + • one of the registers is the zero register (x0), the ABI link register (x1), or the ABI stack pointer (x2); + • the destination register and the first source register are identical; + • the registers used are the 8 most popular ones. + +The C extension is compatible with all other standard instruction extensions. The C extension +allows 16-bit instructions to be freely intermixed with 32-bit instructions, with the latter now able +to start on any 16-bit boundary. With the addition of the C extension, JAL and JALR instructions +will no longer raise an instruction misaligned exception. + +Integer Computational Instructions +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +- **C.LI**: Compressed Load Immediate + + **Format**: c.li rd, imm[5:0] + + **Description**: loads the sign-extended 6-bit immediate, imm, into register rd. + + **Pseudocode**: x[rd] = sext(imm[5:0]) + + **Invalid values**: rd = x0 + + **Exception raised**: NONE + +- **C.LUI**: Compressed Load Upper Immediate + + **Format**: c.lui rd, nzimm[17:12] + + **Description**: loads the non-zero 6-bit immediate field into bits 17–12 of the destination register, clears the bottom 12 bits, and sign-extends bit 17 into all higher bits of the destination. + + **Pseudocode**: x[rd] = sext(nzimm[17:12] << 12) + + **Invalid values**: rd = x0 & rd = x2 & nzimm = 0 + + **Exception raised**: NONE + +- **C.ADDI**: Compressed Addition Immediate + + **Format**: c.addi rd, nzimm[5:0] + + **Description**: adds the non-zero sign-extended 6-bit immediate to the value in register rd then writes the result to rd. + + **Pseudocode**: x[rd] = x[rd] + sext(nzimm[5:0]) + + **Invalid values**: rd = x0 & nzimm = 0 + + **Exception raised**: NONE + +- **C.ADDI16SP**: Addition Immediate Scaled by 16, to Stack Pointer + + **Format**: c.addi16sp nzimm[9:4] + + **Description**: adds the non-zero sign-extended 6-bit immediate to the value in the stack pointer (sp=x2), where the immediate is scaled to represent multiples of 16 in the range (-512,496). C.ADDI16SP is used to adjust the stack pointer in procedure prologues and epilogues. C.ADDI16SP shares the opcode with C.LUI, but has a destination field of x2. + + **Pseudocode**: x[2] = x[2] + sext(nzimm[9:4]) + + **Invalid values**: rd != x2 & nzimm = 0 + + **Exception raised**: NONE + +- **C.ADDI4SPN**: Addition Immediate Scaled by 4, to Stack Pointer + + **Format**: c.addi4spn rd', nzimm[9:2] + + **Description**: adds a zero-extended non-zero immediate, scaled by 4, to the stack pointer, x2, and writes the result to rd'. This instruction is used to generate pointers to stack-allocated variables. + + **Pseudocode**: x[8 + rd'] = x[2] + zext(nzimm[9:2]) + + **Invalid values**: nzimm = 0 + + **Exception raised**: NONE + +- **C.SLLI**: Compressed Shift Left Logic Immediate + + **Format**: c.slli rd, uimm[5:0] + + **Description**: performs a logical left shift (zeros are shifted into the lower bits). + + **Pseudocode**: x[rd] = x[rd] << uimm[5:0] + + **Invalid values**: rd = x0 & uimm[5] = 0 + + **Exception raised**: NONE + +- **C.SRLI**: Compressed Shift Right Logic Immediate + + **Format**: c.srli rd', uimm[5:0] + + **Description**: performs a logical right shift (zeros are shifted into the upper bits). + + **Pseudocode**: x[8 + rd'] = x[8 + rd'] >> uimm[5:0] + + **Invalid values**: uimm[5] = 0 + + **Exception raised**: NONE + +- **C.SRAI**: Compressed Shift Right Arithmetic Immediate + + **Format**: c.srai rd', uimm[5:0] + + **Description**: performs an arithmetic right shift (sign bits are shifted into the upper bits). + + **Pseudocode**: x[8 + rd'] = x[8 + rd'] >>s uimm[5:0] + + **Invalid values**: uimm[5] = 0 + + **Exception raised**: NONE + +- **C.ANDI**: Compressed AND Immediate + + **Format**: c.andi rd', imm[5:0] + + **Description**: computes the bitwise AND of the value in register rd', and the sign-extended 6-bit immediate, then writes the result to rd'. + + **Pseudocode**: x[8 + rd'] = x[8 + rd'] & sext(imm[5:0]) + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **C.ADD**: Compressed Addition + + **Format**: c.add rd, rs2 + + **Description**: adds the values in registers rd and rs2 and writes the result to register rd. + + **Pseudocode**: x[rd] = x[rd] + x[rs2] + + **Invalid values**: rd = x0 & rs2 = x0 + + **Exception raised**: NONE + +- **C.MV**: Move + + **Format**: c.mv rd, rs2 + + **Description**: copies the value in register rs2 into register rd. + + **Pseudocode**: x[rd] = x[rs2] + + **Invalid values**: rd = x0 & rs2 = x0 + + **Exception raised**: NONE + +- **C.AND**: Compressed AND + + **Format**: c.and rd', rs2' + + **Description**: computes the bitwise AND of of the value in register rd', and register rs2', then writes the result to rd'. + + **Pseudocode**: x[8 + rd'] = x[8 + rd'] & x[8 + rs2'] + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **C.OR**: Compressed OR + + **Format**: c.or rd', rs2' + + **Description**: computes the bitwise OR of of the value in register rd', and register rs2', then writes the result to rd'. + + **Pseudocode**: x[8 + rd'] = x[8 + rd'] | x[8 + rs2'] + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **C.XOR**: Compressed XOR + + **Format**: c.and rd', rs2' + + **Description**: computes the bitwise XOR of of the value in register rd', and register rs2', then writes the result to rd'. + + **Pseudocode**: x[8 + rd'] = x[8 + rd'] ^ x[8 + rs2'] + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **C.SUB**: Compressed Subtraction + + **Format**: c.sub rd', rs2' + + **Description**: subtracts the value in registers rs2' from value in rd' and writes the result to register rd'. + + **Pseudocode**: x[8 + rd'] = x[8 + rd'] - x[8 + rs2'] + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **C.EBREAK**: Compressed Ebreak + + **Format**: c.ebreak + + **Description**: cause control to be transferred back to the debugging environment. + + **Pseudocode**: RaiseException(Breakpoint) + + **Invalid values**: NONE + + **Exception raised**: Raise a Breakpoint exception. + +Control Transfer Instructions +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +- **C.J**: Compressed Jump + + **Format**: c.j imm[11:1] + + **Description**: performs an unconditional control transfer. The offset is sign-extended and added to the pc to form the jump target address. + + **Pseudocode**: pc += sext(imm[11:1]) + + **Invalid values**: NONE + + **Exception raised**: jumps to an unaligned address (4-byte or 2-byte boundary) will usually raise an exception. + +- **C.JAL**: Compressed Jump and Link + + **Format**: c.jal imm[11:1] + + **Description**: performs the same operation as C.J, but additionally writes the address of the instruction following the jump (pc+2) to the link register, x1. + + **Pseudocode**: x[1] = pc+2; pc += sext(imm[11:1]) + + **Invalid values**: NONE + + **Exception raised**: jumps to an unaligned address (4-byte or 2-byte boundary) will usually raise an exception. + +- **C.JR**: Compressed Jump Register + + **Format**: c.jr rs1 + + **Description**: performs an unconditional control transfer to the address in register rs1. + + **Pseudocode**: pc = x[rs1] + + **Invalid values**: rs1 = x0 + + **Exception raised**: jumps to an unaligned address (4-byte or 2-byte boundary) will usually raise an exception. + +- **C.JALR**: Compressed Jump and Link Register + + **Format**: c.jalr rs1 + + **Description**: performs the same operation as C.JR, but additionally writes the address of the instruction following the jump (pc+2) to the link register, x1. + + **Pseudocode**: t = pc+2; pc = x[rs1]; x[1] = t + + **Invalid values**: rs1 = x0 + + **Exception raised**: jumps to an unaligned address (4-byte or 2-byte boundary) will usually raise an exception. + +- **C.BEQZ**: Branch if Equal Zero + + **Format**: c.beqz rs1', imm[8:1] + + **Description**: performs conditional control transfers. The offset is sign-extended and added to the pc to form the branch target address. C.BEQZ takes the branch if the value in register rs1' is zero. + + **Pseudocode**: if (x[8+rs1'] == 0) pc += sext(imm[8:1]) + + **Invalid values**: NONE + + **Exception raised**: no instruction fetch misaligned exception is generated for a conditional branch that is not taken. An Instruction address misaligned exception is raised if the target address is not aligned on 4-byte or 2-byte boundary, because the core supports compressed instructions. + +- **C.BNEZ**: Branch if Not Equal Zero + + **Format**: c.bnez rs1', imm[8:1] + + **Description**: performs conditional control transfers. The offset is sign-extended and added to the pc to form the branch target address. C.BEQZ takes the branch if the value in register rs1' isn't zero. + + **Pseudocode**: if (x[8+rs1'] != 0) pc += sext(imm[8:1]) + + **Invalid values**: NONE + + **Exception raised**: no instruction fetch misaligned exception is generated for a conditional branch that is not taken. An Instruction address misaligned exception is raised if the target address is not aligned on 4-byte or 2-byte boundary, because the core supports compressed instructions. + +Load and Store Instructions +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +- **C.LWSP**: Load Word Stack-Pointer + + **Format**: c.lwsp rd, uimm(x2) + + **Description**: loads a 32-bit value from memory into register rd. It computes an effective address by adding the zero-extended offset, scaled by 4, to the stack pointer, x2. + + **Pseudocode**: x[rd] = M[x[2] + zext(uimm[7:2])][31:0] + + **Invalid values**: rd = x0 + + **Exception raised**: loads with a destination of x0 must still raise any exceptions, also an exception if the memory address isn't aligned (4-byte boundary). + +- **C.SWSP**: Store Word Stack-Pointer + + **Format**: c.swsp rd, uimm(x2) + + **Description**: stores a 32-bit value in register rs2 to memory. It computes an effective address by adding the zero-extended offset, scaled by 4, to the stack pointer, x2. + + **Pseudocode**: M[x[2] + zext(uimm[7:2])][31:0] = x[rs2] + + **Invalid values**: NONE + + **Exception raised**: an exception raised if the memory address isn't aligned (4-byte boundary). + +- **C.LW**: Compressed Load Word + + **Format**: c.lw rd', uimm(rs1') + + **Description**: loads a 32-bit value from memory into register rd'. It computes an effective address by adding the zero-extended offset, scaled by 4, to the base address in register rs1'. + + **Pseudocode**: x[8+rd'] = M[x[8+rs1'] + zext(uimm[6:2])][31:0]) + + **Invalid values**: NONE + + **Exception raised**: an exception raised if the memory address isn't aligned (4-byte boundary). + +- **C.SW**: Compressed Store Word + + **Format**: c.sw rs2', uimm(rs1') + + **Description**: stores a 32-bit value from memory into register rd'. It computes an effective address by adding the zero-extended offset, scaled by 4, to the base address in register rs1'. + + **Pseudocode**: M[x[8+rs1'] + zext(uimm[6:2])][31:0] = x[8+rs2'] + + **Invalid values**: NONE + + **Exception raised**: an exception raised if the memory address isn't aligned (4-byte boundary). + +RV32Zicsr Control and Status Register Instructions +--------------------------------------------------- + +All CSR instructions atomically read-modify-write a single CSR, whose CSR specifier is encoded in the 12-bit csr field of the instruction held in bits 31–20. The immediate forms use a 5-bit zero-extended immediate encoded in the rs1 field. + +- **CSRRW**: Control and Status Register Read and Write + + **Format**: csrrw rd, csr, rs1 + + **Description**: reads the old value of the CSR, zero-extends the value to 32 bits, then writes it to integer register rd, the initial value in rs1 is written to the CSR. If rd=x0, then the instruction shall not read the CSR and shall not cause any of the side-effects that might occur on a CSR read. + + **Pseudocode**: t = CSRs[csr]; CSRs[csr] = x[rs1]; x[rd] = t + + **Invalid values**: NONE + + **Exception raised**: attempts to access a non-existent CSR raise an illegal instruction exception, attempts to access a CSR without appropriate privilege level or to write a read-only register also raise illegal instruction exceptions. + +- **CSRRS**: Control and Status Register Read and Set + + **Format**: csrrs rd, csr, rs1 + + **Description**: reads the value of the CSR, zero-extends the value to 32 bits, and writes it to integer register rd, the initial value in integer register rs1 is treated as a bit mask that specifies bit positions to be set in the CSR. Any bit that is high in rs1 will cause the corresponding bit to be set in the CSR, if that CSR bit is writable. Other bits in the CSR are unaffected (though CSRs might have side effects when written), if rs1=x0, then the instruction will not write to the CSR at all, and so shall not cause any of the side effects that might otherwise occur on a CSR write, such as raising illegal instruction exceptions on accesses to read-only CSRs. + + **Pseudocode**: t = CSRs[csr]; CSRs[csr] = t | x[rs1]; x[rd] = t + + **Invalid values**: NONE + + **Exception raised**: attempts to access a non-existent CSR raise an illegal instruction exception, attempts to access a CSR without appropriate privilege level or to write a read-only register also raise illegal instruction exceptions. + +- **CSRRC**: Control and Status Register Read and Clear + + **Format**: csrrc rd, csr, rs1 + + **Description**: reads the value of the CSR, zero-extends the value to 32 bits, and writes it to integer register rd, the initial value in integer register rs1 is treated as a bit mask that specifies bit positions to be cleared in the CSR. Any bit that is high in rs1 will cause the corresponding bit to be set in the CSR, if that CSR bit is writable. Other bits in the CSR are unaffected (though CSRs might have side effects when written), if rs1=x0, then the instruction will not write to the CSR at all, and so shall not cause any of the side effects that might otherwise occur on a CSR write, such as raising illegal instruction exceptions on accesses to read-only CSRs. + + **Pseudocode**: t = CSRs[csr]; CSRs[csr] = t & ∼x[rs1]; x[rd] = t + + **Invalid values**: NONE + + **Exception raised**: attempts to access a non-existent CSR raise an illegal instruction exception, attempts to access a CSR without appropriate privilege level or to write a read-only register also raise illegal instruction exceptions. + +- **CSRRWI**: Control and Status Register Read and Write Immediate + + **Format**: csrrwi rd, csr, uimm[4:0] + + **Description**: reads the old value of the CSR, zero-extends the value to 32 bits, then writes it to integer register rd. The zero-extends immediate is written to the CSR. If rd=x0, then the instruction shall not read the CSR and shall not cause any of the side-effects that might occur on a CSR read. + + **Pseudocode**: x[rd] = CSRs[csr]; CSRs[csr] = zext(uimm[4:0]) + + **Invalid values**: NONE + + **Exception raised**: attempts to access a non-existent CSR raise an illegal instruction exception, attempts to access a CSR without appropriate privilege level or to write a read-only register also raise illegal instruction exceptions. + +- **CSRRSI**: Control and Status Register Read and Set Immediate + + **Format**: csrrsi rd, csr, uimm[4:0] + + **Description**: reads the value of the CSR, zero-extends the value to 32 bits, and writes it to integer register rd. The zero-extends immediate value is treated as a bit mask that specifies bit positions to be set in the CSR. Any bit that is high in zero-extends immediate will cause the corresponding bit to be set in the CSR, if that CSR bit is writable. Other bits in the CSR are unaffected (though CSRs might have side effects when written), if the uimm[4:0] field is zero, then these instructions will not write to the CSR, and shall not cause any of the side effects that might otherwise occur on a CSR write. + + **Pseudocode**: t = CSRs[csr]; CSRs[csr] = t | zext(uimm[4:0]); x[rd] = t + + **Invalid values**: NONE + + **Exception raised**: attempts to access a non-existent CSR raise an illegal instruction exception, attempts to access a CSR without appropriate privilege level or to write a read-only register also raise illegal instruction exceptions. + +- **CSRRCI**: Control and Status Register Read and Clear Immediate + + **Format**: csrrci rd, csr, uimm[4:0] + + **Description**: reads the value of the CSR, zero-extends the value to 32 bits, and writes it to integer register rd. The zero-extends immediate value is treated as a bit mask that specifies bit positions to be cleared in the CSR. Any bit that is high in zero-extends immediate will cause the corresponding bit to be set in the CSR, if that CSR bit is writable. Other bits in the CSR are unaffected (though CSRs might have side effects when written), if the uimm[4:0] field is zero, then these instructions will not write to the CSR, and shall not cause any of the side effects that might otherwise occur on a CSR write. + + **Pseudocode**: t = CSRs[csr]; CSRs[csr] = t & ∼zext(uimm[4:0]); x[rd] = t + + **Invalid values**: NONE + + **Exception raised**: attempts to access a non-existent CSR raise an illegal instruction exception, attempts to access a CSR without appropriate privilege level or to write a read-only register also raise illegal instruction exceptions. + +RV32Zifencei Instruction-Fetch Fence +-------------------------------------- + +- **FENCE.I**: Fence Instruction + + **Format**: fence.i + + **Description**: The FENCE.I instruction is used to synchronize the instruction and data streams. RISC-V does not guarantee that stores to instruction memory will be made visible to instruction fetches on the same RISC-V hart until a FENCE.I instruction is executed. A FENCE.I instruction only ensures that a subsequent instruction fetch on a RISC-V hart will see any previous data stores already visible to the same RISC-V hart. + + **Pseudocode**: Fence(Store, Fetch) + + **Invalid values**: NONE + + **Exception raised**: NONE + +Illegal Instruction +--------------------------- + +This section describe all kind of Illegal Instruction, in this case the Core generate an illegal instruction exception. + +- **ILLEGAL OPCODE**: any instruction (compressed or not compressed) with a non supported opcode is an illegal instruction + +- **ILLEGAL FUNCT2**: any instruction (R4type) with a non supported FUNCT2 is an illegal instruction + +- **ILLEGAL FUNCT3**: any instruction (Rtype, R4type, Itype, Stype or Atype) with a non supported FUNCT3 is an illegal instruction + +- **ILLEGAL FUNCT5**: any instruction (Atype) with a non supported FUNCT5 is an illegal instruction + +- **ILLEGAL FUNCT7**: any instruction (Rtype) with a non supported FUNCT7 is an illegal instruction + +- **ILLEGAL CSR**: any CSR instruction attempts to access a non-existent is an illegal instruction + +- **ILLEGAL PRIVILEGE LEVEL**: any CSR instruction attempts to access a CSR without appropriate privilege level is an illegal instruction + +- **ILLEGAL ACCESS TYPE CSR**: any CSR instruction attempts to write a read-only CSR a non-existent is an illegal instruction diff --git a/verif/docs/VerifPlans/ISA_RV32/VP_IP000.yml b/verif/docs/VerifPlans/ISA_RV32/VP_IP000.yml new file mode 100644 index 0000000000..ce490437ac --- /dev/null +++ b/verif/docs/VerifPlans/ISA_RV32/VP_IP000.yml @@ -0,0 +1,697 @@ +!Feature +next_elt_id: 11 +name: RV32I Register-Immediate Instructions +id: 0 +display_order: 0 +subfeatures: !!omap +- 000_ADDI: !Subfeature + name: 000_ADDI + tag: VP_IP011_P000 + next_elt_id: 3 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F000_S000_I000 + description: "addi rd, rs1, imm[11:0]\nrd = rs1 + Sext(imm[11:0])\nArithmetic\ + \ overflow is lost and ignored" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_addi_cg.cp_rs1\nisacov.rv32i_addi_cg.cp_rd\nisacov.rv32i_addi_cg.cp_rd_rs1_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F000_S000_I001 + description: "addi rd, rs1, imm[11:0]\nrd = rs1 + Sext(imm[11:0])\nArithmetic\ + \ overflow is lost and ignored" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nimmi value\ + \ is +ve, -ve and zero\nAll combinations of rs1 and immi +ve, -ve, and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of immi are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_addi_cg.cp_rs1_value\nisacov.rv32i_addi_cg.cp_immi_value\n\ + isacov.rv32i_addi_cg.cross_rs1_immi_value\nisacov.rv32i_addi_cg.cp_rs1_toggle\n\ + isacov.rv32i_addi_cg.cp_immi_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F000_S000_I002 + description: "addi rd, rs1, imm[11:0]\nrd = rs1 + Sext(imm[11:0])\nArithmetic\ + \ overflow is lost and ignored" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_addi_cg.cp_rd_value\nisacov.rv32i_addi_cg.cp_rd_toggle" + comments: '' +- 001_XORI: !Subfeature + name: 001_XORI + tag: VP_IP011_P001 + next_elt_id: 5 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F000_S001_I000 + description: "xori rd, rs1, imm[11:0]\nrd = rs1 ^ Sext(imm[11:0])\nNote: this\ + \ is a bitwise, not logical operation" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_xori_cg.cp_rs1\nisacov.rv32i_xori_cg.cp_rd\nisacov.rv32i_xori_cg.cp_rd_rs1_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F000_S001_I001 + description: "xori rd, rs1, imm[11:0]\nrd = rs1 ^ Sext(imm[11:0])\nNote: this\ + \ is a bitwise, not logical operation" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nimmi value\ + \ is +ve, -ve and zero\nAll combinations of rs1 and immi +ve, -ve, and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of immi are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_xori_cg.cp_rs1_value\nisacov.rv32i_xori_cg.cp_immi_value\n\ + isacov.rv32i_xori_cg.cross_rs1_immi_value\nisacov.rv32i_xori_cg.cp_rs1_toggle\n\ + isacov.rv32i_xori_cg.cp_immi_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F000_S001_I002 + description: "xori rd, rs1, imm[11:0]\nrd = rs1 ^ Sext(imm[11:0])\nNote: this\ + \ is a bitwise, not logical operation" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_xori_cg.cp_rd_value\nisacov.rv32i_xori_cg.cp_rd_toggle" + comments: '' +- 002_ORI: !Subfeature + name: 002_ORI + tag: VP_IP011_P002 + next_elt_id: 4 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F000_S002_I000 + description: "ori rd, rs1, imm[11:0]\nrd = rs1 | Sext(imm[11:0])\nNote: this\ + \ is a bitwise, not logical operation" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_ori_cg.cp_rs1\nisacov.rv32i_ori_cg.cp_rd\nisacov.rv32i_ori_cg.cp_rd_rs1_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F000_S002_I001 + description: "ori rd, rs1, imm[11:0]\nrd = rs1 | Sext(imm[11:0])\nNote: this\ + \ is a bitwise, not logical operation" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nimmi value\ + \ is +ve, -ve and zero\nAll combinations of rs1 and immi +ve, -ve, and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of immi are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_ori_cg.cp_rs1_value\nisacov.rv32i_ori_cg.cp_immi_value\n\ + isacov.rv32i_ori_cg.cross_rs1_immi_value\nisacov.rv32i_ori_cg.cp_rs1_toggle\n\ + isacov.rv32i_ori_cg.cp_immi_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F000_S002_I002 + description: "ori rd, rs1, imm[11:0]\nrd = rs1 | Sext(imm[11:0])\nNote: this\ + \ is a bitwise, not logical operation" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_ori_cg.cp_rd_value\nisacov.rv32i_ori_cg.cp_rd_toggle" + comments: '' +- 003_ANDI: !Subfeature + name: 003_ANDI + tag: VP_IP011_P003 + next_elt_id: 3 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F000_S003_I000 + description: "andi rd, rs1, imm[11:0]\nrd = rs1 & Sext(imm[11:0])\nNote:\ + \ this is a bitwise, not logical operation" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_andi_cg.cp_rs1\nisacov.rv32i_andi_cg.cp_rd\nisacov.rv32i_andi_cg.cp_rd_rs1_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F000_S003_I001 + description: "andi rd, rs1, imm[11:0]\nrd = rs1 & Sext(imm[11:0])\nNote:\ + \ this is a bitwise, not logical operation" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nimmi value\ + \ is +ve, -ve and zero\nAll combinations of rs1 and immi +ve, -ve, and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of immi are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_andi_cg.cp_rs1_value\nisacov.rv32i_andi_cg.cp_immi_value\n\ + isacov.rv32i_andi_cg.cross_rs1_immi_value\nisacov.rv32i_andi_cg.cp_rs1_toggle\n\ + isacov.rv32i_andi_cg.cp_immi_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F000_S003_I002 + description: "andi rd, rs1, imm[11:0]\nrd = rs1 & Sext(imm[11:0])\nNote:\ + \ this is a bitwise, not logical operation" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_andi_cg.cp_rd_value\nisacov.rv32i_andi_cg.cp_rd_toggle" + comments: '' +- 004_SLTI: !Subfeature + name: 004_SLTI + tag: VP_IP011_P004 + next_elt_id: 3 + display_order: 4 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F000_S004_I000 + description: "slti rd, rs1, imm[11:0]\nrd = (rs1 < Sext(imm[11:0]) ? 1 : 0\n\ + Both imm and rs1 treated as signed numbers" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_slti_cg.cp_rs1\nisacov.rv32i_slti_cg.cp_rd\nisacov.rv32i_slti_cg.cp_rd_rs1_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F000_S004_I001 + description: "slti rd, rs1, imm[11:0]\nrd = (rs1 < Sext(imm[11:0]) ? 1 : 0\n\ + Both imm and rs1 treated as signed numbers" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nimmi value\ + \ is +ve, -ve and zero\nAll combinations of rs1 and immi +ve, -ve, and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of immi are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_slti_cg.cp_rs1_value\nisacov.rv32i_slti_cg.cp_immi_value\n\ + isacov.rv32i_slti_cg.cross_rs1_immi_value\nisacov.rv32i_slti_cg.cp_rs1_toggle\n\ + isacov.rv32i_slti_cg.cp_immi_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F000_S004_I002 + description: "slti rd, rs1, imm[11:0]\nrd = (rs1 < Sext(imm[11:0]) ? 1 : 0\n\ + Both imm and rs1 treated as signed numbers" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is in [0,1]" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_slti_cg.cp_rd_value + comments: '' +- 005_SLTIU: !Subfeature + name: 005_SLTIU + tag: VP_IP011_P005 + next_elt_id: 3 + display_order: 5 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F000_S005_I000 + description: "sltiu rd, rs1, imm[11:0]\nrd = (rs1 < Sext(imm[11:0]) ? 1 :\ + \ 0\nBoth imm and rs1 treated as unsigned numbers" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sltiu_cg.cp_rs1\nisacov.rv32i_sltiu_cg.cp_rd\n\ + isacov.rv32i_sltiu_cg.cp_rd_rs1_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F000_S005_I001 + description: "sltiu rd, rs1, imm[11:0]\nrd = (rs1 < Sext(imm[11:0]) ? 1 :\ + \ 0\nBoth imm and rs1 treated as unsigned numbers" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nimmi value\ + \ is +ve, -ve and zero\nAll combinations of rs1 and immi +ve, -ve, and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of immi are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sltiu_cg.cp_rs1_value\nisacov.rv32i_sltiu_cg.cp_immi_value\n\ + isacov.rv32i_sltiu_cg.cross_rs1_immi_value\nisacov.rv32i_sltiu_cg.cp_rs1_toggle\n\ + isacov.rv32i_sltiu_cg.cp_immi_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F000_S005_I002 + description: "sltiu rd, rs1, imm[11:0]\nrd = (rs1 < Sext(imm[11:0]) ? 1 :\ + \ 0\nBoth imm and rs1 treated as unsigned numbers" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is in [0,1]" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_sltiu_cg.cp_rd_value + comments: '' +- 006_SLLI: !Subfeature + name: 006_SLLI + tag: VP_IP011_P006 + next_elt_id: 3 + display_order: 6 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F000_S006_I000 + description: "slli rd, rs, imm[4:0]\nrd = rs << imm[4:0]\nZeros are shirfted\ + \ into lower bits" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_slli_cg.cp_rs1\nisacov.rv32i_slli_cg.cp_rd\nisacov.rv32i_slli_cg.cp_rd_rs1_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F000_S006_I001 + description: "slli rd, rs, imm[4:0]\nrd = rs << imm[4:0]\nZeros are shirfted\ + \ into lower bits" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nimmediate\ + \ shamt value is [0,31]\nAll combinations of rs1 and immi +ve, -ve, and\ + \ zero values are used\nAll bits of rs1 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_slli_cg.cp_rs1_value\nisacov.rv32i_slli_cg.cp_immi_value\n\ + isacov.rv32i_slli_cg.cross_rs1_immi_value\nisacov.rv32i_slli_cg.cp_rs1_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F000_S006_I002 + description: "slli rd, rs, imm[4:0]\nrd = rs << imm[4:0]\nZeros are shirfted\ + \ into lower bits" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_slli_cg.cp_rd_value\nisacov.rv32i_slli_cg.cp_rd_toggle" + comments: '' +- 007_SRLI: !Subfeature + name: 007_SRLI + tag: VP_IP011_P007 + next_elt_id: 4 + display_order: 7 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F000_S007_I000 + description: "srli rd, rs, imm[4:0]\nrd = rs >> imm[4:0]\nZeros are shirfted\ + \ into upper bits" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_srli_cg.cp_rs1\nisacov.rv32i_srli_cg.cp_rd\nisacov.rv32i_srli_cg.cp_rd_rs1_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F000_S007_I001 + description: "srli rd, rs, imm[4:0]\nrd = rs >> imm[4:0]\nZeros are shirfted\ + \ into upper bits" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nimmediate\ + \ shamt value is [0,31]\nAll combinations of rs1 and immi +ve, -ve, and\ + \ zero values are used\nAll bits of rs1 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_srli_cg.cp_rs1_value\nisacov.rv32i_srli_cg.cp_immi_value\n\ + isacov.rv32i_srli_cg.cross_rs1_immi_value\nisacov.rv32i_srli_cg.cp_rs1_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F000_S007_I002 + description: "srli rd, rs, imm[4:0]\nrd = rs >> imm[4:0]\nZeros are shirfted\ + \ into upper bits" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_srli_cg.cp_rd_value\nisacov.rv32i_srli_cg.cp_rd_toggle" + comments: '' +- 008_SRAI: !Subfeature + name: 008_SRAI + tag: VP_IP011_P008 + next_elt_id: 3 + display_order: 8 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F000_S008_I000 + description: "srli rd, rs, imm[4:0]\nrd = rs >> imm[4:0]\nThe original sign\ + \ bit is copied into the vacated upper bits" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_srai_cg.cp_rs1\nisacov.rv32i_srai_cg.cp_rd\nisacov.rv32i_srai_cg.cp_rd_rs1_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F000_S008_I001 + description: "srli rd, rs, imm[4:0]\nrd = rs >> imm[4:0]\nThe original sign\ + \ bit is copied into the vacated upper bits" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nimmediate\ + \ shamt value is [0,31]\nAll combinations of rs1 and immi +ve, -ve, and\ + \ zero values are used\nAll bits of rs1 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_srai_cg.cp_rs1_value\nisacov.rv32i_srai_cg.cp_immi_value\n\ + isacov.rv32i_srai_cg.cross_rs1_immi_value\nisacov.rv32i_srai_cg.cp_rs1_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F000_S008_I002 + description: "srli rd, rs, imm[4:0]\nrd = rs >> imm[4:0]\nZeros are shirfted\ + \ into upper bits" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_srai_cg.cp_rd_value\nisacov.rv32i_srai_cg.cp_rd_toggle" + comments: '' +- 009_LUI: !Subfeature + name: 009_LUI + tag: VP_IP011_P009 + next_elt_id: 3 + display_order: 9 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F000_S009_I000 + description: "lui rd, imm[19:0]\nrd = imm[19:0] << 12\nrd[11:0] is zero-filled." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rd registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_lui_cg.cp_rd + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F000_S009_I001 + description: "lui rd, imm[19:0]\nrd = imm[19:0] << 12\nrd[11:0] is zero-filled." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nimmediate\ + \ value is zero and non-zero\nAll bits of immu are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lui_cg.cp_immu_value\nisacov.rv32i_lui_cg.cp_immu_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F000_S009_I002 + description: "lui rd, imm[19:0]\nrd = imm[19:0] << 12\nrd[11:0] is zero-filled." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is zero and non-zero\nAll bits of\ + \ rd[31:12] are toggled (11:0 are deposited with 0)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lui_cg.cp_rd_value\nisacov.rv32i_lui_cg.cp_rd_toggle" + comments: '' +- 010_AUIPC: !Subfeature + name: 010_AUIPC + tag: VP_IP011_P010 + next_elt_id: 3 + display_order: 10 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F000_S010_I000 + description: "auipc rd, imm[19:0]\nrd = pc + (imm[19:0] << 12)\npc is address\ + \ of auipc instruction\n\nAssumption: arithmetic overflow is lost and ignored." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rd registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_auipc_cg.cp_rd + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F000_S010_I001 + description: "auipc rd, imm[19:0]\nrd = pc + (imm[19:0] << 12)\npc is address\ + \ of auipc instruction\n\nAssumption: arithmetic overflow is lost and ignored." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nimmediate\ + \ value is zero and non-zero\nAll bits of immu are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_auipc_cg.cp_immu_value\nisacov.rv32i_auipc_cg.cp_immu_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F000_S010_I002 + description: "auipc rd, imm[19:0]\nrd = pc + (imm[19:0] << 12)\npc is address\ + \ of auipc instruction\n\nAssumption: arithmetic overflow is lost and ignored." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is zero and non-zero\nAll bits of\ + \ rd[31:12] are toggled (11:0 are deposited with 0)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_auipc_cg.cp_rd_value\nisacov.rv32i_auipc_cg.cp_rd_toggle" + comments: '' +vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/verif/docs/VerifPlans/ISA_RV32/VP_IP001.yml b/verif/docs/VerifPlans/ISA_RV32/VP_IP001.yml new file mode 100644 index 0000000000..67a3f707d0 --- /dev/null +++ b/verif/docs/VerifPlans/ISA_RV32/VP_IP001.yml @@ -0,0 +1,665 @@ +!Feature +next_elt_id: 10 +name: RV32I Register-Register Instructions +id: 1 +display_order: 1 +subfeatures: !!omap +- 000_ADD: !Subfeature + name: 000_ADD + tag: VP_IP001_P000 + next_elt_id: 4 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F001_S000_I000 + description: "add rd, rs1, rs2\nrd = rs1 + rs2\nArithmetic overflow is lost\ + \ and ignored" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_add_cg.cp_rs1\nisacov.rv32i_add_cg.cp_rs2\nisacov.rv32i_add_cg.cp_rd\n\ + isacov.rv32i_add_cg.cp_rd_rs1_hazard\nisacov.rv32i_add_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F001_S000_I001 + description: "add rd, rs1, rs2\nrd = rs1 + rs2\nArithmetic overflow is lost\ + \ and ignored" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nrs2 value\ + \ is +ve, -ve and zero\nAll combinations of rs1 and rs2 +ve, -ve, and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_add_cg.cp_rs1_value\nisacov.rv32i_add_cg.cp_rs2_value\n\ + isacov.rv32i_add_cg.cross_rs1_rs2_value\nisacov.rv32i_add_cg.cp_rs1_toggle\n\ + isacov.rv32i_add_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F001_S000_I002 + description: "add rd, rs1, rs2\nrd = rs1 + rs2\nArithmetic overflow is lost\ + \ and ignored" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_add_cg.cp_rd_value\nisacov.rv32i_add_cg.cp_rd_toggle" + comments: '' +- 001_SUB: !Subfeature + name: 001_SUB + tag: VP_IP001_P001 + next_elt_id: 3 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F001_S001_I000 + description: "sub rd, rs1, rs2\nrd = rs1 - rs2\nArithmetic underflow is ignored" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sub_cg.cp_rs1\nisacov.rv32i_sub_cg.cp_rs2\nisacov.rv32i_sub_cg.cp_rd\n\ + isacov.rv32i_sub_cg.cp_rd_rs1_hazard\nisacov.rv32i_sub_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F001_S001_I001 + description: "sub rd, rs1, rs2\nrd = rs1 - rs2\nArithmetic underflow is ignored" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nrs2 value\ + \ is +ve, -ve and zero\nAll combinations of rs1 and rs2 +ve, -ve, and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sub_cg.cp_rs1_value\nisacov.rv32i_sub_cg.cp_rs2_value\n\ + isacov.rv32i_sub_cg.cross_rs1_rs2_value\nisacov.rv32i_sub_cg.cp_rs1_toggle\n\ + isacov.rv32i_sub_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F001_S001_I002 + description: "sub rd, rs1, rs2\nrd = rs1 - rs2\nArithmetic underflow is ignored" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sub_cg.cp_rd_value\nisacov.rv32i_sub_cg.cp_rd_toggle" + comments: '' +- 002_AND: !Subfeature + name: 002_AND + tag: VP_IP001_P002 + next_elt_id: 3 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F001_S002_I000 + description: "and rd, rs1, rs2\nrd = rs1 & rs2\nNote: this is a bitwise, not\ + \ logical operation" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_and_cg.cp_rs1\nisacov.rv32i_and_cg.cp_rs2\nisacov.rv32i_and_cg.cp_rd\n\ + isacov.rv32i_and_cg.cp_rd_rs1_hazard\nisacov.rv32i_and_cg.cp_rd_rs2_hazard\n\ + isacov.rv32i_and_cg.cp_rs1\nisacov.rv32i_and_cg.cp_rs2\nisacov.rv32i_and_cg.cp_rd\n\ + isacov.rv32i_and_cg.cp_rd_rs1_hazard\nisacov.rv32i_and_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F001_S002_I001 + description: "and rd, rs1, rs2\nrd = rs1 & rs2\nNote: this is a bitwise, not\ + \ logical operation" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nrs2 value\ + \ is +ve, -ve and zero\nAll combinations of rs1 and rs2 +ve, -ve, and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_and_cg.cp_rs1_value\nisacov.rv32i_and_cg.cp_rs2_value\n\ + isacov.rv32i_and_cg.cross_rs1_rs2_value\nisacov.rv32i_and_cg.cp_rs1_toggle\n\ + isacov.rv32i_and_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F001_S002_I002 + description: "and rd, rs1, rs2\nrd = rs1 & rs2\nNote: this is a bitwise, not\ + \ logical operation" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_and_cg.cp_rd_value\nisacov.rv32i_and_cg.cp_rd_toggle" + comments: '' +- 003_OR: !Subfeature + name: 003_OR + tag: VP_IP001_P003 + next_elt_id: 3 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F001_S003_I000 + description: "or rd, rs1, rs2\nrd = rs1 | rs2\nNote: this is a bitwise, not\ + \ logical operation" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_or_cg.cp_rs1\nisacov.rv32i_or_cg.cp_rs2\nisacov.rv32i_or_cg.cp_rd\n\ + isacov.rv32i_or_cg.cp_rd_rs1_hazard\nisacov.rv32i_or_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F001_S003_I001 + description: "or rd, rs1, rs2\nrd = rs1 | rs2\nNote: this is a bitwise, not\ + \ logical operation" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nrs2 value\ + \ is +ve, -ve and zero\nAll combinations of rs1 and rs2 +ve, -ve, and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_or_cg.cp_rs1_value\nisacov.rv32i_or_cg.cp_rs2_value\n\ + isacov.rv32i_or_cg.cross_rs1_rs2_value\nisacov.rv32i_or_cg.cp_rs1_toggle\n\ + isacov.rv32i_or_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F001_S003_I002 + description: "or rd, rs1, rs2\nrd = rs1 | rs2\nNote: this is a bitwise, not\ + \ logical operation" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_or_cg.cp_rd_value\nisacov.rv32i_or_cg.cp_rd_toggle" + comments: '' +- 004_XOR: !Subfeature + name: 004_XOR + tag: VP_IP001_P004 + next_elt_id: 3 + display_order: 4 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F001_S004_I000 + description: "xor rd, rs1, rs2\nrd = rs1 ^ rs2\nNote: this is a bitwise, not\ + \ logical operation" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_xor_cg.cp_rs1\nisacov.rv32i_xor_cg.cp_rs2\nisacov.rv32i_xor_cg.cp_rd\n\ + isacov.rv32i_xor_cg.rd_rs1_hazard\nisacov.rv32i_xor_cg.rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F001_S004_I001 + description: "xor rd, rs1, rs2\nrd = rs1 ^ rs2\nNote: this is a bitwise, not\ + \ logical operation" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nrs2 value\ + \ is +ve, -ve and zero\nAll combinations of rs1 and rs2 +ve, -ve, and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_xor_cg.cp_rs1_value\nisacov.rv32i_xor_cg.cp_rs2_value\n\ + isacov.rv32i_xor_cg.cross_rs1_rs2_value\nisacov.rv32i_xor_cg.cp_rs1_toggle\n\ + isacov.rv32i_xor_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F001_S004_I002 + description: "xor rd, rs1, rs2\nrd = rs1 ^ rs2\nNote: this is a bitwise, not\ + \ logical operation" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 56 + coverage_loc: "isacov.rv32i_xor_cg.cp_rd_value\nisacov.rv32i_xor_cg.cp_rd_toggle" + comments: '' +- 005_SLT: !Subfeature + name: 005_SLT + tag: VP_IP001_P005 + next_elt_id: 3 + display_order: 5 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F001_S005_I000 + description: "slt rd, rs1, rs2\nrd = (rs1 < rs2) ? 1 : 0\nBoth rs1 ad rs2\ + \ treated as signed numbers" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_slt_cg.cp_rs1\nisacov.rv32i_slt_cg.cp_rs2\nisacov.rv32i_slt_cg.cp_rd\n\ + isacov.rv32i_slt_cg.cp_rd_rs1_hazard\nisacov.rv32i_slt_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F001_S005_I001 + description: "slt rd, rs1, rs2\nrd = (rs1 < rs2) ? 1 : 0\nBoth rs1 ad rs2\ + \ treated as signed numbers" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nrs2 value\ + \ is +ve, -ve and zero\nAll combinations of rs1 and rs2 +ve, -ve, and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_slt_cg.cp_rs1_value\nisacov.rv32i_slt_cg.cp_rs2_value\n\ + isacov.rv32i_slt_cg.cross_rs1_rs2_value\nisacov.rv32i_slt_cg.cp_rs1_toggle\n\ + isacov.rv32i_slt_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F001_S005_I002 + description: "slt rd, rs1, rs2\nrd = (rs1 < rs2) ? 1 : 0\nBoth rs1 ad rs2\ + \ treated as signed numbers" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is [0,1]" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_slt_cg.cp_rd_value + comments: '' +- 006_SLTU: !Subfeature + name: 006_SLTU + tag: VP_IP001_P006 + next_elt_id: 3 + display_order: 6 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F001_S006_I000 + description: "sltu rd, rs1, imm[11:0]\nrd = (rs1 < rs2) ? 1 : 0\nBoth rs1\ + \ and rs2 treated as unsigned numbers" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sltu_cg.cp_rs1\nisacov.rv32i_sltu_cg.cp_rs2\n\ + isacov.rv32i_sltu_cg.cp_rd\nisacov.rv32i_sltu_cg.cp_rd_rs1_hazard\nisacov.rv32i_sltu_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F001_S006_I001 + description: "sltu rd, rs1, imm[11:0]\nrd = (rs1 < rs2) ? 1 : 0\nBoth rs1\ + \ and rs2 treated as unsigned numbers" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nrs1 value is non-zero and zero\nrs2 value\ + \ is non-zero and zero\nAll combinations of rs1 and rs2 non-zero and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sltu_cg.cp_rs1_value\nisacov.rv32i_sltu_cg.cp_rs2_value\n\ + isacov.rv32i_sltu_cg.cross_rs1_rs2_value\nisacov.rv32i_sltu_cg.cp_rs1_toggle\n\ + isacov.rv32i_sltu_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F001_S006_I002 + description: "sltu rd, rs1, imm[11:0]\nrd = (rs1 < rs2) ? 1 : 0\nBoth rs1\ + \ and rs2 treated as unsigned numbers" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is [0,1]" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_sltu_cg.cp_rd_value + comments: '' +- 007_SLL: !Subfeature + name: 007_SLL + tag: VP_IP001_P007 + next_elt_id: 3 + display_order: 7 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F001_S007_I000 + description: "sll rd, rs1, rs2\nrd = rs1 << rs2[4:0]\nZeros are shirfted into\ + \ lower bits" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sll_cg.cp_rs1\nisacov.rv32i_sll_cg.cp_rs2\nisacov.rv32i_sll_cg.cp_rd\n\ + isacov.rv32i_sll_cg.cp_rd_rs1_hazard\nisacov.rv32i_sll_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F001_S007_I001 + description: "sll rd, rs1, rs2\nrd = rs1 << rs2[4:0]\nZeros are shirfted into\ + \ lower bits" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nrs1 value is non-zero and zero\nrs2 value\ + \ is tested from [0,31]\nAll combinations of rs1 and rs2 non-zero and zero\ + \ values with all shift values are used\nAll bits of rs1 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sll_cg.cp_rs1_value\nisacov.rv32i_sll_cg.cp_rs2_value\n\ + isacov.rv32i_sll_cg.cross_rs1_rs2_value\nisacov.rv32i_sll_cg.cp_rs1_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F001_S007_I002 + description: "sll rd, rs1, rs2\nrd = rs1 << rs2[4:0]\nZeros are shirfted into\ + \ lower bits" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is non-zero and zero.\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sll_cg.cp_rd_value\nisacov.rv32i_sll_cg.cp_rd_toggle\n\ + isacov.rv32i_sll_cg.cp_rd_value\nisacov.rv32i_sll_cg.cp_rd_toggle" + comments: '' +- 008_SRL: !Subfeature + name: 008_SRL + tag: VP_IP001_P008 + next_elt_id: 3 + display_order: 8 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F001_S008_I000 + description: "srl rd, rs1, rs2\nrd = rs1 >> rs2[4:0]\nZeros are shirfted into\ + \ upper bits" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_srl_cg.cp_rs1\nisacov.rv32i_srl_cg.cp_rs2\nisacov.rv32i_srl_cg.cp_rd\n\ + isacov.rv32i_srl_cg.cp_rd_rs1_hazard\nisacov.rv32i_srl_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F001_S008_I001 + description: "srl rd, rs1, rs2\nrd = rs1 >> rs2[4:0]\nZeros are shirfted into\ + \ upper bits" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nrs1 value is non-zero and zero\nrs2 value\ + \ is tested from [0,31]\nAll combinations of rs1 and rs2 non-zero and zero\ + \ values with all shift values are used\nAll bits of rs1 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_srl_cg.cp_rs1_value\nisacov.rv32i_srl_cg.cp_rs2_value\n\ + isacov.rv32i_srl_cg.cross_rs1_rs2_value\nisacov.rv32i_srl_cg.cp_rs1_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F001_S008_I002 + description: "srl rd, rs1, rs2\nrd = rs1 >> rs2[4:0]\nZeros are shirfted into\ + \ upper bits" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is non-zero and zero.\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_srl_cg.cp_rd_value\nisacov.rv32i_srl_cg.cp_rd_toggle" + comments: '' +- 009_SRA: !Subfeature + name: 009_SRA + tag: VP_IP001_P009 + next_elt_id: 3 + display_order: 9 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F001_S009_I000 + description: "sra rd, rs1, rs2\nrd = rs1 >> rs2[4:0]\nThe original sign bit\ + \ is copied into the vacated upper bits" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sra_cg.cp_rs1\nisacov.rv32i_sra_cg.cp_rs2\nisacov.rv32i_sra_cg.cp_rd\n\ + isacov.rv32i_sra_cg.cp_rd_rs1_hazard\nisacov.rv32i_sra_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F001_S009_I001 + description: "sra rd, rs1, rs2\nrd = rs1 >> rs2[4:0]\nThe original sign bit\ + \ is copied into the vacated upper bits" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve, and zero\nrs2 value\ + \ is tested from [0,31]\nAll combinations of rs1 and rs2 +ve, -ve and zero\ + \ values with all shift values are used\nAll bits of rs1 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sra_cg.cp_rs1_value\nisacov.rv32i_sra_cg.cp_rs2_value\n\ + isacov.rv32i_sra_cg.cross_rs1_rs2_value\nisacov.rv32i_sra_cg.cp_rs1_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F001_S009_I002 + description: "sra rd, rs1, rs2\nrd = rs1 >> rs2[4:0]\nZeros are shirfted into\ + \ upper bits" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is +ve, -ve, and zero.\nAll bits\ + \ of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sra_cg.cp_rd_value\nisacov.rv32i_sra_cg.cp_rd_toggle" + comments: '' +vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/verif/docs/VerifPlans/ISA_RV32/VP_IP002.yml b/verif/docs/VerifPlans/ISA_RV32/VP_IP002.yml new file mode 100644 index 0000000000..f086395289 --- /dev/null +++ b/verif/docs/VerifPlans/ISA_RV32/VP_IP002.yml @@ -0,0 +1,498 @@ +!Feature +next_elt_id: 8 +name: RV32I Control Transfer Instructions +id: 2 +display_order: 2 +subfeatures: !!omap +- 000_JAL: !Subfeature + name: 000_JAL + tag: VP_IP002_P000 + next_elt_id: 3 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F002_S000_I000 + description: "jal rd, imm[20:1]\nrd = pc+4; pc += Sext({imm[20:1], 1’b0})\n\ + pc is calculated using signed arithmetic\n\njal x0, imm[20:1] (special case:\ + \ unconditional jump)\npc += Sext({imm[20:1], 1’b0})" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rd registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_jal_cg.cp_rd + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F002_S000_I001 + description: "jal rd, imm[20:1]\nrd = pc+4; pc += Sext({imm[20:1], 1’b0})\n\ + pc is calculated using signed arithmetic\n\njal x0, imm[20:1] (special case:\ + \ unconditional jump)\npc += Sext({imm[20:1], 1’b0})" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nimmj value is +ve, -ve, and zero\nAll bits\ + \ of immj are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_jal_cg.cp_immj_value\nisacov.rv32i_jal_cg.cp_immj_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F002_S000_I002 + description: "jal rd, imm[20:1]\nrd = pc+4; pc += Sext({imm[20:1], 1’b0})\n\ + pc is calculated using signed arithmetic\n\njal x0, imm[20:1] (special case:\ + \ unconditional jump)\npc += Sext({imm[20:1], 1’b0})" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nAll bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_jal_cg.cp_rd_toggle + comments: '' +- 001_JALR: !Subfeature + name: 001_JALR + tag: VP_IP002_P001 + next_elt_id: 3 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F002_S001_I000 + description: "jalr rd, rs1, imm[11:0]\nrd = pc+4; pc = rs1 + Sext(imm[11:0])\n\ + pc is calculated using signed arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_jalr_cg.cp_rs1\nisacov.rv32i_jalr_cg.cp_rd\nisacov.rv32i_jalr_cg.cp_rd_rs1_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F002_S001_I001 + description: "jalr rd, rs1, imm[11:0]\nrd = pc+4; pc = rs1 + Sext(imm[11:0])\n\ + pc is calculated using signed arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nimmi value is +ve, -ve, and zero\nAll bits\ + \ of immi are toggled\nAll bits of rs1 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_jalr_cg.cp_immi_value\nisacov.rv32i_jalr_cg.cp_immi_toggle\n\ + isacov.rv32i_jalr_cg.cp_rs1_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F002_S001_I002 + description: "jalr rd, rs1, imm[11:0]\nrd = pc+4; pc = rs1 + Sext(imm[11:0])\n\ + pc is calculated using signed arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nAll bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_jalr_cg.cp_rd_toggle + comments: '' +- 002_BEQ: !Subfeature + name: 002_BEQ + tag: VP_IP002_P002 + next_elt_id: 3 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F002_S002_I000 + description: "beq rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1==rs2)\ + \ else pc += 4\npc is calculated using signed arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_beq_cg.cp_rs1\nisacov.rv32i_beq_cg.cp_rs2" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F002_S002_I001 + description: "beq rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1==rs2)\ + \ else pc += 4\npc is calculated using signed arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nimmb value is +ve, -ve, and zero\nAll bits\ + \ of immb are toggled\nAll bits of rs1 are toggled\nAll bits of rs2 are\ + \ toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_beq_cg.cp_immb_value\nisacov.rv32i_beq_cg.cp_rs1_toggle\n\ + isacov.rv32i_beq_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F002_S002_I002 + description: "beq rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1==rs2)\ + \ else pc += 4\npc is calculated using signed arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nBranch taken or not-taken" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_beq_cg.cp_branch_taken + comments: '' +- 003_BNE: !Subfeature + name: 003_BNE + tag: VP_IP002_P003 + next_elt_id: 3 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F002_S003_I000 + description: "bne rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1!=rs2)\ + \ else pc += 4\npc is calculated using signed arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_bne_cg.cp_rs1\nisacov.rv32i_bne_cg.cp_rs2" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F002_S003_I001 + description: "bne rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1!=rs2)\ + \ else pc += 4\npc is calculated using signed arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nimmb value is +ve, -ve, and zero\nAll bits\ + \ of immb are toggled\nAll bits of rs1 are toggled\nAll bits of rs2 are\ + \ toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_bne_cg.cp_immb_value\nisacov.rv32i_bne_cg.cp_rs1_toggle\n\ + isacov.rv32i_bne_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F002_S003_I002 + description: "bne rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1!=rs2)\ + \ else pc += 4\npc is calculated using signed arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nBranch taken or not-taken" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_bne_cg.cp_branch_taken + comments: '' +- 004_BLT: !Subfeature + name: 004_BLT + tag: VP_IP002_P004 + next_elt_id: 3 + display_order: 4 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F002_S004_I000 + description: "blt rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ + \ < rs2) else pc += 4\npc is calculated using signed arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_blt_cg.cp_rs1\nisacov.rv32i_blt_cg.cp_rs2" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F002_S004_I001 + description: "blt rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ + \ < rs2) else pc += 4\npc is calculated using signed arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nimmb value is +ve, -ve, and zero\nAll bits\ + \ of immb are toggled\nAll bits of rs1 are toggled\nAll bits of rs2 are\ + \ toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_blt_cg.cp_immb_value\nisacov.rv32i_blt_cg.cp_rs1_toggle\n\ + isacov.rv32i_blt_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F002_S004_I002 + description: "blt rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ + \ < rs2) else pc += 4\npc is calculated using signed arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nBranch taken or not-taken" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_blt_cg.cp_branch_taken + comments: '' +- 005_BGE: !Subfeature + name: 005_BGE + tag: VP_IP002_P005 + next_elt_id: 6 + display_order: 5 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F002_S005_I000 + description: "bge rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ + \ >= rs2) else pc += 4\npc is calculated using signed arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_bge_cg.cp_rs1\nisacov.rv32i_bge_cg.cp_rs2" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F002_S005_I001 + description: "bge rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ + \ >= rs2) else pc += 4\npc is calculated using signed arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nimmb value is +ve, -ve, and zero\nAll bits\ + \ of immb are toggled\nAll bits of rs1 are toggled\nAll bits of rs2 are\ + \ toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_bge_cg.cp_immb_value\nisacov.rv32i_bge_cg.cp_rs1_toggle\n\ + isacov.rv32i_bge_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F002_S005_I002 + description: "bge rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ + \ >= rs2) else pc += 4\npc is calculated using signed arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nBranch taken or not-taken" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_bge_cg.cp_branch_taken + comments: '' +- 006_BLTU: !Subfeature + name: 006_BLTU + tag: VP_IP002_P006 + next_elt_id: 3 + display_order: 6 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F002_S006_I000 + description: "bltu rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ + \ < rs2) else pc += 4\npc is calculated using unsigned arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_bltu_cg.cp_rs1\nisacov.rv32i_bltu_cg.cp_rs2" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F002_S006_I001 + description: "bltu rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ + \ < rs2) else pc += 4\npc is calculated using unsigned arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nimmb value is +ve, -ve, and zero\nAll bits\ + \ of immb are toggled\nAll bits of rs1 are toggled\nAll bits of rs2 are\ + \ toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_bltu_cg.cp_immb_value\nisacov.rv32i_bltu_cg.cp_rs1_toggle\n\ + isacov.rv32i_bltu_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F002_S006_I002 + description: "bltu rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ + \ < rs2) else pc += 4\npc is calculated using unsigned arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nBranch taken or not-taken" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_bltu_cg.cp_branch_taken + comments: '' +- 007_BGEU: !Subfeature + name: 007_BGEU + tag: VP_IP002_P007 + next_elt_id: 3 + display_order: 7 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F002_S007_I000 + description: "bgeu rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ + \ >= rs2) else pc += 4\npc is calculated using unsigned arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_bgeu_cg.cp_rs1\nisacov.rv32i_bgeu_cg.cp_rs2" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F002_S007_I001 + description: "bgeu rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ + \ >= rs2) else pc += 4\npc is calculated using unsigned arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nimmb value is +ve, -ve, and zero\nAll bits\ + \ of immb are toggled\nAll bits of rs1 are toggled\nAll bits of rs2 are\ + \ toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_bgeu_cg.cp_immb_value\nisacov.rv32i_bgeu_cg.cp_rs1_toggle\n\ + isacov.rv32i_bgeu_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F002_S007_I002 + description: "bgeu rs1, rs2, imm[12:1]\npc += Sext({imm[12:1], 1’b0}) if (rs1\ + \ >= rs2) else pc += 4\npc is calculated using unsigned arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nBranch taken or not-taken" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_bgeu_cg.cp_branch_taken + comments: '' +vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/verif/docs/VerifPlans/ISA_RV32/VP_IP003.yml b/verif/docs/VerifPlans/ISA_RV32/VP_IP003.yml new file mode 100644 index 0000000000..7980343f7e --- /dev/null +++ b/verif/docs/VerifPlans/ISA_RV32/VP_IP003.yml @@ -0,0 +1,454 @@ +!Feature +next_elt_id: 8 +name: RV32I Load and Store Instructions +id: 3 +display_order: 3 +subfeatures: !!omap +- 000_LB: !Subfeature + name: 000_LB + tag: VP_IP003_P000 + next_elt_id: 3 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F003_S000_I000 + description: "lb rd, rs1, imm\nrd = Sext(M[rs1+imm][0:7])\nrd is calculated\ + \ using signed arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lb_cg.cp_rs1\nisacov.rv32i_lb_cg.cp_rd\nisacov.rv32i_lb_cg.cp_rd_rs1_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F003_S000_I001 + description: "lb rd, rs1, imm\nrd = Sext(M[rs1+imm][0:7])\nrd is calculated\ + \ using signed arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nimmi value is +ve, -ve and zero\nAll combinations\ + \ of rs1 and immi +ve, -ve, and zero values are used\nAll bits of rs1 are\ + \ toggled\nAll bits of immi are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lb_cg.cp_immi_value\nisacov.rv32i_lb_cg.cp_rs1_toggle\n\ + isacov.rv32i_lb_cg.cp_immi_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F003_S000_I002 + description: "lb rd, rs1, imm\nrd = Sext(M[rs1+imm][0:7])\nrd is calculated\ + \ using signed arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lb_cg.cp_rd_value\nisacov.rv32i_lb_cg.cp_rd_toggle" + comments: '' +- 001_LH: !Subfeature + name: 001_LH + tag: VP_IP003_P001 + next_elt_id: 3 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F003_S001_I000 + description: "lh rd, rs1, imm\nrd = Sext(M[rs1+imm][0:15])\nrd is calculated\ + \ using signed arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lh_cg.cp_rs1\nisacov.rv32i_lh_cg.cp_rd\nisacov.rv32i_lh_cg.cp_rd_rs1_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F003_S001_I001 + description: "lh rd, rs1, imm\nrd = Sext(M[rs1+imm][0:15])\nrd is calculated\ + \ using signed arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nimmi value is +ve, -ve and zero\nAll combinations\ + \ of rs1 and immi +ve, -ve, and zero values are used\nAll bits of rs1 are\ + \ toggled\nAll bits of immi are toggled\nUnaligned and aligned accesses\ + \ from memory" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lh_cg.cp_immi_value\nisacov.rv32i_lh_cg.cp_rs1_toggle\n\ + isacov.rv32i_lh_cg.cp_immi_toggle\nisacov.rv32i_lh_cg.cp_aligned" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F003_S001_I002 + description: "lh rd, rs1, imm\nrd = Sext(M[rs1+imm][0:15])\nrd is calculated\ + \ using signed arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lh_cg.cp_rd_value\nisacov.rv32i_lh_cg.cp_rd_toggle" + comments: '' +- 002_LW: !Subfeature + name: 002_LW + tag: VP_IP003_P002 + next_elt_id: 3 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F003_S002_I000 + description: "lw rd, rs1, imm\nrd = Sext(M[rs1+imm][0:31])\nrd is calculated\ + \ using signed arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lw_cg.cp_rs1\nisacov.rv32i_lw_cg.cp_rd\nisacov.rv32i_lw_cg.cp_rd_rs1_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F003_S002_I001 + description: "lw rd, rs1, imm\nrd = Sext(M[rs1+imm][0:31])\nrd is calculated\ + \ using signed arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nimmi value is +ve, -ve and zero\nAll combinations\ + \ of rs1 and immi +ve, -ve, and zero values are used\nAll bits of rs1 are\ + \ toggled\nAll bits of immi are toggled\nUnaligned and aligned accesses\ + \ from memory" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lw_cg.cp_immi_value\nisacov.rv32i_lw_cg.cp_rs1_toggle\n\ + isacov.rv32i_lw_cg.cp_immi_toggle\nisacov.rv32i_lw_cg.cp_aligned" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F003_S002_I002 + description: "lw rd, rs1, imm\nrd = Sext(M[rs1+imm][0:31])\nrd is calculated\ + \ using signed arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lw_cg.cp_rd_value\nisacov.rv32i_lw_cg.cp_rd_toggle" + comments: '' +- 003_LBU: !Subfeature + name: 003_LBU + tag: VP_IP003_P003 + next_elt_id: 3 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F003_S003_I000 + description: "lbu rd, rs1, imm\nrd = Zext(M[rs1+imm][0:7])\nrd is calculated\ + \ using unsigned arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lbu_cg.cp_rs1\nisacov.rv32i_lbu_cg.cp_rd\nisacov.rv32i_lbu_cg.cp_rd_rs1_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F003_S003_I001 + description: "lbu rd, rs1, imm\nrd = Zext(M[rs1+imm][0:7])\nrd is calculated\ + \ using unsigned arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nimmi value is +ve, -ve and zero\nAll combinations\ + \ of rs1 and immi +ve, -ve, and zero values are used\nAll bits of rs1 are\ + \ toggled\nAll bits of immi are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lbu_cg.cp_immi_value\nisacov.rv32i_lbu_cg.cp_rs1_toggle\n\ + isacov.rv32i_lbu_cg.cp_immi_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F003_S003_I002 + description: "lbu rd, rs1, imm\nrd = Zext(M[rs1+imm][0:7])\nrd is calculated\ + \ using unsigned arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd[7:0] are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lbu_cg.cp_rd_value\nisacov.rv32i_lbu_cg.cp_rd_toggle" + comments: '' +- 004_LHU: !Subfeature + name: 004_LHU + tag: VP_IP003_P004 + next_elt_id: 3 + display_order: 4 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F003_S004_I000 + description: "lhu rd, rs1, imm\nrd = Zext(M[rs1+imm][0:15])\nrd is calculated\ + \ using unsigned arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lhu_cg.cp_rs1\nisacov.rv32i_lhu_cg.cp_rd\nisacov.rv32i_lhu_cg.cp_rd_rs1_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F003_S004_I001 + description: "lhu rd, rs1, imm\nrd = Zext(M[rs1+imm][0:15])\nrd is calculated\ + \ using unsigned arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nimmi value is +ve, -ve and zero\nAll combinations\ + \ of rs1 and immi +ve, -ve, and zero values are used\nAll bits of rs1 are\ + \ toggled\nAll bits of immi are toggled\nUnaligned and aligned accesses\ + \ from memory" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lhu_cg.cp_immi_value\nisacov.rv32i_lhu_cg.cp_rs1_toggle\n\ + isacov.rv32i_lhu_cg.cp_immi_toggle\nisacov.rv32i_lhu_cg.cp_aligned" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F003_S004_I002 + description: "lhu rd, rs1, imm\nrd = Zext(M[rs1+imm][0:15])\nrd is calculated\ + \ using unsigned arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd[15:0] are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_lhu_cg.cp_rd_value\nisacov.rv32i_lhu_cg.cp_rd_toggle" + comments: '' +- 005_SB: !Subfeature + name: 005_SB + tag: VP_IP003_P005 + next_elt_id: 3 + display_order: 5 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F003_S005_I000 + description: "sb rs1, rs2, imm\nM[rs1+imm][0:7] = rs2[0:7]" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sb_cg.cp_rs1\nisacov.rv32i_sb_cg.cp_rs2" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F003_S005_I001 + description: "sb rs1, rs2, imm\nM[rs1+imm][0:7] = rs2[0:7]" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nimms value is +ve, -ve and zero\nAll bits\ + \ of rs1 are toggled\nAll bits of rs2 are toggled\nAll bits of imms are\ + \ toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sb_cg.cp_imms_value\nisacov.rv32i_sb_cg.cp_rs1_toggle\n\ + isacov.rv32i_sb_cg.cp_rs2_toggle\nisacov.rv32i_sb_cg.cp_imms_toggle" + comments: '' +- 006_SH: !Subfeature + name: 006_SH + tag: VP_IP003_P006 + next_elt_id: 2 + display_order: 6 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F003_S006_I000 + description: "sh rs1, rs2, imm\nM[rs1+imm][0:15] = rs2[0:15]" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sh_cg.cp_rs1\nisacov.rv32i_sh_cg.cp_rs2" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F003_S006_I001 + description: "sh rs1, rs2, imm\nM[rs1+imm][0:15] = rs2[0:15]" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nimms value is +ve, -ve and zero\nAll bits\ + \ of rs1 are toggled\nAll bits of rs2 are toggled\nAll bits of imms are\ + \ toggled\nUnaligned and aligned accesses to memory" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sh_cg.cp_imms_value\nisacov.rv32i_sh_cg.cp_rs1_toggle\n\ + isacov.rv32i_sh_cg.cp_rs2_toggle\nisacov.rv32i_sh_cg.cp_imms_toggle\nisacov.rv32i_sh_cg.cp_aligned" + comments: '' +- 007_SW: !Subfeature + name: 007_SW + tag: VP_IP003_P007 + next_elt_id: 2 + display_order: 7 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F003_S007_I000 + description: "sw rs1, rs2, imm\nM[rs1+imm][0:31] = rs2[0:31]" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sw_cg.cp_rs1\nisacov.rv32i_sw_cg.cp_rs2" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F003_S007_I001 + description: "sw rs1, rs2, imm\nM[rs1+imm][0:31] = rs2[0:31]" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nimms value is +ve, -ve and zero\nAll bits\ + \ of rs1 are toggled\nAll bits of rs2 are toggled\nAll bits of imms are\ + \ toggled\nUnaligned and aligned accesses to memory" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32i_sw_cg.cp_imms_value\nisacov.rv32i_sw_cg.cp_rs1_toggle\n\ + isacov.rv32i_sw_cg.cp_rs2_toggle\nisacov.rv32i_sw_cg.cp_imms_toggle\nisacov.rv32i_sw_cg.cp_aligned" + comments: '' +vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/verif/docs/VerifPlans/ISA_RV32/VP_IP004.yml b/verif/docs/VerifPlans/ISA_RV32/VP_IP004.yml new file mode 100644 index 0000000000..332583c946 --- /dev/null +++ b/verif/docs/VerifPlans/ISA_RV32/VP_IP004.yml @@ -0,0 +1,33 @@ +!Feature +next_elt_id: 1 +name: RV32I Memory Ordering Instructions +id: 4 +display_order: 4 +subfeatures: !!omap +- 000_FENCE: !Subfeature + name: 000_FENCE + tag: VP_IP004_P000 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F004_S000_I000 + description: "Fence operation executed\nImplementation is microarchitecture\ + \ specific" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Instruction executed + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_fence.cp_fixed + comments: '' +vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/verif/docs/VerifPlans/ISA_RV32/VP_IP005.yml b/verif/docs/VerifPlans/ISA_RV32/VP_IP005.yml new file mode 100644 index 0000000000..a2cfdcaa3e --- /dev/null +++ b/verif/docs/VerifPlans/ISA_RV32/VP_IP005.yml @@ -0,0 +1,70 @@ +!Feature +next_elt_id: 2 +name: RV32I Environment Call and Breakpoints +id: 5 +display_order: 5 +subfeatures: !!omap +- 000_ECALL: !Subfeature + name: 000_ECALL + tag: VP_IP005_P000 + next_elt_id: 2 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F005_S000_I000 + description: Software exception vector entered + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Instruction executed + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_ecall.cp_fixed + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F005_S000_I001 + description: Return control to a debugger + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Instruction executed + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_ebreak.cp_fixed + comments: '' +- 001_EBREAK: !Subfeature + name: 001_EBREAK + tag: VP_IP005_P001 + next_elt_id: 1 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F005_S001_I000 + description: Return control to a debugger + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Instruction executed + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32i_ebreak.cp_fixed + comments: '' +vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/verif/docs/VerifPlans/ISA_RV32/VP_IP006.yml b/verif/docs/VerifPlans/ISA_RV32/VP_IP006.yml new file mode 100644 index 0000000000..d6f0e2de4e --- /dev/null +++ b/verif/docs/VerifPlans/ISA_RV32/VP_IP006.yml @@ -0,0 +1,275 @@ +!Feature +next_elt_id: 7 +name: RV32M Multiplication Operations +id: 6 +display_order: 6 +subfeatures: !!omap +- 000_MUL: !Subfeature + name: 000_MUL + tag: VP_IP000_P000 + next_elt_id: 3 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F006_S000_I000 + description: "mul rd, rs1, rs2\nx[rd] = x[rs1] * x[rs2]\nArithmetic overflow\ + \ is ignored." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_mul_cg.cp_rs1\nisacov.rv32m_mul_cg.cp_rs2\nisacov.rv32m_mul_cg.cp_rd\n\ + isacov.rv32m_mul_cg.cp_rd_rs1_hazard\nisacov.rv32m_mul_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F006_S000_I001 + description: "mul rd, rs1, rs2\nx[rd] = x[rs1] * x[rs2]\nArithmetic overflow\ + \ is ignored." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nrs1 value is non-zero and zero\nrs2 value\ + \ is non-zero and zero\nAll combinations of rs1 and rs2 non-zero and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_mul_cg.cp_rs1_value\nisacov.rv32m_mul_cg.cp_rs2_value\n\ + isacov.rv32m_mul_cg.cross_rs1_rs2_value\nisacov.rv32m_mul_cg.cp_rs1_toggle\ + \ \nisacov.rv32m_mul_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F006_S000_I002 + description: "mul rd, rs1, rs2\nx[rd] = x[rs1] * x[rs2]\nArithmetic overflow\ + \ is ignored." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is non-zero and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_mul_cg.cp_rd_value\nisacov.rv32m_mul_cg.cp_rd_toggle" + comments: '' +- 001_MULH: !Subfeature + name: 001_MULH + tag: VP_IP000_P001 + next_elt_id: 3 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F006_S001_I000 + description: "mulh rd, rs1, rs2\nx[rd] = (x[rs1] * x[rs2]) >>s XLEN\nBoth\ + \ rs1 and rs2 treated as signed numbers" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 32 + coverage_loc: "isacov.rv32m_mulh_cg.cp_rs1\nisacov.rv32m_mulh_cg.cp_rs2\n\ + isacov.rv32m_mulh_cg.cp_rd\nisacov.rv32m_mulh_cg.cp_rd_rs1_hazard\nisacov.rv32m_mulh_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F006_S001_I001 + description: "mulh rd, rs1, rs2\nx[rd] = (x[rs1] * x[rs2]) >>s XLEN\nBoth\ + \ rs1 and rs2 treated as signed numbers" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nrs2 value\ + \ is +ve, -ve and zero\nAll combinations of rs1 and rs2 +ve, -ve, and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 32 + coverage_loc: "isacov.rv32m_mulh_cg.cp_rs1_value\nisacov.rv32m_mulh_cg.cp_rs2_value\n\ + isacov.rv32m_mulh_cg.cross_rs1_rs2_value\nisacov.rv32m_mulh_cg.cp_rs1_toggle\ + \ \nisacov.rv32m_mulh_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F006_S001_I002 + description: "mulh rd, rs1, rs2\nx[rd] = (x[rs1] * x[rs2]) >>s XLEN\nBoth\ + \ rs1 and rs2 treated as signed numbers" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_mulh_cg.cp_rd_value\nisacov.rv32m_mulh_cg.cp_rd_toggle" + comments: '' +- 002_MULHU: !Subfeature + name: 002_MULHU + tag: VP_IP000_P002 + next_elt_id: 3 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F006_S002_I000 + description: "mulhu rd, rs1, rs2\nx[rd] = (x[rs1] * x[rs2]) >> XLEN\nBoth\ + \ rs1 and rs2 treated as unsigned numbers" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_mulhu_cg.cp_rs1\nisacov.rv32m_mulhu_cg.cp_rs2\n\ + isacov.rv32m_mulhu_cg.cp_rd\nisacov.rv32m_mulhu_cg.cp_rd_rs1_hazard\nisacov.rv32m_mulhu_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F006_S002_I001 + description: "mulhu rd, rs1, rs2\nx[rd] = (x[rs1] * x[rs2]) >> XLEN\nBoth\ + \ rs1 and rs2 treated as unsigned numbers" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nrs1 value is non-zero and zero\nrs2 value\ + \ is non-zero and zero\nAll combinations of rs1 and rs2 non-zero and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_mulhu_cg.cp_rs1_value\nisacov.rv32m_mulhu_cg.cp_rs2_value\n\ + isacov.rv32m_mulhu_cg.cross_rs1_rs2_value\nisacov.rv32m_mulhu_cg.cp_rs1_toggle\ + \ \nisacov.rv32m_mulhu_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F006_S002_I002 + description: "mulhu rd, rs1, rs2\nx[rd] = (x[rs1] * x[rs2]) >> XLEN\nBoth\ + \ rs1 and rs2 treated as unsigned numbers" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is non-zero and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_mulhu_cg.cp_rd_value\nisacov.rv32m_mulhu_cg.cp_rd_toggle" + comments: '' +- 003_MULHSU: !Subfeature + name: 003_MULHSU + tag: VP_IP000_P003 + next_elt_id: 3 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F006_S003_I000 + description: "mulhsu rd, rs1, rs2\nx[rd] = (x[rs1] * x[rs2]) >>s XLEN\nrs1\ + \ treated as signed number, rs2 treated as unsigned number" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_mulhsu_cg.cp_rs1\nisacov.rv32m_mulhsu_cg.cp_rs2\n\ + isacov.rv32m_mulhsu_cg.cp_rd\nisacov.rv32m_mulhsu_cg.cp_rd_rs1_hazard\n\ + isacov.rv32m_mulhsu_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F006_S003_I001 + description: "mulhsu rd, rs1, rs2\nx[rd] = (x[rs1] * x[rs2]) >>s XLEN\nrs1\ + \ treated as signed number, rs2 treated as unsigned number" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nrs2 value\ + \ is non-zero and zero\nAll combinations of rs1 and rs2 +ve, -ve, and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_mulhsu_cg.cp_rs1_value\nisacov.rv32m_mulhsu_cg.cp_rs2_value\n\ + isacov.rv32m_mulhsu_cg.cross_rs1_rs2_value\nisacov.rv32m_mulhsu_cg.cp_rs1_toggle\ + \ \nisacov.rv32m_mulhsu_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F006_S003_I002 + description: "mulhsu rd, rs1, rs2\nx[rd] = (x[rs1] * x[rs2]) >>s XLEN\nrs1\ + \ treated as signed number, rs2 treated as unsigned number" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_mulhsu_cg.cp_rd_value\nisacov.rv32m_mulhsu_cg.cp_rd_toggle" + comments: '' +vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/verif/docs/VerifPlans/ISA_RV32/VP_IP007.yml b/verif/docs/VerifPlans/ISA_RV32/VP_IP007.yml new file mode 100644 index 0000000000..f507c377c7 --- /dev/null +++ b/verif/docs/VerifPlans/ISA_RV32/VP_IP007.yml @@ -0,0 +1,350 @@ +!Feature +next_elt_id: 4 +name: RV32M Division Operations +id: 7 +display_order: 7 +subfeatures: !!omap +- 000_DIV: !Subfeature + name: 000_DIV + tag: VP_IP007_P000 + next_elt_id: 4 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F007_S000_I000 + description: "div rd, rs1, rs2\nx[rd] = x[rs1] / x[rs2]\nrd is calculated\ + \ using signed arithmetic; rounding towards zero" + reqt_doc: "Unprivileged ISA\nChapter 7.2" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_div_cg.cp_rs1\nisacov.rv32m_div_cg.cp_rs2\nisacov.rv32m_div_cg.cp_rd\n\ + isacov.rv32m_div_cg.cp_rd_rs1_hazard\nisacov.rv32m_div_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F007_S000_I001 + description: "div rd, rs1, rs2\nx[rd] = x[rs1] / x[rs2]\nrd is calculated\ + \ using signed arithmetic; rounding towards zero" + reqt_doc: "Unprivileged ISA\nChapter 7.2" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nrs2 value\ + \ is +ve, -ve and zero\nAll combinations of rs1 and rs2 +ve, -ve, and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_div_cg.cp_rs1_value\nisacov.rv32m_div_cg.cp_rs2_value\n\ + isacov.rv32m_div_cg.cross_rs1_rs2_value\nisacov.rv32m_div_cg.cp_rs1_toggle\ + \ \nisacov.rv32m_div_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F007_S000_I002 + description: "div rd, rs1, rs2\nx[rd] = x[rs1] / x[rs2]\nrd is calculated\ + \ using signed arithmetic; rounding towards zero" + reqt_doc: "Unprivileged ISA\nChapter 7.2" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_div_cg.cp_rs1_value\nisacov.rv32m_div_cg.cp_rs2_value\n\ + isacov.rv32m_div_cg.cross_rs1_rs2_value\nisacov.rv32m_div_cg.cp_rs1_toggle\ + \ \nisacov.rv32m_div_cg.cp_rs2_toggle" + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_ISA_RV32_F007_S000_I003 + description: "div rd, rs1, rs2\nx[rd] = x[rs1] / x[rs2]\nrd is calculated\ + \ using signed arithmetic; rounding towards zero" + reqt_doc: "Unprivileged ISA\nChapter 7.2" + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Exercise arithmetic overflow (rs1 = -2^31; rs2 = -1; returns\ + \ rd = -2^31).\nExercise division by zero (returns -1 ; all bits set)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_div_results_cg.cp_div_special_results\nisacov.rv32m_div_results_cg.cp_div_arithmetic_overflow" + comments: '' +- 001_REM: !Subfeature + name: 001_REM + tag: VP_IP007_P001 + next_elt_id: 4 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F007_S001_I000 + description: "rem rd, rs1, rs2\nx[rd] = x[rs1] % x[rs2]\nrd is calculated\ + \ using signed arithmetic; remainder from the same division than DIV (the\ + \ sign of rd equals the sign of rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_rem_cg.cp_rs1\nisacov.rv32m_rem_cg.cp_rs2\nisacov.rv32m_rem_cg.cp_rd\n\ + isacov.rv32m_rem_cg.cp_rd_rs1_hazard\nisacov.rv32m_rem_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F007_S001_I001 + description: "rem rd, rs1, rs2\nx[rd] = x[rs1] % x[rs2]\nrd is calculated\ + \ using signed arithmetic; remainder from the same division than DIV (the\ + \ sign of rd equals the sign of rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nrs1 value is +ve, -ve and zero\nrs2 value\ + \ is +ve, -ve and zero\nAll combinations of rs1 and rs2 +ve, -ve, and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_rem_cg.cp_rs1_value\nisacov.rv32m_rem_cg.cp_rs2_value\n\ + isacov.rv32m_rem_cg.cross_rs1_rs2_value\nisacov.rv32m_rem_cg.cp_rs1_toggle\ + \ \nisacov.rv32m_rem_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F007_S001_I002 + description: "rem rd, rs1, rs2\nx[rd] = x[rs1] % x[rs2]\nrd is calculated\ + \ using signed arithmetic; remainder from the same division than DIV (the\ + \ sign of rd equals the sign of rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is +ve, -ve and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_rem_cg.cp_rd_value\nisacov.rv32m_rem_cg.cp_rd_toggle" + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_ISA_RV32_F007_S001_I003 + description: "rem rd, rs1, rs2\nx[rd] = x[rs1] % x[rs2]\nrd is calculated\ + \ using signed arithmetic; remainder from the same division than DIV (the\ + \ sign of rd equals the sign of rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Exercise arithmetic overflow (rs1 = -2^31; rs2 = -1; returns\ + \ rd = 0).\nExercise division by zero (returns rs1)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_rem_results_cg.cp_div_zero\nisacov.rv32m_rem_results_cg.cp_div_arithmetic_overflow" + comments: '' +- 002_DIVU: !Subfeature + name: 002_DIVU + tag: VP_IP007_P002 + next_elt_id: 4 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F007_S002_I000 + description: "divu rd, rs1, rs2\nx[rd] = x[rs1] u/ x[rs2]\nrd is calculated\ + \ using unsigned arithmetic; rounding towards zero" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_divu_cg.cp_rs1\nisacov.rv32m_divu_cg.cp_rs2\n\ + isacov.rv32m_divu_cg.cp_rd\nisacov.rv32m_divu_cg.cp_rd_rs1_hazard\nisacov.rv32m_divu_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F007_S002_I001 + description: "divu rd, rs1, rs2\nx[rd] = x[rs1] u/ x[rs2]\nrd is calculated\ + \ using unsigned arithmetic; rounding towards zero" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nrs1 value is non-zero and zero\nrs2 value\ + \ is non-zero and zero\nAll combinations of rs1 and rs2 non-zero and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_divu_cg.cp_rs1_value\nisacov.rv32m_divu_cg.cp_rs2_value\n\ + isacov.rv32m_divu_cg.cross_rs1_rs2_value\nisacov.rv32m_divu_cg.cp_rs1_toggle\ + \ \nisacov.rv32m_divu_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F007_S002_I002 + description: "divu rd, rs1, rs2\nx[rd] = x[rs1] u/ x[rs2]\nrd is calculated\ + \ using unsigned arithmetic; rounding towards zero" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is non-zero and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_divu_cg.cp_rd_value\nisacov.rv32m_divu_cg.cp_rd_toggle" + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_ISA_RV32_F007_S002_I003 + description: "divu rd, rs1, rs2\nx[rd] = x[rs1] u/ x[rs2]\nrd is calculated\ + \ using unsigned arithmetic; rounding towards zero" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Exercise division by zero (returns 2^32-1 ; all bits set) + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32m_divu_results_cg.cp_div_zero + comments: '' +- 003_REMU: !Subfeature + name: 003_REMU + tag: VP_IP007_P003 + next_elt_id: 4 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F007_S003_I000 + description: "remu rd, rs1, rs2\nx[rd] = x[rs1] % x[rs2]\nrd is calculated\ + \ using unsigned arithmetic; remainder from the same division than DIVU" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_remu_cg.cp_rs1\nisacov.rv32m_remu_cg.cp_rs2\n\ + isacov.rv32m_remu_cg.cp_rd\nisacov.rv32m_remu_cg.cp_rd_rs1_hazard\nisacov.rv32m_remu_cg.cp_rd_rs2_hazard" + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F007_S003_I001 + description: "remu rd, rs1, rs2\nx[rd] = x[rs1] % x[rs2]\nrd is calculated\ + \ using unsigned arithmetic; remainder from the same division than DIVU" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nrs1 value is non-zero and zero\nrs2 value\ + \ is non-zero and zero\nAll combinations of rs1 and rs2 non-zero and zero\ + \ values are used\nAll bits of rs1 are toggled\nAll bits of rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_remu_cg.cp_rs1_value\nisacov.rv32m_remu_cg.cp_rs2_value\n\ + isacov.rv32m_remu_cg.cross_rs1_rs2_value\nisacov.rv32m_remu_cg.cp_rs1_toggle\ + \ \nisacov.rv32m_remu_cg.cp_rs2_toggle" + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F007_S003_I002 + description: "remu rd, rs1, rs2\nx[rd] = x[rs1] % x[rs2]\nrd is calculated\ + \ using unsigned arithmetic; remainder from the same division than DIVU" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is non-zero and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: "isacov.rv32m_remu_cg.cp_rd_value\nisacov.rv32m_remu_cg.cp_rd_toggle" + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_ISA_RV32_F007_S003_I003 + description: "remu rd, rs1, rs2\nx[rd] = x[rs1] % x[rs2]\nrd is calculated\ + \ using unsigned arithmetic; remainder from the same division than DIVU" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Exercise division by zero (returns rs1) + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32m_remu_results_cg.cp_div_zero + comments: '' +vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/verif/docs/VerifPlans/ISA_RV32/VP_IP008.yml b/verif/docs/VerifPlans/ISA_RV32/VP_IP008.yml new file mode 100644 index 0000000000..11e6f403ba --- /dev/null +++ b/verif/docs/VerifPlans/ISA_RV32/VP_IP008.yml @@ -0,0 +1,179 @@ +!Feature +next_elt_id: 2 +name: RV32A Load-Reserved/Store-Conditional Instructions +id: 8 +display_order: 8 +subfeatures: !!omap +- 000_LR.W: !Subfeature + name: 000_LR.W + tag: VP_IP008_P000 + next_elt_id: 4 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F008_S000_I000 + description: "lr.w rd, (rs1)\nrd = [rs1]\nA load occurs to address at rs1\ + \ with the results loaded to rd.\nMisaligned address should cause an exception" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F008_S000_I001 + description: "lr.w rd, (rs1)\nrd = [rs1]\nA load occurs to address at rs1\ + \ with the results loaded to rd.\nMisaligned address should cause an exception" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nAll bits of rs1 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F008_S000_I002 + description: "lr.w rd, (rs1)\nrd = [rs1]\nA load occurs to address at rs1\ + \ with the results loaded to rd.\nMisaligned address should cause an exception" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nAll bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_ISA_RV32_F008_S000_I003 + description: "lr.w rd, (rs1)\nrd = [rs1]\nA load occurs to address at rs1\ + \ with the results loaded to rd.\nMisaligned address should cause an exception" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Exception:\n\nMisaligned address (non-32-bit aligned) will always\ + \ cause exceptio" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 001_SC.W: !Subfeature + name: 001_SC.W + tag: VP_IP008_P001 + next_elt_id: 4 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F008_S001_I000 + description: "sc.w rd, rs2, (rs1)\n[rs1] = rs2\nrd = exokay ? 0 : 1\nA store\ + \ occurs to address at rs1 with data from rs2.\nIf the reservation set\ + \ from a previous LR.W fails, then rd is set to a non-zero value and the\ + \ store does not occur.\nIf the reservation set passes, then rd is set to\ + \ a zero-value and the store succeeds." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used.\n\ + All possible rd registers are used.\nAll possible register combinations\ + \ where rs1 == rd are used\nAll possible register combinations where rs2\ + \ == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F008_S001_I001 + description: "sc.w rd, rs2, (rs1)\n[rs1] = rs2\nrd = exokay ? 0 : 1\nA store\ + \ occurs to address at rs1 with data from rs2.\nIf the reservation set\ + \ from a previous LR.W fails, then rd is set to a non-zero value and the\ + \ store does not occur.\nIf the reservation set passes, then rd is set to\ + \ a zero-value and the store succeeds." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nAll bits of rs1 are toggled\nAll bits of\ + \ rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F008_S001_I002 + description: "sc.w rd, rs2, (rs1)\n[rs1] = rs2\nrd = exokay ? 0 : 1\nA store\ + \ occurs to address at rs1 with data from rs2.\nIf the reservation set\ + \ from a previous LR.W fails, then rd is set to a non-zero value and the\ + \ store does not occur.\nIf the reservation set passes, then rd is set to\ + \ a zero-value and the store succeeds." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd is either zero or non-zero to indicate\ + \ success or failure, respectively" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_ISA_RV32_F008_S001_I003 + description: "sc.w rd, rs2, (rs1)\n[rs1] = rs2\nrd = exokay ? 0 : 1\nA store\ + \ occurs to address at rs1 with data from rs2.\nIf the reservation set\ + \ from a previous LR.W fails, then rd is set to a non-zero value and the\ + \ store does not occur.\nIf the reservation set passes, then rd is set to\ + \ a zero-value and the store succeeds." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Exception:\n\nMisaligned address (non-32-bit aligned) will always\ + \ cause exception" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/verif/docs/VerifPlans/ISA_RV32/VP_IP009.yml b/verif/docs/VerifPlans/ISA_RV32/VP_IP009.yml new file mode 100644 index 0000000000..9799fa6df7 --- /dev/null +++ b/verif/docs/VerifPlans/ISA_RV32/VP_IP009.yml @@ -0,0 +1,788 @@ +!Feature +next_elt_id: 9 +name: RV32A Atomic Memory Operations +id: 9 +display_order: 9 +subfeatures: !!omap +- 000_AMOSWAP.W: !Subfeature + name: 000_AMOSWAP.W + tag: VP_IP009_P000 + next_elt_id: 4 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F009_S000_I000 + description: "amoswap.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2\nA load occurs\ + \ from the address at rs1 into rd.\nThe value at rs2 is then written back\ + \ to the address at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nAll possible rs1 registers are used.\nAll\ + \ possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F009_S000_I001 + description: "amoswap.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2\nA load occurs\ + \ from the address at rs1 into rd.\nThe value at rs2 is then written back\ + \ to the address at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nAll bits of rs1 are toggled\nAll bits of\ + \ rs2 are toggled\nZero and non-zero values of rs2 are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F009_S000_I002 + description: "amoswap.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2\nA load occurs\ + \ from the address at rs1 into rd.\nThe value at rs2 is then written back\ + \ to the address at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Output result: \n\nAll bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_ISA_RV32_F009_S000_I003 + description: "amoswap.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2\nA load occurs\ + \ from the address at rs1 into rd.\nThe value at rs2 is then written back\ + \ to the address at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Exception:\n\nMisaligned address (non-32-bit aligned) will always\ + \ cause exception" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 001_AMOADD.W: !Subfeature + name: 001_AMOADD.W + tag: VP_IP009_P001 + next_elt_id: 4 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F009_S001_I000 + description: "amoadd.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 + [rs1]\nA\ + \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ + \ and added using signed arithmetic and the result iis then written back\ + \ to the address at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nAll possible rs1 registers are used.\nAll\ + \ possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F009_S001_I001 + description: "amoadd.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 + [rs1]\nA\ + \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ + \ and added using signed arithmetic and the result iis then written back\ + \ to the address at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nAll bits of rs1 are toggled\nAll bits of\ + \ rs2 are toggled\n+ve, -ve and zero values of rs2 are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F009_S001_I002 + description: "amoadd.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 + [rs1]\nA\ + \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ + \ and added using signed arithmetic and the result iis then written back\ + \ to the address at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result: \n\n+ve, -ve and zero values of rd are used\n\ + All bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_ISA_RV32_F009_S001_I003 + description: "amoadd.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 + [rs1]\nA\ + \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ + \ and added using signed arithmetic and the result iis then written back\ + \ to the address at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Exception:\n\nMisaligned address (non-32-bit aligned) will always\ + \ cause exception" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 002_AMOAND.W: !Subfeature + name: 002_AMOAND.W + tag: VP_IP009_P002 + next_elt_id: 4 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F009_S002_I000 + description: "amoand.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 & rs[1]\nA\ + \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ + \ and bit-wise ANDed and the result iis then written back to the address\ + \ at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nAll possible rs1 registers are used.\nAll\ + \ possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F009_S002_I001 + description: "amoand.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 & rs[1]\nA\ + \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ + \ and bit-wise ANDed and the result iis then written back to the address\ + \ at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nAll bits of rs1 are toggled\nAll bits of\ + \ rs2 are toggled\nZero and non-zero values of rs2 are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F009_S002_I002 + description: "amoand.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 & rs[1]\nA\ + \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ + \ and bit-wise ANDed and the result iis then written back to the address\ + \ at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result: \n\nAll bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_ISA_RV32_F009_S002_I003 + description: "amoand.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 & rs[1]\nA\ + \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ + \ and bit-wise ANDed and the result iis then written back to the address\ + \ at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Exception:\n\nMisaligned address (non-32-bit aligned) will always\ + \ cause exception" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 003_AMOOR.W: !Subfeature + name: 003_AMOOR.W + tag: VP_IP009_P003 + next_elt_id: 4 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F009_S003_I000 + description: "amoor.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 | [rs1]\nA load\ + \ occurs from the address at rs1 into rd.\nThe values in rd and rs2 and\ + \ bit-wise ORed and the result iis then written back to the address at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nAll possible rs1 registers are used.\nAll\ + \ possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F009_S003_I001 + description: "amoor.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 | [rs1]\nA load\ + \ occurs from the address at rs1 into rd.\nThe values in rd and rs2 and\ + \ bit-wise ORed and the result iis then written back to the address at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nAll bits of rs1 are toggled\nAll bits of\ + \ rs2 are toggled\nZero and non-zero values of rs2 are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F009_S003_I002 + description: "amoor.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 | [rs1]\nA load\ + \ occurs from the address at rs1 into rd.\nThe values in rd and rs2 and\ + \ bit-wise ORed and the result iis then written back to the address at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result: \n\nAll bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_ISA_RV32_F009_S003_I003 + description: "amoor.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 | [rs1]\nA load\ + \ occurs from the address at rs1 into rd.\nThe values in rd and rs2 and\ + \ bit-wise ORed and the result iis then written back to the address at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Exception:\n\nMisaligned address (non-32-bit aligned) will always\ + \ cause exception" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 004_AMOXOR.W: !Subfeature + name: 004_AMOXOR.W + tag: VP_IP009_P004 + next_elt_id: 4 + display_order: 4 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F009_S004_I000 + description: "amoxor.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 ^ [rs1]\nA\ + \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ + \ and bit-wise XORRed and the result iis then written back to the address\ + \ at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nAll possible rs1 registers are used.\nAll\ + \ possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F009_S004_I001 + description: "amoxor.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 ^ [rs1]\nA\ + \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ + \ and bit-wise XORRed and the result iis then written back to the address\ + \ at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nAll bits of rs1 are toggled\nAll bits of\ + \ rs2 are toggled\nZero and non-zero values of rs2 are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F009_S004_I002 + description: "amoxor.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 ^ [rs1]\nA\ + \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ + \ and bit-wise XORRed and the result iis then written back to the address\ + \ at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result: \n\nAll bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_ISA_RV32_F009_S004_I003 + description: "amoxor.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = rs2 ^ [rs1]\nA\ + \ load occurs from the address at rs1 into rd.\nThe values in rd and rs2\ + \ and bit-wise XORRed and the result iis then written back to the address\ + \ at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Exception:\n\nMisaligned address (non-32-bit aligned) will always\ + \ cause exception" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 005_AMOMAX.W: !Subfeature + name: 005_AMOMAX.W + tag: VP_IP009_P005 + next_elt_id: 4 + display_order: 5 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F009_S005_I000 + description: "amomax.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = max_signed(rs2,\ + \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ + \ rd and rs2 and compared assuming signed numbers and the largest value\ + \ is then written back to the address at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nAll possible rs1 registers are used.\nAll\ + \ possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F009_S005_I001 + description: "amomax.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = max_signed(rs2,\ + \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ + \ rd and rs2 and compared assuming signed numbers and the largest value\ + \ is then written back to the address at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nAll bits of rs1 are toggled\nAll bits of\ + \ rs2 are toggled\n+ve, -ve and zero values of rs2 are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F009_S005_I002 + description: "amomax.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = max_signed(rs2,\ + \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ + \ rd and rs2 and compared assuming signed numbers and the largest value\ + \ is then written back to the address at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result: \n\n+ve, -ve and zero values of rd are used\n\ + All bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_ISA_RV32_F009_S005_I003 + description: "amomax.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = max_signed(rs2,\ + \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ + \ rd and rs2 and compared assuming signed numbers and the largest value\ + \ is then written back to the address at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Exception:\n\nMisaligned address (non-32-bit aligned) will always\ + \ cause exception" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 006_AMOMAXU.W: !Subfeature + name: 006_AMOMAXU.W + tag: VP_IP009_P006 + next_elt_id: 4 + display_order: 6 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F009_S006_I000 + description: "amomaxu.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = max_unsigned(rs2,\ + \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ + \ rd and rs2 and compared assuming unsigned numbers and the largest value\ + \ is then written back to the address at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nAll possible rs1 registers are used.\nAll\ + \ possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F009_S006_I001 + description: "amomaxu.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = max_unsigned(rs2,\ + \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ + \ rd and rs2 and compared assuming unsigned numbers and the largest value\ + \ is then written back to the address at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nAll bits of rs1 are toggled\nAll bits of\ + \ rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F009_S006_I002 + description: "amomaxu.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = max_unsigned(rs2,\ + \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ + \ rd and rs2 and compared assuming unsigned numbers and the largest value\ + \ is then written back to the address at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result: \n\nAll bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_ISA_RV32_F009_S006_I003 + description: "amomaxu.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = max_unsigned(rs2,\ + \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ + \ rd and rs2 and compared assuming unsigned numbers and the largest value\ + \ is then written back to the address at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Exception:\n\nMisaligned address (non-32-bit aligned) will always\ + \ cause exception" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 007_AMOMIN.W: !Subfeature + name: 007_AMOMIN.W + tag: VP_IP009_P007 + next_elt_id: 4 + display_order: 7 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F009_S007_I000 + description: "amomin.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = min_signed(rs2,\ + \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ + \ rd and rs2 and compared assuming signed numbers and the smaller value\ + \ is then written back to the address at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nAll possible rs1 registers are used.\nAll\ + \ possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F009_S007_I001 + description: "amomin.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = min_signed(rs2,\ + \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ + \ rd and rs2 and compared assuming signed numbers and the smaller value\ + \ is then written back to the address at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nAll bits of rs1 are toggled\nAll bits of\ + \ rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F009_S007_I002 + description: "amomin.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = min_signed(rs2,\ + \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ + \ rd and rs2 and compared assuming signed numbers and the smaller value\ + \ is then written back to the address at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result: \n\n+ve, -ve and zero values of rd are used\n\ + All bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_ISA_RV32_F009_S007_I003 + description: "amomin.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = min_signed(rs2,\ + \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ + \ rd and rs2 and compared assuming signed numbers and the smaller value\ + \ is then written back to the address at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Exception:\n\nMisaligned address (non-32-bit aligned) will always\ + \ cause exception" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 008_AMOMINU.W: !Subfeature + name: 008_AMOMINU.W + tag: VP_IP009_P008 + next_elt_id: 4 + display_order: 8 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F009_S008_I000 + description: "amominu.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = min_unsigned(rs2,\ + \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ + \ rd and rs2 and compared assuming unsigned numbers and the smaller value\ + \ is then written back to the address at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nAll possible rs1 registers are used.\nAll\ + \ possible rs2 registers are used.\nAll possible rd registers are used.\n\ + All possible register combinations where rs1 == rd are used\nAll possible\ + \ register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F009_S008_I001 + description: "amominu.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = min_unsigned(rs2,\ + \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ + \ rd and rs2 and compared assuming unsigned numbers and the smaller value\ + \ is then written back to the address at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nAll bits of rs1 are toggled\nAll bits of\ + \ rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F009_S008_I002 + description: "amominu.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = min_unsigned(rs2,\ + \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ + \ rd and rs2 and compared assuming unsigned numbers and the smaller value\ + \ is then written back to the address at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result: \n\nAll bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '003': !VerifItem + name: '003' + tag: VP_ISA_RV32_F009_S008_I003 + description: "amominu.w rd, rs2, (rs1)\nrd = [rs1]\n[rs1] = min_unsigned(rs2,\ + \ [rs1])\nA load occurs from the address at rs1 into rd.\nThe values in\ + \ rd and rs2 and compared assuming unsigned numbers and the smaller value\ + \ is then written back to the address at (rs1)" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Exception:\n\nMisaligned address (non-32-bit aligned) will always\ + \ cause exception" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/verif/docs/VerifPlans/ISA_RV32/VP_IP010.yml b/verif/docs/VerifPlans/ISA_RV32/VP_IP010.yml new file mode 100644 index 0000000000..4289289cf2 --- /dev/null +++ b/verif/docs/VerifPlans/ISA_RV32/VP_IP010.yml @@ -0,0 +1,868 @@ +!Feature +next_elt_id: 16 +name: RV32C Integer Computational Instructions +id: 10 +display_order: 10 +subfeatures: !!omap +- 000_C.LI: !Subfeature + name: 000_C.LI + tag: VP_IP008_P000 + next_elt_id: 2 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F010_S000_I000 + description: "c.li rd, imm[5:0]\nx[rd] = sext(imm)\nExpands to addi rd, x0,\ + \ imm[5:0]. Invalid when rd=x0.\nrd is calculated using signed arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nAll bits of imm[5:0] are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F010_S000_I001 + description: "c.li rd, imm[5:0]\nx[rd] = sext(imm)\nExpands to addi rd, x0,\ + \ imm[5:0]. Invalid when rd=x0.\nrd is calculated using signed arithmetic" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nAll bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 001_C.LUI: !Subfeature + name: 001_C.LUI + tag: VP_IP008_P001 + next_elt_id: 2 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F010_S001_I000 + description: "c.lui rd, nzimm[17:12]\nx[rd] = sext(nzimm[17:12] << 12)\nExpands\ + \ to lui rd, nzimm[17:12]. Invalid when rd = {x0, x2} or imm = 0.\nrd is\ + \ calculated using signed arithmetic." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nAll bits of imm[17:12] are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F010_S001_I001 + description: "c.lui rd, nzimm[17:12]\nx[rd] = sext(nzimm[17:12] << 12)\nExpands\ + \ to lui rd, nzimm[17:12]. Invalid when rd = {x0, x2} or imm = 0.\nrd is\ + \ calculated using signed arithmetic." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nAll bits of rd[31:12] are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 002_C.ADDI: !Subfeature + name: 002_C.ADDI + tag: VP_IP008_P002 + next_elt_id: 3 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F010_S002_I000 + description: "c.addi rd, nzimm[5:0]\nx[rd] = x[rd] + sext(nzimm[5:0])\nExpands\ + \ to addi rd, rd, nzimm[5:0].\nInvalid when rd=x0 or nzimm = 0. Arithmetic\ + \ overflow is lost and ignored.\nrd is calculated using signed arithmetic." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rd registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F010_S002_I001 + description: "c.addi rd, nzimm[5:0]\nx[rd] = x[rd] + sext(nzimm[5:0])\nExpands\ + \ to addi rd, rd, nzimm[5:0].\nInvalid when rd=x0 or nzimm = 0. Arithmetic\ + \ overflow is lost and ignored.\nrd is calculated using signed arithmetic." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nAll inputs bits of rd before instruction\ + \ execution are toggled\nAll bits of nzimm are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F010_S002_I002 + description: "c.addi rd, nzimm[5:0]\nx[rd] = x[rd] + sext(nzimm[5:0])\nExpands\ + \ to addi rd, rd, nzimm[5:0].\nInvalid when rd=x0 or nzimm = 0. Arithmetic\ + \ overflow is lost and ignored.\nrd is calculated using signed arithmetic." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nAll bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 003_C.ADDI16SP: !Subfeature + name: 003_C.ADDI16SP + tag: VP_IP008_P003 + next_elt_id: 3 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F010_S003_I000 + description: "c.addi16sp nzimm[9:4]\nx[2] = x[2] + sext(nzimm[9:4])\nExpands\ + \ to addi x2, x2, nzimm[9:4]. Invalid when nzimm=0.\nrd is calculated using\ + \ signed arithmetic." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\n+ve and -ve values of nzimm are used\nAll\ + \ bits of nzimm[9:4] are toggled\nAll bits of x2 before instruction execution\ + \ are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F010_S003_I001 + description: "c.addi16sp nzimm[9:4]\nx[2] = x[2] + sext(nzimm[9:4])\nExpands\ + \ to addi x2, x2, nzimm[9:4]. Invalid when nzimm=0.\nrd is calculated using\ + \ signed arithmetic." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nAll bits of x2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 004_C.ADDI4SPN: !Subfeature + name: 004_C.ADDI4SPN + tag: VP_IP008_P004 + next_elt_id: 3 + display_order: 4 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F010_S004_I000 + description: "c.addi4spn rd', nzuimm[9:2]\nx[8+rd'] = x[2] + nzuimm[9:2]\n\ + Expands to addi rd', x2, nzuimm[9:2]. Invalid when nzuimm = 0.\nrd is calculated\ + \ using signed arithmetic." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rd` registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F010_S004_I001 + description: "c.addi4spn rd', nzuimm[9:2]\nx[8+rd'] = x[2] + nzuimm[9:2]\n\ + Expands to addi rd', x2, nzuimm[9:2]. Invalid when nzuimm = 0.\nrd is calculated\ + \ using signed arithmetic." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nAll bits of nzuimm[9:2] are toggled\nAll\ + \ bits of x2 before instruction execution are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F010_S004_I002 + description: "c.addi4spn rd', nzuimm[9:2]\nx[8+rd'] = x[2] + nzuimm[9:2]\n\ + Expands to addi rd', x2, nzuimm[9:2]. Invalid when nzuimm = 0.\nrd is calculated\ + \ using signed arithmetic." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nAll bits of rd` are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 005_C.SLLI: !Subfeature + name: 005_C.SLLI + tag: VP_IP008_P005 + next_elt_id: 3 + display_order: 5 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F010_S005_I000 + description: "c.slli rd, uimm[5:0]\nx[rd] = x[rd] << uimm[5:0]\nExpands to\ + \ slli rd, rd, uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0, or rd=x0." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rd registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F010_S005_I001 + description: "c.slli rd, uimm[5:0]\nx[rd] = x[rd] << uimm[5:0]\nExpands to\ + \ slli rd, rd, uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0, or rd=x0." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nAll shift amounts from [0:31] are used\n\ + All bits of rd before instruction execution are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F010_S005_I002 + description: "c.slli rd, uimm[5:0]\nx[rd] = x[rd] << uimm[5:0]\nExpands to\ + \ slli rd, rd, uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0, or rd=x0." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nAll bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 006_C.SRLI: !Subfeature + name: 006_C.SRLI + tag: VP_IP008_P006 + next_elt_id: 3 + display_order: 6 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F010_S006_I000 + description: "c.srli rd', uimm[5:0]\nx[8+rd'] = x[8+rd'] >>u uimm[5:0]\nExpands\ + \ to srli rd', rd', uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0," + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rd` registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F010_S006_I001 + description: "c.srli rd', uimm[5:0]\nx[8+rd'] = x[8+rd'] >>u uimm[5:0]\nExpands\ + \ to srli rd', rd', uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0," + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nAll shift amounts from [0:31] are used\n\ + All bits of rd before instruction execution are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F010_S006_I002 + description: "c.srli rd', uimm[5:0]\nx[8+rd'] = x[8+rd'] >>u uimm[5:0]\nExpands\ + \ to srli rd', rd', uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0," + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nAll bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 007_C.SRAI: !Subfeature + name: 007_C.SRAI + tag: VP_IP008_P007 + next_elt_id: 3 + display_order: 7 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F010_S007_I000 + description: "c.srai rd', uimm[5:0]\nx[8+rd'] = x[8+rd'] >> uimm[5:0]\nExpands\ + \ to srai rd', rd', uimm[5:0]." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rd` registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F010_S007_I001 + description: "c.srai rd', uimm[5:0]\nx[8+rd'] = x[8+rd'] >> uimm[5:0]\nExpands\ + \ to srai rd', rd', uimm[5:0]." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nAll shift amounts from [0:31] are used\n\ + +ve, -ve and zero values of rd` are used\nAll bits of rd` before instruction\ + \ execution are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F010_S007_I002 + description: "c.srai rd', uimm[5:0]\nx[8+rd'] = x[8+rd'] >> uimm[5:0]\nExpands\ + \ to srai rd', rd', uimm[5:0]." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nAll bits of rd` are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 008_C.ANDI: !Subfeature + name: 008_C.ANDI + tag: VP_IP008_P008 + next_elt_id: 3 + display_order: 8 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F010_S008_I000 + description: "c.andi rd', imm[5:0]\nx[8+rd'] = x[8+rd'] & sext(imm[5:0])\n\ + Expands to andi rd', rd', imm[5:0].\nimm treated as signed number" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rd` registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F010_S008_I001 + description: "c.andi rd', imm[5:0]\nx[8+rd'] = x[8+rd'] & sext(imm[5:0])\n\ + Expands to andi rd', rd', imm[5:0].\nimm treated as signed number" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nAll shift amounts from [0:31] are used\n\ + +ve, -ve and zero values of imm are used\nAll bits of rd` before instruction\ + \ execution are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F010_S008_I002 + description: "c.andi rd', imm[5:0]\nx[8+rd'] = x[8+rd'] & sext(imm[5:0])\n\ + Expands to andi rd', rd', imm[5:0].\nimm treated as signed number" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nAll bits of rd` are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 009_C.MV: !Subfeature + name: 009_C.MV + tag: VP_IP008_P009 + next_elt_id: 3 + display_order: 9 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F010_S009_I000 + description: "c.mv rd, rs2\nx[rd] = x[rs2]\nExpands to add rd, x0, rs2\nInvalid\ + \ when rs2=x0 or rd=x0." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rd registers are used.\n\ + All possible register combinations where rs2 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F010_S009_I001 + description: "c.mv rd, rs2\nx[rd] = x[rs2]\nExpands to add rd, x0, rs2\nInvalid\ + \ when rs2=x0 or rd=x0." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nAll bits of rs2 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F010_S009_I002 + description: "c.mv rd, rs2\nx[rd] = x[rs2]\nExpands to add rd, x0, rs2\nInvalid\ + \ when rs2=x0 or rd=x0." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nAll bits of rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 010_C.ADD: !Subfeature + name: 010_C.ADD + tag: VP_IP008_P010 + next_elt_id: 3 + display_order: 10 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F010_S010_I000 + description: "c.add rd, rs2\nx[rd] = x[rd] + x[rs2]\nExpands to add rd, rd,\ + \ rs2. Invalid when rd=x0 or rs2=x0.\nArithmetic overflow is lost and ignored" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rd registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F010_S010_I001 + description: "c.add rd, rs2\nx[rd] = x[rd] + x[rs2]\nExpands to add rd, rd,\ + \ rs2. Invalid when rd=x0 or rs2=x0.\nArithmetic overflow is lost and ignored" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\n+ve,-ve and zero values of rs2 are used\n\ + +ve,-ve, and zero values of rdrs1 are used\nAll bits of rs2 are toggled\n\ + All bits of rd before instruction execution are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F010_S010_I002 + description: "c.add rd, rs2\nx[rd] = x[rd] + x[rs2]\nExpands to add rd, rd,\ + \ rs2. Invalid when rd=x0 or rs2=x0.\nArithmetic overflow is lost and ignored" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nAll bits of rd are toggled\n+ve,-ve and zero\ + \ values of rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 011_C.AND: !Subfeature + name: 011_C.AND + tag: VP_IP008_P011 + next_elt_id: 3 + display_order: 11 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F010_S011_I000 + description: "c.and rd', rs2'\nx[8+rd'] = x[8+rd'] & x[8+rs2']\nExpands to\ + \ and rd', rd', rs2'." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rd` registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F010_S011_I001 + description: "c.and rd', rs2'\nx[8+rd'] = x[8+rd'] & x[8+rs2']\nExpands to\ + \ and rd', rd', rs2'." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nNon-zero and zero values of rs2` are used\n\ + Non-zero and zero values of rd` are used\nAll bits of rs2` are toggled\n\ + All bits of rd` before instruction execution are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F010_S011_I002 + description: "c.and rd', rs2'\nx[8+rd'] = x[8+rd'] & x[8+rs2']\nExpands to\ + \ and rd', rd', rs2'." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nAll bits of rd` are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 012_C.OR: !Subfeature + name: 012_C.OR + tag: VP_IP008_P012 + next_elt_id: 3 + display_order: 12 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F010_S012_I000 + description: "c.or rd', rs2'\nx[8+rd'] = x[8+rd'] | x[8+rs2']\nExpands to\ + \ or rd', rd', rs2'." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rd` registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F010_S012_I001 + description: "c.or rd', rs2'\nx[8+rd'] = x[8+rd'] | x[8+rs2']\nExpands to\ + \ or rd', rd', rs2'." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nNon-zero and zero values of rs2` are used\n\ + Non-zero and zero values of rd` are used\nAll bits of rs2` are toggled\n\ + All bits of rd` before instruction execution are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F010_S012_I002 + description: "c.or rd', rs2'\nx[8+rd'] = x[8+rd'] | x[8+rs2']\nExpands to\ + \ or rd', rd', rs2'." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nAll bits of rd` are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 013_C.XOR: !Subfeature + name: 013_C.XOR + tag: VP_IP008_P013 + next_elt_id: 3 + display_order: 13 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F010_S013_I000 + description: "c.xor rd', rs2'\nx[8+rd'] = x[8+rd'] ^ x[8+rs2']\nExpands to\ + \ xor rd', rd', rs2'." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rd` registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F010_S013_I001 + description: "c.xor rd', rs2'\nx[8+rd'] = x[8+rd'] ^ x[8+rs2']\nExpands to\ + \ xor rd', rd', rs2'." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nNon-zero and zero values of rs2` are used\n\ + Non-zero and zero values of rd` are used\nAll bits of rs2` are toggled\n\ + All bits of rd` before instruction execution are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F010_S013_I002 + description: "c.xor rd', rs2'\nx[8+rd'] = x[8+rd'] ^ x[8+rs2']\nExpands to\ + \ xor rd', rd', rs2'." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nAll bits of rd` are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 014_C.SUB: !Subfeature + name: 014_C.SUB + tag: VP_IP008_P014 + next_elt_id: 3 + display_order: 14 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F010_S014_I000 + description: "c.sub rd', rs2'\nx[8+rd'] = x[8+rd'] - x[8+rs2']\nExpands to\ + \ sub rd', rd', rs2'. Arithmetic underflow is ignored" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rd` registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F010_S014_I001 + description: "c.sub rd', rs2'\nx[8+rd'] = x[8+rd'] - x[8+rs2']\nExpands to\ + \ sub rd', rd', rs2'. Arithmetic underflow is ignored" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\n+ve,-ve and zero values of rs2` are used\n\ + +ve, -ve, and zero values of rd` are used\nAll bits of rs2` are toggled\n\ + All bits of rd` before instruction execution are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F010_S014_I002 + description: "c.sub rd', rs2'\nx[8+rd'] = x[8+rd'] - x[8+rs2']\nExpands to\ + \ sub rd', rd', rs2'. Arithmetic underflow is ignored" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nAll bits of rd` are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 015_C.EBREAK: !Subfeature + name: 015_C.EBREAK + tag: VP_IP008_P015 + next_elt_id: 1 + display_order: 15 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F010_S015_I000 + description: "c.ebreak\nRaiseException(Breakpoint)\nExpands to ebreak." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Instruction executed + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/verif/docs/VerifPlans/ISA_RV32/VP_IP011.yml b/verif/docs/VerifPlans/ISA_RV32/VP_IP011.yml new file mode 100644 index 0000000000..2e9439798a --- /dev/null +++ b/verif/docs/VerifPlans/ISA_RV32/VP_IP011.yml @@ -0,0 +1,286 @@ +!Feature +next_elt_id: 6 +name: RV32C Control Transfer Instructions +id: 11 +display_order: 11 +subfeatures: !!omap +- 000_C.J: !Subfeature + name: 000_C.J + tag: VP_IP010_P000 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F011_S000_I000 + description: "c.j imm[11:1]\npc += sext(imm)\npc is calculated using signed\ + \ arithmetic\nExpands to jal x0, imm[11:1]." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nuimm value is non-zero and zero\nAll bits\ + \ of uimm are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 001_C.JAL: !Subfeature + name: 001_C.JAL + tag: VP_IP010_P001 + next_elt_id: 2 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F011_S001_I000 + description: "c.jal imm[11:1]\nx[1] = pc+2; pc += sext(imm)\npc is calculated\ + \ using signed arithmetic." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nuimm value is non-zero and zero\nAll bits\ + \ of uimm are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F011_S001_I001 + description: "c.jal imm[11:1]\nx[1] = pc+2; pc += sext(imm)\npc is calculated\ + \ using signed arithmetic." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nAll bits of x1 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 002_C.JR: !Subfeature + name: 002_C.JR + tag: VP_IP010_P002 + next_elt_id: 2 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F011_S002_I000 + description: "c.jr rs1\npc = x[rs1]\nExpands to jalr x0, 0(rs1). \nInvalid\ + \ when rs1=x0." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F011_S002_I001 + description: "c.jr rs1\npc = x[rs1]\nExpands to jalr x0, 0(rs1). \nInvalid\ + \ when rs1=x0." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nAll bits of rs1 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 003_C.JALR: !Subfeature + name: 003_C.JALR + tag: VP_IP010_P003 + next_elt_id: 3 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F011_S003_I000 + description: "c.jalr rs1\nt = pc + 2; pc = x[rs1]; x[1] = t\nExpands to jalr\ + \ x1, 0(rs1). \nInvalid when rs1=x0." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F011_S003_I001 + description: "c.jalr rs1\nt = pc + 2; pc = x[rs1]; x[1] = t\nExpands to jalr\ + \ x1, 0(rs1). \nInvalid when rs1=x0." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nAll bits of rs1 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F011_S003_I002 + description: "c.jalr rs1\nt = pc + 2; pc = x[rs1]; x[1] = t\nExpands to jalr\ + \ x1, 0(rs1). \nInvalid when rs1=x0." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nAll bits of x1 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 004_C.BEQZ: !Subfeature + name: 004_C.BEQZ + tag: VP_IP010_P004 + next_elt_id: 3 + display_order: 4 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F011_S004_I000 + description: "c.beqz rs1', imm[8:1]\nif (x[8+rs1'] == 0) pc += sext(imm)\n\ + Expands to beq rs1', x0, imm[8:1]. pc is calculated using signed arithmetic." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1` registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F011_S004_I001 + description: "c.beqz rs1', imm[8:1]\nif (x[8+rs1'] == 0) pc += sext(imm)\n\ + Expands to beq rs1', x0, imm[8:1]. pc is calculated using signed arithmetic." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nAll bits of rs1` are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F011_S004_I002 + description: "c.beqz rs1', imm[8:1]\nif (x[8+rs1'] == 0) pc += sext(imm)\n\ + Expands to beq rs1', x0, imm[8:1]. pc is calculated using signed arithmetic." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nBranch taken or not-taken" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 005_C.BNEZ: !Subfeature + name: 005_C.BNEZ + tag: VP_IP010_P005 + next_elt_id: 3 + display_order: 5 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F011_S005_I000 + description: "c.bnez rs1', imm[8:1]\nif (x[8+rs1'] ≠ 0) pc += sext(imm)\n\ + Expands to bne rs1', x0, imm[8:1]. pc is calculated using signed arithmetic." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1` registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F011_S005_I001 + description: "c.bnez rs1', imm[8:1]\nif (x[8+rs1'] ≠ 0) pc += sext(imm)\n\ + Expands to bne rs1', x0, imm[8:1]. pc is calculated using signed arithmetic." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nAll bits of rs1 are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F011_S005_I002 + description: "c.bnez rs1', imm[8:1]\nif (x[8+rs1'] ≠ 0) pc += sext(imm)\n\ + Expands to bne rs1', x0, imm[8:1]. pc is calculated using signed arithmetic." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nBranch taken or not-taken" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/verif/docs/VerifPlans/ISA_RV32/VP_IP012.yml b/verif/docs/VerifPlans/ISA_RV32/VP_IP012.yml new file mode 100644 index 0000000000..c32098fd38 --- /dev/null +++ b/verif/docs/VerifPlans/ISA_RV32/VP_IP012.yml @@ -0,0 +1,218 @@ +!Feature +next_elt_id: 4 +name: RV32C Load and Store Instructions +id: 12 +display_order: 12 +subfeatures: !!omap +- 000_C.LWSP: !Subfeature + name: 000_C.LWSP + tag: VP_IP009_P000 + next_elt_id: 3 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F012_S000_I000 + description: "c.lwsp rd, uimm(x2)\nx[rd] = sext(M[x[2] + uimm][0:31])\nExpands\ + \ to lw rd, uimm[7:2](x2). \nInvalid when rd=x0.\nuimm treated as unsigned\ + \ number" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rd registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F012_S000_I001 + description: "c.lwsp rd, uimm(x2)\nx[rd] = sext(M[x[2] + uimm][0:31])\nExpands\ + \ to lw rd, uimm[7:2](x2). \nInvalid when rd=x0.\nuimm treated as unsigned\ + \ number" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nuimm value is non-zero and zero\nAll bits\ + \ of uimm are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F012_S000_I002 + description: "c.lwsp rd, uimm(x2)\nx[rd] = sext(M[x[2] + uimm][0:31])\nExpands\ + \ to lw rd, uimm[7:2](x2). \nInvalid when rd=x0.\nuimm treated as unsigned\ + \ number" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd value is non-zero and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 001_C.SWSP: !Subfeature + name: 001_C.SWSP + tag: VP_IP009_P001 + next_elt_id: 2 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F012_S001_I000 + description: "c.swsp rs2, uimm(x2)\nM[x[2] + uimm][0:31] = x[rs2]\nExpands\ + \ to sw rs2, uimm[7:2](x2).\nuimm treated as unsigned number" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs2 registers are used." + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F012_S001_I001 + description: "c.swsp rs2, uimm(x2)\nM[x[2] + uimm][0:31] = x[rs2]\nExpands\ + \ to sw rs2, uimm[7:2](x2).\nuimm treated as unsigned number" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nuimm value is non-zero and zero\nAll bits\ + \ of uimm are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 002_C.LW: !Subfeature + name: 002_C.LW + tag: VP_IP009_P002 + next_elt_id: 3 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F012_S002_I000 + description: "c.lw rd', uimm(rs1')\nx[rd] = sext(M[x[rs1] + uimm][0:31]),\ + \ where rd=8+rd' and rs1=8+rs1'\nExpands to lw rd', uimm[6:2](rs1')" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1` registers are used.\n\ + All possible rd` registers are used.\nAll possible register combinations\ + \ where rs1` == rd` are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F012_S002_I001 + description: "c.lw rd', uimm(rs1')\nx[rd] = sext(M[x[rs1] + uimm][0:31]),\ + \ where rd=8+rd' and rs1=8+rs1'\nExpands to lw rd', uimm[6:2](rs1')" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nuimm value is non-zero and zero\nAll bits\ + \ of uimm are toggled\nAll bits of rs1` are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_ISA_RV32_F012_S002_I002 + description: "c.lw rd', uimm(rs1')\nx[rd] = sext(M[x[rs1] + uimm][0:31]),\ + \ where rd=8+rd' and rs1=8+rs1'\nExpands to lw rd', uimm[6:2](rs1')" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Output result:\n\nrd` value is non-zero and zero\nAll bits of\ + \ rd are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 003_C.SW: !Subfeature + name: 003_C.SW + tag: VP_IP009_P003 + next_elt_id: 2 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F012_S003_I000 + description: "c.sw rs2', uimm(rs1')\nM[x[rs1] + uimm][0:31] = x[rs2], where\ + \ rs2=8+rs2' and rs1=8+rs1'\nExpands to sw rs2', uimm[6:2](rs1')." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1` registers are used.\n\ + All possible rd` registers are used.\nAll possible register combinations\ + \ where rs1` == rd` are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F012_S003_I001 + description: "c.sw rs2', uimm(rs1')\nM[x[rs1] + uimm][0:31] = x[rs2], where\ + \ rs2=8+rs2' and rs1=8+rs1'\nExpands to sw rs2', uimm[6:2](rs1')." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operands:\n\nuimm value is non-zero and zero\nAll bits\ + \ of uimm are toggled\nAll bits of rs1` are toggled\nAll bits of rs2` are\ + \ toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/verif/docs/VerifPlans/ISA_RV32/VP_IP013.yml b/verif/docs/VerifPlans/ISA_RV32/VP_IP013.yml new file mode 100644 index 0000000000..d79d48918b --- /dev/null +++ b/verif/docs/VerifPlans/ISA_RV32/VP_IP013.yml @@ -0,0 +1,263 @@ +!Feature +next_elt_id: 6 +name: RV32Zicsr Control and Status Register (CSR) Instructions +id: 13 +display_order: 13 +subfeatures: !!omap +- 000_CSRRW: !Subfeature + name: 000_CSRRW + tag: VP_IP007_P000 + next_elt_id: 2 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F013_S000_I000 + description: "csrrw rd, rs1, csr\nrd = Zext([csr]); csr = [rs1]" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used\n\ + All possible rd registers are used\nAll supported CSRs are used\nAll possible\ + \ register combinations where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F013_S000_I001 + description: "csrrw rd, rs1, csr\nrd = Zext([csr]); csr = [rs1]" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operand:\n\nNon-zero and zero rs1 operands are used (if\ + \ rs1 != x0)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 001_CSRRS: !Subfeature + name: 001_CSRRS + tag: VP_IP007_P001 + next_elt_id: 2 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F013_S001_I000 + description: "csrrs rd, rs1, csr\nrd = Zext([csr]); csr = [rs1] | csr\nNote\ + \ that not all bits of csr will be writable." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used\n\ + All possible rd registers are used\nAll supported CSRs are used\nAll possible\ + \ register combinations where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F013_S001_I001 + description: "csrrs rd, rs1, csr\nrd = Zext([csr]); csr = [rs1] | csr\nNote\ + \ that not all bits of csr will be writable." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operand:\n\nNon-zero and zero rs1 operands are used (if\ + \ rs1 != x0)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 002_CSRRC: !Subfeature + name: 002_CSRRC + tag: VP_IP007_P002 + next_elt_id: 2 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F013_S002_I000 + description: "csrrs rd, rs1, csr\nrd = Zext([csr]); csr = ~[rs1] | csr\nNote\ + \ that not all bits of csr will be writable." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rs1 registers are used\n\ + All possible rd registers are used\nAll supported CSRs are used\nAll possible\ + \ register combinations where rs1 == rd are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F013_S002_I001 + description: "csrrs rd, rs1, csr\nrd = Zext([csr]); csr = ~[rs1] | csr\nNote\ + \ that not all bits of csr will be writable." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operand:\n\nNon-zero and zero rs1 operands are used (if\ + \ rs1 != x0)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 003_CSRRWI: !Subfeature + name: 003_CSRRWI + tag: VP_IP007_P003 + next_elt_id: 2 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F013_S003_I000 + description: "csrrwi rd, imm[4:0], csr\nrd = Zext([csr]); csr = Zext(imm[4:0])\n\ + If rd == x0 then CSR is not read." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rd registers are used\nAll\ + \ supported CSRs are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F013_S003_I001 + description: "csrrwi rd, imm[4:0], csr\nrd = Zext([csr]); csr = Zext(imm[4:0])\n\ + If rd == x0 then CSR is not read." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operand:\n\nNon-zero and zero imm[4:0] operands are used\n\ + All bits of imm[4:0] are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 004_CSRRSI: !Subfeature + name: 004_CSRRSI + tag: VP_IP007_P004 + next_elt_id: 2 + display_order: 4 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F013_S004_I000 + description: "csrrsi rd, imm[4:0], csr\nrd = Zext([csr]); csr = Zext(imm[4:0])\ + \ | csr\nNote that not all bits of csr will be writable." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rd registers are used\nAll\ + \ supported CSRs are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F013_S004_I001 + description: "csrrsi rd, imm[4:0], csr\nrd = Zext([csr]); csr = Zext(imm[4:0])\ + \ | csr\nNote that not all bits of csr will be writable." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operand:\n\nNon-zero and zero imm[4:0] operands are used\n\ + All bits of imm[4:0] are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 005_CSRRCI: !Subfeature + name: 005_CSRRCI + tag: VP_IP007_P005 + next_elt_id: 2 + display_order: 5 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F013_S005_I000 + description: "csrrs rd, imm[4:0], csr\nrd = Zext([csr]); csr = ~(Zext(imm[4:0]))\ + \ | csr\nNote that not all bits of csr will be writable." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Register operands:\n\nAll possible rd registers are used\nAll\ + \ supported CSRs are used" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F013_S005_I001 + description: "csrrs rd, imm[4:0], csr\nrd = Zext([csr]); csr = ~(Zext(imm[4:0]))\ + \ | csr\nNote that not all bits of csr will be writable." + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "Input operand:\n\nNon-zero and zero imm[4:0] operands are used\n\ + All bits of imm[4:0] are toggled" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/verif/docs/VerifPlans/ISA_RV32/VP_IP014.yml b/verif/docs/VerifPlans/ISA_RV32/VP_IP014.yml new file mode 100644 index 0000000000..12f3f86623 --- /dev/null +++ b/verif/docs/VerifPlans/ISA_RV32/VP_IP014.yml @@ -0,0 +1,32 @@ +!Feature +next_elt_id: 1 +name: RV32Zifencei Instruction-Fetch Fence +id: 14 +display_order: 14 +subfeatures: !!omap +- 000_FENCE.I: !Subfeature + name: 000_FENCE.I + tag: VP_IP006_P000 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F014_S000_I000 + description: "Fence.I instruction executed\nImplementation is core-specific" + reqt_doc: ./RISCV_Instructions.rst + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Fence.I instruction is executed + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: isacov.rv32zifencei_fence_i_cg + comments: '' +vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/verif/docs/VerifPlans/ISA_RV32/VP_IP015.yml b/verif/docs/VerifPlans/ISA_RV32/VP_IP015.yml new file mode 100644 index 0000000000..d07158928b --- /dev/null +++ b/verif/docs/VerifPlans/ISA_RV32/VP_IP015.yml @@ -0,0 +1,154 @@ +!Feature +next_elt_id: 4 +name: Instruction execution sequences +id: 15 +display_order: 15 +subfeatures: !!omap +- 000_Instruction Execution: !Subfeature + name: 000_Instruction Execution + tag: VP_ISA_RV32_F015_S000 + next_elt_id: 3 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F015_S000_I000 + description: All suported instructions for the core are executed + reqt_doc: ./RISCV_Instructions.rst + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Instruction is executed + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F015_S000_I001 + description: All suported instructions for the core are executed + reqt_doc: ./RISCV_Instructions.rst + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: All back-to-back supported instruction sequences are executed + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 001_Instruction Group Execution: !Subfeature + name: 001_Instruction Group Execution + tag: VP_ISA_RV32_F015_S001 + next_elt_id: 2 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F015_S001_I000 + description: All defined instruction groups for a core are executed + reqt_doc: ./RISCV_Instructions.rst + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: For the core under test, all instruction groups are executed + in the core + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F015_S001_I001 + description: All defined instruction groups are executed in sequence + reqt_doc: ./RISCV_Instructions.rst + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Depending on the length of the pipeline in the processor, sequence + chains of 2,3,or 4 instruction groups are checked for execution + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 002_GPR Hazard: !Subfeature + name: 002_GPR Hazard + tag: VP_ISA_RV32_F015_S002 + next_elt_id: 1 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F015_S002_I000 + description: An instruction reads from register that was written to in the + previous instruction + reqt_doc: ./RISCV_Instructions.rst + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: All instruction groups are tested across GPR hazards + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' +- 003_CSR Hazard: !Subfeature + name: 003_CSR Hazard + tag: VP_ISA_RV32_F015_S003 + next_elt_id: 2 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_ISA_RV32_F015_S003_I000 + description: CSR writes from the program are executed in conjunction with + all instruction groups + reqt_doc: ./RISCV_Instructions.rst + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "CSR write instruction attempts to write to a supported CSR\n\ + This does not include csr set or clear instructions where rs1 is x0 (bypassing\ + \ the write)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: 56 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_ISA_RV32_F015_S003_I001 + description: CSR writes from the program are executed in conjunction with + all instruction groups + reqt_doc: ./RISCV_Instructions.rst + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: Each instruction group is executed after each supported CSR is + written with a Zicsri write instructio + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 56 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/verif/docs/VerifPlans/ISA_RV32/runme.sh b/verif/docs/VerifPlans/ISA_RV32/runme.sh new file mode 100644 index 0000000000..5c581f0d53 --- /dev/null +++ b/verif/docs/VerifPlans/ISA_RV32/runme.sh @@ -0,0 +1,34 @@ +############################################################################# +# Copyright (C) 2022 Thales DIS France SAS +# +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0. +# +# Original Author: Zbigniew Chamski (zbigniew.chamski@thalesgroup.com) +############################################################################# +#!/bin/sh + +# Location of project-specific directories +ROOTDIR=`readlink -f $(dirname "${BASH_SOURCE[0]}")` + +# Set up platform location. It can be anywhere but should contain +# a valid `vp_config.py` file in `vptool` directory. +# Here we use the verification tree from the example directory. +export PLATFORM_TOP_DIR="$ROOTDIR" + +# Set the printable name for the project that will be used +# in the human-readable documentation. +export PROJECT_NAME="ISA RISC-V 32b" + +# Set the alphanumerical identifier of the project that +# will be used to construct file names etc. +export PROJECT_IDENT="ISA_RV32" + +# Set the destination directory of Markdown files for this project. +# Since it will be used by VPTOOL, it shall NOT be a relative path. +export MARKDOWN_OUTPUT_DIR=`readlink -f "$ROOTDIR/../source"` + +# Run VPTOOL overriding the default theme from Yaml config with 'winxpblue'. +# FIXME: Introduce a suitably named shell variable that points to the root +# directory of the tool set (TOOL_TOP etc.) +# FORNOW use a hardcoded relative path. +sh $ROOTDIR/../../../../tools/vptool/vptool.sh $* diff --git a/verif/docs/VerifPlans/MMU_SV32/VP_IP000.yml b/verif/docs/VerifPlans/MMU_SV32/VP_IP000.yml new file mode 100644 index 0000000000..7149784d8c --- /dev/null +++ b/verif/docs/VerifPlans/MMU_SV32/VP_IP000.yml @@ -0,0 +1,583 @@ +!Feature +next_elt_id: 16 +name: sv32 +id: 0 +display_order: 0 +subfeatures: !!omap +- 000_PMP permissions on Physical Address: !Subfeature + name: 000_PMP permissions on Physical Address + tag: VP_MMU_SV32_F000_S000 + next_elt_id: 2 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_MMU_SV32_F000_S000_I000 + description: "If PTE has valid and non-reserved RWX permissions, but the translated\ + \ Physical address (pte.ppn of leaf PTE + offset) does not have (r,w,x)\ + \ PMP permissions, then accessing the translated Physical address would\ + \ raise access fault exception.\nWhen satp.mode=sv32, and PTE has valid\ + \ and non-reserved RWX permissions then test the following in supervisor\ + \ and user privilege mode for level1 and level0 PTE.\n\n- Remove read PMP\ + \ permission of translated Physical Address in pmpcfg and test the read\ + \ acces.\n- Remvoe write PMP permission of translated Physical Address in\ + \ pmpcfg and test the write access.\n- Remove execute PMP permission of\ + \ translated Physical Address in pmpcfg and test the execute access." + reqt_doc: 'ISA Volume II: Privilege Architecture Version 20211203, Chapter + 3.7, 5.3.2' + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Access fault exception should be raised according to {x,r,w}\ + \ access type. Check that:\n- m/scause must contain the exception number\ + \ of:\n - instruction access fault for execute access.\n \ + \ - load page access for read access.\n - store/AMO access fault\ + \ for write access.\n- m/sepc must contain the virtual address of the instruction\ + \ at which the trap occurs." + pfc: 3 + test_type: 0 + cov_method: 0 + cores: 8 + coverage_loc: '' + comments: '' +- 001_PMP permissions on PTE: !Subfeature + name: 001_PMP permissions on PTE + tag: VP_MMU_SV32_F000_S001 + next_elt_id: 1 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_MMU_SV32_F000_S001_I000 + description: "If PTE does not have (r,w,x) PMP permissions, then accessing\ + \ it would raise access fault exception of the corresponding access type.\ + \ \nWhen satp.mode=sv32, then test the following in supervisor and user\ + \ privilege mode for level0 and level1 PTE.\n- Remove read PMP permission\ + \ of PTE address in pmpcfg and test the read acces.\n- Remvoe write PMP\ + \ permission of PTE address in pmpcfg and test the write access.\n- Remove\ + \ execute PMP permission of PTE address in pmpcfg and test the execute access." + reqt_doc: 'ISA Volume II: Privilege Architecture Version 20211203, Chapter + 3.7, 5.3.2' + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Access fault exception should be raised according to {x,r,w}\ + \ access type. Check that:\n- m/scause must contain the exception number\ + \ of:\n - instruction access fault for execute access.\n \ + \ - load page access for read access.\n - store/AMO access fault\ + \ for write access.\n- m/sepc must contain the virtual address of the instruction\ + \ at which the trap occurs." + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 8 + coverage_loc: '' + comments: '' +- 002_In-Valid Permission of PTE: !Subfeature + name: 002_In-Valid Permission of PTE + tag: VP_MMU_SV32_F000_S002 + next_elt_id: 1 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_MMU_SV32_F000_S002_I000 + description: "If PTE does not have Valid (pte.V=0) permission, then accessing\ + \ it would raise page fault exception of the corresponding access type.\ + \ \nWhen satp.mode=sv32 and PTE has (r,w,x) PMP permissions, then test the\ + \ following in supervisor and user privilege mode for level0 and level1\ + \ PTE.\n- Set PTE.V = 0 and test the read acces.\n- Set PTE.V = 0 and test\ + \ the write access.\n- Set PTE.V = 0 and test the execute access.\n\n* For\ + \ testing at level0, set all the pte perimssions at level1 to 0 except pte.v,\ + \ so that level1 points to level0.\n* Set pte.U=0 when test in Supervisor\ + \ mode and Set pte.U=1 when testing in user mode" + reqt_doc: 'ISA Volume II: Privilege Architecture Version 20211203, Chpter + 5.3.2' + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Page fault exception should be raised according to {x,r,w} access\ + \ type. Check that:\n- m/scause must contain the exception number of:\n\ + \ - instruction page fault for execute access.\n - load\ + \ page fault for read access.\n - store/AMO page fault for write\ + \ access.\n- m/sepc must contain the virtual address of the instruction\ + \ at which the trap occurs." + pfc: 3 + test_type: 0 + cov_method: 0 + cores: 8 + coverage_loc: '' + comments: '' +- 003_Reserved RWX permission encodings of PTE: !Subfeature + name: 003_Reserved RWX permission encodings of PTE + tag: VP_MMU_SV32_F000_S003 + next_elt_id: 1 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_MMU_SV32_F000_S003_I000 + description: "If PTE has reserved RWX encodings (pte.w=1 & pte.r=0), then\ + \ accessing it would raise page fault exception of the corresponding access\ + \ type. \nWhen satp.mode=sv32, PTE has (r,w,x) PMP permissions, and pte.v=1,\ + \ then test the following in supervisor and user privilege mode for level0\ + \ and level1 PTE.\n- Set pte.w=1 & pte.r=0 and test the read acces.\n- Set\ + \ pte.w=1 & pte.r=0 and test the write access.\n- Set pte.w=1 & pte.r=0\ + \ and test the execute access.\n\n* For testing at level0, set all the pte\ + \ perimssions at level1 to 0 except pte.v, so that level1 points to level0.\n\ + * Set pte.U=0 when test in Supervisor mode and Set pte.U=1 when testing\ + \ in user mode" + reqt_doc: 'ISA Volume II: Privilege Architecture Version 20211203, Chapter + 3.7, 5.3.1' + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Page fault exception should be raised according to {x,r,w} access\ + \ type. Check that:\n- m/scause must contain the exception number of:\n\ + \ - instruction page fault for execute access.\n - load\ + \ page fault for read access.\n - store/AMO page fault for write\ + \ access.\n- m/sepc must contain the virtual address of the instruction\ + \ at which the trap occurs." + pfc: 3 + test_type: 0 + cov_method: 0 + cores: 8 + coverage_loc: '' + comments: '' +- 004_Non-leaf PTE permission at level 0: !Subfeature + name: 004_Non-leaf PTE permission at level 0 + tag: VP_MMU_SV32_F000_S004 + next_elt_id: 1 + display_order: 4 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_MMU_SV32_F000_S004_I000 + description: "If PTE at level0 has non-leaf RWX permissions (pte.x=0 & pte.r=0),\ + \ then accessing it would raise page fault exception of the corresponding\ + \ access type. \nWhen satp.mode=sv32, PTE has (r,w,x) PMP permissions, and\ + \ pte.v=1, then test the following in supervisor and user privilege mode\ + \ for level0 PTE.\n- Set pte.x=0 & pte.r=0 & pte.w=0 and test the read acces.\n\ + - Set pte.x=0 & pte.r=0 & pte.w=0 and test the write access.\n- Set pte.x=0\ + \ & pte.r=0 & pte.w=0 and test the execute access.\n\n* For testing at level0,\ + \ set all the pte perimssions at level1 to 0 except pte.v, so that level1\ + \ points to level0.\n* Set pte.U=0 when test in Supervisor mode and Set\ + \ pte.U=1 when testing in user mode" + reqt_doc: 'ISA Volume II: Privilege Architecture Version 20211203, Chapter + 5.3.2' + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Page fault exception should be raised according to {x,r,w} access\ + \ type. Check that:\n- m/scause must contain the exception number of:\n\ + \ - instruction page fault for execute access.\n - load\ + \ page fault for read access.\n - store/AMO page fault for write\ + \ access.\n- m/sepc must contain the virtual address of the instruction\ + \ at which the trap occurs." + pfc: 3 + test_type: 0 + cov_method: 0 + cores: 8 + coverage_loc: '' + comments: '' +- 005_RWX access on S-mode pages in S-mode: !Subfeature + name: 005_RWX access on S-mode pages in S-mode + tag: VP_MMU_SV32_F000_S005 + next_elt_id: 1 + display_order: 5 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_MMU_SV32_F000_S005_I000 + description: "If PTE belongs to supervisor mode i.e. its U permission bit\ + \ is clear (pte.u = 0), then accessing that PTE in supervisor mode should\ + \ be successful if the corresponding (r,w,x) permission of PTE is granted.\ + \ Otherwise raise page fault exception of the corresponding access type.\n\ + When satp.mode=sv32, PTE has (r,w,x) PMP permissions, PTE has non-reserved\ + \ RWX encoding, pte.u=0 and pte.v=1, then test the following in supervisor\ + \ privilege mode for level 0 and level 1 PTE.\n- Test the read access for\ + \ both pte.r=1 and for pte.r=0\n- Test the write access for both pte.w=1\ + \ and for pte.w=0\n- Test the execute access for both pte.x=1 and for pte.x=0\n\ + \n* For testing at level0, set all the pte perimssions at level1 to 0 except\ + \ pte.v, so that level1 points to level0." + reqt_doc: 'ISA Volume II: Privilege Architecture Version 20211203, Chapter + 5.3.1' + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "RWX access should be successful if the corresponding permissions\ + \ are granted in the PTE. Check that load, store and execute works without\ + \ any page fault.\nPage fault exception should be raised according to (x,r,w)\ + \ access type if the corresponding (r,w,x) permissions are not granted in\ + \ the PTE. Check that:\n- m/scause must contain the exception number of:\n\ + \ - instruction page fault for execute.\n - load page fault\ + \ for read access.\n - store/AMO page fault for write access.\n\ + - m/sepc must contain the virtual address of the instruction at which the\ + \ trap occurs." + pfc: 3 + test_type: 0 + cov_method: 0 + cores: 8 + coverage_loc: '' + comments: '' +- 006_RWX access on S-mode pages in U-mode: !Subfeature + name: 006_RWX access on S-mode pages in U-mode + tag: VP_MMU_SV32_F000_S006 + next_elt_id: 1 + display_order: 6 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_MMU_SV32_F000_S006_I000 + description: "If PTE belongs to supervisor mode i.e. its U permission bit\ + \ is clear (pte.u = 0), then accessing that PTE in user mode would raise\ + \ page fault exception of the corresponding access type. \nWhen satp.mode=sv32,\ + \ PTE has (r,w,x) PMP permissions, PTE has non-reserved RWX encoding, and\ + \ pte.v=1, then test the following user privilege mode for level0 and level1\ + \ PTE.\n- Set pte.u=0 and test the read acces.\n- Set pte.u=0 and test the\ + \ write access.\n- Set pte.u=0 and test the execute access.\n\n* For testing\ + \ at level0, set all the pte perimssions at level1 to 0 except pte.v, so\ + \ that level1 points to level0." + reqt_doc: 'ISA Volume II: Privilege Architecture Version 20211203, Chapter + 5.3.2' + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Page fault exception should be raised according to {x,r,w} access\ + \ type. Check that:\n- m/scause must contain the exception number of instruction,\ + \ load, and store/AMO page fault for execute, read and write access type,\ + \ respectively.\n- m/sepc must contain the virtual address of the instruction\ + \ at which the trap occurs." + pfc: 3 + test_type: 0 + cov_method: 0 + cores: 8 + coverage_loc: '' + comments: '' +- 007_RWX access on U-mode pages in S-mode with mstatus.SUM unset: !Subfeature + name: 007_RWX access on U-mode pages in S-mode with mstatus.SUM unset + tag: VP_MMU_SV32_F000_S007 + next_elt_id: 1 + display_order: 7 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_MMU_SV32_F000_S007_I000 + description: "If PTE belongs to user mode i.e. its U permission bit is set\ + \ (pte.u = 1) and m/sstatus.SUM = 0, then accessing that PTE in supervisor\ + \ mode would raise page fault exception of the corresponding access type.\ + \ \nWhen satp.mode=sv32, PTE has (r,w,x) PMP permissions, PTE has non-reserved\ + \ RWX encoding, and pte.v=1, then test the following in supervisor mode\ + \ for level 0 and level 1 PTE.\n- Set pte.u=1 & s/mstatus.SUM = 0 and test\ + \ the read acces.\n- Set pte.u=1 & s/mstatus.SUM = 0 and test the write\ + \ access.\n- Set pte.u=1 & s/mstatus.SUM = 0 and test the execute access.\n\ + \n* For testing at level0, set all the pte perimssions at level1 to 0 except\ + \ pte.v, so that level1 points to level0." + reqt_doc: 'ISA Volume II: Privilege Architecture Version 20211203, Chapter + 3.1.6.3, 5.3.2' + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Page fault exception should be raised according to {x,r,w} access\ + \ type. Check that:\n- m/scause must contain the exception number of:\n\ + \ - instruction page fault for execute access.\n - load\ + \ page fault for read access.\n - store/AMO page fault for write\ + \ access.\n- m/sepc must contain the virtual address of the instruction\ + \ at which the trap occurs." + pfc: 3 + test_type: 0 + cov_method: 0 + cores: 8 + coverage_loc: '' + comments: '' +- 008_RWX access on U-mode pages in S-mode with mstatus.SUM set: !Subfeature + name: 008_RWX access on U-mode pages in S-mode with mstatus.SUM set + tag: VP_MMU_SV32_F000_S008 + next_elt_id: 1 + display_order: 8 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_MMU_SV32_F000_S008_I000 + description: "If PTE belongs to user mode i.e. its U permission bit is set\ + \ (pte.u = 1) and m/sstatus.SUM = 1, then RW access to that PTE in supervisor\ + \ mode would be successful but eXecute access would raise instruction page\ + \ fault exception in s-mode.\nWhen satp.mode=sv32, PTE has (r,w,x) PMP permissions,\ + \ PTE has non-reserved RWX encoding, and pte.v=1, then test the following\ + \ in supervisor mode for level0 and level1 PTE.\n- Set pte.r=1 & pte.u=1\ + \ & s/mstatus.SUM = 1 and test the read acces.\n- Set pte.w=1 & pte.u=1\ + \ & s/mstatus.SUM = 1 and test the write access.\n- Set pte.x=1 & pte.u=1\ + \ & s/mstatus.SUM = 1 and test the execute access.\n\n* For testing at level0,\ + \ set all the pte perimssions at level1 to 0 except pte.v, so that level1\ + \ points to level0." + reqt_doc: 'ISA Volume II: Privilege Architecture Version 20211203, Chapter + 3.1.6.3, 5.3.2' + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Read and Write access to the PTE should be successful. So, check\ + \ that the load and store works without page fault and expected data is\ + \ stored to and loaded from the memory, repectively.\n\nExecute access should\ + \ raise instruction page fault. Check that:\n- m/scause must contain the\ + \ exception number of instruction instruction access fault. \n- m/sepc must\ + \ contain the virtual address of the instruction at which the trap occurs." + pfc: 3 + test_type: 0 + cov_method: 0 + cores: 8 + coverage_loc: '' + comments: '' +- 009_RWX access on U-mode pages in U-mode: !Subfeature + name: 009_RWX access on U-mode pages in U-mode + tag: VP_MMU_SV32_F000_S009 + next_elt_id: 1 + display_order: 9 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_MMU_SV32_F000_S009_I000 + description: "If PTE belongs to user mode i.e. its U permission bit is set\ + \ (pte.u = 1), then accessing that PTE in user mode should be successful\ + \ if the corresponding (r,w,x) permission of PTE is granted. Otherwise raise\ + \ page fault exception of the corresponding access type.\nWhen satp.mode=sv32,\ + \ PTE has (r,w,x) PMP permissions, PTE has non-reserved RWX encoding, pte.u=1\ + \ and pte.v=1, then test the following in user privilege mode for level0\ + \ and level1 PTE.\n- Test the read access for both pte.r=1 and for pte.r=0\n\ + - Test the write access for both pte.w=1 and for pte.w=0\n- Test the execute\ + \ access for both pte.x=1 and for pte.x=0\n\n* For testing at level0, set\ + \ all the pte perimssions at level1 to 0 except pte.v, so that level1 points\ + \ to level0." + reqt_doc: 'ISA Volume II: Privilege Architecture Version 20211203, Chapter + 5.3.2' + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "RWX access should be successful if the corresponding permissions\ + \ are granted in the PTE. Check that load, store and execute works without\ + \ any page fault.\n\nPage fault exception should be raised if the corresponding\ + \ rwx PTE permissions are not granted. Check that:\n- m/scause must contain\ + \ the exception number of:\n - instruction page fault for execute\ + \ access.\n - load page fault for read access.\n - store/AMO\ + \ page fault for write access.\n- m/sepc must contain the virtual address\ + \ of the instruction at which the trap occurs." + pfc: 3 + test_type: 0 + cov_method: 0 + cores: 8 + coverage_loc: '' + comments: '' +- 010_Make Executable Page Readable with s/mstatus.MXR unset: !Subfeature + name: 010_Make Executable Page Readable with s/mstatus.MXR unset + tag: VP_MMU_SV32_F000_S010 + next_elt_id: 1 + display_order: 10 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_MMU_SV32_F000_S010_I000 + description: "If PTE has only execute permission (pte.x = 1) and s/mstatus.MXR=0,\ + \ then read access on that PTE should raise load page fault exception.\n\ + When satp.mode=sv32, PTE has (r,w,x) PMP permissions, and pte.v=1, then\ + \ test the following in supervisor and user privilege mode for level0 and\ + \ level1 PTE.\n- Set pte.r=0 & pte.w=0 & pte.x=1 & s/mstatus.MXR=0 and test\ + \ the read acces.\n\n* For testing at level0, set all the pte perimssions\ + \ at level1 to 0 except pte.v, so that level1 points to level0.\n* Set pte.U=0\ + \ when test in Supervisor mode and Set pte.U=1 when testing in user mode" + reqt_doc: 'ISA Volume II: Privilege Architecture Version 20211203, Chapter + 3.1.6.3, 5.3.2' + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Load Page fault exception should be raised. Check that:\n- m/scause\ + \ must contain the exception number of load page fault for read access.\n\ + - m/sepc must contain the virtual address of the instruction at which the\ + \ trap occurs." + pfc: 2 + test_type: 0 + cov_method: 0 + cores: 8 + coverage_loc: '' + comments: '' +- 011_Make Executable Page Readable with s/mstatus.MXR set: !Subfeature + name: 011_Make Executable Page Readable with s/mstatus.MXR set + tag: VP_MMU_SV32_F000_S011 + next_elt_id: 1 + display_order: 11 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_MMU_SV32_F000_S011_I000 + description: "If PTE has only execute permission (pte.x = 1) and s/mstatus.MXR=1,\ + \ then read access on that PTE should be successful without having explicit\ + \ read permission (pte.r=0).\nWhen satp.mode=sv32, PTE has (r,w,x) PMP permissions,\ + \ and pte.v=1, then test the following in supervisor and user privilege\ + \ mode for level0 and level1 PTE.\n- Set pte.r=0 & pte.w=0 & pte.x=1 & s/mstatus.MXR=1\ + \ and test the read acces.\n\n* For testing at level0, set all the pte perimssions\ + \ at level1 to 0 except pte.v, so that level1 points to level0.\n* Set pte.U=0\ + \ when test in Supervisor mode and Set pte.U=1 when testing in user mode" + reqt_doc: 'ISA Volume II: Privilege Architecture Version 20211203, Chapter + 3.1.6.3 ,5.3.2' + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Read access to the PTE should be successful. Check that load + instructions works without any load page fault exception and expected data + is loaded from the memory. + pfc: 3 + test_type: 0 + cov_method: 0 + cores: 8 + coverage_loc: '' + comments: '' +- '012_Global mapping ': !Subfeature + name: '012_Global mapping ' + tag: VP_MMU_SV32_F000_S012 + next_elt_id: 1 + display_order: 12 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_MMU_SV32_F000_S012_I000 + description: For two different processes having same Virtual address and different + satp.ASID, maps to same Physical address, and the pte.G is set; then one + process will go through the address translation and update the TLB while + the 2nd process will not go through the translation if pte.G is set and + Physical address exist in TLB. + reqt_doc: 'ISA Volume II: Privilege Architecture Version 20211203, Chapter + 5.3.1' + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Show that two different processes having same VA to PA mapping + can access the translated PA from TLB (if exist) and not go through complete + translation. + pfc: 3 + test_type: 0 + cov_method: 0 + cores: 8 + coverage_loc: '' + comments: '' +- 013_Access bit implementation: !Subfeature + name: 013_Access bit implementation + tag: VP_MMU_SV32_F000_S013 + next_elt_id: 1 + display_order: 13 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_MMU_SV32_F000_S013_I000 + description: "If implementation does not sets the pte.A on accessing the PTE,\ + \ and PTE has pte.A=0, then accessing it would raise page fault exception\ + \ of the corresponding access type. \nWhen satp.mode=sv32, PTE has (r,w,x)\ + \ PMP permissions, and pte.v=1, then test the following in supervisor and\ + \ user privilege mode for level0 and level1 PTE. Execute sfence.vma before\ + \ accessign the PTE.\n- Set pte.r=1 & pte.a=0 and test the read acces. \n\ + - Set pte.w=1 & pte.a=0 and test the write access.\n- Set pte.x=1 & pte.a=0\ + \ and test the execute access.\n\n* For testing at level0, set all the pte\ + \ perimssions at level1 to 0 except pte.v, so that level1 points to level0.\n\ + * Set pte.U=0 when test in Supervisor mode and Set pte.U=1 when testing\ + \ in user mode." + reqt_doc: 'ISA Volume II: Privilege Architecture Version 20211203, Chapter + 5.3.1, 5.3.2' + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Page fault exception should be raised according to {x,r,w} access\ + \ type. Check that:\n- m/scause must contain the exception number of:\n\ + \ - instruction page fault for execute access.\n - load\ + \ page fault for read access.\n - store/AMO page fault for write\ + \ access.\n- m/sepc must contain the virtual address of the instruction\ + \ at which the trap occurs." + pfc: 3 + test_type: 0 + cov_method: 0 + cores: 8 + coverage_loc: '' + comments: '' +- 014_Dirty bit Implementation: !Subfeature + name: 014_Dirty bit Implementation + tag: VP_MMU_SV32_F000_S014 + next_elt_id: 1 + display_order: 14 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_MMU_SV32_F000_S014_I000 + description: "If implementation does not sets the pte.D when PTE is written,\ + \ and PTE has pte.D=0, then attempting to store on that PTE would raise\ + \ Store/AMO page fault exception.\nWhen satp.mode=sv32, PTE has (r,w,x)\ + \ PMP permissions, pte.a=1 and pte.v=1, then test the following in supervisor\ + \ and user privilege mode for level0 and level1 PTE. Execute sfence.vma\ + \ before accessign the PTE.\n- Set pte.w=1 & pte.d=0 and test the write\ + \ access.\n\n* For testing at level0, set all the pte perimssions at level1\ + \ to 0 except pte.v, so that level1 points to level0.\n* Set pte.U=0 when\ + \ test in Supervisor mode and Set pte.U=1 when testing in user mode." + reqt_doc: 'ISA Volume II: Privilege Architecture Version 20211203, Chapter + 5.3.1, 5.3.2' + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Store/AMO page fault exception should be raised. Check that:\n\ + - m/scause must contain the exception number of store/AMO page fault for\ + \ write access.\n- m/sepc must contain the virtual address of the instruction\ + \ at which the trap occurs." + pfc: 3 + test_type: 0 + cov_method: 0 + cores: 8 + coverage_loc: '' + comments: '' +- 015_Misaligned Superpage: !Subfeature + name: 015_Misaligned Superpage + tag: VP_MMU_SV32_F000_S015 + next_elt_id: 1 + display_order: 15 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_MMU_SV32_F000_S015_I000 + description: "If PTE at level1 is leaf PTE (superpage) and its pte.ppn[0]=0,\ + \ then it is a misaligned superpage and accessing that PTE would raise page\ + \ fault exception of the corresponding access type.\nWhen satp.mode=sv32,\ + \ PTE has (r,w,x) PMP permissions, PTE has non-reserved RWX encodings, (pte.r\ + \ | pte.x)=1, and pte.v=1, then test the following in supervisor and user\ + \ privilege mode for level1 PTE.\n-set pte.ppn[0]=0 and test for read, write\ + \ and execute access.\n\n* Set pte.U=0 when test in Supervisor mode and\ + \ Set pte.U=1 when testing in user mode." + reqt_doc: 'ISA Volume II: Privilege Architecture Version 20211203, Chapter + 5.3.1, 5.3.2' + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Page fault exception should be raised according to {x,r,w} access\ + \ type. Check that:\n- m/scause must contain the exception number of:\n\ + \ - instruction page fault for execute access.\n - load\ + \ page fault for read access.\n - store/AMO page fault for write\ + \ access.\n- m/sepc must contain the virtual address of the instruction\ + \ at which the trap occurs." + pfc: 3 + test_type: 0 + cov_method: 0 + cores: 8 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/verif/docs/VerifPlans/MMU_SV32/VP_IP001.yml b/verif/docs/VerifPlans/MMU_SV32/VP_IP001.yml new file mode 100644 index 0000000000..1fb582c9f8 --- /dev/null +++ b/verif/docs/VerifPlans/MMU_SV32/VP_IP001.yml @@ -0,0 +1,36 @@ +!Feature +next_elt_id: 1 +name: mstatus.TVM +id: 1 +display_order: 1 +subfeatures: !!omap +- 000_Accessing satp and sfence.vma CSRs: !Subfeature + name: 000_Accessing satp and sfence.vma CSRs + tag: VP_MMU_SV32_F001_S000 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_MMU_SV32_F001_S000_I000 + description: If mstatus.TVM=1, read and write access to the satp and sfence.vma + will raise illegal instruction exception in S-mode. + reqt_doc: 'ISA Volume II: Privilege Architecture Version 20211203, Chapter + 3.1.6.5' + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: "Show that:\n- s/mcause contains the exception number of illegal\ + \ instruction exception.\n- m/sepc must contain the virtual address of the\ + \ instruction at which the trap occurs." + pfc: 3 + test_type: 0 + cov_method: 0 + cores: 8 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/verif/docs/VerifPlans/MMU_SV32/VP_IP002.yml b/verif/docs/VerifPlans/MMU_SV32/VP_IP002.yml new file mode 100644 index 0000000000..6ae361a877 --- /dev/null +++ b/verif/docs/VerifPlans/MMU_SV32/VP_IP002.yml @@ -0,0 +1,110 @@ +!Feature +next_elt_id: 4 +name: satp +id: 2 +display_order: 2 +subfeatures: !!omap +- 000_access permission: !Subfeature + name: 000_access permission + tag: VP_MMU_SV32_F002_S000 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_MMU_SV32_F002_S000_I000 + description: Access satp in M, S, and U mode using csrrw, csrrc, csrrs + reqt_doc: 'ISA Volume II: Privilege Architecture Version 20211203, Chapter + 5.1.11' + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Show that satp is only accessible in M and S mode and illegal + instruction exception is generated when accessed in lower privilege mode + pfc: 3 + test_type: 0 + cov_method: 0 + cores: 8 + coverage_loc: '' + comments: '' +- 001_MODE field: !Subfeature + name: 001_MODE field + tag: VP_MMU_SV32_F002_S001 + next_elt_id: 2 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_MMU_SV32_F002_S001_I000 + description: Allows to select different schemes of address translation. Writes + to satp are ignored when unsupported mode is selected. + reqt_doc: 'ISA Volume II: Privilege Architecture Version 20211203, Chapter + 5.1.11' + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Show that supported address translation scheme i.e sv32 is selected + by writing satp.mode=sv32 and reading back the satp + pfc: 3 + test_type: 0 + cov_method: 0 + cores: 8 + coverage_loc: '' + comments: '' +- 002_MODE=Bare: !Subfeature + name: 002_MODE=Bare + tag: VP_MMU_SV32_F002_S002 + next_elt_id: 1 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_MMU_SV32_F002_S002_I000 + description: Selecting MODE=Bare the remaining feild should be zero. Other + encoding for remaining feild in satp is reserved + reqt_doc: 'ISA Volume II: Privilege Architecture Version 20211203, Chapter + 5.1.11' + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Show wirting {zero, non-zero} value to satp when mode=bare the + behaviour follows the design implemention + pfc: 3 + test_type: 0 + cov_method: 0 + cores: 8 + coverage_loc: '' + comments: '' +- 003_ASIDLEN: !Subfeature + name: 003_ASIDLEN + tag: VP_MMU_SV32_F002_S003 + next_elt_id: 1 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_MMU_SV32_F002_S003_I000 + description: ASIDLEN is the number of ASID bits implemented. MAXASID bits + for sv32 is 9 + reqt_doc: 'ISA Volume II: Privilege Architecture Version 20211203, Chapter + 5.1.11' + ref_mode: '' + ref_page: '' + ref_section: '' + ref_viewer: '' + verif_goals: Determine by writing one to every bit position in the ASID field, + then reading back the value in satp to see which bit positions in the ASID + field hold a one. Show that ASIDLEN is equal to the expected ASIDLEN + pfc: 3 + test_type: 0 + cov_method: 0 + cores: 8 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/verif/docs/VerifPlans/MMU_SV32/runme.sh b/verif/docs/VerifPlans/MMU_SV32/runme.sh new file mode 100755 index 0000000000..a5c8b8c70c --- /dev/null +++ b/verif/docs/VerifPlans/MMU_SV32/runme.sh @@ -0,0 +1,34 @@ +############################################################################# +# Copyright (C) 2022 Thales DIS France SAS +# +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0. +# +# Original Author: Zbigniew Chamski (zbigniew.chamski@thalesgroup.com) +############################################################################# +#!/bin/sh + +# Location of project-specific directories +ROOTDIR=`readlink -f $(dirname "${BASH_SOURCE[0]}")` + +# Set up platform location. It can be anywhere but should contain +# a valid `vp_config.py` file in `vptool` directory. +# Here we use the verification tree from the example directory. +export PLATFORM_TOP_DIR="$ROOTDIR" + +# Set the printable name for the project that will be used +# in the human-readable documentation. +export PROJECT_NAME="MMU_SV32" + +# Set the alphanumerical identifier of the project that +# will be used to construct file names etc. +export PROJECT_IDENT="MMU_SV32" + +# Set the destination directory of Markdown files for this project. +# Since it will be used by VPTOOL, it shall NOT be a relative path. +export MARKDOWN_OUTPUT_DIR=`readlink -f "$ROOTDIR/../source"` + +# Run VPTOOL overriding the default theme from Yaml config with 'winxpblue'. +# FIXME: Introduce a suitably named shell variable that points to the root +# directory of the tool set (TOOL_TOP etc.) +# FORNOW use a hardcoded relative path. +python3 $ROOTDIR/../../../../tools/vptool/vptool/vp.py $* diff --git a/verif/docs/VerifPlans/Makefile b/verif/docs/VerifPlans/Makefile new file mode 100644 index 0000000000..c1c156f05a --- /dev/null +++ b/verif/docs/VerifPlans/Makefile @@ -0,0 +1,38 @@ +# +# Copyright (c) 2020 OpenHW Group +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://solderpad.org/licenses/ +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# +############################################################################### +# +# Minimal makefile for Sphinx documentation +# + +# You can set these variables from the command line. +SPHINXOPTS = +SPHINXBUILD = sphinx-build +SOURCEDIR = source +BUILDDIR = build + +# Put it first so that "make" without argument is like "make help". +help: + @$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) + +.PHONY: help Makefile + +# Catch-all target: route all unknown targets to Sphinx using the new +# "make mode" option. $(O) is meant as a shortcut for $(SPHINXOPTS). +%: Makefile + @$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) diff --git a/verif/docs/VerifPlans/VPTOOL-VerifPlan-HOWTO.md b/verif/docs/VerifPlans/VPTOOL-VerifPlan-HOWTO.md new file mode 100644 index 0000000000..6fdfbf3c0a --- /dev/null +++ b/verif/docs/VerifPlans/VPTOOL-VerifPlan-HOWTO.md @@ -0,0 +1,154 @@ +[//]: # (Copyright 2022 Thales Silicon Security) +[//]: # (SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0.) +[//]: # (Original Author: Zbigniew CHAMSKI <zbigniew.chamski@thalesgroup.com>) + +# HOWTO use VPTOOL to edit and export DV plans + +## Introduction + +New features pertaining to Verification Plan exports are currently being developed and tested within the CVA6 ecosystem. They will be integrated in the `master` branch at a later date. Hence, the instructions below assume that you are working on the `cva6/dev` branch of the `core-v-verif` repository, or on a branch derived from it. + +## Requirements for Markdown output generation + +* VPTOOL (included in the `core-v-verif` distribution under `tools/vptool`) with its dependencies installed, as per instructions in file `core-v-verif/tools/vptool/VPTOOL-readme.txt`. +* Python packages related to the processing of markdown files (listed in file `requirements.txt`). +* Verification Plan directories, one per subsystem. + +## Installation + +### Step 1: Install the required packages + +To generate DV plans in the form of viewable HTML/PDF/ePub documents, `VPTOOL` uses the `Sphinx` documentation generator. +Furthermore, to generate PDF and ePub output formats, VPTOOL relies on the `LaTeX` typesetting program with the `latexmk` wrapper add-on. + +#### Semi-automated installation + +If your system can access a Python package repository (either on the Internet, or local to your site), the Bash shell script `install-prerequisites.sh` will install the necessary Python packages and check for the availability of basic LaTeX-related commands. Run it with +``` +. install-prerequisites.sh +``` + +If LaTeX distribution or the `latexmk` wrapper is missing, the script will inform your about the steps to follow. *Please take note that these steps may require superuser privileges.* + +#### Manual installation +If your system has access to the internet, you can install the packages using your preferred Python installer. Under Bash shell, you can do this using PIP and the command + +``` + for REQT in `cat requirements.txt` ; do python3 -m pip install $REQT ; done +``` + +Otherwise, up-to-date versions of the packages listed in file `requirements.txt` and their dependencies need to be installed manually. + +### Step 2: Configure per-subsystem databases + +Currently, the verification plan for each subsystem is stored in a separate VPTOOL database. The per-subsystem configuration consists of the following information: + +* shell variable `PLATFORM_TOP_DIR` which indicates the root location of the database files. It is recommended to use an absolute path; a good choice is the *effective* location of the database as returned by `dirname $(readlink -f <path_to_vp_config.py>)`. +* shell variable `PROJECT_NAME` which specifies the human-friendly name of the subsystem (a free-form string containing no newline characters). The value of this variable will serve as the name of the subsystem in the generated documentation. +* shell variable `PROJECT_IDENT` which specifies the file name stem to use in Markdown processing (no path separators, spaces nor special characters allowed). This string will be used to construct the name of the output Markdown file, and must be unique across all subsystems of a design. +* shell variable `MARKDOWN_OUTPUT_DIR` which designates the directory in which to place the generated per-subsystem Markdown files. The Markdown rendering tools that produce human-friendly output (e.g. HTML) for CVA6 Verification Plans are configured to take Markdown input from directory `core-v-verif/cva6/docs/VerifPlans/source`. It is recommended to use an absolute path; a good choice is the *effective* location of the database (`readlink -f $PLATFORM_TOP_DIR`) suffixed with the *relative* path to `source` as this avoids hardcoded absolute paths.) + +To ensure consistent configurations between consecutive runs of VPTOOL on a given database, it is recommended to set these variables within a shell script (see `core-v-verif/cva6/docs/VerifPlans/FRONTEND/runme.sh` for an example.) + +Typically, creating a new database could be as simple as: + +* Create a directory for a new per-subsystem DV plan, say `cva6/docs/VerifPlans/NEW_ARCH_VARIANT/NEW_SUBSYSTEM`. +* Copy existing `vp_config.py` and `runme.sh` files from an existing per-subsystem Verification Plan directory to the newly created directory. +* Edit the `runme.sh` in the new directory to adjust the vaue of variable `PROJECT_NAME`, `PROJECT_IDENT` and `MARKDOWN_OUTPUT_DIR`. +* Using the adjusted `runme.sh` script, launch VPTOOL to interactively create the new database: + ``` + . cva6/docs/VerifPlans/NEW_ARCH_VARIANT/NEW_SUBSYSTEM/runme.sh + ``` + +### Step 3: Provide initial content of the database(s) + +In VPTOOL, modify the Verification Plan database of the new subsystem as appropriate. + +## Generation of DV plan documents + +### Step 1: Export database content to Markdown document(s) + +Currently, the generation of Markdown output is directly coupled to the action of saving database content of a project. When saving a database, VPTOOL will also create a Markdown file containing a human readable version of the DV plan in file `dvplan_${PROJECT_IDENT}.md` in directory designated by the shell variable `MARKDOWN_OUTPUT_DIR` set in the `runme.sh` script of the given subsystem. + +After editing the databases for projects `FRONTEND` and `NEW_ARCH_VARIANT/NEW_SUBSYSTEM` the directory layout will thus be: + +* `cva6/docs/VerifPlans` + * `FRONTEND` + * `runme.sh` : wrapper script + * `vp_config.py` : database configuration file for subsystem `FRONTEND` + * `VP_IPnnn.pck` : Verification Plan database files for subsystem `FRONTEND` + * ... + * `NEW_ARCH_VARIANT` + * `NEW_SUBSYSTEM` + * `runme.sh` : wrapper script for `NEW_SUBSYSTEM` (Let's assume that it sets `PROJECT_NAME="New Subsystem"` and `PROJECT_IDENT="NEW_SUBSYS"`.) + * `vp_config.py` : database configuration file for `NEW_SUBSYSTEM` + * `VP_IPnnn.pck` : files of the Verification Plan database for `NEW_SUBSYSTEM` + * ... + * `source` + * `conf.py` : configuration file for document generator + * `dvplan_FRONTEND.md` : Markdown version of verification plan for that `PROJECT_IDENT` for + * `dvplan_NEW_SUBSYS.md` : Markdown version of `NEW_SUBSYSTEM` verification plan (since the wrapper script set `PROJECT_IDENT` to `"NEW_SUBSYS"`.) + * `dvplan_intro.rst` : Markdown version of the introduction to the overall verification plan + * `dvplan_index.rst` : Markdown version of the overall verification plan document. + +### Step 2: Generate final DV plan documents + +In order to include the newly generated `NEW_SUBSYSTEM` verification plan into the overall DV Plan document, the file `source/dvplan_index.rst` needs to be modified so that it includes `dvplan_NEW_SUBSYS.md`. This is achieved by simply adding the name of the new DV plan Markdown document (without the `.md` extension) at the appropriate location in the document structure, e.g. after the line containing 'dvplan_FRONTEND`. + +Once the index file has been adjusted, the final document can generated in a variety of formats by invoking `make` in the directory `core-v-verif/cva6/docs/VerifPlans` with the desired output format as argument. The list of formats supported by your local Sphinx installation can be obtained by invoking `make` without arguments: + +``` +me@ariane:cva6/docs/VerifPlans$ make +Sphinx v1.8.4 +Please use `make target' where target is one of + html to make standalone HTML files + dirhtml to make HTML files named index.html in directories + singlehtml to make a single large HTML file + pickle to make pickle files + json to make JSON files + htmlhelp to make HTML files and an HTML help project + qthelp to make HTML files and a qthelp project + devhelp to make HTML files and a Devhelp project + epub to make an epub + latex to make LaTeX files, you can set PAPER=a4 or PAPER=letter + latexpdf to make LaTeX and PDF files (default pdflatex) + latexpdfja to make LaTeX files and run them through platex/dvipdfmx + text to make text files + man to make manual pages + texinfo to make Texinfo files + info to make Texinfo files and run them through makeinfo + gettext to make PO message catalogs + changes to make an overview of all changed/added/deprecated items + xml to make Docutils-native XML files + pseudoxml to make pseudoxml-XML files for display purposes + linkcheck to check all external links for integrity + doctest to run all doctests embedded in the documentation (if enabled) + coverage to run coverage check of the documentation (if enabled) +me@ariane:cva6/docs/VerifPlans$ +``` + +The recommended target during the development of the verification plans is `singlehtml` as it offers the shortest turnaround time and interactive output with good readability. Also, some of the other formatting targets may depend on the availability of additional tools that may or may not be installed (or even installable) on your system. + +``` +me@ariane:cva6/docs/VerifPlans$ make singlehtml +Running Sphinx v1.8.4 +loading translations [en]... done +loading pickled environment... done +building [mo]: targets for 0 po files that are out of date +building [singlehtml]: all documents +updating environment: 0 added, 0 changed, 0 removed +looking for now-outdated files... none found +preparing documents... done +assembling single document... dvplan_intro dvplan_FRONTEND dvplan_NEW_SUBSYS +writing... done +writing additional files... +copying static files... done +copying extra files... done +dumping object inventory... done +build succeeded. + +The HTML page is in build/singlehtml. +me@ariane:cva6/docs/VerifPlans$ +``` + +The resulting document can be viewed by pointing your browser at the file `core-v-verif/cva6/docs/VerifPlans/build/singlehtml/index.html`. diff --git a/verif/docs/VerifPlans/csr_access/VP_IP000.yml b/verif/docs/VerifPlans/csr_access/VP_IP000.yml new file mode 100644 index 0000000000..47fd5143dc --- /dev/null +++ b/verif/docs/VerifPlans/csr_access/VP_IP000.yml @@ -0,0 +1,71 @@ +!Feature +next_elt_id: 1 +name: machineScratch(MSCRATCH) +id: 0 +display_order: 0 +subfeatures: !!omap +- 000_MSCRATCH: !Subfeature + name: 000_MSCRATCH + tag: VP_csr-test-ident_F000_S000 + next_elt_id: 3 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_csr-test-ident_F000_S000_I000 + description: "To verify the Power-on Reset value for MSCRATCH CSR.\n \nAddress\ + \ Offset : 0x340\nWidth (bits) : 32\nAccess Type : RW\nReset Value : 0x00000000\n\ + priviliged mode : Machine" + reqt_doc: riscv-privileged-20211203 + ref_mode: section + ref_page: '' + ref_section: 3.1.13 + ref_viewer: firefox + verif_goals: Read MSCRATCH CSR to check default POR value that should be equal + to 0x00000000. + pfc: 3 + test_type: 1 + cov_method: 10 + cores: 8 + coverage_loc: '' + comments: '' + - '001': !VerifItem + name: '001' + tag: VP_csr-test-ident_F000_S000_I001 + description: Verifying R/W access of a MSCRATCH CSR by writing random valid + data like 0xFFFFFFFF, 0XA5A5A5A5, 0X5A5A5A5A ... and Read back CSR values + to check correctness. + reqt_doc: riscv-privileged-20211203 + ref_mode: section + ref_page: '' + ref_section: 3.1.13 + ref_viewer: firefox + verif_goals: The read values of MSCRATCH CSR should matches with written random + data values. + pfc: -1 + test_type: -1 + cov_method: -1 + cores: 8 + coverage_loc: '' + comments: '' + - '002': !VerifItem + name: '002' + tag: VP_csr-test-ident_F000_S000_I002 + description: Verifying MSCRATCH CSR in other privilige modes(supervisor, user) + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: It is expected that accessing Machine Mode CSRs in lower privilige + modes will raise an exception. + pfc: 3 + test_type: 1 + cov_method: 10 + cores: 8 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: b0efb3ae3f9057b71a577d43c2b77f1cfb2ef82f $' +io_fmt_gitrev: '$Id: 7ee5d68801f5498a957bcbe23fcad87817a364c5 $' +config_gitrev: '$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $' +ymlcfg_gitrev: '$Id: 286c689bd48b7a58f9a37754267895cffef1270c $' diff --git a/verif/docs/VerifPlans/csr_access/cva6_csr.rst b/verif/docs/VerifPlans/csr_access/cva6_csr.rst new file mode 100644 index 0000000000..0d7e8ce291 --- /dev/null +++ b/verif/docs/VerifPlans/csr_access/cva6_csr.rst @@ -0,0 +1,2653 @@ +REGISTERS CSR CV32A6 +=================== + +Floating-Point Accrued Exceptions Register +-------------------------- +AddressOffset: 'h1 +-------------------------- +Description: +-------------------------- +The fields within the ``fcsr`` can also be accessed individually through different CSR addresses, and separate assembler pseudoinstructions are defined for these accesses. The FRRM instruction reads the Rounding Mode field ``frm`` and copies it into the least-significant three bits of integer register *rd*, with zero in all other bits. FSRM swaps the value in frm by copying the original value into integer register *rd*, and then writing a new value obtained from the three least-significant bits of integer register *rs1* into ``frm``. FRFLAGS and FSFLAGS are defined analogously for the Accrued Exception Flags field ``fflags``. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 4 + - NV + - Invalid operation + - read-write + - The accrued exception flags indicate the exception conditions that have arisen on any floating\-point arithmetic instruction since the field was last reset by software\. The base RISC\-V ISA does not support generating a trap on the setting of a floating\-point exception flag\. + * - 3 + - DZ + - Divide by zero + - read-write + - The accrued exception flags indicate the exception conditions that have arisen on any floating\-point arithmetic instruction since the field was last reset by software\. The base RISC\-V ISA does not support generating a trap on the setting of a floating\-point exception flag\. + * - 2 + - OF + - Overflow + - read-write + - The accrued exception flags indicate the exception conditions that have arisen on any floating\-point arithmetic instruction since the field was last reset by software\. The base RISC\-V ISA does not support generating a trap on the setting of a floating\-point exception flag\. + * - 1 + - UF + - Underflow + - read-write + - The accrued exception flags indicate the exception conditions that have arisen on any floating\-point arithmetic instruction since the field was last reset by software\. The base RISC\-V ISA does not support generating a trap on the setting of a floating\-point exception flag\. + * - 0 + - NX + - Inexact + - read-write + - The accrued exception flags indicate the exception conditions that have arisen on any floating\-point arithmetic instruction since the field was last reset by software\. The base RISC\-V ISA does not support generating a trap on the setting of a floating\-point exception flag\. + +Floating-Point Dynamic Rounding Mode Register +-------------------------- +AddressOffset: 'h2 +-------------------------- +Description: +-------------------------- +The fields within the ``fcsr`` can also be accessed individually through different CSR addresses, and separate assembler pseudoinstructions are defined for these accesses. The FRRM instruction reads the Rounding Mode field ``frm`` and copies it into the least-significant three bits of integer register *rd*, with zero in all other bits. FSRM swaps the value in frm by copying the original value into integer register *rd*, and then writing a new value obtained from the three least-significant bits of integer register *rs1* into ``frm``. FRFLAGS and FSFLAGS are defined analogously for the Accrued Exception Flags field ``fflags``. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 2:0 + - FRM + - Floating-point rounding mode + - read-write + - The fields within the ``fcsr`` can also be accessed individually through different CSR addresses, and separate assembler pseudoinstructions are defined for these accesses\. The FRRM instruction reads the Rounding Mode field ``frm`` and copies it into the least\-significant three bits of integer register \*rd\*, with zero in all other bits\. FSRM swaps the value in frm by copying the original value into integer register \*rd\*, and then writing a new value obtained from the three least\-significant bits of integer register \*rs1\* into ``frm``\. FRFLAGS and FSFLAGS are defined analogously for the Accrued Exception Flags field ``fflags``\. ``Enumerated Values``( "RNE" :0)( "RTZ" :1)( "RDN" :2)( "RUP" :3)( "RMM" :4)( "INVALID_5" :5)( "INVALID_6" :6)( "DYN" :7)'\n' + +Floating-Point Control and Status Register Register +-------------------------- +AddressOffset: 'h3 +-------------------------- +Description: +-------------------------- +The floating-point control and status register, ``fcsr``, is a RISC-V control and status register (CSR). It is a read/write register that selects the dynamic rounding mode for floating-point arithmetic operations and holds the accrued exception flags. + +The ``fcsr`` register can be read and written with the FRCSR and FSCSR instructions, which are assembler pseudoinstructions built on the underlying CSR access instructions. FRCSR reads ``fcsr`` by copying it into integer register *rd*. FSCSR swaps the value in ``fcsr`` by copying the original value into integer register *rd*, and then writing a new value obtained from integer register *rs1* into ``fcsr``. + +The fields within the ``fcsr`` can also be accessed individually through different CSR addresses, and separate assembler pseudoinstructions are defined for these accesses. The FRRM instruction reads the Rounding Mode field ``frm`` and copies it into the least-significant three bits of integer register *rd*, with zero in all other bits. FSRM swaps the value in frm by copying the original value into integer register *rd*, and then writing a new value obtained from the three least-significant bits of integer register *rs1* into ``frm``. FRFLAGS and FSFLAGS are defined analogously for the Accrued Exception Flags field ``fflags``. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 7:5 + - FRM + - Floating-point rounding mode + - read-write + - Floating\-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in ``frm``\. Rounding modes are encoded as shown in the enumerated value\. A value of 111 in the instruction’s \*rm\* field selects the dynamic rounding mode held in ``frm``\. If ``frm`` is set to an invalid value \(101–111\), any subsequent attempt to execute a floating\-point operation with a dynamic rounding mode will raise an illegal instruction exception\. Some instructions, including widening conversions, have the \*rm\* field but are nevertheless unaffected by the rounding mode; software should set their \*rm\* field to RNE \(000\)\. ``Enumerated Values``( "RNE" :0)( "RTZ" :1)( "RDN" :2)( "RUP" :3)( "RMM" :4)( "INVALID_5" :5)( "INVALID_6" :6)( "DYN" :7)'\n' + * - 4 + - NV + - Invalid operation + - read-write + - The accrued exception flags indicate the exception conditions that have arisen on any floating\-point arithmetic instruction since the field was last reset by software\. The base RISC\-V ISA does not support generating a trap on the setting of a floating\-point exception flag\. + * - 3 + - DZ + - Divide by zero + - read-write + - The accrued exception flags indicate the exception conditions that have arisen on any floating\-point arithmetic instruction since the field was last reset by software\. The base RISC\-V ISA does not support generating a trap on the setting of a floating\-point exception flag\. + * - 2 + - OF + - Overflow + - read-write + - The accrued exception flags indicate the exception conditions that have arisen on any floating\-point arithmetic instruction since the field was last reset by software\. The base RISC\-V ISA does not support generating a trap on the setting of a floating\-point exception flag\. + * - 1 + - UF + - Underflow + - read-write + - The accrued exception flags indicate the exception conditions that have arisen on any floating\-point arithmetic instruction since the field was last reset by software\. The base RISC\-V ISA does not support generating a trap on the setting of a floating\-point exception flag\. + * - 0 + - NX + - Inexact + - read-write + - The accrued exception flags indicate the exception conditions that have arisen on any floating\-point arithmetic instruction since the field was last reset by software\. The base RISC\-V ISA does not support generating a trap on the setting of a floating\-point exception flag\. + +Supervisor Status Register +-------------------------- +AddressOffset: 'h100 +-------------------------- +Description: +-------------------------- +The ``sstatus`` register keeps track of the processor’s current operating state. + +The ``sstatus`` register is a subset of the ``mstatus`` register. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31 + - SD + - State dirty + - read-only + - The SD bit is a read\-only bit that summarizes whether either the FS, VS, or XS fields signal the presence of some dirty state that will require saving extended user context to memory\. If FS, XS, and VS are all read\-only zero, then SD is also always zero\. + * - 19 + - MXR + - Make executable readable + - read-write + - The MXR bit modifies the privilege with which loads access virtual memory\. When MXR=0, only loads from pages marked readable will succeed\. When MXR=1, loads from pages marked either readable or executable \(R=1 or X=1\) will succeed\. MXR has no effect when page\-based virtual memory is not in effect\. + * - 18 + - SUM + - Supervisor user memory + - read-write + - The SUM \(permit Supervisor User Memory access\) bit modifies the privilege with which S\-mode loads and stores access virtual memory\. When SUM=0, S\-mode memory accesses to pages that are accessible by U\-mode will fault\. When SUM=1, these accesses are permitted\. SUM has no effect when page\-based virtual memory is not in effect\. Note that, while SUM is ordinarily ignored when not executing in S\-mode, it \*is\* in effect when MPRV=1 and MPP=S\. SUM is read\-only 0 if S\-mode is not supported or if ``satp``\.MODE is read\-only 0\. + * - 16:15 + - XS + - Extension state + - read-only + - The XS field is used to reduce the cost of context save and restore by setting and tracking the current state of the user\-mode extensions\. The XS field encodes the status of the additional user\-mode extensions and associated state\. This field can be checked by a context switch routine to quickly determine whether a state save or restore is required\. If a save or restore is required, additional instructions and CSRs are typically required to effect and optimize the process\. ``Enumerated Values``( "Off" :0)( "Initial" :1)( "Clean" :2)( "Dirty" :3)'\n' + * - 14:13 + - FS + - Floating-point unit state + - read-write + - The FS field is used to reduce the cost of context save and restore by setting and tracking the current state of the floating\-point unit\. The FS field encodes the status of the floating\-point unit state, including the floating\-point registers ``f0–f31`` and the CSRs ``fcsr``, ``frm``, and ``fflags``\. This field can be checked by a context switch routine to quickly determine whether a state save or restore is required\. If a save or restore is required, additional instructions and CSRs are typically required to effect and optimize the process\. ``Enumerated Values``( "Off" :0)( "Initial" :1)( "Clean" :2)( "Dirty" :3)'\n' + * - 8 + - SPP + - Supervisor mode prior privilege + - read-write + - SPP bit indicates the privilege level at which a hart was executing before entering supervisor mode\. When a trap is taken, SPP is set to 0 if the trap originated from user mode, or 1 otherwise\. When an SRET instruction is executed to return from the trap handler, the privilege level is set to user mode if the SPP bit is 0, or supervisor mode if the SPP bit is 1; SPP is then set to 0\. + * - 5 + - SPIE + - Supervisor mode prior interrupt enable + - read-write + - The SPIE bit indicates whether supervisor interrupts were enabled prior to trapping into supervisor mode\. When a trap is taken into supervisor mode, SPIE is set to SIE, and SIE is set to 0\. When an SRET instruction is executed, SIE is set to SPIE, then SPIE is set to 1\. + * - 4 + - UPIE + - + - read-write + - When a URET instruction is executed, UIE is set to UPIE, and UPIE is set to 1\. + * - 1 + - SIE + - Supervisor mode interrupt enable + - read-write + - The SIE bit enables or disables all interrupts in supervisor mode\. When SIE is clear, interrupts are not taken while in supervisor mode\. When the hart is running in user\-mode, the value in SIE is ignored, and supervisor\-level interrupts are enabled\. The supervisor can disable individual interrupt sources using the ``sie`` CSR\. + * - 0 + - UIE + - + - read-write + - The UIE bit enables or disables user\-mode interrupts\. + +Supervisor Interrupt Enable Register +-------------------------- +AddressOffset: 'h104 +-------------------------- +Description: +-------------------------- +The ``sie`` is the register containing supervisor interrupt enable bits. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 9 + - SEIE + - Supervisor-level external interrupt enable + - read-write + - SEIE is the interrupt\-enable bit for supervisor\-level external interrupts\. + * - 8 + - UEIE + - + - read-write + - User\-level external interrupts are disabled when the UEIE bit in the sie register is clear\. + * - 5 + - STIE + - Supervisor-level timer interrupt enable + - read-write + - STIE is the interrupt\-enable bit for supervisor\-level timer interrupts\. + * - 4 + - UTIE + - + - read-write + - User\-level timer interrupts are disabled when the UTIE bit in the sie register is clear\. + * - 1 + - SSIE + - Supervisor-level software interrupt enable + - read-write + - SSIE is the interrupt\-enable bit for supervisor\-level software interrupts\. + * - 0 + - USIE + - + - read-write + - User\-level software interrupts are disabled when the USIE bit in the sie register is clear + +Supervisor Trap Vector Base Address Register +-------------------------- +AddressOffset: 'h105 +-------------------------- +Description: +-------------------------- +The ``stvec`` register holds trap vector configuration, consisting of a vector base address (BASE) and a vector mode (MODE). + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:2 + - BASE + - + - read-write + - The BASE field in stvec is a WARL field that can hold any valid virtual or physical address, subject to the following alignment constraints: the address must be 4\-byte aligned, and MODE settings other than Direct might impose additional alignment constraints on the value in the BASE field\. + * - 1:0 + - MODE + - + - read-write + - When MODE=Direct, all traps into supervisor mode cause the ``pc`` to be set to the address in the BASE field\. When MODE=Vectored, all synchronous exceptions into supervisor mode cause the ``pc`` to be set to the address in the BASE field, whereas interrupts cause the ``pc`` to be set to the address in the BASE field plus four times the interrupt cause number\. ``Enumerated Values``( "Direct" :0)( "Vectored" :1)( "Reserved_2" :2)( "Reserved_3" :3)'\n' + +Supervisor Counter Enable Register +-------------------------- +AddressOffset: 'h106 +-------------------------- +Description: +-------------------------- +The counter-enable register ``scounteren`` controls the availability of the hardware performance monitoring counters to U-mode. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:3 + - HPMn + - Hpmcountern + - read-write + - When HPMn is clear, attempts to read the ``hpmcountern`` register while executing in U\-mode will cause an illegal instruction exception\. When this bit is set, access to the corresponding register is permitted\. + * - 2 + - IR + - Instret + - read-write + - When IR is clear, attempts to read the ``instret`` register while executing in U\-mode will cause an illegal instruction exception\. When this bit is set, access to the corresponding register is permitted\. + * - 1 + - TM + - Time + - read-write + - When TM is clear, attempts to read the ``time`` register while executing in U\-mode will cause an illegal instruction exception\. When this bit is set, access to the corresponding register is permitted\. + * - 0 + - CY + - Cycle + - read-write + - When CY is clear, attempts to read the ``cycle`` register while executing in U\-mode will cause an illegal instruction exception\. When this bit is set, access to the corresponding register is permitted\. + +Supervisor Scratch Register +-------------------------- +AddressOffset: 'h140 +-------------------------- +Description: +-------------------------- +The ``sscratch`` register is dedicated for use by the supervisor. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - SSCRATCH + - Supervisor scratch + - read-write + - The ``sscratch`` register is dedicated for use by the supervisor\. + +Supervisor Exception Program Counter Register +-------------------------- +AddressOffset: 'h141 +-------------------------- +Description: +-------------------------- +When a trap is taken into S-mode, ``sepc`` is written with the virtual address of the instruction that was interrupted or that encountered the exception. Otherwise, ``sepc`` is never written by the implementation, though it may be explicitly written by software. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - SEPC + - Supervisor exception program counter + - read-write + - When a trap is taken into S\-mode, ``sepc`` is written with the virtual address of the instruction that was interrupted or that encountered the exception\. Otherwise, ``sepc`` is never written by the implementation, though it may be explicitly written by software\. + +Supervisor Cause Register +-------------------------- +AddressOffset: 'h142 +-------------------------- +Description: +-------------------------- +When a trap is taken into S-mode, ``scause`` is written with a code indicating the event that caused the trap. Otherwise, ``scause`` is never written by the implementation, though it may be explicitly written by software. +Supervisor cause register (``scause``) values after trap are shown in the following table. + +.. list-table:: + :widths: 20 20 20 + :header-rows: 1 + + * - **Interrupt** + - **Exception Code** + - **Description** + * - 1 + - 0 + - *Reserved* + * - 1 + - 1 + - Supervisor software interrupt + * - 1 + - 2-4 + - *Reserved* + * - 1 + - 5 + - Supervisor timer interrupt + * - 1 + - 6-8 + - *Reserved* + * - 1 + - 9 + - Supervisor external interrupt + * - 1 + - 10-15 + - *Reserved* + * - 1 + - >=16 + - *Designated for platform use* + * - 0 + - 0 + - Instruction address misaligned + * - 0 + - 1 + - Instruction access fault + * - 0 + - 2 + - Illegal instruction + * - 0 + - 3 + - Breakpoint + * - 0 + - 4 + - Load address misaligned + * - 0 + - 5 + - Load access fault + * - 0 + - 6 + - Store/AMO address misaligned + * - 0 + - 7 + - Store/AMO access fault + * - 0 + - 8 + - Environment call from U-mode + * - 0 + - 9 + - Environment call from S-mode + * - 0 + - 10-11 + - *Reserved* + * - 0 + - 12 + - Instruction page fault + * - 0 + - 13 + - Load page fault + * - 0 + - 14 + - *Reserved* + * - 0 + - 15 + - Store/AMO page fault + * - 0 + - 16-23 + - *Reserved* + * - 0 + - 24-31 + - *Designated for custom use* + * - 0 + - 32-47 + - *Reserved* + * - 0 + - 48-63 + - *Designated for custom use* + * - 0 + - >=64 + - *Reserved* + + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31 + - Interrupt + - + - read-write + - The Interrupt bit in the ``scause`` register is set if the trap was caused by an interrupt\. + * - 30:0 + - Exception_Code + - Exception code + - read-write + - The Exception Code field contains a code identifying the last exception or interrupt\. + +Supervisor Trap Value Register +-------------------------- +AddressOffset: 'h143 +-------------------------- +Description: +-------------------------- +When a trap is taken into S-mode, ``stval`` is written with exception-specific information to assist software in handling the trap. Otherwise, ``stval`` is never written by the implementation, though it may be explicitly written by software. The hardware platform will specify which exceptions must set ``stval`` informatively and which may unconditionally set it to zero. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - STVAL + - Supervisor trap value + - read-write + - When a trap is taken into S\-mode, ``stval`` is written with exception\-specific information to assist software in handling the trap\. Otherwise, ``stval`` is never written by the implementation, though it may be explicitly written by software\. The hardware platform will specify which exceptions must set ``stval`` informatively and which may unconditionally set it to zero\. + +Supervisor Interrupt Pending Register +-------------------------- +AddressOffset: 'h144 +-------------------------- +Description: +-------------------------- +The ``sip`` register contains information on pending interrupts. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 9 + - SEIP + - Supervisor-level external interrupt pending + - read-only + - SEIP is the interrupt\-pending bit for supervisor\-level external interrupts\. + * - 8 + - UEIP + - + - read-write + - UEIP may be written by S\-mode software to indicate to U\-mode that an external interrupt is pending\. + * - 5 + - STIP + - Supervisor-level timer interrupt pending + - read-only + - SEIP is the interrupt\-pending bit for supervisor\-level timer interrupts\. + * - 4 + - UTIP + - + - read-write + - A user\-level timer interrupt is pending if the UTIP bit in the sip register is set + * - 1 + - SSIP + - Supervisor-level software interrupt pending + - read-only + - SSIP is the interrupt\-pending bit for supervisor\-level software interrupts\. + * - 0 + - USIP + - + - read-write + - A user\-level software interrupt is triggered on the current hart by riting 1 to its user software interrupt\-pending \(USIP\) bit + +Supervisor Address Translation and Protection Register +-------------------------- +AddressOffset: 'h180 +-------------------------- +Description: +-------------------------- +The ``satp`` register controls supervisor-mode address translation and protection. + +The ``satp`` register is considered active when the effective privilege mode is S-mode or U-mode. Executions of the address-translation algorithm may only begin using a given value of ``satp`` when ``satp`` is active. + +.. note:: + Writing ``satp`` does not imply any ordering constraints between page-table updates and subsequent address translations, nor does it imply any invalidation of address-translation caches. If the new address space’s page tables have been modified, or if an ASID is reused, it may be necessary to execute an SFENCE.VMA instruction after, or in some cases before, writing ``satp``. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:31 + - MODE + - Mode + - read-write + - This bitfield selects the current address\-translation scheme\. When MODE=Bare, supervisor virtual addresses are equal to supervisor physical addresses, and there is no additional memory protection beyond the physical memory protection scheme\. To select MODE=Bare, software must write zero to the remaining fields of ``satp`` \(bits 30–0\)\. Attempting to select MODE=Bare with a nonzero pattern in the remaining fields has an ``unspecified`` effect on the value that the remaining fields assume and an ``unspecified`` effect on address translation and protection behavior\. ``Enumerated Values``( "Bare" :0)( "Sv32" :1)'\n' + * - 30:22 + - ASID + - Address space identifier + - read-write + - This bitfield facilitates address\-translation fences on a per\-address\-space basis\. + * - 21:0 + - PPN + - Physical page number + - read-write + - This bitfield holds the root page table, i\.e\., its supervisor physical address divided by 4 KiB\. + +Machine Status Register +-------------------------- +AddressOffset: 'h300 +-------------------------- +Description: +-------------------------- +The ``mstatus`` register keeps track of and controls the hart’s current operating state. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31 + - SD + - State dirty + - read-only + - The SD bit is a read\-only bit that summarizes whether either the FS, VS, or XS fields signal the presence of some dirty state that will require saving extended user context to memory\. If FS, XS, and VS are all read\-only zero, then SD is also always zero\. + * - 22 + - TSR + - Trap sret + - read-write + - The TSR bit supports intercepting the supervisor exception return instruction, SRET\. When TSR=1, attempts to execute SRET while executing in S\-mode will raise an illegal instruction exception\. When TSR=0, this operation is permitted in S\-mode\. + * - 21 + - TW + - Timeout wait + - read-write + - The TW bit supports intercepting the WFI instruction\. When TW=0, the WFI instruction may execute in lower privilege modes when not prevented for some other reason\. When TW=1, then if WFI is executed in any less\-privileged mode, and it does not complete within an implementation\-specific, bounded time limit, the WFI instruction causes an illegal instruction exception\. The time limit may always be 0, in which case WFI always causes an illegal instruction exception in less\-privileged modes when TW=1\. + * - 20 + - TVM + - Trap virtual memory + - read-write + - The TVM bit supports intercepting supervisor virtual\-memory management operations\. When TVM=1, attempts to read or write the ``satp`` CSR or execute an SFENCE\.VMA or SINVAL\.VMA instruction while executing in S\-mode will raise an illegal instruction exception\. When TVM=0, these operations are permitted in S\-mode\. + * - 19 + - MXR + - Make executable readable + - read-write + - The MXR bit modifies the privilege with which loads access virtual memory\. When MXR=0, only loads from pages marked readable will succeed\. When MXR=1, loads from pages marked either readable or executable \(R=1 or X=1\) will succeed\. MXR has no effect when page\-based virtual memory is not in effect\. + * - 18 + - SUM + - Supervisor user memory + - read-write + - The SUM \(permit Supervisor User Memory access\) bit modifies the privilege with which S\-mode loads and stores access virtual memory\. When SUM=0, S\-mode memory accesses to pages that are accessible by U\-mode will fault\. When SUM=1, these accesses are permitted\. SUM has no effect when page\-based virtual memory is not in effect\. Note that, while SUM is ordinarily ignored when not executing in S\-mode, it is in effect when MPRV=1 and MPP=S\. + * - 17 + - MPRV + - Modify privilege + - read-write + - The MPRV \(Modify PRiVilege\) bit modifies the effective privilege mode, i\.e\., the privilege level at which loads and stores execute\. When MPRV=0, loads and stores behave as normal, using the translation and protection mechanisms of the current privilege mode\. When MPRV=1, load and store memory addresses are translated and protected, and endianness is applied, as though the current privilege mode were set to MPP\. Instruction address\-translation and protection are unaffected by the setting of MPRV\. + * - 16:15 + - XS + - Extension state + - read-only + - The XS field is used to reduce the cost of context save and restore by setting and tracking the current state of the user\-mode extensions\. The XS field encodes the status of the additional user\-mode extensions and associated state\. This field can be checked by a context switch routine to quickly determine whether a state save or restore is required\. If a save or restore is required, additional instructions and CSRs are typically required to effect and optimize the process\. ``Enumerated Values``( "Off" :0)( "Initial" :1)( "Clean" :2)( "Dirty" :3)'\n' + * - 14:13 + - FS + - Floating-point unit state + - read-write + - The FS field is used to reduce the cost of context save and restore by setting and tracking the current state of the floating\-point unit\. The FS field encodes the status of the floating\-point unit state, including the floating\-point registers ``f0–f31`` and the CSRs ``fcsr``, ``frm``, and ``fflags``\. This field can be checked by a context switch routine to quickly determine whether a state save or restore is required\. If a save or restore is required, additional instructions and CSRs are typically required to effect and optimize the process\. ``Enumerated Values``( "Off" :0)( "Initial" :1)( "Clean" :2)( "Dirty" :3)'\n' + * - 12:11 + - MPP + - Machine mode prior privilege + - read-write + - Holds the previous privilege mode for machine mode\. + * - 8 + - SPP + - Supervisor mode prior privilege + - read-write + - Holds the previous privilege mode for supervisor mode\. + * - 7 + - MPIE + - Machine mode prior interrupt enable + - read-write + - Indicates whether machine interrupts were enabled prior to trapping into machine mode\. + * - 5 + - SPIE + - Supervisor mode prior interrupt enable + - read-write + - Indicates whether supervisor interrupts were enabled prior to trapping into supervisor mode\. + * - 4 + - UPIE + - + - read-write + - indicates whether user\-level interrupts were enabled prior to taking a user\-level trap + * - 3 + - MIE + - Machine mode interrupt enable + - read-write + - Global interrupt\-enable bit for Machine mode\. + * - 1 + - SIE + - Supervisor mode interrupt enable + - read-write + - Global interrupt\-enable bit for Supervisor mode\. + * - 0 + - UIE + - + - read-write + - Global interrupt\-enable bits + +Machine ISA Register +-------------------------- +AddressOffset: 'h301 +-------------------------- +Description: +-------------------------- +The misa CSR is reporting the ISA supported by the hart. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:30 + - MXL + - Machine xlen + - read-write + - The MXL field encodes the native base integer ISA width\. ``Enumerated Values``( "XLEN_32" :1)( "XLEN_64" :2)( "XLEN_128" :3)'\n' + * - 25:0 + - Extensions + - Extensions + - read-write + - The Extensions field encodes the presence of the standard extensions, with a single bit per letter of the alphabet\. ``Enumerated Values``( "A" :1)( "B" :2)( "C" :4)( "D" :8)( "E" :16)( "F" :32)( "G" :64)( "H" :128)( "I" :256)( "J" :512)( "K" :1024)( "L" :2048)( "M" :4096)( "N" :8192)( "O" :16384)( "P" :32768)( "Q" :65536)( "R" :131072)( "S" :262144)( "T" :524288)( "U" :1048576)( "V" :2097152)( "W" :4194304)( "X" :8388608)( "Y" :16777216)( "Z" :33554432)'\n' + +Machine Exception Delegation Register +-------------------------- +AddressOffset: 'h302 +-------------------------- +Description: +-------------------------- +Provides individual read/write bits to indicate that certain exceptions should be processed directly by a lower privilege level. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - Synchronous_Exceptions + - Synchronous exceptions + - read-write + - Provides individual read/write bits to indicate that certain exceptions should be processed directly by a lower privilege level\. + +Machine Interrupt Delegation Register +-------------------------- +AddressOffset: 'h303 +-------------------------- +Description: +-------------------------- +Provides individual read/write bits to indicate that certain interrupts should be processed directly by a lower privilege level. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - Interrupts + - Interrupts + - read-write + - Provides individual read/write bits to indicate that certain interrupts should be processed directly by a lower privilege level\. + +Machine Interrupt Enable Register +-------------------------- +AddressOffset: 'h304 +-------------------------- +Description: +-------------------------- +This register contains machine interrupt enable bits. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 11 + - MEIE + - M-mode external interrupt enable + - read-write + - Enables machine mode external interrupts\. + * - 9 + - SEIE + - S-mode external interrupt enable + - read-write + - Enables supervisor mode external interrupts\. + * - 8 + - UEIE + - + - read-write + - enables U\-mode external interrupts + * - 7 + - MTIE + - M-mode timer interrupt enable + - read-write + - Enables machine mode timer interrupts\. + * - 5 + - STIE + - S-mode timer interrupt enable + - read-write + - Enables supervisor mode timer interrupts\. + * - 4 + - UTIE + - + - read-write + - timer interrupt\-enable bit for U\-mode + * - 3 + - MSIE + - M-mode software interrupt enable + - read-write + - Enables machine mode software interrupts\. + * - 1 + - SSIE + - S-mode software interrupt enable + - read-write + - Enables supervisor mode software interrupts\. + * - 0 + - USIE + - + - read-write + - enable U\-mode software interrrupts + +Machine Trap Vector Register +-------------------------- +AddressOffset: 'h305 +-------------------------- +Description: +-------------------------- +This register holds trap vector configuration, consisting of a vector base address and a vector mode. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:2 + - BASE + - + - read-write + - Holds the vector base address\. The value in the BASE field must always be aligned on a 4\-byte boundary\. + * - 1:0 + - MODE + - + - read-write + - Imposes additional alignment constraints on the value in the BASE field\. ``Enumerated Values``( "Direct" :0)( "Vectored" :1)( "Reserved_2" :2)( "Reserved_3" :3)'\n' + +Machine Counter Enable Register +-------------------------- +AddressOffset: 'h306 +-------------------------- +Description: +-------------------------- +This register controls the availability of the hardware performance-monitoring counters to the next-lowest privileged mode. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:3 + - HPMn + - Hpmcountern + - read-write + - When HPMn is clear, attempts to read the ``hpmcountern`` register while executing in S\-mode or U\-mode will cause an illegal instruction exception\. When this bit is set, access to the corresponding register is permitted in the next implemented privilege mode\. + * - 2 + - IR + - Instret + - read-write + - When IR is clear, attempts to read the ``instret`` register while executing in S\-mode or U\-mode will cause an illegal instruction exception\. When this bit is set, access to the corresponding register is permitted in the next implemented privilege mode\. + * - 1 + - TM + - Time + - read-write + - When TM is clear, attempts to read the ``time`` register while executing in S\-mode or U\-mode will cause an illegal instruction exception\. When this bit is set, access to the corresponding register is permitted in the next implemented privilege mode\. + * - 0 + - CY + - Cycle + - read-write + - When CY is clear, attempts to read the ``cycle`` register while executing in S\-mode or U\-mode will cause an illegal instruction exception\. When this bit is set, access to the corresponding register is permitted in the next implemented privilege mode\. + +Hardware Performance-Monitoring Event Selector Register +-------------------------- +AddressOffset: 'h323 +-------------------------- +Description: +-------------------------- +This register controls which event causes the corresponding counter to increment. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 4:0 + - mhpmevent + - + - read-write + - This register controls which event causes the corresponding counter to increment\. + +Machine Scratch Register +-------------------------- +AddressOffset: 'h340 +-------------------------- +Description: +-------------------------- +This register is used to hold a value dedicated to Machine mode. Attempts to access without Machine mode level raise illegal instruction exception. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - mscratch + - Machine scratch + - read-write + - This register is used to hold a value dedicated to Machine mode\. Attempts to access without Machine mode level raise illegal instruction exception\. + +Machine Exception Program Counter Register +-------------------------- +AddressOffset: 'h341 +-------------------------- +Description: +-------------------------- +This register must be able to hold all valid virtual addresses. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - mepc + - Machine exception program counter + - read-write + - This register must be able to hold all valid virtual addresses\. + +Machine Cause Register +-------------------------- +AddressOffset: 'h342 +-------------------------- +Description: +-------------------------- +When a trap is taken into M-mode, mcause is written with a code indicating the event that caused the trap. +Machine cause register (``mcause``) values after trap are shown in the following table. + +.. list-table:: + :widths: 20 20 20 + :header-rows: 1 + + * - **Interrupt** + - **Exception Code** + - **Description** + * - 1 + - 0 + - *Reserved* + * - 1 + - 1 + - Supervisor software interrupt + * - 1 + - 2-4 + - *Reserved* + * - 1 + - 5 + - Supervisor timer interrupt + * - 1 + - 6-8 + - *Reserved* + * - 1 + - 9 + - Supervisor external interrupt + * - 1 + - 10-15 + - *Reserved* + * - 1 + - >=16 + - *Designated for platform use* + * - 0 + - 0 + - Instruction address misaligned + * - 0 + - 1 + - Instruction access fault + * - 0 + - 2 + - Illegal instruction + * - 0 + - 3 + - Breakpoint + * - 0 + - 4 + - Load address misaligned + * - 0 + - 5 + - Load access fault + * - 0 + - 6 + - Store/AMO address misaligned + * - 0 + - 7 + - Store/AMO access fault + * - 0 + - 8 + - Environment call from U-mode + * - 0 + - 9 + - Environment call from S-mode + * - 0 + - 10-11 + - *Reserved* + * - 0 + - 12 + - Instruction page fault + * - 0 + - 13 + - Load page fault + * - 0 + - 14 + - *Reserved* + * - 0 + - 15 + - Store/AMO page fault + * - 0 + - 16-23 + - *Reserved* + * - 0 + - 24-31 + - *Designated for custom use* + * - 0 + - 32-47 + - *Reserved* + * - 0 + - 48-63 + - *Designated for custom use* + * - 0 + - >=64 + - *Reserved* + + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31 + - Interrupt + - Interrupt + - read-write + - This bit is set if the trap was caused by an interrupt\. + * - 30:0 + - exception_code + - Exception code + - read-write + - This field contains a code identifying the last exception or interrupt\. + +Machine Trap Value Register +-------------------------- +AddressOffset: 'h343 +-------------------------- +Description: +-------------------------- +When a trap is taken into M-mode, mtval is either set to zero or written with exception-specific information to assist software in handling the trap. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - mtval + - Machine trap value + - read-write + - When a trap is taken into M\-mode, mtval is either set to zero or written with exception\-specific information to assist software in handling the trap\. + +Machine Interrupt Pending Register +-------------------------- +AddressOffset: 'h344 +-------------------------- +Description: +-------------------------- +This register contains machine interrupt pending bits. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 11 + - MEIP + - M-mode external interrupt pending + - read-only + - The interrupt\-pending bit for machine\-level external interrupts\. + * - 9 + - SEIP + - S-mode external interrupt pending + - read-write + - The interrupt\-pending bit for supervisor\-level external interrupts\. + * - 8 + - UEIP + - + - read-write + - enables external interrupts + * - 7 + - MTIP + - M-mode timer interrupt pending + - read-only + - The interrupt\-pending bit for machine\-level timer interrupts\. + * - 5 + - STIP + - S-mode timer interrupt pending + - read-write + - The interrupt\-pending bit for supervisor\-level timer interrupts\. + * - 4 + - UTIP + - + - read-write + - Correspond to timer interrupt\-pending bits for user interrupt + * - 3 + - MSIP + - M-mode software interrupt pending + - read-only + - The interrupt\-pending bit for machine\-level software interrupts\. + * - 1 + - SSIP + - S-mode software interrupt pending + - read-write + - The interrupt\-pending bit for supervisor\-level software interrupts\. + * - 0 + - USIP + - + - read-write + - A hart to directly write its own USIP bits when running in the appropriate mode + +Physical Memory Protection Config 0 Register +-------------------------- +AddressOffset: 'h3A0 +-------------------------- +Description: +-------------------------- +Holds configuration 0-3. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:24 + - pmp3cfg + - Physical memory protection 3 config + - read-write + - Holds the configuration\. + * - 23:16 + - pmp2cfg + - Physical memory protection 2 config + - read-write + - Holds the configuration\. + * - 15:8 + - pmp1cfg + - Physical memory protection 1 config + - read-write + - Holds the configuration\. + * - 7:0 + - pmp0cfg + - Physical memory protection 0 config + - read-write + - Holds the configuration\. + +Physical Memory Protection Config 1 Register +-------------------------- +AddressOffset: 'h3A1 +-------------------------- +Description: +-------------------------- +Holds configuration 4-7. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:24 + - pmp7cfg + - Physical memory protection 7 config + - read-write + - Holds the configuration\. + * - 23:16 + - pmp6cfg + - Physical memory protection 6 config + - read-write + - Holds the configuration\. + * - 15:8 + - pmp5cfg + - Physical memory protection 5 config + - read-write + - Holds the configuration\. + * - 7:0 + - pmp4cfg + - Physical memory protection 4 config + - read-write + - Holds the configuration\. + +Physical Memory Protection Config 2 Register +-------------------------- +AddressOffset: 'h3A2 +-------------------------- +Description: +-------------------------- +Holds configuration 8-11. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:24 + - pmp11cfg + - Physical memory protection 11 config + - read-write + - Holds the configuration\. + * - 23:16 + - pmp10cfg + - Physical memory protection 10 config + - read-write + - Holds the configuration\. + * - 15:8 + - pmp9cfg + - Physical memory protection 9 config + - read-write + - Holds the configuration\. + * - 7:0 + - pmp8cfg + - Physical memory protection 8 config + - read-write + - Holds the configuration\. + +Physical Memory Protection Config 3 Register +-------------------------- +AddressOffset: 'h3A3 +-------------------------- +Description: +-------------------------- +Holds configuration 12-15. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:24 + - pmp15cfg + - Physical memory protection 15 config + - read-write + - Holds the configuration\. + * - 23:16 + - pmp14cfg + - Physical memory protection 14 config + - read-write + - Holds the configuration\. + * - 15:8 + - pmp13cfg + - Physical memory protection 13 config + - read-write + - Holds the configuration\. + * - 7:0 + - pmp12cfg + - Physical memory protection 12 config + - read-write + - Holds the configuration\. + +Physical Memory Protection Address Register +-------------------------- +AddressOffset: 'h3B0 +-------------------------- +Description: +-------------------------- +Address register for Physical Memory Protection. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - address + - Address + - read-write + - Address register for Physical Memory Protection\. + +Instuction Cache Register +-------------------------- +AddressOffset: 'h700 +-------------------------- +Description: +-------------------------- +Custom Register to enable/disable for Icache [bit 0] + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 0 + - icache + - Instruction cache + - read-write + - Custom Register to enable/disable for Icache \[bit 0\] + +Data Cache Register +-------------------------- +AddressOffset: 'h701 +-------------------------- +Description: +-------------------------- +Custom Register to enable/disable for Dcache [bit 0] + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 0 + - dcache + - Data cache + - read-write + - Custom Register to enable/disable for Dcache \[bit 0\] + +Trigger Select Register +-------------------------- +AddressOffset: 'h7A0 +-------------------------- +Description: +-------------------------- +This register determines which trigger is accessible through the other trigger registers. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - index + - Index + - read-write + - This register determines which trigger is accessible through the other trigger registers\. + +Trigger Data 1 Register +-------------------------- +AddressOffset: 'h7A1 +-------------------------- +Description: +-------------------------- +Trigger-specific data. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:28 + - type + - Type + - read-write + - Type of trigger\. ``Enumerated Values``( "no_trigger" :0)( "legacy_address_match_trigger" :1)( "address_data_match_trigger" :2)( "instruction_count_trigger" :3)( "interrupt_trigger" :4)( "exception_trigger" :5)( "Reserved_6" :6)( "Reserved_7" :7)( "Reserved_8" :8)( "Reserved_9" :9)( "Reserved_10" :10)( "Reserved_11" :11)( "Reserved_12" :12)( "Reserved_13" :13)( "Reserved_14" :14)( "trigger_exists" :15)'\n' + * - 27:27 + - dmode + - Debug mode + - read-write + - This bit is only writable from Debug Mode\. ``Enumerated Values``( "D_and_M_mode" :0)( "M_mode_only" :1)'\n' + * - 26:0 + - data + - Data + - read-write + - Trigger\-specific data\. + +Trigger Data 2 Register +-------------------------- +AddressOffset: 'h7A2 +-------------------------- +Description: +-------------------------- +Trigger-specific data. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - data + - Data + - read-write + - Trigger\-specific data\. + +Trigger Data 3 Register +-------------------------- +AddressOffset: 'h7A3 +-------------------------- +Description: +-------------------------- +Trigger-specific data. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - data + - Data + - read-write + - Trigger\-specific data\. + +Trigger Info Register +-------------------------- +AddressOffset: 'h7A4 +-------------------------- +Description: +-------------------------- +Shows trigger information. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 15:0 + - info + - Info + - read-only + - Shows trigger information\. + +Debug Control and Status Register +-------------------------- +AddressOffset: 'h7B0 +-------------------------- +Description: +-------------------------- +Debug ontrol and status register. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:28 + - xdebugver + - Debug version + - read-only + - Shows the version of the debug support\. ``Enumerated Values``( "no_ext_debug" :0)( "ext_debug_spec" :4)( "ext_debug_no_spec" :15)'\n' + * - 15:15 + - ebreakm + - Environment breakpoint m-mode + - read-write + - Shows the behvior of the ``ebreak`` instruction in machine mode\. ``Enumerated Values``( "break_as_spec" :0)( "break_to_debug" :1)'\n' + * - 13:13 + - ebreaks + - Environment breakpoint s-mode + - read-write + - Shows the behvior of the ``ebreak`` instruction in supervisor mode\. ``Enumerated Values``( "break_as_spec" :0)( "break_to_debug" :1)'\n' + * - 12:12 + - ebreaku + - Environment breakpoint u-mode + - read-write + - Shows the behvior of the ``ebreak`` instruction in user mode\. ``Enumerated Values``( "break_as_spec" :0)( "break_to_debug" :1)'\n' + * - 11:11 + - stepie + - Stepping interrupt enable + - read-write + - Enables/disables interrupts for single stepping\. The debugger must not change the value of this bit while the hart is running\. ``Enumerated Values``( "disabled" :0)( "enabled" :1)'\n' + * - 10:10 + - stopcount + - Stop counters + - read-write + - Starts/stops incrementing counters in debug mode\. ``Enumerated Values``( "increment_counters" :0)( "dont_increment_counters" :1)'\n' + * - 9:9 + - stoptime + - Stop timers + - read-write + - Starts/stops incrementing timers in debug mode\. ``Enumerated Values``( "increment_timers" :0)( "dont_increment_timers" :1)'\n' + * - 8:6 + - cause + - Cause + - read-write + - Explains why Debug Mode was entered\. When there are multiple reasons to enter Debug Mode in a single cycle, hardware sets ``cause`` to the cause with the highest priority\. ``Enumerated Values``( "ebreak_instruction" :1)( "trigger_module" :2)( "debugger_request" :3)( "single_step" :4)( "reset_halt" :5)'\n' + * - 4:4 + - mprven + - Modify privilege enable + - read-write + - Enables/disables the modify privilege setting in debug mode\. ``Enumerated Values``( "disable_mprv" :0)( "enable_mprv" :1)'\n' + * - 3 + - nmip + - Non-maskable interrupt pending + - read-only + - When set, there is a Non\-Maskable\-Interrupt \(NMI\) pending for the hart\. + * - 2 + - step + - Step + - read-write + - When set and not in Debug Mode, the hart will only execute a single instruction and then enter Debug Mode\. If the instruction does not complete due to an exception, the hart will immediately enter Debug Mode before executing the trap handler, with appropriate exception registers set\. The debugger must not change the value of this bit while the hart is running\. + * - 1:0 + - prv + - Privilege level + - read-write + - Contains the privilege level the hart was operating in when Debug Mode was entered\. A debugger can change this value to change the hart’s privilege level when exiting Debug Mode\. ``Enumerated Values``( "User" :0)( "Supervisor" :1)( "Machine" :3)'\n' + +Debug PC Register +-------------------------- +AddressOffset: 'h7B1 +-------------------------- +Description: +-------------------------- +Upon entry to debug mode, ``dpc`` is updated with the virtual address of the next instruction to be executed. + +When resuming, the hart’s PC is updated to the virtual address stored in ``dpc``. A debugger may write ``dpc`` to change where the hart resumes. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - dpc + - + - read-write + - Upon entry to debug mode, ``dpc`` is updated with the virtual address of the next instruction to be executed\. When resuming, the hart’s PC is updated to the virtual address stored in ``dpc``\. A debugger may write ``dpc`` to change where the hart resumes\. + +Debug Scratch Register Register +-------------------------- +AddressOffset: 'h7B2 +-------------------------- +Description: +-------------------------- +Optional scratch register. A debugger must not write to this register unless ``hartinfo`` explicitly mentions it. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - dscratch + - + - read-write + - Optional scratch register\. A debugger must not write to this register unless ``hartinfo`` explicitly mentions it\. + + Register +-------------------------- +AddressOffset: 'h800 +-------------------------- +Description: +-------------------------- +Floating Point Custom CSR + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 6:0 + - ftran + - + - read-write + - Floating Point Custom CSR + +M-mode Cycle counter Register +-------------------------- +AddressOffset: 'hB00 +-------------------------- +Description: +-------------------------- +Counts the number of clock cycles executed by the processor core on which the hart is running. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-write + - Counts the number of clock cycles executed by the processor core on which the hart is running\. + +Machine Instruction Retired counter Register +-------------------------- +AddressOffset: 'hB02 +-------------------------- +Description: +-------------------------- +Counts the number of instructions the hart has retired. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-write + - Counts the number of instructions the hart has retired\. + +L1 Inst Cache Miss Register +-------------------------- +AddressOffset: 'hB03 +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-write + - Hardware performance event counter\. + +L1 Data Cache Miss Register +-------------------------- +AddressOffset: 'hB04 +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-write + - Hardware performance event counter\. + +ITLB Miss Register +-------------------------- +AddressOffset: 'hB05 +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-write + - Hardware performance event counter\. + +DTLB Miss Register +-------------------------- +AddressOffset: 'hB06 +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-write + - Hardware performance event counter\. + +Loads Register +-------------------------- +AddressOffset: 'hB07 +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-write + - Hardware performance event counter\. + +Stores Register +-------------------------- +AddressOffset: 'hB08 +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-write + - Hardware performance event counter\. + +Taken Exceptions Register +-------------------------- +AddressOffset: 'hB09 +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-write + - Hardware performance event counter\. + +Exception Return Register +-------------------------- +AddressOffset: 'hB0A +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-write + - Hardware performance event counter\. + +Software Change of PC Register +-------------------------- +AddressOffset: 'hB0B +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-write + - Hardware performance event counter\. + +Procedure Call Register +-------------------------- +AddressOffset: 'hB0C +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-write + - Hardware performance event counter\. + +Procedure Return Register +-------------------------- +AddressOffset: 'hB0D +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-write + - Hardware performance event counter\. + +Branch mis-predicted Register +-------------------------- +AddressOffset: 'hB0E +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-write + - Hardware performance event counter\. + +Scoreboard Full Register +-------------------------- +AddressOffset: 'hB0F +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-write + - Hardware performance event counter\. + +Instruction Fetch Queue Empty Register +-------------------------- +AddressOffset: 'hB10 +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-write + - Hardware performance event counter\. + +Upper 32-bits of M-mode Cycle counter Register +-------------------------- +AddressOffset: 'hB80 +-------------------------- +Description: +-------------------------- +Counts the number of clock cycles executed by the processor core on which the hart is running. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-write + - Counts the number of clock cycles executed by the processor core on which the hart is running\. + +Upper 32-bits of Machine Instruction Retired counter Register +-------------------------- +AddressOffset: 'hB82 +-------------------------- +Description: +-------------------------- +Counts the number of instructions the hart has retired. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-write + - Counts the number of instructions the hart has retired\. + +Upper 32-bits of Machine Hardware Performance Monitoring Counter Register +-------------------------- +AddressOffset: 'hB83 +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-write + - Hardware performance event counter\. + +Cycle counter Register +-------------------------- +AddressOffset: 'hC00 +-------------------------- +Description: +-------------------------- +Cycle counter for RDCYCLE instruction. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-only + - Cycle counter for RDCYCLE instruction\. + +Timer Register +-------------------------- +AddressOffset: 'hC01 +-------------------------- +Description: +-------------------------- +Timer for RDTIME instruction. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-only + - Timer for RDTIME instruction\. + +Instruction Retired counter Register +-------------------------- +AddressOffset: 'hC02 +-------------------------- +Description: +-------------------------- +Instructions-retired counter for RDINSTRET instruction + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-only + - Instructions\-retired counter for RDINSTRET instruction + +L1 Inst Cache Miss Register +-------------------------- +AddressOffset: 'hC03 +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-only + - Hardware performance event counter\. + +L1 Data Cache Miss Register +-------------------------- +AddressOffset: 'hC04 +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-only + - Hardware performance event counter\. + +ITLB Miss Register +-------------------------- +AddressOffset: 'hC05 +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-only + - Hardware performance event counter\. + +DTLB Miss Register +-------------------------- +AddressOffset: 'hC06 +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-only + - Hardware performance event counter\. + +Loads Register +-------------------------- +AddressOffset: 'hC07 +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-only + - Hardware performance event counter\. + +Stores Register +-------------------------- +AddressOffset: 'hC08 +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-only + - Hardware performance event counter\. + +Taken Exceptions Register +-------------------------- +AddressOffset: 'hC09 +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-only + - Hardware performance event counter\. + +Exception Return Register +-------------------------- +AddressOffset: 'hC0A +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-only + - Hardware performance event counter\. + +Software Change of PC Register +-------------------------- +AddressOffset: 'hC0B +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-only + - Hardware performance event counter\. + +Procedure Call Register +-------------------------- +AddressOffset: 'hC0C +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-only + - Hardware performance event counter\. + +Procedure Return Register +-------------------------- +AddressOffset: 'hC0D +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-only + - Hardware performance event counter\. + +Branch mis-predicted Register +-------------------------- +AddressOffset: 'hC0E +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-only + - Hardware performance event counter\. + +Scoreboard Full Register +-------------------------- +AddressOffset: 'hC0F +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-only + - Hardware performance event counter\. + +Instruction Fetch Queue Empty Register +-------------------------- +AddressOffset: 'hC10 +-------------------------- +Description: +-------------------------- +Hardware performance event counter. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-only + - Hardware performance event counter\. + +Upper 32-bits of Cycle counter Register +-------------------------- +AddressOffset: 'hC80 +-------------------------- +Description: +-------------------------- +Cycle counter for RDCYCLE instruction. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-only + - Cycle counter for RDCYCLE instruction\. + +Upper 32-bit of Timer Register +-------------------------- +AddressOffset: 'hC81 +-------------------------- +Description: +-------------------------- +Timer for RDTIME instruction. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-only + - Timer for RDTIME instruction\. + +Upper 32-bits of Instruction Retired counter Register +-------------------------- +AddressOffset: 'hC82 +-------------------------- +Description: +-------------------------- +Instructions-retired counter for RDINSTRET instruction + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - count + - Count + - read-only + - Instructions\-retired counter for RDINSTRET instruction + +Machine Vendor ID Register +-------------------------- +AddressOffset: 'hF11 +-------------------------- +Description: +-------------------------- +This register provids the JEDEC manufacturer ID of the provider of the core. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:7 + - bank + - Bank + - read-only + - Contain encoding for number of one\-byte continuation codes discarding the parity bit\. + * - 6:0 + - offset + - Offset + - read-only + - Contain encording for the final byte discarding the parity bit\. + +Machine Architecture ID Register +-------------------------- +AddressOffset: 'hF12 +-------------------------- +Description: +-------------------------- +This register encodes the base microarchitecture of the hart. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - architecture_id + - Architecture id + - read-only + - This register encodes the base microarchitecture of the hart\. + +Machine Implementation ID Register +-------------------------- +AddressOffset: 'hF13 +-------------------------- +Description: +-------------------------- +Provides a unique encoding of the version of the processor implementation. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - implementation + - Implementation + - read-only + - Provides a unique encoding of the version of the processor implementation\. + +Machine Hardware Thread ID Register +-------------------------- +AddressOffset: 'hF14 +-------------------------- +Description: +-------------------------- +This register contains the integer ID of the hardware thread running the code. + +.. list-table:: + :widths: 20 20 15 15 40 + :header-rows: 1 + + * - **BIT** + - **NAME** + - **displayName** + - **RIGHT** + - **Description** + * - 31:0 + - hart_id + - Hart id + - read-only + - This register contains the integer ID of the hardware thread running the code\. diff --git a/verif/docs/VerifPlans/csr_access/runme.sh b/verif/docs/VerifPlans/csr_access/runme.sh new file mode 100644 index 0000000000..fbf348b409 --- /dev/null +++ b/verif/docs/VerifPlans/csr_access/runme.sh @@ -0,0 +1,34 @@ +############################################################################# +# Copyright (C) 2022 Thales DIS France SAS +# +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0. +# +# Original Author: Zbigniew Chamski (zbigniew.chamski@thalesgroup.com) +############################################################################# +#!/bin/sh + +# Location of project-specific directories +ROOTDIR=`readlink -f $(dirname "${BASH_SOURCE[0]}")` + +# Set up platform location. It can be anywhere but should contain +# a valid `vp_config.py` file in `vptool` directory. +# Here we use the verification tree from the example directory. +export PLATFORM_TOP_DIR="$ROOTDIR" + +# Set the printable name for the project that will be used +# in the human-readable documentation. +export PROJECT_NAME="CSR ACCESS VERIFICATION" + +# Set the alphanumerical identifier of the project that +# will be used to construct file names etc. +export PROJECT_IDENT="csr-access" + +# Set the destination directory of Markdown files for this project. +# Since it will be used by VPTOOL, it shall NOT be a relative path. +export MARKDOWN_OUTPUT_DIR=`readlink -f "$ROOTDIR/../source"` + +# Run VPTOOL overriding the default theme from Yaml config with 'winxpblue'. +# FIXME: Introduce a suitably named shell variable that points to the root +# directory of the tool set (TOOL_TOP etc.) +# FORNOW use a hardcoded relative path. +sh $ROOTDIR/../../../../tools/vptool/vptool.sh $* diff --git a/verif/docs/VerifPlans/cvxif_VP.xlsx b/verif/docs/VerifPlans/cvxif_VP.xlsx new file mode 100644 index 0000000000..1f22c4ce71 Binary files /dev/null and b/verif/docs/VerifPlans/cvxif_VP.xlsx differ diff --git a/verif/docs/VerifPlans/images/openhw-landscape.svg b/verif/docs/VerifPlans/images/openhw-landscape.svg new file mode 100644 index 0000000000..d6383f3c39 --- /dev/null +++ b/verif/docs/VerifPlans/images/openhw-landscape.svg @@ -0,0 +1,311 @@ +<?xml version="1.0" encoding="utf-8"?> +<!-- Generator: Adobe Illustrator 16.0.4, SVG Export Plug-In . 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M401.717,29.121h6.794c0.291,0,0.528-0.025,0.714-0.078c0.185-0.053,0.326-0.123,0.424-0.211c0.099-0.09,0.165-0.191,0.201-0.311 + c0.035-0.119,0.053-0.25,0.053-0.391c0-0.131-0.018-0.26-0.053-0.383c-0.036-0.123-0.103-0.229-0.201-0.316 + c-0.098-0.088-0.239-0.158-0.424-0.211c-0.186-0.053-0.423-0.078-0.714-0.078h-6.794V29.121z"/> +</g> +<line fill="#6D6E71" stroke="#6D6E71" stroke-miterlimit="10" x1="118.106" y1="82.673" x2="157.744" y2="82.673"/> +<line fill="#6D6E71" stroke="#6D6E71" stroke-miterlimit="10" x1="370.925" y1="82.673" x2="410.562" y2="82.673"/> +</svg> diff --git a/verif/docs/VerifPlans/install-prerequisites.sh b/verif/docs/VerifPlans/install-prerequisites.sh new file mode 100644 index 0000000000..b8f169bb72 --- /dev/null +++ b/verif/docs/VerifPlans/install-prerequisites.sh @@ -0,0 +1,37 @@ +#!/bin/sh + +############################################################################# +# Copyright (C) 2022 Thales DIS France SAS +# +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0. +# +# Original Author: Zbigniew Chamski (zbigniew.chamski@thalesgroup.com) +############################################################################# +# Make sure all necessary components are installed/available. +# +# Install Python dependencies. We can extract the full path of the script only +# when invoked using '$SHELL <script>' syntax. With "source" and "dot" invocation +# methods (basename of $0 equal to $SHELL), the script must be run from the +# directory containing 'requirements.txt'. +[ $(basename $SHELL) = $0 ] && { \ + echo "Please run this script from the directory in which it is located," + echo "or use the syntax '"$0 path-to-script"'" + return 1 +} +python3 -m pip install -q -r $(dirname $(readlink -f $0))/requirements.txt + +# Check for a LaTeX installation. +which latex > /dev/null || { \ + echo "*** LaTeX ecosystem missing on you machine!" + echo "*** Please install a LaTeX distribution if you intend to produce DV plans in PDF and/or ePub formats." + return 1 +} + +# Check for latexmk which is required for printable output. +which latexmk > /dev/null || { \ + echo "*** LaTeX wrapper 'latexmk' missing!" + echo "*** Please install it if you intend to produce DV plans in PDF and/or ePub formats." + return 1 +} + +echo "All dependencies for human-readable Verification Plan generation are OK." diff --git a/verif/docs/VerifPlans/make.bat b/verif/docs/VerifPlans/make.bat new file mode 100644 index 0000000000..543c6b13b4 --- /dev/null +++ b/verif/docs/VerifPlans/make.bat @@ -0,0 +1,35 @@ +@ECHO OFF + +pushd %~dp0 + +REM Command file for Sphinx documentation + +if "%SPHINXBUILD%" == "" ( + set SPHINXBUILD=sphinx-build +) +set SOURCEDIR=source +set BUILDDIR=build + +if "%1" == "" goto help + +%SPHINXBUILD% >NUL 2>NUL +if errorlevel 9009 ( + echo. + echo.The 'sphinx-build' command was not found. Make sure you have Sphinx + echo.installed, then set the SPHINXBUILD environment variable to point + echo.to the full path of the 'sphinx-build' executable. Alternatively you + echo.may add the Sphinx directory to PATH. + echo. + echo.If you don't have Sphinx installed, grab it from + echo.http://sphinx-doc.org/ + exit /b 1 +) + +%SPHINXBUILD% -M %1 %SOURCEDIR% %BUILDDIR% %SPHINXOPTS% +goto end + +:help +%SPHINXBUILD% -M help %SOURCEDIR% %BUILDDIR% %SPHINXOPTS% + +:end +popd diff --git a/verif/docs/VerifPlans/requirements.txt b/verif/docs/VerifPlans/requirements.txt new file mode 100644 index 0000000000..ed9ee59efb --- /dev/null +++ b/verif/docs/VerifPlans/requirements.txt @@ -0,0 +1,5 @@ +sphinx +sphinx-rtd-theme +recommonmark +sphinxcontrib-svg2pdfconverter +sphinx_github_changelog diff --git a/verif/docs/VerifPlans/source/conf.py b/verif/docs/VerifPlans/source/conf.py new file mode 100644 index 0000000000..815b06ffa0 --- /dev/null +++ b/verif/docs/VerifPlans/source/conf.py @@ -0,0 +1,214 @@ +# -*- coding: utf-8 -*- +# +# Copyright (c) 2020 OpenHW Group +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://solderpad.org/licenses/ +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# +############################################################################### +# +# Configuration file for the Sphinx documentation builder. +# +# This file does only contain a selection of the most common options. For a +# full list see the documentation: +# http://www.sphinx-doc.org/en/master/config + +# -- Path setup -------------------------------------------------------------- + +# If extensions (or modules to document with autodoc) are in another directory, +# add these directories to sys.path here. If the directory is relative to the +# documentation root, use os.path.abspath to make it absolute, like shown here. +# +# import os +# import sys +# sys.path.insert(0, os.path.abspath('.')) + + +# -- Project information ----------------------------------------------------- + +project = u'CORE-V CV32A6-step1 Design Verification Plan' +copyright = u'2022, Thales Group' +author = u'Thales' + +# The short X.Y version +version = u'' +# The full version, including alpha/beta/rc tags +release = u'' + + +# -- General configuration --------------------------------------------------- + +# If your documentation needs a minimal Sphinx version, state it here. +# +# needs_sphinx = '1.0' + +# Add any Sphinx extension module names here, as strings. They can be +# extensions coming with Sphinx (named 'sphinx.ext.*') or your custom +# ones. +extensions = [ + 'sphinx.ext.autodoc', + 'sphinx.ext.todo', + 'recommonmark', + 'sphinxcontrib.inkscapeconverter', + 'sphinx_github_changelog', +# 'sphinxcontrib.wavedrom', +] +#wavedrom_html_jsinline = False + +# Add any paths that contain templates here, relative to this directory. +templates_path = ['ytemplates'] + +# The suffix(es) of source filenames. +# You can specify multiple suffix as a list of string: +# +# source_suffix = ['.rst', '.md'] +source_suffix = '.rst' + +# The master toctree document. +master_doc = 'index' + +# The language for content autogenerated by Sphinx. Refer to documentation +# for a list of supported languages. +# +# This is also used if you do content translation via gettext catalogs. +# Usually you set "language" from the command line for these cases. +language = 'en' + +# List of patterns, relative to source directory, that match files and +# directories to ignore when looking for source files. +# This pattern also affects html_static_path and html_extra_path. +exclude_patterns = [] + +# Numbering +numfig=True +numfig_format = {'figure': 'Figure %s', 'table': 'Table %s', 'code-block': 'Listing %s'} + +# The name of the Pygments (syntax highlighting) style to use. +pygments_style = None + + +# -- Options for HTML output ------------------------------------------------- + +# The theme to use for HTML and HTML Help pages. See the documentation for +# a list of builtin themes. +# +#html_theme = 'alabaster' +html_theme = 'sphinx_rtd_theme' + +# Theme options are theme-specific and customize the look and feel of a theme +# further. For a list of options available for each theme, see the +# documentation. +# +html_theme_options = {'style_nav_header_background': '#DDDDDD'} +html_logo = '../images/openhw-landscape.svg' + +# Add any paths that contain custom static files (such as style sheets) here, +# relative to this directory. They are copied after the builtin static files, +# so a file named "default.css" will overwrite the builtin "default.css". +#html_static_path = ['ystatic'] +# Set html_static_path to null on the advice of RTDs: +html_static_path = [] + +# Custom sidebar templates, must be a dictionary that maps document names +# to template names. +# +# The default sidebars (for documents that don't match any pattern) are +# defined by theme itself. Builtin themes are using these templates by +# default: ``['localtoc.html', 'relations.html', 'sourcelink.html', +# 'searchbox.html']``. +# +# html_sidebars = {} + + +# -- Options for HTMLHelp output --------------------------------------------- + +# Output file base name for HTML help builder. +htmlhelp_basename = 'CORE-V_CV32A6-step1_DVPLAN' + + +# -- Options for LaTeX output ------------------------------------------------ + +latex_elements = { + # The paper size ('letterpaper' or 'a4paper'). + # + # 'papersize': 'letterpaper', + + # The font size ('10pt', '11pt' or '12pt'). + # + # 'pointsize': '10pt', + + # Additional stuff for the LaTeX preamble. + # + # 'preamble': '', + + # Latex figure (float) alignment + # + # 'figure_align': 'htbp', +} + +# Grouping the document tree into LaTeX files. List of tuples +# (source start file, target name, title, +# author, documentclass [howto, manual, or own class]). +latex_documents = [ + (master_doc, 'CV32A6-step1_Dvplan.tex', u'CORE-V-Docs Documentation', + u'Jean-Roch Coulon', 'manual'), +] + + +# -- Options for manual page output ------------------------------------------ + +# One entry per manual page. List of tuples +# (source start file, name, description, authors, manual section). +man_pages = [ + (master_doc, 'CV32A6-step1_Dvplan.tex', u'CORE-V-Docs Documentation', + [author], 1) +] + + +# -- Options for Texinfo output ---------------------------------------------- + +# Grouping the document tree into Texinfo files. List of tuples +# (source start file, target name, title, author, +# dir menu entry, description, category) +texinfo_documents = [ + (master_doc, 'CV32A6-step1_Dvplan.tex', u'CORE-V-Docs Documentation', + author, 'UserManual', 'User Manual for CV32A6-step1 CORE-V processor core.', + 'Miscellaneous'), +] + + +# -- Options for Epub output ------------------------------------------------- + +# Bibliographic Dublin Core info. +epub_title = project + +# The unique identifier of the text. This can be a ISBN number +# or the project homepage. +# +# epub_identifier = '' + +# A unique identification for the text. +# +# epub_uid = '' + +# A list of files that should not be packed into the epub file. +epub_exclude_files = ['search.html'] + + +# -- Extension configuration ------------------------------------------------- + +# -- Options for todo extension ---------------------------------------------- + +# If true, `todo` and `todoList` produce output, else they produce nothing. +todo_include_todos = True diff --git a/verif/docs/VerifPlans/source/dvplan_AXI.md b/verif/docs/VerifPlans/source/dvplan_AXI.md new file mode 100644 index 0000000000..a7399eca0f --- /dev/null +++ b/verif/docs/VerifPlans/source/dvplan_AXI.md @@ -0,0 +1,461 @@ +# Module: AXI + +## Feature: Burst + +### Sub-feature: 000_Control_Signals + +#### Item: 000 + +* **Requirement location:** AXI Design doc - Address structure +* **Feature Description** + + All transaction performed by CVA6 are of type INCR. AxBURST = 0b01 +* **Verification Goals** + + Ensure that AxBURST == 0b01 is always true while AX_VALID is asserted. +* **Pass/Fail Criteria:** Assertion +* **Test Type:** Constrained Random +* **Coverage Method:** Assertion Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_1_F005_S000_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** AXI Design doc - Address structure +* **Feature Description** + + All Read transaction performed by CVA6 are of burst lenght less or equal to 2. ARLEN = 0b01 +* **Verification Goals** + + Ensure that ARLEN == 0b01 is always true while AR_VALID is asserted. +* **Pass/Fail Criteria:** Assertion +* **Test Type:** Constrained Random +* **Coverage Method:** Assertion Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_1_F005_S000_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** AXI Design doc - Address structure +* **Feature Description** + + All write transaction performed by CVA6 are of burst lenght equal to 1. AWLEN = 0b00 +* **Verification Goals** + + Ensure that AWLEN == 0b00 is always true while AW_VALID is asserted. +* **Pass/Fail Criteria:** Assertion +* **Test Type:** Constrained Random +* **Coverage Method:** Assertion Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_1_F005_S000_I002 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 003 + +* **Requirement location:** https://developer.arm.com/documentation/ihi0022/hc - (Section A3.4.1) +* **Feature Description** + + The size of a read transfer does not exceed the width of the data interface. The maximum value can be taking by AxSIZE is 3. +* **Verification Goals** + + Ensure that AxSIZE <= log2(AXI_DATA_WIDTH/8) is always true while AR_VALID is asserted. +* **Pass/Fail Criteria:** Assertion +* **Test Type:** Constrained Random +* **Coverage Method:** Assertion Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_1_F005_S000_I003 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 007 + +* **Requirement location:** https://developer.arm.com/documentation/ihi0022/hc - (Section A7.2.4) +* **Feature Description** + + Exclusive access transactions cannot have a length greater than 16 beats +* **Verification Goals** + + Ensure that AxLOCK && AxLEN <= 15 is always true while AX_VALID is asserted. +* **Pass/Fail Criteria:** Assertion +* **Test Type:** Constrained Random +* **Coverage Method:** Assertion Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_1_F005_S000_I007 +* **Link to Coverage:** +* **Comments** + + *(none)* + +## Feature: Signals + +### Sub-feature: 000_ID + +#### Item: 000 + +* **Requirement location:** AXI Design doc - Transaction Identifiers +* **Feature Description** + + The CVA6 identify read transaction with an ID equal to 0 or 1 +* **Verification Goals** + + Ensure that ARID == 0b01 || ARID == 0b00 is always true while AR_VALID is asserted. +* **Pass/Fail Criteria:** Assertion +* **Test Type:** Constrained Random +* **Coverage Method:** Assertion Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_1_F006_S000_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** AXI Design doc - Transaction Identifiers +* **Feature Description** + + The CVA6 identify write transaction with an ID equal to 1 +* **Verification Goals** + + Ensure that AWID == 0b01 is always true while AW_VALID is asserted. +* **Pass/Fail Criteria:** Assertion +* **Test Type:** Constrained Random +* **Coverage Method:** Assertion Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_1_F006_S000_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 001_User + +#### Item: 000 + +* **Requirement location:** AXI Design doc - (table 2.2 and 2.5) +* **Feature Description** + + User-defined extension for the write and read address channel is not supported. AxUSER = 0b00 +* **Verification Goals** + + Ensure that AxUSER = 0b00 is always true while AX_VALID is asserted. +* **Pass/Fail Criteria:** Assertion +* **Test Type:** Constrained Random +* **Coverage Method:** Assertion Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_1_F006_S001_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** AXI Design doc - (table 2.4) +* **Feature Description** + + User-defined extension for the write response channel is not supported. +* **Verification Goals** + + Ensure that BUSER = 0b00 is always true while B_VALID is asserted. +* **Pass/Fail Criteria:** Assertion +* **Test Type:** Constrained Random +* **Coverage Method:** Assertion Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_1_F006_S001_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 002_Quality_of_Service + +#### Item: 000 + +* **Requirement location:** AXI Design doc - (table 2.2 and 2.5) +* **Feature Description** + + Quality of Service identifier is not supported. AxQOS = 0b0000 +* **Verification Goals** + + Ensure that AxQOS = 0b0000 is always true while AX_VALID is asserted. +* **Pass/Fail Criteria:** Assertion +* **Test Type:** Constrained Random +* **Coverage Method:** Assertion Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_1_F006_S002_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 003_Cache + +#### Item: 000 + +* **Requirement location:** AXI Design Doc - Transaction Attributes: Memory types +* **Feature Description** + + AxCACHE always take 0b0000. +* **Verification Goals** + + Ensure that AxCACHE = 0b0000 is always true while AX_VALID is asserted. +* **Pass/Fail Criteria:** Assertion +* **Test Type:** Constrained Random +* **Coverage Method:** Assertion Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_1_F006_S003_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 004_Protection + +#### Item: 000 + +* **Requirement location:** AXI Design Doc - (Table 2.2 and 2.5) +* **Feature Description** + + Protection attributes always take the 0b000 +* **Verification Goals** + + Ensure that AxPROT = 0b000 is always true while AX_VALID is asserted. +* **Pass/Fail Criteria:** Assertion +* **Test Type:** Constrained Random +* **Coverage Method:** Assertion Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_1_F006_S004_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 008_Region + +#### Item: 000 + +* **Requirement location:** AXI Design doc - (table 2.2 and 2.5) +* **Feature Description** + + Region indicator is not supported. AxREGION = 0b0000 +* **Verification Goals** + + Ensure that AxREGION = 0b0000 is always true while AX_VALID is asserted. +* **Pass/Fail Criteria:** Assertion +* **Test Type:** Constrained Random +* **Coverage Method:** Assertion Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_1_F006_S008_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +## Feature: Clock and Reset + +### Sub-feature: 000_Signals_Value + +#### Item: 000 + +* **Requirement location:** https://developer.arm.com/documentation/ihi0022/hc - (Section A3.1.2) +* **Feature Description** + + A value of X on [Ax | x]VALID is not permitted when not in reset +* **Verification Goals** + + Ensure that reset && [Ax | x]VALID != X is always true +* **Pass/Fail Criteria:** Assertion +* **Test Type:** ENV Capability +* **Coverage Method:** Assertion Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_1_F007_S000_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** https://developer.arm.com/documentation/ihi0022/hc - (Section A3.1.2) +* **Feature Description** + + A value of X on [Ax | x]READY is not permitted when not in reset +* **Verification Goals** + + Ensure that reset && [Ax | x]READY != X is always true +* **Pass/Fail Criteria:** Assertion +* **Test Type:** ENV Capability +* **Coverage Method:** Assertion Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_1_F007_S000_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** https://developer.arm.com/documentation/ihi0022/hc - (Figure A3-1) +* **Feature Description** + + [Ax | x]VALID is LOW for the first cycle after RESET goes HIGH +* **Verification Goals** + + Ensure that [Ax | x]VALID is low the first cycle after RESET +* **Pass/Fail Criteria:** Assertion +* **Test Type:** ENV Capability +* **Coverage Method:** Assertion Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_1_F007_S000_I002 +* **Link to Coverage:** +* **Comments** + + *(none)* + +## Feature: Handshake_Process + +### Sub-feature: 000_Stability + +#### Item: 000 + +* **Requirement location:** https://developer.arm.com/documentation/ihi0022/hc - (Section A3.2.2) +* **Feature Description** + + All signals must remain stable when [Ax | x]VALID is asserted and [Ax | x]READY is LOW +* **Verification Goals** + + Ensure that all the signals does not change while [Ax | x]VALID is asserted and [Ax | x]READY not yet asserted. +* **Pass/Fail Criteria:** Assertion +* **Test Type:** ENV Capability +* **Coverage Method:** Assertion Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_1_F008_S000_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** https://developer.arm.com/documentation/ihi0022/hc - (Section A3.2.1) +* **Feature Description** + + [Ax | x]VALID must remain asserted until [Ax | x]READY is HIGH +* **Verification Goals** + + Ensure that [Ax | x]VALID does not change while [Ax | x]READY is low. +* **Pass/Fail Criteria:** Assertion +* **Test Type:** ENV Capability +* **Coverage Method:** Assertion Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_1_F008_S000_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 001_Timing + +#### Item: 000 + +* **Requirement location:** https://developer.arm.com/documentation/ihi0022/hc - (Section A3.3.1) +* **Feature Description** + + The Manager must not wait for the Subordinate to assert ARREADY before asserting ARVALID +* **Verification Goals** + + Ensure that no errors are encountered as the testbench injects random Ready-to-Valid delays. There are two cases to consider: + + ARREADY is asserted on or after same cycle as ARVALID + ARREADY is asserted and deasserted during an interval when ARVALID is de-asserted +* **Pass/Fail Criteria:** Any/All +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_1_F008_S001_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** https://developer.arm.com/documentation/ihi0022/hc - (Section A3.3.1) +* **Feature Description** + + The Manager must not wait for the Subordinate to assert AWREADY before asserting AWVALID or WVALID. +* **Verification Goals** + + Ensure that no errors are encountered as the testbench injects random Ready-to-Valid delays. There are four cases to consider: + + AWREADY is asserted on or after same cycle as AWVALID and WVALID is de-asserted + AWREADY is asserted on or after same cycle as WVALID and AWVALID is de-asserted + AWREADY is asserted on or after same cycle as AWVALID and WVALID + AWREADY is asserted and deasserted during an interval when AWVALID and WVALID is de-asserted +* **Pass/Fail Criteria:** Any/All +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_1_F008_S001_I002 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 003 + +* **Requirement location:** https://developer.arm.com/documentation/ihi0022/hc - (Section A3.3.1) +* **Feature Description** + + The Manager must not wait for the Subordinate to assert WREADY before asserting AWVALID or WVALID. +* **Verification Goals** + + Ensure that no errors are encountered as the testbench injects random Ready-to-Valid delays. There are four cases to consider: + + WREADY is asserted on or after same cycle as AWVALID and WVALID is de-asserted + WREADY is asserted on or after same cycle as WVALID and AWVALID is de-asserted + WREADY is asserted on or after same cycle as AWVALID and WVALID + WREADY is asserted and deasserted during an interval when AWVALID and WVALID is de-asserted +* **Pass/Fail Criteria:** Any/All +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_1_F008_S001_I003 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 005 + +* **Requirement location:** https://developer.arm.com/documentation/ihi0022/hc - (Section A3.3.1) +* **Feature Description** + + The Subordinate must not wait for the Manager to assert [B | R]READY before asserting [B | R]VALID +* **Verification Goals** + + No specific “observable checks” to be made in simulation. Testbench will always provide response data independently of [B | R]READY. +* **Pass/Fail Criteria:** Any/All +* **Test Type:** Other +* **Coverage Method:** N/A +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_1_F008_S001_I005 +* **Link to Coverage:** +* **Comments** + + *(none)* + diff --git a/verif/docs/VerifPlans/source/dvplan_CVXIF.md b/verif/docs/VerifPlans/source/dvplan_CVXIF.md new file mode 100644 index 0000000000..ba6de7ee0f --- /dev/null +++ b/verif/docs/VerifPlans/source/dvplan_CVXIF.md @@ -0,0 +1,1074 @@ +# Module: CVXIF + +## Feature: Issue Interface + +### Sub-feature: 000_issue_req signals stable + +#### Item: 000 + +* **Requirement location:** https://github.com/openhwgroup/core-v-xif/blob/43dc03563e0c79cc55922f653406a9f122f61e80/docs/source/x_ext.rst +* **Feature Description** + + The “instr” and “mode” signals remain stable during an Issue request transaction. +* **Verification Goals** + + Check that “mode” and “instr” are stable during an issue transaction (cannot be modified by an instruction when transaction issue is in process) +* **Pass/Fail Criteria:** Assertion +* **Test Type:** Constrained Random +* **Coverage Method:** Assertion Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F000_S000_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 001_mode signal value + +#### Item: 000 + +* **Requirement location:** https://github.com/openhwgroup/core-v-xif/blob/43dc03563e0c79cc55922f653406a9f122f61e80/docs/source/x_ext.rst +* **Feature Description** + + When issue transaction starts, instruction and current CPU mode are provided +* **Verification Goals** + + Check that a mode modification coming from execution of a first instruction is well provided to the following offloaded instruction +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F000_S001_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** https://github.com/openhwgroup/core-v-xif/blob/43dc03563e0c79cc55922f653406a9f122f61e80/docs/source/x_ext.rst +* **Feature Description** + + Check “mode” signal values. +* **Verification Goals** + + Check that mode take a value that the CPU supports : Privilege level (2’b00 = User, 2’b01 = Supervisor, 2’b10 = Reserved, + 2’b11 = Machine). +* **Pass/Fail Criteria:** NDY (Not Defined Yet) +* **Test Type:** NDY (Not Defined Yet) +* **Coverage Method:** NDY (Not Defined Yet) +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F000_S001_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 002_rs_valid signal transition order + +#### Item: 000 + +* **Requirement location:** https://github.com/openhwgroup/core-v-xif/blob/43dc03563e0c79cc55922f653406a9f122f61e80/docs/source/x_ext.rst +* **Feature Description** + + During a transaction, each bit of “rs_valid” can transition from 0 to 1 but are not allowed to transition back to 0. +* **Verification Goals** + + For issue transaction which lasts more than one cycle, check that asserted “rs_valid” signals do not transition back to 0.(for i in [0;2] if rs_valid[i] = 1 then rs_valid[i] → 0 cannot happen) +* **Pass/Fail Criteria:** Assertion +* **Test Type:** Constrained Random +* **Coverage Method:** Assertion Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F000_S002_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 003_rs signal value + +#### Item: 000 + +* **Requirement location:** https://github.com/openhwgroup/core-v-xif/blob/43dc03563e0c79cc55922f653406a9f122f61e80/docs/source/x_ext.rst +* **Feature Description** + + If XLEN = X_RFR_WIDTH, then rs[X_NUM_RS-1:0] correspond to rs1 and rs2 CPU registers (and rs3 if X_NUM_RS = 3). +* **Verification Goals** + + For every issue transaction check that rs signal correspond to rs1,rs2(rs3) value in CPU register file. +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F000_S003_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** https://github.com/openhwgroup/core-v-xif/blob/43dc03563e0c79cc55922f653406a9f122f61e80/docs/source/x_ext.rst +* **Feature Description** + + rs signals are only required to be stable during the part of a transaction in which these signals are considered to be valid. +* **Verification Goals** + + Check that rs signals are stable when issue_valid==1 && the corresponding bit in rs_valid is 1. +* **Pass/Fail Criteria:** Assertion +* **Test Type:** NDY (Not Defined Yet) +* **Coverage Method:** Assertion Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F000_S003_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** https://github.com/openhwgroup/core-v-xif/blob/43dc03563e0c79cc55922f653406a9f122f61e80/docs/source/x_ext.rst +* **Feature Description** + + If XLEN != X_RFR_WIDTH , then rs[X_NUM_RS-1:0] correspond to even/odd register pair with rs1, rs2, (rs3) are even register and even register is provided in the 32 lower bits of rs signal. +* **Verification Goals** + + For every issue transaction check that rs signal correspond to the concatenation of rs1/rs1+1,rs2/rs2+1, (rs3/rs3+1) value in CPU register file and even register is in the 32 lower bits of rs. + + Can't be check XLEN == X_RFR_WIDTH +* **Pass/Fail Criteria:** NDY (Not Defined Yet) +* **Test Type:** NDY (Not Defined Yet) +* **Coverage Method:** NDY (Not Defined Yet) +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F000_S003_I002 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 004_Default value for unaccepted instruction + +#### Item: 000 + +* **Requirement location:** https://github.com/openhwgroup/core-v-xif/blob/43dc03563e0c79cc55922f653406a9f122f61e80/docs/source/x_ext.rst +* **Feature Description** + + If accept == 0 : + Writeback == 0; dualwrite == 0; dualread == 0; loadstore == 0; exc = 0. +* **Verification Goals** + + Check that for writeback; dualwrite; dualread; loadstore; exc signals if accept == 0 then all those signals are 0. +* **Pass/Fail Criteria:** Assertion +* **Test Type:** Constrained Random +* **Coverage Method:** Assertion Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F000_S004_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 005_Illegal Instruction causes + +#### Item: 000 + +* **Requirement location:** https://github.com/openhwgroup/core-v-xif/blob/43dc03563e0c79cc55922f653406a9f122f61e80/docs/source/x_ext.rst +* **Feature Description** + + The CPU shall cause an illegal instruction if: + - an instruction is considered to be valid by the CPU and accepted by the coprocessor (accept = 1) + - neither to be valid by the CPU nor accepted by the coprocessor (accept = 0) +* **Verification Goals** + + - CPU causes illegal instruction for instruction accepted by the core and the coprocessor. + - CPU causes illegal instruction exception for instruction that are not valid for coprocessor and CPU +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F000_S005_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 006_issue uniquness + +#### Item: 000 + +* **Requirement location:** https://github.com/openhwgroup/core-v-xif/blob/43dc03563e0c79cc55922f653406a9f122f61e80/docs/source/x_ext.rst +* **Feature Description** + + Check for issue id validity. +* **Verification Goals** + + Check that the issue interface doesn't issue an "id" that isn't legal to be used (has not fully completed). +* **Pass/Fail Criteria:** Other +* **Test Type:** Constrained Random +* **Coverage Method:** N/A +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F000_S006_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 007_coprocessor decoding + +#### Item: 000 + +* **Requirement location:** https://github.com/openhwgroup/core-v-xif/blob/43dc03563e0c79cc55922f653406a9f122f61e80/docs/source/x_ext.rst +* **Feature Description** + + Accept = 1 if: + - coprocessor can handle the instruction based on decoding “instr” and "mode". + - “issue_valid” == 1 and required bit(s) of “rs_valid” are 1. +* **Verification Goals** + + To be checked in coprocessor. +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F000_S007_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 008_Transaction definition + +#### Item: 000 + +* **Requirement location:** https://github.com/openhwgroup/core-v-xif/blob/43dc03563e0c79cc55922f653406a9f122f61e80/docs/source/x_ext.rst +* **Feature Description** + + “issue_resp” signals and “issue_req” signals are accepted when “issue_valid” == “issue_ready” == 1 + “issue_resp” is valid when "valid==ready==1". + “issue_req” is valid when "valid==1" +* **Verification Goals** + + The definition of a transaction. + Not to be verified. +* **Pass/Fail Criteria:** Other +* **Test Type:** Other +* **Coverage Method:** N/A +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F000_S008_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +## Feature: Commit Interface + +### Sub-feature: 000_commit_valid pulse + +#### Item: 000 + +* **Requirement location:** https://github.com/openhwgroup/core-v-xif/blob/43dc03563e0c79cc55922f653406a9f122f61e80/docs/source/x_ext.rst +* **Feature Description** + + The “commit_valid” == 1 exactly one clk cycle for every offloaded Instruction by the coprocessor (whether accepted or not). +* **Verification Goals** + + For every offloaded instruction, check that commit_valid is asserted exactly one clk cycle ( is a pulse ). +* **Pass/Fail Criteria:** Assertion +* **Test Type:** Constrained Random +* **Coverage Method:** Assertion Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F001_S000_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 001_commit transaction uniquness + +#### Item: 000 + +* **Requirement location:** https://github.com/openhwgroup/core-v-xif/blob/43dc03563e0c79cc55922f653406a9f122f61e80/docs/source/x_ext.rst +* **Feature Description** + + There is a unique commit transaction for every issue transaction (unique until an instruction has "fully completed" = its result has been submitted). +* **Verification Goals** + + Check that the commit interface doesn't commit an "id" that isn't legal to be used (hasn't been seen in earlier stages, or has not fully completed). +* **Pass/Fail Criteria:** Self-Check +* **Test Type:** Other +* **Coverage Method:** N/A +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F001_S001_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 002_commit transaction for every issue transaction + +#### Item: 000 + +* **Requirement location:** https://github.com/openhwgroup/core-v-xif/blob/43dc03563e0c79cc55922f653406a9f122f61e80/docs/source/x_ext.rst +* **Feature Description** + + - The CPU shall perform a commit transaction for every issue transaction, independent of the accept value of the issue transaction. + - For each offloaded and accepted instruction the core is guaranteed to (eventually) signal that such an instruction is either no longer speculative and can be committed (commit_valid is 1 and commit_kill is 0) or that the instruction must be killed (commit_valid is 1 and commit_kill is 1). +* **Verification Goals** + + Check that for each issue transaction, the commit transaction is sent at the same clock cycle than the issue transaction, or at any clock cycle after the issue transaction. +* **Pass/Fail Criteria:** Assertion +* **Test Type:** Constrained Random +* **Coverage Method:** Assertion Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F001_S002_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 003_Transaction definition + +#### Item: 000 + +* **Requirement location:** https://github.com/openhwgroup/core-v-xif/blob/43dc03563e0c79cc55922f653406a9f122f61e80/docs/source/x_ext.rst +* **Feature Description** + + The signals in commit are valid when commit_valid is 1. +* **Verification Goals** + + The definition of a transaction. + Not to be verified. +* **Pass/Fail Criteria:** Other +* **Test Type:** NDY (Not Defined Yet) +* **Coverage Method:** N/A +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F001_S003_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +## Feature: Result Interface + +### Sub-feature: 000_no speculative result transaction + +#### Item: 000 + +* **Requirement location:** https://github.com/openhwgroup/core-v-xif/blob/43dc03563e0c79cc55922f653406a9f122f61e80/docs/source/x_ext.rst +* **Feature Description** + + A coprocessor is not allowed to perform speculative result transactions. +* **Verification Goals** + + There is no result transaction for instructions that haven't been committed. Check that Result valid is only asserted for instructions that were committed (commit_valid == 1 && commit_kill == 0). +* **Pass/Fail Criteria:** Other +* **Test Type:** Other +* **Coverage Method:** N/A +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F002_S000_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 001_out of order result transaction + +#### Item: 000 + +* **Requirement location:** https://github.com/openhwgroup/core-v-xif/blob/43dc03563e0c79cc55922f653406a9f122f61e80/docs/source/x_ext.rst +* **Feature Description** + + A coprocessor is allowed to provide results to the core in an out of order fashion. +* **Verification Goals** + + Check that the CPU is able to receive the result in an out of order fashion. +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F002_S001_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 002_result transaction uniquness + +#### Item: 000 + +* **Requirement location:** https://github.com/openhwgroup/core-v-xif/blob/43dc03563e0c79cc55922f653406a9f122f61e80/docs/source/x_ext.rst +* **Feature Description** + + Each accepted offloaded (committed and not killed) instruction shall have exactly one result group transaction (even if no data needs to be written back to the CPU’s register file). +* **Verification Goals** + + There is an unique result transaction for every accepted and commit instruction. +* **Pass/Fail Criteria:** Other +* **Test Type:** Other +* **Coverage Method:** N/A +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F002_S002_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 003_result packet stability + +#### Item: 000 + +* **Requirement location:** https://github.com/openhwgroup/core-v-xif/blob/43dc03563e0c79cc55922f653406a9f122f61e80/docs/source/x_ext.rst +* **Feature Description** + + The signals in result shall remain stable during a result transaction (except data ...) +* **Verification Goals** + + Check that result signals (except data) are stable during result transaction (result_valid==1 jusqu'à valid==ready ==1) +* **Pass/Fail Criteria:** Assertion +* **Test Type:** Constrained Random +* **Coverage Method:** Assertion Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F002_S003_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 004_data stability + +#### Item: 000 + +* **Requirement location:** https://github.com/openhwgroup/core-v-xif/blob/43dc03563e0c79cc55922f653406a9f122f61e80/docs/source/x_ext.rst +* **Feature Description** + + Data is only required to remain stable during result transactions in which "we" is not 0. +* **Verification Goals** + + Check that "data" remains stable when we==1. +* **Pass/Fail Criteria:** Assertion +* **Test Type:** Constrained Random +* **Coverage Method:** Assertion Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F002_S004_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 005_synchronous exception + +#### Item: 000 + +* **Requirement location:** https://github.com/openhwgroup/core-v-xif/blob/43dc03563e0c79cc55922f653406a9f122f61e80/docs/source/x_ext.rst +* **Feature Description** + + The exc is used to signal synchronous exceptions. A synchronous exception will lead to a trap in CPU unless the corresponding instruction is killed. +* **Verification Goals** + + Check that synchronous exception (exc ==1) leads to a trap in the CPU if the instruction is committed. +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F002_S005_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** https://github.com/openhwgroup/core-v-xif/blob/43dc03563e0c79cc55922f653406a9f122f61e80/docs/source/x_ext.rst +* **Feature Description** + + exccode provides the least significant bits of the exception code bitfield of the mcause CSR. +* **Verification Goals** + + Check that exccode signal is the value of the mcause CSR when exc == 1. +* **Pass/Fail Criteria:** NDY (Not Defined Yet) +* **Test Type:** NDY (Not Defined Yet) +* **Coverage Method:** NDY (Not Defined Yet) +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F002_S005_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** https://github.com/openhwgroup/core-v-xif/blob/43dc03563e0c79cc55922f653406a9f122f61e80/docs/source/x_ext.rst +* **Feature Description** + + "we" shall be driven to 0 by the coprocessor for synchronous exceptions. +* **Verification Goals** + + Check that "we" signal == 0 when exc == 1. +* **Pass/Fail Criteria:** Assertion +* **Test Type:** NDY (Not Defined Yet) +* **Coverage Method:** Assertion Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F002_S005_I002 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 006_"we" value when dualwrite + +#### Item: 000 + +* **Requirement location:** https://github.com/openhwgroup/core-v-xif/blob/43dc03563e0c79cc55922f653406a9f122f61e80/docs/source/x_ext.rst +* **Feature Description** + + we is 2 bits wide when XLEN = 32 and X_RFW_WIDTH = 64, and 1 bit wide otherwise. If "we" is 2 bits wide, then we[1] is only allowed to be 1 if we[0] is 1 as well (i.e. for dual writeback). +* **Verification Goals** + + For dualwrite instruction, check that we[1]==1 is only allowed if we[0] == 1. + + Dualwrite not supported (for now) +* **Pass/Fail Criteria:** Assertion +* **Test Type:** Constrained Random +* **Coverage Method:** Assertion Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F002_S006_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 007_proper result transaction + +#### Item: 000 + +* **Requirement location:** https://github.com/openhwgroup/core-v-xif/blob/43dc03563e0c79cc55922f653406a9f122f61e80/docs/source/x_ext.rst +* **Feature Description** + + Result transaction starts in the cycle that result_valid = 1 and ends in the cycle that both result_valid == result_ready == 1. +* **Verification Goals** + + Check that result transaction ends properly. +* **Pass/Fail Criteria:** Assertion +* **Test Type:** Constrained Random +* **Coverage Method:** Assertion Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F002_S007_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +## Feature: Custom Instructions + +### Sub-feature: 000_CUS_ADD + +#### Item: 000 + +* **Requirement location:** ./custom_instruction.rst +* **Feature Description** + + cus_add rd, rs1, rs2 + rd = rs1 + rs2 + cus_add works in all privilege modes +* **Verification Goals** + + Register operands: + + All possible rs1 registers are used. + All possible rs2 registers are used. + All possible rd registers are used. + All possible register combinations where rs1 == rd are used + All possible register combinations where rs2 == rd are used +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F003_S000_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./custom_instruction.rst +* **Feature Description** + + cus_add rd, rs1, rs2 + rd = rs1 + rs2 + cus_add works in all privilege modes +* **Verification Goals** + + Input operands: + + rs1 value is +ve, -ve and zero + rs2 value is +ve, -ve and zero + All combinations of rs1 and rs2 +ve, -ve, and zero values are used + All bits of rs1 are toggled + All bits of rs2 are toggled +* **Pass/Fail Criteria:** NDY (Not Defined Yet) +* **Test Type:** NDY (Not Defined Yet) +* **Coverage Method:** NDY (Not Defined Yet) +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F003_S000_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./custom_instruction.rst +* **Feature Description** + + cus_add rd, rs1, rs2 + rd = rs1 + rs2 + cus_add works in all privilege modes +* **Verification Goals** + + Output result: + + rd value is +ve, -ve and zero + All bits of rd are toggled +* **Pass/Fail Criteria:** NDY (Not Defined Yet) +* **Test Type:** NDY (Not Defined Yet) +* **Coverage Method:** NDY (Not Defined Yet) +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F003_S000_I002 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 001_CUS_NOP + +#### Item: 000 + +* **Requirement location:** ./custom_instruction.rst +* **Feature Description** + + No operation Instruction +* **Verification Goals** + + Instruction executed +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F003_S001_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 003_CUS_S_ADD + +#### Item: 000 + +* **Requirement location:** ./custom_instruction.rst +* **Feature Description** + + cus_s_add rd, rs1, rs2 + rd = rs1 + rs2 + cus_s_add works in supervisor privilege mode +* **Verification Goals** + + Register operands: + + if (mode == s) + All possible rs1 registers are used. + All possible rs2 registers are used. + All possible rd registers are used. + All possible register combinations where rs1 == rd are used + All possible register combinations where rs2 == rd are used + + else if (mode != s) + illegal exception raised on hte CPU +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F003_S003_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./custom_instruction.rst +* **Feature Description** + + cus_s_add rd, rs1, rs2 + rd = rs1 + rs2 + cus_s_add works in supervisor privilege mode +* **Verification Goals** + + Input operands: + + if (mode == s) + rs1 value is +ve, -ve and zero + rs2 value is +ve, -ve and zero + All combinations of rs1 and rs2 +ve, -ve, and zero values are used + All bits of rs1 are toggled + All bits of rs2 are toggled + + else if (mode != s) + illegal exception raised on the CPU +* **Pass/Fail Criteria:** NDY (Not Defined Yet) +* **Test Type:** NDY (Not Defined Yet) +* **Coverage Method:** NDY (Not Defined Yet) +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F003_S003_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./custom_instruction.rst +* **Feature Description** + + cus_s_add rd, rs1, rs2 + rd = rs1 + rs2 + cus_s_add works in supervisor privilege mode +* **Verification Goals** + + Output operands: + + if (mode == s) + rd value is +ve, -ve and zero + All bits of rd are toggled + + else if (mode != s) + illegal exception raised on the CPU +* **Pass/Fail Criteria:** NDY (Not Defined Yet) +* **Test Type:** NDY (Not Defined Yet) +* **Coverage Method:** NDY (Not Defined Yet) +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F003_S003_I002 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 004_CUS_U_ADD + +#### Item: 000 + +* **Requirement location:** ./custom_instruction.rst +* **Feature Description** + + cus_u_add rd, rs1, rs2 + rd = rs1 + rs2 + cus_u_add works in User privilege mode +* **Verification Goals** + + Register operands: + + if (mode == u) + All possible rs1 registers are used. + All possible rs2 registers are used. + All possible rd registers are used. + All possible register combinations where rs1 == rd are used + All possible register combinations where rs2 == rd are used + + else if (mode != u) + illegal exception raised on hte CPU +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F003_S004_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./custom_instruction.rst +* **Feature Description** + + cus_u_add rd, rs1, rs2 + rd = rs1 + rs2 + cus_u_add works in User privilege mode +* **Verification Goals** + + Input operands: + + if (mode == u) + rs1 value is +ve, -ve and zero + rs2 value is +ve, -ve and zero + All combinations of rs1 and rs2 +ve, -ve, and zero values are used + All bits of rs1 are toggled + All bits of rs2 are toggled + + else if (mode != u) + illegal exception raised on the CPU +* **Pass/Fail Criteria:** NDY (Not Defined Yet) +* **Test Type:** NDY (Not Defined Yet) +* **Coverage Method:** NDY (Not Defined Yet) +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F003_S004_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./custom_instruction.rst +* **Feature Description** + + cus_u_add rd, rs1, rs2 + rd = rs1 + rs2 + cus_u_add works in User privilege mode +* **Verification Goals** + + Output operands: + + if (mode == u) + rd value is +ve, -ve and zero + All bits of rd are toggled + + else if (mode != u) + illegal exception raised on the CPU +* **Pass/Fail Criteria:** NDY (Not Defined Yet) +* **Test Type:** NDY (Not Defined Yet) +* **Coverage Method:** NDY (Not Defined Yet) +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F003_S004_I002 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 005_CUS_ADD_MULTI + +#### Item: 000 + +* **Requirement location:** ./custom_instruction.rst +* **Feature Description** + + cus_add_multi rd, rs1, rs2 + rd = rs1 + rs2 + cus_add_multi works in all privilege modes +* **Verification Goals** + + Register operands: + + All possible rs1 registers are used. + All possible rs2 registers are used. + All possible rd registers are used. + All possible register combinations where rs1 == rd are used + All possible register combinations where rs2 == rd are used +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F003_S005_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./custom_instruction.rst +* **Feature Description** + + cus_add_multi rd, rs1, rs2 + rd = rs1 + rs2 + cus_add_multi works in all privilege modes +* **Verification Goals** + + Input operands: + + rs1 value is +ve, -ve and zero + rs2 value is +ve, -ve and zero + All combinations of rs1 and rs2 +ve, -ve, and zero values are used + All bits of rs1 are toggled + All bits of rs2 are toggled +* **Pass/Fail Criteria:** NDY (Not Defined Yet) +* **Test Type:** NDY (Not Defined Yet) +* **Coverage Method:** NDY (Not Defined Yet) +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F003_S005_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./custom_instruction.rst +* **Feature Description** + + cus_add_multi rd, rs1, rs2 + rd = rs1 + rs2 + cus_add_multi works in all privilege modes +* **Verification Goals** + + Output result: + + rd value is +ve, -ve and zero + All bits of rd are toggled +* **Pass/Fail Criteria:** NDY (Not Defined Yet) +* **Test Type:** NDY (Not Defined Yet) +* **Coverage Method:** NDY (Not Defined Yet) +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F003_S005_I002 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 003 + +* **Requirement location:** ./custom_instruction.rst +* **Feature Description** + + cus_add_multi rd, rs1, rs2 + rd = rs1 + rs2 + cus_add_multi works in all privilege modes +* **Verification Goals** + + Check all delays from min to max +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F003_S005_I003 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 006_CUS_EXC + +#### Item: 000 + +* **Requirement location:** ./custom_instruction.rst +* **Feature Description** + + cus_exc imm[5:0] + mcause[5:0] = imm[5:0] + cus_exc raise an exception on the CPU base on the imm value +* **Verification Goals** + + Check all possible imm value +* **Pass/Fail Criteria:** NDY (Not Defined Yet) +* **Test Type:** NDY (Not Defined Yet) +* **Coverage Method:** NDY (Not Defined Yet) +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F003_S006_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 007_CUS_ADD_RS3 + +#### Item: 000 + +* **Requirement location:** ./custom_instruction.rst +* **Feature Description** + + cus_add_rs3 rd, rs1, rs2, rs3 + rd = rs1 + rs2 + rs3 + cus_add_rs3 works in all privilege modes + + X_NUM_RS == 3 +* **Verification Goals** + + Register operands: + + if (X_NUM_RS == 3) + All possible rs1 registers are used. + All possible rs2 registers are used. + All possible rs3 registers are used. + All possible rd registers are used. + All possible register combinations where rs1 == rd are used + All possible register combinations where rs2 == rd are used + All possible register combinations where rs3 == rd are used + + + else if (X_NUM_RS != 3) + illegal exception raised on the CPU +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F003_S007_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./custom_instruction.rst +* **Feature Description** + + cus_add_rs3 rd, rs1, rs2, rs3 + rd = rs1 + rs2 + rs3 + cus_add_rs3 works in all privilege modes + + X_NUM_RS == 3 +* **Verification Goals** + + Input operands: + + if (X_NUS_RS == 3) + rs1 value is +ve, -ve and zero + rs2 value is +ve, -ve and zero + rs3 value is +ve, -ve and zero + All combinations of rs1, rs2 and rs3 +ve, -ve, and zero values are used + All bits of rs1 are toggled + All bits of rs2 are toggled + All bits of rs3 are toggled + + else if (X_NUM_RS != 3) + illegal exception raised on the CPU +* **Pass/Fail Criteria:** NDY (Not Defined Yet) +* **Test Type:** NDY (Not Defined Yet) +* **Coverage Method:** NDY (Not Defined Yet) +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F003_S007_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./custom_instruction.rst +* **Feature Description** + + cus_add_rs3 rd, rs1, rs2, rs3 + rd = rs1 + rs2 + rs3 + cus_add_rs3 works in all privilege modes + + X_NUM_RS == 3 +* **Verification Goals** + + Output operands: + + if (X_NUM_RS == 3) + rd value is +ve, -ve and zero + All bits of rd are toggled + + else if (X_NUM_RS != 3) + illegal exception raised on the CPU +* **Pass/Fail Criteria:** NDY (Not Defined Yet) +* **Test Type:** NDY (Not Defined Yet) +* **Coverage Method:** NDY (Not Defined Yet) +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_CVXIF_F003_S007_I002 +* **Link to Coverage:** +* **Comments** + + *(none)* + diff --git a/verif/docs/VerifPlans/source/dvplan_FENCEI.md b/verif/docs/VerifPlans/source/dvplan_FENCEI.md new file mode 100644 index 0000000000..2f77ee43e2 --- /dev/null +++ b/verif/docs/VerifPlans/source/dvplan_FENCEI.md @@ -0,0 +1,439 @@ +# Module: FENCEI + +## Feature: Fetching + +### Sub-feature: 000_Fetching + +#### Item: 000 + +* **Requirement location:** CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fence +* **Feature Description** + + Instruction data for the next PC must be fetched after the fence.i instruction has executed (because only then can data-side stores have completed and caches have been updated). +* **Verification Goals** + + Check that after a fence.i instruction retires then instr-side obi fetches the next instruction to be executed. +* **Pass/Fail Criteria:** Assertion +* **Test Type:** ENV Capability +* **Coverage Method:** Assertion Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_FENCEI_F000_S000_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +## Feature: StoresVisible + +### Sub-feature: 000_StoresVisible + +#### Item: 000 + +* **Requirement location:** The RISC-V Instruction Set Manual +Volume I: Unprivileged ISA +Document Version 20191213 +https://riscv.org/wp-content/uploads/2019/12/riscv-spec-20191213.pdf +* **Feature Description** + + After a fence.i instruction has been executed, all preceding store instructions shall have their effects visible to the instruction fetch of the instructions that are to be executed after the fence.i instruction. +* **Verification Goals** + + Do a fencei, but right before the fencei do a store to the instruction following the fencei, then see that the newly stored value is executed instead of the old instruction (e.g. change addi to use a different immediate). +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_FENCEI_F001_S000_I000 +* **Link to Coverage:** +* **Comments** + + TODO must be added to regression lists! +#### Item: 001 + +* **Requirement location:** The RISC-V Instruction Set Manual +Volume I: Unprivileged ISA +Document Version 20191213 +https://riscv.org/wp-content/uploads/2019/12/riscv-spec-20191213.pdf +* **Feature Description** + + After a fence.i instruction has been executed, all preceding store instructions shall have their effects visible to the instruction fetch of the instructions that are to be executed after the fence.i instruction. +* **Verification Goals** + + Do a fencei followed by any instruction, but let the environment detect when the fencei is being executed and change the memory holding the next instruction, then see that the old instruction is not executed. +* **Pass/Fail Criteria:** NDY (Not Defined Yet) +* **Test Type:** Directed Non-SelfChk +* **Coverage Method:** NDY (Not Defined Yet) +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_FENCEI_F001_S000_I001 +* **Link to Coverage:** +* **Comments** + + TODO missing cover! +#### Item: 002 + +* **Requirement location:** The RISC-V Instruction Set Manual +Volume I: Unprivileged ISA +Document Version 20191213 +https://riscv.org/wp-content/uploads/2019/12/riscv-spec-20191213.pdf +* **Feature Description** + + After a fence.i instruction has been executed, all preceding store instructions shall have their effects visible to the instruction fetch of the instructions that are to be executed after the fence.i instruction. +* **Verification Goals** + + Let the instruction right before a fence.i write a different instruction to the address following the fence.i, then observe that the written instruction is executed instead of the original one and that no side-effects (csr updates or otherwise) occur (can possibly mix 16bit/32bit instructions to force a noticable difference). +* **Pass/Fail Criteria:** Self-Check +* **Test Type:** Directed SelfChk +* **Coverage Method:** Testcase +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_FENCEI_F001_S000_I002 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 003 + +* **Requirement location:** The RISC-V Instruction Set Manual +Volume I: Unprivileged ISA +Document Version 20191213 +https://riscv.org/wp-content/uploads/2019/12/riscv-spec-20191213.pdf +* **Feature Description** + + After a fence.i instruction has been executed, all preceding store instructions shall have their effects visible to the instruction fetch of the instructions that are to be executed after the fence.i instruction. +* **Verification Goals** + + Check that after having read one value from an address, then after storing a value to that same address, if executing that address then the value shall always be that which was written (should work well in both sim/formal). +* **Pass/Fail Criteria:** Assertion +* **Test Type:** ENV Capability +* **Coverage Method:** Assertion Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_FENCEI_F001_S000_I003 +* **Link to Coverage:** +* **Comments** + + TODO missing assert. (Note was ignored because of the difficulty of writing this as an assert for fv.)! +## Feature: ExternalHandshake + +### Sub-feature: 000_ReqHigh + +#### Item: 000 + +* **Requirement location:** CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fence +* **Feature Description** + + When executing a fence.i instruction, fencei_flush_req_o shall rise sometime before executing the next instruction. +* **Verification Goals** + + Check that when executing a fence.i instruction there will be a rising req before has retired. +* **Pass/Fail Criteria:** Assertion +* **Test Type:** ENV Capability +* **Coverage Method:** Assertion Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_FENCEI_F002_S000_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 001_ReqWaitLsu + +#### Item: 000 + +* **Requirement location:** CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fenceThis is a pointer to the source Requirements document of the Features in question. The pointer should state the version of the target document. It is free-form, so it can also indicate the specific section/page/paragraph. +* **Feature Description** + + When executing a fence.i instruction, if there is an ongoing store instruction (not limited to rv32i) that has not completed (data_rvalid_i clocked in as 1), then fencei_flush_req_o shall be low. +* **Verification Goals** + + Make sure a store instruction is run right before a fence.i, and (possibly using obi stalls) ensure that the fence.i is pending retirement but holds off until the store's data_rvalid_i is clocked in and that fencei_flush_req_o was low until this point where it now goes high. +* **Pass/Fail Criteria:** Assertion +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_FENCEI_F002_S001_I000 +* **Link to Coverage:** +* **Comments** + + TODO missing cover! +### Sub-feature: 002_ReqWaitWritebuffer + +#### Item: 000 + +* **Requirement location:** CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fence +* **Feature Description** + + When executing a fence.i instruction, if the write buffer is not empty, then fencei_flush_req_o shall be low until the write buffer has been emptied and the corresponding data_rvalid_i have been clocked in as 1. +* **Verification Goals** + + Fill up the write buffer prior to executing a fence.i and ensure that fencei_flush_req_o holds off going high until the write buffer to has been emptied. +* **Pass/Fail Criteria:** Assertion +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_FENCEI_F002_S002_I000 +* **Link to Coverage:** +* **Comments** + + TODO missing cover! +### Sub-feature: 003_ReqWaitXinterface + +#### Item: 000 + +* **Requirement location:** CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fence +* **Feature Description** + + When executing a fence.i instruction, if the X interface is busy with any store operations, then fencei_flush_req_o shall be low until all the store operations are done +* **Verification Goals** + + Issue one or more store instructions that uses the X interface and ensure that fencei_flush_req_o waits until the stores have all completed before going high. +* **Pass/Fail Criteria:** Assertion +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_FENCEI_F002_S003_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 004_ReqWaitObi + +#### Item: 000 + +* **Requirement location:** CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fenceThis is a pointer to the source Requirements document of the Features in question. The pointer should state the version of the target document. It is free-form, so it can also indicate the specific section/page/paragraph. +* **Feature Description** + + fencei_flush_req_o shall not go high while there are outstanding stores on the obi bus. +* **Verification Goals** + + Check vs the OBI monitors that there are no outstanding stores at the time fencei_flush_req_o goes high. +* **Pass/Fail Criteria:** Assertion +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_FENCEI_F002_S004_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 005_ReqLow + +#### Item: 000 + +* **Requirement location:** CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fenceThis is a pointer to the source Requirements document of the Features in question. The pointer should state the version of the target document. It is free-form, so it can also indicate the specific section/page/paragraph. +* **Feature Description** + + When fencei_flush_req_o is high, it shall stay high until fencei_flush_req_o and fencei_flush_ack_i has been sampled high simultaneously, and then then it shall go low. +* **Verification Goals** + + Check that when fencei_flush_req_o is high, then it behaves correctly with regards to fencei_flush_ack_i. +* **Pass/Fail Criteria:** Assertion +* **Test Type:** ENV Capability +* **Coverage Method:** Assertion Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_FENCEI_F002_S005_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 006_AckChange + +#### Item: 000 + +* **Requirement location:** CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fenceThis is a pointer to the source Requirements document of the Features in question. The pointer should state the version of the target document. It is free-form, so it can also indicate the specific section/page/paragraph. +* **Feature Description** + + fencei_flush_ack_i is allowed to change freely on any clock cycle: It can be permanently high, go high without fence.i and retract, go high at the same cycle as the req, it can delay arbitrarily after req and then go high, etc +* **Verification Goals** + + Drive ack to test all permutations of rising/falling before/after/on req, acking without req, retracting an early ack, delaying ack after req, etc. +* **Pass/Fail Criteria:** Any/All +* **Test Type:** ENV Capability +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_FENCEI_F002_S006_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 007_AckWithold + +#### Item: 000 + +* **Requirement location:** CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fence +* **Feature Description** + + If req is high, but ack never comes, then the core keeps on stalling and the fence.i is blocked from completing. +* **Verification Goals** + + Upon a req, try witholding ack for a long time and see that the fence.i can be stalled arbitrarily long (should have covers for ack delays of at least {[0:5]}). +* **Pass/Fail Criteria:** Assertion +* **Test Type:** ENV Capability +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_FENCEI_F002_S007_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 008_BranchInitiated + +#### Item: 000 + +* **Requirement location:** CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fenceThis is a pointer to the source Requirements document of the Features in question. The pointer should state the version of the target document. It is free-form, so it can also indicate the specific section/page/paragraph. +* **Feature Description** + + After req and ack has been sampled simultaneously high and when req is low again, then the core takes a branch to the instruction after the fence.i instruction. +* **Verification Goals** + + Check that the branch is taken at the point after req and ack has been simultaneously high. +* **Pass/Fail Criteria:** Assertion +* **Test Type:** ENV Capability +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_FENCEI_F002_S008_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 009_ShadowingBranch + +#### Item: 000 + +* **Requirement location:** CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fence +* **Feature Description** + + If the fence.i ends up not retiring because it was preceeded by a taken branch or a jump, then the fencei_flush_req_o shall not go high +* **Verification Goals** + + Take a branch or do a jump to skip a fence.i, and ensure that fencei_flush_req_o doesn't go high. +* **Pass/Fail Criteria:** Assertion +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_FENCEI_F002_S009_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +## Feature: MultiCycle + +### Sub-feature: 000_MultiCycle + +#### Item: 000 + +* **Requirement location:** CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fence +* **Feature Description** + + Given zero stalls on neither instr-side and data-side obi nor on fencei_flush_ack_i, then the execution of fence.i takes a fixed number of cycles. +* **Verification Goals** + + Check that, given ideal conditions, the cycle count of fence.i is as expected. +* **Pass/Fail Criteria:** Assertion +* **Test Type:** ENV Capability +* **Coverage Method:** Assertion Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_FENCEI_F003_S000_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +## Feature: StoresComplete + +### Sub-feature: 000_StoresComplete + +#### Item: 000 + +* **Requirement location:** CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fenceThis is a pointer to the source Requirements document of the Features in question. The pointer should state the version of the target document. It is free-form, so it can also indicate the specific section/page/paragraph. +* **Feature Description** + + Any store instruction that is successfully executed before a fence.i will fully complete and have its effect visible (this is not about syncronization with instruction fetch, but rather seeing that the stores are not aborted). +* **Verification Goals** + + Check that all stores (either to next pc or other places) preceding a fence.i will complete on the bus (excluding exceptions/interrupts/etc) and be readable afterwards (particularly, ensure that the write buffer isn't just purged). +* **Pass/Fail Criteria:** Self-Check +* **Test Type:** Directed SelfChk +* **Coverage Method:** Testcase +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_FENCEI_F004_S000_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 001_StoresComplete + +#### Item: 000 + +* **Requirement location:** CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fence +* **Feature Description** + + Any store instruction that is successfully executed before a fence.i will fully complete and have its effect visible (this is not about syncronization with instruction fetch, but rather seeing that the stores are not aborted). +* **Verification Goals** + + Check that all stores (either to next pc or other places) preceding a fence.i will complete on the bus (excluding exceptions/interrupts/etc) and be readable afterwards (particularly, ensure that the write buffer isn't just purged). +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Testcase +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_FENCEI_F004_S001_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +## Feature: Flush + +### Sub-feature: 000_Flush + +#### Item: 000 + +* **Requirement location:** CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fence +* **Feature Description** + + When fence.i is executed, then any prefetched instructions shall be flushed; meaning that pipeline stages are flushed, prefetcher is flushed, write buffer is flushed, and data_req_o is eventually supressed. +* **Verification Goals** + + Check that a fence.i will cause flushing of the pipeline, prefetcher, write buffer, and data_req_o. +* **Pass/Fail Criteria:** Assertion +* **Test Type:** ENV Capability +* **Coverage Method:** Assertion Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_FENCEI_F005_S000_I000 +* **Link to Coverage:** +* **Comments** + + TODO missing assert. (Have not checked/covered that the pipeline/writebuffer content is actually purged. Or that any memory change WILL be the next instr word.)! +## Feature: UnusedFields + +### Sub-feature: 000_UnusedFields + +#### Item: 000 + +* **Requirement location:** The RISC-V Instruction Set Manual +Volume I: Unprivileged ISA +Document Version 20191213 +https://riscv.org/wp-content/uploads/2019/12/riscv-spec-20191213.pdf +* **Feature Description** + + imm[11:0], rs1, rd are reserved for future extensions, and implementations shall ignore them +* **Verification Goals** + + Try giving random values in those fields and see that all else works as expected +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_FENCEI_F006_S000_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + diff --git a/verif/docs/VerifPlans/source/dvplan_FRONTEND.md b/verif/docs/VerifPlans/source/dvplan_FRONTEND.md new file mode 100644 index 0000000000..0910860f26 --- /dev/null +++ b/verif/docs/VerifPlans/source/dvplan_FRONTEND.md @@ -0,0 +1,331 @@ +# Module: FRONTEND + +## Feature: PC generation stage + +### Sub-feature: 001_BTB + +#### Item: 002 + +* **Requirement location:** FRONTEND sub-system/functionality/PC generation stage/Branch Predict +* **Feature Description** + + If instruction is a JALR and BTB (Branch Target Buffer) returns a valid address, next PC is predicted by BTB. + + Else JALR is not considered as a control flow instruction, which will generate a mispredict. +* **Verification Goals** + + Execute test with JALR instructions. Functional cov: JALR is executed and BTB output is not valid. +* **Pass/Fail Criteria:** Check RM +* **Test Type:** RISC-V Arch-test +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0 +* **Unique verification tag:** VP_FRONTEND_F003_S001_I002 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 002_BHT + +#### Item: 002 + +* **Requirement location:** FRONTEND sub-system/functionality/PC generation stage/Branch Predict +* **Feature Description** + + If instruction is a branch and BTH (Branch History table) returns a valid address, next PC is predicted by BHT. Else branch is not considered as an control flow instruction, which will generate a mispredict when branch is taken. +* **Verification Goals** + + Execute test with BRANCH instructions. Functional cov: a BRANCH is executed, BTB output is not valid and the branch is taken. +* **Pass/Fail Criteria:** Check RM +* **Test Type:** RISC-V Arch-test +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0 +* **Unique verification tag:** VP_FRONTEND_F003_S002_I002 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 003_RAS + +#### Item: 002 + +* **Requirement location:** FRONTEND sub-system/functionality/PC generation stage/Branch Predict +* **Feature Description** + + If instruction is a RET and RAS (Return Address Stack) returns a valid address and RET has already been consummed by instruction queue. Else RET is considered as a control flow instruction but next PC is not predicted. A mispredict wil be generated. +* **Verification Goals** + + Execute test with RET instructions. Functional cov: RET is executed and RAS output is not valid. +* **Pass/Fail Criteria:** Check RM +* **Test Type:** RISC-V Arch-test +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0 +* **Unique verification tag:** VP_FRONTEND_F003_S003_I002 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 004_Return from environment call + +#### Item: 000 + +* **Requirement location:** FRONTEND sub-system/functionality/PC generation stage/Return from env call +* **Feature Description** + + When CSR asks a return from an environment call, the PC is assigned to the successive PC to the one stored in the CSR [m-s]epc register. +* **Verification Goals** + + Set two different addresses for mepc and sepc in CSR registers. Use a arc_test returning from machine env call. + + * Check by assertion that when machine return occurs the mepc address is fetched. + * Functional cov: execute a machine return. +* **Pass/Fail Criteria:** Assertion +* **Test Type:** RISC-V Arch-test +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0 +* **Unique verification tag:** VP_FRONTEND_F003_S004_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** FRONTEND sub-system/functionality/PC generation stage/Return from env call +* **Feature Description** + + When CSR asks a return from an environment call, the PC is assigned to the successive PC to the one stored in the CSR [m-s]epc register. +* **Verification Goals** + + Set two different addresses for mepc and sepc in CSR registers. Use a returning from supervisor env call. + + * Check by assertion that when supervisor return occurs the sepc address is fetched. + * Functional cov: execute a supervisor return. +* **Pass/Fail Criteria:** Assertion +* **Test Type:** RISC-V Arch-test +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2 +* **Unique verification tag:** VP_FRONTEND_F003_S004_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 005_Exception/Interrupt + +#### Item: 000 + +* **Requirement location:** FRONTEND sub-system/functionality/PC generation stage/Exception +* **Feature Description** + + If an exception (or interrupt, which is in the context of RISC-V systems quite similar) is triggered by the COMMIT, the next PC Gen is assigned to the CSR trap vector base address. The trap vector base address can be different depending on whether the exception traps to S-Mode or M-Mode (user mode exceptions are currently not supported) +* **Verification Goals** + + Set two different addresses for machine and supervisor handlers in CSR registers. Use a test which executes in machine mode and generates a machine exception by UVM. Check by assertion that when machine exception occurs the machine address is fetched. Functional cov: exception occurs in machine mode. +* **Pass/Fail Criteria:** Assertion +* **Test Type:** RISC-V Arch-test +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0 +* **Unique verification tag:** VP_FRONTEND_F003_S005_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 006_Pipeline flush + +#### Item: 000 + +* **Requirement location:** FRONTEND sub-system/functionality/PC generation stage/Pipeline flush +* **Feature Description** + + FRONTEND starts fetching from the next instruction again in order to take the up-dated information into account +* **Verification Goals** + + [no need to verify this point] +* **Pass/Fail Criteria:** NDY (Not Defined Yet) +* **Test Type:** NDY (Not Defined Yet) +* **Coverage Method:** NDY (Not Defined Yet) +* **Applicable Cores:** CV32A6_v0.1.0 +* **Unique verification tag:** VP_FRONTEND_F003_S006_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 007_Debug + +### Sub-feature: 008_Address mapping change + +### Sub-feature: 009_Pc gen priority + +#### Item: 000 + +* **Requirement location:** FRONTEND sub-system/functionality/PC generation stage +* **Feature Description** + + The next PC can originate from the following sources (listed in order of precedence) +* **Verification Goals** + + Use arc_test executing return from env call and generate Exceptions by UVM during reset, Branch predict, default, mispredict, replay and return from env call. Functional cov: monitor the 6 events +* **Pass/Fail Criteria:** Check RM +* **Test Type:** RISC-V Arch-test +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0 +* **Unique verification tag:** VP_FRONTEND_F003_S009_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** FRONTEND sub-system/functionality/PC generation stage +* **Feature Description** + + The next PC can originate from the following sources (listed in order of precedence) +* **Verification Goals** + + [other cases to be elaborated] +* **Pass/Fail Criteria:** NDY (Not Defined Yet) +* **Test Type:** NDY (Not Defined Yet) +* **Coverage Method:** NDY (Not Defined Yet) +* **Applicable Cores:** CV32A6_v0.1.0 +* **Unique verification tag:** VP_FRONTEND_F003_S009_I002 +* **Link to Coverage:** +* **Comments** + + *(none)* + +## Feature: BTB + +### Sub-feature: 000_flush + +### Sub-feature: 001_table depth + +### Sub-feature: 002_Table update + +### Sub-feature: 003_debug is not intrusive + +## Feature: BHT + +### Sub-feature: 000_flush + +### Sub-feature: 002_table update + +### Sub-feature: 003_saturation + +#### Item: 000 + +* **Requirement location:** FRONTEND sub-system/Architecture and Modules/BHT +* **Feature Description** + + The Branch History table is a two-bit saturation counter that takes the virtual address of the current fetched instruction by the CACHE. It states whether the current branch request should be taken or not. The two bit counter is updated by the successive execution of the current instructions as shown in the following figure. +* **Verification Goals** + + Execute a serie of taken and not taken branch to check the saturation mechanism +* **Pass/Fail Criteria:** NDY (Not Defined Yet) +* **Test Type:** NDY (Not Defined Yet) +* **Coverage Method:** NDY (Not Defined Yet) +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_FRONTEND_F005_S003_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 004_Table depth + +### Sub-feature: 005_Debug is not intrusive + +## Feature: RAS + +### Sub-feature: 000_flush + +### Sub-feature: 001_table depth + +### Sub-feature: 002_Table update + +### Sub-feature: 003_Debug is not intrusive + +## Feature: Instr_realign + +### Sub-feature: 000_C extension + +### Sub-feature: 001_Flush + +## Feature: Instr_queue + +### Sub-feature: 000_FIFO depth + +#### Item: 000 + +* **Requirement location:** FRONTEND sub-system/Architecture and Modules/Instr_queue +* **Feature Description** + + The instruction queue contains max 4 instructions. +* **Verification Goals** + + Confirm that the best configuration for instruction queue entry number is 4 by monitoring the Coremark performance and silicon footprint +* **Pass/Fail Criteria:** Other +* **Test Type:** Other +* **Coverage Method:** N/A +* **Applicable Cores:** CV32A6_v0.1.0 +* **Unique verification tag:** VP_FRONTEND_F008_S000_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 001_Page fault exception + +### Sub-feature: 002_Flush + +## Feature: Instr_scan + +## Feature: Fetch stage + +### Sub-feature: 001_MMU translation + +### Sub-feature: 002_Exceptions + +#### Item: 000 + +* **Requirement location:** FRONTEND sub-system/functionality/Fetch stage +* **Feature Description** + + Memory and MMU (MMU is not enabled in CV32A6-step1) can feedback potential exceptions generated by the memory fetch request. They can be bus errors, invalid accesses or instruction page faults. +* **Verification Goals** + + Generate a bus error exception by UVM or by test (to be decided) and check that the exception address is fetched. Functional cov: a bus error exception occurs. +* **Pass/Fail Criteria:** NDY (Not Defined Yet) +* **Test Type:** NDY (Not Defined Yet) +* **Coverage Method:** NDY (Not Defined Yet) +* **Applicable Cores:** CV32A6_v0.1.0 +* **Unique verification tag:** VP_FRONTEND_F010_S002_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** FRONTEND sub-system/functionality/Fetch stage +* **Feature Description** + + Memory and MMU (MMU is not enabled in CV32A6-step1) can feedback potential exceptions generated by the memory fetch request. They can be bus errors, invalid accesses or instruction page faults. +* **Verification Goals** + + Generate an invalid access exception by UVM or by test (to be decided) and check that the exception address is fetched. Functional cov: an invalid access exception occurs. +* **Pass/Fail Criteria:** NDY (Not Defined Yet) +* **Test Type:** NDY (Not Defined Yet) +* **Coverage Method:** NDY (Not Defined Yet) +* **Applicable Cores:** CV32A6_v0.1.0 +* **Unique verification tag:** VP_FRONTEND_F010_S002_I002 +* **Link to Coverage:** +* **Comments** + + *(none)* + diff --git a/verif/docs/VerifPlans/source/dvplan_ISA_RV32.md b/verif/docs/VerifPlans/source/dvplan_ISA_RV32.md new file mode 100644 index 0000000000..dcf09dc326 --- /dev/null +++ b/verif/docs/VerifPlans/source/dvplan_ISA_RV32.md @@ -0,0 +1,7191 @@ +# Module: ISA RISC-V 32b + +## Feature: RV32I Register-Immediate Instructions + +### Sub-feature: 000_ADDI + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + addi rd, rs1, imm[11:0] + rd = rs1 + Sext(imm[11:0]) + Arithmetic overflow is lost and ignored +* **Verification Goals** + + Register operands: + + All possible rs1 registers are used. + All possible rd registers are used. + All possible register combinations where rs1 == rd are used +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F000_S000_I000 +* **Link to Coverage:** isacov.rv32i_addi_cg.cp_rs1 +isacov.rv32i_addi_cg.cp_rd +isacov.rv32i_addi_cg.cp_rd_rs1_hazard +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + addi rd, rs1, imm[11:0] + rd = rs1 + Sext(imm[11:0]) + Arithmetic overflow is lost and ignored +* **Verification Goals** + + Input operands: + + rs1 value is +ve, -ve and zero + immi value is +ve, -ve and zero + All combinations of rs1 and immi +ve, -ve, and zero values are used + All bits of rs1 are toggled + All bits of immi are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F000_S000_I001 +* **Link to Coverage:** isacov.rv32i_addi_cg.cp_rs1_value +isacov.rv32i_addi_cg.cp_immi_value +isacov.rv32i_addi_cg.cross_rs1_immi_value +isacov.rv32i_addi_cg.cp_rs1_toggle +isacov.rv32i_addi_cg.cp_immi_toggle +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + addi rd, rs1, imm[11:0] + rd = rs1 + Sext(imm[11:0]) + Arithmetic overflow is lost and ignored +* **Verification Goals** + + Output result: + + rd value is +ve, -ve and zero + All bits of rd are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F000_S000_I002 +* **Link to Coverage:** isacov.rv32i_addi_cg.cp_rd_value +isacov.rv32i_addi_cg.cp_rd_toggle +* **Comments** + + *(none)* + +### Sub-feature: 001_XORI + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + xori rd, rs1, imm[11:0] + rd = rs1 ^ Sext(imm[11:0]) + Note: this is a bitwise, not logical operation +* **Verification Goals** + + Register operands: + + All possible rs1 registers are used. + All possible rd registers are used. + All possible register combinations where rs1 == rd are used +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F000_S001_I000 +* **Link to Coverage:** isacov.rv32i_xori_cg.cp_rs1 +isacov.rv32i_xori_cg.cp_rd +isacov.rv32i_xori_cg.cp_rd_rs1_hazard +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + xori rd, rs1, imm[11:0] + rd = rs1 ^ Sext(imm[11:0]) + Note: this is a bitwise, not logical operation +* **Verification Goals** + + Input operands: + + rs1 value is +ve, -ve and zero + immi value is +ve, -ve and zero + All combinations of rs1 and immi +ve, -ve, and zero values are used + All bits of rs1 are toggled + All bits of immi are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F000_S001_I001 +* **Link to Coverage:** isacov.rv32i_xori_cg.cp_rs1_value +isacov.rv32i_xori_cg.cp_immi_value +isacov.rv32i_xori_cg.cross_rs1_immi_value +isacov.rv32i_xori_cg.cp_rs1_toggle +isacov.rv32i_xori_cg.cp_immi_toggle +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + xori rd, rs1, imm[11:0] + rd = rs1 ^ Sext(imm[11:0]) + Note: this is a bitwise, not logical operation +* **Verification Goals** + + Output result: + + rd value is +ve, -ve and zero + All bits of rd are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F000_S001_I002 +* **Link to Coverage:** isacov.rv32i_xori_cg.cp_rd_value +isacov.rv32i_xori_cg.cp_rd_toggle +* **Comments** + + *(none)* + +### Sub-feature: 002_ORI + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + ori rd, rs1, imm[11:0] + rd = rs1 | Sext(imm[11:0]) + Note: this is a bitwise, not logical operation +* **Verification Goals** + + Register operands: + + All possible rs1 registers are used. + All possible rd registers are used. + All possible register combinations where rs1 == rd are used +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F000_S002_I000 +* **Link to Coverage:** isacov.rv32i_ori_cg.cp_rs1 +isacov.rv32i_ori_cg.cp_rd +isacov.rv32i_ori_cg.cp_rd_rs1_hazard +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + ori rd, rs1, imm[11:0] + rd = rs1 | Sext(imm[11:0]) + Note: this is a bitwise, not logical operation +* **Verification Goals** + + Input operands: + + rs1 value is +ve, -ve and zero + immi value is +ve, -ve and zero + All combinations of rs1 and immi +ve, -ve, and zero values are used + All bits of rs1 are toggled + All bits of immi are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F000_S002_I001 +* **Link to Coverage:** isacov.rv32i_ori_cg.cp_rs1_value +isacov.rv32i_ori_cg.cp_immi_value +isacov.rv32i_ori_cg.cross_rs1_immi_value +isacov.rv32i_ori_cg.cp_rs1_toggle +isacov.rv32i_ori_cg.cp_immi_toggle +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + ori rd, rs1, imm[11:0] + rd = rs1 | Sext(imm[11:0]) + Note: this is a bitwise, not logical operation +* **Verification Goals** + + Output result: + + rd value is +ve, -ve and zero + All bits of rd are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F000_S002_I002 +* **Link to Coverage:** isacov.rv32i_ori_cg.cp_rd_value +isacov.rv32i_ori_cg.cp_rd_toggle +* **Comments** + + *(none)* + +### Sub-feature: 003_ANDI + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + andi rd, rs1, imm[11:0] + rd = rs1 & Sext(imm[11:0]) + Note: this is a bitwise, not logical operation +* **Verification Goals** + + Register operands: + + All possible rs1 registers are used. + All possible rd registers are used. + All possible register combinations where rs1 == rd are used +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F000_S003_I000 +* **Link to Coverage:** isacov.rv32i_andi_cg.cp_rs1 +isacov.rv32i_andi_cg.cp_rd +isacov.rv32i_andi_cg.cp_rd_rs1_hazard +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + andi rd, rs1, imm[11:0] + rd = rs1 & Sext(imm[11:0]) + Note: this is a bitwise, not logical operation +* **Verification Goals** + + Input operands: + + rs1 value is +ve, -ve and zero + immi value is +ve, -ve and zero + All combinations of rs1 and immi +ve, -ve, and zero values are used + All bits of rs1 are toggled + All bits of immi are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F000_S003_I001 +* **Link to Coverage:** isacov.rv32i_andi_cg.cp_rs1_value +isacov.rv32i_andi_cg.cp_immi_value +isacov.rv32i_andi_cg.cross_rs1_immi_value +isacov.rv32i_andi_cg.cp_rs1_toggle +isacov.rv32i_andi_cg.cp_immi_toggle +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + andi rd, rs1, imm[11:0] + rd = rs1 & Sext(imm[11:0]) + Note: this is a bitwise, not logical operation +* **Verification Goals** + + Output result: + + rd value is +ve, -ve and zero + All bits of rd are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F000_S003_I002 +* **Link to Coverage:** isacov.rv32i_andi_cg.cp_rd_value +isacov.rv32i_andi_cg.cp_rd_toggle +* **Comments** + + *(none)* + +### Sub-feature: 004_SLTI + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + slti rd, rs1, imm[11:0] + rd = (rs1 < Sext(imm[11:0]) ? 1 : 0 + Both imm and rs1 treated as signed numbers +* **Verification Goals** + + Register operands: + + All possible rs1 registers are used. + All possible rd registers are used. + All possible register combinations where rs1 == rd are used +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F000_S004_I000 +* **Link to Coverage:** isacov.rv32i_slti_cg.cp_rs1 +isacov.rv32i_slti_cg.cp_rd +isacov.rv32i_slti_cg.cp_rd_rs1_hazard +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + slti rd, rs1, imm[11:0] + rd = (rs1 < Sext(imm[11:0]) ? 1 : 0 + Both imm and rs1 treated as signed numbers +* **Verification Goals** + + Input operands: + + rs1 value is +ve, -ve and zero + immi value is +ve, -ve and zero + All combinations of rs1 and immi +ve, -ve, and zero values are used + All bits of rs1 are toggled + All bits of immi are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F000_S004_I001 +* **Link to Coverage:** isacov.rv32i_slti_cg.cp_rs1_value +isacov.rv32i_slti_cg.cp_immi_value +isacov.rv32i_slti_cg.cross_rs1_immi_value +isacov.rv32i_slti_cg.cp_rs1_toggle +isacov.rv32i_slti_cg.cp_immi_toggle +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + slti rd, rs1, imm[11:0] + rd = (rs1 < Sext(imm[11:0]) ? 1 : 0 + Both imm and rs1 treated as signed numbers +* **Verification Goals** + + Output result: + + rd value is in [0,1] +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F000_S004_I002 +* **Link to Coverage:** isacov.rv32i_slti_cg.cp_rd_value +* **Comments** + + *(none)* + +### Sub-feature: 005_SLTIU + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + sltiu rd, rs1, imm[11:0] + rd = (rs1 < Sext(imm[11:0]) ? 1 : 0 + Both imm and rs1 treated as unsigned numbers +* **Verification Goals** + + Register operands: + + All possible rs1 registers are used. + All possible rd registers are used. + All possible register combinations where rs1 == rd are used +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F000_S005_I000 +* **Link to Coverage:** isacov.rv32i_sltiu_cg.cp_rs1 +isacov.rv32i_sltiu_cg.cp_rd +isacov.rv32i_sltiu_cg.cp_rd_rs1_hazard +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + sltiu rd, rs1, imm[11:0] + rd = (rs1 < Sext(imm[11:0]) ? 1 : 0 + Both imm and rs1 treated as unsigned numbers +* **Verification Goals** + + Input operands: + + rs1 value is +ve, -ve and zero + immi value is +ve, -ve and zero + All combinations of rs1 and immi +ve, -ve, and zero values are used + All bits of rs1 are toggled + All bits of immi are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F000_S005_I001 +* **Link to Coverage:** isacov.rv32i_sltiu_cg.cp_rs1_value +isacov.rv32i_sltiu_cg.cp_immi_value +isacov.rv32i_sltiu_cg.cross_rs1_immi_value +isacov.rv32i_sltiu_cg.cp_rs1_toggle +isacov.rv32i_sltiu_cg.cp_immi_toggle +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + sltiu rd, rs1, imm[11:0] + rd = (rs1 < Sext(imm[11:0]) ? 1 : 0 + Both imm and rs1 treated as unsigned numbers +* **Verification Goals** + + Output result: + + rd value is in [0,1] +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F000_S005_I002 +* **Link to Coverage:** isacov.rv32i_sltiu_cg.cp_rd_value +* **Comments** + + *(none)* + +### Sub-feature: 006_SLLI + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + slli rd, rs, imm[4:0] + rd = rs << imm[4:0] + Zeros are shirfted into lower bits +* **Verification Goals** + + Register operands: + + All possible rs1 registers are used. + All possible rd registers are used. + All possible register combinations where rs1 == rd are used +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F000_S006_I000 +* **Link to Coverage:** isacov.rv32i_slli_cg.cp_rs1 +isacov.rv32i_slli_cg.cp_rd +isacov.rv32i_slli_cg.cp_rd_rs1_hazard +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + slli rd, rs, imm[4:0] + rd = rs << imm[4:0] + Zeros are shirfted into lower bits +* **Verification Goals** + + Input operands: + + rs1 value is +ve, -ve and zero + immediate shamt value is [0,31] + All combinations of rs1 and immi +ve, -ve, and zero values are used + All bits of rs1 are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F000_S006_I001 +* **Link to Coverage:** isacov.rv32i_slli_cg.cp_rs1_value +isacov.rv32i_slli_cg.cp_immi_value +isacov.rv32i_slli_cg.cross_rs1_immi_value +isacov.rv32i_slli_cg.cp_rs1_toggle +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + slli rd, rs, imm[4:0] + rd = rs << imm[4:0] + Zeros are shirfted into lower bits +* **Verification Goals** + + Output result: + + rd value is +ve, -ve and zero + All bits of rd are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F000_S006_I002 +* **Link to Coverage:** isacov.rv32i_slli_cg.cp_rd_value +isacov.rv32i_slli_cg.cp_rd_toggle +* **Comments** + + *(none)* + +### Sub-feature: 007_SRLI + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + srli rd, rs, imm[4:0] + rd = rs >> imm[4:0] + Zeros are shirfted into upper bits +* **Verification Goals** + + Register operands: + + All possible rs1 registers are used. + All possible rd registers are used. + All possible register combinations where rs1 == rd are used +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F000_S007_I000 +* **Link to Coverage:** isacov.rv32i_srli_cg.cp_rs1 +isacov.rv32i_srli_cg.cp_rd +isacov.rv32i_srli_cg.cp_rd_rs1_hazard +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + srli rd, rs, imm[4:0] + rd = rs >> imm[4:0] + Zeros are shirfted into upper bits +* **Verification Goals** + + Input operands: + + rs1 value is +ve, -ve and zero + immediate shamt value is [0,31] + All combinations of rs1 and immi +ve, -ve, and zero values are used + All bits of rs1 are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F000_S007_I001 +* **Link to Coverage:** isacov.rv32i_srli_cg.cp_rs1_value +isacov.rv32i_srli_cg.cp_immi_value +isacov.rv32i_srli_cg.cross_rs1_immi_value +isacov.rv32i_srli_cg.cp_rs1_toggle +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + srli rd, rs, imm[4:0] + rd = rs >> imm[4:0] + Zeros are shirfted into upper bits +* **Verification Goals** + + Output result: + + rd value is +ve, -ve and zero + All bits of rd are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F000_S007_I002 +* **Link to Coverage:** isacov.rv32i_srli_cg.cp_rd_value +isacov.rv32i_srli_cg.cp_rd_toggle +* **Comments** + + *(none)* + +### Sub-feature: 008_SRAI + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + srli rd, rs, imm[4:0] + rd = rs >> imm[4:0] + The original sign bit is copied into the vacated upper bits +* **Verification Goals** + + Register operands: + + All possible rs1 registers are used. + All possible rd registers are used. + All possible register combinations where rs1 == rd are used +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F000_S008_I000 +* **Link to Coverage:** isacov.rv32i_srai_cg.cp_rs1 +isacov.rv32i_srai_cg.cp_rd +isacov.rv32i_srai_cg.cp_rd_rs1_hazard +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + srli rd, rs, imm[4:0] + rd = rs >> imm[4:0] + The original sign bit is copied into the vacated upper bits +* **Verification Goals** + + Input operands: + + rs1 value is +ve, -ve and zero + immediate shamt value is [0,31] + All combinations of rs1 and immi +ve, -ve, and zero values are used + All bits of rs1 are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F000_S008_I001 +* **Link to Coverage:** isacov.rv32i_srai_cg.cp_rs1_value +isacov.rv32i_srai_cg.cp_immi_value +isacov.rv32i_srai_cg.cross_rs1_immi_value +isacov.rv32i_srai_cg.cp_rs1_toggle +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + srli rd, rs, imm[4:0] + rd = rs >> imm[4:0] + Zeros are shirfted into upper bits +* **Verification Goals** + + Output result: + + rd value is +ve, -ve and zero + All bits of rd are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F000_S008_I002 +* **Link to Coverage:** isacov.rv32i_srai_cg.cp_rd_value +isacov.rv32i_srai_cg.cp_rd_toggle +* **Comments** + + *(none)* + +### Sub-feature: 009_LUI + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + lui rd, imm[19:0] + rd = imm[19:0] << 12 + rd[11:0] is zero-filled. +* **Verification Goals** + + Register operands: + + All possible rd registers are used. +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F000_S009_I000 +* **Link to Coverage:** isacov.rv32i_lui_cg.cp_rd +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + lui rd, imm[19:0] + rd = imm[19:0] << 12 + rd[11:0] is zero-filled. +* **Verification Goals** + + Input operands: + + rs1 value is +ve, -ve and zero + immediate value is zero and non-zero + All bits of immu are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F000_S009_I001 +* **Link to Coverage:** isacov.rv32i_lui_cg.cp_immu_value +isacov.rv32i_lui_cg.cp_immu_toggle +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + lui rd, imm[19:0] + rd = imm[19:0] << 12 + rd[11:0] is zero-filled. +* **Verification Goals** + + Output result: + + rd value is zero and non-zero + All bits of rd[31:12] are toggled (11:0 are deposited with 0) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F000_S009_I002 +* **Link to Coverage:** isacov.rv32i_lui_cg.cp_rd_value +isacov.rv32i_lui_cg.cp_rd_toggle +* **Comments** + + *(none)* + +### Sub-feature: 010_AUIPC + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + auipc rd, imm[19:0] + rd = pc + (imm[19:0] << 12) + pc is address of auipc instruction + + Assumption: arithmetic overflow is lost and ignored. +* **Verification Goals** + + Register operands: + + All possible rd registers are used. +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F000_S010_I000 +* **Link to Coverage:** isacov.rv32i_auipc_cg.cp_rd +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + auipc rd, imm[19:0] + rd = pc + (imm[19:0] << 12) + pc is address of auipc instruction + + Assumption: arithmetic overflow is lost and ignored. +* **Verification Goals** + + Input operands: + + rs1 value is +ve, -ve and zero + immediate value is zero and non-zero + All bits of immu are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F000_S010_I001 +* **Link to Coverage:** isacov.rv32i_auipc_cg.cp_immu_value +isacov.rv32i_auipc_cg.cp_immu_toggle +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + auipc rd, imm[19:0] + rd = pc + (imm[19:0] << 12) + pc is address of auipc instruction + + Assumption: arithmetic overflow is lost and ignored. +* **Verification Goals** + + Output result: + + rd value is zero and non-zero + All bits of rd[31:12] are toggled (11:0 are deposited with 0) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F000_S010_I002 +* **Link to Coverage:** isacov.rv32i_auipc_cg.cp_rd_value +isacov.rv32i_auipc_cg.cp_rd_toggle +* **Comments** + + *(none)* + +## Feature: RV32I Register-Register Instructions + +### Sub-feature: 000_ADD + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + add rd, rs1, rs2 + rd = rs1 + rs2 + Arithmetic overflow is lost and ignored +* **Verification Goals** + + Register operands: + + All possible rs1 registers are used. + All possible rs2 registers are used. + All possible rd registers are used. + All possible register combinations where rs1 == rd are used + All possible register combinations where rs2 == rd are used +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F001_S000_I000 +* **Link to Coverage:** isacov.rv32i_add_cg.cp_rs1 +isacov.rv32i_add_cg.cp_rs2 +isacov.rv32i_add_cg.cp_rd +isacov.rv32i_add_cg.cp_rd_rs1_hazard +isacov.rv32i_add_cg.cp_rd_rs2_hazard +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + add rd, rs1, rs2 + rd = rs1 + rs2 + Arithmetic overflow is lost and ignored +* **Verification Goals** + + Input operands: + + rs1 value is +ve, -ve and zero + rs2 value is +ve, -ve and zero + All combinations of rs1 and rs2 +ve, -ve, and zero values are used + All bits of rs1 are toggled + All bits of rs2 are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F001_S000_I001 +* **Link to Coverage:** isacov.rv32i_add_cg.cp_rs1_value +isacov.rv32i_add_cg.cp_rs2_value +isacov.rv32i_add_cg.cross_rs1_rs2_value +isacov.rv32i_add_cg.cp_rs1_toggle +isacov.rv32i_add_cg.cp_rs2_toggle +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + add rd, rs1, rs2 + rd = rs1 + rs2 + Arithmetic overflow is lost and ignored +* **Verification Goals** + + Output result: + + rd value is +ve, -ve and zero + All bits of rd are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F001_S000_I002 +* **Link to Coverage:** isacov.rv32i_add_cg.cp_rd_value +isacov.rv32i_add_cg.cp_rd_toggle +* **Comments** + + *(none)* + +### Sub-feature: 001_SUB + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + sub rd, rs1, rs2 + rd = rs1 - rs2 + Arithmetic underflow is ignored +* **Verification Goals** + + Register operands: + + All possible rs1 registers are used. + All possible rs2 registers are used. + All possible rd registers are used. + All possible register combinations where rs1 == rd are used + All possible register combinations where rs2 == rd are used +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F001_S001_I000 +* **Link to Coverage:** isacov.rv32i_sub_cg.cp_rs1 +isacov.rv32i_sub_cg.cp_rs2 +isacov.rv32i_sub_cg.cp_rd +isacov.rv32i_sub_cg.cp_rd_rs1_hazard +isacov.rv32i_sub_cg.cp_rd_rs2_hazard +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + sub rd, rs1, rs2 + rd = rs1 - rs2 + Arithmetic underflow is ignored +* **Verification Goals** + + Input operands: + + rs1 value is +ve, -ve and zero + rs2 value is +ve, -ve and zero + All combinations of rs1 and rs2 +ve, -ve, and zero values are used + All bits of rs1 are toggled + All bits of rs2 are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F001_S001_I001 +* **Link to Coverage:** isacov.rv32i_sub_cg.cp_rs1_value +isacov.rv32i_sub_cg.cp_rs2_value +isacov.rv32i_sub_cg.cross_rs1_rs2_value +isacov.rv32i_sub_cg.cp_rs1_toggle +isacov.rv32i_sub_cg.cp_rs2_toggle +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + sub rd, rs1, rs2 + rd = rs1 - rs2 + Arithmetic underflow is ignored +* **Verification Goals** + + Output result: + + rd value is +ve, -ve and zero + All bits of rd are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F001_S001_I002 +* **Link to Coverage:** isacov.rv32i_sub_cg.cp_rd_value +isacov.rv32i_sub_cg.cp_rd_toggle +* **Comments** + + *(none)* + +### Sub-feature: 002_AND + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + and rd, rs1, rs2 + rd = rs1 & rs2 + Note: this is a bitwise, not logical operation +* **Verification Goals** + + Register operands: + + All possible rs1 registers are used. + All possible rs2 registers are used. + All possible rd registers are used. + All possible register combinations where rs1 == rd are used + All possible register combinations where rs2 == rd are used +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F001_S002_I000 +* **Link to Coverage:** isacov.rv32i_and_cg.cp_rs1 +isacov.rv32i_and_cg.cp_rs2 +isacov.rv32i_and_cg.cp_rd +isacov.rv32i_and_cg.cp_rd_rs1_hazard +isacov.rv32i_and_cg.cp_rd_rs2_hazard +isacov.rv32i_and_cg.cp_rs1 +isacov.rv32i_and_cg.cp_rs2 +isacov.rv32i_and_cg.cp_rd +isacov.rv32i_and_cg.cp_rd_rs1_hazard +isacov.rv32i_and_cg.cp_rd_rs2_hazard +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + and rd, rs1, rs2 + rd = rs1 & rs2 + Note: this is a bitwise, not logical operation +* **Verification Goals** + + Input operands: + + rs1 value is +ve, -ve and zero + rs2 value is +ve, -ve and zero + All combinations of rs1 and rs2 +ve, -ve, and zero values are used + All bits of rs1 are toggled + All bits of rs2 are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F001_S002_I001 +* **Link to Coverage:** isacov.rv32i_and_cg.cp_rs1_value +isacov.rv32i_and_cg.cp_rs2_value +isacov.rv32i_and_cg.cross_rs1_rs2_value +isacov.rv32i_and_cg.cp_rs1_toggle +isacov.rv32i_and_cg.cp_rs2_toggle +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + and rd, rs1, rs2 + rd = rs1 & rs2 + Note: this is a bitwise, not logical operation +* **Verification Goals** + + Output result: + + rd value is +ve, -ve and zero + All bits of rd are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F001_S002_I002 +* **Link to Coverage:** isacov.rv32i_and_cg.cp_rd_value +isacov.rv32i_and_cg.cp_rd_toggle +* **Comments** + + *(none)* + +### Sub-feature: 003_OR + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + or rd, rs1, rs2 + rd = rs1 | rs2 + Note: this is a bitwise, not logical operation +* **Verification Goals** + + Register operands: + + All possible rs1 registers are used. + All possible rs2 registers are used. + All possible rd registers are used. + All possible register combinations where rs1 == rd are used + All possible register combinations where rs2 == rd are used +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F001_S003_I000 +* **Link to Coverage:** isacov.rv32i_or_cg.cp_rs1 +isacov.rv32i_or_cg.cp_rs2 +isacov.rv32i_or_cg.cp_rd +isacov.rv32i_or_cg.cp_rd_rs1_hazard +isacov.rv32i_or_cg.cp_rd_rs2_hazard +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + or rd, rs1, rs2 + rd = rs1 | rs2 + Note: this is a bitwise, not logical operation +* **Verification Goals** + + Input operands: + + rs1 value is +ve, -ve and zero + rs2 value is +ve, -ve and zero + All combinations of rs1 and rs2 +ve, -ve, and zero values are used + All bits of rs1 are toggled + All bits of rs2 are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F001_S003_I001 +* **Link to Coverage:** isacov.rv32i_or_cg.cp_rs1_value +isacov.rv32i_or_cg.cp_rs2_value +isacov.rv32i_or_cg.cross_rs1_rs2_value +isacov.rv32i_or_cg.cp_rs1_toggle +isacov.rv32i_or_cg.cp_rs2_toggle +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + or rd, rs1, rs2 + rd = rs1 | rs2 + Note: this is a bitwise, not logical operation +* **Verification Goals** + + Output result: + + rd value is +ve, -ve and zero + All bits of rd are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F001_S003_I002 +* **Link to Coverage:** isacov.rv32i_or_cg.cp_rd_value +isacov.rv32i_or_cg.cp_rd_toggle +* **Comments** + + *(none)* + +### Sub-feature: 004_XOR + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + xor rd, rs1, rs2 + rd = rs1 ^ rs2 + Note: this is a bitwise, not logical operation +* **Verification Goals** + + Register operands: + + All possible rs1 registers are used. + All possible rs2 registers are used. + All possible rd registers are used. + All possible register combinations where rs1 == rd are used + All possible register combinations where rs2 == rd are used +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F001_S004_I000 +* **Link to Coverage:** isacov.rv32i_xor_cg.cp_rs1 +isacov.rv32i_xor_cg.cp_rs2 +isacov.rv32i_xor_cg.cp_rd +isacov.rv32i_xor_cg.rd_rs1_hazard +isacov.rv32i_xor_cg.rd_rs2_hazard +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + xor rd, rs1, rs2 + rd = rs1 ^ rs2 + Note: this is a bitwise, not logical operation +* **Verification Goals** + + Input operands: + + rs1 value is +ve, -ve and zero + rs2 value is +ve, -ve and zero + All combinations of rs1 and rs2 +ve, -ve, and zero values are used + All bits of rs1 are toggled + All bits of rs2 are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F001_S004_I001 +* **Link to Coverage:** isacov.rv32i_xor_cg.cp_rs1_value +isacov.rv32i_xor_cg.cp_rs2_value +isacov.rv32i_xor_cg.cross_rs1_rs2_value +isacov.rv32i_xor_cg.cp_rs1_toggle +isacov.rv32i_xor_cg.cp_rs2_toggle +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + xor rd, rs1, rs2 + rd = rs1 ^ rs2 + Note: this is a bitwise, not logical operation +* **Verification Goals** + + Output result: + + rd value is +ve, -ve and zero + All bits of rd are toggled +* **Pass/Fail Criteria:** NDY (Not Defined Yet) +* **Test Type:** NDY (Not Defined Yet) +* **Coverage Method:** NDY (Not Defined Yet) +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F001_S004_I002 +* **Link to Coverage:** isacov.rv32i_xor_cg.cp_rd_value +isacov.rv32i_xor_cg.cp_rd_toggle +* **Comments** + + *(none)* + +### Sub-feature: 005_SLT + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + slt rd, rs1, rs2 + rd = (rs1 < rs2) ? 1 : 0 + Both rs1 ad rs2 treated as signed numbers +* **Verification Goals** + + Register operands: + + All possible rs1 registers are used. + All possible rs2 registers are used. + All possible rd registers are used. + All possible register combinations where rs1 == rd are used + All possible register combinations where rs2 == rd are used +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F001_S005_I000 +* **Link to Coverage:** isacov.rv32i_slt_cg.cp_rs1 +isacov.rv32i_slt_cg.cp_rs2 +isacov.rv32i_slt_cg.cp_rd +isacov.rv32i_slt_cg.cp_rd_rs1_hazard +isacov.rv32i_slt_cg.cp_rd_rs2_hazard +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + slt rd, rs1, rs2 + rd = (rs1 < rs2) ? 1 : 0 + Both rs1 ad rs2 treated as signed numbers +* **Verification Goals** + + Input operands: + + rs1 value is +ve, -ve and zero + rs2 value is +ve, -ve and zero + All combinations of rs1 and rs2 +ve, -ve, and zero values are used + All bits of rs1 are toggled + All bits of rs2 are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F001_S005_I001 +* **Link to Coverage:** isacov.rv32i_slt_cg.cp_rs1_value +isacov.rv32i_slt_cg.cp_rs2_value +isacov.rv32i_slt_cg.cross_rs1_rs2_value +isacov.rv32i_slt_cg.cp_rs1_toggle +isacov.rv32i_slt_cg.cp_rs2_toggle +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + slt rd, rs1, rs2 + rd = (rs1 < rs2) ? 1 : 0 + Both rs1 ad rs2 treated as signed numbers +* **Verification Goals** + + Output result: + + rd value is [0,1] +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F001_S005_I002 +* **Link to Coverage:** isacov.rv32i_slt_cg.cp_rd_value +* **Comments** + + *(none)* + +### Sub-feature: 006_SLTU + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + sltu rd, rs1, imm[11:0] + rd = (rs1 < rs2) ? 1 : 0 + Both rs1 and rs2 treated as unsigned numbers +* **Verification Goals** + + Register operands: + + All possible rs1 registers are used. + All possible rs2 registers are used. + All possible rd registers are used. + All possible register combinations where rs1 == rd are used + All possible register combinations where rs2 == rd are used +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F001_S006_I000 +* **Link to Coverage:** isacov.rv32i_sltu_cg.cp_rs1 +isacov.rv32i_sltu_cg.cp_rs2 +isacov.rv32i_sltu_cg.cp_rd +isacov.rv32i_sltu_cg.cp_rd_rs1_hazard +isacov.rv32i_sltu_cg.cp_rd_rs2_hazard +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + sltu rd, rs1, imm[11:0] + rd = (rs1 < rs2) ? 1 : 0 + Both rs1 and rs2 treated as unsigned numbers +* **Verification Goals** + + Input operands: + + rs1 value is non-zero and zero + rs2 value is non-zero and zero + All combinations of rs1 and rs2 non-zero and zero values are used + All bits of rs1 are toggled + All bits of rs2 are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F001_S006_I001 +* **Link to Coverage:** isacov.rv32i_sltu_cg.cp_rs1_value +isacov.rv32i_sltu_cg.cp_rs2_value +isacov.rv32i_sltu_cg.cross_rs1_rs2_value +isacov.rv32i_sltu_cg.cp_rs1_toggle +isacov.rv32i_sltu_cg.cp_rs2_toggle +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + sltu rd, rs1, imm[11:0] + rd = (rs1 < rs2) ? 1 : 0 + Both rs1 and rs2 treated as unsigned numbers +* **Verification Goals** + + Output result: + + rd value is [0,1] +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F001_S006_I002 +* **Link to Coverage:** isacov.rv32i_sltu_cg.cp_rd_value +* **Comments** + + *(none)* + +### Sub-feature: 007_SLL + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + sll rd, rs1, rs2 + rd = rs1 << rs2[4:0] + Zeros are shirfted into lower bits +* **Verification Goals** + + Register operands: + + All possible rs1 registers are used. + All possible rs2 registers are used. + All possible rd registers are used. + All possible register combinations where rs1 == rd are used + All possible register combinations where rs2 == rd are used +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F001_S007_I000 +* **Link to Coverage:** isacov.rv32i_sll_cg.cp_rs1 +isacov.rv32i_sll_cg.cp_rs2 +isacov.rv32i_sll_cg.cp_rd +isacov.rv32i_sll_cg.cp_rd_rs1_hazard +isacov.rv32i_sll_cg.cp_rd_rs2_hazard +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + sll rd, rs1, rs2 + rd = rs1 << rs2[4:0] + Zeros are shirfted into lower bits +* **Verification Goals** + + Input operands: + + rs1 value is non-zero and zero + rs2 value is tested from [0,31] + All combinations of rs1 and rs2 non-zero and zero values with all shift values are used + All bits of rs1 are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F001_S007_I001 +* **Link to Coverage:** isacov.rv32i_sll_cg.cp_rs1_value +isacov.rv32i_sll_cg.cp_rs2_value +isacov.rv32i_sll_cg.cross_rs1_rs2_value +isacov.rv32i_sll_cg.cp_rs1_toggle +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + sll rd, rs1, rs2 + rd = rs1 << rs2[4:0] + Zeros are shirfted into lower bits +* **Verification Goals** + + Output result: + + rd value is non-zero and zero. + All bits of rd are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F001_S007_I002 +* **Link to Coverage:** isacov.rv32i_sll_cg.cp_rd_value +isacov.rv32i_sll_cg.cp_rd_toggle +isacov.rv32i_sll_cg.cp_rd_value +isacov.rv32i_sll_cg.cp_rd_toggle +* **Comments** + + *(none)* + +### Sub-feature: 008_SRL + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + srl rd, rs1, rs2 + rd = rs1 >> rs2[4:0] + Zeros are shirfted into upper bits +* **Verification Goals** + + Register operands: + + All possible rs1 registers are used. + All possible rs2 registers are used. + All possible rd registers are used. + All possible register combinations where rs1 == rd are used + All possible register combinations where rs2 == rd are used +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F001_S008_I000 +* **Link to Coverage:** isacov.rv32i_srl_cg.cp_rs1 +isacov.rv32i_srl_cg.cp_rs2 +isacov.rv32i_srl_cg.cp_rd +isacov.rv32i_srl_cg.cp_rd_rs1_hazard +isacov.rv32i_srl_cg.cp_rd_rs2_hazard +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + srl rd, rs1, rs2 + rd = rs1 >> rs2[4:0] + Zeros are shirfted into upper bits +* **Verification Goals** + + Input operands: + + rs1 value is non-zero and zero + rs2 value is tested from [0,31] + All combinations of rs1 and rs2 non-zero and zero values with all shift values are used + All bits of rs1 are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F001_S008_I001 +* **Link to Coverage:** isacov.rv32i_srl_cg.cp_rs1_value +isacov.rv32i_srl_cg.cp_rs2_value +isacov.rv32i_srl_cg.cross_rs1_rs2_value +isacov.rv32i_srl_cg.cp_rs1_toggle +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + srl rd, rs1, rs2 + rd = rs1 >> rs2[4:0] + Zeros are shirfted into upper bits +* **Verification Goals** + + Output result: + + rd value is non-zero and zero. + All bits of rd are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F001_S008_I002 +* **Link to Coverage:** isacov.rv32i_srl_cg.cp_rd_value +isacov.rv32i_srl_cg.cp_rd_toggle +* **Comments** + + *(none)* + +### Sub-feature: 009_SRA + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + sra rd, rs1, rs2 + rd = rs1 >> rs2[4:0] + The original sign bit is copied into the vacated upper bits +* **Verification Goals** + + Register operands: + + All possible rs1 registers are used. + All possible rs2 registers are used. + All possible rd registers are used. + All possible register combinations where rs1 == rd are used + All possible register combinations where rs2 == rd are used +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F001_S009_I000 +* **Link to Coverage:** isacov.rv32i_sra_cg.cp_rs1 +isacov.rv32i_sra_cg.cp_rs2 +isacov.rv32i_sra_cg.cp_rd +isacov.rv32i_sra_cg.cp_rd_rs1_hazard +isacov.rv32i_sra_cg.cp_rd_rs2_hazard +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + sra rd, rs1, rs2 + rd = rs1 >> rs2[4:0] + The original sign bit is copied into the vacated upper bits +* **Verification Goals** + + Input operands: + + rs1 value is +ve, -ve, and zero + rs2 value is tested from [0,31] + All combinations of rs1 and rs2 +ve, -ve and zero values with all shift values are used + All bits of rs1 are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F001_S009_I001 +* **Link to Coverage:** isacov.rv32i_sra_cg.cp_rs1_value +isacov.rv32i_sra_cg.cp_rs2_value +isacov.rv32i_sra_cg.cross_rs1_rs2_value +isacov.rv32i_sra_cg.cp_rs1_toggle +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + sra rd, rs1, rs2 + rd = rs1 >> rs2[4:0] + Zeros are shirfted into upper bits +* **Verification Goals** + + Output result: + + rd value is +ve, -ve, and zero. + All bits of rd are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F001_S009_I002 +* **Link to Coverage:** isacov.rv32i_sra_cg.cp_rd_value +isacov.rv32i_sra_cg.cp_rd_toggle +* **Comments** + + *(none)* + +## Feature: RV32I Control Transfer Instructions + +### Sub-feature: 000_JAL + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + jal rd, imm[20:1] + rd = pc+4; pc += Sext({imm[20:1], 1’b0}) + pc is calculated using signed arithmetic + + jal x0, imm[20:1] (special case: unconditional jump) + pc += Sext({imm[20:1], 1’b0}) +* **Verification Goals** + + Register operands: + + All possible rd registers are used. +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F002_S000_I000 +* **Link to Coverage:** isacov.rv32i_jal_cg.cp_rd +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + jal rd, imm[20:1] + rd = pc+4; pc += Sext({imm[20:1], 1’b0}) + pc is calculated using signed arithmetic + + jal x0, imm[20:1] (special case: unconditional jump) + pc += Sext({imm[20:1], 1’b0}) +* **Verification Goals** + + Input operands: + + immj value is +ve, -ve, and zero + All bits of immj are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F002_S000_I001 +* **Link to Coverage:** isacov.rv32i_jal_cg.cp_immj_value +isacov.rv32i_jal_cg.cp_immj_toggle +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + jal rd, imm[20:1] + rd = pc+4; pc += Sext({imm[20:1], 1’b0}) + pc is calculated using signed arithmetic + + jal x0, imm[20:1] (special case: unconditional jump) + pc += Sext({imm[20:1], 1’b0}) +* **Verification Goals** + + Output result: + + All bits of rd are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F002_S000_I002 +* **Link to Coverage:** isacov.rv32i_jal_cg.cp_rd_toggle +* **Comments** + + *(none)* + +### Sub-feature: 001_JALR + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + jalr rd, rs1, imm[11:0] + rd = pc+4; pc = rs1 + Sext(imm[11:0]) + pc is calculated using signed arithmetic +* **Verification Goals** + + Register operands: + + All possible rs1 registers are used. + All possible rd registers are used. + All possible register combinations where rs1 == rd are used +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F002_S001_I000 +* **Link to Coverage:** isacov.rv32i_jalr_cg.cp_rs1 +isacov.rv32i_jalr_cg.cp_rd +isacov.rv32i_jalr_cg.cp_rd_rs1_hazard +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + jalr rd, rs1, imm[11:0] + rd = pc+4; pc = rs1 + Sext(imm[11:0]) + pc is calculated using signed arithmetic +* **Verification Goals** + + Input operands: + + immi value is +ve, -ve, and zero + All bits of immi are toggled + All bits of rs1 are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F002_S001_I001 +* **Link to Coverage:** isacov.rv32i_jalr_cg.cp_immi_value +isacov.rv32i_jalr_cg.cp_immi_toggle +isacov.rv32i_jalr_cg.cp_rs1_toggle +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + jalr rd, rs1, imm[11:0] + rd = pc+4; pc = rs1 + Sext(imm[11:0]) + pc is calculated using signed arithmetic +* **Verification Goals** + + Output result: + + All bits of rd are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F002_S001_I002 +* **Link to Coverage:** isacov.rv32i_jalr_cg.cp_rd_toggle +* **Comments** + + *(none)* + +### Sub-feature: 002_BEQ + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + beq rs1, rs2, imm[12:1] + pc += Sext({imm[12:1], 1’b0}) if (rs1==rs2) else pc += 4 + pc is calculated using signed arithmetic +* **Verification Goals** + + Register operands: + + All possible rs1 registers are used. + All possible rs2 registers are used. +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F002_S002_I000 +* **Link to Coverage:** isacov.rv32i_beq_cg.cp_rs1 +isacov.rv32i_beq_cg.cp_rs2 +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + beq rs1, rs2, imm[12:1] + pc += Sext({imm[12:1], 1’b0}) if (rs1==rs2) else pc += 4 + pc is calculated using signed arithmetic +* **Verification Goals** + + Input operands: + + immb value is +ve, -ve, and zero + All bits of immb are toggled + All bits of rs1 are toggled + All bits of rs2 are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F002_S002_I001 +* **Link to Coverage:** isacov.rv32i_beq_cg.cp_immb_value +isacov.rv32i_beq_cg.cp_rs1_toggle +isacov.rv32i_beq_cg.cp_rs2_toggle +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + beq rs1, rs2, imm[12:1] + pc += Sext({imm[12:1], 1’b0}) if (rs1==rs2) else pc += 4 + pc is calculated using signed arithmetic +* **Verification Goals** + + Output result: + + Branch taken or not-taken +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F002_S002_I002 +* **Link to Coverage:** isacov.rv32i_beq_cg.cp_branch_taken +* **Comments** + + *(none)* + +### Sub-feature: 003_BNE + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + bne rs1, rs2, imm[12:1] + pc += Sext({imm[12:1], 1’b0}) if (rs1!=rs2) else pc += 4 + pc is calculated using signed arithmetic +* **Verification Goals** + + Register operands: + + All possible rs1 registers are used. + All possible rs2 registers are used. +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F002_S003_I000 +* **Link to Coverage:** isacov.rv32i_bne_cg.cp_rs1 +isacov.rv32i_bne_cg.cp_rs2 +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + bne rs1, rs2, imm[12:1] + pc += Sext({imm[12:1], 1’b0}) if (rs1!=rs2) else pc += 4 + pc is calculated using signed arithmetic +* **Verification Goals** + + Input operands: + + immb value is +ve, -ve, and zero + All bits of immb are toggled + All bits of rs1 are toggled + All bits of rs2 are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F002_S003_I001 +* **Link to Coverage:** isacov.rv32i_bne_cg.cp_immb_value +isacov.rv32i_bne_cg.cp_rs1_toggle +isacov.rv32i_bne_cg.cp_rs2_toggle +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + bne rs1, rs2, imm[12:1] + pc += Sext({imm[12:1], 1’b0}) if (rs1!=rs2) else pc += 4 + pc is calculated using signed arithmetic +* **Verification Goals** + + Output result: + + Branch taken or not-taken +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F002_S003_I002 +* **Link to Coverage:** isacov.rv32i_bne_cg.cp_branch_taken +* **Comments** + + *(none)* + +### Sub-feature: 004_BLT + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + blt rs1, rs2, imm[12:1] + pc += Sext({imm[12:1], 1’b0}) if (rs1 < rs2) else pc += 4 + pc is calculated using signed arithmetic +* **Verification Goals** + + Register operands: + + All possible rs1 registers are used. + All possible rs2 registers are used. +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F002_S004_I000 +* **Link to Coverage:** isacov.rv32i_blt_cg.cp_rs1 +isacov.rv32i_blt_cg.cp_rs2 +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + blt rs1, rs2, imm[12:1] + pc += Sext({imm[12:1], 1’b0}) if (rs1 < rs2) else pc += 4 + pc is calculated using signed arithmetic +* **Verification Goals** + + Input operands: + + immb value is +ve, -ve, and zero + All bits of immb are toggled + All bits of rs1 are toggled + All bits of rs2 are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F002_S004_I001 +* **Link to Coverage:** isacov.rv32i_blt_cg.cp_immb_value +isacov.rv32i_blt_cg.cp_rs1_toggle +isacov.rv32i_blt_cg.cp_rs2_toggle +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + blt rs1, rs2, imm[12:1] + pc += Sext({imm[12:1], 1’b0}) if (rs1 < rs2) else pc += 4 + pc is calculated using signed arithmetic +* **Verification Goals** + + Output result: + + Branch taken or not-taken +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F002_S004_I002 +* **Link to Coverage:** isacov.rv32i_blt_cg.cp_branch_taken +* **Comments** + + *(none)* + +### Sub-feature: 005_BGE + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + bge rs1, rs2, imm[12:1] + pc += Sext({imm[12:1], 1’b0}) if (rs1 >= rs2) else pc += 4 + pc is calculated using signed arithmetic +* **Verification Goals** + + Register operands: + + All possible rs1 registers are used. + All possible rs2 registers are used. +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F002_S005_I000 +* **Link to Coverage:** isacov.rv32i_bge_cg.cp_rs1 +isacov.rv32i_bge_cg.cp_rs2 +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + bge rs1, rs2, imm[12:1] + pc += Sext({imm[12:1], 1’b0}) if (rs1 >= rs2) else pc += 4 + pc is calculated using signed arithmetic +* **Verification Goals** + + Input operands: + + immb value is +ve, -ve, and zero + All bits of immb are toggled + All bits of rs1 are toggled + All bits of rs2 are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F002_S005_I001 +* **Link to Coverage:** isacov.rv32i_bge_cg.cp_immb_value +isacov.rv32i_bge_cg.cp_rs1_toggle +isacov.rv32i_bge_cg.cp_rs2_toggle +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + bge rs1, rs2, imm[12:1] + pc += Sext({imm[12:1], 1’b0}) if (rs1 >= rs2) else pc += 4 + pc is calculated using signed arithmetic +* **Verification Goals** + + Output result: + + Branch taken or not-taken +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F002_S005_I002 +* **Link to Coverage:** isacov.rv32i_bge_cg.cp_branch_taken +* **Comments** + + *(none)* + +### Sub-feature: 006_BLTU + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + bltu rs1, rs2, imm[12:1] + pc += Sext({imm[12:1], 1’b0}) if (rs1 < rs2) else pc += 4 + pc is calculated using unsigned arithmetic +* **Verification Goals** + + Register operands: + + All possible rs1 registers are used. + All possible rs2 registers are used. +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F002_S006_I000 +* **Link to Coverage:** isacov.rv32i_bltu_cg.cp_rs1 +isacov.rv32i_bltu_cg.cp_rs2 +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + bltu rs1, rs2, imm[12:1] + pc += Sext({imm[12:1], 1’b0}) if (rs1 < rs2) else pc += 4 + pc is calculated using unsigned arithmetic +* **Verification Goals** + + Input operands: + + immb value is +ve, -ve, and zero + All bits of immb are toggled + All bits of rs1 are toggled + All bits of rs2 are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F002_S006_I001 +* **Link to Coverage:** isacov.rv32i_bltu_cg.cp_immb_value +isacov.rv32i_bltu_cg.cp_rs1_toggle +isacov.rv32i_bltu_cg.cp_rs2_toggle +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + bltu rs1, rs2, imm[12:1] + pc += Sext({imm[12:1], 1’b0}) if (rs1 < rs2) else pc += 4 + pc is calculated using unsigned arithmetic +* **Verification Goals** + + Output result: + + Branch taken or not-taken +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F002_S006_I002 +* **Link to Coverage:** isacov.rv32i_bltu_cg.cp_branch_taken +* **Comments** + + *(none)* + +### Sub-feature: 007_BGEU + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + bgeu rs1, rs2, imm[12:1] + pc += Sext({imm[12:1], 1’b0}) if (rs1 >= rs2) else pc += 4 + pc is calculated using unsigned arithmetic +* **Verification Goals** + + Register operands: + + All possible rs1 registers are used. + All possible rs2 registers are used. +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F002_S007_I000 +* **Link to Coverage:** isacov.rv32i_bgeu_cg.cp_rs1 +isacov.rv32i_bgeu_cg.cp_rs2 +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + bgeu rs1, rs2, imm[12:1] + pc += Sext({imm[12:1], 1’b0}) if (rs1 >= rs2) else pc += 4 + pc is calculated using unsigned arithmetic +* **Verification Goals** + + Input operands: + + immb value is +ve, -ve, and zero + All bits of immb are toggled + All bits of rs1 are toggled + All bits of rs2 are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F002_S007_I001 +* **Link to Coverage:** isacov.rv32i_bgeu_cg.cp_immb_value +isacov.rv32i_bgeu_cg.cp_rs1_toggle +isacov.rv32i_bgeu_cg.cp_rs2_toggle +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + bgeu rs1, rs2, imm[12:1] + pc += Sext({imm[12:1], 1’b0}) if (rs1 >= rs2) else pc += 4 + pc is calculated using unsigned arithmetic +* **Verification Goals** + + Output result: + + Branch taken or not-taken +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F002_S007_I002 +* **Link to Coverage:** isacov.rv32i_bgeu_cg.cp_branch_taken +* **Comments** + + *(none)* + +## Feature: RV32I Load and Store Instructions + +### Sub-feature: 000_LB + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + lb rd, rs1, imm + rd = Sext(M[rs1+imm][0:7]) + rd is calculated using signed arithmetic +* **Verification Goals** + + Register operands: + + All possible rs1 registers are used. + All possible rd registers are used. + All possible register combinations where rs1 == rd are used +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F003_S000_I000 +* **Link to Coverage:** isacov.rv32i_lb_cg.cp_rs1 +isacov.rv32i_lb_cg.cp_rd +isacov.rv32i_lb_cg.cp_rd_rs1_hazard +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + lb rd, rs1, imm + rd = Sext(M[rs1+imm][0:7]) + rd is calculated using signed arithmetic +* **Verification Goals** + + Input operands: + + immi value is +ve, -ve and zero + All combinations of rs1 and immi +ve, -ve, and zero values are used + All bits of rs1 are toggled + All bits of immi are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F003_S000_I001 +* **Link to Coverage:** isacov.rv32i_lb_cg.cp_immi_value +isacov.rv32i_lb_cg.cp_rs1_toggle +isacov.rv32i_lb_cg.cp_immi_toggle +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + lb rd, rs1, imm + rd = Sext(M[rs1+imm][0:7]) + rd is calculated using signed arithmetic +* **Verification Goals** + + Output result: + + rd value is +ve, -ve and zero + All bits of rd are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F003_S000_I002 +* **Link to Coverage:** isacov.rv32i_lb_cg.cp_rd_value +isacov.rv32i_lb_cg.cp_rd_toggle +* **Comments** + + *(none)* + +### Sub-feature: 001_LH + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + lh rd, rs1, imm + rd = Sext(M[rs1+imm][0:15]) + rd is calculated using signed arithmetic +* **Verification Goals** + + Register operands: + + All possible rs1 registers are used. + All possible rd registers are used. + All possible register combinations where rs1 == rd are used +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F003_S001_I000 +* **Link to Coverage:** isacov.rv32i_lh_cg.cp_rs1 +isacov.rv32i_lh_cg.cp_rd +isacov.rv32i_lh_cg.cp_rd_rs1_hazard +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + lh rd, rs1, imm + rd = Sext(M[rs1+imm][0:15]) + rd is calculated using signed arithmetic +* **Verification Goals** + + Input operands: + + immi value is +ve, -ve and zero + All combinations of rs1 and immi +ve, -ve, and zero values are used + All bits of rs1 are toggled + All bits of immi are toggled + Unaligned and aligned accesses from memory +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F003_S001_I001 +* **Link to Coverage:** isacov.rv32i_lh_cg.cp_immi_value +isacov.rv32i_lh_cg.cp_rs1_toggle +isacov.rv32i_lh_cg.cp_immi_toggle +isacov.rv32i_lh_cg.cp_aligned +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + lh rd, rs1, imm + rd = Sext(M[rs1+imm][0:15]) + rd is calculated using signed arithmetic +* **Verification Goals** + + Output result: + + rd value is +ve, -ve and zero + All bits of rd are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F003_S001_I002 +* **Link to Coverage:** isacov.rv32i_lh_cg.cp_rd_value +isacov.rv32i_lh_cg.cp_rd_toggle +* **Comments** + + *(none)* + +### Sub-feature: 002_LW + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + lw rd, rs1, imm + rd = Sext(M[rs1+imm][0:31]) + rd is calculated using signed arithmetic +* **Verification Goals** + + Register operands: + + All possible rs1 registers are used. + All possible rd registers are used. + All possible register combinations where rs1 == rd are used +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F003_S002_I000 +* **Link to Coverage:** isacov.rv32i_lw_cg.cp_rs1 +isacov.rv32i_lw_cg.cp_rd +isacov.rv32i_lw_cg.cp_rd_rs1_hazard +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + lw rd, rs1, imm + rd = Sext(M[rs1+imm][0:31]) + rd is calculated using signed arithmetic +* **Verification Goals** + + Input operands: + + immi value is +ve, -ve and zero + All combinations of rs1 and immi +ve, -ve, and zero values are used + All bits of rs1 are toggled + All bits of immi are toggled + Unaligned and aligned accesses from memory +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F003_S002_I001 +* **Link to Coverage:** isacov.rv32i_lw_cg.cp_immi_value +isacov.rv32i_lw_cg.cp_rs1_toggle +isacov.rv32i_lw_cg.cp_immi_toggle +isacov.rv32i_lw_cg.cp_aligned +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + lw rd, rs1, imm + rd = Sext(M[rs1+imm][0:31]) + rd is calculated using signed arithmetic +* **Verification Goals** + + Output result: + + rd value is +ve, -ve and zero + All bits of rd are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F003_S002_I002 +* **Link to Coverage:** isacov.rv32i_lw_cg.cp_rd_value +isacov.rv32i_lw_cg.cp_rd_toggle +* **Comments** + + *(none)* + +### Sub-feature: 003_LBU + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + lbu rd, rs1, imm + rd = Zext(M[rs1+imm][0:7]) + rd is calculated using unsigned arithmetic +* **Verification Goals** + + Register operands: + + All possible rs1 registers are used. + All possible rd registers are used. + All possible register combinations where rs1 == rd are used +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F003_S003_I000 +* **Link to Coverage:** isacov.rv32i_lbu_cg.cp_rs1 +isacov.rv32i_lbu_cg.cp_rd +isacov.rv32i_lbu_cg.cp_rd_rs1_hazard +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + lbu rd, rs1, imm + rd = Zext(M[rs1+imm][0:7]) + rd is calculated using unsigned arithmetic +* **Verification Goals** + + Input operands: + + immi value is +ve, -ve and zero + All combinations of rs1 and immi +ve, -ve, and zero values are used + All bits of rs1 are toggled + All bits of immi are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F003_S003_I001 +* **Link to Coverage:** isacov.rv32i_lbu_cg.cp_immi_value +isacov.rv32i_lbu_cg.cp_rs1_toggle +isacov.rv32i_lbu_cg.cp_immi_toggle +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + lbu rd, rs1, imm + rd = Zext(M[rs1+imm][0:7]) + rd is calculated using unsigned arithmetic +* **Verification Goals** + + Output result: + + rd value is +ve, -ve and zero + All bits of rd[7:0] are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F003_S003_I002 +* **Link to Coverage:** isacov.rv32i_lbu_cg.cp_rd_value +isacov.rv32i_lbu_cg.cp_rd_toggle +* **Comments** + + *(none)* + +### Sub-feature: 004_LHU + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + lhu rd, rs1, imm + rd = Zext(M[rs1+imm][0:15]) + rd is calculated using unsigned arithmetic +* **Verification Goals** + + Register operands: + + All possible rs1 registers are used. + All possible rd registers are used. + All possible register combinations where rs1 == rd are used +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F003_S004_I000 +* **Link to Coverage:** isacov.rv32i_lhu_cg.cp_rs1 +isacov.rv32i_lhu_cg.cp_rd +isacov.rv32i_lhu_cg.cp_rd_rs1_hazard +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + lhu rd, rs1, imm + rd = Zext(M[rs1+imm][0:15]) + rd is calculated using unsigned arithmetic +* **Verification Goals** + + Input operands: + + immi value is +ve, -ve and zero + All combinations of rs1 and immi +ve, -ve, and zero values are used + All bits of rs1 are toggled + All bits of immi are toggled + Unaligned and aligned accesses from memory +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F003_S004_I001 +* **Link to Coverage:** isacov.rv32i_lhu_cg.cp_immi_value +isacov.rv32i_lhu_cg.cp_rs1_toggle +isacov.rv32i_lhu_cg.cp_immi_toggle +isacov.rv32i_lhu_cg.cp_aligned +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + lhu rd, rs1, imm + rd = Zext(M[rs1+imm][0:15]) + rd is calculated using unsigned arithmetic +* **Verification Goals** + + Output result: + + rd value is +ve, -ve and zero + All bits of rd[15:0] are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F003_S004_I002 +* **Link to Coverage:** isacov.rv32i_lhu_cg.cp_rd_value +isacov.rv32i_lhu_cg.cp_rd_toggle +* **Comments** + + *(none)* + +### Sub-feature: 005_SB + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + sb rs1, rs2, imm + M[rs1+imm][0:7] = rs2[0:7] +* **Verification Goals** + + Register operands: + + All possible rs1 registers are used. + All possible rs2 registers are used. +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F003_S005_I000 +* **Link to Coverage:** isacov.rv32i_sb_cg.cp_rs1 +isacov.rv32i_sb_cg.cp_rs2 +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + sb rs1, rs2, imm + M[rs1+imm][0:7] = rs2[0:7] +* **Verification Goals** + + Input operands: + + imms value is +ve, -ve and zero + All bits of rs1 are toggled + All bits of rs2 are toggled + All bits of imms are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F003_S005_I001 +* **Link to Coverage:** isacov.rv32i_sb_cg.cp_imms_value +isacov.rv32i_sb_cg.cp_rs1_toggle +isacov.rv32i_sb_cg.cp_rs2_toggle +isacov.rv32i_sb_cg.cp_imms_toggle +* **Comments** + + *(none)* + +### Sub-feature: 006_SH + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + sh rs1, rs2, imm + M[rs1+imm][0:15] = rs2[0:15] +* **Verification Goals** + + Register operands: + + All possible rs1 registers are used. + All possible rs2 registers are used. +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F003_S006_I000 +* **Link to Coverage:** isacov.rv32i_sh_cg.cp_rs1 +isacov.rv32i_sh_cg.cp_rs2 +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + sh rs1, rs2, imm + M[rs1+imm][0:15] = rs2[0:15] +* **Verification Goals** + + Input operands: + + imms value is +ve, -ve and zero + All bits of rs1 are toggled + All bits of rs2 are toggled + All bits of imms are toggled + Unaligned and aligned accesses to memory +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F003_S006_I001 +* **Link to Coverage:** isacov.rv32i_sh_cg.cp_imms_value +isacov.rv32i_sh_cg.cp_rs1_toggle +isacov.rv32i_sh_cg.cp_rs2_toggle +isacov.rv32i_sh_cg.cp_imms_toggle +isacov.rv32i_sh_cg.cp_aligned +* **Comments** + + *(none)* + +### Sub-feature: 007_SW + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + sw rs1, rs2, imm + M[rs1+imm][0:31] = rs2[0:31] +* **Verification Goals** + + Register operands: + + All possible rs1 registers are used. + All possible rs2 registers are used. +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F003_S007_I000 +* **Link to Coverage:** isacov.rv32i_sw_cg.cp_rs1 +isacov.rv32i_sw_cg.cp_rs2 +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + sw rs1, rs2, imm + M[rs1+imm][0:31] = rs2[0:31] +* **Verification Goals** + + Input operands: + + imms value is +ve, -ve and zero + All bits of rs1 are toggled + All bits of rs2 are toggled + All bits of imms are toggled + Unaligned and aligned accesses to memory +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F003_S007_I001 +* **Link to Coverage:** isacov.rv32i_sw_cg.cp_imms_value +isacov.rv32i_sw_cg.cp_rs1_toggle +isacov.rv32i_sw_cg.cp_rs2_toggle +isacov.rv32i_sw_cg.cp_imms_toggle +isacov.rv32i_sw_cg.cp_aligned +* **Comments** + + *(none)* + +## Feature: RV32I Memory Ordering Instructions + +### Sub-feature: 000_FENCE + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + Fence operation executed + Implementation is microarchitecture specific +* **Verification Goals** + + Instruction executed +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F004_S000_I000 +* **Link to Coverage:** isacov.rv32i_fence.cp_fixed +* **Comments** + + *(none)* + +## Feature: RV32I Environment Call and Breakpoints + +### Sub-feature: 000_ECALL + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + Software exception vector entered +* **Verification Goals** + + Instruction executed +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F005_S000_I000 +* **Link to Coverage:** isacov.rv32i_ecall.cp_fixed +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + Return control to a debugger +* **Verification Goals** + + Instruction executed +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F005_S000_I001 +* **Link to Coverage:** isacov.rv32i_ebreak.cp_fixed +* **Comments** + + *(none)* + +### Sub-feature: 001_EBREAK + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + Return control to a debugger +* **Verification Goals** + + Instruction executed +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F005_S001_I000 +* **Link to Coverage:** isacov.rv32i_ebreak.cp_fixed +* **Comments** + + *(none)* + +## Feature: RV32M Multiplication Operations + +### Sub-feature: 000_MUL + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + mul rd, rs1, rs2 + x[rd] = x[rs1] * x[rs2] + Arithmetic overflow is ignored. +* **Verification Goals** + + Register operands: + + All possible rs1 registers are used. + All possible rs2 registers are used. + All possible rd registers are used. + All possible register combinations where rs1 == rd are used + All possible register combinations where rs2 == rd are used +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F006_S000_I000 +* **Link to Coverage:** isacov.rv32m_mul_cg.cp_rs1 +isacov.rv32m_mul_cg.cp_rs2 +isacov.rv32m_mul_cg.cp_rd +isacov.rv32m_mul_cg.cp_rd_rs1_hazard +isacov.rv32m_mul_cg.cp_rd_rs2_hazard +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + mul rd, rs1, rs2 + x[rd] = x[rs1] * x[rs2] + Arithmetic overflow is ignored. +* **Verification Goals** + + Input operands: + + rs1 value is non-zero and zero + rs2 value is non-zero and zero + All combinations of rs1 and rs2 non-zero and zero values are used + All bits of rs1 are toggled + All bits of rs2 are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F006_S000_I001 +* **Link to Coverage:** isacov.rv32m_mul_cg.cp_rs1_value +isacov.rv32m_mul_cg.cp_rs2_value +isacov.rv32m_mul_cg.cross_rs1_rs2_value +isacov.rv32m_mul_cg.cp_rs1_toggle +isacov.rv32m_mul_cg.cp_rs2_toggle +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + mul rd, rs1, rs2 + x[rd] = x[rs1] * x[rs2] + Arithmetic overflow is ignored. +* **Verification Goals** + + Output result: + + rd value is non-zero and zero + All bits of rd are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F006_S000_I002 +* **Link to Coverage:** isacov.rv32m_mul_cg.cp_rd_value +isacov.rv32m_mul_cg.cp_rd_toggle +* **Comments** + + *(none)* + +### Sub-feature: 001_MULH + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + mulh rd, rs1, rs2 + x[rd] = (x[rs1] * x[rs2]) >>s XLEN + Both rs1 and rs2 treated as signed numbers +* **Verification Goals** + + Output result: + + rd value is +ve, -ve and zero + All bits of rd are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F006_S001_I002 +* **Link to Coverage:** isacov.rv32m_mulh_cg.cp_rd_value +isacov.rv32m_mulh_cg.cp_rd_toggle +* **Comments** + + *(none)* + +### Sub-feature: 002_MULHU + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + mulhu rd, rs1, rs2 + x[rd] = (x[rs1] * x[rs2]) >> XLEN + Both rs1 and rs2 treated as unsigned numbers +* **Verification Goals** + + Register operands: + + All possible rs1 registers are used. + All possible rs2 registers are used. + All possible rd registers are used. + All possible register combinations where rs1 == rd are used + All possible register combinations where rs2 == rd are used +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F006_S002_I000 +* **Link to Coverage:** isacov.rv32m_mulhu_cg.cp_rs1 +isacov.rv32m_mulhu_cg.cp_rs2 +isacov.rv32m_mulhu_cg.cp_rd +isacov.rv32m_mulhu_cg.cp_rd_rs1_hazard +isacov.rv32m_mulhu_cg.cp_rd_rs2_hazard +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + mulhu rd, rs1, rs2 + x[rd] = (x[rs1] * x[rs2]) >> XLEN + Both rs1 and rs2 treated as unsigned numbers +* **Verification Goals** + + Input operands: + + rs1 value is non-zero and zero + rs2 value is non-zero and zero + All combinations of rs1 and rs2 non-zero and zero values are used + All bits of rs1 are toggled + All bits of rs2 are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F006_S002_I001 +* **Link to Coverage:** isacov.rv32m_mulhu_cg.cp_rs1_value +isacov.rv32m_mulhu_cg.cp_rs2_value +isacov.rv32m_mulhu_cg.cross_rs1_rs2_value +isacov.rv32m_mulhu_cg.cp_rs1_toggle +isacov.rv32m_mulhu_cg.cp_rs2_toggle +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + mulhu rd, rs1, rs2 + x[rd] = (x[rs1] * x[rs2]) >> XLEN + Both rs1 and rs2 treated as unsigned numbers +* **Verification Goals** + + Output result: + + rd value is non-zero and zero + All bits of rd are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F006_S002_I002 +* **Link to Coverage:** isacov.rv32m_mulhu_cg.cp_rd_value +isacov.rv32m_mulhu_cg.cp_rd_toggle +* **Comments** + + *(none)* + +### Sub-feature: 003_MULHSU + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + mulhsu rd, rs1, rs2 + x[rd] = (x[rs1] * x[rs2]) >>s XLEN + rs1 treated as signed number, rs2 treated as unsigned number +* **Verification Goals** + + Register operands: + + All possible rs1 registers are used. + All possible rs2 registers are used. + All possible rd registers are used. + All possible register combinations where rs1 == rd are used + All possible register combinations where rs2 == rd are used +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F006_S003_I000 +* **Link to Coverage:** isacov.rv32m_mulhsu_cg.cp_rs1 +isacov.rv32m_mulhsu_cg.cp_rs2 +isacov.rv32m_mulhsu_cg.cp_rd +isacov.rv32m_mulhsu_cg.cp_rd_rs1_hazard +isacov.rv32m_mulhsu_cg.cp_rd_rs2_hazard +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + mulhsu rd, rs1, rs2 + x[rd] = (x[rs1] * x[rs2]) >>s XLEN + rs1 treated as signed number, rs2 treated as unsigned number +* **Verification Goals** + + Input operands: + + rs1 value is +ve, -ve and zero + rs2 value is non-zero and zero + All combinations of rs1 and rs2 +ve, -ve, and zero values are used + All bits of rs1 are toggled + All bits of rs2 are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F006_S003_I001 +* **Link to Coverage:** isacov.rv32m_mulhsu_cg.cp_rs1_value +isacov.rv32m_mulhsu_cg.cp_rs2_value +isacov.rv32m_mulhsu_cg.cross_rs1_rs2_value +isacov.rv32m_mulhsu_cg.cp_rs1_toggle +isacov.rv32m_mulhsu_cg.cp_rs2_toggle +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + mulhsu rd, rs1, rs2 + x[rd] = (x[rs1] * x[rs2]) >>s XLEN + rs1 treated as signed number, rs2 treated as unsigned number +* **Verification Goals** + + Output result: + + rd value is +ve, -ve and zero + All bits of rd are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F006_S003_I002 +* **Link to Coverage:** isacov.rv32m_mulhsu_cg.cp_rd_value +isacov.rv32m_mulhsu_cg.cp_rd_toggle +* **Comments** + + *(none)* + +## Feature: RV32M Division Operations + +### Sub-feature: 000_DIV + +#### Item: 000 + +* **Requirement location:** Unprivileged ISA +Chapter 7.2 +* **Feature Description** + + div rd, rs1, rs2 + x[rd] = x[rs1] / x[rs2] + rd is calculated using signed arithmetic; rounding towards zero +* **Verification Goals** + + Register operands: + + All possible rs1 registers are used. + All possible rs2 registers are used. + All possible rd registers are used. + All possible register combinations where rs1 == rd are used + All possible register combinations where rs2 == rd are used +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F007_S000_I000 +* **Link to Coverage:** isacov.rv32m_div_cg.cp_rs1 +isacov.rv32m_div_cg.cp_rs2 +isacov.rv32m_div_cg.cp_rd +isacov.rv32m_div_cg.cp_rd_rs1_hazard +isacov.rv32m_div_cg.cp_rd_rs2_hazard +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** Unprivileged ISA +Chapter 7.2 +* **Feature Description** + + div rd, rs1, rs2 + x[rd] = x[rs1] / x[rs2] + rd is calculated using signed arithmetic; rounding towards zero +* **Verification Goals** + + Input operands: + + rs1 value is +ve, -ve and zero + rs2 value is +ve, -ve and zero + All combinations of rs1 and rs2 +ve, -ve, and zero values are used + All bits of rs1 are toggled + All bits of rs2 are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F007_S000_I001 +* **Link to Coverage:** isacov.rv32m_div_cg.cp_rs1_value +isacov.rv32m_div_cg.cp_rs2_value +isacov.rv32m_div_cg.cross_rs1_rs2_value +isacov.rv32m_div_cg.cp_rs1_toggle +isacov.rv32m_div_cg.cp_rs2_toggle +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** Unprivileged ISA +Chapter 7.2 +* **Feature Description** + + div rd, rs1, rs2 + x[rd] = x[rs1] / x[rs2] + rd is calculated using signed arithmetic; rounding towards zero +* **Verification Goals** + + Output result: + + rd value is +ve, -ve and zero + All bits of rd are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F007_S000_I002 +* **Link to Coverage:** isacov.rv32m_div_cg.cp_rs1_value +isacov.rv32m_div_cg.cp_rs2_value +isacov.rv32m_div_cg.cross_rs1_rs2_value +isacov.rv32m_div_cg.cp_rs1_toggle +isacov.rv32m_div_cg.cp_rs2_toggle +* **Comments** + + *(none)* + +#### Item: 003 + +* **Requirement location:** Unprivileged ISA +Chapter 7.2 +* **Feature Description** + + div rd, rs1, rs2 + x[rd] = x[rs1] / x[rs2] + rd is calculated using signed arithmetic; rounding towards zero +* **Verification Goals** + + Exercise arithmetic overflow (rs1 = -2^31; rs2 = -1; returns rd = -2^31). + Exercise division by zero (returns -1 ; all bits set) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F007_S000_I003 +* **Link to Coverage:** isacov.rv32m_div_results_cg.cp_div_special_results +isacov.rv32m_div_results_cg.cp_div_arithmetic_overflow +* **Comments** + + *(none)* + +### Sub-feature: 001_REM + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + rem rd, rs1, rs2 + x[rd] = x[rs1] % x[rs2] + rd is calculated using signed arithmetic; remainder from the same division than DIV (the sign of rd equals the sign of rs1) +* **Verification Goals** + + Register operands: + + All possible rs1 registers are used. + All possible rs2 registers are used. + All possible rd registers are used. + All possible register combinations where rs1 == rd are used + All possible register combinations where rs2 == rd are used +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F007_S001_I000 +* **Link to Coverage:** isacov.rv32m_rem_cg.cp_rs1 +isacov.rv32m_rem_cg.cp_rs2 +isacov.rv32m_rem_cg.cp_rd +isacov.rv32m_rem_cg.cp_rd_rs1_hazard +isacov.rv32m_rem_cg.cp_rd_rs2_hazard +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + rem rd, rs1, rs2 + x[rd] = x[rs1] % x[rs2] + rd is calculated using signed arithmetic; remainder from the same division than DIV (the sign of rd equals the sign of rs1) +* **Verification Goals** + + Input operands: + + rs1 value is +ve, -ve and zero + rs2 value is +ve, -ve and zero + All combinations of rs1 and rs2 +ve, -ve, and zero values are used + All bits of rs1 are toggled + All bits of rs2 are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F007_S001_I001 +* **Link to Coverage:** isacov.rv32m_rem_cg.cp_rs1_value +isacov.rv32m_rem_cg.cp_rs2_value +isacov.rv32m_rem_cg.cross_rs1_rs2_value +isacov.rv32m_rem_cg.cp_rs1_toggle +isacov.rv32m_rem_cg.cp_rs2_toggle +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + rem rd, rs1, rs2 + x[rd] = x[rs1] % x[rs2] + rd is calculated using signed arithmetic; remainder from the same division than DIV (the sign of rd equals the sign of rs1) +* **Verification Goals** + + Output result: + + rd value is +ve, -ve and zero + All bits of rd are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F007_S001_I002 +* **Link to Coverage:** isacov.rv32m_rem_cg.cp_rd_value +isacov.rv32m_rem_cg.cp_rd_toggle +* **Comments** + + *(none)* + +#### Item: 003 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + rem rd, rs1, rs2 + x[rd] = x[rs1] % x[rs2] + rd is calculated using signed arithmetic; remainder from the same division than DIV (the sign of rd equals the sign of rs1) +* **Verification Goals** + + Exercise arithmetic overflow (rs1 = -2^31; rs2 = -1; returns rd = 0). + Exercise division by zero (returns rs1) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F007_S001_I003 +* **Link to Coverage:** isacov.rv32m_rem_results_cg.cp_div_zero +isacov.rv32m_rem_results_cg.cp_div_arithmetic_overflow +* **Comments** + + *(none)* + +### Sub-feature: 002_DIVU + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + divu rd, rs1, rs2 + x[rd] = x[rs1] u/ x[rs2] + rd is calculated using unsigned arithmetic; rounding towards zero +* **Verification Goals** + + Register operands: + + All possible rs1 registers are used. + All possible rs2 registers are used. + All possible rd registers are used. + All possible register combinations where rs1 == rd are used + All possible register combinations where rs2 == rd are used +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F007_S002_I000 +* **Link to Coverage:** isacov.rv32m_divu_cg.cp_rs1 +isacov.rv32m_divu_cg.cp_rs2 +isacov.rv32m_divu_cg.cp_rd +isacov.rv32m_divu_cg.cp_rd_rs1_hazard +isacov.rv32m_divu_cg.cp_rd_rs2_hazard +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + divu rd, rs1, rs2 + x[rd] = x[rs1] u/ x[rs2] + rd is calculated using unsigned arithmetic; rounding towards zero +* **Verification Goals** + + Input operands: + + rs1 value is non-zero and zero + rs2 value is non-zero and zero + All combinations of rs1 and rs2 non-zero and zero values are used + All bits of rs1 are toggled + All bits of rs2 are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F007_S002_I001 +* **Link to Coverage:** isacov.rv32m_divu_cg.cp_rs1_value +isacov.rv32m_divu_cg.cp_rs2_value +isacov.rv32m_divu_cg.cross_rs1_rs2_value +isacov.rv32m_divu_cg.cp_rs1_toggle +isacov.rv32m_divu_cg.cp_rs2_toggle +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + divu rd, rs1, rs2 + x[rd] = x[rs1] u/ x[rs2] + rd is calculated using unsigned arithmetic; rounding towards zero +* **Verification Goals** + + Output result: + + rd value is non-zero and zero + All bits of rd are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F007_S002_I002 +* **Link to Coverage:** isacov.rv32m_divu_cg.cp_rd_value +isacov.rv32m_divu_cg.cp_rd_toggle +* **Comments** + + *(none)* + +#### Item: 003 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + divu rd, rs1, rs2 + x[rd] = x[rs1] u/ x[rs2] + rd is calculated using unsigned arithmetic; rounding towards zero +* **Verification Goals** + + Exercise division by zero (returns 2^32-1 ; all bits set) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F007_S002_I003 +* **Link to Coverage:** isacov.rv32m_divu_results_cg.cp_div_zero +* **Comments** + + *(none)* + +### Sub-feature: 003_REMU + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + remu rd, rs1, rs2 + x[rd] = x[rs1] % x[rs2] + rd is calculated using unsigned arithmetic; remainder from the same division than DIVU +* **Verification Goals** + + Register operands: + + All possible rs1 registers are used. + All possible rs2 registers are used. + All possible rd registers are used. + All possible register combinations where rs1 == rd are used + All possible register combinations where rs2 == rd are used +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F007_S003_I000 +* **Link to Coverage:** isacov.rv32m_remu_cg.cp_rs1 +isacov.rv32m_remu_cg.cp_rs2 +isacov.rv32m_remu_cg.cp_rd +isacov.rv32m_remu_cg.cp_rd_rs1_hazard +isacov.rv32m_remu_cg.cp_rd_rs2_hazard +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + remu rd, rs1, rs2 + x[rd] = x[rs1] % x[rs2] + rd is calculated using unsigned arithmetic; remainder from the same division than DIVU +* **Verification Goals** + + Input operands: + + rs1 value is non-zero and zero + rs2 value is non-zero and zero + All combinations of rs1 and rs2 non-zero and zero values are used + All bits of rs1 are toggled + All bits of rs2 are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F007_S003_I001 +* **Link to Coverage:** isacov.rv32m_remu_cg.cp_rs1_value +isacov.rv32m_remu_cg.cp_rs2_value +isacov.rv32m_remu_cg.cross_rs1_rs2_value +isacov.rv32m_remu_cg.cp_rs1_toggle +isacov.rv32m_remu_cg.cp_rs2_toggle +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + remu rd, rs1, rs2 + x[rd] = x[rs1] % x[rs2] + rd is calculated using unsigned arithmetic; remainder from the same division than DIVU +* **Verification Goals** + + Output result: + + rd value is non-zero and zero + All bits of rd are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F007_S003_I002 +* **Link to Coverage:** isacov.rv32m_remu_cg.cp_rd_value +isacov.rv32m_remu_cg.cp_rd_toggle +* **Comments** + + *(none)* + +#### Item: 003 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + remu rd, rs1, rs2 + x[rd] = x[rs1] % x[rs2] + rd is calculated using unsigned arithmetic; remainder from the same division than DIVU +* **Verification Goals** + + Exercise division by zero (returns rs1) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F007_S003_I003 +* **Link to Coverage:** isacov.rv32m_remu_results_cg.cp_div_zero +* **Comments** + + *(none)* + +## Feature: RV32A Load-Reserved/Store-Conditional Instructions + +### Sub-feature: 000_LR.W + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + lr.w rd, (rs1) + rd = [rs1] + A load occurs to address at rs1 with the results loaded to rd. + Misaligned address should cause an exception +* **Verification Goals** + + Register operands: + + All possible rs1 registers are used. + All possible rd registers are used. + All possible register combinations where rs1 == rd are used +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F008_S000_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + lr.w rd, (rs1) + rd = [rs1] + A load occurs to address at rs1 with the results loaded to rd. + Misaligned address should cause an exception +* **Verification Goals** + + Input operands: + + All bits of rs1 are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F008_S000_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + lr.w rd, (rs1) + rd = [rs1] + A load occurs to address at rs1 with the results loaded to rd. + Misaligned address should cause an exception +* **Verification Goals** + + Output result: + + All bits of rd are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F008_S000_I002 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 003 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + lr.w rd, (rs1) + rd = [rs1] + A load occurs to address at rs1 with the results loaded to rd. + Misaligned address should cause an exception +* **Verification Goals** + + Exception: + + Misaligned address (non-32-bit aligned) will always cause exceptio +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F008_S000_I003 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 001_SC.W + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + sc.w rd, rs2, (rs1) + [rs1] = rs2 + rd = exokay ? 0 : 1 + A store occurs to address at rs1 with data from rs2. + If the reservation set from a previous LR.W fails, then rd is set to a non-zero value and the store does not occur. + If the reservation set passes, then rd is set to a zero-value and the store succeeds. +* **Verification Goals** + + Register operands: + + All possible rs1 registers are used. + All possible rd registers are used. + All possible register combinations where rs1 == rd are used + All possible register combinations where rs2 == rd are used +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F008_S001_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + sc.w rd, rs2, (rs1) + [rs1] = rs2 + rd = exokay ? 0 : 1 + A store occurs to address at rs1 with data from rs2. + If the reservation set from a previous LR.W fails, then rd is set to a non-zero value and the store does not occur. + If the reservation set passes, then rd is set to a zero-value and the store succeeds. +* **Verification Goals** + + Input operands: + + All bits of rs1 are toggled + All bits of rs2 are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F008_S001_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + sc.w rd, rs2, (rs1) + [rs1] = rs2 + rd = exokay ? 0 : 1 + A store occurs to address at rs1 with data from rs2. + If the reservation set from a previous LR.W fails, then rd is set to a non-zero value and the store does not occur. + If the reservation set passes, then rd is set to a zero-value and the store succeeds. +* **Verification Goals** + + Output result: + + rd is either zero or non-zero to indicate success or failure, respectively +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F008_S001_I002 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 003 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + sc.w rd, rs2, (rs1) + [rs1] = rs2 + rd = exokay ? 0 : 1 + A store occurs to address at rs1 with data from rs2. + If the reservation set from a previous LR.W fails, then rd is set to a non-zero value and the store does not occur. + If the reservation set passes, then rd is set to a zero-value and the store succeeds. +* **Verification Goals** + + Exception: + + Misaligned address (non-32-bit aligned) will always cause exception +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F008_S001_I003 +* **Link to Coverage:** +* **Comments** + + *(none)* + +## Feature: RV32A Atomic Memory Operations + +### Sub-feature: 000_AMOSWAP.W + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + amoswap.w rd, rs2, (rs1) + rd = [rs1] + [rs1] = rs2 + A load occurs from the address at rs1 into rd. + The value at rs2 is then written back to the address at (rs1) +* **Verification Goals** + + Input operands: + + All possible rs1 registers are used. + All possible rs2 registers are used. + All possible rd registers are used. + All possible register combinations where rs1 == rd are used + All possible register combinations where rs2 == rd are used +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F009_S000_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + amoswap.w rd, rs2, (rs1) + rd = [rs1] + [rs1] = rs2 + A load occurs from the address at rs1 into rd. + The value at rs2 is then written back to the address at (rs1) +* **Verification Goals** + + Input operands: + + All bits of rs1 are toggled + All bits of rs2 are toggled + Zero and non-zero values of rs2 are used +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F009_S000_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + amoswap.w rd, rs2, (rs1) + rd = [rs1] + [rs1] = rs2 + A load occurs from the address at rs1 into rd. + The value at rs2 is then written back to the address at (rs1) +* **Verification Goals** + + Output result: + + All bits of rd are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F009_S000_I002 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 003 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + amoswap.w rd, rs2, (rs1) + rd = [rs1] + [rs1] = rs2 + A load occurs from the address at rs1 into rd. + The value at rs2 is then written back to the address at (rs1) +* **Verification Goals** + + Exception: + + Misaligned address (non-32-bit aligned) will always cause exception +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F009_S000_I003 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 001_AMOADD.W + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + amoadd.w rd, rs2, (rs1) + rd = [rs1] + [rs1] = rs2 + [rs1] + A load occurs from the address at rs1 into rd. + The values in rd and rs2 and added using signed arithmetic and the result iis then written back to the address at (rs1) +* **Verification Goals** + + Input operands: + + All possible rs1 registers are used. + All possible rs2 registers are used. + All possible rd registers are used. + All possible register combinations where rs1 == rd are used + All possible register combinations where rs2 == rd are used +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F009_S001_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + amoadd.w rd, rs2, (rs1) + rd = [rs1] + [rs1] = rs2 + [rs1] + A load occurs from the address at rs1 into rd. + The values in rd and rs2 and added using signed arithmetic and the result iis then written back to the address at (rs1) +* **Verification Goals** + + Input operands: + + All bits of rs1 are toggled + All bits of rs2 are toggled + +ve, -ve and zero values of rs2 are used +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F009_S001_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + amoadd.w rd, rs2, (rs1) + rd = [rs1] + [rs1] = rs2 + [rs1] + A load occurs from the address at rs1 into rd. + The values in rd and rs2 and added using signed arithmetic and the result iis then written back to the address at (rs1) +* **Verification Goals** + + Output result: + + +ve, -ve and zero values of rd are used + All bits of rd are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F009_S001_I002 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 003 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + amoadd.w rd, rs2, (rs1) + rd = [rs1] + [rs1] = rs2 + [rs1] + A load occurs from the address at rs1 into rd. + The values in rd and rs2 and added using signed arithmetic and the result iis then written back to the address at (rs1) +* **Verification Goals** + + Exception: + + Misaligned address (non-32-bit aligned) will always cause exception +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F009_S001_I003 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 002_AMOAND.W + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + amoand.w rd, rs2, (rs1) + rd = [rs1] + [rs1] = rs2 & rs[1] + A load occurs from the address at rs1 into rd. + The values in rd and rs2 and bit-wise ANDed and the result iis then written back to the address at (rs1) +* **Verification Goals** + + Input operands: + + All possible rs1 registers are used. + All possible rs2 registers are used. + All possible rd registers are used. + All possible register combinations where rs1 == rd are used + All possible register combinations where rs2 == rd are used +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F009_S002_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + amoand.w rd, rs2, (rs1) + rd = [rs1] + [rs1] = rs2 & rs[1] + A load occurs from the address at rs1 into rd. + The values in rd and rs2 and bit-wise ANDed and the result iis then written back to the address at (rs1) +* **Verification Goals** + + Input operands: + + All bits of rs1 are toggled + All bits of rs2 are toggled + Zero and non-zero values of rs2 are used +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F009_S002_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + amoand.w rd, rs2, (rs1) + rd = [rs1] + [rs1] = rs2 & rs[1] + A load occurs from the address at rs1 into rd. + The values in rd and rs2 and bit-wise ANDed and the result iis then written back to the address at (rs1) +* **Verification Goals** + + Output result: + + All bits of rd are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F009_S002_I002 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 003 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + amoand.w rd, rs2, (rs1) + rd = [rs1] + [rs1] = rs2 & rs[1] + A load occurs from the address at rs1 into rd. + The values in rd and rs2 and bit-wise ANDed and the result iis then written back to the address at (rs1) +* **Verification Goals** + + Exception: + + Misaligned address (non-32-bit aligned) will always cause exception +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F009_S002_I003 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 003_AMOOR.W + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + amoor.w rd, rs2, (rs1) + rd = [rs1] + [rs1] = rs2 | [rs1] + A load occurs from the address at rs1 into rd. + The values in rd and rs2 and bit-wise ORed and the result iis then written back to the address at (rs1) +* **Verification Goals** + + Input operands: + + All possible rs1 registers are used. + All possible rs2 registers are used. + All possible rd registers are used. + All possible register combinations where rs1 == rd are used + All possible register combinations where rs2 == rd are used +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F009_S003_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + amoor.w rd, rs2, (rs1) + rd = [rs1] + [rs1] = rs2 | [rs1] + A load occurs from the address at rs1 into rd. + The values in rd and rs2 and bit-wise ORed and the result iis then written back to the address at (rs1) +* **Verification Goals** + + Input operands: + + All bits of rs1 are toggled + All bits of rs2 are toggled + Zero and non-zero values of rs2 are used +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F009_S003_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + amoor.w rd, rs2, (rs1) + rd = [rs1] + [rs1] = rs2 | [rs1] + A load occurs from the address at rs1 into rd. + The values in rd and rs2 and bit-wise ORed and the result iis then written back to the address at (rs1) +* **Verification Goals** + + Output result: + + All bits of rd are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F009_S003_I002 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 003 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + amoor.w rd, rs2, (rs1) + rd = [rs1] + [rs1] = rs2 | [rs1] + A load occurs from the address at rs1 into rd. + The values in rd and rs2 and bit-wise ORed and the result iis then written back to the address at (rs1) +* **Verification Goals** + + Exception: + + Misaligned address (non-32-bit aligned) will always cause exception +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F009_S003_I003 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 004_AMOXOR.W + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + amoxor.w rd, rs2, (rs1) + rd = [rs1] + [rs1] = rs2 ^ [rs1] + A load occurs from the address at rs1 into rd. + The values in rd and rs2 and bit-wise XORRed and the result iis then written back to the address at (rs1) +* **Verification Goals** + + Input operands: + + All possible rs1 registers are used. + All possible rs2 registers are used. + All possible rd registers are used. + All possible register combinations where rs1 == rd are used + All possible register combinations where rs2 == rd are used +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F009_S004_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + amoxor.w rd, rs2, (rs1) + rd = [rs1] + [rs1] = rs2 ^ [rs1] + A load occurs from the address at rs1 into rd. + The values in rd and rs2 and bit-wise XORRed and the result iis then written back to the address at (rs1) +* **Verification Goals** + + Input operands: + + All bits of rs1 are toggled + All bits of rs2 are toggled + Zero and non-zero values of rs2 are used +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F009_S004_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + amoxor.w rd, rs2, (rs1) + rd = [rs1] + [rs1] = rs2 ^ [rs1] + A load occurs from the address at rs1 into rd. + The values in rd and rs2 and bit-wise XORRed and the result iis then written back to the address at (rs1) +* **Verification Goals** + + Output result: + + All bits of rd are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F009_S004_I002 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 003 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + amoxor.w rd, rs2, (rs1) + rd = [rs1] + [rs1] = rs2 ^ [rs1] + A load occurs from the address at rs1 into rd. + The values in rd and rs2 and bit-wise XORRed and the result iis then written back to the address at (rs1) +* **Verification Goals** + + Exception: + + Misaligned address (non-32-bit aligned) will always cause exception +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F009_S004_I003 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 005_AMOMAX.W + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + amomax.w rd, rs2, (rs1) + rd = [rs1] + [rs1] = max_signed(rs2, [rs1]) + A load occurs from the address at rs1 into rd. + The values in rd and rs2 and compared assuming signed numbers and the largest value is then written back to the address at (rs1) +* **Verification Goals** + + Input operands: + + All possible rs1 registers are used. + All possible rs2 registers are used. + All possible rd registers are used. + All possible register combinations where rs1 == rd are used + All possible register combinations where rs2 == rd are used +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F009_S005_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + amomax.w rd, rs2, (rs1) + rd = [rs1] + [rs1] = max_signed(rs2, [rs1]) + A load occurs from the address at rs1 into rd. + The values in rd and rs2 and compared assuming signed numbers and the largest value is then written back to the address at (rs1) +* **Verification Goals** + + Input operands: + + All bits of rs1 are toggled + All bits of rs2 are toggled + +ve, -ve and zero values of rs2 are used +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F009_S005_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + amomax.w rd, rs2, (rs1) + rd = [rs1] + [rs1] = max_signed(rs2, [rs1]) + A load occurs from the address at rs1 into rd. + The values in rd and rs2 and compared assuming signed numbers and the largest value is then written back to the address at (rs1) +* **Verification Goals** + + Output result: + + +ve, -ve and zero values of rd are used + All bits of rd are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F009_S005_I002 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 003 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + amomax.w rd, rs2, (rs1) + rd = [rs1] + [rs1] = max_signed(rs2, [rs1]) + A load occurs from the address at rs1 into rd. + The values in rd and rs2 and compared assuming signed numbers and the largest value is then written back to the address at (rs1) +* **Verification Goals** + + Exception: + + Misaligned address (non-32-bit aligned) will always cause exception +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F009_S005_I003 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 006_AMOMAXU.W + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + amomaxu.w rd, rs2, (rs1) + rd = [rs1] + [rs1] = max_unsigned(rs2, [rs1]) + A load occurs from the address at rs1 into rd. + The values in rd and rs2 and compared assuming unsigned numbers and the largest value is then written back to the address at (rs1) +* **Verification Goals** + + Input operands: + + All possible rs1 registers are used. + All possible rs2 registers are used. + All possible rd registers are used. + All possible register combinations where rs1 == rd are used + All possible register combinations where rs2 == rd are used +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F009_S006_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + amomaxu.w rd, rs2, (rs1) + rd = [rs1] + [rs1] = max_unsigned(rs2, [rs1]) + A load occurs from the address at rs1 into rd. + The values in rd and rs2 and compared assuming unsigned numbers and the largest value is then written back to the address at (rs1) +* **Verification Goals** + + Input operands: + + All bits of rs1 are toggled + All bits of rs2 are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F009_S006_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + amomaxu.w rd, rs2, (rs1) + rd = [rs1] + [rs1] = max_unsigned(rs2, [rs1]) + A load occurs from the address at rs1 into rd. + The values in rd and rs2 and compared assuming unsigned numbers and the largest value is then written back to the address at (rs1) +* **Verification Goals** + + Output result: + + All bits of rd are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F009_S006_I002 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 003 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + amomaxu.w rd, rs2, (rs1) + rd = [rs1] + [rs1] = max_unsigned(rs2, [rs1]) + A load occurs from the address at rs1 into rd. + The values in rd and rs2 and compared assuming unsigned numbers and the largest value is then written back to the address at (rs1) +* **Verification Goals** + + Exception: + + Misaligned address (non-32-bit aligned) will always cause exception +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F009_S006_I003 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 007_AMOMIN.W + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + amomin.w rd, rs2, (rs1) + rd = [rs1] + [rs1] = min_signed(rs2, [rs1]) + A load occurs from the address at rs1 into rd. + The values in rd and rs2 and compared assuming signed numbers and the smaller value is then written back to the address at (rs1) +* **Verification Goals** + + Input operands: + + All possible rs1 registers are used. + All possible rs2 registers are used. + All possible rd registers are used. + All possible register combinations where rs1 == rd are used + All possible register combinations where rs2 == rd are used +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F009_S007_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + amomin.w rd, rs2, (rs1) + rd = [rs1] + [rs1] = min_signed(rs2, [rs1]) + A load occurs from the address at rs1 into rd. + The values in rd and rs2 and compared assuming signed numbers and the smaller value is then written back to the address at (rs1) +* **Verification Goals** + + Input operands: + + All bits of rs1 are toggled + All bits of rs2 are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F009_S007_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + amomin.w rd, rs2, (rs1) + rd = [rs1] + [rs1] = min_signed(rs2, [rs1]) + A load occurs from the address at rs1 into rd. + The values in rd and rs2 and compared assuming signed numbers and the smaller value is then written back to the address at (rs1) +* **Verification Goals** + + Output result: + + +ve, -ve and zero values of rd are used + All bits of rd are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F009_S007_I002 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 003 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + amomin.w rd, rs2, (rs1) + rd = [rs1] + [rs1] = min_signed(rs2, [rs1]) + A load occurs from the address at rs1 into rd. + The values in rd and rs2 and compared assuming signed numbers and the smaller value is then written back to the address at (rs1) +* **Verification Goals** + + Exception: + + Misaligned address (non-32-bit aligned) will always cause exception +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F009_S007_I003 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 008_AMOMINU.W + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + amominu.w rd, rs2, (rs1) + rd = [rs1] + [rs1] = min_unsigned(rs2, [rs1]) + A load occurs from the address at rs1 into rd. + The values in rd and rs2 and compared assuming unsigned numbers and the smaller value is then written back to the address at (rs1) +* **Verification Goals** + + Input operands: + + All possible rs1 registers are used. + All possible rs2 registers are used. + All possible rd registers are used. + All possible register combinations where rs1 == rd are used + All possible register combinations where rs2 == rd are used +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F009_S008_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + amominu.w rd, rs2, (rs1) + rd = [rs1] + [rs1] = min_unsigned(rs2, [rs1]) + A load occurs from the address at rs1 into rd. + The values in rd and rs2 and compared assuming unsigned numbers and the smaller value is then written back to the address at (rs1) +* **Verification Goals** + + Input operands: + + All bits of rs1 are toggled + All bits of rs2 are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F009_S008_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + amominu.w rd, rs2, (rs1) + rd = [rs1] + [rs1] = min_unsigned(rs2, [rs1]) + A load occurs from the address at rs1 into rd. + The values in rd and rs2 and compared assuming unsigned numbers and the smaller value is then written back to the address at (rs1) +* **Verification Goals** + + Output result: + + All bits of rd are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F009_S008_I002 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 003 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + amominu.w rd, rs2, (rs1) + rd = [rs1] + [rs1] = min_unsigned(rs2, [rs1]) + A load occurs from the address at rs1 into rd. + The values in rd and rs2 and compared assuming unsigned numbers and the smaller value is then written back to the address at (rs1) +* **Verification Goals** + + Exception: + + Misaligned address (non-32-bit aligned) will always cause exception +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F009_S008_I003 +* **Link to Coverage:** +* **Comments** + + *(none)* + +## Feature: RV32C Integer Computational Instructions + +### Sub-feature: 000_C.LI + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + c.li rd, imm[5:0] + x[rd] = sext(imm) + Expands to addi rd, x0, imm[5:0]. Invalid when rd=x0. + rd is calculated using signed arithmetic +* **Verification Goals** + + Input operands: + + All bits of imm[5:0] are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F010_S000_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + c.li rd, imm[5:0] + x[rd] = sext(imm) + Expands to addi rd, x0, imm[5:0]. Invalid when rd=x0. + rd is calculated using signed arithmetic +* **Verification Goals** + + Output result: + + All bits of rd are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F010_S000_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 001_C.LUI + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + c.lui rd, nzimm[17:12] + x[rd] = sext(nzimm[17:12] << 12) + Expands to lui rd, nzimm[17:12]. Invalid when rd = {x0, x2} or imm = 0. + rd is calculated using signed arithmetic. +* **Verification Goals** + + Input operands: + + All bits of imm[17:12] are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F010_S001_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + c.lui rd, nzimm[17:12] + x[rd] = sext(nzimm[17:12] << 12) + Expands to lui rd, nzimm[17:12]. Invalid when rd = {x0, x2} or imm = 0. + rd is calculated using signed arithmetic. +* **Verification Goals** + + Output result: + + All bits of rd[31:12] are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F010_S001_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 002_C.ADDI + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + c.addi rd, nzimm[5:0] + x[rd] = x[rd] + sext(nzimm[5:0]) + Expands to addi rd, rd, nzimm[5:0]. + Invalid when rd=x0 or nzimm = 0. Arithmetic overflow is lost and ignored. + rd is calculated using signed arithmetic. +* **Verification Goals** + + Register operands: + + All possible rd registers are used. +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F010_S002_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + c.addi rd, nzimm[5:0] + x[rd] = x[rd] + sext(nzimm[5:0]) + Expands to addi rd, rd, nzimm[5:0]. + Invalid when rd=x0 or nzimm = 0. Arithmetic overflow is lost and ignored. + rd is calculated using signed arithmetic. +* **Verification Goals** + + Input operands: + + All inputs bits of rd before instruction execution are toggled + All bits of nzimm are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F010_S002_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + c.addi rd, nzimm[5:0] + x[rd] = x[rd] + sext(nzimm[5:0]) + Expands to addi rd, rd, nzimm[5:0]. + Invalid when rd=x0 or nzimm = 0. Arithmetic overflow is lost and ignored. + rd is calculated using signed arithmetic. +* **Verification Goals** + + Output result: + + All bits of rd are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F010_S002_I002 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 003_C.ADDI16SP + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + c.addi16sp nzimm[9:4] + x[2] = x[2] + sext(nzimm[9:4]) + Expands to addi x2, x2, nzimm[9:4]. Invalid when nzimm=0. + rd is calculated using signed arithmetic. +* **Verification Goals** + + Input operands: + + +ve and -ve values of nzimm are used + All bits of nzimm[9:4] are toggled + All bits of x2 before instruction execution are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F010_S003_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + c.addi16sp nzimm[9:4] + x[2] = x[2] + sext(nzimm[9:4]) + Expands to addi x2, x2, nzimm[9:4]. Invalid when nzimm=0. + rd is calculated using signed arithmetic. +* **Verification Goals** + + Output result: + + All bits of x2 are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F010_S003_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 004_C.ADDI4SPN + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + c.addi4spn rd', nzuimm[9:2] + x[8+rd'] = x[2] + nzuimm[9:2] + Expands to addi rd', x2, nzuimm[9:2]. Invalid when nzuimm = 0. + rd is calculated using signed arithmetic. +* **Verification Goals** + + Register operands: + + All possible rd` registers are used. +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F010_S004_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + c.addi4spn rd', nzuimm[9:2] + x[8+rd'] = x[2] + nzuimm[9:2] + Expands to addi rd', x2, nzuimm[9:2]. Invalid when nzuimm = 0. + rd is calculated using signed arithmetic. +* **Verification Goals** + + Input operands: + + All bits of nzuimm[9:2] are toggled + All bits of x2 before instruction execution are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F010_S004_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + c.addi4spn rd', nzuimm[9:2] + x[8+rd'] = x[2] + nzuimm[9:2] + Expands to addi rd', x2, nzuimm[9:2]. Invalid when nzuimm = 0. + rd is calculated using signed arithmetic. +* **Verification Goals** + + Output result: + + All bits of rd` are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F010_S004_I002 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 005_C.SLLI + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + c.slli rd, uimm[5:0] + x[rd] = x[rd] << uimm[5:0] + Expands to slli rd, rd, uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0, or rd=x0. +* **Verification Goals** + + Register operands: + + All possible rd registers are used. +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F010_S005_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + c.slli rd, uimm[5:0] + x[rd] = x[rd] << uimm[5:0] + Expands to slli rd, rd, uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0, or rd=x0. +* **Verification Goals** + + Input operands: + + All shift amounts from [0:31] are used + All bits of rd before instruction execution are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F010_S005_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + c.slli rd, uimm[5:0] + x[rd] = x[rd] << uimm[5:0] + Expands to slli rd, rd, uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0, or rd=x0. +* **Verification Goals** + + Output result: + + All bits of rd are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F010_S005_I002 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 006_C.SRLI + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + c.srli rd', uimm[5:0] + x[8+rd'] = x[8+rd'] >>u uimm[5:0] + Expands to srli rd', rd', uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0, +* **Verification Goals** + + Register operands: + + All possible rd` registers are used. +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F010_S006_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + c.srli rd', uimm[5:0] + x[8+rd'] = x[8+rd'] >>u uimm[5:0] + Expands to srli rd', rd', uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0, +* **Verification Goals** + + Input operands: + + All shift amounts from [0:31] are used + All bits of rd before instruction execution are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F010_S006_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + c.srli rd', uimm[5:0] + x[8+rd'] = x[8+rd'] >>u uimm[5:0] + Expands to srli rd', rd', uimm[5:0]. Invalid when uimm[5] = 1, or uimm=0, +* **Verification Goals** + + Output result: + + All bits of rd are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F010_S006_I002 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 007_C.SRAI + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + c.srai rd', uimm[5:0] + x[8+rd'] = x[8+rd'] >> uimm[5:0] + Expands to srai rd', rd', uimm[5:0]. +* **Verification Goals** + + Register operands: + + All possible rd` registers are used. +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F010_S007_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + c.srai rd', uimm[5:0] + x[8+rd'] = x[8+rd'] >> uimm[5:0] + Expands to srai rd', rd', uimm[5:0]. +* **Verification Goals** + + Input operands: + + All shift amounts from [0:31] are used + +ve, -ve and zero values of rd` are used + All bits of rd` before instruction execution are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F010_S007_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + c.srai rd', uimm[5:0] + x[8+rd'] = x[8+rd'] >> uimm[5:0] + Expands to srai rd', rd', uimm[5:0]. +* **Verification Goals** + + Output result: + + All bits of rd` are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F010_S007_I002 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 008_C.ANDI + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + c.andi rd', imm[5:0] + x[8+rd'] = x[8+rd'] & sext(imm[5:0]) + Expands to andi rd', rd', imm[5:0]. + imm treated as signed number +* **Verification Goals** + + Register operands: + + All possible rd` registers are used. +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F010_S008_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + c.andi rd', imm[5:0] + x[8+rd'] = x[8+rd'] & sext(imm[5:0]) + Expands to andi rd', rd', imm[5:0]. + imm treated as signed number +* **Verification Goals** + + Input operands: + + All shift amounts from [0:31] are used + +ve, -ve and zero values of imm are used + All bits of rd` before instruction execution are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F010_S008_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + c.andi rd', imm[5:0] + x[8+rd'] = x[8+rd'] & sext(imm[5:0]) + Expands to andi rd', rd', imm[5:0]. + imm treated as signed number +* **Verification Goals** + + Output result: + + All bits of rd` are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F010_S008_I002 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 009_C.MV + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + c.mv rd, rs2 + x[rd] = x[rs2] + Expands to add rd, x0, rs2 + Invalid when rs2=x0 or rd=x0. +* **Verification Goals** + + Register operands: + + All possible rd registers are used. + All possible register combinations where rs2 == rd are used +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F010_S009_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + c.mv rd, rs2 + x[rd] = x[rs2] + Expands to add rd, x0, rs2 + Invalid when rs2=x0 or rd=x0. +* **Verification Goals** + + Input operands: + + All bits of rs2 are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F010_S009_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + c.mv rd, rs2 + x[rd] = x[rs2] + Expands to add rd, x0, rs2 + Invalid when rs2=x0 or rd=x0. +* **Verification Goals** + + Output result: + + All bits of rd are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F010_S009_I002 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 010_C.ADD + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + c.add rd, rs2 + x[rd] = x[rd] + x[rs2] + Expands to add rd, rd, rs2. Invalid when rd=x0 or rs2=x0. + Arithmetic overflow is lost and ignored +* **Verification Goals** + + Register operands: + + All possible rd registers are used. +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F010_S010_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + c.add rd, rs2 + x[rd] = x[rd] + x[rs2] + Expands to add rd, rd, rs2. Invalid when rd=x0 or rs2=x0. + Arithmetic overflow is lost and ignored +* **Verification Goals** + + Input operands: + + +ve,-ve and zero values of rs2 are used + +ve,-ve, and zero values of rdrs1 are used + All bits of rs2 are toggled + All bits of rd before instruction execution are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F010_S010_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + c.add rd, rs2 + x[rd] = x[rd] + x[rs2] + Expands to add rd, rd, rs2. Invalid when rd=x0 or rs2=x0. + Arithmetic overflow is lost and ignored +* **Verification Goals** + + Output result: + + All bits of rd are toggled + +ve,-ve and zero values of rd are used +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F010_S010_I002 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 011_C.AND + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + c.and rd', rs2' + x[8+rd'] = x[8+rd'] & x[8+rs2'] + Expands to and rd', rd', rs2'. +* **Verification Goals** + + Register operands: + + All possible rd` registers are used. +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F010_S011_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + c.and rd', rs2' + x[8+rd'] = x[8+rd'] & x[8+rs2'] + Expands to and rd', rd', rs2'. +* **Verification Goals** + + Input operands: + + Non-zero and zero values of rs2` are used + Non-zero and zero values of rd` are used + All bits of rs2` are toggled + All bits of rd` before instruction execution are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F010_S011_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + c.and rd', rs2' + x[8+rd'] = x[8+rd'] & x[8+rs2'] + Expands to and rd', rd', rs2'. +* **Verification Goals** + + Output result: + + All bits of rd` are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F010_S011_I002 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 012_C.OR + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + c.or rd', rs2' + x[8+rd'] = x[8+rd'] | x[8+rs2'] + Expands to or rd', rd', rs2'. +* **Verification Goals** + + Register operands: + + All possible rd` registers are used. +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F010_S012_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + c.or rd', rs2' + x[8+rd'] = x[8+rd'] | x[8+rs2'] + Expands to or rd', rd', rs2'. +* **Verification Goals** + + Input operands: + + Non-zero and zero values of rs2` are used + Non-zero and zero values of rd` are used + All bits of rs2` are toggled + All bits of rd` before instruction execution are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F010_S012_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + c.or rd', rs2' + x[8+rd'] = x[8+rd'] | x[8+rs2'] + Expands to or rd', rd', rs2'. +* **Verification Goals** + + Output result: + + All bits of rd` are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F010_S012_I002 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 013_C.XOR + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + c.xor rd', rs2' + x[8+rd'] = x[8+rd'] ^ x[8+rs2'] + Expands to xor rd', rd', rs2'. +* **Verification Goals** + + Register operands: + + All possible rd` registers are used. +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F010_S013_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + c.xor rd', rs2' + x[8+rd'] = x[8+rd'] ^ x[8+rs2'] + Expands to xor rd', rd', rs2'. +* **Verification Goals** + + Input operands: + + Non-zero and zero values of rs2` are used + Non-zero and zero values of rd` are used + All bits of rs2` are toggled + All bits of rd` before instruction execution are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F010_S013_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + c.xor rd', rs2' + x[8+rd'] = x[8+rd'] ^ x[8+rs2'] + Expands to xor rd', rd', rs2'. +* **Verification Goals** + + Output result: + + All bits of rd` are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F010_S013_I002 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 014_C.SUB + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + c.sub rd', rs2' + x[8+rd'] = x[8+rd'] - x[8+rs2'] + Expands to sub rd', rd', rs2'. Arithmetic underflow is ignored +* **Verification Goals** + + Register operands: + + All possible rd` registers are used. +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F010_S014_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + c.sub rd', rs2' + x[8+rd'] = x[8+rd'] - x[8+rs2'] + Expands to sub rd', rd', rs2'. Arithmetic underflow is ignored +* **Verification Goals** + + Input operands: + + +ve,-ve and zero values of rs2` are used + +ve, -ve, and zero values of rd` are used + All bits of rs2` are toggled + All bits of rd` before instruction execution are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F010_S014_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + c.sub rd', rs2' + x[8+rd'] = x[8+rd'] - x[8+rs2'] + Expands to sub rd', rd', rs2'. Arithmetic underflow is ignored +* **Verification Goals** + + Output result: + + All bits of rd` are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F010_S014_I002 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 015_C.EBREAK + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + c.ebreak + RaiseException(Breakpoint) + Expands to ebreak. +* **Verification Goals** + + Instruction executed +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F010_S015_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +## Feature: RV32C Control Transfer Instructions + +### Sub-feature: 000_C.J + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + c.j imm[11:1] + pc += sext(imm) + pc is calculated using signed arithmetic + Expands to jal x0, imm[11:1]. +* **Verification Goals** + + Input operands: + + uimm value is non-zero and zero + All bits of uimm are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F011_S000_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 001_C.JAL + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + c.jal imm[11:1] + x[1] = pc+2; pc += sext(imm) + pc is calculated using signed arithmetic. +* **Verification Goals** + + Input operands: + + uimm value is non-zero and zero + All bits of uimm are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F011_S001_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + c.jal imm[11:1] + x[1] = pc+2; pc += sext(imm) + pc is calculated using signed arithmetic. +* **Verification Goals** + + Output result: + + All bits of x1 are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F011_S001_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 002_C.JR + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + c.jr rs1 + pc = x[rs1] + Expands to jalr x0, 0(rs1). + Invalid when rs1=x0. +* **Verification Goals** + + Register operands: + + All possible rs1 registers are used. +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F011_S002_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + c.jr rs1 + pc = x[rs1] + Expands to jalr x0, 0(rs1). + Invalid when rs1=x0. +* **Verification Goals** + + Input operands: + + All bits of rs1 are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F011_S002_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 003_C.JALR + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + c.jalr rs1 + t = pc + 2; pc = x[rs1]; x[1] = t + Expands to jalr x1, 0(rs1). + Invalid when rs1=x0. +* **Verification Goals** + + Register operands: + + All possible rs1 registers are used. +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F011_S003_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + c.jalr rs1 + t = pc + 2; pc = x[rs1]; x[1] = t + Expands to jalr x1, 0(rs1). + Invalid when rs1=x0. +* **Verification Goals** + + Input operands: + + All bits of rs1 are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F011_S003_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + c.jalr rs1 + t = pc + 2; pc = x[rs1]; x[1] = t + Expands to jalr x1, 0(rs1). + Invalid when rs1=x0. +* **Verification Goals** + + Output result: + + All bits of x1 are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F011_S003_I002 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 004_C.BEQZ + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + c.beqz rs1', imm[8:1] + if (x[8+rs1'] == 0) pc += sext(imm) + Expands to beq rs1', x0, imm[8:1]. pc is calculated using signed arithmetic. +* **Verification Goals** + + Register operands: + + All possible rs1` registers are used. +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F011_S004_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + c.beqz rs1', imm[8:1] + if (x[8+rs1'] == 0) pc += sext(imm) + Expands to beq rs1', x0, imm[8:1]. pc is calculated using signed arithmetic. +* **Verification Goals** + + Input operands: + + All bits of rs1` are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F011_S004_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + c.beqz rs1', imm[8:1] + if (x[8+rs1'] == 0) pc += sext(imm) + Expands to beq rs1', x0, imm[8:1]. pc is calculated using signed arithmetic. +* **Verification Goals** + + Output result: + + Branch taken or not-taken +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F011_S004_I002 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 005_C.BNEZ + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + c.bnez rs1', imm[8:1] + if (x[8+rs1'] ≠ 0) pc += sext(imm) + Expands to bne rs1', x0, imm[8:1]. pc is calculated using signed arithmetic. +* **Verification Goals** + + Register operands: + + All possible rs1` registers are used. +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F011_S005_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + c.bnez rs1', imm[8:1] + if (x[8+rs1'] ≠ 0) pc += sext(imm) + Expands to bne rs1', x0, imm[8:1]. pc is calculated using signed arithmetic. +* **Verification Goals** + + Input operands: + + All bits of rs1 are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F011_S005_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + c.bnez rs1', imm[8:1] + if (x[8+rs1'] ≠ 0) pc += sext(imm) + Expands to bne rs1', x0, imm[8:1]. pc is calculated using signed arithmetic. +* **Verification Goals** + + Output result: + + Branch taken or not-taken +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F011_S005_I002 +* **Link to Coverage:** +* **Comments** + + *(none)* + +## Feature: RV32C Load and Store Instructions + +### Sub-feature: 000_C.LWSP + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + c.lwsp rd, uimm(x2) + x[rd] = sext(M[x[2] + uimm][0:31]) + Expands to lw rd, uimm[7:2](x2). + Invalid when rd=x0. + uimm treated as unsigned number +* **Verification Goals** + + Register operands: + + All possible rd registers are used. +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F012_S000_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + c.lwsp rd, uimm(x2) + x[rd] = sext(M[x[2] + uimm][0:31]) + Expands to lw rd, uimm[7:2](x2). + Invalid when rd=x0. + uimm treated as unsigned number +* **Verification Goals** + + Input operands: + + uimm value is non-zero and zero + All bits of uimm are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F012_S000_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + c.lwsp rd, uimm(x2) + x[rd] = sext(M[x[2] + uimm][0:31]) + Expands to lw rd, uimm[7:2](x2). + Invalid when rd=x0. + uimm treated as unsigned number +* **Verification Goals** + + Output result: + + rd value is non-zero and zero + All bits of rd are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F012_S000_I002 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 001_C.SWSP + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + c.swsp rs2, uimm(x2) + M[x[2] + uimm][0:31] = x[rs2] + Expands to sw rs2, uimm[7:2](x2). + uimm treated as unsigned number +* **Verification Goals** + + Register operands: + + All possible rs2 registers are used. +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F012_S001_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + c.swsp rs2, uimm(x2) + M[x[2] + uimm][0:31] = x[rs2] + Expands to sw rs2, uimm[7:2](x2). + uimm treated as unsigned number +* **Verification Goals** + + Input operands: + + uimm value is non-zero and zero + All bits of uimm are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F012_S001_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 002_C.LW + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + c.lw rd', uimm(rs1') + x[rd] = sext(M[x[rs1] + uimm][0:31]), where rd=8+rd' and rs1=8+rs1' + Expands to lw rd', uimm[6:2](rs1') +* **Verification Goals** + + Register operands: + + All possible rs1` registers are used. + All possible rd` registers are used. + All possible register combinations where rs1` == rd` are used +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F012_S002_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + c.lw rd', uimm(rs1') + x[rd] = sext(M[x[rs1] + uimm][0:31]), where rd=8+rd' and rs1=8+rs1' + Expands to lw rd', uimm[6:2](rs1') +* **Verification Goals** + + Input operands: + + uimm value is non-zero and zero + All bits of uimm are toggled + All bits of rs1` are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F012_S002_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + c.lw rd', uimm(rs1') + x[rd] = sext(M[x[rs1] + uimm][0:31]), where rd=8+rd' and rs1=8+rs1' + Expands to lw rd', uimm[6:2](rs1') +* **Verification Goals** + + Output result: + + rd` value is non-zero and zero + All bits of rd are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F012_S002_I002 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 003_C.SW + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + c.sw rs2', uimm(rs1') + M[x[rs1] + uimm][0:31] = x[rs2], where rs2=8+rs2' and rs1=8+rs1' + Expands to sw rs2', uimm[6:2](rs1'). +* **Verification Goals** + + Register operands: + + All possible rs1` registers are used. + All possible rd` registers are used. + All possible register combinations where rs1` == rd` are used +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F012_S003_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + c.sw rs2', uimm(rs1') + M[x[rs1] + uimm][0:31] = x[rs2], where rs2=8+rs2' and rs1=8+rs1' + Expands to sw rs2', uimm[6:2](rs1'). +* **Verification Goals** + + Input operands: + + uimm value is non-zero and zero + All bits of uimm are toggled + All bits of rs1` are toggled + All bits of rs2` are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F012_S003_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + +## Feature: RV32Zicsr Control and Status Register (CSR) Instructions + +### Sub-feature: 000_CSRRW + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + csrrw rd, rs1, csr + rd = Zext([csr]); csr = [rs1] +* **Verification Goals** + + Register operands: + + All possible rs1 registers are used + All possible rd registers are used + All supported CSRs are used + All possible register combinations where rs1 == rd are used +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F013_S000_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + csrrw rd, rs1, csr + rd = Zext([csr]); csr = [rs1] +* **Verification Goals** + + Input operand: + + Non-zero and zero rs1 operands are used (if rs1 != x0) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F013_S000_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 001_CSRRS + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + csrrs rd, rs1, csr + rd = Zext([csr]); csr = [rs1] | csr + Note that not all bits of csr will be writable. +* **Verification Goals** + + Register operands: + + All possible rs1 registers are used + All possible rd registers are used + All supported CSRs are used + All possible register combinations where rs1 == rd are used +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F013_S001_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + csrrs rd, rs1, csr + rd = Zext([csr]); csr = [rs1] | csr + Note that not all bits of csr will be writable. +* **Verification Goals** + + Input operand: + + Non-zero and zero rs1 operands are used (if rs1 != x0) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F013_S001_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 002_CSRRC + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + csrrs rd, rs1, csr + rd = Zext([csr]); csr = ~[rs1] | csr + Note that not all bits of csr will be writable. +* **Verification Goals** + + Register operands: + + All possible rs1 registers are used + All possible rd registers are used + All supported CSRs are used + All possible register combinations where rs1 == rd are used +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F013_S002_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + csrrs rd, rs1, csr + rd = Zext([csr]); csr = ~[rs1] | csr + Note that not all bits of csr will be writable. +* **Verification Goals** + + Input operand: + + Non-zero and zero rs1 operands are used (if rs1 != x0) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F013_S002_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 003_CSRRWI + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + csrrwi rd, imm[4:0], csr + rd = Zext([csr]); csr = Zext(imm[4:0]) + If rd == x0 then CSR is not read. +* **Verification Goals** + + Register operands: + + All possible rd registers are used + All supported CSRs are used +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F013_S003_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + csrrwi rd, imm[4:0], csr + rd = Zext([csr]); csr = Zext(imm[4:0]) + If rd == x0 then CSR is not read. +* **Verification Goals** + + Input operand: + + Non-zero and zero imm[4:0] operands are used + All bits of imm[4:0] are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F013_S003_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 004_CSRRSI + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + csrrsi rd, imm[4:0], csr + rd = Zext([csr]); csr = Zext(imm[4:0]) | csr + Note that not all bits of csr will be writable. +* **Verification Goals** + + Register operands: + + All possible rd registers are used + All supported CSRs are used +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F013_S004_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + csrrsi rd, imm[4:0], csr + rd = Zext([csr]); csr = Zext(imm[4:0]) | csr + Note that not all bits of csr will be writable. +* **Verification Goals** + + Input operand: + + Non-zero and zero imm[4:0] operands are used + All bits of imm[4:0] are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F013_S004_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 005_CSRRCI + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + csrrs rd, imm[4:0], csr + rd = Zext([csr]); csr = ~(Zext(imm[4:0])) | csr + Note that not all bits of csr will be writable. +* **Verification Goals** + + Register operands: + + All possible rd registers are used + All supported CSRs are used +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F013_S005_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + csrrs rd, imm[4:0], csr + rd = Zext([csr]); csr = ~(Zext(imm[4:0])) | csr + Note that not all bits of csr will be writable. +* **Verification Goals** + + Input operand: + + Non-zero and zero imm[4:0] operands are used + All bits of imm[4:0] are toggled +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F013_S005_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + +## Feature: RV32Zifencei Instruction-Fetch Fence + +### Sub-feature: 000_FENCE.I + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + Fence.I instruction executed + Implementation is core-specific +* **Verification Goals** + + Fence.I instruction is executed +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F014_S000_I000 +* **Link to Coverage:** isacov.rv32zifencei_fence_i_cg +* **Comments** + + *(none)* + +## Feature: Instruction execution sequences + +### Sub-feature: 000_Instruction Execution + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + All suported instructions for the core are executed +* **Verification Goals** + + Instruction is executed +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F015_S000_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + All suported instructions for the core are executed +* **Verification Goals** + + All back-to-back supported instruction sequences are executed +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F015_S000_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 001_Instruction Group Execution + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + All defined instruction groups for a core are executed +* **Verification Goals** + + For the core under test, all instruction groups are executed in the core +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F015_S001_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + All defined instruction groups are executed in sequence +* **Verification Goals** + + Depending on the length of the pipeline in the processor, sequence chains of 2,3,or 4 instruction groups are checked for execution +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F015_S001_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 002_GPR Hazard + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + An instruction reads from register that was written to in the previous instruction +* **Verification Goals** + + All instruction groups are tested across GPR hazards +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F015_S002_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 003_CSR Hazard + +#### Item: 000 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + CSR writes from the program are executed in conjunction with all instruction groups +* **Verification Goals** + + CSR write instruction attempts to write to a supported CSR + This does not include csr set or clear instructions where rs1 is x0 (bypassing the write) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F015_S003_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** ./RISCV_Instructions.rst +* **Feature Description** + + CSR writes from the program are executed in conjunction with all instruction groups +* **Verification Goals** + + Each instruction group is executed after each supported CSR is written with a Zicsri write instructio +* **Pass/Fail Criteria:** NDY (Not Defined Yet) +* **Test Type:** NDY (Not Defined Yet) +* **Coverage Method:** NDY (Not Defined Yet) +* **Applicable Cores:** CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_ISA_RV32_F015_S003_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + diff --git a/verif/docs/VerifPlans/source/dvplan_MMU_SV32.md b/verif/docs/VerifPlans/source/dvplan_MMU_SV32.md new file mode 100644 index 0000000000..55cd6efa67 --- /dev/null +++ b/verif/docs/VerifPlans/source/dvplan_MMU_SV32.md @@ -0,0 +1,600 @@ +# Module: MMU_SV32 + +## Feature: sv32 + +### Sub-feature: 000_PMP permissions on Physical Address + +#### Item: 000 + +* **Requirement location:** ISA Volume II: Privilege Architecture Version 20211203, Chapter 3.7, 5.3.2 +* **Feature Description** + + If PTE has valid and non-reserved RWX permissions, but the translated Physical address (pte.ppn of leaf PTE + offset) does not have (r,w,x) PMP permissions, then accessing the translated Physical address would raise access fault exception. + When satp.mode=sv32, and PTE has valid and non-reserved RWX permissions then test the following in supervisor and user privilege mode for level1 and level0 PTE. + + - Remove read PMP permission of translated Physical Address in pmpcfg and test the read acces. + - Remvoe write PMP permission of translated Physical Address in pmpcfg and test the write access. + - Remove execute PMP permission of translated Physical Address in pmpcfg and test the execute access. +* **Verification Goals** + + Access fault exception should be raised according to {x,r,w} access type. Check that: + - m/scause must contain the exception number of: + - instruction access fault for execute access. + - load page access for read access. + - store/AMO access fault for write access. + - m/sepc must contain the virtual address of the instruction at which the trap occurs. +* **Pass/Fail Criteria:** Check RM +* **Test Type:** RISC-V Arch-test +* **Coverage Method:** Testcase +* **Applicable Cores:** CV32A6_v0.1.0 +* **Unique verification tag:** VP_MMU_SV32_F000_S000_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 001_PMP permissions on PTE + +#### Item: 000 + +* **Requirement location:** ISA Volume II: Privilege Architecture Version 20211203, Chapter 3.7, 5.3.2 +* **Feature Description** + + If PTE does not have (r,w,x) PMP permissions, then accessing it would raise access fault exception of the corresponding access type. + When satp.mode=sv32, then test the following in supervisor and user privilege mode for level0 and level1 PTE. + - Remove read PMP permission of PTE address in pmpcfg and test the read acces. + - Remvoe write PMP permission of PTE address in pmpcfg and test the write access. + - Remove execute PMP permission of PTE address in pmpcfg and test the execute access. +* **Verification Goals** + + Access fault exception should be raised according to {x,r,w} access type. Check that: + - m/scause must contain the exception number of: + - instruction access fault for execute access. + - load page access for read access. + - store/AMO access fault for write access. + - m/sepc must contain the virtual address of the instruction at which the trap occurs. +* **Pass/Fail Criteria:** NDY (Not Defined Yet) +* **Test Type:** NDY (Not Defined Yet) +* **Coverage Method:** NDY (Not Defined Yet) +* **Applicable Cores:** CV32A6_v0.1.0 +* **Unique verification tag:** VP_MMU_SV32_F000_S001_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 002_In-Valid Permission of PTE + +#### Item: 000 + +* **Requirement location:** ISA Volume II: Privilege Architecture Version 20211203, Chpter 5.3.2 +* **Feature Description** + + If PTE does not have Valid (pte.V=0) permission, then accessing it would raise page fault exception of the corresponding access type. + When satp.mode=sv32 and PTE has (r,w,x) PMP permissions, then test the following in supervisor and user privilege mode for level0 and level1 PTE. + - Set PTE.V = 0 and test the read acces. + - Set PTE.V = 0 and test the write access. + - Set PTE.V = 0 and test the execute access. + + * For testing at level0, set all the pte perimssions at level1 to 0 except pte.v, so that level1 points to level0. + * Set pte.U=0 when test in Supervisor mode and Set pte.U=1 when testing in user mode +* **Verification Goals** + + Page fault exception should be raised according to {x,r,w} access type. Check that: + - m/scause must contain the exception number of: + - instruction page fault for execute access. + - load page fault for read access. + - store/AMO page fault for write access. + - m/sepc must contain the virtual address of the instruction at which the trap occurs. +* **Pass/Fail Criteria:** Check RM +* **Test Type:** RISC-V Arch-test +* **Coverage Method:** Testcase +* **Applicable Cores:** CV32A6_v0.1.0 +* **Unique verification tag:** VP_MMU_SV32_F000_S002_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 003_Reserved RWX permission encodings of PTE + +#### Item: 000 + +* **Requirement location:** ISA Volume II: Privilege Architecture Version 20211203, Chapter 3.7, 5.3.1 +* **Feature Description** + + If PTE has reserved RWX encodings (pte.w=1 & pte.r=0), then accessing it would raise page fault exception of the corresponding access type. + When satp.mode=sv32, PTE has (r,w,x) PMP permissions, and pte.v=1, then test the following in supervisor and user privilege mode for level0 and level1 PTE. + - Set pte.w=1 & pte.r=0 and test the read acces. + - Set pte.w=1 & pte.r=0 and test the write access. + - Set pte.w=1 & pte.r=0 and test the execute access. + + * For testing at level0, set all the pte perimssions at level1 to 0 except pte.v, so that level1 points to level0. + * Set pte.U=0 when test in Supervisor mode and Set pte.U=1 when testing in user mode +* **Verification Goals** + + Page fault exception should be raised according to {x,r,w} access type. Check that: + - m/scause must contain the exception number of: + - instruction page fault for execute access. + - load page fault for read access. + - store/AMO page fault for write access. + - m/sepc must contain the virtual address of the instruction at which the trap occurs. +* **Pass/Fail Criteria:** Check RM +* **Test Type:** RISC-V Arch-test +* **Coverage Method:** Testcase +* **Applicable Cores:** CV32A6_v0.1.0 +* **Unique verification tag:** VP_MMU_SV32_F000_S003_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 004_Non-leaf PTE permission at level 0 + +#### Item: 000 + +* **Requirement location:** ISA Volume II: Privilege Architecture Version 20211203, Chapter 5.3.2 +* **Feature Description** + + If PTE at level0 has non-leaf RWX permissions (pte.x=0 & pte.r=0), then accessing it would raise page fault exception of the corresponding access type. + When satp.mode=sv32, PTE has (r,w,x) PMP permissions, and pte.v=1, then test the following in supervisor and user privilege mode for level0 PTE. + - Set pte.x=0 & pte.r=0 & pte.w=0 and test the read acces. + - Set pte.x=0 & pte.r=0 & pte.w=0 and test the write access. + - Set pte.x=0 & pte.r=0 & pte.w=0 and test the execute access. + + * For testing at level0, set all the pte perimssions at level1 to 0 except pte.v, so that level1 points to level0. + * Set pte.U=0 when test in Supervisor mode and Set pte.U=1 when testing in user mode +* **Verification Goals** + + Page fault exception should be raised according to {x,r,w} access type. Check that: + - m/scause must contain the exception number of: + - instruction page fault for execute access. + - load page fault for read access. + - store/AMO page fault for write access. + - m/sepc must contain the virtual address of the instruction at which the trap occurs. +* **Pass/Fail Criteria:** Check RM +* **Test Type:** RISC-V Arch-test +* **Coverage Method:** Testcase +* **Applicable Cores:** CV32A6_v0.1.0 +* **Unique verification tag:** VP_MMU_SV32_F000_S004_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 005_RWX access on S-mode pages in S-mode + +#### Item: 000 + +* **Requirement location:** ISA Volume II: Privilege Architecture Version 20211203, Chapter 5.3.1 +* **Feature Description** + + If PTE belongs to supervisor mode i.e. its U permission bit is clear (pte.u = 0), then accessing that PTE in supervisor mode should be successful if the corresponding (r,w,x) permission of PTE is granted. Otherwise raise page fault exception of the corresponding access type. + When satp.mode=sv32, PTE has (r,w,x) PMP permissions, PTE has non-reserved RWX encoding, pte.u=0 and pte.v=1, then test the following in supervisor privilege mode for level 0 and level 1 PTE. + - Test the read access for both pte.r=1 and for pte.r=0 + - Test the write access for both pte.w=1 and for pte.w=0 + - Test the execute access for both pte.x=1 and for pte.x=0 + + * For testing at level0, set all the pte perimssions at level1 to 0 except pte.v, so that level1 points to level0. +* **Verification Goals** + + RWX access should be successful if the corresponding permissions are granted in the PTE. Check that load, store and execute works without any page fault. + Page fault exception should be raised according to (x,r,w) access type if the corresponding (r,w,x) permissions are not granted in the PTE. Check that: + - m/scause must contain the exception number of: + - instruction page fault for execute. + - load page fault for read access. + - store/AMO page fault for write access. + - m/sepc must contain the virtual address of the instruction at which the trap occurs. +* **Pass/Fail Criteria:** Check RM +* **Test Type:** RISC-V Arch-test +* **Coverage Method:** Testcase +* **Applicable Cores:** CV32A6_v0.1.0 +* **Unique verification tag:** VP_MMU_SV32_F000_S005_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 006_RWX access on S-mode pages in U-mode + +#### Item: 000 + +* **Requirement location:** ISA Volume II: Privilege Architecture Version 20211203, Chapter 5.3.2 +* **Feature Description** + + If PTE belongs to supervisor mode i.e. its U permission bit is clear (pte.u = 0), then accessing that PTE in user mode would raise page fault exception of the corresponding access type. + When satp.mode=sv32, PTE has (r,w,x) PMP permissions, PTE has non-reserved RWX encoding, and pte.v=1, then test the following user privilege mode for level0 and level1 PTE. + - Set pte.u=0 and test the read acces. + - Set pte.u=0 and test the write access. + - Set pte.u=0 and test the execute access. + + * For testing at level0, set all the pte perimssions at level1 to 0 except pte.v, so that level1 points to level0. +* **Verification Goals** + + Page fault exception should be raised according to {x,r,w} access type. Check that: + - m/scause must contain the exception number of instruction, load, and store/AMO page fault for execute, read and write access type, respectively. + - m/sepc must contain the virtual address of the instruction at which the trap occurs. +* **Pass/Fail Criteria:** Check RM +* **Test Type:** RISC-V Arch-test +* **Coverage Method:** Testcase +* **Applicable Cores:** CV32A6_v0.1.0 +* **Unique verification tag:** VP_MMU_SV32_F000_S006_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 007_RWX access on U-mode pages in S-mode with mstatus.SUM unset + +#### Item: 000 + +* **Requirement location:** ISA Volume II: Privilege Architecture Version 20211203, Chapter 3.1.6.3, 5.3.2 +* **Feature Description** + + If PTE belongs to user mode i.e. its U permission bit is set (pte.u = 1) and m/sstatus.SUM = 0, then accessing that PTE in supervisor mode would raise page fault exception of the corresponding access type. + When satp.mode=sv32, PTE has (r,w,x) PMP permissions, PTE has non-reserved RWX encoding, and pte.v=1, then test the following in supervisor mode for level 0 and level 1 PTE. + - Set pte.u=1 & s/mstatus.SUM = 0 and test the read acces. + - Set pte.u=1 & s/mstatus.SUM = 0 and test the write access. + - Set pte.u=1 & s/mstatus.SUM = 0 and test the execute access. + + * For testing at level0, set all the pte perimssions at level1 to 0 except pte.v, so that level1 points to level0. +* **Verification Goals** + + Page fault exception should be raised according to {x,r,w} access type. Check that: + - m/scause must contain the exception number of: + - instruction page fault for execute access. + - load page fault for read access. + - store/AMO page fault for write access. + - m/sepc must contain the virtual address of the instruction at which the trap occurs. +* **Pass/Fail Criteria:** Check RM +* **Test Type:** RISC-V Arch-test +* **Coverage Method:** Testcase +* **Applicable Cores:** CV32A6_v0.1.0 +* **Unique verification tag:** VP_MMU_SV32_F000_S007_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 008_RWX access on U-mode pages in S-mode with mstatus.SUM set + +#### Item: 000 + +* **Requirement location:** ISA Volume II: Privilege Architecture Version 20211203, Chapter 3.1.6.3, 5.3.2 +* **Feature Description** + + If PTE belongs to user mode i.e. its U permission bit is set (pte.u = 1) and m/sstatus.SUM = 1, then RW access to that PTE in supervisor mode would be successful but eXecute access would raise instruction page fault exception in s-mode. + When satp.mode=sv32, PTE has (r,w,x) PMP permissions, PTE has non-reserved RWX encoding, and pte.v=1, then test the following in supervisor mode for level0 and level1 PTE. + - Set pte.r=1 & pte.u=1 & s/mstatus.SUM = 1 and test the read acces. + - Set pte.w=1 & pte.u=1 & s/mstatus.SUM = 1 and test the write access. + - Set pte.x=1 & pte.u=1 & s/mstatus.SUM = 1 and test the execute access. + + * For testing at level0, set all the pte perimssions at level1 to 0 except pte.v, so that level1 points to level0. +* **Verification Goals** + + Read and Write access to the PTE should be successful. So, check that the load and store works without page fault and expected data is stored to and loaded from the memory, repectively. + + Execute access should raise instruction page fault. Check that: + - m/scause must contain the exception number of instruction instruction access fault. + - m/sepc must contain the virtual address of the instruction at which the trap occurs. +* **Pass/Fail Criteria:** Check RM +* **Test Type:** RISC-V Arch-test +* **Coverage Method:** Testcase +* **Applicable Cores:** CV32A6_v0.1.0 +* **Unique verification tag:** VP_MMU_SV32_F000_S008_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 009_RWX access on U-mode pages in U-mode + +#### Item: 000 + +* **Requirement location:** ISA Volume II: Privilege Architecture Version 20211203, Chapter 5.3.2 +* **Feature Description** + + If PTE belongs to user mode i.e. its U permission bit is set (pte.u = 1), then accessing that PTE in user mode should be successful if the corresponding (r,w,x) permission of PTE is granted. Otherwise raise page fault exception of the corresponding access type. + When satp.mode=sv32, PTE has (r,w,x) PMP permissions, PTE has non-reserved RWX encoding, pte.u=1 and pte.v=1, then test the following in user privilege mode for level0 and level1 PTE. + - Test the read access for both pte.r=1 and for pte.r=0 + - Test the write access for both pte.w=1 and for pte.w=0 + - Test the execute access for both pte.x=1 and for pte.x=0 + + * For testing at level0, set all the pte perimssions at level1 to 0 except pte.v, so that level1 points to level0. +* **Verification Goals** + + RWX access should be successful if the corresponding permissions are granted in the PTE. Check that load, store and execute works without any page fault. + + Page fault exception should be raised if the corresponding rwx PTE permissions are not granted. Check that: + - m/scause must contain the exception number of: + - instruction page fault for execute access. + - load page fault for read access. + - store/AMO page fault for write access. + - m/sepc must contain the virtual address of the instruction at which the trap occurs. +* **Pass/Fail Criteria:** Check RM +* **Test Type:** RISC-V Arch-test +* **Coverage Method:** Testcase +* **Applicable Cores:** CV32A6_v0.1.0 +* **Unique verification tag:** VP_MMU_SV32_F000_S009_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 010_Make Executable Page Readable with s/mstatus.MXR unset + +#### Item: 000 + +* **Requirement location:** ISA Volume II: Privilege Architecture Version 20211203, Chapter 3.1.6.3, 5.3.2 +* **Feature Description** + + If PTE has only execute permission (pte.x = 1) and s/mstatus.MXR=0, then read access on that PTE should raise load page fault exception. + When satp.mode=sv32, PTE has (r,w,x) PMP permissions, and pte.v=1, then test the following in supervisor and user privilege mode for level0 and level1 PTE. + - Set pte.r=0 & pte.w=0 & pte.x=1 & s/mstatus.MXR=0 and test the read acces. + + * For testing at level0, set all the pte perimssions at level1 to 0 except pte.v, so that level1 points to level0. + * Set pte.U=0 when test in Supervisor mode and Set pte.U=1 when testing in user mode +* **Verification Goals** + + Load Page fault exception should be raised. Check that: + - m/scause must contain the exception number of load page fault for read access. + - m/sepc must contain the virtual address of the instruction at which the trap occurs. +* **Pass/Fail Criteria:** Signature +* **Test Type:** RISC-V Arch-test +* **Coverage Method:** Testcase +* **Applicable Cores:** CV32A6_v0.1.0 +* **Unique verification tag:** VP_MMU_SV32_F000_S010_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 011_Make Executable Page Readable with s/mstatus.MXR set + +#### Item: 000 + +* **Requirement location:** ISA Volume II: Privilege Architecture Version 20211203, Chapter 3.1.6.3 ,5.3.2 +* **Feature Description** + + If PTE has only execute permission (pte.x = 1) and s/mstatus.MXR=1, then read access on that PTE should be successful without having explicit read permission (pte.r=0). + When satp.mode=sv32, PTE has (r,w,x) PMP permissions, and pte.v=1, then test the following in supervisor and user privilege mode for level0 and level1 PTE. + - Set pte.r=0 & pte.w=0 & pte.x=1 & s/mstatus.MXR=1 and test the read acces. + + * For testing at level0, set all the pte perimssions at level1 to 0 except pte.v, so that level1 points to level0. + * Set pte.U=0 when test in Supervisor mode and Set pte.U=1 when testing in user mode +* **Verification Goals** + + Read access to the PTE should be successful. Check that load instructions works without any load page fault exception and expected data is loaded from the memory. +* **Pass/Fail Criteria:** Check RM +* **Test Type:** RISC-V Arch-test +* **Coverage Method:** Testcase +* **Applicable Cores:** CV32A6_v0.1.0 +* **Unique verification tag:** VP_MMU_SV32_F000_S011_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 012_Global mapping + +#### Item: 000 + +* **Requirement location:** ISA Volume II: Privilege Architecture Version 20211203, Chapter 5.3.1 +* **Feature Description** + + For two different processes having same Virtual address and different satp.ASID, maps to same Physical address, and the pte.G is set; then one process will go through the address translation and update the TLB while the 2nd process will not go through the translation if pte.G is set and Physical address exist in TLB. +* **Verification Goals** + + Show that two different processes having same VA to PA mapping can access the translated PA from TLB (if exist) and not go through complete translation. +* **Pass/Fail Criteria:** Check RM +* **Test Type:** RISC-V Arch-test +* **Coverage Method:** Testcase +* **Applicable Cores:** CV32A6_v0.1.0 +* **Unique verification tag:** VP_MMU_SV32_F000_S012_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 013_Access bit implementation + +#### Item: 000 + +* **Requirement location:** ISA Volume II: Privilege Architecture Version 20211203, Chapter 5.3.1, 5.3.2 +* **Feature Description** + + If implementation does not sets the pte.A on accessing the PTE, and PTE has pte.A=0, then accessing it would raise page fault exception of the corresponding access type. + When satp.mode=sv32, PTE has (r,w,x) PMP permissions, and pte.v=1, then test the following in supervisor and user privilege mode for level0 and level1 PTE. Execute sfence.vma before accessign the PTE. + - Set pte.r=1 & pte.a=0 and test the read acces. + - Set pte.w=1 & pte.a=0 and test the write access. + - Set pte.x=1 & pte.a=0 and test the execute access. + + * For testing at level0, set all the pte perimssions at level1 to 0 except pte.v, so that level1 points to level0. + * Set pte.U=0 when test in Supervisor mode and Set pte.U=1 when testing in user mode. +* **Verification Goals** + + Page fault exception should be raised according to {x,r,w} access type. Check that: + - m/scause must contain the exception number of: + - instruction page fault for execute access. + - load page fault for read access. + - store/AMO page fault for write access. + - m/sepc must contain the virtual address of the instruction at which the trap occurs. +* **Pass/Fail Criteria:** Check RM +* **Test Type:** RISC-V Arch-test +* **Coverage Method:** Testcase +* **Applicable Cores:** CV32A6_v0.1.0 +* **Unique verification tag:** VP_MMU_SV32_F000_S013_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 014_Dirty bit Implementation + +#### Item: 000 + +* **Requirement location:** ISA Volume II: Privilege Architecture Version 20211203, Chapter 5.3.1, 5.3.2 +* **Feature Description** + + If implementation does not sets the pte.D when PTE is written, and PTE has pte.D=0, then attempting to store on that PTE would raise Store/AMO page fault exception. + When satp.mode=sv32, PTE has (r,w,x) PMP permissions, pte.a=1 and pte.v=1, then test the following in supervisor and user privilege mode for level0 and level1 PTE. Execute sfence.vma before accessign the PTE. + - Set pte.w=1 & pte.d=0 and test the write access. + + * For testing at level0, set all the pte perimssions at level1 to 0 except pte.v, so that level1 points to level0. + * Set pte.U=0 when test in Supervisor mode and Set pte.U=1 when testing in user mode. +* **Verification Goals** + + Store/AMO page fault exception should be raised. Check that: + - m/scause must contain the exception number of store/AMO page fault for write access. + - m/sepc must contain the virtual address of the instruction at which the trap occurs. +* **Pass/Fail Criteria:** Check RM +* **Test Type:** RISC-V Arch-test +* **Coverage Method:** Testcase +* **Applicable Cores:** CV32A6_v0.1.0 +* **Unique verification tag:** VP_MMU_SV32_F000_S014_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 015_Misaligned Superpage + +#### Item: 000 + +* **Requirement location:** ISA Volume II: Privilege Architecture Version 20211203, Chapter 5.3.1, 5.3.2 +* **Feature Description** + + If PTE at level1 is leaf PTE (superpage) and its pte.ppn[0]=0, then it is a misaligned superpage and accessing that PTE would raise page fault exception of the corresponding access type. + When satp.mode=sv32, PTE has (r,w,x) PMP permissions, PTE has non-reserved RWX encodings, (pte.r | pte.x)=1, and pte.v=1, then test the following in supervisor and user privilege mode for level1 PTE. + -set pte.ppn[0]=0 and test for read, write and execute access. + + * Set pte.U=0 when test in Supervisor mode and Set pte.U=1 when testing in user mode. +* **Verification Goals** + + Page fault exception should be raised according to {x,r,w} access type. Check that: + - m/scause must contain the exception number of: + - instruction page fault for execute access. + - load page fault for read access. + - store/AMO page fault for write access. + - m/sepc must contain the virtual address of the instruction at which the trap occurs. +* **Pass/Fail Criteria:** Check RM +* **Test Type:** RISC-V Arch-test +* **Coverage Method:** Testcase +* **Applicable Cores:** CV32A6_v0.1.0 +* **Unique verification tag:** VP_MMU_SV32_F000_S015_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +## Feature: mstatus.TVM + +### Sub-feature: 000_Accessing satp and sfence.vma CSRs + +#### Item: 000 + +* **Requirement location:** ISA Volume II: Privilege Architecture Version 20211203, Chapter 3.1.6.5 +* **Feature Description** + + If mstatus.TVM=1, read and write access to the satp and sfence.vma will raise illegal instruction exception in S-mode. +* **Verification Goals** + + Show that: + - s/mcause contains the exception number of illegal instruction exception. + - m/sepc must contain the virtual address of the instruction at which the trap occurs. +* **Pass/Fail Criteria:** Check RM +* **Test Type:** RISC-V Arch-test +* **Coverage Method:** Testcase +* **Applicable Cores:** CV32A6_v0.1.0 +* **Unique verification tag:** VP_MMU_SV32_F001_S000_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +## Feature: satp + +### Sub-feature: 000_access permission + +#### Item: 000 + +* **Requirement location:** ISA Volume II: Privilege Architecture Version 20211203, Chapter 5.1.11 +* **Feature Description** + + Access satp in M, S, and U mode using csrrw, csrrc, csrrs +* **Verification Goals** + + Show that satp is only accessible in M and S mode and illegal instruction exception is generated when accessed in lower privilege mode +* **Pass/Fail Criteria:** Check RM +* **Test Type:** RISC-V Arch-test +* **Coverage Method:** Testcase +* **Applicable Cores:** CV32A6_v0.1.0 +* **Unique verification tag:** VP_MMU_SV32_F002_S000_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 001_MODE field + +#### Item: 000 + +* **Requirement location:** ISA Volume II: Privilege Architecture Version 20211203, Chapter 5.1.11 +* **Feature Description** + + Allows to select different schemes of address translation. Writes to satp are ignored when unsupported mode is selected. +* **Verification Goals** + + Show that supported address translation scheme i.e sv32 is selected by writing satp.mode=sv32 and reading back the satp +* **Pass/Fail Criteria:** Check RM +* **Test Type:** RISC-V Arch-test +* **Coverage Method:** Testcase +* **Applicable Cores:** CV32A6_v0.1.0 +* **Unique verification tag:** VP_MMU_SV32_F002_S001_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 002_MODE=Bare + +#### Item: 000 + +* **Requirement location:** ISA Volume II: Privilege Architecture Version 20211203, Chapter 5.1.11 +* **Feature Description** + + Selecting MODE=Bare the remaining feild should be zero. Other encoding for remaining feild in satp is reserved +* **Verification Goals** + + Show wirting {zero, non-zero} value to satp when mode=bare the behaviour follows the design implemention +* **Pass/Fail Criteria:** Check RM +* **Test Type:** RISC-V Arch-test +* **Coverage Method:** Testcase +* **Applicable Cores:** CV32A6_v0.1.0 +* **Unique verification tag:** VP_MMU_SV32_F002_S002_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 003_ASIDLEN + +#### Item: 000 + +* **Requirement location:** ISA Volume II: Privilege Architecture Version 20211203, Chapter 5.1.11 +* **Feature Description** + + ASIDLEN is the number of ASID bits implemented. MAXASID bits for sv32 is 9 +* **Verification Goals** + + Determine by writing one to every bit position in the ASID field, then reading back the value in satp to see which bit positions in the ASID field hold a one. Show that ASIDLEN is equal to the expected ASIDLEN +* **Pass/Fail Criteria:** Check RM +* **Test Type:** RISC-V Arch-test +* **Coverage Method:** Testcase +* **Applicable Cores:** CV32A6_v0.1.0 +* **Unique verification tag:** VP_MMU_SV32_F002_S003_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + diff --git a/verif/docs/VerifPlans/source/dvplan_csr-access.md b/verif/docs/VerifPlans/source/dvplan_csr-access.md new file mode 100644 index 0000000000..3db4f93f73 --- /dev/null +++ b/verif/docs/VerifPlans/source/dvplan_csr-access.md @@ -0,0 +1,69 @@ +# Module: CSR ACCESS VERIFICATION + +## Feature: machineScratch(MSCRATCH) + +### Sub-feature: 000_MSCRATCH + +#### Item: 000 + +* **Requirement location:** riscv-privileged-20211203 +* **Feature Description** + + To verify the Power-on Reset value for MSCRATCH CSR. + + Address Offset : 0x340 + Width (bits) : 32 + Access Type : RW + Reset Value : 0x00000000 + priviliged mode : Machine +* **Verification Goals** + + Read MSCRATCH CSR to check default POR value that should be equal to 0x00000000. +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Directed SelfChk +* **Coverage Method:** N/A +* **Applicable Cores:** CV32A6_v0.1.0 +* **Unique verification tag:** VP_csr-test-ident_F000_S000_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 001 + +* **Requirement location:** riscv-privileged-20211203 +* **Feature Description** + + Verifying R/W access of a MSCRATCH CSR by writing random valid data like 0xFFFFFFFF, 0XA5A5A5A5, 0X5A5A5A5A ... and Read back CSR values to check correctness. +* **Verification Goals** + + The read values of MSCRATCH CSR should matches with written random data values. +* **Pass/Fail Criteria:** NDY (Not Defined Yet) +* **Test Type:** NDY (Not Defined Yet) +* **Coverage Method:** NDY (Not Defined Yet) +* **Applicable Cores:** CV32A6_v0.1.0 +* **Unique verification tag:** VP_csr-test-ident_F000_S000_I001 +* **Link to Coverage:** +* **Comments** + + *(none)* + +#### Item: 002 + +* **Requirement location:** +* **Feature Description** + + Verifying MSCRATCH CSR in other privilige modes(supervisor, user) +* **Verification Goals** + + It is expected that accessing Machine Mode CSRs in lower privilige modes will raise an exception. +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Directed SelfChk +* **Coverage Method:** N/A +* **Applicable Cores:** CV32A6_v0.1.0 +* **Unique verification tag:** VP_csr-test-ident_F000_S000_I002 +* **Link to Coverage:** +* **Comments** + + *(none)* + diff --git a/verif/docs/VerifPlans/source/dvplan_intro.rst b/verif/docs/VerifPlans/source/dvplan_intro.rst new file mode 100644 index 0000000000..8c99d086a7 --- /dev/null +++ b/verif/docs/VerifPlans/source/dvplan_intro.rst @@ -0,0 +1,77 @@ + +.. + Copyright 2022 Thales DIS design services SAS + Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 + You may obtain a copy of the License at https://solderpad.org/licenses/ + + Original Author: Jean-Roch COULON - Thales + +.. _DVPLAN_INTRO: + +Introduction +============= + +The objective of this document is to describe what must be covered to verify CVA6 RISC-V processor. + + +License +------- + +| Copyright 2022 Thales +| SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +| Licensed under the Solderpad Hardware License v 2.1 (the “License”); + you may not use this file except in compliance with the License, or, + at your option, the Apache License version 2.0. You may obtain a copy + of the License at https://solderpad.org/licenses/SHL-2.1/. +| Unless required by applicable law or agreed to in writing, any work + distributed under the License is distributed on an “AS IS” BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + +Standards Compliance +-------------------- + +To ease the reading, the reference to these specifications can be implicit in the requirements below. For the sake of precision, the requirements identify the versions of RISC-V extensions from these specifications. + +* **[CVA6req]** “CVA6 requirement specification”, https://github.com/openhwgroup/cva6/blob/master/docs/specifications/cva6_requirement_specification.rst, HASH#767c465. +* **[CVA6design]** “CVA6 design document”, TO BE COMPLETED +* **[RVunpriv]** “The RISC-V Instruction Set Manual, Volume I: User-Level ISA, Document Version 20191213”, Editors Andrew Waterman and Krste Asanović, RISC-V Foundation, December 13, 2019. +* **[RVpriv]** “The RISC-V Instruction Set Manual, Volume II: Privileged Architecture, Document Version 20211203”, Editors Andrew Waterman, Krste Asanović and John Hauser, RISC-V Foundation, December 4, 2021. +* **[RVdbg]** “RISC-V External Debug Support, Document Version 0.13.2”, Editors Tim Newsome and Megan Wachs, RISC-V Foundation, March 22, 2019. +* **[RVcompat]** “RISC-V Architectural Compatibility Test Framework”, https://github.com/riscv-non-isa/riscv-arch-test. +* **[AXI]** AXI Specification, https://developer.arm.com/documentation/ihi0022/hc. +* **[CV-X-IF]** Placeholder for the CV-X-IF coprocessor interface currently prepared at OpenHW Group; current version in https://docs.openhwgroup.org/projects/openhw-group-core-v-xif/. +* **[OpenPiton]** “OpenPiton Microarchitecture Specification”, Princeton University, https://parallel.princeton.edu/openpiton/docs/micro_arch.pdf. + +CV32A6 is a 32-bit processor fully compliant with RISC-V specifications: [RVunpriv], [RVpriv] and [RVdbg] and passes [RVcompat] compatibility tests, as requested by [GEN-10] in [CVA6req]. + + +Getting start verification +-------------------------- + +[TO BE COMPLETED] + + +Documentation framework +----------------------- + +The framework of this document is aligned with the CVA6 design document [CVA6design]. + +Description of the framework: + +* Processor is a subsystem +* Processor subsystems are split into several modules +* Modules are verified separately + + +Contributors +------------ + +| Jean-Roch Coulon - Thales + +[TO BE COMPLETED] + diff --git a/verif/docs/VerifPlans/source/index.rst b/verif/docs/VerifPlans/source/index.rst new file mode 100644 index 0000000000..3515ac8ff0 --- /dev/null +++ b/verif/docs/VerifPlans/source/index.rst @@ -0,0 +1,32 @@ +.. + Copyright (c) 2022 Thales + + Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + https://solderpad.org/licenses/ + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + + SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 + +CV32A6-step1 Design Verification Plan +===================================== + +.. toctree:: + :maxdepth: 3 + :caption: Contents: + + dvplan_intro + dvplan_FRONTEND + dvplan_ISA_RV32 + dvplan_CVXIF + dvplan_AXI + dvplan_FENCEI + dvplan_csr-access + diff --git a/verif/docs/VerifPlans/vp_config.py b/verif/docs/VerifPlans/vp_config.py new file mode 100644 index 0000000000..3cfd9556e9 --- /dev/null +++ b/verif/docs/VerifPlans/vp_config.py @@ -0,0 +1,40 @@ +############################################################################# +# Copyright (C) 2022 Thales DIS France SAS +# +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0. +# +# Original Author: Zbigniew Chamski (zbigniew.chamski@thalesgroup.com) +############################################################################# + +import re, os, glob, sys +import subprocess + +##################################### +# Default initialization +VP_PLATFORM_TOP_DIR = "" + +## Want to load/save db in/from a unique file (False), or with split files, one per Feature(True) +SPLIT_SAVE = True + +########################################################################## +########################################################################## +##### PROJECT SETUP + +##################################### +##### Paths are relative to the value of env variable PLATFORM_TOP_DIR +if "PLATFORM_TOP_DIR" in os.environ: ## Env Variable existence Check + VP_PLATFORM_TOP_DIR = os.environ["PLATFORM_TOP_DIR"] + # Name of the project (can be empty if the variable is not defined in environment.) + PROJECT_NAME = os.environ["PROJECT_NAME"] + # Location of database files + SAVED_DB_LOCATION = os.path.join(VP_PLATFORM_TOP_DIR, "*.pck") + # Location of the Pickle file containing the current IP/Feature lock info. + LOCKED_IP_LOCATION = os.path.join(VP_PLATFORM_TOP_DIR, "locked_ip.pick") +else: + print("--- Error: Please define PLATFORM_TOP_DIR env variable") + sys.exit() + +# Globally accessible YAML config +def init_yaml_config(config): + global yaml_config + yaml_config = config diff --git a/verif/docs/coverage_status/isacov_status.rst b/verif/docs/coverage_status/isacov_status.rst new file mode 100644 index 0000000000..014b8ab07d --- /dev/null +++ b/verif/docs/coverage_status/isacov_status.rst @@ -0,0 +1,192 @@ +**ISACOV MISSING COVERAGE** +=============================== + +The table blow resume what’s missing in ISACOV agent fucntionnal coverage : + ++----------------------+------------------------------------+----------------------------------------+ +| **Cover group - | **Missing bins/cover point** | **Why ?** | +| Instance** | | | ++======================+====================================+========================================+ +| cg_executed_type | - rv32c_ebreak_cg.cp_executed | - RVFI limitation\* | +| | | | +| - rv32c_ebreak_cg | - rv32i_dret_cg.cp_executed | | +| | | | +| - rv32i_dret_cg | - rv32i_ebreak_cg.cp_executed | | +| | | | +| - rv32i_ebreak_cg | - rv32i_ecall_cg.cp_executed | | +| | | | +| - rv32i_ecall_cg | - rv32i_wfi_cg.cp_executed | | +| | | | +| - rv32i_wfi_cg | | | ++----------------------+------------------------------------+----------------------------------------+ +| cg_sequential | - cp_instr, cp_instr_prev_x2 | - RVFI limitation\* | +| | | | +| | - cp_group, cp_group_pipe_x2 | - RVFI limitation\* | +| | | | +| | - cp_csr | - RVFI limitation\* | +| | | | +| | - cross_seq_instr_x2 | - RVFI limitation\* | +| | | | +| | - cross_seq_group_x2 | - RVFI limitation\* | +| | | | +| | - cross_seq_gpr_raw_hazard | - RVFI limitation\* | +| | | | +| | - cross_seq_csr_hazard_x2 | - RVFI limitation\* | +| | | | ++----------------------+------------------------------------+----------------------------------------+ +| cg_csritype | - \*.cp_csr | - Need CSR tests*\* | +| | | | +| - | | | +| rv32zicsr_csrrwi_cg | | | +| | | | +| - | | | +| rv32zicsr_csrrsi_cg | | | +| | | | +| - | | | +| rv32zicsr_csrrci_cg | | | ++----------------------+------------------------------------+----------------------------------------+ +| cg_cr_j | - rv32c_jalr_cg.cp_rs1_value | - boot_addr != 0x0 | +| | | | +| - rv32c_jalr_cg | - rv32c_jr_cg.cp_rs1_value | - boot_addr != 0x0 | +| | | | +| - rv32c_jr_cg | - rv32c_jalr_cg.cp_rs1_toggle | - Tests needed**\* | +| | | | +| | - rv32c_jr_cg.cp_rs1_toggle | - Tests needed**\* | +| | | | ++----------------------+------------------------------------+----------------------------------------+ +| cg_csritype | - \*.cp_csr | - Need CSR tests*\* | +| | | | +| - | | | +| rv32zicsr_csrrw_cg | | | +| | | | +| - | | | +| rv32zicsr_csrrs_cg | | | +| | | | +| - | | | +| rv32zicsr_csrrc_cg | | | ++----------------------+------------------------------------+----------------------------------------+ +| cg_cb_shift | - \*.cp_rs1 | - UVM_BUG #1425 | +| | | | +| - rv32c_srli_cg | | | +| | | | +| - rv32c_srai_cg | | | ++----------------------+------------------------------------+----------------------------------------+ +| cg_cj | - \*.cp_imm_value | - imm = 0x0 (infinite loop) | +| | | | +| - rv32c_j_cg | | | +| | | | +| - rv32c_jal_cg | | | ++----------------------+------------------------------------+----------------------------------------+ +| cg_itype_load | - rv32i_lbu_cg.cp_rd_toggle | - LBU,LHU limitation | +| | | | +| - rv32i_lbu_cg | - rv32i_lhu_cg.cp_rd_toggle | | +| | | | +| - rv32i_lhu_cg | | | ++----------------------+------------------------------------+----------------------------------------+ +| cg_jtype | - cp_immj_value | - immj = 0x0 (infinite loop) | +| | | | +| - rv32i_jal_cg | - cp_rd_toggle | - Tests needed***\* | ++----------------------+------------------------------------+----------------------------------------+ +| cg_cb_andi | - cp_rs1 | - UVM_BUG #1425 | +| | | | +| - rv32c_andi_cg | | | ++----------------------+------------------------------------+----------------------------------------+ +| cg_cr | - cp_rs1_toggle | - c.mv should not have rs1 (UVM_BUG) | +| | | | +| - rv32c_mv_cg | | | ++----------------------+------------------------------------+----------------------------------------+ +| cg_utype | - rv32i_lui_cg.cp_immu_value | - Test needed**\* | +| | | | +| - rv32i_auipc_cg | | | ++----------------------+------------------------------------+----------------------------------------+ +| cg_rtype_slt | - \*.cross_rd_rs1_rs2 | - Test needed***\* | +| | | | +| - rv32i_sltu_cg | | | +| | | | +| - rv32i_slt_cg | | | ++----------------------+------------------------------------+----------------------------------------+ +| cg_rtype_shift | - \*.cross_rd_rs1_rs2 | - Test needed***\* | +| | | | +| - rv32i_sra_cg | | | +| | | | +| - rv32i_srl_cg | | | +| | | | +| - rv32i_sll_cg | | | ++----------------------+------------------------------------+----------------------------------------+ +| cg_rtype | - \*.cross_rd_rs1_rs2 | - Test needed***\* | +| | | | +| - rv32i_add_cg | | | +| | | | +| - rv32i_sub_cg | | | +| | | | +| - rv32i_xor_cg | | | +| | | | +| - rv32i_and_cg | | | +| | | | +| - rv32i_or_cg | | | +| | | | +| - rv32m_mul_cg | | | +| | | | +| - rv32m_mulh_cg | | | +| | | | +| - rv32m_mulhu_cg | | | +| | | | +| - rv32m_mulhsu_cg | | | +| | | | +| - rv32m_rem_cg | | | +| | | | +| - rv32m_remu_cg | | | +| | | | +| - rv32m_div_cg | | | +| | | | +| - rv32m_divu_cg | | | ++----------------------+------------------------------------+----------------------------------------+ +| cg_itype | - rv32i_jalr_cg.cp_rs1 | - Test needed**\* | +| | | | +| - rv32i_jalr_cg | - rv32i_jalr_cg.cp_rd | - rd = 0x0 it’s a c.jalr (UVM_BUG) | +| | | | +| - rv32i_andi_cg | - rv32i_jalr_cg.cp_rd_rs1_hazard | - imm = 0x0 for jalr infinite loop | +| | | | +| - rv32i_ori_cg | - rv32i_jalr_cg.cp_rs1_value | - infinite loop | +| | | | +| - rv32i_xori_cg | - rv32i_jalr_cg.cp_rd_value | | +| | | | +| | - rv32i_jalr_cg.cp_rd_toggle | | ++----------------------+------------------------------------+----------------------------------------+ +| cg_btype | - \*.cross_rs1_rs2 | - Test needed***\* | +| | | | +| - rv32i_bge_cg | | | +| | | | +| - rv32i_bltu_cg | | | +| | | | +| - rv32i_beq_cg | | | +| | | | +| - rv32i_bne_cg | | | +| | | | +| - rv32i_blt_cg | | | +| | | | +| - rv32i_bgeu_cg | | | ++----------------------+------------------------------------+----------------------------------------+ +| cg_itype_slt | - cross_rs1_immi_value | - Test needed**\* | +| | | | +| - rv32i_slti_cg | | | ++----------------------+------------------------------------+----------------------------------------+ +| cg_itype_shift | - rv32i_slli_cg.cp_rd_rs1_hazard | - Test needed**\* | +| | | | +| - rv32i_slli_cg | - rv32i_srli_cg.cp_rd_rs1_hazard | | +| | | | +| - rv32i_srli_cg | - rv32i_slli_cg.cross_rd_rs1 | | +| | | | +| - rv32i_srai_cg | - rv32i_srli_cg. cross_rd_rs1 | | ++----------------------+------------------------------------+----------------------------------------+ + +**Conventions and Terminology :** + +*RVFI limitation\** : the RVFI in the CVA6 get it's information from the commit stage, that means the ISACOV agent can get only information of valid instruction (committed instruction), so any instruction raising an exception or can’t be cover. + +*Need CSR tests*\** : we can get what has been done in CSR verification task. + +*Test needed*\*** : the test is feasible. + +*Test needed*\**** : the test isn’t feasible, because it’s going to take a +lot of time to write (a lot of combination to cover). diff --git a/verif/docs/images/CVA6_env.drawio.drawio.png b/verif/docs/images/CVA6_env.drawio.drawio.png new file mode 100644 index 0000000000..b7cb35952c Binary files /dev/null and b/verif/docs/images/CVA6_env.drawio.drawio.png differ diff --git a/verif/docs/verif-approvals.md b/verif/docs/verif-approvals.md new file mode 100644 index 0000000000..68ab40377e --- /dev/null +++ b/verif/docs/verif-approvals.md @@ -0,0 +1,77 @@ +# Approvals of CVA6 verification tasks +For each verification task on CVA6 v5.0.0, the artefacts have to be checked. +It means dedicated approvals for each artifact produced by engineers. + +## Approval +To approve an artefact, the approving person has to update this document. + +## User manual chapter/section +For some the topics, the user manual chapter may only describe differences +and precisions with existing specifications +like RISC-V Instruction Set Manual, AXI Protocol, or CV-X-IF. +For other ones (when no specification already exists), it shall be a brand new chapter. + +Each chapter/section has to be formally approved. + +## DV plan (VP tool) +Based on the user manual, DV plan is written using the VP tool which +provides a way to have text files allowing easier differences than binary format. + +Each DV plan has to be formally approved. + +## Test bench +To implement the DV plan, the test bench has to be enriched. +When needed a UVM agent has to be developed or to be reused from core-v-verif. +Such UVM agents have to be generic as much as possible to be reusable. +Specific CVA6 behaviours have to be part of the CVA6 UVM environment. + +To exercise the DUT, tests have to be added. Two types of tests are possible: +- Generated ones: produced by riscv-dv +- Directed ones: hand crafted to address specific cases difficult to exercise with generated tests + +The implementation of the different components (tests, code coverage, assertions, agents,...) have to be formally approved. + +## Coverage +- Functional coverage: if not 100%, missing points explained and approved +- Code coverage: provide delta results after new tests +- Results available in CI dashboard + +The results of coverage and the missing points have to be formally approved. + +## GitHub issues +Once running tests, discrepancies with the expected behaviour can be observed. +For each of them, a GitHub issue has to be created with the relevant +information (e.g. a detailed explanation how to reproduce the problem). + +Each issue has to be assigned. + + +## ISACOV + +| Task | Date | Owner | Approved by | Commit hash | link to extra information (GitHub issue, doc,..) | +| --------------- | ---------- | --------------------- | --------------------- | ------------ | ------------------------------------------------ | +| User Manual | 2023-05-26 | Ayoub Jalali | André Sintzoff | [be58d57d](https://github.com/openhwgroup/cva6/commit/be58d57d)| [User Manual chapter](https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/RISCV_Instructions.html) | +| DV plan | YYYY-MM-DD | First name, Last name | First name, Last name | 8 characters | 50 characters | +| Test bench | YYYY-MM-DD | First name, Last name | First name, Last name | 8 characters | 50 characters | +| Coverage | YYYY-MM-DD | First name, Last name | First name, Last name | 8 characters | 50 characters | +| Assigned Issues | YYYY-MM-DD | First name, Last name | First name, Last name | 8 characters | 50 characters | + +## CV-X-IF + +| Task | Date | Owner | Approved by | Commit hash | link to extra information (GitHub issue, doc,..) | +| --------------- | ---------- | --------------------- | --------------------- | ------------ | ------------------------------------------------ | +| User Manual | YYYY-MM-DD | First name, Last name | First name, Last name | 8 characters | 50 characters | +| DV plan | YYYY-MM-DD | First name, Last name | First name, Last name | 8 characters | 50 characters | +| Test bench | YYYY-MM-DD | First name, Last name | First name, Last name | 8 characters | 50 characters | +| Coverage | YYYY-MM-DD | First name, Last name | First name, Last name | 8 characters | 50 characters | +| Assigned Issues | YYYY-MM-DD | First name, Last name | First name, Last name | 8 characters | 50 characters | + +## AXI + +| Task | Date | Owner | Approved by | Commit hash | link to extra information (GitHub issue, doc,..) | +| --------------- | ---------- | --------------------- | --------------------- | ------------ | ------------------------------------------------ | +| User Manual | YYYY-MM-DD | First name, Last name | First name, Last name | 8 characters | 50 characters | +| DV plan | YYYY-MM-DD | First name, Last name | First name, Last name | 8 characters | 50 characters | +| Test bench | YYYY-MM-DD | First name, Last name | First name, Last name | 8 characters | 50 characters | +| Coverage | YYYY-MM-DD | First name, Last name | First name, Last name | 8 characters | 50 characters | +| Assigned Issues | YYYY-MM-DD | First name, Last name | First name, Last name | 8 characters | 50 characters | diff --git a/verif/env/corev-dv/README.md b/verif/env/corev-dv/README.md new file mode 100644 index 0000000000..bf0377b0f7 --- /dev/null +++ b/verif/env/corev-dv/README.md @@ -0,0 +1,40 @@ +Customize and Extend Generator +============================== + +Add custom instructions +----------------------- + +- To generate a test containing the cvxif custom instructions, run the commands below, in sim directory: + ```bash + cp ../env/corev-dv/custom/riscv_custom_instr_enum.sv ./dv/src/isa/custom/ + python3 cva6.py --testlist=dv/yaml/base_testlist.yaml --test riscv_arithmetic_basic_test --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=vcs-uvm + -cs ../env/corev-dv/target/rv64gc/ --mabi lp64 --isa rv64gc --sim_opts="+uvm_set_inst_override=riscv_asm_program_gen,cva6_asm_program_gen_c,'uvm_test_top.asm_gen'" --simulator_yaml ../env/corev-dv/simulator.yaml + ``` + The command generates the riscv_arithmetic_basic_test described in dv/yaml/base_testlist.yaml, you can define your own testlist.yaml. + +- Supported targets: `rv64gc` and `rv32imc` + +- CUS_EXC, CUS_M_ADD, CUS_S_ADD, CUS_NOP_EXC and CUS_ISS_EXC instructions will not be generated, because they are not yet supported by CVA6/SPIKE. + +- To add new custom instructions: + - 1. Add the new instruction enum to `riscv_custom_instr_enum.sv` + .. code-block example:: verilog + CUSTOM_ADD, + CUSTOM_SUB, + ... + - 2. Add custom instruction definition to `rv32x_instr.sv` (or to another custom file.sv) + .. code-block example:: verilog + `DEFINE_CVXIF_CUSTOM_INSTR(CUSTOM_ADD, R_FORMAT, ARITHMETIC, RV32X) + `DEFINE_CVXIF_CUSTOM_INSTR(CUSTOM_SUB, R_FORMAT, ARITHMETIC, RV32X)` + ... + - 3. Add your macros to `cva6_defines.svh` + .. code-block example: + `define DEFINE_CVXIF_CUSTOM_INSTR(instr_n, instr_format, instr_category, instr_group, imm_tp = IMM) \ + class riscv_``instr_n``_instr extends cvxif_custom_instr;` \ + `INSTR_BODY(instr_n, instr_format, instr_category, instr_group, imm_tp)` + ... + - 4. If the instructions are related to cvxif: add the instr description to `cvxif_custom_instr` class + else: Extend `riscv_custom_instr.sv` and implement key functions like get_instr_name, convert2asm + - 5. Add RV32X to supported_isa in riscv_core_setting.sv + - 6. Add the instruction macros to `user_define.include` or `user_define.h` + diff --git a/verif/env/corev-dv/custom/cvxif_custom_instr.sv b/verif/env/corev-dv/custom/cvxif_custom_instr.sv new file mode 100644 index 0000000000..efb0a593ec --- /dev/null +++ b/verif/env/corev-dv/custom/cvxif_custom_instr.sv @@ -0,0 +1,119 @@ +// Copyright 2022 Thales DIS design services SAS +// Copyright 2022 OpenHW Group +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Zineb EL KACIMI (zineb.el-kacimi@external.thalesgroup.com) +// ------------------------------------------------------------------------------ // + +`ifndef __CVXIF_CUSTOM_INSTR_SV__ +`define __CVXIF_CUSTOM_INSTR_SV__ + +/** + * This class describe custom instructions used with the cvxif agent. + */ +class cvxif_custom_instr extends riscv_custom_instr; + + rand riscv_reg_t rs3; + + `uvm_object_utils(cvxif_custom_instr) + `uvm_object_new + + virtual function string get_instr_name(); + get_instr_name = instr_name.name(); + return get_instr_name; + endfunction : get_instr_name + + + constraint cus_rx { + if (instr_name inside {CUS_EXC}) { + rs1 dist { [0:9] := 10, 10 := 2, [11:13] := 10, 14 := 2, 15 := 10, [16:23] := 2, [25:31] := 2 }; + } + } + + // Convert the instruction to assembly code + virtual function string convert2asm(string prefix = ""); + string asm_str; + asm_str = format_string(get_instr_name(), MAX_INSTR_STR_LEN); + case (instr_name) + CUS_ADD: asm_str = $sformatf("%0s %0s, %0s, %0s", asm_str, rd.name(), rs1.name(), rs2.name()); + CUS_ADD_MULTI: asm_str = $sformatf("%0s %0s, %0s, %0s", asm_str, rd.name(), rs1.name(), rs2.name()); + CUS_ADD_RS3: asm_str = $sformatf("%0s %0s, %0s, %0s, %0s", asm_str, rd.name(), rs1.name(), rs2.name(), rs3.name()); + CUS_NOP: asm_str = "cus_nop"; + CUS_S_ADD: asm_str = $sformatf("%0s %0s, %0s, %0s", asm_str, rd.name(), rs1.name(), rs2.name()); + CUS_U_ADD: asm_str = $sformatf("%0s %0s, %0s, %0s", asm_str, rd.name(), rs1.name(), rs2.name()); + CUS_EXC: asm_str = $sformatf("%0s %0s", asm_str, rs1.name()); + endcase + comment = {get_instr_name(), " ", comment}; + if (comment != "") begin + asm_str = {asm_str, " #", comment}; + end + return asm_str.tolower(); + endfunction : convert2asm + + virtual function void set_imm_len(); + imm_len = 6; + endfunction : set_imm_len + + function bit [6:0] get_opcode(); + case (instr_name) inside + {CUS_ADD, CUS_ADD_MULTI, CUS_ADD_RS3, CUS_NOP, CUS_U_ADD, CUS_S_ADD, CUS_EXC} : get_opcode = 7'b1111011; + default : `uvm_fatal(`gfn, $sformatf("Unsupported instruction %0s", instr_name.name())) + endcase + endfunction + + virtual function bit [2:0] get_func3(); + case (instr_name) inside + CUS_ADD_MULTI, CUS_ADD_RS3, CUS_U_ADD, CUS_S_ADD : get_func3 = 3'b000; + CUS_ADD : get_func3 = 3'b001; + CUS_EXC : get_func3 = 3'b010; + endcase + endfunction + + virtual function bit [6:0] get_func7(); + case (instr_name) + CUS_ADD : get_func7 = 7'b0000000; + CUS_NOP : get_func7 = 7'b0000000; + CUS_ADD_MULTI : get_func7 = 7'b0001000; + CUS_U_ADD : get_func7 = 7'b0000010; + CUS_S_ADD : get_func7 = 7'b0000110; + CUS_EXC : get_func7 = 7'b1100000; + endcase + endfunction + + virtual function bit [1:0] get_func2(); + case (instr_name) + CUS_ADD_RS3 : get_func2 = 2'b01; + endcase + endfunction + + virtual function void set_rand_mode(); + case (instr_name) inside + "CUS_NOP": begin + has_rd = 1'b0; + has_rs1 = 1'b0; + has_rs2 = 1'b0; + has_imm = 1'b0; + end + "CUS_EXC": begin + has_rd = 1'b0; + has_rs1 = 1'b1; + has_rs2 = 1'b0; + has_imm = 1'b0; + end + endcase + endfunction + + function void pre_randomize(); + rd.rand_mode(has_rd); + rs1.rand_mode(has_rs1); + rs2.rand_mode(has_rs2); + imm.rand_mode(has_imm); + endfunction + +endclass + +`endif // __CVXIF_CUSTOM_INSTR_SV__ diff --git a/verif/env/corev-dv/custom/riscv_custom_instr_enum.sv b/verif/env/corev-dv/custom/riscv_custom_instr_enum.sv new file mode 100644 index 0000000000..314a3078de --- /dev/null +++ b/verif/env/corev-dv/custom/riscv_custom_instr_enum.sv @@ -0,0 +1,20 @@ +// Copyright 2022 Thales DIS design services SAS +// Copyright 2022 OpenHW Group +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Zineb EL KACIMI (zineb.el-kacimi@external.thalesgroup.com) +// ------------------------------------------------------------------------------ // + +// Add custom instruction name enum +CUSTOM_1, +CUS_ADD, +CUS_ADD_MULTI, +CUS_NOP, +CUS_ADD_RS3, +CUS_EXC, +CUS_U_ADD, +CUS_S_ADD, diff --git a/verif/env/corev-dv/custom/rv32x_instr.sv b/verif/env/corev-dv/custom/rv32x_instr.sv new file mode 100644 index 0000000000..098e15b0f4 --- /dev/null +++ b/verif/env/corev-dv/custom/rv32x_instr.sv @@ -0,0 +1,18 @@ +// Copyright 2022 Thales DIS design services SAS +// Copyright 2022 OpenHW Group +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Zineb EL KACIMI (zineb.el-kacimi@external.thalesgroup.com) +// ------------------------------------------------------------------------------ // + +`DEFINE_CVXIF_CUSTOM_INSTR(CUS_ADD, R_FORMAT, ARITHMETIC, RV32X) +`DEFINE_CVXIF_CUSTOM_INSTR(CUS_ADD_MULTI, R_FORMAT, ARITHMETIC, RV32X) +`DEFINE_CVXIF_CUSTOM_INSTR(CUS_NOP, R_FORMAT, ARITHMETIC, RV32X) +`DEFINE_CVXIF_CUSTOM_INSTR(CUS_ADD_RS3, R4_FORMAT, ARITHMETIC, RV32X) +`DEFINE_CVXIF_CUSTOM_INSTR(CUS_EXC, R_FORMAT, ARITHMETIC, RV32X) +`DEFINE_CVXIF_CUSTOM_INSTR(CUS_U_ADD, R_FORMAT, ARITHMETIC, RV32X) +`DEFINE_CVXIF_CUSTOM_INSTR(CUS_S_ADD, R_FORMAT, ARITHMETIC, RV32X) diff --git a/verif/env/corev-dv/cva6-files.f b/verif/env/corev-dv/cva6-files.f new file mode 100644 index 0000000000..31ac1e72ef --- /dev/null +++ b/verif/env/corev-dv/cva6-files.f @@ -0,0 +1,20 @@ +// Copyright 2022 Thales DIS design services SAS +// Copyright 2022 OpenHW Group +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Zineb EL KACIMI (zineb.el-kacimi@external.thalesgroup.com) +// ------------------------------------------------------------------------------ // + +// HEADERS ++incdir+${CVA6_DV_ROOT}/ ++incdir+${CVA6_DV_ROOT}/custom ++incdir+${CVA6_DV_ROOT}/user_extension + +// SOURCES +${CVA6_DV_ROOT}/cva6_signature_pkg.sv +${CVA6_DV_ROOT}/cva6_instr_test_pkg.sv + diff --git a/verif/env/corev-dv/cva6_asm_program_gen.sv b/verif/env/corev-dv/cva6_asm_program_gen.sv new file mode 100644 index 0000000000..9fb9e2e451 --- /dev/null +++ b/verif/env/corev-dv/cva6_asm_program_gen.sv @@ -0,0 +1,443 @@ +/* + * Copyright 2018 Google LLC + * Copyright 2020 Andes Technology Co., Ltd. + * Copyright 2020 OpenHW Group + * Copyright 2022 Thales DIS design services SAS + * + * Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 + * + * You may obtain a copy of the License at + * https://solderpad.org/licenses/ + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +`ifndef __CVA6_ASM_PROGRAM_GEN_SV__ +`define __CVA6_ASM_PROGRAM_GEN_SV__ + +//----------------------------------------------------------------------------------------- +// CVA6 assembly program generator - extension of the RISC-V assembly program generator. +// +// Overrides gen_program_header() and gen_test_done() +//----------------------------------------------------------------------------------------- + +class cva6_asm_program_gen_c extends riscv_asm_program_gen; + + `uvm_object_utils(cva6_asm_program_gen_c) + + function new (string name = ""); + super.new(name); + endfunction + + virtual function void gen_program_header(); + string str[$]; + cva6_instr_gen_config_c cfg_cva6; + `DV_CHECK_FATAL($cast(cfg_cva6, cfg), "Could not cast cfg into cfg_cva6") + if (cfg_cva6.enable_x_extension) begin //used for cvxif custom test + instr_stream.push_back(".include \"x_extn_user_define.h\""); + end + instr_stream.push_back(".include \"user_define.h\""); + instr_stream.push_back(".globl _start"); + instr_stream.push_back(".section .text"); + if (cfg.disable_compressed_instr) begin + instr_stream.push_back(".option norvc;"); + end + str = {"csrr x5, mhartid"}; + for (int hart = 0; hart < cfg.num_of_harts; hart++) begin + str = {str, $sformatf("li x6, %0d", hart), + $sformatf("beq x5, x6, %0df", hart)}; + end + gen_section("_start", str); + for (int hart = 0; hart < cfg.num_of_harts; hart++) begin + instr_stream.push_back($sformatf("%0d: j h%0d_start", hart, hart)); + end + endfunction + + // Generate the interrupt and trap handler for different privileged mode. + // The trap handler checks the xCAUSE to determine the type of the exception and jumps to + // corresponding exeception handling routine. + virtual function void gen_trap_handler_section(int hart, + string mode, + privileged_reg_t cause, privileged_reg_t tvec, + privileged_reg_t tval, privileged_reg_t epc, + privileged_reg_t scratch, privileged_reg_t status, + privileged_reg_t ie, privileged_reg_t ip); + bit is_interrupt = 'b1; + string tvec_name; + string instr[$]; + if (cfg.mtvec_mode == VECTORED) begin + gen_interrupt_vector_table(hart, mode, status, cause, ie, ip, scratch, instr); + end else begin + // Push user mode GPR to kernel stack before executing exception handling, this is to avoid + // exception handling routine modify user program state unexpectedly + push_gpr_to_kernel_stack(status, scratch, cfg.mstatus_mprv, cfg.sp, cfg.tp, instr); + // Checking xStatus can be optional if ISS (like spike) has different implementation of + // certain fields compared with the RTL processor. + if (cfg.check_xstatus) begin + instr = {instr, $sformatf("csrr x%0d, 0x%0x # %0s", cfg.gpr[0], status, status.name())}; + end + instr = {instr, + // Use scratch CSR to save a GPR value + // Check if the exception is caused by an interrupt, if yes, jump to interrupt + // handler Interrupt is indicated by xCause[XLEN-1] + $sformatf("csrr x%0d, 0x%0x # %0s", cfg.gpr[0], cause, cause.name()), + $sformatf("srli x%0d, x%0d, %0d", cfg.gpr[0], cfg.gpr[0], XLEN-1), + $sformatf("bne x%0d, x0, %0s%0smode_intr_handler", + cfg.gpr[0], hart_prefix(hart), mode)}; + end + // The trap handler will occupy one 4KB page, it will be allocated one entry in the page table + // with a specific privileged mode. + if (SATP_MODE != BARE) begin + instr_stream.push_back(".align 12"); + end else begin + instr_stream.push_back($sformatf(".align %d", cfg.tvec_alignment)); + end + tvec_name = tvec.name(); + gen_section(get_label($sformatf("%0s_handler", tvec_name.tolower()), hart), instr); + // Exception handler + instr = {}; + if (cfg.mtvec_mode == VECTORED) begin + push_gpr_to_kernel_stack(status, scratch, cfg.mstatus_mprv, cfg.sp, cfg.tp, instr); + end + gen_signature_handshake(instr, CORE_STATUS, HANDLING_EXCEPTION); + instr = {instr, + // The trap is caused by an exception, read back xCAUSE, xEPC to see if these + // CSR values are set properly. The checking is done by comparing against the log + // generated by ISA simulator (spike). + $sformatf("csrr x%0d, 0x%0x # %0s", cfg.gpr[0], epc, epc.name()), + $sformatf("csrr x%0d, 0x%0x # %0s", cfg.gpr[0], cause, cause.name()), + // Breakpoint + $sformatf("li x%0d, 0x%0x # BREAKPOINT", cfg.gpr[1], BREAKPOINT), + $sformatf("beq x%0d, x%0d, %0sebreak_handler", + cfg.gpr[0], cfg.gpr[1], hart_prefix(hart)), + // Check if it's an ECALL exception. Jump to ECALL exception handler + $sformatf("li x%0d, 0x%0x # ECALL_UMODE", cfg.gpr[1], ECALL_UMODE), + $sformatf("beq x%0d, x%0d, %0secall_handler", + cfg.gpr[0], cfg.gpr[1], hart_prefix(hart)), + $sformatf("li x%0d, 0x%0x # ECALL_SMODE", cfg.gpr[1], ECALL_SMODE), + $sformatf("beq x%0d, x%0d, %0secall_handler", + cfg.gpr[0], cfg.gpr[1], hart_prefix(hart)), + $sformatf("li x%0d, 0x%0x # ECALL_MMODE", cfg.gpr[1], ECALL_MMODE), + $sformatf("beq x%0d, x%0d, %0secall_handler", + cfg.gpr[0], cfg.gpr[1], hart_prefix(hart)), + // Page table fault or access fault conditions + $sformatf("li x%0d, 0x%0x", cfg.gpr[1], INSTRUCTION_ACCESS_FAULT), + $sformatf("beq x%0d, x%0d, %0sinstr_fault_handler", + cfg.gpr[0], cfg.gpr[1], hart_prefix(hart)), + $sformatf("li x%0d, 0x%0x", cfg.gpr[1], LOAD_ACCESS_FAULT), + $sformatf("beq x%0d, x%0d, %0sload_fault_handler", + cfg.gpr[0], cfg.gpr[1], hart_prefix(hart)), + $sformatf("li x%0d, 0x%0x", cfg.gpr[1], STORE_AMO_ACCESS_FAULT), + $sformatf("beq x%0d, x%0d, %0sstore_fault_handler", + cfg.gpr[0], cfg.gpr[1], hart_prefix(hart)), + $sformatf("li x%0d, 0x%0x", cfg.gpr[1], INSTRUCTION_PAGE_FAULT), + $sformatf("beq x%0d, x%0d, %0spt_instr_fault_handler", + cfg.gpr[0], cfg.gpr[1], hart_prefix(hart)), + $sformatf("li x%0d, 0x%0x", cfg.gpr[1], LOAD_PAGE_FAULT), + $sformatf("beq x%0d, x%0d, %0spt_load_fault_handler", + cfg.gpr[0], cfg.gpr[1], hart_prefix(hart)), + $sformatf("li x%0d, 0x%0x", cfg.gpr[1], STORE_AMO_PAGE_FAULT), + $sformatf("beq x%0d, x%0d, %0spt_store_fault_handler", + cfg.gpr[0], cfg.gpr[1], hart_prefix(hart)), + // Illegal instruction exception + $sformatf("li x%0d, 0x%0x # ILLEGAL_INSTRUCTION", cfg.gpr[1], ILLEGAL_INSTRUCTION), + $sformatf("beq x%0d, x%0d, %0sillegal_instr_handler", + cfg.gpr[0], cfg.gpr[1], hart_prefix(hart)), + // Instruction Address misaligned exception + $sformatf("li x%0d, 0x%0x # INSTR ADDR MISALIGNED", cfg.gpr[1], INSTRUCTION_ADDRESS_MISALIGNED), + $sformatf("beq x%0d, x%0d, %0sinstr_misaligned_handler", + cfg.gpr[0], cfg.gpr[1], hart_prefix(hart)), + // Load Address misaligned exception + $sformatf("li x%0d, 0x%0x # LOAD ADDR MISALIGNED", cfg.gpr[1], LOAD_ADDRESS_MISALIGNED), + $sformatf("beq x%0d, x%0d, %0sload_misaligned_handler", + cfg.gpr[0], cfg.gpr[1], hart_prefix(hart)), + // Store Address misaligned exception + $sformatf("li x%0d, 0x%0x # STORE ADDR MISALIGNED", cfg.gpr[1], STORE_AMO_ADDRESS_MISALIGNED), + $sformatf("beq x%0d, x%0d, %0sstore_misaligned_handler", + cfg.gpr[0], cfg.gpr[1], hart_prefix(hart)), + // Skip checking tval for illegal instruction as it's implementation specific + $sformatf("csrr x%0d, 0x%0x # %0s", cfg.gpr[1], tval, tval.name()), + "1: jal x1, test_done " + }; + gen_section(get_label($sformatf("%0smode_exception_handler", mode), hart), instr); + endfunction + + // Trap handling routine + virtual function void gen_all_trap_handler(int hart); + string instr[$]; + // If PMP isn't supported, generate the relevant trap handler sections as per usual + if (!support_pmp) begin + gen_trap_handlers(hart); + // Ecall handler + gen_ecall_handler(hart); + // Instruction fault handler + gen_instr_fault_handler(hart); + // Load fault handler + gen_load_fault_handler(hart); + // Store fault handler + gen_store_fault_handler(hart); + end + // Ebreak handler + gen_ebreak_handler(hart); + // Illegal instruction handler + gen_illegal_instr_handler(hart); + // Instruction page fault handler + gen_pt_instr_fault_handler(hart); + // Load page fault handler + gen_pt_load_fault_handler(hart); + // Store page fault handler + gen_pt_store_fault_handler(hart); + // Instruction Address Misaligned handler + gen_instr_misaligned_handler(hart); + // Load Address Misaligned handler + gen_load_misaligned_handler(hart); + // Store Address Misaligned handler + gen_store_misaligned_handler(hart); + // Generate page table fault handling routine + // Page table fault is always handled in machine mode, as virtual address translation may be + // broken when page fault happens. + gen_signature_handshake(instr, CORE_STATUS, HANDLING_EXCEPTION); + if(page_table_list != null) begin + page_table_list.gen_page_fault_handling_routine(instr); + end else begin + instr.push_back("nop"); + end + gen_section(get_label("pt_fault_handler", hart), instr); + endfunction + + // Helper function to generate the proper sequence of handshake instructions + // to signal the testbench (see riscv_signature_pkg.sv) + function void gen_signature_handshake(ref string instr[$], + input signature_type_t signature_type, + core_status_t core_status = INITIALIZED, + test_result_t test_result = TEST_FAIL, + privileged_reg_t csr = MSCRATCH, + string addr_label = ""); + if (cfg.require_signature_addr) begin + string str[$]; + str = {$sformatf("li x%0d, 0x%0h", cfg.gpr[1], cfg.signature_addr)}; + instr = {instr, str}; + case (signature_type) + // A single data word is written to the signature address. + // Bits [7:0] contain the signature_type of CORE_STATUS, and the upper + // XLEN-8 bits contain the core_status_t data. + CORE_STATUS: begin + str = {$sformatf("li x%0d, 0x%0h", cfg.gpr[0], core_status), + $sformatf("slli x%0d, x%0d, 8", cfg.gpr[0], cfg.gpr[0]), + $sformatf("addi x%0d, x%0d, 0x%0h", cfg.gpr[0], + cfg.gpr[0], signature_type), + $sformatf("sw x%0d, 0(x%0d)", cfg.gpr[0], cfg.gpr[1])}; + instr = {instr, str}; + end + // A single data word is written to the signature address. + // Bits [7:0] contain the signature_type of TEST_RESULT, and the upper + // XLEN-8 bits contain the test_result_t data. + TEST_RESULT: begin + str = {$sformatf("li x%0d, 0x%0h", cfg.gpr[0], test_result), + $sformatf("slli x%0d, x%0d, 8", cfg.gpr[0], cfg.gpr[0]), + $sformatf("addi x%0d, x%0d, 0x%0h", cfg.gpr[0], + cfg.gpr[0], signature_type), + $sformatf("sw x%0d, 0(x%0d)", cfg.gpr[0], cfg.gpr[1])}; + instr = {instr, str}; + end + // The first write to the signature address contains just the + // signature_type of WRITE_GPR. + // It is followed by 32 consecutive writes to the signature address, + // each writing the data contained in one GPR, starting from x0 as the + // first write, and ending with x31 as the 32nd write. + WRITE_GPR: begin + str = {$sformatf("li x%0d, 0x%0h", cfg.gpr[0], signature_type), + $sformatf("sw x%0d, 0(x%0d)", cfg.gpr[0], cfg.gpr[1])}; + instr = {instr, str}; + for(int i = 0; i < 32; i++) begin + str = {$sformatf("sw x%0x, 0(x%0d)", i, cfg.gpr[1])}; + instr = {instr, str}; + end + end + // The first write to the signature address contains the + // signature_type of WRITE_CSR in bits [7:0], and the CSR address in + // the upper XLEN-8 bits. + // It is followed by a second write to the signature address, + // containing the data stored in the specified CSR. + WRITE_CSR: begin + if (!(csr inside {implemented_csr})) begin + return; + end + str = {$sformatf("li x%0d, 0x%0h", cfg.gpr[0], csr), + $sformatf("slli x%0d, x%0d, 8", cfg.gpr[0], cfg.gpr[0]), + $sformatf("addi x%0d, x%0d, 0x%0h", cfg.gpr[0], + cfg.gpr[0], signature_type), + $sformatf("sw x%0d, 0(x%0d)", cfg.gpr[0], cfg.gpr[1]), + $sformatf("csrr x%0d, 0x%0h", cfg.gpr[0], csr), + $sformatf("sw x%0d, 0(x%0d)", cfg.gpr[0], cfg.gpr[1])}; + instr = {instr, str}; + end + default: begin + `uvm_fatal(`gfn, "signature_type is not defined") + end + endcase + end + endfunction + + // ECALL trap handler + virtual function void gen_ecall_handler(int hart); + string instr[$]; + gen_signature_handshake(instr, CORE_STATUS, ECALL_EXCEPTION); + gen_signature_handshake(.instr(instr), .signature_type(WRITE_CSR), .csr(MCAUSE)); + instr = {instr, + $sformatf("csrr x%0d, mepc", cfg.gpr[0]), + $sformatf("addi x%0d, x%0d, 4", cfg.gpr[0], cfg.gpr[0]), + $sformatf("csrw mepc, x%0d", cfg.gpr[0]) + }; + pop_gpr_from_kernel_stack(MSTATUS, MSCRATCH, cfg.mstatus_mprv, cfg.sp, cfg.tp, instr); + instr.push_back("mret"); + gen_section(get_label("ecall_handler", hart), instr); + endfunction + + // TODO: handshake correct csr based on delegation + virtual function void gen_instr_fault_handler(int hart); + string instr[$]; + gen_signature_handshake(instr, CORE_STATUS, INSTR_FAULT_EXCEPTION); + gen_signature_handshake(.instr(instr), .signature_type(WRITE_CSR), .csr(MCAUSE)); + instr = {instr, + $sformatf("csrr x%0d, mepc", cfg.gpr[0]), + $sformatf("addi x%0d, x%0d, 4", cfg.gpr[0], cfg.gpr[0]), + $sformatf("csrw mepc, x%0d", cfg.gpr[0]) + }; + pop_gpr_from_kernel_stack(MSTATUS, MSCRATCH, cfg.mstatus_mprv, cfg.sp, cfg.tp, instr); + instr.push_back("mret"); + gen_section(get_label("instr_fault_handler", hart), instr); + endfunction + + // TODO: handshake correct csr based on delegation + virtual function void gen_load_fault_handler(int hart); + string instr[$]; + gen_signature_handshake(instr, CORE_STATUS, LOAD_FAULT_EXCEPTION); + gen_signature_handshake(.instr(instr), .signature_type(WRITE_CSR), .csr(MCAUSE)); + instr = {instr, + $sformatf("csrr x%0d, mepc", cfg.gpr[0]), + $sformatf("addi x%0d, x%0d, 4", cfg.gpr[0], cfg.gpr[0]), + $sformatf("csrw mepc, x%0d", cfg.gpr[0]) + }; + pop_gpr_from_kernel_stack(MSTATUS, MSCRATCH, cfg.mstatus_mprv, cfg.sp, cfg.tp, instr); + instr.push_back("mret"); + gen_section(get_label("load_fault_handler", hart), instr); + endfunction + + // TODO: handshake correct csr based on delegation + virtual function void gen_store_fault_handler(int hart); + string instr[$]; + gen_signature_handshake(instr, CORE_STATUS, STORE_FAULT_EXCEPTION); + gen_signature_handshake(.instr(instr), .signature_type(WRITE_CSR), .csr(MCAUSE)); + instr = {instr, + $sformatf("csrr x%0d, mepc", cfg.gpr[0]), + $sformatf("addi x%0d, x%0d, 4", cfg.gpr[0], cfg.gpr[0]), + $sformatf("csrw mepc, x%0d", cfg.gpr[0]) + }; + pop_gpr_from_kernel_stack(MSTATUS, MSCRATCH, cfg.mstatus_mprv, cfg.sp, cfg.tp, instr); + instr.push_back("mret"); + gen_section(get_label("store_fault_handler", hart), instr); + endfunction + + virtual function void gen_pt_instr_fault_handler(int hart); + string instr[$]; + gen_signature_handshake(instr, CORE_STATUS, INSTR_PAGE_FAULT_EXCEPTION); + gen_signature_handshake(.instr(instr), .signature_type(WRITE_CSR), .csr(MCAUSE)); + instr = {instr, + $sformatf("csrr x%0d, mepc", cfg.gpr[0]), + $sformatf("addi x%0d, x%0d, 4", cfg.gpr[0], cfg.gpr[0]), + $sformatf("csrw mepc, x%0d", cfg.gpr[0]) + }; + pop_gpr_from_kernel_stack(MSTATUS, MSCRATCH, cfg.mstatus_mprv, cfg.sp, cfg.tp, instr); + instr.push_back("mret"); + gen_section(get_label("pt_instr_fault_handler", hart), instr); + endfunction + + virtual function void gen_pt_load_fault_handler(int hart); + string instr[$]; + gen_signature_handshake(instr, CORE_STATUS, LOAD_PAGE_FAULT_EXCEPTION); + gen_signature_handshake(.instr(instr), .signature_type(WRITE_CSR), .csr(MCAUSE)); + instr = {instr, + $sformatf("csrr x%0d, mepc", cfg.gpr[0]), + $sformatf("addi x%0d, x%0d, 4", cfg.gpr[0], cfg.gpr[0]), + $sformatf("csrw mepc, x%0d", cfg.gpr[0]) + }; + pop_gpr_from_kernel_stack(MSTATUS, MSCRATCH, cfg.mstatus_mprv, cfg.sp, cfg.tp, instr); + instr.push_back("mret"); + gen_section(get_label("pt_load_fault_handler", hart), instr); + endfunction + + virtual function void gen_pt_store_fault_handler(int hart); + string instr[$]; + gen_signature_handshake(instr, CORE_STATUS, STORE_PAGE_FAULT_EXCEPTION); + gen_signature_handshake(.instr(instr), .signature_type(WRITE_CSR), .csr(MCAUSE)); + instr = {instr, + $sformatf("csrr x%0d, mepc", cfg.gpr[0]), + $sformatf("addi x%0d, x%0d, 4", cfg.gpr[0], cfg.gpr[0]), + $sformatf("csrw mepc, x%0d", cfg.gpr[0]) + }; + pop_gpr_from_kernel_stack(MSTATUS, MSCRATCH, cfg.mstatus_mprv, cfg.sp, cfg.tp, instr); + instr.push_back("mret"); + gen_section(get_label("pt_store_fault_handler", hart), instr); + endfunction + + virtual function void gen_load_misaligned_handler(int hart); + string instr[$]; + gen_signature_handshake(instr, CORE_STATUS, LD_MISALIGNED_EXCEPTION); + gen_signature_handshake(.instr(instr), .signature_type(WRITE_CSR), .csr(MCAUSE)); + instr = {instr, + $sformatf("csrr x%0d, mepc", cfg.gpr[0]), + $sformatf("addi x%0d, x%0d, 4", cfg.gpr[0], cfg.gpr[0]), + $sformatf("csrw mepc, x%0d", cfg.gpr[0]) + }; + pop_gpr_from_kernel_stack(MSTATUS, MSCRATCH, cfg.mstatus_mprv, cfg.sp, cfg.tp, instr); + instr.push_back("mret"); + gen_section(get_label("load_misaligned_handler", hart), instr); + endfunction + + virtual function void gen_store_misaligned_handler(int hart); + string instr[$]; + gen_signature_handshake(instr, CORE_STATUS, ST_MISALIGNED_EXCEPTION); + gen_signature_handshake(.instr(instr), .signature_type(WRITE_CSR), .csr(MCAUSE)); + instr = {instr, + $sformatf("csrr x%0d, mepc", cfg.gpr[0]), + $sformatf("addi x%0d, x%0d, 4", cfg.gpr[0], cfg.gpr[0]), + $sformatf("csrw mepc, x%0d", cfg.gpr[0]) + }; + pop_gpr_from_kernel_stack(MSTATUS, MSCRATCH, cfg.mstatus_mprv, cfg.sp, cfg.tp, instr); + instr.push_back("mret"); + gen_section(get_label("store_misaligned_handler", hart), instr); + endfunction + + virtual function void gen_instr_misaligned_handler(int hart); + string instr[$]; + gen_signature_handshake(instr, CORE_STATUS, INSTR_MISALIGNED_EXCEPTION); + gen_signature_handshake(.instr(instr), .signature_type(WRITE_CSR), .csr(MCAUSE)); + instr = {instr, + $sformatf("csrr x%0d, mepc", cfg.gpr[0]), + $sformatf("addi x%0d, x%0d, 4", cfg.gpr[0], cfg.gpr[0]), + $sformatf("csrw mepc, x%0d", cfg.gpr[0]) + }; + pop_gpr_from_kernel_stack(MSTATUS, MSCRATCH, cfg.mstatus_mprv, cfg.sp, cfg.tp, instr); + instr.push_back("mret"); + gen_section(get_label("instr_misaligned_handler", hart), instr); + endfunction + + virtual function void gen_test_done(); + string str = format_string("test_done:", LABEL_STR_LEN); + instr_stream.push_back(str); + instr_stream.push_back({indent, "li gp, 1"}); + instr_stream.push_back({indent, "sw gp, tohost, t5"}); + instr_stream.push_back({indent, "wfi"}); + endfunction + +endclass : cva6_asm_program_gen_c + +`endif // __CVA6_ASM_PROGRAM_GEN_SV__ diff --git a/verif/env/corev-dv/cva6_defines.svh b/verif/env/corev-dv/cva6_defines.svh new file mode 100644 index 0000000000..4ce0352ce2 --- /dev/null +++ b/verif/env/corev-dv/cva6_defines.svh @@ -0,0 +1,15 @@ +// Copyright 2022 Thales DIS design services SAS +// Copyright 2022 OpenHW Group +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Zineb EL KACIMI (zineb.el-kacimi@external.thalesgroup.com) +// ------------------------------------------------------------------------------------------- + +// Custom extension instruction for CVXIF +`define DEFINE_CVXIF_CUSTOM_INSTR(instr_n, instr_format, instr_category, instr_group, imm_tp = IMM) \ + class riscv_``instr_n``_instr extends cvxif_custom_instr; \ + `INSTR_BODY(instr_n, instr_format, instr_category, instr_group, imm_tp) diff --git a/verif/env/corev-dv/cva6_instr_base_test.sv b/verif/env/corev-dv/cva6_instr_base_test.sv new file mode 100644 index 0000000000..951378e70c --- /dev/null +++ b/verif/env/corev-dv/cva6_instr_base_test.sv @@ -0,0 +1,54 @@ +/* + * Copyright 2018 Google LLC + * Copyright 2020 OpenHW Group + * Copyright 2023 Thales + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +//------------------------------------------------------------------------------ +// CORE-V instruction generator base test: +// - extension of the RISC-V instruction generator base test. +// +//------------------------------------------------------------------------------ + +class cva6_instr_base_test_c extends riscv_instr_base_test; + + `uvm_component_utils(cva6_instr_base_test_c) + + + function new(string name="", uvm_component parent=null); + super.new(name, parent); + endfunction + + virtual function void build_phase(uvm_phase phase); + override_asm_program_gen(); + override_gen_config(); + super.build_phase(phase); + endfunction + + virtual function void override_asm_program_gen(); + `uvm_info("CVA6_DV", $sformatf("Overriding ..."), UVM_LOW) + uvm_factory::get().set_type_override_by_type(riscv_asm_program_gen::get_type(), + cva6_asm_program_gen_c::get_type()); + `uvm_info("CVA6_DV", $sformatf("Overrid done "), UVM_LOW) + endfunction + + virtual function void override_gen_config(); + `uvm_info("CVA6_DV", $sformatf("Overriding ..."), UVM_LOW) + uvm_factory::get().set_type_override_by_type(riscv_instr_gen_config::get_type(), + cva6_instr_gen_config_c::get_type()); + `uvm_info("CVA6_DV", $sformatf("Overrid done "), UVM_LOW) + endfunction + +endclass : cva6_instr_base_test_c diff --git a/verif/env/corev-dv/cva6_instr_gen_config.sv b/verif/env/corev-dv/cva6_instr_gen_config.sv new file mode 100644 index 0000000000..05aab13db6 --- /dev/null +++ b/verif/env/corev-dv/cva6_instr_gen_config.sv @@ -0,0 +1,56 @@ +/* + * Copyright 2018 Google LLC + * Copyright 2023 Thales + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +//----------------------------------------------------------------------------- +// RISC-V assembly program generator configuration class +//----------------------------------------------------------------------------- + +class cva6_instr_gen_config_c extends riscv_instr_gen_config; + + //----------------------------------------------------------------------------- + // Random instruction generation option + //----------------------------------------------------------------------------- + + // cvxif extension support + bit enable_x_extension; + bit enable_rdrs1_hazard; + bit enable_rdrs2_hazard; + bit enable_same_reg; + + constraint hazard_reg_c { + if (enable_same_reg) { + enable_rdrs1_hazard == 1'b0; + enable_rdrs2_hazard == 1'b0; + } + } + + `uvm_object_utils_begin(cva6_instr_gen_config_c) + `uvm_field_int(enable_x_extension, UVM_DEFAULT) + `uvm_field_int(enable_rdrs1_hazard, UVM_DEFAULT) + `uvm_field_int(enable_rdrs2_hazard, UVM_DEFAULT) + `uvm_field_int(enable_same_reg, UVM_DEFAULT) + `uvm_object_utils_end + + function new (string name = ""); + super.new(name); + get_bool_arg_value("+enable_x_extension=", enable_x_extension); + get_bool_arg_value("+enable_rdrs1_hazard=", enable_rdrs1_hazard); + get_bool_arg_value("+enable_rdrs2_hazard=", enable_rdrs2_hazard); + get_bool_arg_value("+enable_same_reg=", enable_same_reg); + endfunction + +endclass : cva6_instr_gen_config_c diff --git a/verif/env/corev-dv/cva6_instr_hazard_test.sv b/verif/env/corev-dv/cva6_instr_hazard_test.sv new file mode 100644 index 0000000000..2652dbf5e9 --- /dev/null +++ b/verif/env/corev-dv/cva6_instr_hazard_test.sv @@ -0,0 +1,61 @@ +/* + * Copyright 2018 Google LLC + * Copyright 2020 OpenHW Group + * Copyright 2023 Thales + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +//------------------------------------------------------------------------------ +// CORE-V instruction generator base test: +// - extension of the RISC-V instruction generator base test. +// +//------------------------------------------------------------------------------ + +class cva6_instr_hazard_test_c extends riscv_instr_base_test; + + `uvm_component_utils(cva6_instr_hazard_test_c) + + function new(string name="", uvm_component parent=null); + super.new(name, parent); + endfunction + + virtual function void build_phase(uvm_phase phase); + override_asm_program_gen(); + override_gen_config(); + override_rand_stream(); + super.build_phase(phase); + endfunction + + virtual function void override_asm_program_gen(); + `uvm_info("CVA6_DV", $sformatf("Overriding ..."), UVM_LOW) + uvm_factory::get().set_type_override_by_type(riscv_asm_program_gen::get_type(), + cva6_asm_program_gen_c::get_type()); + `uvm_info("CVA6_DV", $sformatf("Overrid done "), UVM_LOW) + endfunction + + virtual function void override_gen_config(); + `uvm_info("CVA6_DV", $sformatf("Overriding ..."), UVM_LOW) + uvm_factory::get().set_type_override_by_type(riscv_instr_gen_config::get_type(), + cva6_instr_gen_config_c::get_type()); + `uvm_info("CVA6_DV", $sformatf("Overrid done "), UVM_LOW) + endfunction + + virtual function void override_rand_stream(); + `uvm_info("CVA6_DV", $sformatf("Overriding ..."), UVM_LOW) + uvm_factory::get().set_type_override_by_type(riscv_rand_instr_stream::get_type(), + cva6_reg_hazard_stream_c::get_type()); + `uvm_info("CVA6_DV", $sformatf("Overrid done "), UVM_LOW) + endfunction + +endclass : cva6_instr_hazard_test_c diff --git a/verif/env/corev-dv/cva6_instr_test_pkg.sv b/verif/env/corev-dv/cva6_instr_test_pkg.sv new file mode 100644 index 0000000000..6019226563 --- /dev/null +++ b/verif/env/corev-dv/cva6_instr_test_pkg.sv @@ -0,0 +1,28 @@ +// Copyright 2022 Thales DIS design services SAS +// Copyright 2022 OpenHW Group +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Zineb EL KACIMI (zineb.el-kacimi@external.thalesgroup.com) +// ------------------------------------------------------------------------------ // + +package cva6_instr_test_pkg; + + import uvm_pkg::*; + `include "cva6_defines.svh" + import riscv_instr_pkg::*; + import riscv_instr_test_pkg::*; + import cva6_signature_pkg::*; + + `include "cva6_instr_gen_config.sv" + `include "cva6_reg_hazard_stream.sv" + `include "cva6_asm_program_gen.sv" + `include "cva6_instr_base_test.sv" + `include "cva6_instr_hazard_test.sv" + `include "cvxif_custom_instr.sv" + `include "rv32x_instr.sv" + +endpackage : cva6_instr_test_pkg; diff --git a/verif/env/corev-dv/cva6_reg_hazard_stream.sv b/verif/env/corev-dv/cva6_reg_hazard_stream.sv new file mode 100644 index 0000000000..0b4ff473c5 --- /dev/null +++ b/verif/env/corev-dv/cva6_reg_hazard_stream.sv @@ -0,0 +1,62 @@ +// class for hazard instruction stream (RAW) +// that means destination register of previous instruction is the same source register of the current instruction + +class cva6_reg_hazard_stream_c extends riscv_rand_instr_stream; + + `uvm_object_utils(cva6_reg_hazard_stream_c) + + string label; + + function new(string name = ""); + super.new(name); + endfunction + + virtual function void gen_instr(bit no_branch = 1'b0, bit no_load_store = 1'b1, + bit is_debug_program = 1'b0); + riscv_reg_t prev_reg; + cva6_instr_gen_config_c cfg_cva6; + `DV_CHECK_FATAL($cast(cfg_cva6, cfg), "Could not cast cfg into cfg_cva6") + setup_allowed_instr(no_branch, no_load_store); + foreach(instr_list[i]) begin + if (i == 0) begin + randomize_instr(instr_list[i], is_debug_program); + prev_reg = instr_list[i].rd; + end + else if (i >= 1) begin + randomize_instr(instr_list[i], is_debug_program); + if (!instr_list[i].is_compressed) begin + `DV_CHECK_RANDOMIZE_WITH_FATAL(instr_list[i], + if (has_rs1 && cfg_cva6.enable_rdrs1_hazard) { + instr_list[i].rs1 == prev_reg; + } + if (has_rs2 && cfg_cva6.enable_rdrs2_hazard) { + instr_list[i].rs2 == prev_reg; + } + if (cfg_cva6.enable_same_reg) { + instr_list[i].rd == instr_list[i].rs1; + instr_list[i].rs1 == instr_list[i].rs2; + }) + prev_reg = instr_list[i].rd; + end + else begin + `DV_CHECK_RANDOMIZE_WITH_FATAL(instr_list[i], + if (instr_list[i-1].rd inside {[S0:A5]}) { + if (has_rs1 && cfg_cva6.enable_rdrs1_hazard) { + instr_list[i].rs1 == prev_reg; + } + if (has_rs2 && cfg_cva6.enable_rdrs2_hazard) { + instr_list[i].rs2 == prev_reg; + }}) + prev_reg = instr_list[i].rd; + end + end + end + // Do not allow branch instruction as the last instruction because there's no + // forward branch target + while (instr_list[$].category == BRANCH) begin + void'(instr_list.pop_back()); + if (instr_list.size() == 0) break; + end + endfunction + +endclass diff --git a/verif/env/corev-dv/cva6_signature_pkg.sv b/verif/env/corev-dv/cva6_signature_pkg.sv new file mode 100644 index 0000000000..ffe40a5089 --- /dev/null +++ b/verif/env/corev-dv/cva6_signature_pkg.sv @@ -0,0 +1,66 @@ +/* + * Copyright 2019 Google LLC + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +package cva6_signature_pkg; + + // Will be the lowest 8 bits of the data word + typedef enum bit[7:0] { + // Information sent to the core relating its current status. + // Bits [12:8] of the data word will be the core_status_t value + // corresponding to the current core status. + CORE_STATUS, + // Information sent to the core conveying the uvm simulation result. + // Bit [8] of the data word will be the test_result_t value. + TEST_RESULT, + // Sent to the core to indicate a dump of GPRs to testbench. + // Will be followed by 32 writes of registers x0-x32. + WRITE_GPR, + // Sent to the core to indicate a write of a CSR's data. + // Bits [19:8] of the data word will be the CSR address. + // Will be followed by a second write of the actual data from the CSR. + WRITE_CSR + } signature_type_t; + + typedef enum bit[4:0] { + INITIALIZED, + IN_DEBUG_MODE, + IN_MACHINE_MODE, + IN_HYPERVISOR_MODE, + IN_SUPERVISOR_MODE, + IN_USER_MODE, + HANDLING_IRQ, + FINISHED_IRQ, + HANDLING_EXCEPTION, + INSTR_FAULT_EXCEPTION, + ILLEGAL_INSTR_EXCEPTION, + LOAD_FAULT_EXCEPTION, + STORE_FAULT_EXCEPTION, + EBREAK_EXCEPTION, + ECALL_EXCEPTION, + INSTR_MISALIGNED_EXCEPTION, + LD_MISALIGNED_EXCEPTION, + ST_MISALIGNED_EXCEPTION, + INSTR_PAGE_FAULT_EXCEPTION, + LOAD_PAGE_FAULT_EXCEPTION, + STORE_PAGE_FAULT_EXCEPTION + } core_status_t; + + typedef enum bit { + TEST_PASS, + TEST_FAIL + } test_result_t; + +endpackage diff --git a/verif/env/corev-dv/simulator.yaml b/verif/env/corev-dv/simulator.yaml new file mode 100644 index 0000000000..19cee982dc --- /dev/null +++ b/verif/env/corev-dv/simulator.yaml @@ -0,0 +1,39 @@ +# Copyright Google LLC +# Copyright 2022 Thales DIS Design Services SAS +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# SPDX-License-Identifier: Apache-2.0 + +###### This file is based on <cwd>/cva6-simuator.yaml + +- tool: vcs + compile: + cmd: + - "vcs -file <cwd>/dv/vcs.compile.option.f + +incdir+<setting> + +incdir+<user_extension> + -f <cwd>/dv/files.f + -f <cwd>/../env/corev-dv/cva6-files.f + -full64 + -l <out>/compile.log + -LDFLAGS '-Wl,--no-as-needed' + -Mdir=<out>/vcs_simv.csrc + -o <out>/vcs_simv <cmp_opts> <cov_opts> " + cov_opts: > + -cm_dir <out>/test.vdb + sim: + cmd: > + <out>/vcs_simv +vcs+lic+wait gen="true" <sim_opts> +ntb_random_seed=<seed> <cov_opts> + cov_opts: > + -cm_dir <out>/test.vdb -cm_log /dev/null -cm_name test_<seed>_<test_id> diff --git a/verif/env/corev-dv/target/rv32imac/riscv_core_setting.sv b/verif/env/corev-dv/target/rv32imac/riscv_core_setting.sv new file mode 100644 index 0000000000..9732c2433a --- /dev/null +++ b/verif/env/corev-dv/target/rv32imac/riscv_core_setting.sv @@ -0,0 +1,118 @@ +/* + * Copyright 2019 Google LLC + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +//----------------------------------------------------------------------------- +// Processor feature configuration +//----------------------------------------------------------------------------- +// XLEN +parameter int XLEN = 32; + +// Parameter for SATP mode, set to BARE if address translation is not supported +parameter satp_mode_t SATP_MODE = BARE; + +// Supported Privileged mode +privileged_mode_t supported_privileged_mode[] = {MACHINE_MODE}; + +// Unsupported instructions +riscv_instr_name_t unsupported_instr[]; + +// ISA supported by the processor +riscv_instr_group_t supported_isa[$] = {RV32I, RV32M, RV32C, RV32A}; + +// Interrupt mode support +mtvec_mode_t supported_interrupt_mode[$] = {DIRECT, VECTORED}; + +// The number of interrupt vectors to be generated, only used if VECTORED interrupt mode is +// supported +int max_interrupt_vector_num = 16; + +// Physical memory protection support +bit support_pmp = 0; + +// Debug mode support +bit support_debug_mode = 0; + +// Support delegate trap to user mode +bit support_umode_trap = 0; + +// Support sfence.vma instruction +bit support_sfence = 0; + +// Support unaligned load/store +bit support_unaligned_load_store = 1'b1; + +// Parameter for vector extension +parameter int VECTOR_EXTENSION_ENABLE = 0; +parameter int VLEN = 512; +parameter int ELEN = 64; +parameter int SLEN = 64; + +// Number of harts +parameter int NUM_HARTS = 1; + +// ---------------------------------------------------------------------------- +// Previleged CSR implementation +// ---------------------------------------------------------------------------- + +// Implemented previlieged CSR list +`ifdef DSIM +privileged_reg_t implemented_csr[] = { +`else +const privileged_reg_t implemented_csr[] = { +`endif + // Machine mode mode CSR + MVENDORID, // Vendor ID + MARCHID, // Architecture ID + MIMPID, // Implementation ID + MHARTID, // Hardware thread ID + MSTATUS, // Machine status + MISA, // ISA and extensions + MIE, // Machine interrupt-enable register + MTVEC, // Machine trap-handler base address + MCOUNTEREN, // Machine counter enable + MSCRATCH, // Scratch register for machine trap handlers + MEPC, // Machine exception program counter + MCAUSE, // Machine trap cause + MTVAL, // Machine bad address or instruction + MIP // Machine interrupt pending +}; + +// ---------------------------------------------------------------------------- +// Supported interrupt/exception setting, used for functional coverage +// ---------------------------------------------------------------------------- + +`ifdef DSIM +interrupt_cause_t implemented_interrupt[] = { +`else +const interrupt_cause_t implemented_interrupt[] = { +`endif + M_SOFTWARE_INTR, + M_TIMER_INTR, + M_EXTERNAL_INTR +}; + +`ifdef DSIM +exception_cause_t implemented_exception[] = { +`else +const exception_cause_t implemented_exception[] = { +`endif + INSTRUCTION_ACCESS_FAULT, + ILLEGAL_INSTRUCTION, + BREAKPOINT, + LOAD_ADDRESS_MISALIGNED, + LOAD_ACCESS_FAULT, + ECALL_MMODE +}; diff --git a/verif/env/corev-dv/target/rv32imc/riscv_core_setting.sv b/verif/env/corev-dv/target/rv32imc/riscv_core_setting.sv new file mode 100644 index 0000000000..0ebba66baf --- /dev/null +++ b/verif/env/corev-dv/target/rv32imc/riscv_core_setting.sv @@ -0,0 +1,132 @@ +/* + * Copyright 2019 Google LLC + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +//----------------------------------------------------------------------------- +// Processor feature configuration +//----------------------------------------------------------------------------- +// XLEN +parameter int XLEN = 32; + +// Parameter for SATP mode, set to BARE if address translation is not supported +parameter satp_mode_t SATP_MODE = BARE; + +// Supported Privileged mode +privileged_mode_t supported_privileged_mode[] = {MACHINE_MODE}; + +// Unsupported instructions +riscv_instr_name_t unsupported_instr[]; + +// ISA supported by the processor +riscv_instr_group_t supported_isa[$] = {RV32I, RV32M, RV32C, RV32X}; + +// Interrupt mode support +mtvec_mode_t supported_interrupt_mode[$] = {DIRECT, VECTORED}; + +// The number of interrupt vectors to be generated, only used if VECTORED interrupt mode is +// supported +int max_interrupt_vector_num = 16; + +// Physical memory protection support +bit support_pmp = 0; + +// Debug mode support +bit support_debug_mode = 0; + +// Support delegate trap to user mode +bit support_umode_trap = 0; + +// Support sfence.vma instruction +bit support_sfence = 0; + +// Support unaligned load/store +bit support_unaligned_load_store = 1'b1; + +// Parameter for vector extension +parameter int VECTOR_EXTENSION_ENABLE = 0; +parameter int VLEN = 512; +parameter int ELEN = 64; +parameter int SLEN = 64; + +// Number of harts +parameter int NUM_HARTS = 1; + +// ---------------------------------------------------------------------------- +// Previleged CSR implementation +// ---------------------------------------------------------------------------- + +// Implemented previlieged CSR list +`ifdef DSIM +privileged_reg_t implemented_csr[] = { +`else +const privileged_reg_t implemented_csr[] = { +`endif + // Machine mode mode CSR + MVENDORID, // Vendor ID + MARCHID, // Architecture ID + MIMPID, // Implementation ID + MHARTID, // Hardware thread ID + MSTATUS, // Machine status + MISA, // ISA and extensions + MIE, // Machine interrupt-enable register + MTVEC, // Machine trap-handler base address + MCOUNTEREN, // Machine counter enable + MSCRATCH, // Scratch register for machine trap handlers + MEPC, // Machine exception program counter + MCAUSE, // Machine trap cause + MTVAL, // Machine bad address or instruction + MIP // Machine interrupt pending +}; + +// ---------------------------------------------------------------------------- +// Supported interrupt/exception setting, used for functional coverage +// ---------------------------------------------------------------------------- + +`ifdef DSIM +interrupt_cause_t implemented_interrupt[] = { +`else +const interrupt_cause_t implemented_interrupt[] = { +`endif + U_SOFTWARE_INTR, + S_SOFTWARE_INTR, + M_SOFTWARE_INTR, + U_TIMER_INTR, + S_TIMER_INTR, + M_TIMER_INTR, + U_EXTERNAL_INTR, + S_EXTERNAL_INTR, + M_EXTERNAL_INTR +}; + +`ifdef DSIM +exception_cause_t implemented_exception[] = { +`else +const exception_cause_t implemented_exception[] = { +`endif + INSTRUCTION_ADDRESS_MISALIGNED, + INSTRUCTION_ACCESS_FAULT, + ILLEGAL_INSTRUCTION, + BREAKPOINT, + LOAD_ADDRESS_MISALIGNED, + LOAD_ACCESS_FAULT, + STORE_AMO_ADDRESS_MISALIGNED, + STORE_AMO_ACCESS_FAULT, + ECALL_UMODE, + ECALL_SMODE, + ECALL_MMODE, + INSTRUCTION_PAGE_FAULT, + LOAD_PAGE_FAULT, + STORE_AMO_PAGE_FAULT +}; diff --git a/verif/env/corev-dv/target/rv64gc/riscv_core_setting.sv b/verif/env/corev-dv/target/rv64gc/riscv_core_setting.sv new file mode 100644 index 0000000000..386c675712 --- /dev/null +++ b/verif/env/corev-dv/target/rv64gc/riscv_core_setting.sv @@ -0,0 +1,157 @@ +/* + * Copyright 2019 Google LLC + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +//----------------------------------------------------------------------------- +// Processor feature configuration +//----------------------------------------------------------------------------- +// XLEN +parameter int XLEN = 64; + +// Parameter for SATP mode, set to BARE if address translation is not supported +parameter satp_mode_t SATP_MODE = SV39; + +// Supported Privileged mode +privileged_mode_t supported_privileged_mode[] = {USER_MODE, SUPERVISOR_MODE, MACHINE_MODE}; + +// Unsupported instructions +riscv_instr_name_t unsupported_instr[]; + +// ISA supported by the processor +riscv_instr_group_t supported_isa[$] = {RV32I, RV32M, RV64I, RV64M, RV32C, RV64C, RV32A, RV64A, + RV32F, RV64F, RV32D, RV64D, RV32X}; +// Interrupt mode support +mtvec_mode_t supported_interrupt_mode[$] = {DIRECT, VECTORED}; + +// The number of interrupt vectors to be generated, only used if VECTORED interrupt mode is +// supported +int max_interrupt_vector_num = 16; + +// Physical memory protection support +bit support_pmp = 0; + +// Debug mode support +bit support_debug_mode = 0; + +// Support delegate trap to user mode +bit support_umode_trap = 0; + +// Support sfence.vma instruction +bit support_sfence = 1; + +// Support unaligned load/store +bit support_unaligned_load_store = 1'b1; + +// Parameter for vector extension +parameter int VECTOR_EXTENSION_ENABLE = 0; +parameter int VLEN = 512; +parameter int ELEN = 64; +parameter int SLEN = 64; + +// Number of harts +parameter int NUM_HARTS = 1; + +// ---------------------------------------------------------------------------- +// Previleged CSR implementation +// ---------------------------------------------------------------------------- + +// Implemented previlieged CSR list +`ifdef DSIM +privileged_reg_t implemented_csr[] = { +`else +const privileged_reg_t implemented_csr[] = { +`endif + // User mode CSR + USTATUS, // User status + UIE, // User interrupt-enable register + UTVEC, // User trap-handler base address + USCRATCH, // Scratch register for user trap handlers + UEPC, // User exception program counter + UCAUSE, // User trap cause + UTVAL, // User bad address or instruction + UIP, // User interrupt pending + // Supervisor mode CSR + SSTATUS, // Supervisor status + SEDELEG, // Supervisor exception delegation register + SIDELEG, // Supervisor interrupt delegation register + SIE, // Supervisor interrupt-enable register + STVEC, // Supervisor trap-handler base address + SCOUNTEREN, // Supervisor counter enable + SSCRATCH, // Scratch register for supervisor trap handlers + SEPC, // Supervisor exception program counter + SCAUSE, // Supervisor trap cause + STVAL, // Supervisor bad address or instruction + SIP, // Supervisor interrupt pending + SATP, // Supervisor address translation and protection + // Machine mode mode CSR + MVENDORID, // Vendor ID + MARCHID, // Architecture ID + MIMPID, // Implementation ID + MHARTID, // Hardware thread ID + MSTATUS, // Machine status + MISA, // ISA and extensions + MEDELEG, // Machine exception delegation register + MIDELEG, // Machine interrupt delegation register + MIE, // Machine interrupt-enable register + MTVEC, // Machine trap-handler base address + MCOUNTEREN, // Machine counter enable + MSCRATCH, // Scratch register for machine trap handlers + MEPC, // Machine exception program counter + MCAUSE, // Machine trap cause + MTVAL, // Machine bad address or instruction + MIP, // Machine interrupt pending + // Floating point CSR + FCSR // Floating point control and status +}; + +// ---------------------------------------------------------------------------- +// Supported interrupt/exception setting, used for functional coverage +// ---------------------------------------------------------------------------- + +`ifdef DSIM +interrupt_cause_t implemented_interrupt[] = { +`else +const interrupt_cause_t implemented_interrupt[] = { +`endif + U_SOFTWARE_INTR, + S_SOFTWARE_INTR, + M_SOFTWARE_INTR, + U_TIMER_INTR, + S_TIMER_INTR, + M_TIMER_INTR, + U_EXTERNAL_INTR, + S_EXTERNAL_INTR, + M_EXTERNAL_INTR +}; + +`ifdef DSIM +exception_cause_t implemented_exception[] = { +`else +const exception_cause_t implemented_exception[] = { +`endif + INSTRUCTION_ACCESS_FAULT, + ILLEGAL_INSTRUCTION, + BREAKPOINT, + LOAD_ADDRESS_MISALIGNED, + LOAD_ACCESS_FAULT, + STORE_AMO_ADDRESS_MISALIGNED, + STORE_AMO_ACCESS_FAULT, + ECALL_UMODE, + ECALL_SMODE, + ECALL_MMODE, + INSTRUCTION_PAGE_FAULT, + LOAD_PAGE_FAULT, + STORE_AMO_PAGE_FAULT +}; diff --git a/verif/env/corev-dv/user_extension/user_define.h b/verif/env/corev-dv/user_extension/user_define.h new file mode 100644 index 0000000000..e7e3557ff1 --- /dev/null +++ b/verif/env/corev-dv/user_extension/user_define.h @@ -0,0 +1 @@ +# Add user macros, routines in this file diff --git a/verif/env/corev-dv/user_extension/x_extn_user_define.h b/verif/env/corev-dv/user_extension/x_extn_user_define.h new file mode 100644 index 0000000000..885c561f08 --- /dev/null +++ b/verif/env/corev-dv/user_extension/x_extn_user_define.h @@ -0,0 +1,49 @@ +# Copyright 2022 Thales DIS design services SAS +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# ------------------------------------------------------------------------------ # + +# Add user macros, routines in this file + +# Mappings of custom_* mnemonics to .insn pseudo-op of GAS + + +# CUS_ADD rd, rs1, rs2 -> .insn r CUSTOM_3, 0x1, 0x0, rd, rs1, rs2 +.macro cus_add rd, rs1, rs2 + .insn r CUSTOM_3, 0x1, 0x0, \rd, \rs1, \rs2 +.endm + +# CUS_NOP -> .insn r CUSTOM_3, 0x0, 0x0, x0, x0, x0 +.macro cus_nop + .insn r CUSTOM_3, 0x0, 0x0, x0, x0, x0 +.endm + +# CUS_ADD_RS3 rd, rs1, rs2, rs3 -> .insn r CUSTOM_3, 0x0, 0x1, rd, rs1, rs2, rs3 +.macro cus_add_rs3 rd, rs1, rs2, rs3 + .insn r CUSTOM_3, 0x0, 0x1, \rd, \rs1, \rs2, \rs3 +.endm + +# CUS_U_ADD rd, rs1, rs2 -> .insn r CUSTOM_3, 0x0, 0x2, rd, rs1, rs2 +.macro cus_u_add rd, rs1, rs2 + .insn r CUSTOM_3, 0x0, 0x2, \rd, \rs1, \rs2 +.endm + +# CUS_S_ADD rd, rs1, rs2 -> .insn r CUSTOM_3, 0x0, 0x6, rd, rs1, rs2 +.macro cus_s_add rd, rs1, rs2 + .insn r CUSTOM_3, 0x0, 0x6, \rd, \rs1, \rs2 +.endm + +# CUS_ADD_MULTI rd, rs1, rs2 -> .insn r CUSTOM_3, 0x0, 0x8, rd, rs1, rs2 +.macro cus_add_multi rd, rs1, rs2 + .insn r CUSTOM_3, 0x0, 0x8, \rd, \rs1, \rs2 +.endm + +# CUS_EXC rs1 -> .insn r CUSTOM_3, 0x2, 0x60, x0, rs1, x0 +.macro cus_exc rs1 + .insn r CUSTOM_3, 0x2, 0x60, x0, \rs1, x0 +.endm + diff --git a/verif/env/uvme/cov/uvme_cva6_cov_model.sv b/verif/env/uvme/cov/uvme_cva6_cov_model.sv new file mode 100644 index 0000000000..599145f214 --- /dev/null +++ b/verif/env/uvme/cov/uvme_cva6_cov_model.sv @@ -0,0 +1,140 @@ +// +// Copyright 2020 OpenHW Group +// Copyright 2021 Thales DIS Design Services SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// + + +`ifndef __UVME_CVA6_COV_MODEL_SV__ +`define __UVME_CVA6_COV_MODEL_SV__ + + +/** + * Component encapsulating CVA6 environment's functional coverage model. + */ +class uvme_cva6_cov_model_c extends uvm_component; + + // Objects + uvme_cva6_cfg_c cfg; + uvme_cva6_cntxt_c cntxt; + + // Components + uvme_cvxif_covg_c cvxif_covg; + + `uvm_component_utils_begin(uvme_cva6_cov_model_c) + `uvm_field_object(cfg , UVM_DEFAULT) + `uvm_field_object(cntxt, UVM_DEFAULT) + `uvm_component_utils_end + + /** + * Default constructor. + */ + extern function new(string name="uvme_cva6_cov_model", uvm_component parent=null); + + /** + * Ensures cfg & cntxt handles are not null. + */ + extern virtual function void build_phase(uvm_phase phase); + + /** + * Describe uvme_cva6_cov_model_c::run_phase() + */ + extern virtual task run_phase(uvm_phase phase); + + /** + * TODO Describe uvme_cva6_cov_model_c::sample_cfg() + */ + extern virtual function void sample_cfg(); + + /** + * TODO Describe uvme_cva6_cov_model_c::sample_cntxt() + */ + extern virtual function void sample_cntxt(); + + // TODO Add coverage functions to uvme_cva6_cov_model_c + +endclass : uvme_cva6_cov_model_c + + +function uvme_cva6_cov_model_c::new(string name="uvme_cva6_cov_model", uvm_component parent=null); + + super.new(name, parent); + +endfunction : new + +function void uvme_cva6_cov_model_c::build_phase(uvm_phase phase); + + super.build_phase(phase); + + void'(uvm_config_db#(uvme_cva6_cfg_c)::get(this, "", "cfg", cfg)); + if (!cfg) begin + `uvm_fatal("CFG", "Configuration handle is null") + end + + void'(uvm_config_db#(uvme_cva6_cntxt_c)::get(this, "", "cntxt", cntxt)); + if (!cntxt) begin + `uvm_fatal("CNTXT", "Context handle is null") + end + + cvxif_covg = uvme_cvxif_covg_c::type_id::create("cvxif_covg", this); + uvm_config_db#(uvme_cva6_cfg_c)::set(this, "cvxif_covg", "cfg", cfg); + uvm_config_db#(uvme_cva6_cntxt_c)::set(this, "cvxif_covg", "cntxt", cntxt); + +endfunction : build_phase + + +task uvme_cva6_cov_model_c::run_phase(uvm_phase phase); + + super.run_phase(phase); + + fork + // Configuration + forever begin + cntxt.sample_cfg_e.wait_trigger(); + sample_cfg(); + end + + // Context + forever begin + cntxt.sample_cntxt_e.wait_trigger(); + sample_cntxt(); + end + + // TODO Implement uvme_cva6_cov_model_c::run_phase() + // Ex: forever begin + // debug_fifo.get(debug_trn); + // sample_debug(); + // end + join_none + +endtask : run_phase + + +function void uvme_cva6_cov_model_c::sample_cfg(); + + // TODO Implement uvme_cva6_cov_model_c::sample_cfg(); + // Ex: cva6_cfg_cg.sample(); + +endfunction : sample_cfg + + +function void uvme_cva6_cov_model_c::sample_cntxt(); + + // TODO Implement uvme_cva6_cov_model_c::sample_cntxt(); + // Ex: cva6_cntxt_cg.sample(); + +endfunction : sample_cntxt + + +`endif // __UVME_CVA6_COV_MODEL_SV__ diff --git a/verif/env/uvme/cov/uvme_cvxif_covg.sv b/verif/env/uvme/cov/uvme_cvxif_covg.sv new file mode 100644 index 0000000000..6e4b0f4fc9 --- /dev/null +++ b/verif/env/uvme/cov/uvme_cvxif_covg.sv @@ -0,0 +1,293 @@ +// +// Copyright 2020 OpenHW Group +// Copyright 2021 Thales DIS Design Services SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 + +covergroup cg_executed( + string name, + bit seq_cus_instr_x2_enabled + ) with function + sample(uvma_cvxif_req_item_c req_item, + uvma_cvxif_req_item_c prev_req_item); + + option.per_instance = 1; + option.name = name; + + cp_instr : coverpoint req_item.issue_req.instr { + wildcard bins CUS_ADD = {32'b0000000??????????001?????1111011}; + wildcard bins CUS_ADD_RS3 = {32'b?????01??????????000?????1111011}; + wildcard bins CUS_ADD_MULTI = {32'b0001000??????????000?????1111011}; + wildcard bins CUS_U_ADD = {32'b0000010??????????000?????1111011}; + wildcard bins CUS_S_ADD = {32'b0000110??????????000?????1111011}; + wildcard bins CUS_NOP = {32'b00000000000000000000000001111011}; + wildcard bins CUS_EXC = {32'b110000000000?????010000001111011}; + } + + cp_prev_instr : coverpoint prev_req_item.issue_req.instr iff (prev_req_item != null) { + ignore_bins IGN_X2_OFF = {[0:$]} iff (!seq_cus_instr_x2_enabled); + wildcard bins CUS_ADD = {32'b0000000??????????001?????1111011}; + wildcard bins CUS_ADD_RS3 = {32'b?????01??????????000?????1111011}; + wildcard bins CUS_ADD_MULTI = {32'b0001000??????????000?????1111011}; + wildcard bins CUS_U_ADD = {32'b0000010??????????000?????1111011}; + wildcard bins CUS_S_ADD = {32'b0000110??????????000?????1111011}; + wildcard bins CUS_NOP = {32'b00000000000000000000000001111011}; + wildcard bins CUS_EXC = {32'b110000000000?????010000001111011}; + } + + cross_seq_cus_instr_x2 : cross cp_instr, cp_prev_instr; + +endgroup: cg_executed + +covergroup cg_cus_add_instr( + string name, + bit reg_cus_crosses_enabled, + bit rs3_valid + ) with function sample(uvma_cvxif_req_item_c req_item); + + option.per_instance = 1; + option.name = name; + + cp_rd : coverpoint req_item.issue_req.instr[11:7] { + bins RD[] = {[0:31]}; + } + + cp_rs1 : coverpoint req_item.issue_req.instr[19:15] { + bins RS1[] = {[0:31]}; + } + + cp_rs2 : coverpoint req_item.issue_req.instr[24:20] { + bins RS2[] = {[0:31]}; + } + + cp_rs3 : coverpoint req_item.issue_req.instr[31:27] { + ignore_bins IGN_RS3[] = {[0:31]} iff (!rs3_valid); + bins RS3[] = {[0:31]}; + } + + cross_rd_rs1 : cross cp_rd, cp_rs1 { + ignore_bins IGN_OFF = cross_rd_rs1 iff (!reg_cus_crosses_enabled); + } + + cross_rd_rs2 : cross cp_rd, cp_rs2 { + ignore_bins IGN_OFF = cross_rd_rs2 iff (!reg_cus_crosses_enabled); + } + + cross_rd_rs3 : cross cp_rd, cp_rs3 { + ignore_bins IGN_OFF = cross_rd_rs3 iff (!reg_cus_crosses_enabled || !rs3_valid); + } + + `CVXIF_CP_BITWISE(cp_rs1_toggle, req_item.issue_req.rs[0], 1) + `CVXIF_CP_BITWISE(cp_rs2_toggle, req_item.issue_req.rs[1], 1) + `CVXIF_CP_BITWISE(cp_rs3_toggle, req_item.issue_req.rs[2], rs3_valid) //TODO : fix need more filtring + +endgroup: cg_cus_add_instr + +covergroup cg_cus_instr( + string name + ) with function sample(uvma_cvxif_req_item_c req_item); + + option.per_instance = 1; + option.name = name; + + cp_rs1 : coverpoint req_item.issue_req.instr[19:15] { + bins RS1[] = {[0:31]}; + } + +endgroup: cg_cus_instr + +class uvme_cvxif_covg_c extends uvm_component; + + /* + * Class members + */ + // Objects + uvme_cva6_cfg_c cfg ; + uvme_cva6_cntxt_c cntxt ; + + uvma_cvxif_req_item_c req_item; + uvma_cvxif_req_item_c prev_req_item; + + // TLM + uvm_tlm_analysis_fifo#(uvma_cvxif_req_item_c ) req_item_fifo; + + `uvm_component_utils_begin(uvme_cvxif_covg_c) + `uvm_field_object(cfg , UVM_DEFAULT) + `uvm_field_object(cntxt, UVM_DEFAULT) + `uvm_component_utils_end + + // Covergroups + //ADD INSTRUCTIONS + cg_cus_add_instr cus_add_cg; + cg_cus_add_instr cus_add_rs3_cg; + cg_cus_add_instr cus_add_multi_cg; + cg_cus_add_instr cus_add_u_cg; + cg_cus_add_instr cus_add_s_cg; + cg_cus_instr cus_exc_cg; + + //Sequential instruction + cg_executed cus_seq_cg; + + extern function new(string name = "cvxif_covg", uvm_component parent = null); + extern function void build_phase(uvm_phase phase); + extern task run_phase(uvm_phase phase); + + extern task sample_cvxif_req(uvma_cvxif_req_item_c req_item); + +endclass : uvme_cvxif_covg_c + +function uvme_cvxif_covg_c::new(string name = "cvxif_covg", uvm_component parent = null); + + super.new(name, parent); + +endfunction : new + +function void uvme_cvxif_covg_c::build_phase(uvm_phase phase); + + super.build_phase(phase); + + void'(uvm_config_db#(uvme_cva6_cfg_c)::get(this, "", "cfg", cfg)); + if (!cfg) begin + `uvm_fatal("CFG", "Configuration handle is null") + end + + void'(uvm_config_db#(uvme_cva6_cntxt_c)::get(this, "", "cntxt", cntxt)); + if (!cntxt) begin + `uvm_fatal("CNTXT", "Context handle is null") + end + + cus_add_cg = new("cus_add_cg", + .reg_cus_crosses_enabled(cfg.cvxif_cfg.reg_cus_crosses_enabled), + .rs3_valid(0)); + cus_add_rs3_cg = new("cus_add_rs3_cg", + .reg_cus_crosses_enabled(cfg.cvxif_cfg.reg_cus_crosses_enabled), + .rs3_valid(1)); + cus_add_multi_cg = new("cus_add_multi_cg", + .reg_cus_crosses_enabled(cfg.cvxif_cfg.reg_cus_crosses_enabled), + .rs3_valid(0)); + cus_add_u_cg = new("cus_add_u_cg", + .reg_cus_crosses_enabled(cfg.cvxif_cfg.reg_cus_crosses_enabled), + .rs3_valid(0)); + cus_add_s_cg = new("cus_add_s_cg", + .reg_cus_crosses_enabled(cfg.cvxif_cfg.reg_cus_crosses_enabled), + .rs3_valid(0)); + cus_exc_cg = new("cus_exc_cg"); + + cus_seq_cg = new("cus_seq_cg", + .seq_cus_instr_x2_enabled(cfg.cvxif_cfg.seq_cus_instr_x2_enabled)); + + req_item_fifo = new("req_item_fifo" , this); + +endfunction : build_phase + +task uvme_cvxif_covg_c::run_phase(uvm_phase phase); + + super.run_phase(phase); + + `uvm_info("CVXIFCOVG", "The CVXIF coverage model is running", UVM_LOW); + forever begin + req_item_fifo.get(req_item); + sample_cvxif_req(req_item); + end + +endtask : run_phase + +task uvme_cvxif_covg_c::sample_cvxif_req(uvma_cvxif_req_item_c req_item); + + logic have_sample = 0; + bit [6:0] opcode = req_item.issue_req.instr [6:0]; + bit [6:0] custom3 = 7'b1111011; + bit [6:0] func7 = req_item.issue_req.instr [31:25]; + bit [1:0] func2 = req_item.issue_req.instr [26:25]; + bit [2:0] func3 = req_item.issue_req.instr [14:12]; + bit [4:0] rd = req_item.issue_req.instr [11:7]; + bit [4:0] rs1 = req_item.issue_req.instr [19:15]; + bit [4:0] rs2 = req_item.issue_req.instr [24:20]; + + if (opcode == custom3) begin + if (func3 == 3'b000) begin + if (func7 == 7'b0000000 && rd != 0) begin + cus_add_cg.sample(req_item); + cus_seq_cg.sample(req_item, + prev_req_item); + // Move instructions down the pipeline + prev_req_item = req_item; + have_sample = 1; + end + if (func7 == 7'b0001000) begin + cus_add_multi_cg.sample(req_item); + cus_seq_cg.sample(req_item, + prev_req_item); + // Move instructions down the pipeline + prev_req_item = req_item; + have_sample = 1; + end + if (func2 == 2'b01) begin + cus_add_rs3_cg.sample(req_item); + cus_seq_cg.sample(req_item, + prev_req_item); + // Move instructions down the pipeline + prev_req_item = req_item; + have_sample = 1; + end + if (func7 == 7'b0000010) begin + cus_add_u_cg.sample(req_item); + cus_seq_cg.sample(req_item, + prev_req_item); + // Move instructions down the pipeline + prev_req_item = req_item; + have_sample = 1; + end + if (func7 == 7'b0000110) begin + cus_add_s_cg.sample(req_item); + cus_seq_cg.sample(req_item, + prev_req_item); + // Move instructions down the pipeline + prev_req_item = req_item; + have_sample = 1; + end + if (func7 == 7'b0000000 && rd == 0 && rs1 == 0 && rs2 == 0) begin + cus_seq_cg.sample(req_item, + prev_req_item); + // Move instructions down the pipeline + prev_req_item = req_item; + have_sample = 1; + end + end + if (func3 == 3'b001) begin + if (func7 == 7'b0000000) begin + cus_add_cg.sample(req_item); + cus_seq_cg.sample(req_item, + prev_req_item); + // Move instructions down the pipeline + prev_req_item = req_item; + have_sample = 1; + end + end + if (func3 == 3'b010 && rd == 0 && rs2 == 0) begin + if (func7 == 7'b1100000) begin + cus_exc_cg.sample(req_item); + cus_seq_cg.sample(req_item, + prev_req_item); + // Move instructions down the pipeline + prev_req_item = req_item; + have_sample = 1; + end + end + end + if (!have_sample) `uvm_warning("CVXIF", $sformatf("Could not sample instruction: %b", req_item.issue_req.instr)); + +endtask : sample_cvxif_req + diff --git a/verif/env/uvme/cvxif_vseq/custom_instruction.rst b/verif/env/uvme/cvxif_vseq/custom_instruction.rst new file mode 100644 index 0000000000..ca973d2600 --- /dev/null +++ b/verif/env/uvme/cvxif_vseq/custom_instruction.rst @@ -0,0 +1,100 @@ +.. + Copyright (c) 2023 OpenHW Group + + Copyright (c) 2023 Thales DIS design services SAS + + + SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + +.. + +Custom Instruction to challenge CV-X-IF protocol +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +This section describes some custom instruction, for stress or challenge the CV-X-IF protocol for the 3 implemented interfaces, it's just to interact with the cvxif agent. +All instructions use opcode `CUSTOM_3`(0x7b, 0b111_1011). + +- **CUS_ADD**: Custom Add + + **Format**: cus_add rd, rs1, rs2 -> |0000000|rs2|rs1|001|rd|111_1011| + + **Description**: add register rs1 to rs2, and store the result in rd (works for all privilege modes). + + **Pseudocode**: x[rd] = x[rs1] + x[rs2] + + **Invalid values**: NONE + + **Exception raised**: Illegal instruction exception is raised if rs_valid != 2'b11 && rs_valid != 3'b111. + +- **CUS_NOP**: Custom No Operation + + **Format**: cus_nop -> |0000000000000000000000000|111_1011| + + **Description**: do nothing, it's just a hint instruction. + + **Pseudocode**: cus_nop + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **CUS_ADD_RS3**: Custom Add + + **Format**: cus_add_rs3 rd, rs1, rs2, rs3 -> |rs3|01|rs2|rs1|000|rd|111_1011| + + **Description**: add register rs1 to rs2 then the result to rs3, and store the result in register rd (works for all privilege modes). + + **Pseudocode**: x[rd] = x[rs1] + x[rs2] + x[rs3] + + **Invalid values**: NONE + + **Exception raised**: Illegal instruction exception is raised if rs_valid != 3'b111. + +- **CUS_S_ADD**: Custom Supervisor Add + + **Format**: add rd, rs1, rs2 -> |0000110|rs2|rs1|000|rd|111_1011| + + **Description**: add register rs1 to rs2, and store the result in register rd (works only in Supervisor mode). + + **Pseudocode**: x[rd] = x[rs1] + x[rs2] + + **Invalid values**: NONE + + **Exception raised**: Illegal instruction exception is raised if the privilege mode isn't Supervisor mode, or rs_valid != 2'b11 && rs_valid != 3'b111. + +- **CUS_U_ADD**: Custom User Add + + **Format**: add rd, rs1, rs2 -> |0000010|rs2|rs1|000|rd|111_1011| + + **Description**: add register rs1 to rs2, and store the result in register rd (works only in User mode). + + **Pseudocode**: x[rd] = x[rs1] + x[rs2] + + **Invalid values**: NONE + + **Exception raised**: Illegal instruction exception is raised if the privilege mode isn't User mode, or rs_valid != 2'b11 && rs_valid != 3'b111. + +- **CUS_ADD_MULTI**: Custom Multicycle Add + + **Format**: addi rd, rs1, rs2 -> |0001000|rs2|rs1|000|rd|111_1011| + + **Description**: add register rs1 to rs2, and store the result in rd (works for all privilege mode). + + **Pseudocode**: x[rd] = x[rs1] + x[rs2] + + **Invalid values**: NONE + + **Exception raised**: Illegal instruction exception is raised if rs_valid != 2'b11 && rs_valid != 3'b111. + +- **CUS_EXC**: Custom Exception + + **Format**: cus_exc rs1 -> |1100000|00000|rs1|010|00000|111_1011| + + **Description**: raise an exception. + + **Pseudocode**: mcause[5:0] = rs1 + + **Invalid values**: NONE + + **Exception raised**: raise an exception based on the rs1 register address. + +When a CV-X-IF exception is raised, mcause[5:0] of the corresponding CORE-V hart is assumed set to exccode[5:0] of CV-X-IF. diff --git a/verif/env/uvme/cvxif_vseq/uvme_cvxif_base_vseq.sv b/verif/env/uvme/cvxif_vseq/uvme_cvxif_base_vseq.sv new file mode 100644 index 0000000000..cb47ecc3db --- /dev/null +++ b/verif/env/uvme/cvxif_vseq/uvme_cvxif_base_vseq.sv @@ -0,0 +1,95 @@ +// Copyright 2021 Thales DIS design services SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Zineb EL KACIMI (zineb.el-kacimi@external.thalesgroup.com) + + +`ifndef __UVME_CVXIF_BASE_VSEQ_SV__ +`define __UVME_CVXIF_BASE_VSEQ_SV__ + + +class uvme_cvxif_base_vseq_c extends uvm_sequence #(uvma_cvxif_resp_item_c); + + `uvm_object_utils (uvme_cvxif_base_vseq_c) + `uvm_declare_p_sequencer (uvma_cvxif_vsqr_c) + + uvma_cvxif_resp_item_c resp_item; + uvma_cvxif_req_item_c req_item; + + uvma_cvxif_cfg_c cfg; + + string info_tag = "CVXIF_BASE_VSEQ"; + + extern function new(string name="uvme_cvxif_base_vseq"); + + extern virtual task pre_body(); + + extern function string decode(input logic [31:0] instr); + +endclass + +function uvme_cvxif_base_vseq_c::new(string name="uvme_cvxif_base_vseq"); + + super.new(name); + +endfunction : new + +task uvme_cvxif_base_vseq_c::pre_body(); + + req_item = uvma_cvxif_req_item_c::type_id::create("req_item"); + resp_item = uvma_cvxif_resp_item_c::type_id::create("resp_item"); + + cfg = p_sequencer.cfg; + +endtask + +function string uvme_cvxif_base_vseq_c::decode(input logic [31:0] instr); + + bit [6:0] opcode = instr [6:0]; + bit [6:0] custom3 = 7'b1111011; + bit [6:0] func7 = instr [31:25]; + bit [1:0] func2 = instr [26:25]; + bit [2:0] func3 = instr [14:12]; + bit [4:0] rd = instr [11:7]; + bit [4:0] rs1 = instr [19:15]; + bit [4:0] rs2 = instr [24:20]; + + if (opcode == custom3) begin + if (func3 == 3'b000) begin + if (func7 == 7'b0001000) begin + return ("CUS_ADD_MULTI"); + end + if (func2 == 2'b01) begin + return ("CUS_ADD_RS3"); + end + if (func7 == 7'b0000010) begin + return ("CUS_U_ADD"); + end + if (func7 == 7'b0000110) begin + return ("CUS_S_ADD"); + end + if (func7 == 7'b0000000 && rd == 0 && rs1 == 0 && rs2 == 0) begin + return ("CUS_NOP"); + end + end + if (func3 == 3'b001) begin + if (func7 == 7'b0000000) begin + return ("CUS_ADD"); + end + end + if (func3 == 3'b010 && rd == 0 && rs2 == 0) begin + if (func7 == 7'b1100000) begin + return ("CUS_EXC"); + end + end + end + return ("ILLEGAL"); + +endfunction + + +`endif // __UVME_CVXIF_BASE_VSEQ_SV__ diff --git a/verif/env/uvme/cvxif_vseq/uvme_cvxif_vseq.sv b/verif/env/uvme/cvxif_vseq/uvme_cvxif_vseq.sv new file mode 100644 index 0000000000..a253ad7ca6 --- /dev/null +++ b/verif/env/uvme/cvxif_vseq/uvme_cvxif_vseq.sv @@ -0,0 +1,288 @@ +// Copyright 2021 Thales DIS design services SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Zineb EL KACIMI (zineb.el-kacimi@external.thalesgroup.com) + +`ifndef __UVME_CVXIF_VSEQ_SV__ +`define __UVME_CVXIF_VSEQ_SV__ + + +class uvme_cvxif_vseq_c extends uvme_cvxif_base_vseq_c#(uvma_cvxif_resp_item_c); + + `uvm_object_utils (uvme_cvxif_vseq_c) + `uvm_declare_p_sequencer (uvma_cvxif_vsqr_c) + + string info_tag = "CVXIF_VSEQ_RESP"; + string instr; + + /** + * Default constructor. + */ + extern function new(string name="uvme_cvxif_vseq"); + + /** + * Send the Sequence Response to the Sequencer. + */ + extern task send_resp(uvma_cvxif_resp_item_c resp); + + /** + * Default response in case of illegal/inaccepted instruction. + * Or in case of an invalid issue_req + */ + extern task do_default(); + + /** + * Generate an issue response depending on received request + */ + extern task do_issue_resp(); + + /** + * Generate the result response independent of instruction received + */ + extern task do_result_resp(); + + /** + * Generate the result response depending on instruction received + */ + extern task do_instr_result(); + + /** + * Main sequence body + */ + extern virtual task body(); + +endclass + +task uvme_cvxif_vseq_c::body(); + + forever begin + // wait for a transaction request (get is blocking) + `uvm_info(info_tag, $sformatf("Waiting for the transaction request from monitor"), UVM_HIGH); + p_sequencer.mm_req_fifo.get(req_item); + + //Decode the instruction received + instr = decode(req_item.issue_req.instr); + + // generate response based on observed request, e.g: + if (instr == "") begin + do_default(); + end + else begin + if (req_item.issue_valid && req_item.issue_ready) begin + //issue_resp + do_issue_resp(); + //result_resp + do_result_resp(); + //send resp to sqr + send_resp(resp_item); + end + end + end + +endtask + +function uvme_cvxif_vseq_c::new(string name="uvme_cvxif_vseq"); + + super.new(name); + +endfunction : new + +task uvme_cvxif_vseq_c::do_default(); + + resp_item.issue_resp.accept=0; + resp_item.issue_resp.writeback=0; + resp_item.issue_resp.dualwrite=0; + resp_item.issue_resp.dualread=0; + resp_item.issue_resp.exc=0; + resp_item.result_valid=0; + resp_item.result.id=0; + resp_item.result.exc=0; + resp_item.result.data=0; + resp_item.result.rd=0; + resp_item.result.we=0; + resp_item.result.exccode=0; + `uvm_info(info_tag, $sformatf("Sending default sequence response to sqr, accept = %d, result_valid = %d", resp_item.issue_resp.accept, resp_item.result_valid), UVM_HIGH); + send_resp(resp_item); + +endtask + +task uvme_cvxif_vseq_c::do_issue_resp(); + + resp_item.issue_resp.dualwrite = 0; + resp_item.issue_resp.dualread = 0; + resp_item.issue_resp.exc = 0; + case (instr) inside + "CUS_ADD", "CUS_ADD_MULTI" : begin + if (req_item.issue_req.rs_valid == 2'b11 || req_item.issue_req.rs_valid == 3'b111) begin + resp_item.issue_resp.writeback = 1; + resp_item.issue_resp.accept = 1; + end + end + "CUS_ADD_RS3" : begin + if (req_item.issue_req.rs_valid == 3'b111) begin + resp_item.issue_resp.writeback = 1; + resp_item.issue_resp.accept = 1; + end + else begin + resp_item.issue_resp.writeback = 0; + resp_item.issue_resp.accept = 1; + resp_item.issue_resp.exc = 1; + end + end + "CUS_NOP" : begin + resp_item.issue_resp.writeback = 0; + resp_item.issue_resp.accept = 1; + end + "CUS_EXC" : begin + resp_item.issue_resp.writeback = 0; + resp_item.issue_resp.accept = 1; + resp_item.issue_resp.exc = 1; + end + "CUS_U_ADD" : begin + if (req_item.issue_req.mode == PRIV_LVL_U && req_item.issue_req.rs_valid == 2'b11 || req_item.issue_req.rs_valid == 3'b111) begin + resp_item.issue_resp.writeback = 1; + resp_item.issue_resp.accept = 1; + end + else begin + resp_item.issue_resp.writeback = 0; + resp_item.issue_resp.accept = 1; + resp_item.issue_resp.exc = 1; + end + end + "CUS_S_ADD" : begin + if (req_item.issue_req.mode == PRIV_LVL_S && req_item.issue_req.rs_valid == 2'b11 || req_item.issue_req.rs_valid == 3'b111) begin + resp_item.issue_resp.writeback = 1; + resp_item.issue_resp.accept = 1; + end + else begin + resp_item.issue_resp.writeback = 0; + resp_item.issue_resp.accept = 1; + resp_item.issue_resp.exc = 1; + end + end + "ILLEGAL" : begin + resp_item.issue_resp.writeback = 0; + resp_item.issue_resp.accept = 1; + resp_item.issue_resp.exc = 1; + end + endcase + `uvm_info(info_tag, $sformatf("instr = %s", instr), UVM_LOW); + `uvm_info(info_tag, $sformatf("Response : accept = %h writeback = %h dualwrite = %h dualread = %h exc = %h", + resp_item.issue_resp.accept, resp_item.issue_resp.writeback, resp_item.issue_resp.dualwrite, resp_item.issue_resp.dualread, resp_item.issue_resp.exc), UVM_LOW); + +endtask + +task uvme_cvxif_vseq_c::do_result_resp(); + + //result_resp + if (!req_item.commit_req.commit_kill && req_item.commit_valid) begin + resp_item.result_valid = 1; + resp_item.result.id = req_item.commit_req.id; + resp_item.result.rd = req_item.issue_req.instr[11:7]; + resp_item.result.we = resp_item.issue_resp.writeback; + resp_item.result.data = 0; + resp_item.result_ready = req_item.result_ready; + do_instr_result(); + if (cfg.instr_delayed) begin + cfg.randomize(rnd_delay); + resp_item.rnd_delay = cfg.rnd_delay; + end + else begin + resp_item.rnd_delay = 0; + end + end + else begin + resp_item.result_valid = 0; + resp_item.result.id = 0; + resp_item.result.exc = 0; + resp_item.result.data = 0; + resp_item.result.rd = 0; + resp_item.result.we = 0; + resp_item.result.exccode = 0; + resp_item.rnd_delay = 0; + end + +endtask + +task uvme_cvxif_vseq_c::do_instr_result(); + + //result response depend on instruction + resp_item.result.exc = 0; + resp_item.result.exccode = 0; + cfg.instr_delayed = 0; + case (instr) + "CUS_ADD": begin + if (req_item.issue_req.rs_valid == 2'b11 || req_item.issue_req.rs_valid == 3'b111) + resp_item.result.data = req_item.issue_req.rs[0] + req_item.issue_req.rs[1]; + else begin + resp_item.result.exc = 1; + resp_item.result.exccode[5:0] = 6'b000010; //Exception Illegal instruction + `uvm_info(info_tag, $sformatf("Exception Illegal instruction -> EXCCODE: %d", resp_item.result.exccode), UVM_LOW); + end + end + "CUS_ADD_MULTI": begin + if (req_item.issue_req.rs_valid == 2'b11 || req_item.issue_req.rs_valid == 3'b111) begin + resp_item.result.data = req_item.issue_req.rs[0] + req_item.issue_req.rs[1]; + cfg.instr_delayed = 1; + end + else begin + resp_item.result.exc = 1; + resp_item.result.exccode[5:0] = 6'b000010; //Exception Illegal instruction + `uvm_info(info_tag, $sformatf("Exception Illegal instruction -> EXCCODE: %d", resp_item.result.exccode), UVM_LOW); + end + end + "CUS_EXC": begin + resp_item.result.exc = 1; + resp_item.result.exccode[4:0] = req_item.issue_req.instr[19:15]; + resp_item.result.exccode[5] = 1'b0; + `uvm_info(info_tag, $sformatf("EXCCODE: %d", resp_item.result.exccode), UVM_LOW); + end + "CUS_ADD_RS3": begin + if (req_item.issue_req.rs_valid == 3'b111) + resp_item.result.data = req_item.issue_req.rs[0] + req_item.issue_req.rs[1] + req_item.issue_req.rs[2]; + else begin + resp_item.result.exc = 1; + resp_item.result.exccode[5:0] = 6'b000010; //Exception Illegal instruction + `uvm_info(info_tag, $sformatf("Exception Illegal instruction -> EXCCODE: %d", resp_item.result.exccode), UVM_LOW); + end + end + "CUS_U_ADD": begin + if (req_item.issue_req.mode == PRIV_LVL_U && req_item.issue_req.rs_valid == 2'b11 || req_item.issue_req.rs_valid == 3'b111) + resp_item.result.data = req_item.issue_req.rs[0] + req_item.issue_req.rs[1]; + else begin + resp_item.result.exc = 1; + resp_item.result.exccode[5:0] = 6'b000010; //Exception Illegal instruction + `uvm_info(info_tag, $sformatf("Exception Illegal instruction -> EXCCODE: %d", resp_item.result.exccode), UVM_LOW); + end + end + "CUS_S_ADD": begin + if (req_item.issue_req.mode == PRIV_LVL_S && req_item.issue_req.rs_valid == 2'b11 || req_item.issue_req.rs_valid == 3'b111) + resp_item.result.data = req_item.issue_req.rs[0] + req_item.issue_req.rs[1]; + else begin + resp_item.result.exc = 1; + resp_item.result.exccode[5:0] = 6'b000010; //Exception Illegal instruction + `uvm_info(info_tag, $sformatf("Exception Illegal instruction -> EXCCODE: %d", resp_item.result.exccode), UVM_LOW); + end + end + "ILLEGAL": begin + resp_item.result.exc = 1; + resp_item.result.exccode[5:0] = 6'b000010; //Exception Illegal instruction + `uvm_info(info_tag, $sformatf("Exception Illegal instruction -> EXCCODE: %d", resp_item.result.exccode), UVM_LOW); + end + endcase + +endtask + +task uvme_cvxif_vseq_c::send_resp(uvma_cvxif_resp_item_c resp); + + resp_item.set_sequencer(p_sequencer); + `uvm_send(resp_item); + +endtask : send_resp + + +`endif diff --git a/verif/env/uvme/uvma_cva6_core_cntrl_agent.sv b/verif/env/uvme/uvma_cva6_core_cntrl_agent.sv new file mode 100644 index 0000000000..465a238e46 --- /dev/null +++ b/verif/env/uvme/uvma_cva6_core_cntrl_agent.sv @@ -0,0 +1,114 @@ +// Copyright 2023 OpenHW Group +// Copyright 2023 Datum Technology Corporation +// Copyright 2023 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// + + +`ifndef __UVMA_CVA6_CORE_CNTRL_AGENT_SV__ +`define __UVMA_CVA6_CORE_CNTRL_AGENT_SV__ + +/** + * Core control agent defined for the CVA6 + */ +class uvma_cva6_core_cntrl_agent_c extends uvma_core_cntrl_agent_c; + + + string log_tag = "CVA6CORECTRLAGT"; + + `uvm_component_utils_begin(uvma_cva6_core_cntrl_agent_c) + `uvm_component_utils_end + + /** + * Default constructor. + */ + extern function new(string name="uvma_cva6_core_cntrl_agent", uvm_component parent=null); + + /** + * Uses uvm_config_db to retrieve cntxt and hand out to sub-components. + */ + extern virtual function void get_and_set_cntxt(); + + /** + * Uses uvm_config_db to retrieve the Virtual Interface (vif) associated with this + * agent. + */ + extern virtual function void retrieve_vif(); + + /** + * Spawn active sequnces + */ + extern virtual task run_phase(uvm_phase phase); + + /** + * Spawn fetch enable control sequence + */ + extern virtual task start_fetch_toggle_seq(); + +endclass : uvma_cva6_core_cntrl_agent_c + +function uvma_cva6_core_cntrl_agent_c::new(string name="uvma_cva6_core_cntrl_agent", uvm_component parent=null); + + super.new(name, parent); + + set_inst_override_by_type("driver", uvma_core_cntrl_drv_c::get_type(), uvma_cva6_core_cntrl_drv_c::get_type()); + +endfunction : new + +function void uvma_cva6_core_cntrl_agent_c::retrieve_vif(); + + uvma_cva6_core_cntrl_cntxt_c cva6_cntxt; + + $cast(cva6_cntxt, cntxt); + + // Core control interface + if (!uvm_config_db#(virtual uvme_cva6_core_cntrl_if)::get(this, "", $sformatf("core_cntrl_vif"), cva6_cntxt.core_cntrl_vif)) begin + `uvm_fatal("VIF", $sformatf("Could not find vif handle of type %s in uvm_config_db", + $typename(cva6_cntxt.core_cntrl_vif))) + end + else begin + `uvm_info("VIF", $sformatf("Found vif handle of type %s in uvm_config_db", + $typename(cva6_cntxt.core_cntrl_vif)), UVM_DEBUG) + end +endfunction : retrieve_vif + +function void uvma_cva6_core_cntrl_agent_c::get_and_set_cntxt(); + + void'(uvm_config_db#(uvma_core_cntrl_cntxt_c)::get(this, "", "cntxt", cntxt)); + if (!cntxt) begin + `uvm_info(log_tag, "Context handle is null; creating", UVM_LOW); + cntxt = uvma_cva6_core_cntrl_cntxt_c::type_id::create("cntxt"); + end + + uvm_config_db#(uvma_core_cntrl_cntxt_c)::set(this, "*", "cntxt", cntxt); + +endfunction : get_and_set_cntxt + +task uvma_cva6_core_cntrl_agent_c::run_phase(uvm_phase phase); + + if (cfg.is_active) begin + fork + start_fetch_toggle_seq(); + join_none + end + +endtask : run_phase + +task uvma_cva6_core_cntrl_agent_c::start_fetch_toggle_seq(); + + `uvm_warning(log_tag, "fetch toggle not supported in CVA6"); + +endtask : start_fetch_toggle_seq + +`endif // __UVMA_CVA6_CORE_CNTRL_AGENT_SV__ diff --git a/verif/env/uvme/uvma_cva6_core_cntrl_cntxt.sv b/verif/env/uvme/uvma_cva6_core_cntrl_cntxt.sv new file mode 100644 index 0000000000..0973c58e3c --- /dev/null +++ b/verif/env/uvme/uvma_cva6_core_cntrl_cntxt.sv @@ -0,0 +1,51 @@ +// Copyright 2023 OpenHW Group +// Copyright 2023 Datum Technology Corporation +// Copyright 2023 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + +`ifndef __UVMA_CVA6_CORE_CNTRL_CNTXT_SV__ +`define __UVMA_CVA6_CORE_CNTRL_CNTXT_SV__ + + +/** + * Object encapsulating all state variables for all Rvvi agent + * (uvma_core_cntrl_agent_c) components. + */ + class uvma_cva6_core_cntrl_cntxt_c extends uvma_core_cntrl_cntxt_c; + + virtual uvme_cva6_core_cntrl_if core_cntrl_vif; + + `uvm_object_utils_begin(uvma_cva6_core_cntrl_cntxt_c) + `uvm_object_utils_end + + /** + * Builds events. + */ + extern function new(string name="uvma_cva6_core_cntrl_cntxt"); + +endclass : uvma_cva6_core_cntrl_cntxt_c + +`pragma protect begin + +function uvma_cva6_core_cntrl_cntxt_c::new(string name="uvma_cva6_core_cntrl_cntxt"); + + super.new(name); + +endfunction : new + +`pragma protect end + + +`endif // __UVMA_CVA6_CORE_CNTRL_CNTXT_SV__ diff --git a/verif/env/uvme/uvma_cva6_core_cntrl_drv.sv b/verif/env/uvme/uvma_cva6_core_cntrl_drv.sv new file mode 100644 index 0000000000..5c6a37bd92 --- /dev/null +++ b/verif/env/uvme/uvma_cva6_core_cntrl_drv.sv @@ -0,0 +1,62 @@ +// Copyright 2023 OpenHW Group +// Copyright 2023 Datum Technology Corporation +// Copyright 2023 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// + +`ifndef __UVMA_CVA6_CORE_CNTRL_DRV_SV__ +`define __UVMA_CVA6_CORE_CNTRL_DRV_SV__ + +/** + * Component driving bootstrap pins and other misecllaneous I/O for cva6 core + */ +class uvma_cva6_core_cntrl_drv_c extends uvma_core_cntrl_drv_c; + + `uvm_component_utils_begin(uvma_cva6_core_cntrl_drv_c) + `uvm_component_utils_end + + /** + * Default constructor. + */ + extern function new(string name="uvma_cva6_core_cntrl_drv", uvm_component parent=null); + + extern task drive_bootstrap(); + +endclass : uvma_cva6_core_cntrl_drv_c + +function uvma_cva6_core_cntrl_drv_c::new(string name="uvma_cva6_core_cntrl_drv", uvm_component parent=null); + + super.new(name, parent); + +endfunction : new + +task uvma_cva6_core_cntrl_drv_c::drive_bootstrap(); + + uvma_cva6_core_cntrl_cntxt_c cva6_cntxt; + + $cast(cva6_cntxt, cntxt); + + cva6_cntxt.core_cntrl_vif.boot_addr = cfg.boot_addr; + cva6_cntxt.core_cntrl_vif.nmi_addr = cfg.nmi_addr; + cva6_cntxt.core_cntrl_vif.mtvec_addr = cfg.mtvec_addr; + cva6_cntxt.core_cntrl_vif.dm_halt_addr = cfg.dm_halt_addr; + cva6_cntxt.core_cntrl_vif.dm_exception_addr = cfg.dm_exception_addr; + cva6_cntxt.core_cntrl_vif.mhartid = cfg.mhartid; + cva6_cntxt.core_cntrl_vif.mimpid = cfg.mimpid; + cva6_cntxt.core_cntrl_vif.fetch_en = 1'b0; + cva6_cntxt.core_cntrl_vif.scan_cg_en = 1'b0; + +endtask : drive_bootstrap + +`endif // __UVMA_CVA6_CORE_CNTRL_DRV_SV__ diff --git a/verif/env/uvme/uvme_cva6_cfg.sv b/verif/env/uvme/uvme_cva6_cfg.sv new file mode 100644 index 0000000000..1479d98b82 --- /dev/null +++ b/verif/env/uvme/uvme_cva6_cfg.sv @@ -0,0 +1,244 @@ +// Copyright 2020 OpenHW Group +// Copyright 2020 Datum Technology Corporation +// Copyright 2020 Silicon Labs, Inc. +// Copyright 2021 Thales DIS Design Services SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 + + +`ifndef __UVME_CVA6_CFG_SV__ +`define __UVME_CVA6_CFG_SV__ + + +/** + * Object encapsulating all parameters for creating, connecting and running + * CVA6 environment (uvme_cva6_env_c) components. + */ +class uvme_cva6_cfg_c extends uvma_core_cntrl_cfg_c; + + // Integrals + rand bit enabled; + + rand bit scoreboarding_enabled; + rand bit cov_model_enabled; + rand bit trn_log_enabled; + rand int unsigned sys_clk_period; + + // Agent cfg handles + rand uvma_clknrst_cfg_c clknrst_cfg; + rand uvma_cvxif_cfg_c cvxif_cfg; + rand uvma_axi_cfg_c axi_cfg; + rand uvma_rvfi_cfg_c#(ILEN,XLEN) rvfi_cfg; + rand uvma_isacov_cfg_c isacov_cfg; + + `uvm_object_utils_begin(uvme_cva6_cfg_c) + `uvm_field_int ( enabled , UVM_DEFAULT ) + `uvm_field_enum(uvm_active_passive_enum, is_active , UVM_DEFAULT ) + `uvm_field_int ( scoreboarding_enabled , UVM_DEFAULT ) + `uvm_field_int ( cov_model_enabled , UVM_DEFAULT ) + `uvm_field_int ( trn_log_enabled , UVM_DEFAULT ) + `uvm_field_int ( sys_clk_period , UVM_DEFAULT + UVM_DEC) + + `uvm_field_object(clknrst_cfg, UVM_DEFAULT) + + `uvm_field_object(cvxif_cfg, UVM_DEFAULT) + + `uvm_field_object(axi_cfg, UVM_DEFAULT) + + `uvm_field_object(rvfi_cfg, UVM_DEFAULT) + + `uvm_field_object(isacov_cfg, UVM_DEFAULT) + + `uvm_object_utils_end + + + constraint defaults_cons { + soft enabled == 0; + soft is_active == UVM_ACTIVE; + soft scoreboarding_enabled == 1; + soft cov_model_enabled == 1; + soft trn_log_enabled == 1; + soft sys_clk_period == uvme_cva6_sys_default_clk_period; // see uvme_cva6_constants.sv + } + + constraint cvxif_feature { //CV32A60X do not support dual read & write also the memory interface + cvxif_cfg.dual_read_write_support_x == 0; + cvxif_cfg.load_store_support_x == 0; + cvxif_cfg.seq_cus_instr_x2_enabled == 1; + cvxif_cfg.reg_cus_crosses_enabled == 0; + } + constraint cva6_riscv_cons { + xlen == uvma_core_cntrl_pkg::MXL_32; + ilen == 32; + + ext_i_supported == 1; + ext_a_supported == 0; + ext_m_supported == 1; + ext_c_supported == 1; + ext_p_supported == 0; + ext_v_supported == 0; + ext_f_supported == 0; + ext_d_supported == 0; + ext_zba_supported == 0; + ext_zbb_supported == 0; + ext_zbc_supported == 0; + ext_zbe_supported == 0; + ext_zbf_supported == 0; + ext_zbm_supported == 0; + ext_zbp_supported == 0; + ext_zbr_supported == 0; + ext_zbs_supported == 0; + ext_zbt_supported == 0; + ext_zifencei_supported == 1; + ext_zicsr_supported == 1; + + mode_s_supported == 0; + mode_u_supported == 0; + + pmp_supported == 0; + debug_supported == 0; + + unaligned_access_supported == 0; + unaligned_access_amo_supported == 0; + + bitmanip_version == BITMANIP_VERSION_1P00; + priv_spec_version == PRIV_VERSION_MASTER; + endianness == ENDIAN_LITTLE; + + boot_addr_valid == 1; + mtvec_addr_valid == 1; + dm_halt_addr_valid == 1; + dm_exception_addr_valid == 1; + nmi_addr_valid == 1; + } + + constraint default_cva6_boot_cons { + (!mhartid_plusarg_valid) -> (mhartid == 'h0000_0000); + (!mimpid_plusarg_valid) -> (mimpid == 'h0000_0000); + (!boot_addr_plusarg_valid) -> (boot_addr == 'h8000_0000); + (!mtvec_addr_plusarg_valid) -> (mtvec_addr == 'h0000_0000); + (!nmi_addr_plusarg_valid) -> (nmi_addr == 'h0000_0000); + (!dm_halt_addr_plusarg_valid) -> (dm_halt_addr == 'h0000_0000); + (!dm_exception_addr_plusarg_valid) -> (dm_exception_addr == 'h0000_0000); + } + + constraint agent_cfg_cons { + if (enabled) { + clknrst_cfg.enabled == 1; + isacov_cfg.enabled == 1; + rvfi_cfg.enabled == 1; + } + + isacov_cfg.seq_instr_group_x2_enabled == 1; + isacov_cfg.seq_instr_group_x3_enabled == 0; + isacov_cfg.seq_instr_group_x4_enabled == 0; + isacov_cfg.seq_instr_x2_enabled == 1; + isacov_cfg.reg_crosses_enabled == 0; + isacov_cfg.reg_hazards_enabled == 1; + rvfi_cfg.nret == RVFI_NRET; + + if (is_active == UVM_ACTIVE) { + clknrst_cfg.is_active == UVM_ACTIVE; + isacov_cfg.is_active == UVM_PASSIVE; + rvfi_cfg.is_active == UVM_PASSIVE; + } + + if (trn_log_enabled) { + clknrst_cfg.trn_log_enabled == 0; + axi_cfg.trn_log_enabled == 1; + rvfi_cfg.trn_log_enabled == 1; + isacov_cfg.trn_log_enabled == 1; + } + + if (cov_model_enabled) { + cvxif_cfg.cov_model_enabled == 1; + isacov_cfg.cov_model_enabled == 1; + } + + } + + /** + * Creates sub-configuration objects. + */ + extern function new(string name="uvme_cva6_cfg"); + + /** + * Sample the parameters of the DUT via the virtual interface in a context + */ + extern virtual function void sample_parameters(uvma_core_cntrl_cntxt_c cntxt); + + /** + * Set unsupported_csr_mask based on extensions/modes supported + */ + extern virtual function void set_unsupported_csr_mask(); + +endclass : uvme_cva6_cfg_c + + +function uvme_cva6_cfg_c::new(string name="uvme_cva6_cfg"); + + super.new(name); + + clknrst_cfg = uvma_clknrst_cfg_c::type_id::create("clknrst_cfg"); + cvxif_cfg = uvma_cvxif_cfg_c::type_id::create("cvxif_cfg"); + axi_cfg = uvma_axi_cfg_c::type_id::create("axi_cfg"); + rvfi_cfg = uvma_rvfi_cfg_c#(ILEN,XLEN)::type_id::create("rvfi_cfg"); + isacov_cfg = uvma_isacov_cfg_c::type_id::create("isacov_cfg"); + + isacov_cfg.core_cfg = this; + rvfi_cfg.core_cfg = this; + +endfunction : new + +function void uvme_cva6_cfg_c::sample_parameters(uvma_core_cntrl_cntxt_c cntxt); + + uvma_cva6_core_cntrl_cntxt_c cva6_cntxt; + + if (!$cast(cva6_cntxt, cntxt)) begin + `uvm_fatal("SAMPLECNTXT", "Could not cast cntxt to uvma_cva6_core_cntrl_cntxt_c"); + end + + + num_mhpmcounters = cva6_cntxt.core_cntrl_vif.num_mhpmcounters; + // TODO : Check PMA + //~ pma_regions = new[cva6_cntxt.core_cntrl_vif.pma_cfg.size()]; + + //~ foreach (pma_regions[i]) begin + //~ pma_regions[i] = uvma_core_cntrl_pma_region_c::type_id::create($sformatf("pma_region%0d", i)); + //~ pma_regions[i].word_addr_low = cva6_cntxt.core_cntrl_vif.pma_cfg[i].word_addr_low; + //~ pma_regions[i].word_addr_high = cva6_cntxt.core_cntrl_vif.pma_cfg[i].word_addr_high; + //~ pma_regions[i].main = cva6_cntxt.core_cntrl_vif.pma_cfg[i].main; + //~ pma_regions[i].bufferable = core_cntrl_vif.pma_cfg[i].bufferable; + //~ pma_regions[i].cacheable = core_cntrl_vif.pma_cfg[i].cacheable; + //~ pma_regions[i].atomic = core_cntrl_vif.pma_cfg[i].atomic; + //~ end + + //~ // Copy to the pma_configuration + //~ pma_cfg.regions = new[pma_regions.size()]; + //~ foreach (pma_cfg.regions[i]) + //~ pma_cfg.regions[i] = pma_regions[i]; + +endfunction : sample_parameters + +function void uvme_cva6_cfg_c::set_unsupported_csr_mask(); + + super.set_unsupported_csr_mask(); + + // Remove unsupported CSRs for STEP1 configuration + unsupported_csr_mask[uvma_core_cntrl_pkg::MCOUNTINHIBIT] = 1; + +endfunction : set_unsupported_csr_mask + +`endif // __UVME_CVA6_CFG_SV__ diff --git a/verif/env/uvme/uvme_cva6_cntxt.sv b/verif/env/uvme/uvme_cva6_cntxt.sv new file mode 100644 index 0000000000..247d5f92be --- /dev/null +++ b/verif/env/uvme/uvme_cva6_cntxt.sv @@ -0,0 +1,82 @@ +// Copyright 2020 OpenHW Group +// Copyright 2020 Datum Technology Corporation +// Copyright 2020 Silicon Labs, Inc. +// Copyright 2021 Thales DIS Design Services SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 + + +`ifndef __UVME_CVA6_CNTXT_SV__ +`define __UVME_CVA6_CNTXT_SV__ + +/** + * Object encapsulating all state variables for CVA6 environment + * (uvme_cva6_env_c) components. + */ +class uvme_cva6_cntxt_c extends uvm_object; + + // Agent context handles + uvma_clknrst_cntxt_c clknrst_cntxt; + uvma_cvxif_cntxt_c cvxif_cntxt; + uvma_axi_cntxt_c axi_cntxt; + uvma_cva6_core_cntrl_cntxt_c core_cntrl_cntxt; + uvma_rvfi_cntxt_c rvfi_cntxt; + +// Memory modelling + rand uvml_mem_c mem; + + // Events + uvm_event sample_cfg_e; + uvm_event sample_cntxt_e; + + + `uvm_object_utils_begin(uvme_cva6_cntxt_c) + `uvm_field_object(clknrst_cntxt, UVM_DEFAULT) + `uvm_field_object(axi_cntxt, UVM_DEFAULT) + `uvm_field_object(core_cntrl_cntxt, UVM_DEFAULT) + `uvm_field_object(rvfi_cntxt, UVM_DEFAULT) + `uvm_field_event(sample_cfg_e , UVM_DEFAULT) + `uvm_field_event(sample_cntxt_e, UVM_DEFAULT) + `uvm_field_object(mem, UVM_DEFAULT) + `uvm_object_utils_end + + constraint mem_cfg_cons { + mem.mem_default == MEM_DEFAULT_0; + } + + /** + * Builds events and sub-context objects. + */ + extern function new(string name="uvme_cva6_cntxt"); + +endclass : uvme_cva6_cntxt_c + + +function uvme_cva6_cntxt_c::new(string name="uvme_cva6_cntxt"); + + super.new(name); + + clknrst_cntxt = uvma_clknrst_cntxt_c::type_id::create("clknrst_cntxt"); + core_cntrl_cntxt = uvma_cva6_core_cntrl_cntxt_c::type_id::create("core_cntrl_cntxt"); + axi_cntxt = uvma_axi_cntxt_c::type_id::create("axi_cntxt"); + mem = uvml_mem_c::type_id::create("mem"); + rvfi_cntxt = uvma_rvfi_cntxt_c::type_id::create("rvfi_cntxt"); + + sample_cfg_e = new("sample_cfg_e" ); + sample_cntxt_e = new("sample_cntxt_e"); + +endfunction : new + +`endif // __UVME_CVA6_CNTXT_SV__ diff --git a/verif/env/uvme/uvme_cva6_constants.sv b/verif/env/uvme/uvme_cva6_constants.sv new file mode 100644 index 0000000000..aea0364e17 --- /dev/null +++ b/verif/env/uvme/uvme_cva6_constants.sv @@ -0,0 +1,31 @@ +// Copyright 2020 OpenHW Group +// Copyright 2020 Datum Technology Corporation +// Copyright 2021 Thales DIS Design Services SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 + + +`ifndef __UVME_CVA6_CONSTANTS_SV__ +`define __UVME_CVA6_CONSTANTS_SV__ + + +parameter uvme_cva6_sys_default_clk_period = 1_500; // 10ns +parameter uvme_cva6_debug_default_clk_period = 10_000; // 10ns + +parameter XLEN = 32; +parameter ILEN = 32; +parameter RVFI_NRET = 1; + +`endif // __UVME_CVA6_CONSTANTS_SV__ diff --git a/verif/env/uvme/uvme_cva6_core_cntrl_if.sv b/verif/env/uvme/uvme_cva6_core_cntrl_if.sv new file mode 100644 index 0000000000..e8e32e3403 --- /dev/null +++ b/verif/env/uvme/uvme_cva6_core_cntrl_if.sv @@ -0,0 +1,31 @@ +/** + * Quasi-static core control signals. + */ +interface uvme_cva6_core_cntrl_if + import uvm_pkg::*; + import uvme_cva6_pkg::*; + (); + + logic clk; + logic fetch_en; + + logic scan_cg_en; + logic [XLEN-1:0] boot_addr; + logic [XLEN-1:0] mtvec_addr; + logic [XLEN-1:0] dm_halt_addr; + logic [XLEN-1:0] dm_exception_addr; + logic [XLEN-1:0] nmi_addr; + logic [XLEN-1:0] mhartid; + logic [XLEN-1:0] mimpid; + + logic [XLEN-1:0] num_mhpmcounters; + //~ pma_region_t pma_cfg[]; + + // Testcase asserts this to load memory (not really a core control signal) + logic load_instr_mem; + + clocking drv_cb @(posedge clk); + output fetch_en; + endclocking : drv_cb + +endinterface : uvme_cva6_core_cntrl_if diff --git a/verif/env/uvme/uvme_cva6_env.sv b/verif/env/uvme/uvme_cva6_env.sv new file mode 100644 index 0000000000..045f032eec --- /dev/null +++ b/verif/env/uvme/uvme_cva6_env.sv @@ -0,0 +1,346 @@ +// Copyright 2020 OpenHW Group +// Copyright 2020 Datum Technology Corporation +// Copyright 2020 Silicon Labs, Inc. +// Copyright 2021 Thales DIS Design Services SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 + + +`ifndef __UVME_CVA6_ENV_SV__ +`define __UVME_CVA6_ENV_SV__ + + +/** + * Top-level component that encapsulates, builds and connects all other + * CVA6 environment components. + */ +class uvme_cva6_env_c extends uvm_env; + + // Objects + uvme_cva6_cfg_c cfg; + uvme_cva6_cntxt_c cntxt; + + // Components + uvme_cva6_prd_c predictor; + uvme_cva6_sb_c sb; + uvme_cva6_vsqr_c vsequencer; + uvme_cva6_cov_model_c cov_model; + + // Agents + uvma_clknrst_agent_c clknrst_agent; + uvma_cvxif_agent_c cvxif_agent; + uvma_axi_agent_c axi_agent; + uvma_cva6_core_cntrl_agent_c core_cntrl_agent; + uvma_rvfi_agent_c#(ILEN,XLEN) rvfi_agent; + uvma_isacov_agent_c#(ILEN,XLEN) isacov_agent; + + // Handle to agent switch interface + virtual uvmt_axi_switch_intf axi_switch_vif; + + + + `uvm_component_utils_begin(uvme_cva6_env_c) + `uvm_field_object(cfg , UVM_DEFAULT) + `uvm_field_object(cntxt, UVM_DEFAULT) + `uvm_component_utils_end + + + /** + * Default constructor. + */ + extern function new(string name="uvme_cva6_env", uvm_component parent=null); + + /** + * 1. Ensures cfg & cntxt handles are not null + * 2. Assigns cfg and cntxt handles via assign_cfg() & assign_cntxt() + * 3. Builds all components via create_<x>() + */ + extern virtual function void build_phase(uvm_phase phase); + + /** + * 1. Connects agents to predictor via connect_predictor() + * 3. Connects predictor & agents to scoreboard via connect_scoreboard() + * 4. Assembles virtual sequencer handles via assemble_vsequencer() + */ + extern virtual function void connect_phase(uvm_phase phase); + + /** + * Print out final elaboration + */ + extern virtual function void end_of_elaboration_phase(uvm_phase phase); + + /** + * Creates and starts the instruction and virtual peripheral sequences in active mode. + */ + extern virtual task run_phase(uvm_phase phase); + + /** + * Get switch vif and set signals values + */ + extern function void retrieve_vif(); + + /** + * Assigns configuration handles to components using UVM Configuration Database. + */ + extern virtual function void assign_cfg(); + + /** + * Assigns context handles to components using UVM Configuration Database. + */ + extern virtual function void assign_cntxt(); + + /** + * Creates agent components. + */ + extern virtual function void create_agents(); + + /** + * Creates additional (non-agent) environment components (and objects). + */ + extern virtual function void create_env_components(); + + /** + * Creates environment's virtual sequencer. + */ + extern virtual function void create_vsequencer(); + + /** + * Connects agents to predictor. + */ + extern virtual function void connect_predictor(); + + /** + * Connects scoreboards components to agents/predictor. + */ + extern virtual function void connect_scoreboard(); + + /** + * Connects environment coverage model to agents/scoreboards/predictor. + */ + extern virtual function void connect_coverage_model(); + + /** + * Assembles virtual sequencer from agent sequencers. + */ + extern virtual function void assemble_vsequencer(); + +endclass : uvme_cva6_env_c + + +function uvme_cva6_env_c::new(string name="uvme_cva6_env", uvm_component parent=null); + + super.new(name, parent); + +endfunction : new + + +function void uvme_cva6_env_c::build_phase(uvm_phase phase); + + super.build_phase(phase); + + void'(uvm_config_db#(uvme_cva6_cfg_c)::get(this, "", "cfg", cfg)); + if (!cfg) begin + `uvm_fatal("CFG", "Configuration handle is null") + end + else begin + `uvm_info("CFG", $sformatf("Found configuration handle:\n%s", cfg.sprint()), UVM_DEBUG) + end + + if (cfg.enabled) begin + void'(uvm_config_db#(uvme_cva6_cntxt_c)::get(this, "", "cntxt", cntxt)); + if (!cntxt) begin + `uvm_info("CNTXT", "Context handle is null; creating.", UVM_DEBUG) + cntxt = uvme_cva6_cntxt_c::type_id::create("cntxt"); + end + + retrieve_vif(); + assign_cfg (); + assign_cntxt (); + create_agents (); + create_env_components(); + + if (cfg.is_active) begin + create_vsequencer(); + end + end + +endfunction : build_phase + + +function void uvme_cva6_env_c::connect_phase(uvm_phase phase); + + super.connect_phase(phase); + + if (cfg.enabled) begin + if (cfg.scoreboarding_enabled) begin + connect_predictor (); + connect_scoreboard(); + end + + if (cfg.is_active) begin + assemble_vsequencer(); + end + if (cfg.cov_model_enabled) begin + connect_coverage_model(); + end + end + +endfunction: connect_phase + + +function void uvme_cva6_env_c::end_of_elaboration_phase(uvm_phase phase); + super.end_of_elaboration_phase(phase); + + `uvm_info("UVMECVA6ENV", $sformatf("Configuration:\n%s", cfg.sprint()), UVM_LOW) + +endfunction : end_of_elaboration_phase + +function void uvme_cva6_env_c::assign_cfg(); + + uvm_config_db#(uvme_cva6_cfg_c)::set(this, "*", "cfg", cfg); + + uvm_config_db#(uvma_clknrst_cfg_c)::set(this, "*clknrst_agent", "cfg", cfg.clknrst_cfg); + + uvm_config_db#(uvma_cvxif_cfg_c)::set(this, "*cvxif_agent", "cfg", cfg.cvxif_cfg); + + uvm_config_db#(uvma_axi_cfg_c)::set(this, "*axi_agent", "cfg", cfg.axi_cfg); + + uvm_config_db#(uvma_core_cntrl_cfg_c)::set(this, "core_cntrl_agent", "cfg", cfg); + + uvm_config_db#(uvma_rvfi_cfg_c#(ILEN,XLEN))::set(this, "*rvfi_agent", "cfg", cfg.rvfi_cfg); + + uvm_config_db#(uvma_isacov_cfg_c)::set(this, "*isacov_agent", "cfg", cfg.isacov_cfg); + +endfunction: assign_cfg + + +function void uvme_cva6_env_c::assign_cntxt(); + + uvm_config_db#(uvme_cva6_cntxt_c)::set(this, "*", "cntxt", cntxt); + uvm_config_db#(uvma_clknrst_cntxt_c)::set(this, "clknrst_agent", "cntxt", cntxt.clknrst_cntxt); + uvm_config_db#(uvma_axi_cntxt_c)::set(this, "axi_agent", "cntxt", cntxt.axi_cntxt); + uvm_config_db#(uvma_rvfi_cntxt_c)::set(this, "rvfi_agent", "cntxt", cntxt.rvfi_cntxt); + +endfunction: assign_cntxt + + +function void uvme_cva6_env_c::create_agents(); + + clknrst_agent = uvma_clknrst_agent_c::type_id::create("clknrst_agent", this); + cvxif_agent = uvma_cvxif_agent_c::type_id::create("cvxif_agent", this); + axi_agent = uvma_axi_agent_c::type_id::create("axi_agent", this); + core_cntrl_agent = uvma_cva6_core_cntrl_agent_c::type_id::create("core_cntrl_agent", this); + rvfi_agent = uvma_rvfi_agent_c#(ILEN,XLEN)::type_id::create("rvfi_agent", this); + isacov_agent = uvma_isacov_agent_c#(ILEN,XLEN)::type_id::create("isacov_agent", this); + +endfunction: create_agents + + +function void uvme_cva6_env_c::create_env_components(); + + if (cfg.scoreboarding_enabled) begin + predictor = uvme_cva6_prd_c::type_id::create("predictor", this); + sb = uvme_cva6_sb_c ::type_id::create("sb" , this); + end + + if (cfg.cov_model_enabled) begin + cov_model = uvme_cva6_cov_model_c::type_id::create("cov_model", this); + end + +endfunction: create_env_components + + +function void uvme_cva6_env_c::create_vsequencer(); + + vsequencer = uvme_cva6_vsqr_c::type_id::create("vsequencer", this); + +endfunction: create_vsequencer + +function void uvme_cva6_env_c::retrieve_vif(); + + if (!uvm_config_db#(virtual uvmt_axi_switch_intf)::get(this, "", "axi_switch_vif", axi_switch_vif)) begin + `uvm_fatal("VIF", $sformatf("Could not find vif handle of type %s in uvm_config_db", $typename(axi_switch_vif))) + end + else begin + `uvm_info("VIF", $sformatf("Found vif handle of type %s in uvm_config_db", $typename(axi_switch_vif)), UVM_DEBUG) + end + + if(cfg.axi_cfg.is_active == UVM_PASSIVE) begin + axi_switch_vif.active <= 0; + end else begin + axi_switch_vif.active <= 1; + end + +endfunction : retrieve_vif + +function void uvme_cva6_env_c::connect_predictor(); + + //debug_agent.mon_ap.connect(predictor.debug_export); + //clknrst_agent.mon_ap.connect(predictor.clknrst_export); + // TODO Connect agents monitor analysis ports to predictor + +endfunction: connect_predictor + + +function void uvme_cva6_env_c::connect_scoreboard(); + + // TODO Connect agents -> scoreboard + // Ex: debug_agent.mon_ap.connect(sb.debug_sb.act_export); + + // TODO Connect predictor -> scoreboard + // Ex: predictor.debug_ap.connect(sb.debug_sb.exp_export); + +endfunction: connect_scoreboard + + +function void uvme_cva6_env_c::assemble_vsequencer(); + + vsequencer.clknrst_sequencer = clknrst_agent.sequencer; + vsequencer.cvxif_vsequencer = cvxif_agent.vsequencer; + vsequencer.axi_vsequencer = axi_agent.vsequencer; + +endfunction: assemble_vsequencer + + +task uvme_cva6_env_c::run_phase(uvm_phase phase); + + fork + + begin + uvme_cvxif_vseq_c cvxif_vseq; + cvxif_vseq = uvme_cvxif_vseq_c::type_id::create("cvxif_vseq"); + cvxif_vseq.start(cvxif_agent.vsequencer); + end + + begin + if(cfg.axi_cfg.is_active == UVM_ACTIVE) begin + uvma_axi_vseq_c axi_vseq; + axi_vseq = uvma_axi_vseq_c::type_id::create("axi_vseq"); + axi_vseq.start(axi_agent.vsequencer); + end + end + join_none +endtask + +function void uvme_cva6_env_c::connect_coverage_model(); + + cvxif_agent.monitor.req_ap.connect(cov_model.cvxif_covg.req_item_fifo.analysis_export); + foreach (rvfi_agent.instr_mon_ap[i]) begin + rvfi_agent.instr_mon_ap[i].connect(isacov_agent.monitor.rvfi_instr_imp); + end + +endfunction: connect_coverage_model + +`endif // __UVME_CVA6_ENV_SV__ diff --git a/verif/env/uvme/uvme_cva6_macros.sv b/verif/env/uvme/uvme_cva6_macros.sv new file mode 100644 index 0000000000..cd18e6071b --- /dev/null +++ b/verif/env/uvme/uvme_cva6_macros.sv @@ -0,0 +1,27 @@ +// Copyright 2020 OpenHW Group +// Copyright 2020 Datum Technology Corporation +// Copyright 2021 Thales DIS Design Services SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 + + +`ifndef __UVME_CVA6_MACROS_SV__ +`define __UVME_CVA6_MACROS_SV__ + + +`define per_instance_fcov `ifndef DSIM option.per_instance = 1; `endif + + +`endif // __UVME_CVA6_MACROS_SV__ diff --git a/verif/env/uvme/uvme_cva6_pkg.flist b/verif/env/uvme/uvme_cva6_pkg.flist new file mode 100644 index 0000000000..3f38acb01f --- /dev/null +++ b/verif/env/uvme/uvme_cva6_pkg.flist @@ -0,0 +1,27 @@ +// Copyright 2020 OpenHW Group +// Copyright 2020 Datum Technology Corporation +// Copyright 2021 Thales DIS Design Services SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 + + +// Directories ++incdir+${CVA6_UVME_PATH} ++incdir+${CVA6_UVME_PATH}/cov ++incdir+${CVA6_UVME_PATH}/vseq ++incdir+${CVA6_UVME_PATH}/cvxif_vseq + +// Files +${CVA6_UVME_PATH}/uvme_cva6_pkg.sv diff --git a/verif/env/uvme/uvme_cva6_pkg.sv b/verif/env/uvme/uvme_cva6_pkg.sv new file mode 100644 index 0000000000..5b0908c633 --- /dev/null +++ b/verif/env/uvme/uvme_cva6_pkg.sv @@ -0,0 +1,83 @@ +// Copyright 2020 OpenHW Group +// Copyright 2020 Datum Technology Corporation +// Copyright 2020 Silicon Labs, Inc. +// Copyright 2021 Thales DIS Design Services SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 + + +`ifndef __UVME_CVA6_PKG_SV__ +`define __UVME_CVA6_PKG_SV__ + + +// Pre-processor macros +`include "uvm_macros.svh" +`include "uvml_hrtbt_macros.sv" +`include "uvml_sb_macros.sv" + +`include "uvma_clknrst_macros.sv" +`include "uvme_cva6_macros.sv" + + + /** + * Encapsulates all the types needed for an UVM environment capable of driving/ + * monitoring and verifying the behavior of an CVA6 design. + */ +package uvme_cva6_pkg; + + import uvm_pkg ::*; + import uvml_hrtbt_pkg ::*; + import uvml_sb_pkg ::*; + import uvml_trn_pkg ::*; + import uvma_clknrst_pkg::*; + import uvma_cvxif_pkg::*; + import uvma_axi_pkg::*; + import uvml_mem_pkg ::*; + import uvma_core_cntrl_pkg::*; + import uvma_rvfi_pkg::*; + import uvma_isacov_pkg::*; + + // Constants / Structs / Enums + `include "uvme_cva6_constants.sv" + `include "uvme_cva6_tdefs.sv" + + // Objects + `include "uvma_cva6_core_cntrl_cntxt.sv" + `include "uvme_cva6_cfg.sv" + `include "uvme_cva6_cntxt.sv" + + // Predictor + `include "uvme_cva6_prd.sv" + + // Environment components + `include "uvma_cva6_core_cntrl_drv.sv" + `include "uvma_cva6_core_cntrl_agent.sv" + `include "uvme_cva6_sb.sv" + `include "uvme_cva6_vsqr.sv" + `include "uvme_cvxif_covg.sv" + `include "uvme_cva6_cov_model.sv" + `include "uvme_cva6_env.sv" + + // Virtual sequences + `include "uvme_cva6_base_vseq.sv" + `include "uvme_cva6_reset_vseq.sv" +// `include "uvme_cva6_interrupt_noise_vseq.sv" + `include "uvme_cva6_vseq_lib.sv" + +endpackage : uvme_cva6_pkg + +`include "uvme_cva6_core_cntrl_if.sv" + +`endif // __UVME_CVA6_PKG_SV__ diff --git a/verif/env/uvme/uvme_cva6_prd.sv b/verif/env/uvme/uvme_cva6_prd.sv new file mode 100644 index 0000000000..81f2148d4b --- /dev/null +++ b/verif/env/uvme/uvme_cva6_prd.sv @@ -0,0 +1,146 @@ +// Copyright 2020 OpenHW Group +// Copyright 2020 Datum Technology Corporation +// Copyright 2021 Thales DIS Design Services SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 + + +`ifndef __UVME_CVA6_PRD_SV__ +`define __UVME_CVA6_PRD_SV__ + + +/** + * Component implementing transaction-based software model of CVA6 DUT. + */ +class uvme_cva6_prd_c extends uvm_component; + + // Objects + uvme_cva6_cfg_c cfg; + uvme_cva6_cntxt_c cntxt; + + // Input TLM + uvm_analysis_export #(uvma_clknrst_mon_trn_c) clknrst_export; + uvm_tlm_analysis_fifo#(uvma_clknrst_mon_trn_c) clknrst_fifo; + + `uvm_component_utils_begin(uvme_cva6_prd_c) + `uvm_field_object(cfg , UVM_DEFAULT) + `uvm_field_object(cntxt, UVM_DEFAULT) + `uvm_component_utils_end + + + /** + * Default constructor. + */ + extern function new(string name="uvme_cva6_prd", uvm_component parent=null); + + /** + * TODO Describe uvme_cva6_prd_c::build_phase() + */ + extern virtual function void build_phase(uvm_phase phase); + + /** + * TODO Describe uvme_cva6_prd_c::connect_phase() + */ + extern virtual function void connect_phase(uvm_phase phase); + + /** + * TODO Describe uvme_cva6_prd_c::run_phase() + */ + extern virtual task run_phase(uvm_phase phase); + + /** + * TODO Describe uvme_cva6_prd_c::process_clknrst() + */ + extern task process_clknrst(); + + /** + * TODO Describe uvme_cva6_prd_c::process_debug() + */ + //extern task process_debug(); + +endclass : uvme_cva6_prd_c + + +function uvme_cva6_prd_c::new(string name="uvme_cva6_prd", uvm_component parent=null); + + super.new(name, parent); + +endfunction : new + + +function void uvme_cva6_prd_c::build_phase(uvm_phase phase); + + super.build_phase(phase); + + void'(uvm_config_db#(uvme_cva6_cfg_c)::get(this, "", "cfg", cfg)); + if (!cfg) begin + `uvm_fatal("CFG", "Configuration handle is null") + end + + void'(uvm_config_db#(uvme_cva6_cntxt_c)::get(this, "", "cntxt", cntxt)); + if (!cntxt) begin + `uvm_fatal("CNTXT", "Context handle is null") + end + + // Build Input TLM objects + clknrst_export = new("clknrst_export", this); + clknrst_fifo = new("clknrst_fifo" , this); + //debug_export = new("debug_export", this); + //debug_fifo = new("debug_fifo" , this); + + // Build Output TLM objects + // TODO Create Output TLM objects for uvme_cva6_prd_c + // Ex: pkts_out_ap = new("pkts_out_ap", this); + +endfunction : build_phase + + +function void uvme_cva6_prd_c::connect_phase(uvm_phase phase); + + super.connect_phase(phase); + + // Connect TLM objects + clknrst_export.connect(clknrst_fifo.analysis_export); + //debug_export.connect(debug_fifo.analysis_export); + +endfunction: connect_phase + + +task uvme_cva6_prd_c::run_phase(uvm_phase phase); + + super.run_phase(phase); + + fork + process_clknrst(); + //process_debug(); + join_none + +endtask: run_phase + + +task uvme_cva6_prd_c::process_clknrst(); + + uvma_clknrst_mon_trn_c clknrst_trn; + + forever begin + clknrst_fifo.get(clknrst_trn); + + // TODO Implement uvme_cva6_prd_c::process_clknrst() + end + +endtask : process_clknrst + + +`endif // __UVME_CVA6_PRD_SV__ diff --git a/verif/env/uvme/uvme_cva6_sb.sv b/verif/env/uvme/uvme_cva6_sb.sv new file mode 100644 index 0000000000..cd4650f05b --- /dev/null +++ b/verif/env/uvme/uvme_cva6_sb.sv @@ -0,0 +1,136 @@ +// Copyright 2020 OpenHW Group +// Copyright 2020 Datum Technology Corporation +// Copyright 2021 Thales DIS Design Services SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 + + +`ifndef __UVME_CVA6_SB_SV__ +`define __UVME_CVA6_SB_SV__ + + +/** + * Component encapsulating scoreboards which compare CVA6 + * DUT's expected (from predictor) vs. actual (monitored) transactions. + */ +class uvme_cva6_sb_c extends uvm_scoreboard; + + // Objects + uvme_cva6_cfg_c cfg; + uvme_cva6_cntxt_c cntxt; + + // Components + // TODO Add sub-scoreboards + // Ex: uvme_cva6_sb_simplex_c egress_sb; + // uvme_cva6_sb_simplex_c ingress_sb; + + + `uvm_component_utils_begin(uvme_cva6_sb_c) + `uvm_field_object(cfg , UVM_DEFAULT) + `uvm_field_object(cntxt, UVM_DEFAULT) + + // TODO Add sub-scoreboards field macros + // Ex: `uvm_field_object(egress_sb , UVM_DEFAULT) + // `uvm_field_object(ingress_sb, UVM_DEFAULT) + `uvm_component_utils_end + + + /** + * Default constructor. + */ + extern function new(string name="uvme_cva6_sb", uvm_component parent=null); + + /** + * Create and configures sub-scoreboards via: + * 1. assign_cfg() + * 2. assign_cntxt() + * 3. create_sbs() + */ + extern virtual function void build_phase(uvm_phase phase); + + /** + * Assigns configuration handles. + */ + extern virtual function void assign_cfg(); + + /** + * Assigns context handles. + */ + extern virtual function void assign_cntxt(); + + /** + * Creates sub-scoreboard components. + */ + extern virtual function void create_sbs(); + +endclass : uvme_cva6_sb_c + + +function uvme_cva6_sb_c::new(string name="uvme_cva6_sb", uvm_component parent=null); + + super.new(name, parent); + +endfunction : new + + +function void uvme_cva6_sb_c::build_phase(uvm_phase phase); + + super.build_phase(phase); + + void'(uvm_config_db#(uvme_cva6_cfg_c)::get(this, "", "cfg", cfg)); + if (!cfg) begin + `uvm_fatal("CFG", "Configuration handle is null") + end + + void'(uvm_config_db#(uvme_cva6_cntxt_c)::get(this, "", "cntxt", cntxt)); + if (!cntxt) begin + `uvm_fatal("CNTXT", "Context handle is null") + end + + assign_cfg (); + assign_cntxt(); + create_sbs (); + +endfunction : build_phase + + +function void uvme_cva6_sb_c::assign_cfg(); + + // TODO Implement uvme_cva6_sb_c::assign_cfg() + // Ex: uvm_config_db#(uvm_sb_cfg_c)::set(this, "egress_sb" , "cfg", cfg.sb_egress_cfg ); + // uvm_config_db#(uvm_sb_cfg_c)::set(this, "ingress_sb", "cfg", cfg.sb_ingress_cfg); + +endfunction : assign_cfg + + +function void uvme_cva6_sb_c::assign_cntxt(); + + // TODO Implement uvme_cva6_sb_c::assign_cntxt() + // Ex: uvm_config_db#(uvme_cva6_sb_cntxt_c)::set(this, "egress_sb" , "cntxt", cntxt.sb_egress_cntxt ); + // uvm_config_db#(uvme_cva6_sb_cntxt_c)::set(this, "ingress_sb", "cntxt", cntxt.sb_ingress_cntxt); + +endfunction : assign_cntxt + + +function void uvme_cva6_sb_c::create_sbs(); + + // TODO Implement uvme_cva6_sb_c::create_sbs() + // Ex: egress_sb = uvme_cva6_sb_simplex_c::type_id::create("egress_sb" , this); + // ingress_sb = uvme_cva6_sb_simplex_c::type_id::create("ingress_sb", this); + +endfunction : create_sbs + + +`endif // __UVME_CVA6_SB_SV__ diff --git a/verif/env/uvme/uvme_cva6_tdefs.sv b/verif/env/uvme/uvme_cva6_tdefs.sv new file mode 100644 index 0000000000..890e1e2707 --- /dev/null +++ b/verif/env/uvme/uvme_cva6_tdefs.sv @@ -0,0 +1,113 @@ +// Copyright 2020 OpenHW Group +// Copyright 2020 Datum Technology Corporation +// Copyright 2021 Thales DIS Design Services SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 + + +`ifndef __UVME_CVA6_TDEFS_SV__ +`define __UVME_CVA6_TDEFS_SV__ + + +// The following pseudo-instructions have been removed: +// BEQZ, BGEZ, BGT,BGTU,BGTZ, BLE,BLEU,BLEZ,BLTZ, BNEZ, ILLEGAL +// J, JR, MV, NOT, NEG, NEGW, RET, SEQZ, SGTZ, SLTZ, SNEZ +// The following compressed instructions have not been added: +// C_FLWSP,C_FLDSP,C_FSWSP,C_FSDSP,C_FLW,C_FLD,C_FSW,C_FSD, +// C_J,C_JR,C_BEQZ,C_BNEZ,C_MV,C_SLLI64,C_SRLI64,C_SRAI64 +// The following instructions have been added: +// FENCE +typedef enum { + ADD,ADDI,AND,ANDI,AUIPC,BEQ,BGE,BGEU + ,BLTU,BNE,BLT, FENCE, FENCE_I,EBREAK,ECALL + ,JAL,JALR,LB,LBU,LH,LHU + ,LUI,LW,OR + ,ORI, SB, SH,SLL,SLLI + ,SLT,SLTI,SLTIU,SLTU,SRA,SRAI + ,SRL,SRLI,SUB,SW,XOR,XORI + ,MUL,MULH,MULHU,MULHSU + ,DIV,REM,DIVU,REMU,WFI,MRET,DRET + ,CSRRW, CSRRC, CSRRS + ,CSRRCI, CSRRSI, CSRRWI + ,C_LWSP,C_SWSP,C_LW,C_SW + ,C_BEQZ,C_BNEZ + ,C_J,C_JR,C_JAL,C_JALR,C_LI,C_LUI + ,C_ADDI,C_ADDI16SP,C_ADDI4SPN,C_MV + ,C_SLLI,C_SRLI,C_SRAI,C_ANDI,C_ADD + ,C_AND,C_OR,C_XOR,C_SUB,C_EBREAK +} instr_name_t; // assembler + + +// The following CSR ABI names are not currently included: +// fp, pc +//"gpr_none" CSR ABI name added for JALR instruction check: +typedef enum { + zero,ra,sp,gp,tp,t0,t1,t2,s0 + ,s1,a0,a1,a2,a3,a4,a5,a6 + ,a7,s2,s3,s4,s5,s6,s7,s8 + ,s9,s10,s11,t3,t4,t5,t6 + ,gpr_none +} gpr_name_t; // ABI name + +// TODO: add missing CSRs +typedef enum { + marchid,mcause,mcountinhibit,mcycle,mcycleh,mepc,mhartid + ,mie,mcontext,scontext + ,minstret,minstreth,mip,misa,mscratch,mstatus,mtval,mtvec,mimpid + ,mvendorid + ,tselect,tdata1,tdata2,tdata3,tinfo + ,dscratch0,dscratch1 + + ,mhpmevent3 + ,mhpmevent4,mhpmevent5,mhpmevent6,mhpmevent7,mhpmevent8,mhpmevent9 + ,mhpmevent10,mhpmevent11,mhpmevent12,mhpmevent13,mhpmevent14,mhpmevent15,mhpmevent16,mhpmevent17 + ,mhpmevent18,mhpmevent19,mhpmevent20,mhpmevent21,mhpmevent22,mhpmevent23,mhpmevent24,mhpmevent25 + ,mhpmevent26,mhpmevent27,mhpmevent28,mhpmevent29,mhpmevent30,mhpmevent31 + + ,mhpmcounter3 + ,mhpmcounter4,mhpmcounter5,mhpmcounter6,mhpmcounter7,mhpmcounter8,mhpmcounter9 + ,mhpmcounter10,mhpmcounter11,mhpmcounter12,mhpmcounter13,mhpmcounter14,mhpmcounter15,mhpmcounter16 + ,mhpmcounter17,mhpmcounter18,mhpmcounter19,mhpmcounter20,mhpmcounter21,mhpmcounter22,mhpmcounter23 + ,mhpmcounter24,mhpmcounter25,mhpmcounter26,mhpmcounter27,mhpmcounter28,mhpmcounter29,mhpmcounter30 + ,mhpmcounter31 + + ,mhpmcounterh3 + ,mhpmcounterh4,mhpmcounterh5,mhpmcounterh6,mhpmcounterh7,mhpmcounterh8,mhpmcounterh9 + ,mhpmcounterh10,mhpmcounterh11,mhpmcounterh12,mhpmcounterh13,mhpmcounterh14,mhpmcounterh15,mhpmcounterh16 + ,mhpmcounterh17,mhpmcounterh18,mhpmcounterh19,mhpmcounterh20,mhpmcounterh21,mhpmcounterh22,mhpmcounterh23 + ,mhpmcounterh24,mhpmcounterh25,mhpmcounterh26,mhpmcounterh27,mhpmcounterh28,mhpmcounterh29,mhpmcounterh30 + ,mhpmcounterh31 + + ,medeleg,mcounteren + ,mideleg + ,pmpaddr0,pmpaddr1,pmpaddr10,pmpaddr11,pmpaddr12,pmpaddr13,pmpaddr14 + ,pmpaddr15,pmpaddr2,pmpaddr3,pmpaddr4,pmpaddr5,pmpaddr6,pmpaddr7,pmpaddr8 + ,pmpaddr9,pmpcfg0,pmpcfg1,pmpcfg2,pmpcfg3 +} csr_name_t; + +typedef struct { + string key; + string val; +} ops_t; + +typedef struct { + string ins_str; + instr_name_t asm; + ops_t ops[4]; + bit compressed; + bit[31:0] pc; +} ins_t; + +`endif // __UVME_CVA6_TDEFS_SV__ diff --git a/verif/env/uvme/uvme_cva6_vsqr.sv b/verif/env/uvme/uvme_cva6_vsqr.sv new file mode 100644 index 0000000000..221d4765f8 --- /dev/null +++ b/verif/env/uvme/uvme_cva6_vsqr.sv @@ -0,0 +1,86 @@ +// Copyright 2020 OpenHW Group +// Copyright 2020 Datum Technology Corporation +// Copyright 2020 Silicon Labs, Inc. +// Copyright 2021 Thales DIS Design Services SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 + + +`ifndef __UVME_CVA6_VSQR_SV__ +`define __UVME_CVA6_VSQR_SV__ + + +/** + * Component on which all CVA6 virtual sequences are run. + */ +class uvme_cva6_vsqr_c extends uvm_sequencer#( + .REQ(uvm_sequence_item), + .RSP(uvm_sequence_item) +); + + // Objects + uvme_cva6_cfg_c cfg; + uvme_cva6_cntxt_c cntxt; + + // Sequencer handles + uvma_clknrst_sqr_c clknrst_sequencer; + uvma_cvxif_vsqr_c cvxif_vsequencer; + uvma_axi_vsqr_c axi_vsequencer; + + + `uvm_component_utils_begin(uvme_cva6_vsqr_c) + `uvm_field_object(cfg , UVM_DEFAULT) + `uvm_field_object(cntxt, UVM_DEFAULT) + `uvm_component_utils_end + + + /** + * Default constructor. + */ + extern function new(string name="uvme_cva6_sqr", uvm_component parent=null); + + /** + * Ensures cfg & cntxt handles are not null. + */ + extern virtual function void build_phase(uvm_phase phase); + +endclass : uvme_cva6_vsqr_c + + +function uvme_cva6_vsqr_c::new(string name="uvme_cva6_sqr", uvm_component parent=null); + + super.new(name, parent); + +endfunction : new + + +function void uvme_cva6_vsqr_c::build_phase(uvm_phase phase); + + super.build_phase(phase); + + void'(uvm_config_db#(uvme_cva6_cfg_c)::get(this, "", "cfg", cfg)); + if (!cfg) begin + `uvm_fatal("CFG", "Configuration handle is null") + end + + void'(uvm_config_db#(uvme_cva6_cntxt_c)::get(this, "", "cntxt", cntxt)); + if (!cntxt) begin + `uvm_fatal("CNTXT", "Context handle is null") + end + +endfunction : build_phase + + +`endif // __UVME_CVA6_VSQR_SV__ diff --git a/verif/env/uvme/vseq/uvme_cva6_base_vseq.sv b/verif/env/uvme/vseq/uvme_cva6_base_vseq.sv new file mode 100644 index 0000000000..937e1995e2 --- /dev/null +++ b/verif/env/uvme/vseq/uvme_cva6_base_vseq.sv @@ -0,0 +1,71 @@ +// Copyright 2020 OpenHW Group +// Copyright 2020 Datum Technology Corporation +// Copyright 2021 Thales DIS Design Services SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 + + +`ifndef __UVME_CVA6_BASE_VSEQ_SV__ +`define __UVME_CVA6_BASE_VSEQ_SV__ + + +/** + * Abstract object from which all other CVA6 virtual sequences extend. + * Does not generate any sequence items of its own. Subclasses must be run on + * CVA6 Virtual Sequencer (uvme_cva6_vsqr_c) instance. + */ +class uvme_cva6_base_vseq_c extends uvm_sequence#( + .REQ(uvm_sequence_item), + .RSP(uvm_sequence_item) +); + + // Environment handles + uvme_cva6_cfg_c cfg; + uvme_cva6_cntxt_c cntxt; + + + `uvm_object_utils(uvme_cva6_base_vseq_c) + `uvm_declare_p_sequencer(uvme_cva6_vsqr_c) + + + /** + * Default constructor. + */ + extern function new(string name="uvme_cva6_base_vseq"); + + /** + * Retrieve cfg and cntxt handles from p_sequencer. + */ + extern virtual task pre_start(); + +endclass : uvme_cva6_base_vseq_c + + +function uvme_cva6_base_vseq_c::new(string name="uvme_cva6_base_vseq"); + + super.new(name); + +endfunction : new + + +task uvme_cva6_base_vseq_c::pre_start(); + + cfg = p_sequencer.cfg ; + cntxt = p_sequencer.cntxt; + +endtask : pre_start + + +`endif // __UVME_CVA6_BASE_VSEQ_SV__ diff --git a/verif/env/uvme/vseq/uvme_cva6_reset_vseq.sv b/verif/env/uvme/vseq/uvme_cva6_reset_vseq.sv new file mode 100644 index 0000000000..ffa34503ab --- /dev/null +++ b/verif/env/uvme/vseq/uvme_cva6_reset_vseq.sv @@ -0,0 +1,102 @@ +// Copyright 2020 OpenHW Group +// Copyright 2020 Datum Technology Corporation +// Copyright 2021 Thales DIS Design Services SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 + + +`ifndef __UVME_CVA6_RESET_VSEQ_SV__ +`define __UVME_CVA6_RESET_VSEQ_SV__ + + +/** + * Virtual sequence responsible for starting the system clock and issuing + * the initial reset pulse to the DUT. + */ +class uvme_cva6_reset_vseq_c extends uvme_cva6_base_vseq_c; + + rand int unsigned num_clk_before_reset; ///< Number of clock cylces between start of clock and resert assert + rand int unsigned rst_deassert_period ; ///< Time delta between resert assert and de-assert, measured in picoseconds (ps) + rand int unsigned post_rst_wait ; ///< Time delta between resert de-assert and end of virtual sequence, measured in picoseconds (ps) + + + `uvm_object_utils_begin(uvme_cva6_reset_vseq_c) + `uvm_field_int(num_clk_before_reset, UVM_DEFAULT + UVM_DEC) + `uvm_field_int(rst_deassert_period , UVM_DEFAULT + UVM_DEC) + `uvm_field_int(post_rst_wait , UVM_DEFAULT + UVM_DEC) + `uvm_object_utils_end + + + constraint defaults_cons { + soft num_clk_before_reset == 50; + soft rst_deassert_period == 7_400; // 7.4 ns + soft post_rst_wait == 7_400; // 7.4 ns + } + + + /** + * Default constructor. + */ + extern function new(string name="uvme_cva6_reset_vseq"); + + /** + * Starts the clock, waits, then resets the DUT. + */ + extern virtual task body(); + +endclass : uvme_cva6_reset_vseq_c + + +function uvme_cva6_reset_vseq_c::new(string name="uvme_cva6_reset_vseq"); + + super.new(name); + +endfunction : new + + +task uvme_cva6_reset_vseq_c::body(); + + uvma_clknrst_seq_item_c clk_start_req; + uvma_clknrst_seq_item_c reset_assrt_req; + + // Define the clock before applying reset + #1; + cntxt.clknrst_cntxt.vif.clk = 0; + #1; + + `uvm_info("RST_VSEQ", $sformatf("Starting clock with period of %0t", (cfg.sys_clk_period * 1ps)), UVM_LOW) + `uvm_do_on_with(clk_start_req, p_sequencer.clknrst_sequencer, { + action == UVMA_CLKNRST_SEQ_ITEM_ACTION_START_CLK; + initial_value == UVMA_CLKNRST_SEQ_ITEM_INITIAL_VALUE_0; + //clk_period == local::cfg.sys_clk_period; + clk_period == cfg.sys_clk_period; + //clk_period == uvme_cva6_sys_default_clk_period; + }) + + `uvm_info("RST_VSEQ", $sformatf("Asserting reset for %0t", (rst_deassert_period * 1ps)), UVM_LOW) + `uvm_do_on_with(reset_assrt_req, p_sequencer.clknrst_sequencer, { + action == UVMA_CLKNRST_SEQ_ITEM_ACTION_ASSERT_RESET; + initial_value == UVMA_CLKNRST_SEQ_ITEM_INITIAL_VALUE_1 ; + rst_deassert_period == local::rst_deassert_period; + }) + +// `uvm_info("RST_VSEQ", $sformatf("Done reset, waiting %0t for DUT to stabilize", (post_rst_wait * 1ps)), UVM_LOW) +// #(post_rst_wait * 1ps); + + +endtask : body + + +`endif // __UVME_CVA6_RESET_VSEQ_SV__ diff --git a/verif/env/uvme/vseq/uvme_cva6_vseq_lib.sv b/verif/env/uvme/vseq/uvme_cva6_vseq_lib.sv new file mode 100644 index 0000000000..7895dc6c84 --- /dev/null +++ b/verif/env/uvme/vseq/uvme_cva6_vseq_lib.sv @@ -0,0 +1,55 @@ +// Copyright 2020 OpenHW Group +// Copyright 2020 Datum Technology Corporation +// Copyright 2021 Thales DIS Design Services SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 + + +`ifndef __UVME_CVA6_VSEQ_LIB_SV__ +`define __UVME_CVA6_VSEQ_LIB_SV__ + + +/** + * Virtual sequence library for CVA6 environment. + */ +class uvme_cva6_vseq_lib_c extends uvm_sequence_library#( + .REQ(uvm_sequence_item), + .RSP(uvm_sequence_item) +); + + `uvm_object_utils (uvme_cva6_vseq_lib_c) + `uvm_sequence_library_utils(uvme_cva6_vseq_lib_c) + + + /** + * Initializes sequence library. + */ + extern function new(string name="uvme_cva6_vseq_lib"); + +endclass : uvme_cva6_vseq_lib_c + + +function uvme_cva6_vseq_lib_c::new(string name="uvme_cva6_vseq_lib"); + + super.new(name); + init_sequence_library(); + + // TODO Add sequences to uvme_cva6_vseq_lib_c + // Ex: add_sequence(uvme_cva6_abc_vseq_c::get_type()); + +endfunction : new + + +`endif // __UVME_CVA6_VSEQ_LIB_SV__ diff --git a/verif/regress/benchmark.sh b/verif/regress/benchmark.sh new file mode 100644 index 0000000000..3035a62a42 --- /dev/null +++ b/verif/regress/benchmark.sh @@ -0,0 +1,68 @@ +# Copyright 2022 Thales DIS design services SAS +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Original Author: Guillaume Chauvon (guillaume.chauvon@thalesgroup.com) + +# where are the tools +if [ -z "$RISCV" ]; then + echo "Error: RISCV variable undefined" + return +fi + +# install the required tools +source verif/regress/install-cva6.sh +source verif/regress/install-riscv-dv.sh + +if [ -z "$DV_SIMULATORS" ]; then + DV_SIMULATORS=veri-testharness,spike +fi + +if [ -z "$DV_TARGET" ]; then + DV_TARGET=cv64a6_imafdc_sv39 +fi + +cd verif/sim/ + +BDIR=../tests/riscv-tests/benchmarks/ +CVA6_FLAGS="--target $DV_TARGET --iss=$DV_SIMULATORS --iss_yaml cva6.yaml --linker ../tests/custom/common/test.ld" + +GCC_COMMON_SRC=( + ../tests/riscv-tests/benchmarks/common/syscalls.c + ../tests/riscv-tests/benchmarks/common/crt.S +) + +GCC_CFLAGS=( + -fno-tree-loop-distribute-patterns + -nostdlib + -nostartfiles + -lgcc + -O3 --no-inline + -I../tests/custom/env + -I../tests/custom/common + -DNOPRINT +) + +GCC_OPTS="${GCC_CFLAGS[*]} ${GCC_COMMON_SRC[*]}" + +python3 cva6.py $CVA6_FLAGS --c_tests $BDIR/dhrystone/dhrystone.c --gcc_opts "$GCC_OPTS -I$BDIR/dhrystone/ $BDIR/dhrystone/dhrystone_main.c" +python3 cva6.py $CVA6_FLAGS --c_tests $BDIR/median/median.c --gcc_opts "$GCC_OPTS -I$BDIR/median/ $BDIR/median/median_main.c" +python3 cva6.py $CVA6_FLAGS --c_tests $BDIR/mm/mm.c --gcc_opts "$GCC_OPTS -I$BDIR/mm/ $BDIR/mm/mm_main.c" +python3 cva6.py $CVA6_FLAGS --c_tests $BDIR/mt-matmul/mt-matmul.c --gcc_opts "$GCC_OPTS -I$BDIR/mt-matmul/ $BDIR/mt-matmul/matmul.c" +python3 cva6.py $CVA6_FLAGS --c_tests $BDIR/mt-vvadd/mt-vvadd.c --gcc_opts "$GCC_OPTS -I$BDIR/mt-vvadd/ $BDIR/mt-vvadd/vvadd.c" +python3 cva6.py $CVA6_FLAGS --c_tests $BDIR/multiply/multiply.c --gcc_opts "$GCC_OPTS -I$BDIR/multiply/ $BDIR/multiply/multiply_main.c" +python3 cva6.py $CVA6_FLAGS --c_tests $BDIR/pmp/pmp.c --gcc_opts "$GCC_OPTS -I$BDIR/pmp/" +python3 cva6.py $CVA6_FLAGS --c_tests $BDIR/qsort/qsort_main.c --gcc_opts "$GCC_OPTS -I$BDIR/qsort/" +python3 cva6.py $CVA6_FLAGS --c_tests $BDIR/rsort/rsort.c --gcc_opts "$GCC_OPTS -I$BDIR/rsort/" +python3 cva6.py $CVA6_FLAGS --c_tests $BDIR/spmv/spmv_main.c --gcc_opts "$GCC_OPTS -I$BDIR/spmv/" +python3 cva6.py $CVA6_FLAGS --c_tests $BDIR/towers/towers_main.c --gcc_opts "$GCC_OPTS -I$BDIR/towers/" +python3 cva6.py $CVA6_FLAGS --c_tests $BDIR/vvadd/vvadd.c --gcc_opts "$GCC_OPTS -I$BDIR/vvadd/ $BDIR/vvadd/vvadd_main.c" + +make clean +make -C verif/sim clean_all + +cd - + diff --git a/verif/regress/coremark.sh b/verif/regress/coremark.sh new file mode 100644 index 0000000000..932597e3e8 --- /dev/null +++ b/verif/regress/coremark.sh @@ -0,0 +1,80 @@ +# Copyright 2022 Thales DIS design services SAS +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Original Author: Zbigniew CHAMSKI (zbigniew.chamski@thalesgroup.fr) + +noprint="" +if [ "$1" == "--no-print" ]; then + noprint="-DHAS_PRINTF=0" +fi + +# where are the tools +if ! [ -n "$RISCV" ]; then + echo "Error: RISCV variable undefined" + return +fi + +# install the required tools +source verif/regress/install-cva6.sh +source verif/regress/install-riscv-dv.sh +source verif/regress/install-riscv-compliance.sh +source verif/regress/install-riscv-tests.sh + +if ! [ -n "$DV_SIMULATORS" ]; then + DV_SIMULATORS=veri-testharness +fi + +cd verif/sim/ + +make clean +make -C verif/sim clean_all + +src0=../tests/custom/coremark/core_main.c +srcA=( + ../tests/custom/coremark/uart.c + ../tests/custom/coremark/core_list_join.c + ../tests/custom/coremark/core_matrix.c + ../tests/custom/coremark/core_portme.c + ../tests/custom/coremark/core_state.c + ../tests/custom/coremark/core_util.c + ../tests/custom/common/syscalls.c + ../tests/custom/common/crt.S +) + +cflags_opt=( + -O3 -g + -fno-tree-loop-distribute-patterns + -nostdlib + -nostartfiles + -lgcc + $noprint + -funroll-all-loops + -ffunction-sections -fdata-sections + -Wl,-gc-sections + -falign-jumps=4 -falign-functions=16 +) + +cflags=( + "${cflags_opt[@]}" + "-DCOMPILER_FLAGS='\"${cflags_opt[*]}\"'" + -DITERATIONS=2 + -DPERFORMANCE_RUN + -DSKIP_TIME_CHECK + -I../tests/custom/env + -I../tests/custom/common + -DNOPRINT +) + +set -x +python3 cva6.py \ + --target hwconfig \ + --hwconfig_opts="--default_config=cv32a6_imac_sv0 --isa=rv32imac --NrLoadPipeRegs=0" \ + --iss="$DV_SIMULATORS" \ + --iss_yaml=cva6.yaml \ + --c_tests "$src0" \ + --gcc_opts "${srcA[*]} ${cflags[*]}" \ + --linker ../tests/custom/common/test.ld diff --git a/verif/regress/dhrystone.sh b/verif/regress/dhrystone.sh new file mode 100644 index 0000000000..83a72d082c --- /dev/null +++ b/verif/regress/dhrystone.sh @@ -0,0 +1,57 @@ +# Copyright 2022 Thales DIS design services SAS +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Original Author: Zbigniew CHAMSKI (zbigniew.chamski@thalesgroup.fr) + +# where are the tools +if ! [ -n "$RISCV" ]; then + echo "Error: RISCV variable undefined" + return +fi + +# install the required tools +source verif/regress/install-cva6.sh +source verif/regress/install-riscv-dv.sh +source verif/regress/install-riscv-compliance.sh +source verif/regress/install-riscv-tests.sh + +if ! [ -n "$DV_SIMULATORS" ]; then + DV_SIMULATORS=veri-testharness +fi + +cd verif/sim + +make clean +make -C verif/sim clean_all + +src0=../tests/riscv-tests/benchmarks/dhrystone/dhrystone_main.c +srcA=( + ../tests/riscv-tests/benchmarks/dhrystone/dhrystone.c + ../tests/custom/common/syscalls.c + ../tests/custom/common/crt.S +) +cflags=( + -fno-tree-loop-distribute-patterns + -nostdlib + -nostartfiles + -lgcc + -O3 --no-inline + -I../tests/custom/env + -I../tests/custom/common + -I../tests/riscv-tests/benchmarks/dhrystone/ + -DNOPRINT +) + +set -x +python3 cva6.py \ + --target hwconfig \ + --hwconfig_opts="--default_config=cv64a6_imafdc_sv39 --isa=rv64imafdc --NrLoadPipeRegs=0" \ + --iss="$DV_SIMULATORS" \ + --iss_yaml=cva6.yaml \ + --c_tests "$src0" \ + --gcc_opts "${srcA[*]} ${cflags[*]}" \ + --linker ../tests/custom/common/test.ld diff --git a/verif/regress/dv-generated-tests.sh b/verif/regress/dv-generated-tests.sh new file mode 100644 index 0000000000..0207e216ce --- /dev/null +++ b/verif/regress/dv-generated-tests.sh @@ -0,0 +1,140 @@ +# Copyright 2022 Thales DIS SAS +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Original Author: Ayoub JALALI (ayoub.jalali@external.thalesgroup.com) + +if ! [ -n "$RISCV" ]; then + echo "Error: RISCV variable undefined" + return +fi + +# install the required tools +source verif/regress/install-cva6.sh +source verif/regress/install-riscv-dv.sh +source verif/regress/install-spike.sh + +if ! [ -n "$DV_TARGET" ]; then + DV_TARGET=cv32a60x +fi + +if ! [ -n "$DV_SIMULATORS" ]; then + DV_SIMULATORS=vcs-uvm,spike +fi + +if ! [ -n "$list_num" ]; then + list_num=1 #default test list +fi + +export cov=1 #enable the Code Coverage + +cd verif/sim/ +dd=$(date '+%Y-%m-%d') +key_word="Mismatch[1]:" +#Read from the iss_regr.log to detect the failed tests +logfile=out_$dd/iss_regr.log +TESTLIST_FILE=cva6_base_testlist.yaml +DIRECTED_TESTLIST=../tests/testlist_isacov.yaml +j=0; +rm -rf out_$dd + +if [[ "$list_num" = 1 ]];then + TEST_NAME=( + "riscv_arithmetic_basic_test_no_comp" + "riscv_arithmetic_basic_test_bcomp" + "riscv_arithmetic_basic_illegal" + "riscv_arithmetic_basic_test_comp" + "riscv_arithmetic_basic_illegal_hint_test" + "riscv_arithmetic_basic_loop_test" + ); + I=(100 100 20 100 20 20); +elif [[ "$list_num" = 2 ]];then + TEST_NAME=( + "riscv_arithmetic_basic_same_reg_test" + "riscv_arithmetic_basic_hazard_rdrs1_test" + "riscv_arithmetic_basic_hazard_rdrs2_test" + ); + I=(100 100 100); +elif [[ "$list_num" = 3 ]];then + TEST_NAME=( + "riscv_arithmetic_basic_csr_dummy" + "riscv_arithmetic_basic_Randcsr_test" + "riscv_arithmetic_basic_ebreak_dret_test" + "riscv_arithmetic_basic_illegal_csr" + ); + I=(20 20 20 20); +elif [[ "$list_num" = 4 ]];then + TEST_NAME=( + "riscv_mmu_stress_hint_test" + "riscv_mmu_stress_test" + ); + I=(100 100); +elif [[ "$list_num" = 5 ]];then + TEST_NAME=( + "riscv_load_store_test" + "riscv_load_store_cmp_test" + "riscv_load_store_hazard_test" + "riscv_unaligned_load_store_test" + ); + I=(50 50 50 50); +elif [[ "$list_num" = 6 ]];then + TEST_NAME=( + "riscv_rand_jump_hint_comp_test" + "riscv_rand_jump_no_cmp_test" + "riscv_rand_jump_illegal_test" + "riscv_arithmetic_basic_sub_prog_test" + ); + I=(75 75 50 20); +fi + +if [[ "$list_num" != 0 ]];then +if [[ ${#TEST_NAME[@]} != ${#I[@]} ]];then + echo "***********ERROR***************" + echo "The length of TEST_NAME and Iteration should be equal !!!!" + echo "Fix the length of one of the arrays" + exit +fi +printf "+====================================================================================+" +header="\n %-50s %-20s %s\n" +format=" %-50s %-20d %d\n" +printf "$header" "TEST NAME" "ITERATION" "BATCH SIZE" +printf "+====================================================================================+\n" + +while [[ $j -lt ${#TEST_NAME[@]} ]];do + printf "$format" \ + ${TEST_NAME[j]} ${I[j]} ${BZ[j]} + j=$((j+1)) +done +printf "+====================================================================================+\n" +j=0 +while [[ $j -lt ${#TEST_NAME[@]} ]];do + cp ../env/corev-dv/custom/riscv_custom_instr_enum.sv ./dv/src/isa/custom/ + python3 cva6.py --testlist=$TESTLIST_FILE --test ${TEST_NAME[j]} --iss_yaml cva6.yaml --target $DV_TARGET -cs ../env/corev-dv/target/rv32imac/ --mabi ilp32 --isa rv32imac --simulator_yaml ../env/corev-dv/simulator.yaml --iss=vcs-uvm,spike -i ${I[j]} -bz 1 --iss_timeout 300 + n=0 + echo "Generate the test: ${TEST_NAME[j]}" +#this while loop detects the failed tests from the log file and remove them + echo "Deleting failed tests: " + while read line;do + if [[ "$line" = "" ]];then + n=$((n+1)) + fi + for word in $line;do + if [[ "$word" = "$key_word" ]];then + echo -e ""${TEST_NAME[j]}"_"$n": Failed" + rm -rf vcs_results/default/vcs.d/simv.vdb/snps/coverage/db/testdata/"${TEST_NAME[j]}"_"$n"/ + fi + done + done < $logfile + rm -rf out_$dd + j=$((j+1)) +done +#Execute directed tests to improve functional coverage of ISA +j=0 +elif [[ "$list_num" = 0 ]];then + printf "==== Execute Directed tests to improve functional coverage of isa, by hitting corners !!! ====\n\n" + python3 cva6.py --testlist=$DIRECTED_TESTLIST --iss_yaml cva6.yaml --target $DV_TARGET --iss=vcs-uvm,spike +fi +cd - diff --git a/verif/regress/dv-generated-xif-tests.sh b/verif/regress/dv-generated-xif-tests.sh new file mode 100644 index 0000000000..78acaf2f32 --- /dev/null +++ b/verif/regress/dv-generated-xif-tests.sh @@ -0,0 +1,102 @@ +# Copyright 2023 Thales DIS SAS +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Original Author: Ayoub JALALI (ayoub.jalali@external.thalesgroup.com) + +if ! [ -n "$RISCV" ]; then + echo "Error: RISCV variable undefined" + return +fi + +# install the required tools +source verif/regress/install-cva6.sh +source verif/regress/install-riscv-dv.sh +source verif/regress/install-spike.sh + +if ! [ -n "$DV_TARGET" ]; then + DV_TARGET=cv32a60x +fi + +if ! [ -n "$DV_SIMULATORS" ]; then + DV_SIMULATORS=vcs-uvm,spike +fi + +if ! [ -n "$list_num" ]; then + list_num=1 #default test list +fi + +export cov=1 #enable the Code Coverage +export cvxif=1 #enable cvxif extension for Spike + +cd verif/sim/ +dd=$(date '+%Y-%m-%d') +key_word="Mismatch[1]:" +#Read from the iss_regr.log to detect the failed tests +logfile=out_$dd/iss_regr.log +TESTLIST_FILE=cva6_base_testlist.yaml +DIRECTED_TESTLIST=../tests/testlist_cvxif.yaml +j=0; +rm -rf out_$dd + +if [[ "$list_num" = 1 ]];then + TEST_NAME=( + "riscv_arithmetic_basic_xif_test" + "riscv_arithmetic_basic_xif_illegal_test" + "riscv_load_store_xif_test" + "riscv_rand_jump_xif_test" + ); + I=(100 100 100 100); +fi + +if [[ "$list_num" != 0 ]];then +if [[ ${#TEST_NAME[@]} != ${#I[@]} ]];then + echo "***********ERROR***************" + echo "The length of TEST_NAME and Iteration should be equal !!!!" + echo "Fix the length of one of the arrays" + exit +fi +printf "+====================================================================================+" +header="\n %-50s %-20s %s\n" +format=" %-50s %-20d %d\n" +printf "$header" "TEST NAME" "ITERATION" "BATCH SIZE" +printf "+====================================================================================+\n" + +while [[ $j -lt ${#TEST_NAME[@]} ]];do + printf "$format" \ + ${TEST_NAME[j]} ${I[j]} ${BZ[j]} + j=$((j+1)) +done +printf "+====================================================================================+\n" +j=0 +while [[ $j -lt ${#TEST_NAME[@]} ]];do + cp ../env/corev-dv/custom/riscv_custom_instr_enum.sv ./dv/src/isa/custom/ + python3 cva6.py --testlist=$TESTLIST_FILE --test ${TEST_NAME[j]} --iss_yaml cva6.yaml --target $DV_TARGET -cs ../env/corev-dv/target/rv32imc/ --mabi ilp32 --isa rv32imc --simulator_yaml ../env/corev-dv/simulator.yaml --iss=vcs-uvm,spike -i ${I[j]} -bz 1 --iss_timeout 300 + n=0 + echo "Generate the test: ${TEST_NAME[j]}" +#this while loop detects the failed tests from the log file and remove them + echo "Deleting failed tests: " + while read line;do + if [[ "$line" = "" ]];then + n=$((n+1)) + fi + for word in $line;do + if [[ "$word" = "$key_word" ]];then + echo -e ""${TEST_NAME[j]}"_"$n": Failed" + rm -rf vcs_results/default/vcs.d/simv.vdb/snps/coverage/db/testdata/"${TEST_NAME[j]}"_"$n"/ + fi + done + done < $logfile + rm -rf out_$dd + j=$((j+1)) +done +#Execute directed tests to improve functional coverage of ISA +j=0 +elif [[ "$list_num" = 0 ]];then + printf "==== Execute Directed tests to improve functional coverage of isa, by hitting corners !!! ====\n\n" + python3 cva6.py --testlist=$DIRECTED_TESTLIST --iss_yaml cva6.yaml --target $DV_TARGET --iss=vcs-uvm,spike +fi +cd - diff --git a/verif/regress/dv-riscv-arch-test.sh b/verif/regress/dv-riscv-arch-test.sh new file mode 100644 index 0000000000..678652e296 --- /dev/null +++ b/verif/regress/dv-riscv-arch-test.sh @@ -0,0 +1,31 @@ +# Copyright 2021 Thales DIS design services SAS +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Original Author: Jean-Roch COULON - Thales + +# where are the tools +if ! [ -n "$RISCV" ]; then + echo "Error: RISCV variable undefined" + return +fi + +# install the required tools +source verif/regress/install-cva6.sh +source verif/regress/install-riscv-dv.sh +source verif/regress/install-riscv-arch-test.sh + +if ! [ -n "$DV_TARGET" ]; then + DV_TARGET=cv64a6_imafdc_sv39 +fi + +if ! [ -n "$DV_SIMULATORS" ]; then + DV_SIMULATORS=veri-testharness,spike +fi + +cd verif/sim +python3 cva6.py --testlist=../tests/testlist_riscv-arch-test-$DV_TARGET.yaml --target $DV_TARGET --iss_yaml=cva6.yaml --iss=$DV_SIMULATORS $DV_OPTS --linker=../tests/riscv-arch-test/riscv-target/spike/link.ld +cd - diff --git a/verif/regress/dv-riscv-compliance.sh b/verif/regress/dv-riscv-compliance.sh new file mode 100755 index 0000000000..25cfb2af58 --- /dev/null +++ b/verif/regress/dv-riscv-compliance.sh @@ -0,0 +1,31 @@ +# Copyright 2021 Thales DIS design services SAS +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Original Author: Jean-Roch COULON - Thales + +# where are the tools +if ! [ -n "$RISCV" ]; then + echo "Error: RISCV variable undefined" + return +fi + +# install the required tools +source verif/regress/install-cva6.sh +source verif/regress/install-riscv-dv.sh +source verif/regress/install-riscv-compliance.sh + +if ! [ -n "$DV_TARGET" ]; then + DV_TARGET=cv64a6_imafdc_sv39 +fi + +if ! [ -n "$DV_SIMULATORS" ]; then + DV_SIMULATORS=veri-testharness,spike +fi + +cd verif/sim +python3 cva6.py --testlist=../tests/testlist_riscv-compliance-$DV_TARGET.yaml --target $DV_TARGET --iss_yaml=cva6.yaml --iss=$DV_SIMULATORS $DV_OPTS +cd - diff --git a/verif/regress/dv-riscv-csr-access-test.sh b/verif/regress/dv-riscv-csr-access-test.sh new file mode 100644 index 0000000000..3cdcf7c210 --- /dev/null +++ b/verif/regress/dv-riscv-csr-access-test.sh @@ -0,0 +1,33 @@ +# Copyright 2021 Thales DIS design services SAS +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Original Author: Jean-Roch COULON - Thales + +# where are the tools +if ! [ -n "$RISCV" ]; then + echo "Error: RISCV variable undefined" + return +fi + +# install the required tools +source verif/regress/install-cva6.sh +source verif/regress/install-riscv-dv.sh +source verif/regress/install-riscv-arch-test.sh + +if ! [ -n "$DV_TARGET" ]; then + DV_TARGET=cv32a60x +fi + +if ! [ -n "$DV_SIMULATORS" ]; then + DV_SIMULATORS=veri-testharness,spike +fi + +cd verif/sim +python3 cva6.py --testlist=../tests/testlist_riscv-csr-access-test-$DV_TARGET.yaml --target $DV_TARGET --iss_yaml=cva6.yaml --iss=$DV_SIMULATORS $DV_OPTS --linker=../sim/link.ld + +cd - + diff --git a/verif/regress/dv-riscv-tests.sh b/verif/regress/dv-riscv-tests.sh new file mode 100755 index 0000000000..71be0abd72 --- /dev/null +++ b/verif/regress/dv-riscv-tests.sh @@ -0,0 +1,39 @@ +# Copyright 2021 Thales DIS design services SAS +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Original Author: Jean-Roch COULON - Thales + +# where are the tools +if ! [ -n "$RISCV" ]; then + echo "Error: RISCV variable undefined" + return +fi + +# install the required tools +source verif/regress/install-cva6.sh +source verif/regress/install-riscv-dv.sh +source verif/regress/install-riscv-tests.sh + +if ! [ -n "$DV_TARGET" ]; then + DV_TARGET=cv64a6_imafdc_sv39 +fi + +if ! [ -n "$DV_SIMULATORS" ]; then + DV_SIMULATORS=veri-testharness,spike +fi + +if ! [ -n "$DV_TESTLISTS" ]; then + DV_TESTLISTS="../tests/testlist_riscv-tests-$DV_TARGET-p.yaml \ + ../tests/testlist_riscv-tests-$DV_TARGET-v.yaml" +fi + +cd verif/sim +for TESTLIST in $DV_TESTLISTS +do + python3 cva6.py --testlist=$TESTLIST --target $DV_TARGET --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml $DV_OPTS +done +cd - diff --git a/verif/regress/hwconfig_tests.sh b/verif/regress/hwconfig_tests.sh new file mode 100644 index 0000000000..aa95bd7c68 --- /dev/null +++ b/verif/regress/hwconfig_tests.sh @@ -0,0 +1,30 @@ +# Copyright 2022 Thales DIS design services SAS +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Original Author: Guillaume Chauvon (guillaume.chauvon@thalesgroup.com) + +# where are the tools +if ! [ -n "$RISCV" ]; then + echo "Error: RISCV variable undefined" + return +fi + +# install the required tools +source verif/regress/install-cva6.sh +source verif/regress/install-riscv-dv.sh +source verif/regress/install-riscv-tests.sh + +if ! [ -n "$DV_SIMULATORS" ]; then + DV_SIMULATORS=veri-testharness,spike +fi + +cd verif/sim/ +python3 cva6.py --testlist=../tests/testlist_hwconfig.yaml --iss_yaml cva6.yaml --target hwconfig --hwconfig_opts="$DV_HWCONFIG_OPTS" --iss=$DV_SIMULATORS +make -C ../.. clean +make clean_all + +cd - diff --git a/verif/regress/install-cva6.sh b/verif/regress/install-cva6.sh new file mode 100755 index 0000000000..f403c1e33b --- /dev/null +++ b/verif/regress/install-cva6.sh @@ -0,0 +1,82 @@ +# Copyright 2021 Thales DIS design services SAS +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Original Author: Jean-Roch COULON - Thales + +# Customise this to a fast local disk +export ROOT_PROJECT=$(readlink -f $(dirname "${BASH_SOURCE[0]}")/../../) +export TOP="$ROOT_PROJECT/tools" + +# where to install the tools +if [ -z "$RISCV" ]; then + echo "Error: RISCV variable undefined." + return +fi + +if [ -z "$CV_SW_PREFIX" ]; then + export CV_SW_PREFIX="$(ls -1 -r $RISCV/bin/riscv*-gcc | head -n 1| grep gcc | rev | cut -d '/' -f 1 | cut -d '-' -f 2- | rev)-" +fi + +if [ -z "$RISCV_GCC" ]; then + export RISCV_GCC=$RISCV/bin/${CV_SW_PREFIX}gcc +fi + +if [ -z "$RISCV_OBJCOPY" ]; then + export RISCV_OBJCOPY=$RISCV/bin/${CV_SW_PREFIX}objcopy +fi + +# Set up tool-related variables. +export PATH="$RISCV/bin:$PATH" +export LIBRARY_PATH="$RISCV/lib" +export LD_LIBRARY_PATH="$RISCV/lib:$LD_LIBRARY_PATH" +export C_INCLUDE_PATH="$RISCV/include" +export CPLUS_INCLUDE_PATH="$RISCV/include" + +# Install Verilator v5. +# Set VERILATOR_INSTALL_DIR to 'NO' to skip installation and checks +# of Verilator (useful for CI jobs not depending on Verilator in any way). +if [ "$VERILATOR_INSTALL_DIR" != "NO" ]; then + source verif/regress/install-verilator.sh + + # Complain if the installation directory of Verilator still is not set + # after running the installer. + if [ -z "$VERILATOR_INSTALL_DIR" ]; then + echo "Error: VERILATOR_INSTALL_DIR variable still undefined after running Verilator installer." + return + fi + + # Verilator was set up: add Verilator paths to appropriate variables. + export PATH="$VERILATOR_INSTALL_DIR/bin:$PATH" + export C_INCLUDE_PATH="$VERILATOR_INSTALL_DIR/share/verilator/include:$C_INCLUDE_PATH" + export CPLUS_INCLUDE_PATH="$VERILATOR_INSTALL_DIR/share/verilator/include:$CPLUS_INCLUDE_PATH" + + echo "Verilator version:" + verilator --version || { echo "Error: Verilator not in \$PATH." ; return ; } +else + echo "Skipping Verilator setup on user's request (\$VERILATOR_INSTALL_DIR = \"NO\")." +fi + +# number of parallel jobs to use for make commands and simulation +export NUM_JOBS=24 + +# install the required tools for cva6 +if [ -z "$CVA6_REPO" ]; then + CVA6_REPO="https://github.com/openhwgroup/cva6.git" + CVA6_BRANCH="master" + CVA6_HASH="853fb4bee5ca6e36e39dc3c272a97f49d95c3c1d" + CVA6_PATCH= +fi +echo $CVA6_REPO +echo $CVA6_BRANCH +echo $CVA6_HASH +echo $CVA6_PATCH + +# install Spike +if [ -z "$SPIKE_ROOT" ]; then + export SPIKE_ROOT=$TOP/spike/ +fi +source verif/regress/install-spike.sh diff --git a/verif/regress/install-riscv-arch-test.sh b/verif/regress/install-riscv-arch-test.sh new file mode 100644 index 0000000000..7d5c858216 --- /dev/null +++ b/verif/regress/install-riscv-arch-test.sh @@ -0,0 +1,35 @@ +# Copyright 2021 Thales DIS design services SAS +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Original Author: Jean-Roch COULON - Thales + +# riscv-arch-tests uses definition of RVMODEL_HALT provided by Spike. +. verif/regress/install-spike.sh +if [ ! -d $SPIKE_SRC_DIR/arch_test_target ]; then + echo "*** Variable SPIKE_SRC_DIR must point to a source-based installation of Spike." + return 1 +fi + +if ! [ -n "$ARCH_TEST_REPO" ]; then + ARCH_TEST_REPO=https://github.com/riscv-non-isa/riscv-arch-test + ARCH_TEST_BRANCH=main + ARCH_TEST_HASH="46cf99d0e020887e398508fc776928a1adad7c23" +fi +echo "Repo: " $ARCH_TEST_REPO +echo "Branch:" $ARCH_TEST_BRANCH +echo "Hash: " $ARCH_TEST_HASH + + +mkdir -p verif/tests +if ! [ -d verif/tests/riscv-arch-test ]; then + git clone $ARCH_TEST_REPO -b $ARCH_TEST_BRANCH verif/tests/riscv-arch-test + cd verif/tests/riscv-arch-test; git checkout $ARCH_TEST_HASH; + # Copy Spike definitions to the corresponding riscv-target subdirectory. + cp -rpa $SPIKE_SRC_DIR/arch_test_target riscv-target + cd - +fi + diff --git a/verif/regress/install-riscv-compliance.sh b/verif/regress/install-riscv-compliance.sh new file mode 100755 index 0000000000..980ccf9107 --- /dev/null +++ b/verif/regress/install-riscv-compliance.sh @@ -0,0 +1,30 @@ +# Copyright 2021 Thales DIS design services SAS +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Original Author: Jean-Roch COULON - Thales + +if ! [ -n "$COMPLIANCE_REPO" ]; then + COMPLIANCE_REPO="https://github.com/riscv-non-isa/riscv-arch-test.git" + COMPLIANCE_BRANCH="main" + COMPLIANCE_HASH="220e78542da4510e40eac31e31fdd4e77cdae437" + COMPLIANCE_PATCH="../../../verif/regress/riscv-compliance.patch" +fi +echo "Repo: " $COMPLIANCE_REPO +echo "Branch:" $COMPLIANCE_BRANCH +echo "Hash: " $COMPLIANCE_HASH +echo "Patch: " $COMPLIANCE_PATCH + +mkdir -p verif/tests +if ! [ -d verif/tests/riscv-compliance ]; then + git clone $COMPLIANCE_REPO -b $COMPLIANCE_BRANCH verif/tests/riscv-compliance + cd verif/tests/riscv-compliance; git checkout $COMPLIANCE_HASH; + if [[ -n "$COMPLIANCE_PATCH" && -f "$COMPLIANCE_PATCH" ]]; then + echo "Applying patch $COMPLIANCE_PATCH in $PWD..." + git apply "$COMPLIANCE_PATCH" + fi + cd - +fi diff --git a/verif/regress/install-riscv-dv.sh b/verif/regress/install-riscv-dv.sh new file mode 100755 index 0000000000..7e34d04159 --- /dev/null +++ b/verif/regress/install-riscv-dv.sh @@ -0,0 +1,45 @@ +# Copyright 2021 Thales DIS design services SAS +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Original Author: Jean-Roch COULON - Thales + +# riscv-dv env variables +export RISCV_TOOLCHAIN=$RISCV +if [ -z "$RISCV_GCC" ]; then + export RISCV_GCC="$RISCV_TOOLCHAIN/bin/riscv-none-elf-gcc" +fi +if [ -z "$RISCV_OBJCOPY" ]; then + export RISCV_OBJCOPY="$RISCV_TOOLCHAIN/bin/riscv-none-elf-objcopy" +fi +export SPIKE_PATH=$SPIKE_ROOT/bin +export RTL_PATH=$ROOT_PROJECT/ +export TB_PATH=$ROOT_PROJECT/verif/tb/core +export TESTS_PATH=$ROOT_PROJECT/verif/tests + +if [ -z "$DV_REPO" ]; then + export DV_REPO="https://github.com/google/riscv-dv.git" + export DV_BRANCH="master" + export DV_HASH="96c1ee6f371f2754c45b4831fcab95f6671689d9" + export DV_PATCH= +fi +echo "Repo: " $DV_REPO +echo "Branch:" $DV_BRANCH +echo "Hash: " $DV_HASH +echo "Patch: " $DV_PATCH + +mkdir -p verif/sim +if ! [ -d verif/sim/dv ]; then + git clone $DV_REPO -b $DV_BRANCH verif/sim/dv + cd verif/sim/dv; git checkout $DV_HASH; + if [[ -n "$DV_PATCH" && -f "$DV_PATCH" ]]; then + git apply "$DV_PATCH" + fi + cd - + # install riscv-dv dependencies + cd verif/sim/dv; pip3 install -r requirements.txt; cd - +fi + diff --git a/verif/regress/install-riscv-tests.sh b/verif/regress/install-riscv-tests.sh new file mode 100755 index 0000000000..1c1a707848 --- /dev/null +++ b/verif/regress/install-riscv-tests.sh @@ -0,0 +1,26 @@ +# Copyright 2021 Thales DIS design services SAS +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Original Author: Jean-Roch COULON - Thales + +if ! [ -n "$TESTS_REPO" ]; then + TESTS_REPO="https://github.com/riscv/riscv-tests.git" + TESTS_BRANCH="master" + TESTS_HASH="f92842f91644092960ac7946a61ec2895e543cec" +fi +echo "Repo: " $TESTS_REPO +echo "Branch:" $TESTS_BRANCH +echo "Hash: " $TESTS_HASH + +mkdir -p verif/tests +if ! [ -d verif/tests/riscv-tests ]; then + git clone $TESTS_REPO -b $TESTS_BRANCH verif/tests/riscv-tests + cd verif/tests/riscv-tests; git checkout $TESTS_HASH; + git submodule update --init --recursive + git apply --directory=env ../../../verif/regress/riscv-tests-env.patch + cd - +fi diff --git a/verif/regress/install-spike.sh b/verif/regress/install-spike.sh new file mode 100755 index 0000000000..f9dd05b3fb --- /dev/null +++ b/verif/regress/install-spike.sh @@ -0,0 +1,60 @@ +# Copyright 2021-2023 Thales DIS design services SAS +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Original Author: Jean-Roch COULON - Thales + +if [ -z ${NUM_JOBS} ]; then + NUM_JOBS=1 +fi + +# Set SPIKE_ROOT to 'NO' to skip the installation/checks of Spike altogether. +# This is useful for CI jobs not depending on Spike in any way. +# Otherwise expect/perform Spike installation in directory $SPIKE_ROOT +# which defaults to $ROOT_PROJECT/tools/spike. +if [ -z "$SPIKE_ROOT" ]; then + # Set the default location if not provided by caller. + export SPIKE_ROOT=$ROOT_PROJECT/tools/spike +fi + +if [ "$SPIKE_ROOT" = "NO" ]; then + echo "NOTE: Skipping Spike setup on user's request (\$SPIKE_ROOT = \"NO\")." +else + # Export the location of Spike source code. + export SPIKE_SRC_DIR=$ROOT_PROJECT/vendor/riscv/riscv-isa-sim + + # Check if a local copy of Spike should be built/used ($SPIKE_INSTALL_DIR non empty). + # A value equal to '__local__' means $ROOT_PROJECT/tools/spike (same as $TOP/spike). + if [ -n "$SPIKE_INSTALL_DIR" ]; then + # Handle the 'default' value. + if [ "$SPIKE_INSTALL_DIR" = "__local__" ]; then + export SPIKE_INSTALL_DIR="$ROOT_PROJECT/tools/spike" + fi + # Override SPIKE_ROOT value with $SPIKE_INSTALL_DIR (the latter takes priority.) + echo "NOTE: Overriding SPIKE_ROOT value ('$SPIKE_ROOT') with \$SPIKE_INSTALL_DIR ('$SPIKE_INSTALL_DIR')." + export SPIKE_ROOT="$SPIKE_INSTALL_DIR" + # Do not clean up the destination directory: leave that to the user (real or CI job). + fi + + # Rebuild Spike or reuse an existing Spike build. + if [ ! -d "$SPIKE_ROOT" -o ! -f "$SPIKE_ROOT/bin/spike" ]; then + echo "Installing Spike in '$SPIKE_ROOT'..." + # Keep track of current working dir. + CALLER_DIR=$(readlink -f $(pwd)) + # Enter the vendorized tree. It already captures the desired Spike config. + cd $SPIKE_SRC_DIR + # Build and install Spike (including extensions). + mkdir -p build + cd build + ../configure --enable-commitlog --prefix="$SPIKE_ROOT" + make -j${NUM_JOBS} + make install + cd $CALLER_DIR + else + echo "Using Spike from cached directory '$SPIKE_ROOT'." + fi +fi + diff --git a/verif/regress/install-verilator.sh b/verif/regress/install-verilator.sh new file mode 100755 index 0000000000..26ed703e4d --- /dev/null +++ b/verif/regress/install-verilator.sh @@ -0,0 +1,78 @@ +# Copyright 2021 Thales DIS design services SAS +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Original Author: Jean-Roch COULON - Thales + +if [ -z "$NUM_JOBS" ]; then + NUM_JOBS=1 +fi + +# Ensure the location of tools is known (usually, .../core-v-verif/tools). +if [ -z "$TOP" ]; then + echo "Error: location of core-v-verif 'tools' tree (\$TOP) is not defined." + return +fi + +VERILATOR_REPO="https://github.com/verilator/verilator.git" +VERILATOR_BRANCH="master" +# Use the release tag instead of a full SHA1 hash. +VERILATOR_HASH="v5.008" +VERILATOR_PATCH="$TOP/../verif/regress/verilator-v5.patch" + +# Unset historical variable VERILATOR_ROOT as it collides with the build process. +if [ -n "$VERILATOR_ROOT" ]; then + unset VERILATOR_ROOT +fi + +# Define the default src+build location of Verilator. +# No need to force this location in Continuous Integration scripts. +if [ -z "$VERILATOR_BUILD_DIR" ]; then + export VERILATOR_BUILD_DIR=${TOP}/verilator-$VERILATOR_HASH/verilator +fi + +# Define the default installation location of Verilator: one level up +# from the source tree in the core-v-verif tree. +# Continuous Integration may need to override this particular variable +# to use a preinstalled build of Verilator. +if [ -z "$VERILATOR_INSTALL_DIR" ]; then + export VERILATOR_INSTALL_DIR="$(dirname $VERILATOR_BUILD_DIR)" +fi + +# Build and install Verilator only if not already installed at the expected +# location $VERILATOR_INSTALL_DIR. +if [ ! -f "$VERILATOR_INSTALL_DIR/bin/verilator" ]; then + echo "Building Verilator in $VERILATOR_BUILD_DIR..." + echo "Verilator will be installed in $VERILATOR_INSTALL_DIR" + echo "VERILATOR_REPO=$VERILATOR_REPO" + echo "VERILATOR_BRANCH=$VERILATOR_BRANCH" + echo "VERILATOR_HASH=$VERILATOR_HASH" + echo "VERILATOR_PATCH=$VERILATOR_PATCH" + mkdir -p $VERILATOR_BUILD_DIR + cd $VERILATOR_BUILD_DIR + # Clone only if the ".git" directory does not exist. + # Do not remove the content arbitrarily if ".git" does not exist in order + # to preserve user content - let git fail instead. + [ -d .git ] || git clone $VERILATOR_REPO -b $VERILATOR_BRANCH . + git checkout $VERILATOR_HASH + if [[ -n "$VERILATOR_PATCH" && -f "$VERILATOR_PATCH" ]] ; then + git apply $VERILATOR_PATCH || true + fi + # Generate the config script and configure Verilator. + autoconf && ./configure --prefix="$VERILATOR_INSTALL_DIR" && make -j${NUM_JOBS} + # FORNOW: Accept failure in 'make test' (segfault issue on Debian10) + make test || true + echo "Installing Verilator in $VERILATOR_INSTALL_DIR..." + make install + #make test || echo "### 'make test' in $VERILATOR_ROOT: some tests failed." + cd - +else + echo "Using Verilator from cached directory $VERILATOR_INSTALL_DIR." +fi + +# Update PATH to match the verilator installation. +export PATH="$VERILATOR_INSTALL_DIR/bin:$PATH" + diff --git a/verif/regress/iss-tests.sh b/verif/regress/iss-tests.sh new file mode 100644 index 0000000000..f1e3978931 --- /dev/null +++ b/verif/regress/iss-tests.sh @@ -0,0 +1,33 @@ +# Copyright 2021 Thales DIS design services SAS +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Original Author: Guillaume CHAUVON (guillaume.chauvon@thalesgroup.fr) + +# where are the tools +if ! [ -n "$RISCV" ]; then + echo "Error: RISCV variable undefined" + return +fi + +# install the required tools +source verif/regress/install-cva6.sh +source verif/regress/install-riscv-dv.sh +source verif/regress/install-riscv-compliance.sh + +if ! [ -n "$DV_SIMULATORS" ]; then + echo "Error DV_SIMULATORS variable undefined" +fi +if ! [ -n "$DV_TARGET" ]; then + echo "Error DV_TARGET variable undefined" +fi + +cd verif/sim/ +python3 cva6.py --target $DV_TARGET --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml --testlist=../tests/testlist_riscv-compliance-$DV_TARGET.yaml --test rv32ui-addi +make clean +make -C verif/sim clean_all + +cd - diff --git a/verif/regress/issue-tests.sh b/verif/regress/issue-tests.sh new file mode 100644 index 0000000000..537e98a855 --- /dev/null +++ b/verif/regress/issue-tests.sh @@ -0,0 +1,34 @@ +# Copyright 2022 Thales DIS France +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Original Author: Zbigniew CHAMSKI (zbigniew.chamski@thalesgroup.fr) + +# where are the tools +if ! [ -n "$RISCV" ]; then + echo "Error: RISCV variable undefined" + return +fi + +# install the required tools +source verif/regress/install-cva6.sh +source verif/regress/install-riscv-dv.sh +source verif/regress/install-riscv-compliance.sh +source verif/regress/install-riscv-tests.sh + +if ! [ -n "$DV_SIMULATORS" ]; then + DV_SIMULATORS=veri-testharness,spike +fi + +cd verif/sim/ +python3 cva6.py --testlist=../tests/testlist_issues.yaml --test compressed-fpreg-commits-rv64 --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS +make clean +make -C verif/sim clean_all +python3 cva6.py --testlist=../tests/testlist_issues.yaml --test compressed-fpreg-commits-rv32 --iss_yaml cva6.yaml --target cv32a6_imafc_sv32 --iss=$DV_SIMULATORS $DV_OPTS +make clean +make -C verif/sim clean_all + +cd - diff --git a/verif/regress/linux.sh b/verif/regress/linux.sh new file mode 100644 index 0000000000..9e28465348 --- /dev/null +++ b/verif/regress/linux.sh @@ -0,0 +1,35 @@ +# Copyright 2021 Thales DIS design services SAS +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Original Author: Jean-Roch COULON - Thales + +# where are the tools +if ! [ -n "$RISCV" ]; then + echo "Error: RISCV variable undefined" + return +fi + +if ! [ -n "$BBL_ROOT" ]; then + echo "Error: BBL_ROOT variable undefined" + echo "BBL_ROOT is the path to access bbl.o" + echo "bbl.o is generated by using https://github.com/pulp-platform/ariane-sdk.git" + return 1 +fi + +# install the required tools +source verif/regress/install-cva6.sh +source verif/regress/install-riscv-dv.sh + +if ! [ -n "$DV_SIMULATORS" ]; then + DV_SIMULATORS=veri-testharness +fi + +cd verif/sim +cp $BBL_ROOT/bbl bbl.o +python3 cva6.py --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml --elf_tests bbl.o\ + --issrun_opts="+time_out=40000000 +debug_disable=1" --isspostrun_opts="ffffffe0005e5cd4" +cd - diff --git a/verif/regress/llvm-riscv-compliance.patch b/verif/regress/llvm-riscv-compliance.patch new file mode 100644 index 0000000000..85f0dfe056 --- /dev/null +++ b/verif/regress/llvm-riscv-compliance.patch @@ -0,0 +1,240 @@ +diff --git a/riscv-test-env/p/riscv_test.h b/riscv-test-env/p/riscv_test.h +index eaa6758..d655d3c 100644 +--- a/riscv-test-env/p/riscv_test.h ++++ b/riscv-test-env/p/riscv_test.h +@@ -66,7 +66,7 @@ + #define INIT_SPTBR \ + la t0, 1f; \ + csrw mtvec, t0; \ +- csrwi sptbr, 0; \ ++ csrwi satp, 0; \ + .align 2; \ + 1: + +diff --git a/riscv-test-env/v/entry.S b/riscv-test-env/v/entry.S +index 9719662..a9ae411 100644 +--- a/riscv-test-env/v/entry.S ++++ b/riscv-test-env/v/entry.S +@@ -111,12 +111,12 @@ trap_entry: + csrrw t0,sscratch,sp + STORE t0,2*REGBYTES(sp) + +- # get sr, epc, badvaddr, cause ++ # get sr, epc, tval, cause + csrr t0,sstatus + STORE t0,32*REGBYTES(sp) + csrr t0,sepc + STORE t0,33*REGBYTES(sp) +- csrr t0,sbadaddr ++ csrr t0,stval + STORE t0,34*REGBYTES(sp) + csrr t0,scause + STORE t0,35*REGBYTES(sp) +diff --git a/riscv-test-env/v/vm.c b/riscv-test-env/v/vm.c +index 6ab7fd1..3486475 100644 +--- a/riscv-test-env/v/vm.c ++++ b/riscv-test-env/v/vm.c +@@ -230,7 +230,7 @@ void vm_boot(uintptr_t test_addr) + l1pt[PTES_PER_PT-1] = (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_R | PTE_W | PTE_X | PTE_A | PTE_D; + uintptr_t vm_choice = SPTBR_MODE_SV32; + #endif +- write_csr(sptbr, ((uintptr_t)l1pt >> PGSHIFT) | ++ write_csr(satp, ((uintptr_t)l1pt >> PGSHIFT) | + (vm_choice * (SPTBR_MODE & ~(SPTBR_MODE<<1)))); + + // Set up PMPs if present, ignoring illegal instruction trap if not. +diff --git a/riscv-test-suite/rv32i/src/I-EBREAK-01.S b/riscv-test-suite/rv32i/src/I-EBREAK-01.S +index 958eebc..b84559f 100644 +--- a/riscv-test-suite/rv32i/src/I-EBREAK-01.S ++++ b/riscv-test-suite/rv32i/src/I-EBREAK-01.S +@@ -71,6 +71,7 @@ RV_COMPLIANCE_CODE_BEGIN + + # --------------------------------------------------------------------------------------------- + # Exception handler ++ .align 2 + _trap_handler: + # increment return address + csrr x30, mepc +diff --git a/riscv-test-suite/rv32i/src/I-ECALL-01.S b/riscv-test-suite/rv32i/src/I-ECALL-01.S +index 5278207..d181526 100644 +--- a/riscv-test-suite/rv32i/src/I-ECALL-01.S ++++ b/riscv-test-suite/rv32i/src/I-ECALL-01.S +@@ -73,6 +73,7 @@ RV_COMPLIANCE_CODE_BEGIN + + # --------------------------------------------------------------------------------------------- + # Exception handler ++ .align 2 + _trap_handler: + # increment return address + csrr x30, mepc +diff --git a/riscv-test-suite/rv32i/src/I-MISALIGN_JMP-01.S b/riscv-test-suite/rv32i/src/I-MISALIGN_JMP-01.S +index 8f54534..79461b8 100644 +--- a/riscv-test-suite/rv32i/src/I-MISALIGN_JMP-01.S ++++ b/riscv-test-suite/rv32i/src/I-MISALIGN_JMP-01.S +@@ -277,14 +277,15 @@ RV_COMPLIANCE_CODE_BEGIN + + # --------------------------------------------------------------------------------------------- + # Exception handler ++ .align 2 + _trap_handler: + # increment return address +- csrr x30, mbadaddr ++ csrr x30, mtval + addi x30, x30, -2 + csrw mepc, x30 + +- # store low bits of mbadaddr +- csrr x30, mbadaddr ++ # store low bits of mtval ++ csrr x30, mtval + andi x30, x30, 3 + sw x30, 0(x1) + +diff --git a/riscv-test-suite/rv32i/src/I-MISALIGN_LDST-01.S b/riscv-test-suite/rv32i/src/I-MISALIGN_LDST-01.S +index 5a20187..9d3f668 100644 +--- a/riscv-test-suite/rv32i/src/I-MISALIGN_LDST-01.S ++++ b/riscv-test-suite/rv32i/src/I-MISALIGN_LDST-01.S +@@ -188,14 +188,15 @@ RV_COMPLIANCE_CODE_BEGIN + + # --------------------------------------------------------------------------------------------- + # Exception handler ++ .align 2 + _trap_handler: + # increment return address + csrr x30, mepc + addi x30, x30, 4 + csrw mepc, x30 + +- # store low bits of mbadaddr +- csrr x30, mbadaddr ++ # store low bits of mtval ++ csrr x30, mtval + andi x30, x30, 3 + sw x30, 0(x1) + +diff --git a/riscv-test-suite/rv32mi/rv64mi/illegal.S b/riscv-test-suite/rv32mi/rv64mi/illegal.S +index 4d859a8..c78a6fc 100644 +--- a/riscv-test-suite/rv32mi/rv64mi/illegal.S ++++ b/riscv-test-suite/rv32mi/rv64mi/illegal.S +@@ -72,19 +72,19 @@ bad4: + wfi + j fail + +- # Make sure SFENCE.VMA and sptbr don't trap when TVM=0. ++ # Make sure SFENCE.VMA and satp don't trap when TVM=0. + sfence.vma +- csrr t0, sptbr ++ csrr t0, satp + bad5: + .word 0 + j fail + + bad6: +- # Make sure SFENCE.VMA and sptbr do trap when TVM=1. ++ # Make sure SFENCE.VMA and satp do trap when TVM=1. + sfence.vma + j fail + bad7: +- csrr t0, sptbr ++ csrr t0, satp + j fail + + # Make sure SRET doesn't trap when TSR=0. +@@ -135,8 +135,8 @@ synchronous_exception: + bne t0, t1, fail + csrr t0, mepc + +- # Make sure mbadaddr contains either 0 or the instruction word. +- csrr t2, mbadaddr ++ # Make sure mtval contains either 0 or the instruction word. ++ csrr t2, mtval + beqz t2, 1f + lhu t3, 0(t0) + lhu t4, 2(t0) +diff --git a/riscv-test-suite/rv32mi/rv64mi/ma_addr.S b/riscv-test-suite/rv32mi/rv64mi/ma_addr.S +index c35f147..3428323 100644 +--- a/riscv-test-suite/rv32mi/rv64mi/ma_addr.S ++++ b/riscv-test-suite/rv32mi/rv64mi/ma_addr.S +@@ -102,7 +102,7 @@ mtvec_handler: + csrr t0, mcause + bne t0, s1, fail + +- csrr t0, mbadaddr ++ csrr t0, mtval + bne t0, t1, fail + + lb t0, (t0) +diff --git a/riscv-test-suite/rv32mi/rv64si/dirty.S b/riscv-test-suite/rv32mi/rv64si/dirty.S +index 26f185f..6390bfe 100644 +--- a/riscv-test-suite/rv32mi/rv64si/dirty.S ++++ b/riscv-test-suite/rv32mi/rv64si/dirty.S +@@ -18,7 +18,7 @@ RV_COMPLIANCE_CODE_BEGIN + la a1, page_table_1 + srl a1, a1, RISCV_PGSHIFT + or a1, a1, a0 +- csrw sptbr, a1 ++ csrw satp, a1 + sfence.vma + + # Set up MPRV with MPP=S, so loads and stores use S-mode +diff --git a/riscv-test-suite/rv32mi/rv64si/ma_fetch.S b/riscv-test-suite/rv32mi/rv64si/ma_fetch.S +index e52ab83..185051d 100644 +--- a/riscv-test-suite/rv32mi/rv64si/ma_fetch.S ++++ b/riscv-test-suite/rv32mi/rv64si/ma_fetch.S +@@ -19,7 +19,7 @@ RV_COMPLIANCE_CODE_BEGIN + #define sscratch mscratch + #define sstatus mstatus + #define scause mcause +- #define sbadaddr mbadaddr ++ #define stval mtval + #define sepc mepc + #define sret mret + #define stvec_handler mtvec_handler +@@ -192,8 +192,8 @@ stvec_handler: + addi a1, a1, 4 + bne t0, a1, fail + +- # verify that badaddr == 0 or badaddr == t0+2. +- csrr a0, sbadaddr ++ # verify that tval == 0 or tval == t0+2. ++ csrr a0, stval + beqz a0, 1f + addi a0, a0, -2 + bne a0, t0, fail +diff --git a/riscv-test-suite/rv32si/rv64si/dirty.S b/riscv-test-suite/rv32si/rv64si/dirty.S +index 1a324a8..2d684a4 100644 +--- a/riscv-test-suite/rv32si/rv64si/dirty.S ++++ b/riscv-test-suite/rv32si/rv64si/dirty.S +@@ -21,7 +21,7 @@ RV_COMPLIANCE_CODE_BEGIN + la a1, page_table_1 + srl a1, a1, RISCV_PGSHIFT + or a1, a1, a0 +- csrw sptbr, a1 ++ csrw satp, a1 + sfence.vma + + # Set up MPRV with MPP=S, so loads and stores use S-mode +diff --git a/riscv-test-suite/rv32si/rv64si/ma_fetch.S b/riscv-test-suite/rv32si/rv64si/ma_fetch.S +index e52ab83..185051d 100644 +--- a/riscv-test-suite/rv32si/rv64si/ma_fetch.S ++++ b/riscv-test-suite/rv32si/rv64si/ma_fetch.S +@@ -19,7 +19,7 @@ RV_COMPLIANCE_CODE_BEGIN + #define sscratch mscratch + #define sstatus mstatus + #define scause mcause +- #define sbadaddr mbadaddr ++ #define stval mtval + #define sepc mepc + #define sret mret + #define stvec_handler mtvec_handler +@@ -192,8 +192,8 @@ stvec_handler: + addi a1, a1, 4 + bne t0, a1, fail + +- # verify that badaddr == 0 or badaddr == t0+2. +- csrr a0, sbadaddr ++ # verify that tval == 0 or tval == t0+2. ++ csrr a0, stval + beqz a0, 1f + addi a0, a0, -2 + bne a0, t0, fail diff --git a/verif/regress/llvm-riscv-tests-env.patch b/verif/regress/llvm-riscv-tests-env.patch new file mode 100644 index 0000000000..8eebbd651d --- /dev/null +++ b/verif/regress/llvm-riscv-tests-env.patch @@ -0,0 +1,47 @@ +diff --git a/p/riscv_test.h b/p/riscv_test.h +index 88ca6c1..3bd4767 100644 +--- a/p/riscv_test.h ++++ b/p/riscv_test.h +@@ -110,7 +110,7 @@ + #define INIT_SATP \ + la t0, 1f; \ + csrw mtvec, t0; \ +- csrwi sptbr, 0; \ ++ csrwi satp, 0; \ + .align 2; \ + 1: + +diff --git a/v/entry.S b/v/entry.S +index fa492e6..5924ee9 100644 +--- a/v/entry.S ++++ b/v/entry.S +@@ -148,12 +148,12 @@ trap_entry: + csrrw t0,sscratch,sp + STORE t0,2*REGBYTES(sp) + +- # get sr, epc, badvaddr, cause ++ # get sr, epc, tval, cause + csrr t0,sstatus + STORE t0,32*REGBYTES(sp) + csrr t0,sepc + STORE t0,33*REGBYTES(sp) +- csrr t0,sbadaddr ++ csrr t0,stval + STORE t0,34*REGBYTES(sp) + csrr t0,scause + STORE t0,35*REGBYTES(sp) +diff --git a/v/vm.c b/v/vm.c +index 6bf05f7..71700f5 100644 +--- a/v/vm.c ++++ b/v/vm.c +@@ -17,8 +17,8 @@ + void trap_entry(); + void pop_tf(trapframe_t*); + +-volatile uint64_t tohost; +-volatile uint64_t fromhost; ++extern volatile uint64_t tohost; ++extern volatile uint64_t fromhost; + + static void do_tohost(uint64_t tohost_value) + { diff --git a/verif/regress/riscv-compliance.patch b/verif/regress/riscv-compliance.patch new file mode 100644 index 0000000000..eaffaf9164 --- /dev/null +++ b/verif/regress/riscv-compliance.patch @@ -0,0 +1,94 @@ +diff --git a/riscv-test-env/p/riscv_test.h b/riscv-test-env/p/riscv_test.h +index eaa6758..887408a 100644 +--- a/riscv-test-env/p/riscv_test.h ++++ b/riscv-test-env/p/riscv_test.h +@@ -162,7 +162,7 @@ handle_exception: \ + 1: ori TESTNUM, TESTNUM, 1337; \ + write_tohost: \ + sw TESTNUM, tohost, t5; \ +- j write_tohost; \ ++ 2: j 2b; \ + reset_vector: \ + RISCV_MULTICORE_DISABLE; \ + INIT_SPTBR; \ +@@ -215,7 +215,7 @@ end_testcode: \ + RVTEST_SYNC; \ + li TESTNUM, 1; \ + SWSIG (0, TESTNUM); \ +- ecall ++ j write_tohost; + + #define TESTNUM gp + #define RVTEST_FAIL \ +@@ -224,7 +224,7 @@ end_testcode: \ + sll TESTNUM, TESTNUM, 1; \ + or TESTNUM, TESTNUM, 1; \ + SWSIG (0, TESTNUM); \ +- ecall ++ j write_tohost; + + //----------------------------------------------------------------------- + // Data Section Macro +diff --git a/riscv-test-env/v/vm.c b/riscv-test-env/v/vm.c +index 6ab7fd1..fc01b94 100644 +--- a/riscv-test-env/v/vm.c ++++ b/riscv-test-env/v/vm.c +@@ -9,8 +9,8 @@ + void trap_entry(); + void pop_tf(trapframe_t*); + +-volatile uint64_t tohost; +-volatile uint64_t fromhost; ++extern volatile uint64_t tohost; ++extern volatile uint64_t fromhost; + + static void do_tohost(uint64_t tohost_value) + { +diff --git a/riscv-test-suite/rv32i/src/I-EBREAK-01.S b/riscv-test-suite/rv32i/src/I-EBREAK-01.S +index 958eebc..b84559f 100644 +--- a/riscv-test-suite/rv32i/src/I-EBREAK-01.S ++++ b/riscv-test-suite/rv32i/src/I-EBREAK-01.S +@@ -71,6 +71,7 @@ RV_COMPLIANCE_CODE_BEGIN + + # --------------------------------------------------------------------------------------------- + # Exception handler ++ .align 2 + _trap_handler: + # increment return address + csrr x30, mepc +diff --git a/riscv-test-suite/rv32i/src/I-ECALL-01.S b/riscv-test-suite/rv32i/src/I-ECALL-01.S +index 5278207..d181526 100644 +--- a/riscv-test-suite/rv32i/src/I-ECALL-01.S ++++ b/riscv-test-suite/rv32i/src/I-ECALL-01.S +@@ -73,6 +73,7 @@ RV_COMPLIANCE_CODE_BEGIN + + # --------------------------------------------------------------------------------------------- + # Exception handler ++ .align 2 + _trap_handler: + # increment return address + csrr x30, mepc +diff --git a/riscv-test-suite/rv32i/src/I-MISALIGN_JMP-01.S b/riscv-test-suite/rv32i/src/I-MISALIGN_JMP-01.S +index 8f54534..a09cf76 100644 +--- a/riscv-test-suite/rv32i/src/I-MISALIGN_JMP-01.S ++++ b/riscv-test-suite/rv32i/src/I-MISALIGN_JMP-01.S +@@ -277,6 +277,7 @@ RV_COMPLIANCE_CODE_BEGIN + + # --------------------------------------------------------------------------------------------- + # Exception handler ++ .align 2 + _trap_handler: + # increment return address + csrr x30, mbadaddr +diff --git a/riscv-test-suite/rv32i/src/I-MISALIGN_LDST-01.S b/riscv-test-suite/rv32i/src/I-MISALIGN_LDST-01.S +index 5a20187..0eeb9d1 100644 +--- a/riscv-test-suite/rv32i/src/I-MISALIGN_LDST-01.S ++++ b/riscv-test-suite/rv32i/src/I-MISALIGN_LDST-01.S +@@ -188,6 +188,7 @@ RV_COMPLIANCE_CODE_BEGIN + + # --------------------------------------------------------------------------------------------- + # Exception handler ++ .align 2 + _trap_handler: + # increment return address + csrr x30, mepc diff --git a/verif/regress/riscv-dv.patch b/verif/regress/riscv-dv.patch new file mode 100644 index 0000000000..5bb6e411cf --- /dev/null +++ b/verif/regress/riscv-dv.patch @@ -0,0 +1,395 @@ +diff --git a/run.py b/run.py +index bae34b7..76df3c7 100644 +--- a/run.py ++++ b/run.py +@@ -23,6 +23,7 @@ import sys + import logging + + from scripts.lib import * ++from scripts.verilator_log_to_trace_csv import * + from scripts.spike_log_to_trace_csv import * + from scripts.ovpsim_log_to_trace_csv import * + from scripts.whisper_log_trace_csv import * +@@ -414,7 +415,7 @@ def run_assembly(asm_test, iss_yaml, isa, mabi, gcc_opts, iss_opts, output_dir, + base_cmd = parse_iss_yaml(iss, iss_yaml, isa, setting_dir, debug_cmd) + logging.info("[%0s] Running ISS simulation: %s" % (iss, elf)) + cmd = get_iss_cmd(base_cmd, elf, log) +- run_cmd(cmd, 10, debug_cmd = debug_cmd) ++ run_cmd(cmd, 1500, debug_cmd = debug_cmd) + logging.info("[%0s] Running ISS simulation: %s ...done" % (iss, elf)) + if len(iss_list) == 2: + compare_iss_log(iss_list, log_list, report) +@@ -596,7 +597,6 @@ def iss_cmp(test_list, iss, output_dir, stop_on_first_error, exp, debug_cmd): + if len(iss_list) != 2: + return + report = ("%s/iss_regr.log" % output_dir).rstrip() +- run_cmd("rm -rf %s" % report) + for test in test_list: + for i in range(0, test['iterations']): + elf = ("%s/asm_tests/%s_%d.o" % (output_dir, test['test'], i)) +@@ -622,6 +622,8 @@ def compare_iss_log(iss_list, log_list, report, stop_on_first_error=0, exp=False + csv_list.append(csv) + if iss == "spike": + process_spike_sim_log(log, csv) ++ elif "verilator" in iss or "vsim" in iss: ++ process_verilator_sim_log(log, csv) + elif iss == "ovpsim": + process_ovpsim_sim_log(log, csv, stop_on_first_error) + elif iss == "sail": +@@ -654,7 +656,7 @@ def setup_parser(): + + parser.add_argument("--target", type=str, default="rv32imc", + help="Run the generator with pre-defined targets: \ +- rv32imc, rv32i, rv64imc, rv64gc") ++ rv32imc, rv32i, rv32ima, rv64imc, rv64gc, rv64imac") + parser.add_argument("-o", "--output", type=str, + help="Output directory name", dest="o") + parser.add_argument("-tl", "--testlist", type=str, default="", +@@ -772,6 +774,15 @@ def load_config(args, cwd): + if args.target == "rv32imc": + args.mabi = "ilp32" + args.isa = "rv32imc" ++ elif args.target == "rv32imac": ++ args.mabi = "ilp32" ++ args.isa = "rv32imac" ++ elif args.target == "rv32ima": ++ args.mabi = "ilp32" ++ args.isa = "rv32ima" ++ elif args.target == "rv32gc": ++ args.mabi = "ilp32" ++ args.isa = "rv32gc" + elif args.target == "multi_harts": + args.mabi = "ilp32" + args.isa = "rv32gc" +@@ -787,6 +798,9 @@ def load_config(args, cwd): + elif args.target == "rv64gc": + args.mabi = "lp64" + args.isa = "rv64gc" ++ elif args.target == "rv64imac": ++ args.mabi = "lp64" ++ args.isa = "rv64imac" + elif args.target == "rv64gcv": + args.mabi = "lp64" + args.isa = "rv64gcv" +@@ -817,7 +831,7 @@ def main(): + # Load configuration from the command line and the configuration file. + cfg = load_config(args, cwd) + # Create output directory +- output_dir = create_output(args.o, args.noclean) ++ output_dir = create_output(args.o, args.noclean, cwd+"/out_") + + if args.verilog_style_check: + logging.debug("Run style check") +diff --git a/scripts/lib.py b/scripts/lib.py +index b974637..90aef00 100644 +--- a/scripts/lib.py ++++ b/scripts/lib.py +@@ -230,6 +230,8 @@ def process_regression_list(testlist, test, iterations, matched_list, riscv_dv_r + if (iterations > 0 and entry['iterations'] > 0): + entry['iterations'] = iterations + if entry['iterations'] > 0: ++ entry['asm_tests'] = re.sub("\<path_var\>", get_env_var(entry['path_var']), entry['asm_tests']) ++ entry['gcc_opts'] = re.sub("\<path_var\>", get_env_var(entry['path_var']), entry['gcc_opts']) + logging.info("Found matched tests: %s, iterations:%0d" % + (entry['test'], entry['iterations'])) + matched_list.append(entry) +diff --git a/scripts/link.ld b/scripts/link.ld +index df08889..ad50f56 100644 +--- a/scripts/link.ld ++++ b/scripts/link.ld +@@ -19,15 +19,17 @@ ENTRY(_start) + SECTIONS + { + . = 0x80000000; +- .text : { *(.text) } ++ .text.init : { *(.text.init) } + . = ALIGN(0x1000); + .tohost : { *(.tohost) } + . = ALIGN(0x1000); ++ .text : { *(.text) } ++ . = ALIGN(0x1000); + .page_table : { *(.page_table) } +- .data : { *(.data) } + .user_stack : { *(.user_stack) } + .kernel_data : { *(.kernel_data) } + .kernel_stack : { *(.kernel_stack) } ++ .data : { *(.data) } + .bss : { *(.bss) } + _end = .; + } +diff --git a/scripts/verilator_log_to_trace_csv.py b/scripts/verilator_log_to_trace_csv.py +new file mode 100644 +index 0000000..2be83ae +--- /dev/null ++++ b/scripts/verilator_log_to_trace_csv.py +@@ -0,0 +1,249 @@ ++""" ++Copyright 2019 Google LLC ++ ++Licensed under the Apache License, Version 2.0 (the "License"); ++you may not use this file except in compliance with the License. ++You may obtain a copy of the License at ++ ++ http://www.apache.org/licenses/LICENSE-2.0 ++ ++Unless required by applicable law or agreed to in writing, software ++distributed under the License is distributed on an "AS IS" BASIS, ++WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ++See the License for the specific language governing permissions and ++limitations under the License. ++ ++Convert verilator sim log to standard riscv instruction trace format ++""" ++ ++import argparse ++import os ++import re ++import sys ++import logging ++ ++sys.path.insert(0, os.path.dirname(os.path.realpath(__file__))) ++ ++from riscv_trace_csv import * ++from lib import * ++ ++RD_RE = re.compile(r"(?P<pri>\d) 0x(?P<addr>[a-f0-9]+?) " \ ++ "\((?P<bin>.*?)\) (?P<reg>[xf]\s*\d*?) 0x(?P<val>[a-f0-9]+)") ++CORE_RE = re.compile(r"core.*0x(?P<addr>[a-f0-9]+?) \(0x(?P<bin>.*?)\) (?P<instr>.*?)$") ++ILLE_RE = re.compile(r"trap_illegal_instruction") ++ ++LOGGER = logging.getLogger() ++ ++ ++def process_instr(trace): ++ if trace.instr == "jal": ++ # Spike jal format jal rd, -0xf -> jal rd, -15 ++ idx = trace.operand.rfind(",") ++ imm = trace.operand[idx+1:] ++ if imm[0] == "-": ++ imm = "-" + str(int(imm[1:], 16)) ++ else: ++ imm = str(int(imm, 16)) ++ trace.operand = trace.operand[0:idx+1] + imm ++ trace.operand = trace.operand.replace("(", ",") ++ trace.operand = trace.operand.replace(")", "") ++ ++ ++def read_verilator_instr(match, full_trace): ++ '''Unpack a regex match for CORE_RE to a RiscvInstructionTraceEntry ++ ++ If full_trace is true, extract operand data from the disassembled ++ instruction. ++ ++ ''' ++ ++ # Extract the disassembled instruction. ++ disasm = match.group('instr') ++ ++ # Spike's disassembler shows a relative jump as something like "j pc + ++ # 0x123" or "j pc - 0x123". We just want the relative offset. ++ disasm = disasm.replace('pc + ', '').replace('pc - ', '-') ++ ++ instr = RiscvInstructionTraceEntry() ++ instr.pc = match.group('addr') ++ instr.instr_str = disasm ++ instr.binary = match.group('bin') ++ ++ if full_trace: ++ opcode = disasm.split(' ')[0] ++ operand = disasm[len(opcode):].replace(' ', '') ++ instr.instr, instr.operand = \ ++ convert_pseudo_instr(opcode, operand, instr.binary) ++ ++ process_instr(instr) ++ ++ return instr ++ ++ ++def read_verilator_trace(path, full_trace): ++ '''Read a Spike simulation log at <path>, yielding executed instructions. ++ ++ This assumes that the log was generated with the -l and --log-commits options ++ to Spike. ++ ++ If full_trace is true, extract operands from the disassembled instructions. ++ ++ Since Spike has a strange trampoline that always runs at the start, we skip ++ instructions up to and including the one at PC 0x1010 (the end of the ++ trampoline). At the end of a DV program, there's an ECALL instruction, which ++ we take as a signal to stop checking, so we ditch everything that follows ++ that instruction. ++ ++ This function yields instructions as it parses them as tuples of the form ++ (entry, illegal). entry is a RiscvInstructionTraceEntry. illegal is a ++ boolean, which is true if the instruction caused an illegal instruction trap. ++ ++ ''' ++ ++ # This loop is a simple FSM with states TRAMPOLINE, INSTR, EFFECT. The idea ++ # is that we're in state TRAMPOLINE until we get to the end of Spike's ++ # trampoline, then we switch between INSTR (where we expect to read an ++ # instruction) and EFFECT (where we expect to read commit information). ++ # ++ # We yield a RiscvInstructionTraceEntry object each time we leave EFFECT ++ # (going back to INSTR), we loop back from INSTR to itself, or we get to the ++ # end of the file and have an instruction in hand. ++ # ++ # On entry to the loop body, we are in state TRAMPOLINE if in_trampoline is ++ # true. Otherwise, we are in state EFFECT if instr is not None, otherwise we ++ # are in state INSTR. ++ ++ end_trampoline_re = re.compile(r'core.*: 0x0000000080000000 ') ++ start_debug_it_re = re.compile(r'core.*: 0x0000000000000800 ') ++ stop_debug_it_re = re.compile(r'core.*: 0x0000000000000890 ') ++ ++ in_trampoline = True ++ in_debug = False ++ instr = None ++ ++ with open(path, 'r') as handle: ++ for line in handle: ++ if in_trampoline: ++ # The TRAMPOLINE state ++ if end_trampoline_re.match(line): ++ in_trampoline = False ++ continue ++ ++ if not in_trampoline: ++ if in_debug: ++ if stop_debug_it_re.match(line): ++ in_debug = False ++ continue ++ else: ++ if start_debug_it_re.match(line): ++ in_debug = True ++ continue ++ ++ if instr is None: ++ # The INSTR state. We expect to see a line matching CORE_RE. We'll ++ # discard any other lines. ++ instr_match = CORE_RE.match(line) ++ if not instr_match: ++ continue ++ ++ instr = read_verilator_instr(instr_match, full_trace) ++ ++ # If instr.instr_str is 'ecall', we should stop. ++ if instr.instr_str == 'ecall': ++ break ++ ++ continue ++ ++ # The EFFECT state. If the line matches CORE_RE, we should have been in ++ # state INSTR, so we yield the instruction we had, read the new ++ # instruction and continue. As above, if the new instruction is 'ecall', ++ # we need to stop immediately. ++ instr_match = CORE_RE.match(line) ++ if instr_match: ++ yield (instr, False) ++ instr = read_verilator_instr(instr_match, full_trace) ++ if instr.instr_str == 'ecall': ++ break ++ continue ++ ++ # The line doesn't match CORE_RE, so we are definitely on a follow-on ++ # line in the log. First, check for illegal instructions ++ if 'trap_illegal_instruction' in line: ++ yield (instr, True) ++ instr = None ++ continue ++ ++ # The instruction seems to have been fine. Do we have commit data (from ++ # the --log-commits Spike option)? ++ commit_match = RD_RE.match(line) ++ if commit_match: ++ instr.gpr.append(gpr_to_abi(commit_match.group('reg') ++ .replace(' ', '')) + ++ ':' + commit_match.group('val')) ++ instr.mode = commit_match.group('pri') ++ ++ # At EOF, we might have an instruction in hand. Yield it if so. ++ if instr is not None: ++ yield (instr, False) ++ ++ ++def process_verilator_sim_log(verilator_log, csv, full_trace = 0): ++ """Process VERILATOR simulation log. ++ ++ Extract instruction and affected register information from verilator simulation ++ log and write the results to a CSV file at csv. Returns the number of ++ instructions written. ++ ++ """ ++ logging.info("Processing verilator log : %s" % verilator_log) ++ ++ instrs_in = 0 ++ instrs_out = 0 ++ ++ with open(csv, "w") as csv_fd: ++ trace_csv = RiscvInstructionTraceCsv(csv_fd) ++ trace_csv.start_new_trace() ++ ++ for (entry, illegal) in read_verilator_trace(verilator_log, full_trace): ++ instrs_in += 1 ++ ++ if illegal and full_trace: ++ logging.debug("Illegal instruction: {}, opcode:{}" ++ .format(entry.instr_str, entry.binary)) ++ ++ # Instructions that cause no architectural update (which includes illegal ++ # instructions) are ignored if full_trace is false. ++ # ++ # We say that an instruction caused an architectural update if either we ++ # saw a commit line (in which case, entry.gpr will contain a single ++ # entry) or the instruction was 'wfi' or 'ecall'. ++ if not (full_trace or entry.gpr or entry.instr_str in ['wfi', 'ecall']): ++ continue ++ ++ trace_csv.write_trace_entry(entry) ++ instrs_out += 1 ++ ++ logging.info("Processed instruction count : %d" % instrs_in) ++ logging.info("CSV saved to : %s" % csv) ++ return instrs_out ++ ++ ++def main(): ++ # Parse input arguments ++ parser = argparse.ArgumentParser() ++ parser.add_argument("--log", type=str, help="Input verilator simulation log") ++ parser.add_argument("--csv", type=str, help="Output trace csv_buf file") ++ parser.add_argument("-f", "--full_trace", dest="full_trace", action="store_true", ++ help="Generate the full trace") ++ parser.add_argument("-v", "--verbose", dest="verbose", action="store_true", ++ help="Verbose logging") ++ parser.set_defaults(full_trace=False) ++ parser.set_defaults(verbose=False) ++ args = parser.parse_args() ++ setup_logging(args.verbose) ++ # Process verilator log ++ process_verilator_sim_log(args.log, args.csv, args.full_trace) ++ ++ ++if __name__ == "__main__": ++ main() +diff --git a/yaml/iss.yaml b/yaml/iss.yaml +index 344ef79..381cda6 100644 +--- a/yaml/iss.yaml ++++ b/yaml/iss.yaml +@@ -17,6 +17,16 @@ + cmd: > + <path_var>/spike --log-commits --isa=<variant> -l <elf> + ++- iss: verilator ++ path_var: RTL_PATH ++ cmd: > ++ make -C <path_var> generate-trace-verilator elf-bin=<elf> ++ ++- iss: vsim ++ path_var: RTL_PATH ++ cmd: > ++ make -C <path_var> generate-trace-vsim preload=<elf> elf-bin=none ++ + - iss: ovpsim + path_var: OVPSIM_PATH + cmd: > diff --git a/verif/regress/riscv-isa-sim.patch b/verif/regress/riscv-isa-sim.patch new file mode 100644 index 0000000000..26cc20c6be --- /dev/null +++ b/verif/regress/riscv-isa-sim.patch @@ -0,0 +1,15 @@ +diff --git a/arch_test_target/spike/model_test.h b/arch_test_target/spike/model_test.h +index e968e43a..7628af51 100644 +--- a/arch_test_target/spike/model_test.h ++++ b/arch_test_target/spike/model_test.h +@@ -23,6 +23,7 @@ + li x1, 1; \ + write_tohost: \ + sw x1, tohost, t1; \ ++ ecall + self_loop: j self_loop; + + #define RVMODEL_BOOT +-- +2.39.0 + diff --git a/verif/regress/riscv-tests-env.patch b/verif/regress/riscv-tests-env.patch new file mode 100644 index 0000000000..725a3da235 --- /dev/null +++ b/verif/regress/riscv-tests-env.patch @@ -0,0 +1,43 @@ +diff --git a/p/riscv_test.h b/p/riscv_test.h +index 88ca6c1..61c53ca 100644 +--- a/p/riscv_test.h ++++ b/p/riscv_test.h +@@ -236,9 +236,8 @@ reset_vector: \ + #define RVTEST_PASS \ + fence; \ + li TESTNUM, 1; \ +- li a7, 93; \ +- li a0, 0; \ +- ecall ++ sw TESTNUM, tohost, t5; \ ++42: j 42b + + #define TESTNUM gp + #define RVTEST_FAIL \ +@@ -246,9 +245,8 @@ reset_vector: \ + 1: beqz TESTNUM, 1b; \ + sll TESTNUM, TESTNUM, 1; \ + or TESTNUM, TESTNUM, 1; \ +- li a7, 93; \ +- addi a0, TESTNUM, 0; \ +- ecall ++ sw TESTNUM, tohost, t5; \ ++42: j 42b + + //----------------------------------------------------------------------- + // Data Section Macro +diff --git a/v/vm.c b/v/vm.c +index 6bf05f7..71700f5 100644 +--- a/v/vm.c ++++ b/v/vm.c +@@ -17,8 +17,8 @@ + void trap_entry(); + void pop_tf(trapframe_t*); + +-volatile uint64_t tohost; +-volatile uint64_t fromhost; ++extern volatile uint64_t tohost; ++extern volatile uint64_t fromhost; + + static void do_tohost(uint64_t tohost_value) + { diff --git a/verif/regress/smoke-gen_tests.sh b/verif/regress/smoke-gen_tests.sh new file mode 100644 index 0000000000..d6d5ba94b5 --- /dev/null +++ b/verif/regress/smoke-gen_tests.sh @@ -0,0 +1,36 @@ +# Copyright 2023 Thales DIS +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Original Author: Ayoub JALALI - Thales + +# where are the tools +if ! [ -n "$RISCV" ]; then + echo "Error: RISCV variable undefined" + return +fi + +# install the required tools +source verif/regress/install-cva6.sh +source verif/regress/install-riscv-dv.sh +source verif/regress/install-riscv-isa-sim.sh + +if ! [ -n "$DV_TARGET" ]; then + DV_TARGET=cv32a60x +fi + +if ! [ -n "$DV_SIMULATORS" ]; then + DV_SIMULATORS=vcs-uvm,spike +fi + +cd verif/sim/ +cp ../env/corev-dv/custom/riscv_custom_instr_enum.sv ./dv/src/isa/custom/ +python3 cva6.py --testlist=cva6_base_testlist.yaml --test riscv_arithmetic_basic_test_comp --iss_yaml cva6.yaml --target $DV_TARGET -cs ../env/corev-dv/target/rv32imac/ --mabi ilp32 --isa rv32imac --simulator_yaml ../env/corev-dv/simulator.yaml --iss=$DV_SIMULATORS $DV_OPTS -i 1 --iss_timeout 300 +python3 cva6.py --testlist=cva6_base_testlist.yaml --test riscv_load_store_test --iss_yaml cva6.yaml --target $DV_TARGET -cs ../env/corev-dv/target/rv32imac/ --mabi ilp32 --isa rv32imac --simulator_yaml ../env/corev-dv/simulator.yaml --iss=$DV_SIMULATORS $DV_OPTS -i 1 --iss_timeout 300 +python3 cva6.py --testlist=cva6_base_testlist.yaml --test riscv_unaligned_load_store_test --iss_yaml cva6.yaml --target $DV_TARGET -cs ../env/corev-dv/target/rv32imac/ --mabi ilp32 --isa rv32imac --simulator_yaml ../env/corev-dv/simulator.yaml --iss=$DV_SIMULATORS $DV_OPTS -i 1 --iss_timeout 300 +make clean_all + +cd - diff --git a/verif/regress/smoke-tests.sh b/verif/regress/smoke-tests.sh new file mode 100644 index 0000000000..b967c16622 --- /dev/null +++ b/verif/regress/smoke-tests.sh @@ -0,0 +1,46 @@ +# Copyright 2021 Thales DIS design services SAS +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Original Author: Jean-Roch COULON - Thales + +# where are the tools +if ! [ -n "$RISCV" ]; then + echo "Error: RISCV variable undefined" + return +fi + +# install the required tools +source ./verif/regress/install-cva6.sh +source ./verif/regress/install-riscv-dv.sh +source ./verif/regress/install-riscv-compliance.sh +source ./verif/regress/install-riscv-tests.sh +source ./verif/regress/install-riscv-arch-test.sh + + +if ! [ -n "$DV_SIMULATORS" ]; then + DV_SIMULATORS=vcs-testharness,spike +fi + +cd verif/sim/ +python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv64a6_imafdc_sv39-v.yaml --test rv64ui-v-add --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS +python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv64a6_imafdc_sv39-p.yaml --test rv64ui-p-add --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS +python3 cva6.py --testlist=../tests/testlist_riscv-compliance-cv64a6_imafdc_sv39.yaml --test rv32i-I-ADD-01 --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS +python3 cva6.py --testlist=../tests/testlist_riscv-arch-test-cv64a6_imafdc_sv39.yaml --test rv64i_m-add-01 --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS --linker=../tests/riscv-arch-test/riscv-target/spike/link.ld +python3 cva6.py --testlist=../tests/testlist_custom.yaml --test custom_test_template --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS +python3 cva6.py --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml --c_tests ../tests/custom/hello_world/hello_world.c\ + --gcc_opts "-g ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -T ../tests/custom/common/test.ld" +make -C ../.. clean +make clean_all +python3 cva6.py --testlist=../tests/testlist_riscv-compliance-cv32a60x.yaml --test rv32i-I-ADD-01 --iss_yaml cva6.yaml --target cv32a60x --iss=$DV_SIMULATORS $DV_OPTS +python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv32a60x-p.yaml --test rv32ui-p-add --iss_yaml cva6.yaml --target cv32a60x --iss=$DV_SIMULATORS $DV_OPTS +python3 cva6.py --testlist=../tests/testlist_riscv-arch-test-cv32a60x.yaml --test rv32im-cadd-01 --iss_yaml cva6.yaml --target cv32a60x --iss=$DV_SIMULATORS $DV_OPTS --linker=../tests/riscv-arch-test/riscv-target/spike/link.ld +python3 cva6.py --target cv32a60x --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml --c_tests ../tests/custom/hello_world/hello_world.c --linker=../tests/custom/common/test.ld\ + --gcc_opts "-g ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -lgcc -I../tests/custom/env -I../tests/custom/common" +make -C ../.. clean +make clean_all + +cd - diff --git a/verif/regress/verilator-v5.patch b/verif/regress/verilator-v5.patch new file mode 100644 index 0000000000..ed8df2b9f8 --- /dev/null +++ b/verif/regress/verilator-v5.patch @@ -0,0 +1,26 @@ +diff --git a/docs/CONTRIBUTORS b/docs/CONTRIBUTORS +index 215fb6bd8..829752e6b 100644 +--- a/docs/CONTRIBUTORS ++++ b/docs/CONTRIBUTORS +@@ -154,5 +154,6 @@ Yuri Victorovich + Yutetsu TAKATSUKASA + Yu-Sheng Lin + Yves Mathieu ++Zbigniew Chamski + Zhanglei Wang + Zixi Li +diff --git a/include/verilated_types.h b/include/verilated_types.h +index cb7265e32..f1d482d8e 100644 +--- a/include/verilated_types.h ++++ b/include/verilated_types.h +@@ -1012,8 +1012,8 @@ struct VlUnpacked final { + + // METHODS + // Raw access +- WData* data() { return &m_storage[0]; } +- const WData* data() const { return &m_storage[0]; } ++ WData* data() { return (WData*)&m_storage[0]; } ++ const WData* data() const { return (const WData*)&m_storage[0]; } + + T_Value& operator[](size_t index) { return m_storage[index]; } + const T_Value& operator[](size_t index) const { return m_storage[index]; } diff --git a/verif/sim/Makefile b/verif/sim/Makefile new file mode 100644 index 0000000000..88cda74931 --- /dev/null +++ b/verif/sim/Makefile @@ -0,0 +1,275 @@ +# Copyright 2021 Thales DIS design services SAS +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Original Author: Jean-Roch COULON - Thales + +mkfile_path := $(abspath $(lastword $(MAKEFILE_LIST))) +root-dir := $(dir $(mkfile_path)) + +ifndef CVA6_REPO_DIR +$(warning must set CVA6_REPO_DIR to point at the root of CVA6 sources and CVA6_TB_DIR to point here -- doing it for you...) +export CVA6_REPO_DIR = $(abspath $(root-dir)../..) +export CVA6_TB_DIR = $(root-dir)/../tb/core +endif +ifndef TARGET_CFG +export TARGET_CFG = $(target) +endif + +.DEFAULT_GOAL := help + +FLIST_TB := $(CVA6_TB_DIR)/Flist.cva6_tb +# target takes one of the following cva6 hardware configuration: +# cv64a6_imafdc_sv39, cv32a6_imac_sv0, cv32a6_imac_sv32, cv32a6_imafc_sv32 +target ?= cv64a6_imafdc_sv39 +FLIST_CORE := $(if $(gate), $(CVA6_REPO_DIR)/core/Flist.cva6_gate,$(CVA6_REPO_DIR)/core/Flist.cva6) + +TRACE_FAST ?= +TRACE_COMPACT ?= +VERDI ?= +path-var ?= +tool_path ?= +isscomp_opts ?= +issrun_opts ?= +isspostrun_opts ?= +log ?= +variant ?= +# Set Spike step count limit if the caller provided a step count value in variable 'steps'. +ifneq ($(steps),) + spike_stepout = --steps=$(steps) +endif + +# TRACE_FAST, TRACE_COMPACT and VERDI are mutually exclusive and imply non-empty DEBUG. +ifneq ($(TRACE_FAST),) +ifneq ($(TRACE_COMPACT),) +$(error Variables TRACE_FAST and TRACE_COMPACT are mutually exclusive, please unset one of them) +endif +ifneq ($(VERDI),) +$(error Variables TRACE_FAST and VERDI are mutually exclusive, please unset one of them) +endif +DEBUG=1 +endif + +ifneq ($(TRACE_COMPACT),) +ifneq ($(TRACE_FAST),) +$(error Variables TRACE_COMPACT and TRACE_FAST are mutually exclusive, please unset one of them) +endif +ifneq ($(VERDI),) +$(error Variables TRACE_COMPACT and VERDI are mutually exclusive, please unset one of them) +endif +DEBUG=1 +endif + +ifneq ($(VERDI),) +ifneq ($(TRACE_COMPACT),) +$(error Variables VERDI and TRACE_COMPACT are mutually exclusive, please unset one of them) +endif +ifneq ($(TRACE_FAST),) +$(error Variables VERDI and TRACE_FAST are mutually exclusive, please unset one of them) +endif +DEBUG=1 +endif + +# Make these variables available to sub-Makefiles. +export DEBUG TRACE_FAST TRACE_COMPACT + +TESTNAME := $(shell basename -s .o $(elf)) + +ifeq ($(isspostrun_opts), "") +grep_address: + grep $(isspostrun_opts) ./trace_rvfi_hart_00.dasm +else +grep_address: +endif + +####################################################################################### +# Code Coverage +####################################################################################### +#code coverage is deactivated by default +#To activate the code coverage: define the env variable cov with: (export cov=value) , to deactivate it: (unset cov) OR (export cov= ) +cov-exclude-list ?= $(root-dir)/cov-exclude-mod.lst + +ifdef cov + cov-comp-opt = -cm line+cond+fsm+tgl+assert -cm_hier $(cov-exclude-list) + cov-run-opt = -cm line+cond+fsm+tgl+assert -cm_name $(TESTNAME) +else + cov-comp-opt = + cov-run-opt = +endif + +ifdef cvxif + spike_extension = --extension=cvxif +endif + +############################################################################### +# Spike specific commands, variables +############################################################################### +spike: + LD_LIBRARY_PATH="$$(realpath ../../tools/spike/lib):$$LD_LIBRARY_PATH" \ + $(tool_path)/spike $(spike_stepout) $(spike_extension) --log-commits --isa=$(variant) -l $(elf) + cp $(log).iss $(log) + +############################################################################### +# testharness specific commands, variables +############################################################################### +vcs-testharness: + make -C $(path_var) vcs_build target=$(target) defines=$(subst +define+,,$(isscomp_opts)) + $(path_var)/work-vcs/simv $(if $(VERDI), -verdi -do $(path_var)/init_testharness.do,) +permissive -sv_lib $(path_var)/work-dpi/ariane_dpi \ + +tohost_addr=$(shell $$RISCV/bin/${CV_SW_PREFIX}nm -B $(elf) | grep -w tohost | cut -d' ' -f1) \ + +PRELOAD=$(elf) +permissive-off ++$(elf) $(issrun_opts) + $(tool_path)/spike-dasm --isa=$(variant) < ./trace_rvfi_hart_00.dasm > $(log) + grep $(isspostrun_opts) ./trace_rvfi_hart_00.dasm + +veri-testharness: + make -C $(path_var) verilate verilator="verilator --no-timing" target=$(target) defines=$(subst +define+,,$(isscomp_opts)) + $(path_var)/work-ver/Variane_testharness $(if $(TRACE_COMPACT), -f verilator.fst) $(if $(TRACE_FAST), -v verilator.vcd) $(elf) $(issrun_opts) +PRELOAD=$(elf) \ + +tohost_addr=$(shell $$RISCV/bin/${CV_SW_PREFIX}nm -B $(elf) | grep -w tohost | cut -d' ' -f1) + $(tool_path)/spike-dasm --isa=$(variant) < ./trace_rvfi_hart_00.dasm > $(log) + # If present, move default trace files to per-test directory. + [ ! -f verilator.fst ] || mv verilator.fst `dirname $(log)`/`basename $(log) .log`.$(target).fst + [ ! -f verilator.vcd ] || mv verilator.vcd `dirname $(log)`/`basename $(log) .log`.$(target).vcd + grep $(isspostrun_opts) ./trace_rvfi_hart_00.dasm + +questa-testharness: + mkdir -p $(path_var)/tmp + make -C $(path_var) sim target=$(target) defines=$(subst +define+,,$(isscomp_opts)) batch-mode=1 elf-bin=$(elf) $(issrun_opts) + $(tool_path)/spike-dasm --isa=$(variant) < $(path_var)/trace_rvfi_hart_00.dasm > $(log) + grep $(isspostrun_opts) $(path_var)/trace_rvfi_hart_00.dasm + +############################################################################### +# UVM specific commands, variables +############################################################################### +ALL_VCS_FLAGS = $(if $(VERDI), -kdb -debug_access+all -lca,) -sverilog -full64 -timescale=1ns/1ns +VCS_WORK_DIR = $(CVA6_REPO_DIR)/verif/sim/vcs_results/default/vcs.d +SIMV = $(VCS_WORK_DIR)/simv + +export CVA6_UVMT_DIR = $(CVA6_REPO_DIR)/verif/tb/uvmt +export CVA6_UVMT_PATH = $(CVA6_REPO_DIR)/verif/tb/uvmt +export CVA6_UVME_PATH = $(CVA6_REPO_DIR)/verif/env/uvme +export CV_CORE_LC = cva6 +export CV_CORE_UC = CVA6 +export DV_UVMT_PATH = $(CVA6_REPO_DIR)/verif/core-v-verif/$(CV_CORE_LC)/tb/uvmt +export DV_UVME_PATH = $(CVA6_REPO_DIR)/verif/core-v-verif/$(CV_CORE_LC)/env/uvme +export DV_UVML_HRTBT_PATH = $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_libs/uvml_hrtbt +export DV_UVMA_CORE_CNTRL_PATH = $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_agents/uvma_core_cntrl +export DV_UVMA_RVFI_PATH = $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_agents/uvma_rvfi +export DV_UVMA_ISACOV_PATH = $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_agents/uvma_isacov +export DV_UVMA_CLKNRST_PATH = $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_agents/uvma_clknrst +export DV_UVMA_CVXIF_PATH = $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_agents/uvma_cvxif +export DV_UVMA_AXI_PATH = $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_agents/uvma_axi +export DV_UVMA_INTERRUPT_PATH = $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_agents/uvma_interrupt +export DV_UVMA_DEBUG_PATH = $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_agents/uvma_debug +export DV_UVMA_OBI_PATH = $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_agents/uvma_obi +export DV_UVML_TRN_PATH = $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_libs/uvml_trn +export DV_UVML_MEM_PATH = $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_libs/uvml_mem +export DV_UVML_LOGS_PATH = $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_libs/uvml_logs +export DV_UVML_SB_PATH = $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_libs/uvml_sb +export CV_CORE_PKG = $(CVA6_REPO_DIR)/verif/core-v-verif/core-v-cores/$(CV_CORE_LC) +export DESIGN_RTL_DIR = $(CV_CORE_PKG)/rtl + +DPI_DASM_PKG = $(CVA6_REPO_DIR)/verif/core-v-verif/lib/dpi_dasm +DPI_DASM_SPIKE_PKG = $(CVA6_REPO_DIR)/verif/core-v-verif/$(CV_CORE_LC)/vendor_lib/dpi_dasm_spike +export DPI_DASM_ROOT = $(DPI_DASM_PKG) +export DPI_DASM_SPIKE_ROOT = $(DPI_DASM_SPIKE_PKG) +export TBSRC_HOME = $(CVA6_REPO_DIR)/verif/tb +export DV_OVPM_HOME = $(CVA6_REPO_DIR)/verif/core-v-verif/$(CV_CORE_LC)/vendor_lib/imperas +export DV_OVPM_MODEL = $(DV_OVPM_HOME)/riscv_$(CV_CORE_UC)_OVPsim +export DV_OVPM_DESIGN = $(DV_OVPM_HOME)/design + +ALL_UVM_FLAGS = -lca -sverilog +incdir+$(VCS_HOME)/etc/uvm/src \ + $(VCS_HOME)/etc/uvm/src/uvm_pkg.sv +UVM_VERBOSITY=UVM_MEDIUM -ntb_opts uvm-1.2 -timescale=1ns/1ps \ + -assert svaext -race=all -ignore unique_checks -full64 -q +incdir+$(VCS_HOME)/etc/uvm/src \ + +incdir+$(CVA6_REPO_DIR)/verif/core-v-verif/$(CV_CORE_LC)/env/uvme +incdir+$(CVA6_REPO_DIR)/verif/core-v-verif/$(CV_CORE_LC)/tb/uvmt \ + $(if $(DEBUG), -debug_access+all $(if $(VERDI), -kdb) $(if $(TRACE_COMPACT),+vcs+fsdbon)) + +ALL_SIMV_UVM_FLAGS = -licwait 20 $(issrun_opts) \ + -sv_lib $(CVA6_REPO_DIR)/verif/core-v-verif/lib/dpi_dasm/lib/Linux64/libdpi_dasm +signature=I-ADD-01.signature_output \ + +UVM_TESTNAME=uvmt_cva6_firmware_test_c + +ifneq ($(DEBUG),) # If RTL DEBUG support requested + ifneq ($(VERDI),) # If VERDI interactive mode requested, use GUI and do not run simulation + ALL_SIMV_UVM_FLAGS += \ + -gui -do $(CVA6_REPO_DIR)/verif/sim/init_uvm.do + else # else: *not* VERDI, use CLI mode and appropriate batch dump controls + ifneq ($(TRACE_FAST),) # TRACE_FAST: Generate waveform trace in VPD format + ALL_SIMV_UVM_FLAGS += \ + -ucli -do $(CVA6_REPO_DIR)/verif/sim/init_run_uvm_vpd.do + SIMV_TRACE_EXTN = vpd + endif + ifneq ($(TRACE_COMPACT),) # TRACE_COMPACT: Generate waveform trace in FSDB format + ALL_SIMV_UVM_FLAGS += \ + -ucli -do $(CVA6_REPO_DIR)/verif/sim/init_run_uvm_fsdb.do + SIMV_TRACE_EXTN = fsdb + endif + endif +endif + +dpi-library = $(VCS_WORK_DIR)/work-dpi +dpi_build: + mkdir -p $(dpi-library) + g++ -shared -fPIC -std=c++17 -Bsymbolic -I../corev_apu/tb/dpi -O3 -I$(SPIKE_ROOT)/include \ + -I$(VCS_HOME)/include -I$(RISCV)/include -c $(CVA6_REPO_DIR)/corev_apu/tb/dpi/elfloader.cc \ + -o $(dpi-library)/elfloader.o + g++ -shared -m64 -o $(dpi-library)/ariane_dpi.so $(dpi-library)/elfloader.o -L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib + +vcs_uvm_comp: dpi_build + @echo "[VCS] Building Model" + mkdir -p $(VCS_WORK_DIR) + cd $(VCS_WORK_DIR) && vcs $(ALL_UVM_FLAGS) \ + -f $(FLIST_CORE) -f $(FLIST_TB) \ + -f $(CVA6_UVMT_DIR)/uvmt_cva6.flist \ + $(cov-comp-opt) +define+UNSUPPORTED_WITH+ $(isscomp_opts)\ + -top uvmt_cva6_tb + +vcs_uvm_run: + $(if $(TRACE_FAST), unset VERDI_HOME ;) \ + cd $(VCS_WORK_DIR)/ && \ + $(VCS_WORK_DIR)/simv ${ALL_SIMV_UVM_FLAGS} \ + ++$(elf) \ + +PRELOAD=$(elf) \ + +tohost_addr=$(shell $$RISCV/bin/riscv-none-elf-nm -B $(elf) | grep -w tohost | cut -d' ' -f1) \ + -sv_lib $(dpi-library)/ariane_dpi \ + $(cov-run-opt) $(issrun_opts) && \ + mv $(VCS_WORK_DIR)/trace_rvfi_hart_00.dasm $(CVA6_REPO_DIR)/verif/sim/ && \ + { [ -z "`ls $(VCS_WORK_DIR)/*.$(SIMV_TRACE_EXTN)`" ] || \ + for i in `ls $(VCS_WORK_DIR)/*.$(SIMV_TRACE_EXTN)` ; do mv $$i $(CVA6_REPO_DIR)/verif/sim/`basename $$i` ; done || \ + true ; } + +vcs-uvm: + make vcs_uvm_comp + make vcs_uvm_run + $(tool_path)/spike-dasm --isa=$(variant) < ./trace_rvfi_hart_00.dasm > $(log) + grep $(isspostrun_opts) ./trace_rvfi_hart_00.dasm + [ -z "`ls *.$(SIMV_TRACE_EXTN)`" ] || \ + for i in `ls *.$(SIMV_TRACE_EXTN)` ; do mv $$i `dirname $(log)`/`basename $(log) .log`.$(target).$$i ; done || true + +generate_cov_dash: + urg -dir $(VCS_WORK_DIR)/simv.vdb -group instcov_for_score + +vcs_clean_all: + @echo "[VCS] Cleanup (entire vcs_work dir)" + rm -rf $(CVA6_REPO_DIR)/verif/sim/vcs_results/ verdiLog/ simv* *.daidir *.vpd *.fsdb *.db csrc ucli.key vc_hdrs.h novas* inter.fsdb uart + +############################################################################### +# Common targets and rules +############################################################################### + +clean_all: vcs_clean_all + rm -f *.txt + rm -f trace*.log + rm -f trace*.dasm + rm -f *.vpd *.fsdb *.vcd *.fst + +help: + @echo "Shell environment:" + @echo " CVA6_REPO_DIR : $(CVA6_REPO_DIR)" + @echo " CVA6_TB_DIR : $(CVA6_TB_DIR)" + @echo "VCS targets:" + @echo " make vcs_uvm_comp : Compiles with VCS" + @echo " make vcs_uvm_run : Runs with VCS" + @echo "Clean-up targets:" + @echo " make clean_all : Deletes ALL generated files" + @echo "Support for other simulators on the ToDo list..." diff --git a/verif/sim/cov-exclude-mod.lst b/verif/sim/cov-exclude-mod.lst new file mode 100644 index 0000000000..0b31887aab --- /dev/null +++ b/verif/sim/cov-exclude-mod.lst @@ -0,0 +1,12 @@ +// Copyright 2021 Thales DIS design services SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Zineb EL KACIMI (zineb.el-kacimi@external.thalesgroup.com) + + +-tree uvmt_cva6_tb.cva6_dut_wrap.cva6_tb_wrapper_i.i_cva6.instr_tracer_i +-tree uvmt_cva6_tb.cva6_dut_wrap.cva6_tb_wrapper_i.i_cva6.tracer_if diff --git a/verif/sim/cva6-simulator.yaml b/verif/sim/cva6-simulator.yaml new file mode 100644 index 0000000000..caa42d0062 --- /dev/null +++ b/verif/sim/cva6-simulator.yaml @@ -0,0 +1,107 @@ +# Copyright Google LLC +# Copyright 2021 Thales DIS Design Services SAS +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# SPDX-License-Identifier: Apache-2.0 + +- tool: vcs + compile: + cmd: + - "vcs -file <cwd>/dv/vcs.compile.option.f + +incdir+<setting> + +incdir+<user_extension> + -f <cwd>/dv/files.f -full64 + -l <out>/compile.log + -LDFLAGS '-Wl,--no-as-needed' + -Mdir=<out>/vcs_simv.csrc + -o <out>/vcs_simv <cmp_opts> <cov_opts> " + cov_opts: > + -cm_dir <out>/test.vdb + sim: + cmd: > + <out>/vcs_simv +vcs+lic+wait gen="true" <sim_opts> +ntb_random_seed=<seed> <cov_opts> + cov_opts: > + -cm_dir <out>/test.vdb -cm_log /dev/null -cm_name test_<seed>_<test_id> + +- tool: ius + compile: + cmd: + - "irun -64bit -access +rwc -f <cwd>/dv/files.f + +incdir+<setting> + +incdir+<user_extension> + -q -sv -uvm -vlog_ext +.vh -I. + -uvmhome CDNS-1.2 + -elaborate + -l <out>/compile.log <cmp_opts>" + sim: + cmd: > + irun -R <sim_opts> -svseed <seed> -svrnc rand_struct + +- tool: questa + compile: + cmd: + - "vmap mtiUvm $QUESTA_HOME/questasim/uvm-1.2" + - "vlog -64 + +incdir+<setting> + +incdir+<user_extension> + -access=rwc + -f <cwd>/dv/files.f + -sv + -mfcu -cuname design_cuname + +define+UVM_REGEX_NO_DPI + -writetoplevels <out>/top.list + -l <out>/compile.log <cmp_opts>" + - "vopt -64 -debug + +designfile -f <out>/top.list + -l <out>/optimize.log <cmp_opts> + -o design_opt" + sim: + cmd: > + vsim -64 -c <cov_opts> -do <cwd>/dv/questa_sim.tcl design_opt <sim_opts> -sv_seed <seed> + cov_opts: > + -do "coverage save -onexit <out>/cov.ucdb;" + +- tool: dsim + env_var: DSIM,DSIM_LIB_PATH + compile: + cmd: + - "mkdir -p <out>/dsim" + - "<DSIM> -sv -work <out>/dsim + -genimage image + +incdir+$UVM_HOME/src + $UVM_HOME/src/uvm_pkg.sv + +define+DSIM + -suppress EnumMustBePositive + +incdir+<setting> + +incdir+<user_extension> + -f <cwd>/dv/files.f + -l <out>/dsim/compile.log <cmp_opts>" + sim: + cmd: > + <DSIM> <sim_opts> -sv_seed <seed> -pli_lib <DSIM_LIB_PATH>/libuvm_dpi.so +acc+rwb -image image -work <out>/dsim + +- tool: qrun + compile: + cmd: + - "qrun -f <cwd>/dv/qrun_option.f + +incdir+<setting> + +incdir+<user_extension> + -f <cwd>/dv/files.f <cmp_opts> + -l <out>/qrun_compile_optimize.log + -outdir <out>/qrun.out" + sim: + cmd: > + qrun -64 -simulate -snapshot design_opt -c <cov_opts> <sim_opts> -sv_seed <seed> -outdir <out>/qrun.out + cov_opts: > + -coverage -ucdb <out>/cov.ucdb diff --git a/verif/sim/cva6.py b/verif/sim/cva6.py new file mode 100644 index 0000000000..1b566c039d --- /dev/null +++ b/verif/sim/cva6.py @@ -0,0 +1,1225 @@ +""" +Copyright 2019 Google LLC + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +Regression script for RISC-V random instruction generator +""" + +import argparse +import os +import re +import sys +import logging +import time +import datetime + +from dv.scripts.lib import * +from verilator_log_to_trace_csv import * +from cva6_spike_log_to_trace_csv import * +from dv.scripts.ovpsim_log_to_trace_csv import * +from dv.scripts.whisper_log_trace_csv import * +from dv.scripts.sail_log_to_trace_csv import * +from dv.scripts.instr_trace_compare import * + +from types import SimpleNamespace + +LOGGER = logging.getLogger() + +def get_generator_cmd(simulator, simulator_yaml, cov, exp, debug_cmd): + """ Setup the compile and simulation command for the generator + + Args: + simulator : RTL simulator used to run instruction generator + simulator_yaml : RTL simulator configuration file in YAML format + cov : Enable functional coverage + exp : Use experimental version + debug_cmd : Produce the debug cmd log without running + + Returns: + compile_cmd : RTL simulator command to compile the instruction generator + sim_cmd : RTL simulator command to run the instruction generator + """ + logging.info("Processing simulator setup file : %s" % simulator_yaml) + yaml_data = read_yaml(simulator_yaml) + # Search for matched simulator + for entry in yaml_data: + if entry['tool'] == simulator: + logging.info("Found matching simulator: %s" % entry['tool']) + compile_spec = entry['compile'] + compile_cmd = compile_spec['cmd'] + for i in range(len(compile_cmd)): + if ('cov_opts' in compile_spec) and cov: + compile_cmd[i] = re.sub('<cov_opts>', compile_spec['cov_opts'].rstrip(), compile_cmd[i]) + else: + compile_cmd[i] = re.sub('<cov_opts>', '', compile_cmd[i]) + if exp: + compile_cmd[i] += " +define+EXPERIMENTAL " + sim_cmd = entry['sim']['cmd'] + if ('cov_opts' in entry['sim']) and cov: + sim_cmd = re.sub('<cov_opts>', entry['sim']['cov_opts'].rstrip(), sim_cmd) + else: + sim_cmd = re.sub('<cov_opts>', '', sim_cmd) + if 'env_var' in entry: + for env_var in entry['env_var'].split(','): + for i in range(len(compile_cmd)): + compile_cmd[i] = re.sub("<"+env_var+">", get_env_var(env_var, debug_cmd = debug_cmd), + compile_cmd[i]) + sim_cmd = re.sub("<"+env_var+">", get_env_var(env_var, debug_cmd = debug_cmd), sim_cmd) + return compile_cmd, sim_cmd + logging.error("Cannot find RTL simulator %0s" % simulator) + sys.exit(RET_FAIL) + + +def parse_iss_yaml(iss, iss_yaml, isa, target, setting_dir, debug_cmd): + """Parse ISS YAML to get the simulation command + + Args: + iss : target ISS used to look up in ISS YAML + iss_yaml : ISS configuration file in YAML format + isa : ISA variant passed to the ISS + setting_dir : Generator setting directory + debug_cmd : Produce the debug cmd log without running + + Returns: + cmd : ISS run command + """ + logging.info("Processing ISS setup file : %s" % iss_yaml) + yaml_data = read_yaml(iss_yaml) + # Search for matched ISS + for entry in yaml_data: + if entry['iss'] == iss: + logging.info("Found matching ISS: %s" % entry['iss']) + m = re.search(r"rv(?P<xlen>[0-9]+?)(?P<variant>[a-z]+(_[szx]\w+)*)$", isa) + if m: logging.info("ISA %0s" % isa) + else: logging.error("Illegal ISA %0s" % isa) + + cmd = entry['cmd'].rstrip() + cmd = re.sub("\<path_var\>", get_env_var(entry['path_var'], debug_cmd = debug_cmd), cmd) + cmd = re.sub("\<tool_path\>", get_env_var(entry['tool_path'], debug_cmd = debug_cmd), cmd) + cmd = re.sub("\<tb_path\>", get_env_var(entry['tb_path'], debug_cmd = debug_cmd), cmd) + cmd = re.sub("\<isscomp_opts\>", isscomp_opts, cmd) + cmd = re.sub("\<issrun_opts\>", issrun_opts, cmd) + cmd = re.sub("\<isspostrun_opts\>", isspostrun_opts, cmd) + if m: cmd = re.sub("\<xlen\>", m.group('xlen'), cmd) + if iss == "ovpsim": + cmd = re.sub("\<cfg_path\>", setting_dir, cmd) + elif iss == "whisper": + if m: + # TODO: Support u/s mode + variant = re.sub('g', 'imafd', m.group('variant')) + cmd = re.sub("\<variant\>", variant, cmd) + else: + cmd = re.sub("\<variant\>", isa, cmd) + + return cmd + logging.error("Cannot find ISS %0s" % iss) + sys.exit(RET_FAIL) + + +def get_iss_cmd(base_cmd, elf, target, log): + """Get the ISS simulation command + + Args: + base_cmd : Original command template + elf : ELF file to run ISS simualtion + log : ISS simulation log name + + Returns: + cmd : Command for ISS simulation + """ + cmd = re.sub("\<elf\>", elf, base_cmd) + cmd = re.sub("\<target\>", target, cmd) + cmd = re.sub("\<log\>", log, cmd) + cmd += (" &> %s.iss" % log) + return cmd + + +def do_compile(compile_cmd, test_list, core_setting_dir, cwd, ext_dir, + cmp_opts, output_dir, debug_cmd, lsf_cmd): + """Compile the instruction generator + + Args: + compile_cmd : Compile command for the generator + test_list : List of assembly programs to be compiled + core_setting_dir : Path for riscv_core_setting.sv + cwd : Filesystem path to RISCV-DV repo + ext_dir : User extension directory + cmd_opts : Compile options for the generator + output_dir : Output directory of the ELF files + debug_cmd : Produce the debug cmd log without running + lsf_cmd : LSF command used to run the instruction generator + """ + if (not((len(test_list) == 1) and (test_list[0]['test'] == 'riscv_csr_test'))): + logging.info("Building RISC-V instruction generator") + for cmd in compile_cmd: + cmd = re.sub("<out>", os.path.abspath(output_dir), cmd) + cmd = re.sub("<setting>", core_setting_dir, cmd) + if ext_dir == "": + cmd = re.sub("<user_extension>", "<cwd>/dv/user_extension", cmd) + else: + cmd = re.sub("<user_extension>", ext_dir, cmd) + cmd = re.sub("<cwd>", cwd, cmd) + cmd = re.sub("<cmp_opts>", cmp_opts, cmd) + if lsf_cmd: + cmd = lsf_cmd + " " + cmd + run_parallel_cmd([cmd], debug_cmd = debug_cmd) + else: + logging.debug("Compile command: %s" % cmd) + run_cmd(cmd, debug_cmd = debug_cmd) + + +def run_csr_test(cmd_list, cwd, csr_file, isa, iterations, lsf_cmd, + end_signature_addr, timeout_s, output_dir, debug_cmd): + """Run CSR test + It calls a separate python script to generate directed CSR test code, + located at scripts/gen_csr_test.py. + """ + cmd = "python3 " + cwd + "/scripts/gen_csr_test.py" + \ + (" --csr_file %s" % csr_file) + \ + (" --xlen %s" % re.search(r"(?P<xlen>[0-9]+)", isa).group("xlen")) + \ + (" --iterations %i" % iterations) + \ + (" --out %s/asm_tests" % output_dir) + \ + (" --end_signature_addr %s" % end_signature_addr) + if lsf_cmd: + cmd_list.append(cmd) + else: + run_cmd(cmd, timeout_s, debug_cmd = debug_cmd) + + +def do_simulate(sim_cmd, test_list, cwd, sim_opts, seed_yaml, seed, csr_file, + isa, end_signature_addr, lsf_cmd, timeout_s, log_suffix, + batch_size, output_dir, verbose, check_return_code, debug_cmd): + """Run the instruction generator + + Args: + sim_cmd : Simulate command for the generator + test_list : List of assembly programs to be compiled + cwd : Filesystem path to RISCV-DV repo + sim_opts : Simulation options for the generator + seed_yaml : Seed specification from a prior regression + seed : Seed to the instruction generator + csr_file : YAML file containing description of all CSRs + isa : Processor supported ISA subset + end_signature_addr : Address that tests will write pass/fail signature to at end of test + lsf_cmd : LSF command used to run the instruction generator + timeout_s : Timeout limit in seconds + log_suffix : Simulation log file name suffix + batch_size : Number of tests to generate per run + output_dir : Output directory of the ELF files + check_return_code : Check return code of the command + debug_cmd : Produce the debug cmd log without running + """ + cmd_list = [] + sim_cmd = re.sub("<out>", os.path.abspath(output_dir), sim_cmd) + sim_cmd = re.sub("<cwd>", cwd, sim_cmd) + sim_cmd = re.sub("<sim_opts>", sim_opts, sim_cmd) + rerun_seed = {} + if seed_yaml: + rerun_seed = read_yaml(seed_yaml) + logging.info("Running RISC-V instruction generator") + sim_seed = {} + for test in test_list: + iterations = test['iterations'] + logging.info("Generating %d %s" % (iterations, test['test'])) + if iterations > 0: + # Running a CSR test + if test['test'] == 'riscv_csr_test': + run_csr_test(cmd_list, cwd, csr_file, isa, iterations, lsf_cmd, + end_signature_addr, timeout_s, output_dir, debug_cmd) + else: + batch_cnt = 1 + if batch_size > 0: + batch_cnt = int((iterations + batch_size - 1) / batch_size); + logging.info("Running %s with %0d batches" % (test['test'], batch_cnt)) + for i in range(0, batch_cnt): + test_id = '%0s_%0d' % (test['test'], i) + if test_id in rerun_seed: + rand_seed = rerun_seed[test_id] + else: + rand_seed = get_seed(seed) + if i < batch_cnt - 1: + test_cnt = batch_size + else: + test_cnt = iterations - i * batch_size; + cmd = lsf_cmd + " " + sim_cmd.rstrip() + \ + (" +UVM_TESTNAME=%s " % test['gen_test']) + \ + (" +num_of_tests=%i " % test_cnt) + \ + (" +start_idx=%d " % (i*batch_size)) + \ + (" +asm_file_name=%s/asm_tests/%s " % (output_dir, test['test'])) + \ + (" -l %s/sim_%s_%d%s.log " % (output_dir, test['test'], i, log_suffix)) + if verbose: + cmd += "+UVM_VERBOSITY=UVM_HIGH " + cmd = re.sub("<seed>", str(rand_seed), cmd) + cmd = re.sub("<test_id>", test_id, cmd) + sim_seed[test_id] = str(rand_seed) + if "gen_opts" in test: + cmd += test['gen_opts'] + if not re.search("c", isa): + cmd += "+disable_compressed_instr=1 "; + if lsf_cmd: + cmd_list.append(cmd) + else: + logging.info("Running %s, batch %0d/%0d, test_cnt:%0d" % + (test['test'], i+1, batch_cnt, test_cnt)) + run_cmd(cmd, timeout_s, check_return_code = check_return_code, debug_cmd = debug_cmd) + if sim_seed: + with open(('%s/seed.yaml' % os.path.abspath(output_dir)) , 'w') as outfile: + yaml.dump(sim_seed, outfile, default_flow_style=False) + with open(('seedlist.yaml') , 'a') as seedlist: + yaml.dump(sim_seed, seedlist, default_flow_style=False) + if lsf_cmd: + run_parallel_cmd(cmd_list, timeout_s, check_return_code = check_return_code, + debug_cmd = debug_cmd) + + +def gen(test_list, cfg, output_dir, cwd): + """Run the instruction generator + + Args: + test_list : List of assembly programs to be compiled + cfg : Loaded configuration dictionary. + output_dir : Output directory of the ELF files + cwd : Filesystem path to RISCV-DV repo + """ + # Convert key dictionary to argv variable + argv= SimpleNamespace(**cfg) + + check_return_code = True + if argv.simulator == "ius": + # Incisive return non-zero return code even test passes + check_return_code = False + logging.debug("Disable return_code checking for %s" % argv.simulator) + # Mutually exclusive options between compile_only and sim_only + if argv.co and argv.so: + logging.error("argument -co is not allowed with argument -so") + return + if ((argv.co == 0) and (len(test_list) == 0)): + return + # Setup the compile and simulation command for the generator + compile_cmd = [] + sim_cmd = "" + compile_cmd, sim_cmd = get_generator_cmd(argv.simulator, argv.simulator_yaml, argv.cov, + argv.exp, argv.debug); + # Compile the instruction generator + if not argv.so: + do_compile(compile_cmd, test_list, argv.core_setting_dir, cwd, argv.user_extension_dir, + argv.cmp_opts, output_dir, argv.debug, argv.lsf_cmd) + # Run the instruction generator + if not argv.co: + do_simulate(sim_cmd, test_list, cwd, argv.sim_opts, argv.seed_yaml, argv.seed, argv.csr_yaml, + argv.isa, argv.end_signature_addr, argv.lsf_cmd, argv.gen_timeout, argv.log_suffix, + argv.batch_size, output_dir, argv.verbose, check_return_code, argv.debug) + + +# Convert the ELF to plain binary, used in RTL sim +def elf2bin(elf, binary, debug_cmd): + logging.info("Converting to %s" % binary) + cmd = ("%s -O binary %s %s" % (get_env_var("RISCV_OBJCOPY", debug_cmd = debug_cmd), elf, binary)) + run_cmd_output(cmd.split(), debug_cmd = debug_cmd) + + +def gcc_compile(test_list, output_dir, isa, mabi, opts, debug_cmd, linker): + """Use riscv gcc toolchain to compile the assembly program + + Args: + test_list : List of assembly programs to be compiled + output_dir : Output directory of the ELF files + isa : ISA variant passed to GCC + mabi : MABI variant passed to GCC + debug_cmd : Produce the debug cmd log without running + linker : Path to the linker + """ + cwd = os.path.dirname(os.path.realpath(__file__)) + for test in test_list: + for i in range(0, test['iterations']): + if 'no_gcc' in test and test['no_gcc'] == 1: + continue + prefix = ("%s/asm_tests/%s_%d" % (output_dir, test['test'], i)) + asm = prefix + ".S" + elf = prefix + ".o" + binary = prefix + ".bin" + test_isa=re.match("[a-z0-9A-Z]+", isa) + test_isa=test_isa.group() + isa_ext=isa + if not os.path.isfile(asm) and not debug_cmd: + logging.error("Cannot find assembly test: %s\n", asm) + sys.exit(RET_FAIL) + # gcc comilation + cmd = ("%s -static -mcmodel=medany \ + -fvisibility=hidden -nostdlib \ + -nostartfiles %s \ + -I%s/../env/corev-dv/user_extension \ + -T%s %s -o %s " % \ + (get_env_var("RISCV_GCC", debug_cmd = debug_cmd), asm, cwd, linker, opts, elf)) + if 'gcc_opts' in test: + cmd += test['gcc_opts'] + if 'gen_opts' in test: + # Disable compressed instruction + if re.search('disable_compressed_instr=1', test['gen_opts']): + test_isa = re.sub("c", "", test_isa) + #add z,s,x extensions to the isa if there are some + if isa_extension_list !=['none']: + for i in isa_extension_list: + test_isa += (f"_{i}") + isa_ext=test_isa + # If march/mabi is not defined in the test gcc_opts, use the default + # setting from the command line. + if not re.search('march', cmd): + cmd += (" -march=%s" % isa_ext) + if not re.search('mabi', cmd): + cmd += (" -mabi=%s" % mabi) + logging.info("Compiling test : %s" % asm) + run_cmd_output(cmd.split(), debug_cmd = debug_cmd) + elf2bin(elf, binary, debug_cmd) + + +def run_assembly(asm_test, iss_yaml, isa, target, mabi, gcc_opts, iss_opts, output_dir, + setting_dir, debug_cmd, linker): + """Run a directed assembly test with ISS + + Args: + asm_test : Assembly test file + iss_yaml : ISS configuration file in YAML format + isa : ISA variant passed to the ISS + mabi : MABI variant passed to GCC + gcc_opts : User-defined options for GCC compilation + iss_opts : Instruction set simulators + output_dir : Output directory of compiled test files + setting_dir : Generator setting directory + debug_cmd : Produce the debug cmd log without running + linker : Path to the linker + """ + if not asm_test.endswith(".S"): + logging.error("%s is not an assembly .S file" % asm_test) + return + cwd = os.path.dirname(os.path.realpath(__file__)) + asm_test = os.path.expanduser(asm_test) + report = ("%s/iss_regr.log" % output_dir).rstrip() + asm = re.sub(r"^.*\/", "", asm_test) + asm = re.sub(r"\.S$", "", asm) + if os.getenv('cov'): + asm = asm + "-" + str(datetime.datetime.now().isoformat()) + prefix = ("%s/directed_asm_tests/%s" % (output_dir, asm)) + elf = prefix + ".o" + binary = prefix + ".bin" + iss_list = iss_opts.split(",") + run_cmd("mkdir -p %s/directed_asm_tests" % output_dir) + logging.info("Compiling assembly test : %s" % asm_test) + + # gcc compilation + cmd = ("%s -static -mcmodel=medany \ + -fvisibility=hidden -nostdlib \ + -nostartfiles %s \ + -I%s/../env/corev-dv/user_extension \ + -T%s %s -o %s " % \ + (get_env_var("RISCV_GCC", debug_cmd = debug_cmd), asm_test, cwd, linker, + gcc_opts, elf)) + cmd += (" -march=%s" % isa) + cmd += (" -mabi=%s" % mabi) + run_cmd_output(cmd.split(), debug_cmd = debug_cmd) + elf2bin(elf, binary, debug_cmd) + log_list = [] + # ISS simulation + for iss in iss_list: + run_cmd("mkdir -p %s/%s_sim" % (output_dir, iss)) + if log_format == 1: + log = ("%s/%s_sim/%s_%d.log" % (output_dir, iss, asm, test_iteration)) + else: + log = ("%s/%s_sim/%s.log" % (output_dir, iss, asm)) + log_list.append(log) + base_cmd = parse_iss_yaml(iss, iss_yaml, isa, target, setting_dir, debug_cmd) + cmd = get_iss_cmd(base_cmd, elf, target, log) + logging.info("[%0s] Running ISS simulation: %s" % (iss, cmd)) + run_cmd(cmd, 300, debug_cmd = debug_cmd) + logging.info("[%0s] Running ISS simulation: %s ...done" % (iss, elf)) + if len(iss_list) == 2: + compare_iss_log(iss_list, log_list, report) + + +def run_assembly_from_dir(asm_test_dir, iss_yaml, isa, mabi, gcc_opts, iss, + output_dir, setting_dir, debug_cmd): + """Run a directed assembly test from a directory with spike + + Args: + asm_test_dir : Assembly test file directory + iss_yaml : ISS configuration file in YAML format + isa : ISA variant passed to the ISS + mabi : MABI variant passed to GCC + gcc_opts : User-defined options for GCC compilation + iss : Instruction set simulators + output_dir : Output directory of compiled test files + setting_dir : Generator setting directory + debug_cmd : Produce the debug cmd log without running + """ + result = run_cmd("find %s -name \"*.S\"" % asm_test_dir) + if result: + asm_list = result.splitlines() + logging.info("Found %0d assembly tests under %s" % + (len(asm_list), asm_test_dir)) + for asm_file in asm_list: + run_assembly(asm_file, iss_yaml, isa, target, mabi, gcc_opts, iss, output_dir, + setting_dir, debug_cmd, linker) + if "," in iss: + report = ("%s/iss_regr.log" % output_dir).rstrip() + save_regr_report(report) + else: + logging.error("No assembly test(*.S) found under %s" % asm_test_dir) + +# python3 run.py --target rv64gc --iss=spike,verilator --elf_tests bbl.o +def run_elf(c_test, iss_yaml, isa, target, mabi, gcc_opts, iss_opts, output_dir, + setting_dir, debug_cmd): + """Run a directed c test with ISS + + Args: + c_test : C test file + iss_yaml : ISS configuration file in YAML format + isa : ISA variant passed to the ISS + mabi : MABI variant passed to GCC + gcc_opts : User-defined options for GCC compilation + iss_opts : Instruction set simulators + output_dir : Output directory of compiled test files + setting_dir : Generator setting directory + debug_cmd : Produce the debug cmd log without running + """ + if not c_test.endswith(".o"): + logging.error("%s is not a .o file" % c_test) + return + cwd = os.path.dirname(os.path.realpath(__file__)) + c_test = os.path.expanduser(c_test) + report = ("%s/iss_regr.log" % output_dir).rstrip() + c = re.sub(r"^.*\/", "", c_test) + c = re.sub(r"\.o$", "", c) + prefix = ("%s/directed_elf_tests/%s" % (output_dir, c)) + elf = prefix + ".o" + binary = prefix + ".bin" + iss_list = iss_opts.split(",") + run_cmd("mkdir -p %s/directed_elf_tests" % output_dir, 600, debug_cmd=debug_cmd) + logging.info("Copy elf test : %s" % c_test) + run_cmd("cp %s %s/directed_elf_tests" % (c_test, output_dir)) + elf2bin(elf, binary, debug_cmd) + log_list = [] + # ISS simulation + for iss in iss_list: + run_cmd("mkdir -p %s/%s_sim" % (output_dir, iss)) + log = ("%s/%s_sim/%s.log" % (output_dir, iss, c)) + log_list.append(log) + base_cmd = parse_iss_yaml(iss, iss_yaml, isa, target, setting_dir, debug_cmd) + cmd = get_iss_cmd(base_cmd, elf, target, log) + logging.info("[%0s] Running ISS simulation: %s" % (iss, cmd)) + if "veri" in iss: ratio = 35 + else: ratio = 1 + run_cmd(cmd, 50000*ratio, debug_cmd = debug_cmd) + logging.info("[%0s] Running ISS simulation: %s ...done" % (iss, elf)) + if len(iss_list) == 2: + compare_iss_log(iss_list, log_list, report) + + +def run_c(c_test, iss_yaml, isa, target, mabi, gcc_opts, iss_opts, output_dir, + setting_dir, debug_cmd, linker): + """Run a directed c test with ISS + + Args: + c_test : C test file + iss_yaml : ISS configuration file in YAML format + isa : ISA variant passed to the ISS + mabi : MABI variant passed to GCC + gcc_opts : User-defined options for GCC compilation + iss_opts : Instruction set simulators + output_dir : Output directory of compiled test files + setting_dir : Generator setting directory + debug_cmd : Produce the debug cmd log without running + linker : Path to the linker + """ + if not c_test.endswith(".c"): + logging.error("%s is not a .c file" % c_test) + return + cwd = os.path.dirname(os.path.realpath(__file__)) + c_test = os.path.expanduser(c_test) + report = ("%s/iss_regr.log" % output_dir).rstrip() + c = re.sub(r"^.*\/", "", c_test) + c = re.sub(r"\.c$", "", c) + prefix = (f"{output_dir}/directed_c_tests/{c}") + elf = prefix + ".o" + binary = prefix + ".bin" + iss_list = iss_opts.split(",") + run_cmd("mkdir -p %s/directed_c_tests" % output_dir) + logging.info("Compiling c test : %s" % c_test) + + # gcc compilation + cmd = ("%s -mcmodel=medany -nostdlib \ + -nostartfiles %s \ + -I%s/dv/user_extension \ + -T%s %s -o %s " % \ + (get_env_var("RISCV_GCC", debug_cmd = debug_cmd), c_test, cwd, + linker, gcc_opts, elf)) + cmd += (" -march=%s" % isa) + cmd += (" -mabi=%s" % mabi) + run_cmd(cmd, debug_cmd = debug_cmd) + elf2bin(elf, binary, debug_cmd) + log_list = [] + # ISS simulation + for iss in iss_list: + run_cmd("mkdir -p %s/%s_sim" % (output_dir, iss)) + if log_format == 1: + log = ("%s/%s_sim/%s_%d.log" % (output_dir, iss, c, test_iteration)) + else: + log = ("%s/%s_sim/%s.log" % (output_dir, iss, c)) + log_list.append(log) + base_cmd = parse_iss_yaml(iss, iss_yaml, isa, target, setting_dir, debug_cmd) + cmd = get_iss_cmd(base_cmd, elf, target, log) + logging.info("[%0s] Running ISS simulation: %s" % (iss, cmd)) + run_cmd(cmd, 300, debug_cmd = debug_cmd) + logging.info("[%0s] Running ISS simulation: %s ...done" % (iss, elf)) + if len(iss_list) == 2: + compare_iss_log(iss_list, log_list, report) + + +def run_c_from_dir(c_test_dir, iss_yaml, isa, mabi, gcc_opts, iss, + output_dir, setting_dir, debug_cmd): + """Run a directed c test from a directory with spike + + Args: + c_test_dir : C test file directory + iss_yaml : ISS configuration file in YAML format + isa : ISA variant passed to the ISS + mabi : MABI variant passed to GCC + gcc_opts : User-defined options for GCC compilation + iss : Instruction set simulators + output_dir : Output directory of compiled test files + setting_dir : Generator setting directory + debug_cmd : Produce the debug cmd log without running + """ + result = run_cmd("find %s -name \"*.c\"" % c_test_dir) + if result: + c_list = result.splitlines() + logging.info("Found %0d c tests under %s" % + (len(c_list), c_test_dir)) + for c_file in c_list: + run_c(c_file, iss_yaml, isa, target, mabi, gcc_opts, iss, output_dir, + setting_dir, debug_cmd, linker) + if "," in iss: + report = ("%s/iss_regr.log" % output_dir).rstrip() + save_regr_report(report) + else: + logging.error("No c test(*.c) found under %s" % c_test_dir) + + +def iss_sim(test_list, output_dir, iss_list, iss_yaml, iss_opts, + isa, target, setting_dir, timeout_s, debug_cmd): + """Run ISS simulation with the generated test program + + Args: + test_list : List of assembly programs to be compiled + output_dir : Output directory of the ELF files + iss_list : List of instruction set simulators + iss_yaml : ISS configuration file in YAML format + iss_opts : ISS command line options + isa : ISA variant passed to the ISS + setting_dir : Generator setting directory + timeout_s : Timeout limit in seconds + debug_cmd : Produce the debug cmd log without running + """ + for iss in iss_list.split(","): + log_dir = ("%s/%s_sim" % (output_dir, iss)) + base_cmd = parse_iss_yaml(iss, iss_yaml, isa, target, setting_dir, debug_cmd) + logging.info("%s sim log dir: %s" % (iss, log_dir)) + run_cmd_output(["mkdir", "-p", log_dir]) + for test in test_list: + if 'no_iss' in test and test['no_iss'] == 1: + continue + else: + for i in range(0, test['iterations']): + prefix = ("%s/asm_tests/%s_%d" % (output_dir, test['test'], i)) + elf = prefix + ".o" + log = ("%s/%s.%d.log" % (log_dir, test['test'], i)) + cmd = get_iss_cmd(base_cmd, elf, target, log) + if 'iss_opts' in test: + cmd += ' ' + cmd += test['iss_opts'] + logging.info("Running %s sim: %s" % (iss, elf)) + if iss == "ovpsim": + run_cmd(cmd, timeout_s, check_return_code=False, debug_cmd = debug_cmd) + else: + run_cmd(cmd, timeout_s, debug_cmd = debug_cmd) + logging.debug(cmd) + + +def iss_cmp(test_list, iss, output_dir, stop_on_first_error, exp, debug_cmd): + """Compare ISS simulation reult + + Args: + test_list : List of assembly programs to be compiled + iss : List of instruction set simulators + output_dir : Output directory of the ELF files + stop_on_first_error : will end run on first error detected + exp : Use experimental version + debug_cmd : Produce the debug cmd log without running + """ + if debug_cmd: + return + iss_list = iss.split(",") + if len(iss_list) != 2: + return + report = ("%s/iss_regr.log" % output_dir).rstrip() + for test in test_list: + for i in range(0, test['iterations']): + elf = ("%s/asm_tests/%s_%d.o" % (output_dir, test['test'], i)) + logging.info("Comparing ISS sim result %s/%s : %s" % + (iss_list[0], iss_list[1], elf)) + log_list = [] + run_cmd(("echo 'Test binary: %s' >> %s" % (elf, report))) + for iss in iss_list: + log_list.append("%s/%s_sim/%s.%d.log" % (output_dir, iss, test['test'], i)) + compare_iss_log(iss_list, log_list, report, stop_on_first_error, exp) + save_regr_report(report) + + +def compare_iss_log(iss_list, log_list, report, stop_on_first_error=0, exp=False): + if (len(iss_list) != 2 or len(log_list) != 2) : + logging.error("Only support comparing two ISS logs") + logging.info("len(iss_list) = %s len(log_list) = %s" % (len(iss_list), len(log_list))) + else: + csv_list = [] + for i in range(2): + log = log_list[i] + csv = log.replace(".log", ".csv"); + iss = iss_list[i] + csv_list.append(csv) + if iss == "spike": + process_spike_sim_log(log, csv) + elif "veri" in iss or "vsim" in iss or "vcs" in iss or "questa" in iss: + process_verilator_sim_log(log, csv) + elif iss == "ovpsim": + process_ovpsim_sim_log(log, csv, stop_on_first_error) + elif iss == "sail": + process_sail_sim_log(log, csv) + elif iss == "whisper": + process_whisper_sim_log(log, csv) + else: + logging.error("Unsupported ISS" % iss) + sys.exit(RET_FAIL) + result = compare_trace_csv(csv_list[0], csv_list[1], iss_list[0], iss_list[1], report) + logging.info(result) + + +def save_regr_report(report): + passed_cnt = run_cmd("grep '\[PASSED\]' %s | wc -l" % report).strip() + failed_cnt = run_cmd("grep '\[FAILED\]' %s | wc -l" % report).strip() + summary = ("%s PASSED, %s FAILED" % (passed_cnt, failed_cnt)) + logging.info(summary) + run_cmd(("echo %s >> %s" % (summary, report))) + if failed_cnt != "0": + failed_details = run_cmd("sed -e 's,.*_sim/,,' %s | grep '\(csv\|matched\)' | uniq | sed -e 'N;s/\\n/ /g' | grep '\[FAILED\]'" % report).strip() + logging.info(failed_details) + run_cmd(("echo %s >> %s" % (failed_details, report))) + #sys.exit(RET_FAIL) #Do not return error code in case of test fail. + logging.info("ISS regression report is saved to %s" % report) + + +def setup_parser(): + """Create a command line parser. + + Returns: The created parser. + """ + # Parse input arguments + parser = argparse.ArgumentParser() + + parser.add_argument("--target", type=str, default="rv32imc", + help="Run the generator with pre-defined targets: \ + rv32imc, rv32i, rv32ima, rv64imc, rv64gc, rv64imac") + parser.add_argument("-o", "--output", type=str, + help="Output directory name", dest="o") + parser.add_argument("-tl", "--testlist", type=str, default="", + help="Regression testlist", dest="testlist") + parser.add_argument("-tn", "--test", type=str, default="all", + help="Test name, 'all' means all tests in the list", dest="test") + parser.add_argument("--seed", type=int, default=-1, + help="Randomization seed, default -1 means random seed") + parser.add_argument("-i", "--iterations", type=int, default=0, + help="Override the iteration count in the test list", dest="iterations") + parser.add_argument("-si", "--simulator", type=str, default="vcs", + help="Simulator used to run the generator, default VCS", dest="simulator") + parser.add_argument("--iss", type=str, default="spike", + help="RISC-V instruction set simulator: spike,ovpsim,sail") + parser.add_argument("-v", "--verbose", dest="verbose", action="store_true", default=False, + help="Verbose logging") + parser.add_argument("--co", dest="co", action="store_true", default=False, + help="Compile the generator only") + parser.add_argument("--cov", dest="cov", action="store_true", default=False, + help="Enable functional coverage") + parser.add_argument("--so", dest="so", action="store_true", default=False, + help="Simulate the generator only") + parser.add_argument("--cmp_opts", type=str, default="", + help="Compile options for the generator") + parser.add_argument("--sim_opts", type=str, default="", + help="Simulation options for the generator") + parser.add_argument("--gcc_opts", type=str, default="", + help="GCC compile options") + parser.add_argument("--issrun_opts", type=str, default="+debug_disable=1", + help="simulation run options") + parser.add_argument("--isscomp_opts", type=str, default="", + help="simulation comp options") + parser.add_argument("--isspostrun_opts", type=str, default="0x0000000080000000", + help="simulation post run options") + parser.add_argument("-s", "--steps", type=str, default="all", + help="Run steps: gen,gcc_compile,iss_sim,iss_cmp", dest="steps") + parser.add_argument("--lsf_cmd", type=str, default="", + help="LSF command. Run in local sequentially if lsf \ + command is not specified") + parser.add_argument("--isa", type=str, default="", + help="RISC-V ISA subset") + parser.add_argument("-m", "--mabi", type=str, default="", + help="mabi used for compilation", dest="mabi") + parser.add_argument("--gen_timeout", type=int, default=360, + help="Generator timeout limit in seconds") + parser.add_argument("--end_signature_addr", type=str, default="0", + help="Address that privileged CSR test writes to at EOT") + parser.add_argument("--iss_opts", type=str, default="", + help="Any ISS command line arguments") + parser.add_argument("--iss_timeout", type=int, default=10, + help="ISS sim timeout limit in seconds") + parser.add_argument("--iss_yaml", type=str, default="", + help="ISS setting YAML") + parser.add_argument("--simulator_yaml", type=str, default="", + help="RTL simulator setting YAML") + parser.add_argument("--csr_yaml", type=str, default="", + help="CSR description file") + parser.add_argument("--seed_yaml", type=str, default="", + help="Rerun the generator with the seed specification \ + from a prior regression") + parser.add_argument("-ct", "--custom_target", type=str, default="", + help="Directory name of the custom target") + parser.add_argument("-cs", "--core_setting_dir", type=str, default="", + help="Path for the riscv_core_setting.sv") + parser.add_argument("-ext", "--user_extension_dir", type=str, default="", + help="Path for the user extension directory") + parser.add_argument("--asm_tests", type=str, default="", + help="Directed assembly tests") + parser.add_argument("--c_tests", type=str, default="", + help="Directed c tests") + parser.add_argument("--elf_tests", type=str, default="", + help="Directed elf tests") + parser.add_argument("--log_suffix", type=str, default="", + help="Simulation log name suffix") + parser.add_argument("--exp", action="store_true", default=False, + help="Run generator with experimental features") + parser.add_argument("-bz", "--batch_size", type=int, default=0, + help="Number of tests to generate per run. You can split a big" + " job to small batches with this option") + parser.add_argument("--stop_on_first_error", dest="stop_on_first_error", + action="store_true", default=False, + help="Stop on detecting first error") + parser.add_argument("--noclean", action="store_true", default=True, + help="Do not clean the output of the previous runs") + parser.add_argument("--verilog_style_check", action="store_true", default=False, + help="Run verilog style check") + parser.add_argument("-d", "--debug", type=str, default="", + help="Generate debug command log file") + parser.add_argument("--hwconfig_opts", type=str, default="", + help="custom configuration options, to be passed in config_pkg_generator.py in cva6") + parser.add_argument("-l", "--linker", type=str, default="", + help="Path for the link.ld") + parser.add_argument("--axi_active", type=str, default="", + help="switch AXI agent mode: yes for Active, no for Passive") + parser.add_argument("--gen_sv_seed", type=int, default=0, + help="Run test N times with random seed") + parser.add_argument("--sv_seed", type=str, default="1", + help="Run test with a specific seed") + parser.add_argument("--isa_extension", type=str, default="", + help="Choose additional z, s, x extensions") + return parser + + +def load_config(args, cwd): + """ + Load configuration from the command line and the configuration file. + Args: + args: Parsed command-line configuration + Returns: + Loaded configuration dictionary. + """ + + global isa_extension_list + isa_extension_list = args.isa_extension.split(",") + isa_extension_list.append("zicsr") + isa_extension_list.append("zifencei") + + if args.debug: + args.debug = open(args.debug, "w") + if not args.csr_yaml: + args.csr_yaml = cwd + "/yaml/csr_template.yaml" + + if not args.iss_yaml: + args.iss_yaml = cwd + "/yaml/iss.yaml" + + if not args.simulator_yaml: + args.simulator_yaml = cwd + "/cva6-simulator.yaml" + + if not args.linker: + args.linker = cwd + "/link.ld" + + # Keep the core_setting_dir option to be backward compatible, suggest to use + # --custom_target + if args.core_setting_dir: + if not args.custom_target: + args.custom_target = args.core_setting_dir + else: + args.core_setting_dir = args.custom_target + + if not args.custom_target: + if not args.testlist: + args.testlist = cwd + "/target/"+ args.target +"/testlist.yaml" + if args.target == "cv64a6_imafdc_sv39": + args.mabi = "lp64d" + args.isa = "rv64gc" + elif args.target == "cv32a60x": # step1 configuration + args.mabi = "ilp32" + args.isa = "rv32imac" + elif args.target == "cv32a6_embedded": + args.mabi = "ilp32" + args.isa = "rv32imc" + elif args.target == "cv32a6_imac_sv0": + args.mabi = "ilp32" + args.isa = "rv32imac" + elif args.target == "cv32a6_imac_sv32": + args.mabi = "ilp32" + args.isa = "rv32imac" + elif args.target == "cv32a6_imafc_sv32": + args.mabi = "ilp32f" + args.isa = "rv32imafc" + elif args.target == "rv32imc": + args.mabi = "ilp32" + args.isa = "rv32imc" + elif args.target == "rv32imac": + args.mabi = "ilp32" + args.isa = "rv32imac" + elif args.target == "rv32ima": + args.mabi = "ilp32" + args.isa = "rv32ima" + elif args.target == "rv32gc": + args.mabi = "ilp32f" + args.isa = "rv32gc" + elif args.target == "multi_harts": + args.mabi = "ilp32f" + args.isa = "rv32gc" + elif args.target == "rv32imcb": + args.mabi = "ilp32" + args.isa = "rv32imcb" + elif args.target == "rv32i": + args.mabi = "ilp32" + args.isa = "rv32i" + elif args.target == "rv64imc": + args.mabi = "lp64" + args.isa = "rv64imc" + elif args.target == "rv64gc": + args.mabi = "lp64d" + args.isa = "rv64gc" + elif args.target == "rv64imac": + args.mabi = "lp64" + args.isa = "rv64imac" + elif args.target == "rv64gcv": + args.mabi = "lp64d" + args.isa = "rv64gcv" + elif args.target == "ml": + args.mabi = "lp64" + args.isa = "rv64imc" + elif args.target == "hwconfig": + current_path = os.getcwd() + os.chdir(os.getcwd()+"/../../") + [args.isa,args.mabi, args.target, args.hwconfig_opts] = generate_config(args.hwconfig_opts.split()) + os.chdir(current_path) + else: + sys.exit("Unsupported pre-defined target: %0s" % args.target) + args.core_setting_dir = cwd + "/dv" + "/target/"+ args.isa + else: + if re.match(".*gcc_compile.*", args.steps) or re.match(".*iss_sim.*", args.steps): + if (not args.mabi) or (not args.isa): + sys.exit("mabi and isa must be specified for custom target %0s" % args.custom_target) + if not args.testlist: + args.testlist = args.custom_target + "/testlist.yaml" + # Create loaded configuration dictionary. + cfg = vars(args) + return cfg + + +def main(): + """This is the main entry point.""" + try: + parser = setup_parser() + args = parser.parse_args() + global issrun_opts + global test_iteration + global log_format + if args.axi_active == "yes": + args.issrun_opts = args.issrun_opts + " +uvm_set_config_int=*uvm_test_top,force_axi_mode,1" + elif args.axi_active == "no": + args.issrun_opts = args.issrun_opts + " +uvm_set_config_int=uvm_test_top,force_axi_mode,0" + + if args.gen_sv_seed > 0 and args.sv_seed != "1": + logging.error('You cannot use gen_sv_seed and sv_seed options at the same time') + + if args.gen_sv_seed > 0: + args.issrun_opts = args.issrun_opts + " +ntb_random_seed_automatic" + log_format = 1 + elif args.gen_sv_seed == 0: + args.issrun_opts = args.issrun_opts + " +ntb_random_seed=" + args.sv_seed + args.gen_sv_seed = 1 + log_format = 0 + else: + logging.error('gen_sv_seed can not take a negative value') + + issrun_opts = "\""+args.issrun_opts+"\"" + + global isspostrun_opts + isspostrun_opts = "\""+args.isspostrun_opts+"\"" + global isscomp_opts + isscomp_opts = "\""+args.isscomp_opts+"\"" + cwd = os.path.dirname(os.path.realpath(__file__)) + os.environ["RISCV_DV_ROOT"] = cwd + "/dv" + os.environ["CVA6_DV_ROOT"] = cwd + "/../env/corev-dv" + setup_logging(args.verbose) + logg = logging.getLogger() + #Check gcc version + gcc_path=get_env_var("RISCV_GCC") + version=run_cmd("%s --version" % gcc_path) + gcc_version=re.match(".*\s(\d+\.\d+\.\d+).*", version) + gcc_version=gcc_version.group(1) + version_number=gcc_version.split('.') + if int(version_number[0])<11 : + logging.error('Your are currently using version %s of gcc, please update your version to version 11.1.0 or more to use all features of this script' % gcc_version) + sys.exit(RET_FAIL) + #print environment softwares + logging.info("GCC Version : %s" % (gcc_version)) + spike_version=get_env_var("SPIKE_ROOT") + logging.info("Spike Version : %s" % (spike_version)) + verilator_version=run_cmd("verilator --version") + logging.info("Verilator Version : %s" % (verilator_version)) + # create file handler which logs even debug messages13.1.1 + fh = logging.FileHandler('logfile.log') + fh.setLevel(logging.DEBUG) + # create formatter and add it to the handlers + formatter = logging.Formatter('%(asctime)s %(levelname)-8s %(message)s',datefmt='%a, %d %b %Y %H:%M:%S') + fh.setFormatter(formatter) + logg.addHandler(fh) + + # Load configuration from the command line and the configuration file. + cfg = load_config(args, cwd) + # Create output directory + output_dir = create_output(args.o, args.noclean, cwd+"/out_") + + #add z,s,x extensions to the isa if there are some + if isa_extension_list !=['']: + for i in isa_extension_list: + if i!= "": + args.isa += (f"_{i}") + + if args.verilog_style_check: + logging.debug("Run style check") + style_err = run_cmd("verilog_style/run.sh") + if style_err: logging.info("Found style error: \nERROR: " + style_err) + + for i in range(args.gen_sv_seed): + test_executed = 0 + test_iteration = i + print("") + logging.info("Execution numero : %s" % (i+1)) + # Run any handcoded/directed assembly tests specified by args.asm_tests + if args.asm_tests != "": + asm_test = args.asm_tests.split(',') + for path_asm_test in asm_test: + full_path = os.path.expanduser(path_asm_test) + # path_asm_test is a directory + if os.path.isdir(full_path): + run_assembly_from_dir(full_path, args.iss_yaml, args.isa, args.mabi, + args.gcc_opts, args.iss, output_dir, + args.core_setting_dir, args.debug) + # path_asm_test is an assembly file + elif os.path.isfile(full_path) or args.debug: + run_assembly(full_path, args.iss_yaml, args.isa, args.target, args.mabi, args.gcc_opts, + args.iss, output_dir, args.core_setting_dir, args.debug, args.linker) + else: + logging.error('%s does not exist' % full_path) + sys.exit(RET_FAIL) + test_executed = 1 + + # Run any handcoded/directed c tests specified by args.c_tests + if args.c_tests != "": + c_test = args.c_tests.split(',') + for path_c_test in c_test: + full_path = os.path.expanduser(path_c_test) + # path_c_test is a directory + if os.path.isdir(full_path): + run_c_from_dir(full_path, args.iss_yaml, args.isa, args.mabi, + args.gcc_opts, args.iss, output_dir, + args.core_setting_dir, args.debug) + # path_c_test is a c file + elif os.path.isfile(full_path) or args.debug: + run_c(full_path, args.iss_yaml, args.isa, args.target, args.mabi, args.gcc_opts, + args.iss, output_dir, args.core_setting_dir, args.debug, args.linker) + else: + logging.error('%s does not exist' % full_path) + sys.exit(RET_FAIL) + test_executed = 1 + + # Run any handcoded/directed elf tests specified by args.elf_tests + if args.elf_tests != "": + elf_test = args.elf_tests.split(',') + for path_elf_test in elf_test: + full_path = os.path.expanduser(path_elf_test) + # path_elf_test is an elf file + if os.path.isfile(full_path) or args.debug: + run_elf(full_path, args.iss_yaml, args.isa, args.target, args.mabi, args.gcc_opts, + args.iss, output_dir, args.core_setting_dir, args.debug) + else: + logging.error('%s does not exist' % full_path) + sys.exit(RET_FAIL) + test_executed = 1 + + run_cmd_output(["mkdir", "-p", ("%s/asm_tests" % output_dir)]) + # Process regression test list + matched_list = [] + # Any tests in the YAML test list that specify a directed assembly test + asm_directed_list = [] + # Any tests in the YAML test list that specify a directed c test + c_directed_list = [] + + if test_executed ==0: + if not args.co: + process_regression_list(args.testlist, args.test, args.iterations, matched_list, cwd) + logging.info('CVA6 Configuration is %s'% cfg["hwconfig_opts"]) + for entry in list(matched_list): + yaml_needs = entry["needs"] if "needs" in entry else [] + if yaml_needs: + needs = dict() + for i in range(len(yaml_needs)): + needs.update(yaml_needs[i]) + for keys in needs.keys(): + if cfg["hwconfig_opts"][keys] != needs[keys]: + logging.info('Removing test %s CVA6 configuration can not run it' % entry['test']) + matched_list.remove(entry) + break + for t in list(matched_list): + try: + t['gcc_opts'] = re.sub("\<path_var\>", get_env_var(t['path_var']), t['gcc_opts']) + except KeyError: + continue + + # Check mutual exclusive between gen_test, asm_tests, and c_tests + if 'asm_tests' in t: + if 'gen_test' in t or 'c_tests' in t: + logging.error('asm_tests must not be defined in the testlist ' + 'together with the gen_test or c_tests field') + sys.exit(RET_FATAL) + t['asm_tests'] = re.sub("\<path_var\>", get_env_var(t['path_var']), t['asm_tests']) + asm_directed_list.append(t) + matched_list.remove(t) + + if 'c_tests' in t: + if 'gen_test' in t or 'asm_tests' in t: + logging.error('c_tests must not be defined in the testlist ' + 'together with the gen_test or asm_tests field') + sys.exit(RET_FATAL) + t['c_tests'] = re.sub("\<path_var\>", get_env_var(t['path_var']), t['c_tests']) + c_directed_list.append(t) + matched_list.remove(t) + + if len(matched_list) == 0 and len(asm_directed_list) == 0 and len(c_directed_list) == 0: + sys.exit("Cannot find %s in %s" % (args.test, args.testlist)) + + for t in c_directed_list: + copy = re.sub(r'(.*)\/(.*).c$', r'cp \1/\2.c \1/', t['c_tests'])+t['test']+'.c' + run_cmd("%s" % copy) + t['c_tests'] = re.sub(r'(.*)\/(.*).c$', r'\1/', t['c_tests'])+t['test']+'.c' + + # Run instruction generator + if args.steps == "all" or re.match(".*gen.*", args.steps): + # Run any handcoded/directed assembly tests specified in YAML format + if len(asm_directed_list) != 0: + for test_entry in asm_directed_list: + gcc_opts = args.gcc_opts + gcc_opts += test_entry.get('gcc_opts', '') + path_asm_test = os.path.expanduser(test_entry.get('asm_tests')) + if path_asm_test: + # path_asm_test is a directory + if os.path.isdir(path_asm_test): + run_assembly_from_dir(path_asm_test, args.iss_yaml, args.isa, args.mabi, + gcc_opts, args.iss, output_dir, + args.core_setting_dir, args.debug) + # path_asm_test is an assembly file + elif os.path.isfile(path_asm_test): + run_assembly(path_asm_test, args.iss_yaml, args.isa, args.target, args.mabi, gcc_opts, + args.iss, output_dir, args.core_setting_dir, args.debug, args.linker) + else: + if not args.debug: + logging.error('%s does not exist' % path_asm_test) + sys.exit(RET_FAIL) + + # Run any handcoded/directed C tests specified in YAML format + if len(c_directed_list) != 0: + for test_entry in c_directed_list: + gcc_opts = args.gcc_opts + gcc_opts += test_entry.get('gcc_opts', '') + + if 'sim_do' in test_entry: + sim_do = test_entry['sim_do'].split(';') + with open("sim.do", "w") as fd: + for cmd in sim_do: + fd.write(cmd + "\n") + logging.info('sim.do: %s' % sim_do) + + path_c_test = os.path.expanduser(test_entry.get('c_tests')) + if path_c_test: + # path_c_test is a directory + if os.path.isdir(path_c_test): + run_c_from_dir(path_c_test, args.iss_yaml, args.isa, args.mabi, + gcc_opts, args.iss, output_dir, + args.core_setting_dir, args.debug) + # path_c_test is a C file + elif os.path.isfile(path_c_test): + run_c(path_c_test, args.iss_yaml, args.isa, args.target, args.mabi, gcc_opts, + args.iss, output_dir, args.core_setting_dir, args.debug, args.linker) + else: + if not args.debug: + logging.error('%s does not exist' % path_c_test) + sys.exit(RET_FAIL) + + # Run remaining tests using the instruction generator + gen(matched_list, cfg, output_dir, cwd) + + if not args.co: + # Compile the assembly program to ELF, convert to plain binary + if args.steps == "all" or re.match(".*gcc_compile.*", args.steps): + gcc_compile(matched_list, output_dir, args.isa, args.mabi, + args.gcc_opts, args.debug, args.linker) + + # Run ISS simulation + if args.steps == "all" or re.match(".*iss_sim.*", args.steps): + iss_sim(matched_list, output_dir, args.iss, args.iss_yaml, args.iss_opts, + args.isa, args.target, args.core_setting_dir, args.iss_timeout, args.debug) + + # Compare ISS simulation result + if args.steps == "all" or re.match(".*iss_cmp.*", args.steps): + iss_cmp(matched_list, args.iss, output_dir, args.stop_on_first_error, + args.exp, args.debug) + + sys.exit(RET_SUCCESS) + except KeyboardInterrupt: + logging.info("\nExited Ctrl-C from user request.") + sys.exit(130) + +if __name__ == "__main__": + sys.path.append(os.getcwd()+"/../../util") + from config_pkg_generator import * + main() + diff --git a/verif/sim/cva6.yaml b/verif/sim/cva6.yaml new file mode 100644 index 0000000000..4112c73fb9 --- /dev/null +++ b/verif/sim/cva6.yaml @@ -0,0 +1,65 @@ +# Copyright 2021 Thales DIS design services SAS +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Original Author: Jean-Roch COULON - Thales + +############################################################################### +# Spike +############################################################################### +- iss: spike + path_var: RTL_PATH + tool_path: SPIKE_PATH + tb_path: TB_PATH + # Set a limit of 2M steps for Spike to match the RVFI 2M cycles RTL timeout. + # Always keep this value in sync with the settings of RTL simulators (cf. + # <issrun_opts> values below). + cmd: > + make spike steps=2000000 variant=<variant> elf=<elf> tool_path=<tool_path> log=<log> + +############################################################################### +# Verilator +############################################################################### +- iss: veri-testharness + path_var: RTL_PATH + tool_path: SPIKE_PATH + tb_path: TB_PATH + cmd: > + make veri-testharness target=<target> variant=<variant> elf=<elf> path_var=<path_var> tool_path=<tool_path> isscomp_opts=<isscomp_opts> issrun_opts=<issrun_opts> isspostrun_opts=<isspostrun_opts> log=<log> + +############################################################################### +# Synopsys VCS specific commands, variables +############################################################################### +- iss: vcs-testharness + path_var: RTL_PATH + tool_path: SPIKE_PATH + tb_path: TB_PATH + cmd: > + make vcs-testharness target=<target> variant=<variant> elf=<elf> path_var=<path_var> tool_path=<tool_path> isscomp_opts=<isscomp_opts> issrun_opts=<issrun_opts> isspostrun_opts=<isspostrun_opts> log=<log> + +- iss: vcs-gate + path_var: RTL_PATH + tool_path: SPIKE_PATH + tb_path: TB_PATH + cmd: > + make vcs-uvm target=<target> gate=1 cov=${cov} variant=<variant> elf=<elf> tool_path=<tool_path> isscomp_opts=<isscomp_opts> issrun_opts=<issrun_opts> isspostrun_opts=<isspostrun_opts> log=<log> + +- iss: vcs-uvm + path_var: RTL_PATH + tool_path: SPIKE_PATH + tb_path: TB_PATH + cmd: > + make vcs-uvm target=<target> cov=${cov} variant=<variant> elf=<elf> tool_path=<tool_path> isscomp_opts=<isscomp_opts> issrun_opts=<issrun_opts> isspostrun_opts=<isspostrun_opts> log=<log> + +############################################################################### +# Questasim specific commands, variables +############################################################################### +- iss: questa-testharness + path_var: RTL_PATH + tool_path: SPIKE_PATH + tb_path: TB_PATH + cmd: > + make questa-testharness target=<target> variant=<variant> elf=<elf> path_var=<path_var> tool_path=<tool_path> isscomp_opts=<isscomp_opts> issrun_opts=<issrun_opts> isspostrun_opts=<isspostrun_opts> log=<log> diff --git a/verif/sim/cva6_base_testlist.yaml b/verif/sim/cva6_base_testlist.yaml new file mode 100644 index 0000000000..dd026edd88 --- /dev/null +++ b/verif/sim/cva6_base_testlist.yaml @@ -0,0 +1,506 @@ +# Copyright 2022 Thales DIS SAS +# +# CVA6-specific testlist. Written in the same format as riscv-dv testlists. +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Original Author: Ayoub JALALI (ayoub.jalali@external.thalesgroup.com) + +# ================================================================================ +# Regression test list format +# -------------------------------------------------------------------------------- +# test : Assembly test name +# description : Description of this test +# gen_opts : Instruction generator options +# iterations : Number of iterations of this test +# no_iss : Enable/disable ISS simulator (Optional) +# gen_test : Test name used by the instruction generator +# asm_tests : Path to directed, hand-coded assembly test file or directory +# c_tests : Path to directed, hand-coded C test file or directory +# rtl_test : RTL simulation test name +# cmp_opts : Compile options passed to the instruction generator +# sim_opts : Simulation options passed to the instruction generator +# no_post_compare : Enable/disable comparison of trace log and ISS log (Optional) +# compare_opts : Options for the RTL & ISS trace comparison +# gcc_opts : gcc compile options +# -------------------------------------------------------------------------------- + +- test: riscv_mmu_stress_test + description: > + Test with different patterns of load/store instructions, stress test MMU + operations. + gen_opts: > + +instr_cnt=500 + +num_of_sub_program=5 + +directed_instr_0=riscv_load_store_rand_instr_stream,10 + +directed_instr_1=riscv_load_store_hazard_instr_stream,10 + +directed_instr_2=riscv_multi_page_load_store_instr_stream,10 + +directed_instr_3=riscv_mem_region_stress_test,10 + +disable_compressed_instr=0 + iterations: 2 + gen_test: cva6_instr_base_test_c + rtl_test: core_base_test + +- test: riscv_mmu_stress_hint_test + description: > + Test with different patterns of load/store instructions, stress test MMU + operations. + gen_opts: > + +instr_cnt=500 + +num_of_sub_program=5 + +directed_instr_0=riscv_load_store_rand_instr_stream,10 + +directed_instr_1=riscv_load_store_hazard_instr_stream,10 + +directed_instr_2=riscv_multi_page_load_store_instr_stream,10 + +directed_instr_3=riscv_mem_region_stress_test,10 + +hint_instr_ratio=500 + iterations: 2 + gen_test: cva6_instr_base_test_c + rtl_test: core_base_test + +- test: riscv_rand_jump_illegal_test + description: > + Jump among large number of sub-programs, stress testing iTLB operations. + gen_opts: > + +instr_cnt=300 + +num_of_sub_program=0 + +directed_instr_0=riscv_load_store_rand_instr_stream,10 + +directed_instr_1=riscv_jal_instr,20 + +illegal_instr_ratio=100 + +tvec_alignment=8 + iterations: 2 + gen_test: cva6_instr_base_test_c + rtl_test: core_base_test + +- test: riscv_rand_jump_hint_comp_test + description: > + Jump among large number of sub-programs, stress testing iTLB operations. + gen_opts: > + +instr_cnt=500 + +num_of_sub_program=0 + +directed_instr_1=riscv_jal_instr,70 + +hint_instr_ratio=500 + iterations: 2 + gen_test: cva6_instr_base_test_c + rtl_test: core_base_test + +- test: riscv_rand_jump_no_cmp_test + description: > + Jump among large number of sub-programs, stress testing iTLB operations. + gen_opts: > + +instr_cnt=500 + +num_of_sub_program=0 + +directed_instr_0=riscv_jal_instr,70 + +disable_compressed_instr=1 + iterations: 2 + gen_test: cva6_instr_base_test_c + rtl_test: core_base_test + +- test: riscv_load_store_test + description: > + Unaligned load/store test + gen_opts: > + +instr_cnt=500 + +num_of_sub_program=0 + +no_load_store=0 + +no_branch_jump=0 + +directed_instr_0=riscv_load_store_rand_instr_stream,70 + +directed_instr_1=riscv_load_store_hazard_instr_stream,50 + +disable_compressed_instr=0 + iterations: 2 + gen_test: cva6_instr_base_test_c + rtl_test: core_base_test + +- test: riscv_load_store_cmp_test + description: > + Unaligned load/store test + gen_opts: > + +instr_cnt=500 + +num_of_sub_program=0 + +no_load_store=0 + +no_branch_jump=0 + +directed_instr_0=riscv_load_store_rand_instr_stream,20 + +directed_instr_1=riscv_load_store_hazard_instr_stream,50 + +disable_compressed_instr=1 + iterations: 2 + gen_test: cva6_instr_base_test_c + rtl_test: core_base_test + +- test: riscv_load_store_hazard_test + description: > + Arithmetic instruction test, no load/store/branch instructions no compressed + gen_opts: > + +instr_cnt=500 + +num_of_sub_program=0 + +no_fence=1 + +directed_instr_1=riscv_multi_page_load_store_instr_stream,20 + +no_data_page=0 + +no_branch_jump=1 + +boot_mode=m + +no_csr_instr=1 + +disable_compressed_instr=0 + iterations: 2 + gen_test: cva6_instr_base_test_c + rtl_test: core_base_test + +- test: riscv_arithmetic_basic_xif_test + description: > + Arithmetic instruction test, no load/store/branch instructions no compressed + gen_opts: > + +instr_cnt=500 + +num_of_sub_program=0 + +no_fence=1 + +no_data_page=1 + +no_branch_jump=1 + +boot_mode=m + +no_csr_instr=1 + +enable_x_extension=1 + +disable_compressed_instr=1 + +tvec_alignment=8 + iterations: 2 + gen_test: cva6_instr_base_test_c + rtl_test: core_base_test + +- test: riscv_arithmetic_basic_xif_illegal_test + description: > + Arithmetic instruction test, no load/store/branch instructions + gen_opts: > + +instr_cnt=500 + +num_of_sub_program=0 + +no_data_page=1 + +no_branch_jump=1 + +boot_mode=m + +no_csr_instr=1 + +enable_x_extension=1 + +illegal_instr_ratio=100 + +tvec_alignment=8 + iterations: 2 + gen_test: cva6_instr_base_test_c + rtl_test: core_base_test + +- test: riscv_load_store_xif_test + description: > + Unaligned load/store test + gen_opts: > + +instr_cnt=500 + +num_of_sub_program=0 + +no_load_store=0 + +no_branch_jump=1 + +directed_instr_0=riscv_load_store_rand_instr_stream,20 + +directed_instr_1=riscv_load_store_hazard_instr_stream,50 + +tvec_alignment=8 + +enable_x_extension=1 + iterations: 2 + gen_test: cva6_instr_base_test_c + rtl_test: core_base_test + +- test: riscv_rand_jump_xif_test + description: > + Jump among large number of sub-programs, stress testing iTLB operations. + gen_opts: > + +instr_cnt=500 + +num_of_sub_program=0 + +directed_instr_1=riscv_jal_instr,70 + +enable_x_extension=1 + +tvec_alignment=8 + iterations: 2 + gen_test: cva6_instr_base_test_c + rtl_test: core_base_test + +- test: riscv_arithmetic_basic_test_no_comp + description: > + Arithmetic instruction test, no load/store/branch instructions no compressed + gen_opts: > + +instr_cnt=500 + +num_of_sub_program=0 + +directed_instr_0=riscv_int_numeric_corner_stream,4 + +no_fence=1 + +no_data_page=1 + +no_branch_jump=1 + +boot_mode=m + +no_csr_instr=1 + +disable_compressed_instr=1 + iterations: 2 + gen_test: cva6_instr_base_test_c + rtl_test: core_base_test + +- test: riscv_arithmetic_basic_test_comp + description: > + Arithmetic instruction test, no load/store/branch instructions no compressed + gen_opts: > + +instr_cnt=500 + +num_of_sub_program=0 + +directed_instr_0=riscv_int_numeric_corner_stream,4 + +no_fence=1 + +no_data_page=1 + +no_branch_jump=1 + +boot_mode=m + +no_csr_instr=1 + iterations: 2 + gen_test: cva6_instr_base_test_c + rtl_test: core_base_test + +- test: riscv_arithmetic_basic_test_bcomp + description: > + Arithmetic instruction test, no load/store/branch instructions no compressed + gen_opts: > + +instr_cnt=500 + +num_of_sub_program=0 + +directed_instr_0=riscv_int_numeric_corner_stream,4 + +no_fence=1 + +no_data_page=1 + +no_branch_jump=0 + +boot_mode=m + +no_csr_instr=1 + iterations: 2 + gen_test: cva6_instr_base_test_c + rtl_test: core_base_test + +- test: riscv_arithmetic_basic_sub_prog_test + description: > + Arithmetic instruction test, no load/store/branch instructions no compressed + gen_opts: > + +instr_cnt=500 + +num_of_sub_program=20 + +no_fence=1 + +no_data_page=1 + +no_branch_jump=1 + +boot_mode=m + +no_csr_instr=1 + iterations: 2 + gen_test: cva6_instr_base_test_c + rtl_test: core_base_test + +- test: riscv_arithmetic_basic_illegal + description: > + Arithmetic instruction test, no load/store/branch instructions + gen_opts: > + +instr_cnt=500 + +num_of_sub_program=0 + +no_data_page=1 + +no_branch_jump=1 + +boot_mode=m + +no_csr_instr=1 + +illegal_instr_ratio=100 + +tvec_alignment=8 + iterations: 2 + gen_test: cva6_instr_base_test_c + rtl_test: core_base_test + +- test: riscv_unaligned_load_store_test + description: > + Unaligned load/store test + gcc_opts: > + -mno-strict-align + gen_opts: > + +instr_cnt=100 + +num_of_sub_program=0 + +no_branch_jump=1 + +no_data_page=0 + +directed_instr_0=riscv_load_store_rand_instr_stream,20 + +directed_instr_1=riscv_load_store_hazard_instr_stream,20 + +enable_unaligned_load_store=1 + +tvec_alignment=8 + +disable_compressed_instr=1 + +enable_x_extension=1 + iterations: 2 + gen_test: cva6_instr_base_test_c + rtl_test: core_base_test + +- test: riscv_arithmetic_basic_illegal_csr + description: > + Arithmetic instruction test, no load/store/branch instructions + gen_opts: > + +instr_cnt=500 + +num_of_sub_program=5 + +directed_instr_0=riscv_int_numeric_corner_stream,4 + +no_data_page=1 + +no_branch_jump=1 + +boot_mode=m + +no_csr_instr=0 + +enable_access_invalid_csr_level=1 + +disable_compressed_instr=1 + +tvec_alignment=8 + iterations: 2 + gen_test: cva6_instr_base_test_c + rtl_test: core_base_test + +- test: riscv_arithmetic_basic_csr_dummy + description: > + Arithmetic instruction test, no load/store/branch instructions + gen_opts: > + +instr_cnt=500 + +num_of_sub_program=5 + +directed_instr_0=riscv_int_numeric_corner_stream,4 + +no_data_page=1 + +no_branch_jump=1 + +boot_mode=m + +enable_dummy_csr_write=1 + +no_csr_instr=0 + iterations: 2 + gen_test: cva6_instr_base_test_c + rtl_test: core_base_test + +- test: riscv_arithmetic_basic_Randcsr_test + description: > + Arithmetic instruction test, no load/store/branch instructions + gen_opts: > + +instr_cnt=500 + +num_of_sub_program=0 + +directed_instr_0=riscv_int_numeric_corner_stream,10 + +no_fence=0 + +no_data_page=1 + +no_branch_jump=1 + +boot_mode=m + +no_csr_instr=0 + +randomize_csr=1 + +enable_acess_invalid_csr_level=1 + +tvec_alignment=8 + iterations: 2 + gen_test: cva6_instr_base_test_c + rtl_test: core_base_test + +- test: riscv_arithmetic_basic_hint_illegal_csr + description: > + Arithmetic instruction test, no load/store/branch instructions + gen_opts: > + +instr_cnt=500 + +num_of_sub_program=0 + +directed_instr_0=riscv_int_numeric_corner_stream,5 + +no_fence=0 + +no_data_page=1 + +no_branch_jump=1 + +boot_mode=m + +no_csr_instr=0 + +enable_illegal_csr_instruction=1 + +hint_instr_ratio=150 + +tvec_alignment=8 + iterations: 2 + gen_test: cva6_instr_base_test_c + rtl_test: core_base_test + +- test: riscv_arithmetic_basic_illegal_hint_test + description: > + Arithmetic instruction test, no load/store/branch instructions + gen_opts: > + +instr_cnt=500 + +num_of_sub_program=5 + +directed_instr_0=riscv_int_numeric_corner_stream,4 + +no_fence=1 + +no_data_page=1 + +no_branch_jump=1 + +no_load_store=1 + +boot_mode=m + +no_csr_instr=1 + +illegal_instr_ratio=200 + +hint_instr_ratio=500 + +tvec_alignment=8 + iterations: 2 + gen_test: cva6_instr_base_test_c + rtl_test: core_base_test + +- test: riscv_arithmetic_basic_hint_test + description: > + Arithmetic instruction test, no load/store/branch instructions + gen_opts: > + +instr_cnt=500 + +num_of_sub_program=15 + +directed_instr_0=riscv_int_numeric_corner_stream,4 + +no_fence=1 + +no_data_page=1 + +no_branch_jump=1 + +boot_mode=m + +no_csr_instr=1 + +enable_interrupt=1 + +enable_timer_irq=1 + +hint_instr_ratio=500 + iterations: 2 + gen_test: cva6_instr_base_test_c + rtl_test: core_base_test + +- test: riscv_arithmetic_basic_loop_test + description: > + Arithmetic instruction test, no load/store/branch instructions + gen_opts: > + +instr_cnt=500 + +num_of_sub_program=10 + +directed_instr_1=riscv_loop_instr,2 + +no_fence=1 + +no_data_page=1 + +no_branch_jump=1 + +boot_mode=m + +no_csr_instr=1 + iterations: 2 + gen_test: cva6_instr_base_test_c + rtl_test: core_base_test + +- test: riscv_arithmetic_basic_ebreak_dret_test + description: > + Arithmetic instruction test, no load/store/branch instructions + gen_opts: > + +instr_cnt=500 + +num_of_sub_program=0 + +no_data_page=1 + +no_branch_jump=1 + +boot_mode=m + +no_csr_instr=1 + +no_ebreak=0 + +no_dret=0 + +no_fence=0 + +tvec_alignment=8 + iterations: 2 + gen_test: cva6_instr_base_test_c + rtl_test: core_base_test + +- test: riscv_arithmetic_basic_same_reg_test + description: > + Arithmetic instruction test, no load/store/branch instructions no compressed + gen_opts: > + +instr_cnt=1000 + +num_of_sub_program=0 + +no_fence=1 + +no_data_page=1 + +no_branch_jump=1 + +boot_mode=m + +no_csr_instr=1 + +enable_same_reg=1 + +disable_compressed_instr=1 + iterations: 2 + gen_test: cva6_instr_hazard_test_c + rtl_test: core_base_test + +- test: riscv_arithmetic_basic_hazard_rdrs1_test + description: > + Arithmetic instruction test, no load/store/branch instructions no compressed + gen_opts: > + +instr_cnt=1000 + +num_of_sub_program=0 + +no_fence=1 + +no_data_page=1 + +no_branch_jump=1 + +boot_mode=m + +no_csr_instr=1 + +enable_rdrs1_hazard=1 + +disable_compressed_instr=1 + iterations: 2 + gen_test: cva6_instr_hazard_test_c + rtl_test: core_base_test + +- test: riscv_arithmetic_basic_hazard_rdrs2_test + description: > + Arithmetic instruction test, no load/store/branch instructions no compressed + gen_opts: > + +instr_cnt=1000 + +num_of_sub_program=0 + +no_fence=1 + +no_data_page=1 + +no_branch_jump=1 + +boot_mode=m + +no_csr_instr=1 + +enable_rdrs2_hazard=1 + +disable_compressed_instr=1 + iterations: 2 + gen_test: cva6_instr_hazard_test_c + rtl_test: core_base_test diff --git a/verif/sim/cva6_spike_log_to_trace_csv.py b/verif/sim/cva6_spike_log_to_trace_csv.py new file mode 100644 index 0000000000..486c8d9750 --- /dev/null +++ b/verif/sim/cva6_spike_log_to_trace_csv.py @@ -0,0 +1,244 @@ +""" +Copyright 2019 Google LLC + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +Convert spike sim log to standard riscv instruction trace format +""" + +import argparse +import os +import re +import sys +import logging + +sys.path.insert(0, os.path.dirname(os.path.realpath(__file__))) + +from riscv_trace_csv import * +from lib import * + +RD_RE = re.compile(r"(core\s+\d+:\s+)?(?P<pri>\d) 0x(?P<addr>[a-f0-9]+?) " \ + "\((?P<bin>.*?)\)(( c\S* 0x[a-f0-9]+)*) (?P<reg>[xf]\s*\d*?)\s*0x(?P<val>[a-f0-9]+)") + +CORE_RE = re.compile( + r"core\s+\d+:\s+0x(?P<addr>[a-f0-9]+?) \(0x(?P<bin>.*?)\) (?P<instr>.*?)$") +ADDR_RE = re.compile( + r"(?P<rd>[a-z0-9]+?),(?P<imm>[\-0-9]+?)\((?P<rs1>[a-z0-9]+)\)") +ILLE_RE = re.compile(r"trap_illegal_instruction") + +LOGGER = logging.getLogger() + + +def process_instr(trace): + if trace.instr == "jal": + # Spike jal format jal rd, -0xf -> jal rd, -15 + idx = trace.operand.rfind(",") + imm = trace.operand[idx + 1:] + if imm[0] == "-": + imm = "-" + str(int(imm[1:], 16)) + else: + imm = str(int(imm, 16)) + trace.operand = trace.operand[0:idx + 1] + imm + # Properly format operands of all instructions of the form: + # <instr> <reg1> <imm>(<reg2>) + # The operands should be converted into CSV as: + # "<reg1>,<reg2>,<imm>" + m = ADDR_RE.search(trace.operand) + if m: + trace.operand = "{},{},{}".format( + m.group("rd"), m.group("rs1"), m.group("imm")) + + +def read_spike_instr(match, full_trace): + """Unpack a regex match for CORE_RE to a RiscvInstructionTraceEntry + + If full_trace is true, extract operand data from the disassembled + instruction. + + """ + # Extract the disassembled instruction. + disasm = match.group('instr') + + # Spike's disassembler shows a relative jump as something like "j pc + + # 0x123" or "j pc - 0x123". We just want the relative offset. + disasm = disasm.replace('pc + ', '').replace('pc - ', '-') + + instr = RiscvInstructionTraceEntry() + instr.pc = match.group('addr') + instr.instr_str = disasm + instr.binary = match.group('bin') + if full_trace: + opcode = disasm.split(' ')[0] + operand = disasm[len(opcode):].replace(' ', '') + instr.instr, instr.operand = \ + convert_pseudo_instr(opcode, operand, instr.binary) + + process_instr(instr) + + return instr + + +def read_spike_trace(path, full_trace): + """Read a Spike simulation log at <path>, yielding executed instructions. + + This assumes that the log was generated with the -l and --log-commits options + to Spike. + + If full_trace is true, extract operands from the disassembled instructions. + + Since Spike has a strange trampoline that always runs at the start, we skip + instructions up to and including the one at PC 0x1010 (the end of the + trampoline). At the end of a DV program, there's an ECALL instruction, which + we take as a signal to stop checking, so we ditch everything that follows + that instruction. + + This function yields instructions as it parses them as tuples of the form + (entry, illegal). entry is a RiscvInstructionTraceEntry. illegal is a + boolean, which is true if the instruction caused an illegal instruction trap. + + """ + + # This loop is a simple FSM with states TRAMPOLINE, INSTR, EFFECT. The idea + # is that we're in state TRAMPOLINE until we get to the end of Spike's + # trampoline, then we switch between INSTR (where we expect to read an + # instruction) and EFFECT (where we expect to read commit information). + # + # We yield a RiscvInstructionTraceEntry object each time we leave EFFECT + # (going back to INSTR), we loop back from INSTR to itself, or we get to the + # end of the file and have an instruction in hand. + # + # On entry to the loop body, we are in state TRAMPOLINE if in_trampoline is + # true. Otherwise, we are in state EFFECT if instr is not None, otherwise we + # are in state INSTR. + + end_trampoline_re = re.compile(r'core.*: 0x0*1010 ') + + in_trampoline = True + instr = None + + with open(path, 'r') as handle: + for line in handle: + if in_trampoline: + # The TRAMPOLINE state + if end_trampoline_re.match(line): + in_trampoline = False + continue + + if instr is None: + # The INSTR state. We expect to see a line matching CORE_RE. + # We'll discard any other lines. + instr_match = CORE_RE.match(line) + if not instr_match: + continue + + instr = read_spike_instr(instr_match, full_trace) + + # If instr.instr_str is 'ecall', we should stop. + if instr.instr_str == 'ecall': + break + + continue + + # The EFFECT state. If the line matches CORE_RE, we should have been in + # state INSTR, so we yield the instruction we had, read the new + # instruction and continue. As above, if the new instruction is 'ecall', + # we need to stop immediately. + instr_match = CORE_RE.match(line) + if instr_match: + yield instr, False + instr = read_spike_instr(instr_match, full_trace) + if instr.instr_str == 'ecall': + break + continue + + # The line doesn't match CORE_RE, so we are definitely on a follow-on + # line in the log. First, check for illegal instructions + if 'trap_illegal_instruction' in line: + yield (instr, True) + instr = None + continue + + # The instruction seems to have been fine. Do we have commit data (from + # the --log-commits Spike option)? + commit_match = RD_RE.match(line) + if commit_match: + instr.gpr.append(gpr_to_abi(commit_match.group('reg') + .replace(' ', '')) + + ':' + commit_match.group('val')) + instr.mode = commit_match.group('pri') + + # At EOF, we might have an instruction in hand. Yield it if so. + if instr is not None: + yield (instr, False) + + +def process_spike_sim_log(spike_log, csv, full_trace=0): + """Process SPIKE simulation log. + + Extract instruction and affected register information from spike simulation + log and write the results to a CSV file at csv. Returns the number of + instructions written. + + """ + logging.info("Processing spike log : {}".format(spike_log)) + instrs_in = 0 + instrs_out = 0 + + with open(csv, "w") as csv_fd: + trace_csv = RiscvInstructionTraceCsv(csv_fd) + trace_csv.start_new_trace() + + for (entry, illegal) in read_spike_trace(spike_log, full_trace): + instrs_in += 1 + if illegal and full_trace: + logging.debug("Illegal instruction: {}, opcode:{}" + .format(entry.instr_str, entry.binary)) + + # Instructions that cause no architectural update (which includes illegal + # instructions) are ignored if full_trace is false. + # + # We say that an instruction caused an architectural update if either we + # saw a commit line (in which case, entry.gpr will contain a single + # entry) or the instruction was 'wfi' or 'ecall'. + if not (full_trace or entry.gpr or entry.instr_str in ['wfi', + 'ecall']): + continue + + trace_csv.write_trace_entry(entry) + instrs_out += 1 + + logging.info("Processed instruction count : {}".format(instrs_in)) + logging.info("CSV saved to : {}".format(csv)) + return instrs_out + + +def main(): + # Parse input arguments + parser = argparse.ArgumentParser() + parser.add_argument("--log", type=str, help="Input spike simulation log") + parser.add_argument("--csv", type=str, help="Output trace csv_buf file") + parser.add_argument("-f", "--full_trace", dest="full_trace", + action="store_true", + help="Generate the full trace") + parser.add_argument("-v", "--verbose", dest="verbose", action="store_true", + help="Verbose logging") + parser.set_defaults(full_trace=False) + parser.set_defaults(verbose=False) + args = parser.parse_args() + setup_logging(args.verbose) + # Process spike log + process_spike_sim_log(args.log, args.csv, args.full_trace) + + +if __name__ == "__main__": + main() diff --git a/verif/sim/init_run_uvm_fsdb.do b/verif/sim/init_run_uvm_fsdb.do new file mode 100644 index 0000000000..a65868818b --- /dev/null +++ b/verif/sim/init_run_uvm_fsdb.do @@ -0,0 +1,7 @@ +# Copyright 2022 Thales DIS France +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# Original Author: Zbigniew CHAMSKI (zbigniew.chamski@thalesgroup.com) + +fsdbDumpvars 0 "uvmt_cva6_tb" +all +trace_process +run + diff --git a/verif/sim/init_run_uvm_vpd.do b/verif/sim/init_run_uvm_vpd.do new file mode 100644 index 0000000000..6f7f35741d --- /dev/null +++ b/verif/sim/init_run_uvm_vpd.do @@ -0,0 +1,8 @@ +# Copyright 2022 Thales DIS France +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# Original Author: Zbigniew CHAMSKI (zbigniew.chamski@thalesgroup.com) + +dump -file "novas.vpd" -type VPD +dump -add "uvmt_cva6_tb" -depth 0 +run + diff --git a/verif/sim/init_uvm.do b/verif/sim/init_uvm.do new file mode 100644 index 0000000000..bc8f1ba976 --- /dev/null +++ b/verif/sim/init_uvm.do @@ -0,0 +1 @@ +fsdbDumpvars 0 "uvmt_cva6_tb" +all +trace_process diff --git a/verif/sim/link.ld b/verif/sim/link.ld new file mode 100644 index 0000000000..ad50f56e2e --- /dev/null +++ b/verif/sim/link.ld @@ -0,0 +1,35 @@ +/* Copyright 2018 Google LLC +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http:*www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*/ + +OUTPUT_ARCH( "riscv" ) +ENTRY(_start) + +SECTIONS +{ + . = 0x80000000; + .text.init : { *(.text.init) } + . = ALIGN(0x1000); + .tohost : { *(.tohost) } + . = ALIGN(0x1000); + .text : { *(.text) } + . = ALIGN(0x1000); + .page_table : { *(.page_table) } + .user_stack : { *(.user_stack) } + .kernel_data : { *(.kernel_data) } + .kernel_stack : { *(.kernel_stack) } + .data : { *(.data) } + .bss : { *(.bss) } + _end = .; +} diff --git a/verif/sim/verilator_log_to_trace_csv.py b/verif/sim/verilator_log_to_trace_csv.py new file mode 100644 index 0000000000..ab35106373 --- /dev/null +++ b/verif/sim/verilator_log_to_trace_csv.py @@ -0,0 +1,251 @@ +""" +Copyright 2019 Google LLC +Copyright 2020 Thales DIS Design Services SAS + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +Convert verilator sim log to standard riscv instruction trace format +""" + +import argparse +import os +import re +import sys +import logging + +sys.path.insert(0, "dv/scripts") + +from riscv_trace_csv import * +from lib import * + +RD_RE = re.compile(r"(?P<pri>\d) 0x(?P<addr>[a-f0-9]+?) " \ + "\((?P<bin>.*?)\) (?P<reg>[xf]\s*\d*?) 0x(?P<val>[a-f0-9]+)") +CORE_RE = re.compile(r"core.*0x(?P<addr>[a-f0-9]+?) \(0x(?P<bin>.*?)\) (?P<instr>.*?)$") +ILLE_RE = re.compile(r"trap_illegal_instruction") + +LOGGER = logging.getLogger() + + +def process_instr(trace): + if trace.instr == "jal": + # Spike jal format jal rd, -0xf -> jal rd, -15 + idx = trace.operand.rfind(",") + imm = trace.operand[idx+1:] + if imm[0] == "-": + imm = "-" + str(int(imm[1:], 16)) + else: + imm = str(int(imm, 16)) + trace.operand = trace.operand[0:idx+1] + imm + trace.operand = trace.operand.replace("(", ",") + trace.operand = trace.operand.replace(")", "") + + +def read_verilator_instr(match, full_trace): + '''Unpack a regex match for CORE_RE to a RiscvInstructionTraceEntry + + If full_trace is true, extract operand data from the disassembled + instruction. + + ''' + + # Extract the disassembled instruction. + disasm = match.group('instr') + + # Spike's disassembler shows a relative jump as something like "j pc + + # 0x123" or "j pc - 0x123". We just want the relative offset. + disasm = disasm.replace('pc + ', '').replace('pc - ', '-') + + instr = RiscvInstructionTraceEntry() + instr.pc = match.group('addr') + instr.instr_str = disasm + instr.binary = match.group('bin') + + if full_trace: + opcode = disasm.split(' ')[0] + operand = disasm[len(opcode):].replace(' ', '') + instr.instr, instr.operand = \ + convert_pseudo_instr(opcode, operand, instr.binary) + + process_instr(instr) + + return instr + + +def read_verilator_trace(path, full_trace): + '''Read a Spike simulation log at <path>, yielding executed instructions. + + This assumes that the log was generated with the -l and --log-commits options + to Spike. + + If full_trace is true, extract operands from the disassembled instructions. + + Since Spike has a strange trampoline that always runs at the start, we skip + instructions up to and including the one at PC 0x1010 (the end of the + trampoline). At the end of a DV program, there's an ECALL instruction, which + we take as a signal to stop checking, so we ditch everything that follows + that instruction. + + This function yields instructions as it parses them as tuples of the form + (entry, illegal). entry is a RiscvInstructionTraceEntry. illegal is a + boolean, which is true if the instruction caused an illegal instruction trap. + + ''' + + # This loop is a simple FSM with states TRAMPOLINE, INSTR, EFFECT. The idea + # is that we're in state TRAMPOLINE until we get to the end of Spike's + # trampoline, then we switch between INSTR (where we expect to read an + # instruction) and EFFECT (where we expect to read commit information). + # + # We yield a RiscvInstructionTraceEntry object each time we leave EFFECT + # (going back to INSTR), we loop back from INSTR to itself, or we get to the + # end of the file and have an instruction in hand. + # + # On entry to the loop body, we are in state TRAMPOLINE if in_trampoline is + # true. Otherwise, we are in state EFFECT if instr is not None, otherwise we + # are in state INSTR. + + end_trampoline_re = re.compile(r'core.*: 0x0000000080000000 ') + start_debug_it_re = re.compile(r'core.*: 0x0000000000000800 ') + stop_debug_it_re = re.compile(r'core.*: 0x0000000000000890 ') + + in_trampoline = True + in_debug = False + instr = None + + with open(path, 'r') as handle: + for line in handle: + if in_trampoline: + # The TRAMPOLINE state + if end_trampoline_re.match(line): + in_trampoline = False + else : + continue + + if not in_trampoline: + if in_debug: + if stop_debug_it_re.match(line): + in_debug = False + continue + else: + if start_debug_it_re.match(line): + in_debug = True + continue + + if instr is None: + # The INSTR state. We expect to see a line matching CORE_RE. We'll + # discard any other lines. + instr_match = CORE_RE.match(line) + if not instr_match: + continue + + instr = read_verilator_instr(instr_match, full_trace) + + # If instr.instr_str is 'ecall', we should stop. + if instr.instr_str == 'ecall': + break + + continue + + # The EFFECT state. If the line matches CORE_RE, we should have been in + # state INSTR, so we yield the instruction we had, read the new + # instruction and continue. As above, if the new instruction is 'ecall', + # we need to stop immediately. + instr_match = CORE_RE.match(line) + if instr_match: + yield (instr, False) + instr = read_verilator_instr(instr_match, full_trace) + if instr.instr_str == 'ecall': + break + continue + + # The line doesn't match CORE_RE, so we are definitely on a follow-on + # line in the log. First, check for illegal instructions + if 'trap_illegal_instruction' in line: + yield (instr, True) + instr = None + continue + + # The instruction seems to have been fine. Do we have commit data (from + # the --log-commits Spike option)? + commit_match = RD_RE.match(line) + if commit_match: + instr.gpr.append(gpr_to_abi(commit_match.group('reg') + .replace(' ', '')) + + ':' + commit_match.group('val')) + instr.mode = commit_match.group('pri') + + # At EOF, we might have an instruction in hand. Yield it if so. + if instr is not None: + yield (instr, False) + + +def process_verilator_sim_log(verilator_log, csv, full_trace = 0): + """Process VERILATOR simulation log. + + Extract instruction and affected register information from verilator simulation + log and write the results to a CSV file at csv. Returns the number of + instructions written. + + """ + logging.info("Processing verilator log : %s" % verilator_log) + + instrs_in = 0 + instrs_out = 0 + + with open(csv, "w") as csv_fd: + trace_csv = RiscvInstructionTraceCsv(csv_fd) + trace_csv.start_new_trace() + + for (entry, illegal) in read_verilator_trace(verilator_log, full_trace): + instrs_in += 1 + + if illegal and full_trace: + logging.debug("Illegal instruction: {}, opcode:{}" + .format(entry.instr_str, entry.binary)) + + # Instructions that cause no architectural update (which includes illegal + # instructions) are ignored if full_trace is false. + # + # We say that an instruction caused an architectural update if either we + # saw a commit line (in which case, entry.gpr will contain a single + # entry) or the instruction was 'wfi' or 'ecall'. + if not (full_trace or entry.gpr or entry.instr_str in ['wfi', 'ecall']): + continue + + trace_csv.write_trace_entry(entry) + instrs_out += 1 + + logging.info("Processed instruction count : %d" % instrs_in) + logging.info("CSV saved to : %s" % csv) + return instrs_out + + +def main(): + # Parse input arguments + parser = argparse.ArgumentParser() + parser.add_argument("--log", type=str, help="Input verilator simulation log") + parser.add_argument("--csv", type=str, help="Output trace csv_buf file") + parser.add_argument("-f", "--full_trace", dest="full_trace", action="store_true", + help="Generate the full trace") + parser.add_argument("-v", "--verbose", dest="verbose", action="store_true", + help="Verbose logging") + parser.set_defaults(full_trace=False) + parser.set_defaults(verbose=False) + args = parser.parse_args() + setup_logging(args.verbose) + # Process verilator log + process_verilator_sim_log(args.log, args.csv, args.full_trace) + + +if __name__ == "__main__": + main() diff --git a/verif/tb/core/Flist.cva6_tb b/verif/tb/core/Flist.cva6_tb new file mode 100644 index 0000000000..67b49b0634 --- /dev/null +++ b/verif/tb/core/Flist.cva6_tb @@ -0,0 +1,39 @@ +////////////////////////////////////////////////////////////////////////////// +// +// Copyright 2021 OpenHW Group +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// +/////////////////////////////////////////////////////////////////////////////// +// +// Manifest for the CVA6 TB. +// - This is a CORE-ONLY testbench. +// - Relevent simulation scripts/Makefiles must set the shell ENV variable +// CVA6_TB_DIR as required. +// +/////////////////////////////////////////////////////////////////////////////// + +// These need to be moved +${CVA6_REPO_DIR}/corev_apu/riscv-dbg/src/dm_pkg.sv +${CVA6_REPO_DIR}/corev_apu/axi_mem_if/src/axi2mem.sv +${CVA6_REPO_DIR}/corev_apu/tb/ariane_soc_pkg.sv +${CVA6_REPO_DIR}/corev_apu/tb/axi_intf.sv +${CVA6_REPO_DIR}/corev_apu/tb/ariane_axi_pkg.sv + +// RVFI tracer +${CVA6_REPO_DIR}/corev_apu/tb/rvfi_tracer.sv + +// AXI master connect +${CVA6_TB_DIR}/tb_components/axi_master_connect.sv diff --git a/verif/tb/core/Makefile b/verif/tb/core/Makefile new file mode 100644 index 0000000000..7a3519b270 --- /dev/null +++ b/verif/tb/core/Makefile @@ -0,0 +1,158 @@ +############################################################################### +# +# Copyright 2021 OpenHW Group +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://solderpad.org/licenses/ +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# +############################################################################### +# +# Makefile for the CVA6 "core_only" testbench. +# +############################################################################### + +mkfile_path := $(abspath $(lastword $(MAKEFILE_LIST))) +root-dir := $(dir $(mkfile_path)) + +ifndef CVA6_REPO_DIR +$(warning must set CVA6_REPO_DIR to point at the root of CVA6 sources and CVA6_TB_DIR to point here -- doing it for you...) +export CVA6_REPO_DIR = $(abspath $(root-dir)../../../) +export CVA6_TB_DIR = $(root-dir) +endif + +.DEFAULT_GOAL := help + +# target takes one of the following cva6 hardware configuration: +# cv64a6_imafdc_sv39, cv32a6_imac_sv0 +target ?= cv64a6_imafdc_sv39 +FLIST_CORE := $(CVA6_REPO_DIR)/core/Flist.$(target) + +############################################################################### +# Cadence Xcelium specific commands, variables +############################################################################### +XRUN ?= xrun +XRUN_COMP_FLAGS ?= -sv -64bit -disable_sem2009 -access +rwc -timescale 1ns/1ps +XRUN_ACC_FLAGS ?= +XRUN_DISABLED_WARNINGS ?= -nowarn UEXPSC +XRUN_UVMHOME_ARG ?= -uvm -uvmhome CDNS-1.2-ML +XRUN_COMPL_LOG ?= xrun_compl.log +XRUN_RUN_LOG ?= xrun_run.log +XRUN_RESULTS_DIR ?= xrun_results + +XRUN_COMP = $(XRUN_COMP_FLAGS) \ + $(XRUN_ACC_FLAGS) \ + $(XRUN_DISABLED_WARNINGS) \ + $(XRUN_UVMHOME_ARG) \ + -l $(XRUN_COMPL_LOG) \ + -f $(FLIST_CORE) \ + -f $(CVA6_TB_DIR)/Flist.cva6_tb \ + -top cva6_core_only_tb \ + -elaborate + +xrun_comp: + @echo "[XRUN] Building Model" + mkdir -p $(XRUN_RESULTS_DIR) + cd $(XRUN_RESULTS_DIR) && \ + $(XRUN) $(XRUN_COMP) + +xrun_run: xrun_comp + @echo "[XRUN] Running Model" + cd $(XRUN_RESULTS_DIR) && \ + $(XRUN) -R -xmlibdirname ./xcelium.d -l $(XRUN_RUN_LOG) + +xrun_clean_all: + @echo "[XRUN] Cleanup (entire xrun_results dir)" + rm -rf $(XRUN_RESULTS_DIR) + +############################################################################### +# dsim-specific commands, variables +############################################################################### +DSIM ?= dsim +DSIM_HOME ?= /tools/Metrics/dsim +DSIM_CMP_FLAGS ?= $(TIMESCALE) -top worklib.$(top_level) -pli_lib +DSIM_WORK_DIR ?= dsim_work +DSIM_RESULTS_DIR ?= dsim_results +DSIM_UVMHOME_ARG ?= +incdir+$(UVM_HOME)/src $(UVM_HOME)/src/uvm_pkg.sv +DSIM_COMPL_LOG ?= dsim_compl.log +DSIM_RUN_LOG ?= dsim_run.log +DSIM_IMAGE ?= dsim.out +DSIM_ACC_FLAGS ?= +acc +DSIM_DMP_FILE ?= dsim.fst +DSIM_DMP_FLAGS ?= -waves $(DSIM_DMP_FILE) + +DSIM_COMP = $(DSIM_COMP_FLAGS) \ + $(DSIM_ACC_FLAGS) \ + $(DSIM_DISABLED_WARNINGS) \ + $(DSIM_UVMHOME_ARG) \ + -l $(DSIM_COMPL_LOG) \ + -genimage $(DSIM_IMAGE) \ + -f $(FLIST_CORE) \ + -f $(CVA6_TB_DIR)/Flist.cva6_tb + +dsim_comp: + @echo "[DSIM] Building Model" + mkdir -p $(DSIM_RESULTS_DIR) + cd $(DSIM_RESULTS_DIR) && \ + $(DSIM) $(DSIM_COMP) + +dsim_run: dsim_comp + @echo "[DSIM] Running Model" + cd $(DSIM_RESULTS_DIR) && \ + $(DSIM) \ + $(DSIM_RUN_FLAGS) \ + $(DSIM_DMP_FLAGS) \ + -l $(DSIM_RUN_LOG) \ + -image $(DSIM_IMAGE) \ + -sv_lib $(UVM_HOME)/src/dpi/libuvm_dpi.so + +dsim_clean: + @echo "[DSIM] Cleanup (select contents of dsim_results dir)" + cd $(DSIM_RESULTS_DIR) && \ + rm -rf $(DSIM_RESULTS_DIR) && \ + rm -rf $(DSIM_WORK_DIR) && \ + rm -f $(DSIM_IMAGE) && \ + rm -f $(DSIM_COMPL_LOG) && \ + rm -f $(DSIM_RUN_LOG) && \ + rm -f dsim.env && \ + rm -f metrics.db && \ + rm -f metrics_history.db && \ + rm -f trace_hart*.log && \ + rm -f $(DSIM_DMP_FILE) && \ + rm -f $(DSIM_DMP_FILE).hier + +dsim_clean_all: + @echo "[DSIM] Cleanup (entire dsim_results dir)" + rm -rf $(DSIM_RESULTS_DIR) + +############################################################################### +# Common targets and rules +############################################################################### + +clean_all: xrun_clean_all dsim_clean_all veri_clean_all + + +help: + @echo "Shell environment:" + @echo " CVA6_REPO_DIR : $(CVA6_REPO_DIR)" + @echo " CVA6_TB_DIR : $(CVA6_TB_DIR)" + @echo "DSIM targets:" + @echo " make dsim_comp : Compiles with DSIM" + @echo " make dsim_run : Compiles and runs with DSIM" + @echo "XRUN targets:" + @echo " make xrun_comp : Compiles with XRUN" + @echo " make xrun_run : Compiles and runs with XRUN" + @echo "Clean-up targets:" + @echo " make clean_all : Deletes ALL generated files" + @echo "Support for other simulators on the ToDo list..." + diff --git a/verif/tb/core/README.md b/verif/tb/core/README.md new file mode 100644 index 0000000000..eb3c4f63b1 --- /dev/null +++ b/verif/tb/core/README.md @@ -0,0 +1,11 @@ +## Experimental Stand-alone testbench for the CVA6 +This do-nothing TB supports experiments with the CVA6 to develop a standalone testbenech for the CVA6. +It uses a "core-only" manifest file `Flist.cva6`. + +### Current status: +Compiles and runs without errors for a few thousand clock cycles under either Verilator, Metrics DSIM or Cadence Xcelium (xrun). + +### Give it a try: +``` +$ make help +``` diff --git a/verif/tb/core/bootrom/.gitignore b/verif/tb/core/bootrom/.gitignore new file mode 100644 index 0000000000..b553ec26ea --- /dev/null +++ b/verif/tb/core/bootrom/.gitignore @@ -0,0 +1,3 @@ +*.elf +*.img +*.dtb diff --git a/verif/tb/core/bootrom/Makefile b/verif/tb/core/bootrom/Makefile new file mode 100644 index 0000000000..86708317c8 --- /dev/null +++ b/verif/tb/core/bootrom/Makefile @@ -0,0 +1,53 @@ +############################################################################### +# $@ is the file being generated. +# $< is first prerequiste. +# $^ is all prerequistes. +# $* is file_name (w/o extension) of target + +DTB ?= cva6.dtb +LCS ?= linker.ld + +# Tools yer gonna need +RISCV_EXE_PREFIX ?= riscv64-unknown-elf +RISCV_GCC ?= $(RISCV_EXE_PREFIX)-gcc +RISCV_OBJCOPY ?= $(RISCV_EXE_PREFIX)-objcopy +RISCV_READELF ?= $(RISCV_EXE_PREFIX)-readelf +RISCV_OBJDUMP ?= $(RISCV_EXE_PREFIX)-objdump +PYTHON ?= python3 +DTC ?= dtc +DD ?= dd + +.PRECIOUS : %.elf + +%.dtb: %.dts + $(DTC) -I dts $< -O dtb -o $@ + +%.elf: %.S $(LCS) $(DTB) + $(RISCV_GCC) -T$(LCS) -march=rv32i -mabi=ilp32 $< -nostdlib -static -Wl,--no-gc-sections -o $@ + +%.hex: %.elf + $(RISCV_OBJCOPY) -O verilog $< $@ + +%.readelf: %.elf + $(RISCV_READELF) -a $< > $@ + +%.objdump: %.elf + $(RISCV_OBJDUMP) -D -S $< > $@ + +clean: + rm -f $(bootrom_img) $(DTB) *.elf *.hex *.readelf *.objdump + +############################################################################### +# Deprecated variables and targets + +#bootrom_img = bootrom.img bootrom.sv + +#%.sv: %.img +# $(PYTHON) ./gen_rom.py $< + +#%.img: %.bin +# $(DD) if=$< of=$@ bs=128 + +#%.bin: %.elf +# $(RISCV_OBJCOPY) -O binary $< $@ + diff --git a/verif/tb/core/bootrom/bootrom.S b/verif/tb/core/bootrom/bootrom.S new file mode 100644 index 0000000000..e8089b552e --- /dev/null +++ b/verif/tb/core/bootrom/bootrom.S @@ -0,0 +1,27 @@ +.section .text.start, "ax", @progbits +.globl _start +_start: +# bootrom.sv need to be functional in 64 and 32 bits, +# li s0, DRAM_BASE creates instructions not compatible with both +# versions. That's why we have replaced it by li and slli instructions +# to generates code compatible with both versions. + li s0, 1 + slli s0, s0, 31 + csrr a0, mhartid + la a1, _dtb + jr s0 + +.section .text.hang, "ax", @progbits +.globl _hang +_hang: + csrr a0, mhartid + la a1, _dtb +1: + wfi + j 1b + +.section .rodata.dtb, "a", @progbits +.globl _dtb +.align 5, 0 +_dtb: +.incbin "cva6.dtb" diff --git a/verif/tb/core/bootrom/bootrom.h b/verif/tb/core/bootrom/bootrom.h new file mode 100644 index 0000000000..e1419e65b1 --- /dev/null +++ b/verif/tb/core/bootrom/bootrom.h @@ -0,0 +1,408 @@ +// Auto-generated code + +const int reset_vec_size = 402; + +uint32_t reset_vec[reset_vec_size] = { + 0x00100413, + 0x01f41413, + 0xf1402573, + 0x00000597, + 0x07458593, + 0x00040067, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0xf1402573, + 0x00000597, + 0x03c58593, + 0x10500073, + 0xffdff06f, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0xedfe0dd0, + 0xc2050000, + 0x38000000, + 0xbc040000, + 0x28000000, + 0x11000000, + 0x10000000, + 0x00000000, + 0x06010000, + 0x84040000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x01000000, + 0x00000000, + 0x03000000, + 0x04000000, + 0x00000000, + 0x02000000, + 0x03000000, + 0x04000000, + 0x0f000000, + 0x02000000, + 0x03000000, + 0x14000000, + 0x1b000000, + 0x2c687465, + 0x61697261, + 0x622d656e, + 0x2d657261, + 0x00766564, + 0x03000000, + 0x10000000, + 0x26000000, + 0x2c687465, + 0x61697261, + 0x622d656e, + 0x00657261, + 0x01000000, + 0x73757063, + 0x00000000, + 0x03000000, + 0x04000000, + 0x00000000, + 0x01000000, + 0x03000000, + 0x04000000, + 0x0f000000, + 0x00000000, + 0x03000000, + 0x04000000, + 0x2c000000, + 0x00800000, + 0x01000000, + 0x40757063, + 0x00000030, + 0x03000000, + 0x04000000, + 0x3f000000, + 0x80f0fa02, + 0x03000000, + 0x04000000, + 0x4f000000, + 0x00757063, + 0x03000000, + 0x04000000, + 0x5b000000, + 0x00000000, + 0x03000000, + 0x05000000, + 0x5f000000, + 0x79616b6f, + 0x00000000, + 0x03000000, + 0x12000000, + 0x1b000000, + 0x2c687465, + 0x69726120, + 0x00656e61, + 0x63736972, + 0x00000076, + 0x03000000, + 0x0b000000, + 0x66000000, + 0x34367672, + 0x66616d69, + 0x00006364, + 0x03000000, + 0x0b000000, + 0x70000000, + 0x63736972, + 0x76732c76, + 0x00003933, + 0x03000000, + 0x00000000, + 0x79000000, + 0x01000000, + 0x65746e69, + 0x70757272, + 0x6f632d74, + 0x6f72746e, + 0x72656c6c, + 0x00000000, + 0x03000000, + 0x04000000, + 0x83000000, + 0x01000000, + 0x03000000, + 0x00000000, + 0x94000000, + 0x03000000, + 0x0f000000, + 0x1b000000, + 0x63736972, + 0x70632c76, + 0x6e692d75, + 0x00006374, + 0x03000000, + 0x04000000, + 0xa9000000, + 0x01000000, + 0x02000000, + 0x02000000, + 0x02000000, + 0x01000000, + 0x6f6d656d, + 0x38407972, + 0x30303030, + 0x00303030, + 0x03000000, + 0x07000000, + 0x4f000000, + 0x6f6d656d, + 0x00007972, + 0x03000000, + 0x10000000, + 0x5b000000, + 0x00000000, + 0x00000080, + 0x00000000, + 0x00000010, + 0x02000000, + 0x01000000, + 0x00636f73, + 0x03000000, + 0x04000000, + 0x00000000, + 0x02000000, + 0x03000000, + 0x04000000, + 0x0f000000, + 0x02000000, + 0x03000000, + 0x1f000000, + 0x1b000000, + 0x2c687465, + 0x61697261, + 0x622d656e, + 0x2d657261, + 0x00636f73, + 0x706d6973, + 0x622d656c, + 0x00007375, + 0x03000000, + 0x00000000, + 0xb1000000, + 0x01000000, + 0x6e696c63, + 0x30324074, + 0x30303030, + 0x00000030, + 0x03000000, + 0x0d000000, + 0x1b000000, + 0x63736972, + 0x6c632c76, + 0x30746e69, + 0x00000000, + 0x03000000, + 0x10000000, + 0xb8000000, + 0x01000000, + 0x03000000, + 0x01000000, + 0x07000000, + 0x03000000, + 0x10000000, + 0x5b000000, + 0x00000000, + 0x00000002, + 0x00000000, + 0x00000c00, + 0x03000000, + 0x08000000, + 0xcc000000, + 0x746e6f63, + 0x006c6f72, + 0x02000000, + 0x01000000, + 0x75626564, + 0x6f632d67, + 0x6f72746e, + 0x72656c6c, + 0x00003040, + 0x03000000, + 0x10000000, + 0x1b000000, + 0x63736972, + 0x65642c76, + 0x2d677562, + 0x00333130, + 0x03000000, + 0x08000000, + 0xb8000000, + 0x01000000, + 0xffff0000, + 0x03000000, + 0x10000000, + 0x5b000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00100000, + 0x03000000, + 0x08000000, + 0xcc000000, + 0x746e6f63, + 0x006c6f72, + 0x02000000, + 0x01000000, + 0x74726175, + 0x30303140, + 0x30303030, + 0x00000030, + 0x03000000, + 0x08000000, + 0x1b000000, + 0x3631736e, + 0x00303537, + 0x03000000, + 0x10000000, + 0x5b000000, + 0x00000000, + 0x00000010, + 0x00000000, + 0x00100000, + 0x03000000, + 0x04000000, + 0x3f000000, + 0x80f0fa02, + 0x03000000, + 0x04000000, + 0xd6000000, + 0x00c20100, + 0x03000000, + 0x04000000, + 0xe4000000, + 0x01000000, + 0x03000000, + 0x04000000, + 0xef000000, + 0x02000000, + 0x03000000, + 0x04000000, + 0xf9000000, + 0x04000000, + 0x02000000, + 0x01000000, + 0x656d6974, + 0x38314072, + 0x30303030, + 0x00003030, + 0x03000000, + 0x0f000000, + 0x1b000000, + 0x706c7570, + 0x6270612c, + 0x6d69745f, + 0x00007265, + 0x03000000, + 0x10000000, + 0xe4000000, + 0x04000000, + 0x05000000, + 0x06000000, + 0x07000000, + 0x03000000, + 0x10000000, + 0x5b000000, + 0x00000000, + 0x00000018, + 0x00000000, + 0x00100000, + 0x03000000, + 0x08000000, + 0xcc000000, + 0x746e6f63, + 0x006c6f72, + 0x02000000, + 0x02000000, + 0x02000000, + 0x09000000, + 0x64646123, + 0x73736572, + 0x6c65632d, + 0x2300736c, + 0x657a6973, + 0x6c65632d, + 0x6300736c, + 0x61706d6f, + 0x6c626974, + 0x6f6d0065, + 0x006c6564, + 0x656d6974, + 0x65736162, + 0x6572662d, + 0x6e657571, + 0x63007963, + 0x6b636f6c, + 0x6572662d, + 0x6e657571, + 0x64007963, + 0x63697665, + 0x79745f65, + 0x72006570, + 0x73006765, + 0x75746174, + 0x69720073, + 0x2c766373, + 0x00617369, + 0x2d756d6d, + 0x65707974, + 0x626c7400, + 0x6c70732d, + 0x23007469, + 0x65746e69, + 0x70757272, + 0x65632d74, + 0x00736c6c, + 0x65746e69, + 0x70757272, + 0x6f632d74, + 0x6f72746e, + 0x72656c6c, + 0x61687000, + 0x656c646e, + 0x6e617200, + 0x00736567, + 0x65746e69, + 0x70757272, + 0x652d7374, + 0x6e657478, + 0x00646564, + 0x2d676572, + 0x656d616e, + 0x75630073, + 0x6e657272, + 0x70732d74, + 0x00646565, + 0x65746e69, + 0x70757272, + 0x72007374, + 0x732d6765, + 0x74666968, + 0x67657200, + 0x2d6f692d, + 0x74646977, + 0x00000068, + 0x00000000 +}; diff --git a/verif/tb/core/bootrom/cva6.dts b/verif/tb/core/bootrom/cva6.dts new file mode 100644 index 0000000000..e54da14e61 --- /dev/null +++ b/verif/tb/core/bootrom/cva6.dts @@ -0,0 +1,68 @@ +/dts-v1/; + +/ { + #address-cells = <2>; + #size-cells = <2>; + compatible = "eth,cva6-bare-dev"; + model = "eth,cva6-bare"; + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <32768>; // 32.768 kHz + CPU0: cpu@0 { + clock-frequency = <50000000>; // 50 MHz + device_type = "cpu"; + reg = <0>; + status = "okay"; + compatible = "eth, cva6", "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + tlb-split; + // HLIC - hart local interrupt controller + CPU0_intc: interrupt-controller { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; + }; + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x10000000>; + }; + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "eth,cva6-bare-soc", "simple-bus"; + ranges; + clint@2000000 { + compatible = "riscv,clint0"; + interrupts-extended = <&CPU0_intc 3 &CPU0_intc 7>; + reg = <0x0 0x2000000 0x0 0xc0000>; + reg-names = "control"; + }; + debug-controller@0 { + compatible = "riscv,debug-013"; + interrupts-extended = <&CPU0_intc 65535>; + reg = <0x0 0x0 0x0 0x1000>; + reg-names = "control"; + }; + uart@10000000 { + compatible = "ns16750"; + reg = <0x0 0x10000000 0x0 0x1000>; + clock-frequency = <50000000>; + current-speed = <115200>; + // interrupt-parent = <&PLIC0>; + interrupts = <1>; + reg-shift = <2>; // regs are spaced on 32 bit boundary + reg-io-width = <4>; // only 32-bit access are supported + }; + timer@18000000 { + compatible = "pulp,apb_timer"; + interrupts = <0x00000004 0x00000005 0x00000006 0x00000007>; + reg = <0x00000000 0x18000000 0x00000000 0x00001000>; + // interrupt-parent = <&PLIC0>; + reg-names = "control"; + }; + }; +}; diff --git a/verif/tb/core/bootrom/encoding.h b/verif/tb/core/bootrom/encoding.h new file mode 100644 index 0000000000..f5a40afdad --- /dev/null +++ b/verif/tb/core/bootrom/encoding.h @@ -0,0 +1,1475 @@ +// See LICENSE for license details. + +#ifndef RISCV_CSR_ENCODING_H +#define RISCV_CSR_ENCODING_H + +#define MSTATUS_UIE 0x00000001 +#define MSTATUS_SIE 0x00000002 +#define MSTATUS_HIE 0x00000004 +#define MSTATUS_MIE 0x00000008 +#define MSTATUS_UPIE 0x00000010 +#define MSTATUS_SPIE 0x00000020 +#define MSTATUS_HPIE 0x00000040 +#define MSTATUS_MPIE 0x00000080 +#define MSTATUS_SPP 0x00000100 +#define MSTATUS_HPP 0x00000600 +#define MSTATUS_MPP 0x00001800 +#define MSTATUS_FS 0x00006000 +#define MSTATUS_XS 0x00018000 +#define MSTATUS_MPRV 0x00020000 +#define MSTATUS_SUM 0x00040000 +#define MSTATUS_MXR 0x00080000 +#define MSTATUS_TVM 0x00100000 +#define MSTATUS_TW 0x00200000 +#define MSTATUS_TSR 0x00400000 +#define MSTATUS32_SD 0x80000000 +#define MSTATUS_UXL 0x0000000300000000 +#define MSTATUS_SXL 0x0000000C00000000 +#define MSTATUS64_SD 0x8000000000000000 + +#define SSTATUS_UIE 0x00000001 +#define SSTATUS_SIE 0x00000002 +#define SSTATUS_UPIE 0x00000010 +#define SSTATUS_SPIE 0x00000020 +#define SSTATUS_SPP 0x00000100 +#define SSTATUS_FS 0x00006000 +#define SSTATUS_XS 0x00018000 +#define SSTATUS_SUM 0x00040000 +#define SSTATUS_MXR 0x00080000 +#define SSTATUS32_SD 0x80000000 +#define SSTATUS_UXL 0x0000000300000000 +#define SSTATUS64_SD 0x8000000000000000 + +#define DCSR_XDEBUGVER (3U<<30) +#define DCSR_NDRESET (1<<29) +#define DCSR_FULLRESET (1<<28) +#define DCSR_EBREAKM (1<<15) +#define DCSR_EBREAKH (1<<14) +#define DCSR_EBREAKS (1<<13) +#define DCSR_EBREAKU (1<<12) +#define DCSR_STOPCYCLE (1<<10) +#define DCSR_STOPTIME (1<<9) +#define DCSR_CAUSE (7<<6) +#define DCSR_DEBUGINT (1<<5) +#define DCSR_HALT (1<<3) +#define DCSR_STEP (1<<2) +#define DCSR_PRV (3<<0) + +#define DCSR_CAUSE_NONE 0 +#define DCSR_CAUSE_SWBP 1 +#define DCSR_CAUSE_HWBP 2 +#define DCSR_CAUSE_DEBUGINT 3 +#define DCSR_CAUSE_STEP 4 +#define DCSR_CAUSE_HALT 5 + +#define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4)) +#define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5)) +#define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11)) + +#define MCONTROL_SELECT (1<<19) +#define MCONTROL_TIMING (1<<18) +#define MCONTROL_ACTION (0x3f<<12) +#define MCONTROL_CHAIN (1<<11) +#define MCONTROL_MATCH (0xf<<7) +#define MCONTROL_M (1<<6) +#define MCONTROL_H (1<<5) +#define MCONTROL_S (1<<4) +#define MCONTROL_U (1<<3) +#define MCONTROL_EXECUTE (1<<2) +#define MCONTROL_STORE (1<<1) +#define MCONTROL_LOAD (1<<0) + +#define MCONTROL_TYPE_NONE 0 +#define MCONTROL_TYPE_MATCH 2 + +#define MCONTROL_ACTION_DEBUG_EXCEPTION 0 +#define MCONTROL_ACTION_DEBUG_MODE 1 +#define MCONTROL_ACTION_TRACE_START 2 +#define MCONTROL_ACTION_TRACE_STOP 3 +#define MCONTROL_ACTION_TRACE_EMIT 4 + +#define MCONTROL_MATCH_EQUAL 0 +#define MCONTROL_MATCH_NAPOT 1 +#define MCONTROL_MATCH_GE 2 +#define MCONTROL_MATCH_LT 3 +#define MCONTROL_MATCH_MASK_LOW 4 +#define MCONTROL_MATCH_MASK_HIGH 5 + +#define MIP_SSIP (1 << IRQ_S_SOFT) +#define MIP_HSIP (1 << IRQ_H_SOFT) +#define MIP_MSIP (1 << IRQ_M_SOFT) +#define MIP_STIP (1 << IRQ_S_TIMER) +#define MIP_HTIP (1 << IRQ_H_TIMER) +#define MIP_MTIP (1 << IRQ_M_TIMER) +#define MIP_SEIP (1 << IRQ_S_EXT) +#define MIP_HEIP (1 << IRQ_H_EXT) +#define MIP_MEIP (1 << IRQ_M_EXT) + +#define SIP_SSIP MIP_SSIP +#define SIP_STIP MIP_STIP + +#define PRV_U 0 +#define PRV_S 1 +#define PRV_H 2 +#define PRV_M 3 + +#define SATP32_MODE 0x80000000 +#define SATP32_ASID 0x7FC00000 +#define SATP32_PPN 0x003FFFFF +#define SATP64_MODE 0xF000000000000000 +#define SATP64_ASID 0x0FFFF00000000000 +#define SATP64_PPN 0x00000FFFFFFFFFFF + +#define SATP_MODE_OFF 0 +#define SATP_MODE_SV32 1 +#define SATP_MODE_SV39 8 +#define SATP_MODE_SV48 9 +#define SATP_MODE_SV57 10 +#define SATP_MODE_SV64 11 + +#define PMP_R 0x01 +#define PMP_W 0x02 +#define PMP_X 0x04 +#define PMP_A 0x18 +#define PMP_L 0x80 +#define PMP_SHIFT 2 + +#define PMP_TOR 0x08 +#define PMP_NA4 0x10 +#define PMP_NAPOT 0x18 + +#define IRQ_S_SOFT 1 +#define IRQ_H_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_S_TIMER 5 +#define IRQ_H_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_S_EXT 9 +#define IRQ_H_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_COP 12 +#define IRQ_HOST 13 + +#define DEFAULT_RSTVEC 0x00001000 +#define CLINT_BASE 0x02000000 +#define CLINT_SIZE 0x000c0000 +#define EXT_IO_BASE 0x40000000 +#define DRAM_BASE 0x80000000 + +// page table entry (PTE) fields +#define PTE_V 0x001 // Valid +#define PTE_R 0x002 // Read +#define PTE_W 0x004 // Write +#define PTE_X 0x008 // Execute +#define PTE_U 0x010 // User +#define PTE_G 0x020 // Global +#define PTE_A 0x040 // Accessed +#define PTE_D 0x080 // Dirty +#define PTE_SOFT 0x300 // Reserved for Software + +#define PTE_PPN_SHIFT 10 + +#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V) + +#ifdef __riscv + +#if __riscv_xlen == 64 +# define MSTATUS_SD MSTATUS64_SD +# define SSTATUS_SD SSTATUS64_SD +# define RISCV_PGLEVEL_BITS 9 +# define SATP_MODE SATP64_MODE +#else +# define MSTATUS_SD MSTATUS32_SD +# define SSTATUS_SD SSTATUS32_SD +# define RISCV_PGLEVEL_BITS 10 +# define SATP_MODE SATP32_MODE +#endif +#define RISCV_PGSHIFT 12 +#define RISCV_PGSIZE (1 << RISCV_PGSHIFT) + +#ifndef __ASSEMBLER__ + +#ifdef __GNUC__ + +#define read_csr(reg) ({ unsigned long __tmp; \ + asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ + __tmp; }) + +#define write_csr(reg, val) ({ \ + asm volatile ("csrw " #reg ", %0" :: "rK"(val)); }) + +#define swap_csr(reg, val) ({ unsigned long __tmp; \ + asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "rK"(val)); \ + __tmp; }) + +#define set_csr(reg, bit) ({ unsigned long __tmp; \ + asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ + __tmp; }) + +#define clear_csr(reg, bit) ({ unsigned long __tmp; \ + asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ + __tmp; }) + +#define rdtime() read_csr(time) +#define rdcycle() read_csr(cycle) +#define rdinstret() read_csr(instret) + +#endif + +#endif + +#endif + +#endif +/* Automatically generated by parse-opcodes. */ +#ifndef RISCV_ENCODING_H +#define RISCV_ENCODING_H +#define MATCH_BEQ 0x63 +#define MASK_BEQ 0x707f +#define MATCH_BNE 0x1063 +#define MASK_BNE 0x707f +#define MATCH_BLT 0x4063 +#define MASK_BLT 0x707f +#define MATCH_BGE 0x5063 +#define MASK_BGE 0x707f +#define MATCH_BLTU 0x6063 +#define MASK_BLTU 0x707f +#define MATCH_BGEU 0x7063 +#define MASK_BGEU 0x707f +#define MATCH_JALR 0x67 +#define MASK_JALR 0x707f +#define MATCH_JAL 0x6f +#define MASK_JAL 0x7f +#define MATCH_LUI 0x37 +#define MASK_LUI 0x7f +#define MATCH_AUIPC 0x17 +#define MASK_AUIPC 0x7f +#define MATCH_ADDI 0x13 +#define MASK_ADDI 0x707f +#define MATCH_SLLI 0x1013 +#define MASK_SLLI 0xfc00707f +#define MATCH_SLTI 0x2013 +#define MASK_SLTI 0x707f +#define MATCH_SLTIU 0x3013 +#define MASK_SLTIU 0x707f +#define MATCH_XORI 0x4013 +#define MASK_XORI 0x707f +#define MATCH_SRLI 0x5013 +#define MASK_SRLI 0xfc00707f +#define MATCH_SRAI 0x40005013 +#define MASK_SRAI 0xfc00707f +#define MATCH_ORI 0x6013 +#define MASK_ORI 0x707f +#define MATCH_ANDI 0x7013 +#define MASK_ANDI 0x707f +#define MATCH_ADD 0x33 +#define MASK_ADD 0xfe00707f +#define MATCH_SUB 0x40000033 +#define MASK_SUB 0xfe00707f +#define MATCH_SLL 0x1033 +#define MASK_SLL 0xfe00707f +#define MATCH_SLT 0x2033 +#define MASK_SLT 0xfe00707f +#define MATCH_SLTU 0x3033 +#define MASK_SLTU 0xfe00707f +#define MATCH_XOR 0x4033 +#define MASK_XOR 0xfe00707f +#define MATCH_SRL 0x5033 +#define MASK_SRL 0xfe00707f +#define MATCH_SRA 0x40005033 +#define MASK_SRA 0xfe00707f +#define MATCH_OR 0x6033 +#define MASK_OR 0xfe00707f +#define MATCH_AND 0x7033 +#define MASK_AND 0xfe00707f +#define MATCH_ADDIW 0x1b +#define MASK_ADDIW 0x707f +#define MATCH_SLLIW 0x101b +#define MASK_SLLIW 0xfe00707f +#define MATCH_SRLIW 0x501b +#define MASK_SRLIW 0xfe00707f +#define MATCH_SRAIW 0x4000501b +#define MASK_SRAIW 0xfe00707f +#define MATCH_ADDW 0x3b +#define MASK_ADDW 0xfe00707f +#define MATCH_SUBW 0x4000003b +#define MASK_SUBW 0xfe00707f +#define MATCH_SLLW 0x103b +#define MASK_SLLW 0xfe00707f +#define MATCH_SRLW 0x503b +#define MASK_SRLW 0xfe00707f +#define MATCH_SRAW 0x4000503b +#define MASK_SRAW 0xfe00707f +#define MATCH_LB 0x3 +#define MASK_LB 0x707f +#define MATCH_LH 0x1003 +#define MASK_LH 0x707f +#define MATCH_LW 0x2003 +#define MASK_LW 0x707f +#define MATCH_LD 0x3003 +#define MASK_LD 0x707f +#define MATCH_LBU 0x4003 +#define MASK_LBU 0x707f +#define MATCH_LHU 0x5003 +#define MASK_LHU 0x707f +#define MATCH_LWU 0x6003 +#define MASK_LWU 0x707f +#define MATCH_SB 0x23 +#define MASK_SB 0x707f +#define MATCH_SH 0x1023 +#define MASK_SH 0x707f +#define MATCH_SW 0x2023 +#define MASK_SW 0x707f +#define MATCH_SD 0x3023 +#define MASK_SD 0x707f +#define MATCH_FENCE 0xf +#define MASK_FENCE 0x707f +#define MATCH_FENCE_I 0x100f +#define MASK_FENCE_I 0x707f +#define MATCH_MUL 0x2000033 +#define MASK_MUL 0xfe00707f +#define MATCH_MULH 0x2001033 +#define MASK_MULH 0xfe00707f +#define MATCH_MULHSU 0x2002033 +#define MASK_MULHSU 0xfe00707f +#define MATCH_MULHU 0x2003033 +#define MASK_MULHU 0xfe00707f +#define MATCH_DIV 0x2004033 +#define MASK_DIV 0xfe00707f +#define MATCH_DIVU 0x2005033 +#define MASK_DIVU 0xfe00707f +#define MATCH_REM 0x2006033 +#define MASK_REM 0xfe00707f +#define MATCH_REMU 0x2007033 +#define MASK_REMU 0xfe00707f +#define MATCH_MULW 0x200003b +#define MASK_MULW 0xfe00707f +#define MATCH_DIVW 0x200403b +#define MASK_DIVW 0xfe00707f +#define MATCH_DIVUW 0x200503b +#define MASK_DIVUW 0xfe00707f +#define MATCH_REMW 0x200603b +#define MASK_REMW 0xfe00707f +#define MATCH_REMUW 0x200703b +#define MASK_REMUW 0xfe00707f +#define MATCH_AMOADD_W 0x202f +#define MASK_AMOADD_W 0xf800707f +#define MATCH_AMOXOR_W 0x2000202f +#define MASK_AMOXOR_W 0xf800707f +#define MATCH_AMOOR_W 0x4000202f +#define MASK_AMOOR_W 0xf800707f +#define MATCH_AMOAND_W 0x6000202f +#define MASK_AMOAND_W 0xf800707f +#define MATCH_AMOMIN_W 0x8000202f +#define MASK_AMOMIN_W 0xf800707f +#define MATCH_AMOMAX_W 0xa000202f +#define MASK_AMOMAX_W 0xf800707f +#define MATCH_AMOMINU_W 0xc000202f +#define MASK_AMOMINU_W 0xf800707f +#define MATCH_AMOMAXU_W 0xe000202f +#define MASK_AMOMAXU_W 0xf800707f +#define MATCH_AMOSWAP_W 0x800202f +#define MASK_AMOSWAP_W 0xf800707f +#define MATCH_LR_W 0x1000202f +#define MASK_LR_W 0xf9f0707f +#define MATCH_SC_W 0x1800202f +#define MASK_SC_W 0xf800707f +#define MATCH_AMOADD_D 0x302f +#define MASK_AMOADD_D 0xf800707f +#define MATCH_AMOXOR_D 0x2000302f +#define MASK_AMOXOR_D 0xf800707f +#define MATCH_AMOOR_D 0x4000302f +#define MASK_AMOOR_D 0xf800707f +#define MATCH_AMOAND_D 0x6000302f +#define MASK_AMOAND_D 0xf800707f +#define MATCH_AMOMIN_D 0x8000302f +#define MASK_AMOMIN_D 0xf800707f +#define MATCH_AMOMAX_D 0xa000302f +#define MASK_AMOMAX_D 0xf800707f +#define MATCH_AMOMINU_D 0xc000302f +#define MASK_AMOMINU_D 0xf800707f +#define MATCH_AMOMAXU_D 0xe000302f +#define MASK_AMOMAXU_D 0xf800707f +#define MATCH_AMOSWAP_D 0x800302f +#define MASK_AMOSWAP_D 0xf800707f +#define MATCH_LR_D 0x1000302f +#define MASK_LR_D 0xf9f0707f +#define MATCH_SC_D 0x1800302f +#define MASK_SC_D 0xf800707f +#define MATCH_ECALL 0x73 +#define MASK_ECALL 0xffffffff +#define MATCH_EBREAK 0x100073 +#define MASK_EBREAK 0xffffffff +#define MATCH_URET 0x200073 +#define MASK_URET 0xffffffff +#define MATCH_SRET 0x10200073 +#define MASK_SRET 0xffffffff +#define MATCH_MRET 0x30200073 +#define MASK_MRET 0xffffffff +#define MATCH_DRET 0x7b200073 +#define MASK_DRET 0xffffffff +#define MATCH_SFENCE_VMA 0x12000073 +#define MASK_SFENCE_VMA 0xfe007fff +#define MATCH_WFI 0x10500073 +#define MASK_WFI 0xffffffff +#define MATCH_CSRRW 0x1073 +#define MASK_CSRRW 0x707f +#define MATCH_CSRRS 0x2073 +#define MASK_CSRRS 0x707f +#define MATCH_CSRRC 0x3073 +#define MASK_CSRRC 0x707f +#define MATCH_CSRRWI 0x5073 +#define MASK_CSRRWI 0x707f +#define MATCH_CSRRSI 0x6073 +#define MASK_CSRRSI 0x707f +#define MATCH_CSRRCI 0x7073 +#define MASK_CSRRCI 0x707f +#define MATCH_FADD_S 0x53 +#define MASK_FADD_S 0xfe00007f +#define MATCH_FSUB_S 0x8000053 +#define MASK_FSUB_S 0xfe00007f +#define MATCH_FMUL_S 0x10000053 +#define MASK_FMUL_S 0xfe00007f +#define MATCH_FDIV_S 0x18000053 +#define MASK_FDIV_S 0xfe00007f +#define MATCH_FSGNJ_S 0x20000053 +#define MASK_FSGNJ_S 0xfe00707f +#define MATCH_FSGNJN_S 0x20001053 +#define MASK_FSGNJN_S 0xfe00707f +#define MATCH_FSGNJX_S 0x20002053 +#define MASK_FSGNJX_S 0xfe00707f +#define MATCH_FMIN_S 0x28000053 +#define MASK_FMIN_S 0xfe00707f +#define MATCH_FMAX_S 0x28001053 +#define MASK_FMAX_S 0xfe00707f +#define MATCH_FSQRT_S 0x58000053 +#define MASK_FSQRT_S 0xfff0007f +#define MATCH_FADD_D 0x2000053 +#define MASK_FADD_D 0xfe00007f +#define MATCH_FSUB_D 0xa000053 +#define MASK_FSUB_D 0xfe00007f +#define MATCH_FMUL_D 0x12000053 +#define MASK_FMUL_D 0xfe00007f +#define MATCH_FDIV_D 0x1a000053 +#define MASK_FDIV_D 0xfe00007f +#define MATCH_FSGNJ_D 0x22000053 +#define MASK_FSGNJ_D 0xfe00707f +#define MATCH_FSGNJN_D 0x22001053 +#define MASK_FSGNJN_D 0xfe00707f +#define MATCH_FSGNJX_D 0x22002053 +#define MASK_FSGNJX_D 0xfe00707f +#define MATCH_FMIN_D 0x2a000053 +#define MASK_FMIN_D 0xfe00707f +#define MATCH_FMAX_D 0x2a001053 +#define MASK_FMAX_D 0xfe00707f +#define MATCH_FCVT_S_D 0x40100053 +#define MASK_FCVT_S_D 0xfff0007f +#define MATCH_FCVT_D_S 0x42000053 +#define MASK_FCVT_D_S 0xfff0007f +#define MATCH_FSQRT_D 0x5a000053 +#define MASK_FSQRT_D 0xfff0007f +#define MATCH_FADD_Q 0x6000053 +#define MASK_FADD_Q 0xfe00007f +#define MATCH_FSUB_Q 0xe000053 +#define MASK_FSUB_Q 0xfe00007f +#define MATCH_FMUL_Q 0x16000053 +#define MASK_FMUL_Q 0xfe00007f +#define MATCH_FDIV_Q 0x1e000053 +#define MASK_FDIV_Q 0xfe00007f +#define MATCH_FSGNJ_Q 0x26000053 +#define MASK_FSGNJ_Q 0xfe00707f +#define MATCH_FSGNJN_Q 0x26001053 +#define MASK_FSGNJN_Q 0xfe00707f +#define MATCH_FSGNJX_Q 0x26002053 +#define MASK_FSGNJX_Q 0xfe00707f +#define MATCH_FMIN_Q 0x2e000053 +#define MASK_FMIN_Q 0xfe00707f +#define MATCH_FMAX_Q 0x2e001053 +#define MASK_FMAX_Q 0xfe00707f +#define MATCH_FCVT_S_Q 0x40300053 +#define MASK_FCVT_S_Q 0xfff0007f +#define MATCH_FCVT_Q_S 0x46000053 +#define MASK_FCVT_Q_S 0xfff0007f +#define MATCH_FCVT_D_Q 0x42300053 +#define MASK_FCVT_D_Q 0xfff0007f +#define MATCH_FCVT_Q_D 0x46100053 +#define MASK_FCVT_Q_D 0xfff0007f +#define MATCH_FSQRT_Q 0x5e000053 +#define MASK_FSQRT_Q 0xfff0007f +#define MATCH_FLE_S 0xa0000053 +#define MASK_FLE_S 0xfe00707f +#define MATCH_FLT_S 0xa0001053 +#define MASK_FLT_S 0xfe00707f +#define MATCH_FEQ_S 0xa0002053 +#define MASK_FEQ_S 0xfe00707f +#define MATCH_FLE_D 0xa2000053 +#define MASK_FLE_D 0xfe00707f +#define MATCH_FLT_D 0xa2001053 +#define MASK_FLT_D 0xfe00707f +#define MATCH_FEQ_D 0xa2002053 +#define MASK_FEQ_D 0xfe00707f +#define MATCH_FLE_Q 0xa6000053 +#define MASK_FLE_Q 0xfe00707f +#define MATCH_FLT_Q 0xa6001053 +#define MASK_FLT_Q 0xfe00707f +#define MATCH_FEQ_Q 0xa6002053 +#define MASK_FEQ_Q 0xfe00707f +#define MATCH_FCVT_W_S 0xc0000053 +#define MASK_FCVT_W_S 0xfff0007f +#define MATCH_FCVT_WU_S 0xc0100053 +#define MASK_FCVT_WU_S 0xfff0007f +#define MATCH_FCVT_L_S 0xc0200053 +#define MASK_FCVT_L_S 0xfff0007f +#define MATCH_FCVT_LU_S 0xc0300053 +#define MASK_FCVT_LU_S 0xfff0007f +#define MATCH_FMV_X_W 0xe0000053 +#define MASK_FMV_X_W 0xfff0707f +#define MATCH_FCLASS_S 0xe0001053 +#define MASK_FCLASS_S 0xfff0707f +#define MATCH_FCVT_W_D 0xc2000053 +#define MASK_FCVT_W_D 0xfff0007f +#define MATCH_FCVT_WU_D 0xc2100053 +#define MASK_FCVT_WU_D 0xfff0007f +#define MATCH_FCVT_L_D 0xc2200053 +#define MASK_FCVT_L_D 0xfff0007f +#define MATCH_FCVT_LU_D 0xc2300053 +#define MASK_FCVT_LU_D 0xfff0007f +#define MATCH_FMV_X_D 0xe2000053 +#define MASK_FMV_X_D 0xfff0707f +#define MATCH_FCLASS_D 0xe2001053 +#define MASK_FCLASS_D 0xfff0707f +#define MATCH_FCVT_W_Q 0xc6000053 +#define MASK_FCVT_W_Q 0xfff0007f +#define MATCH_FCVT_WU_Q 0xc6100053 +#define MASK_FCVT_WU_Q 0xfff0007f +#define MATCH_FCVT_L_Q 0xc6200053 +#define MASK_FCVT_L_Q 0xfff0007f +#define MATCH_FCVT_LU_Q 0xc6300053 +#define MASK_FCVT_LU_Q 0xfff0007f +#define MATCH_FMV_X_Q 0xe6000053 +#define MASK_FMV_X_Q 0xfff0707f +#define MATCH_FCLASS_Q 0xe6001053 +#define MASK_FCLASS_Q 0xfff0707f +#define MATCH_FCVT_S_W 0xd0000053 +#define MASK_FCVT_S_W 0xfff0007f +#define MATCH_FCVT_S_WU 0xd0100053 +#define MASK_FCVT_S_WU 0xfff0007f +#define MATCH_FCVT_S_L 0xd0200053 +#define MASK_FCVT_S_L 0xfff0007f +#define MATCH_FCVT_S_LU 0xd0300053 +#define MASK_FCVT_S_LU 0xfff0007f +#define MATCH_FMV_W_X 0xf0000053 +#define MASK_FMV_W_X 0xfff0707f +#define MATCH_FCVT_D_W 0xd2000053 +#define MASK_FCVT_D_W 0xfff0007f +#define MATCH_FCVT_D_WU 0xd2100053 +#define MASK_FCVT_D_WU 0xfff0007f +#define MATCH_FCVT_D_L 0xd2200053 +#define MASK_FCVT_D_L 0xfff0007f +#define MATCH_FCVT_D_LU 0xd2300053 +#define MASK_FCVT_D_LU 0xfff0007f +#define MATCH_FMV_D_X 0xf2000053 +#define MASK_FMV_D_X 0xfff0707f +#define MATCH_FCVT_Q_W 0xd6000053 +#define MASK_FCVT_Q_W 0xfff0007f +#define MATCH_FCVT_Q_WU 0xd6100053 +#define MASK_FCVT_Q_WU 0xfff0007f +#define MATCH_FCVT_Q_L 0xd6200053 +#define MASK_FCVT_Q_L 0xfff0007f +#define MATCH_FCVT_Q_LU 0xd6300053 +#define MASK_FCVT_Q_LU 0xfff0007f +#define MATCH_FMV_Q_X 0xf6000053 +#define MASK_FMV_Q_X 0xfff0707f +#define MATCH_FLW 0x2007 +#define MASK_FLW 0x707f +#define MATCH_FLD 0x3007 +#define MASK_FLD 0x707f +#define MATCH_FLQ 0x4007 +#define MASK_FLQ 0x707f +#define MATCH_FSW 0x2027 +#define MASK_FSW 0x707f +#define MATCH_FSD 0x3027 +#define MASK_FSD 0x707f +#define MATCH_FSQ 0x4027 +#define MASK_FSQ 0x707f +#define MATCH_FMADD_S 0x43 +#define MASK_FMADD_S 0x600007f +#define MATCH_FMSUB_S 0x47 +#define MASK_FMSUB_S 0x600007f +#define MATCH_FNMSUB_S 0x4b +#define MASK_FNMSUB_S 0x600007f +#define MATCH_FNMADD_S 0x4f +#define MASK_FNMADD_S 0x600007f +#define MATCH_FMADD_D 0x2000043 +#define MASK_FMADD_D 0x600007f +#define MATCH_FMSUB_D 0x2000047 +#define MASK_FMSUB_D 0x600007f +#define MATCH_FNMSUB_D 0x200004b +#define MASK_FNMSUB_D 0x600007f +#define MATCH_FNMADD_D 0x200004f +#define MASK_FNMADD_D 0x600007f +#define MATCH_FMADD_Q 0x6000043 +#define MASK_FMADD_Q 0x600007f +#define MATCH_FMSUB_Q 0x6000047 +#define MASK_FMSUB_Q 0x600007f +#define MATCH_FNMSUB_Q 0x600004b +#define MASK_FNMSUB_Q 0x600007f +#define MATCH_FNMADD_Q 0x600004f +#define MASK_FNMADD_Q 0x600007f +#define MATCH_C_NOP 0x1 +#define MASK_C_NOP 0xffff +#define MATCH_C_ADDI16SP 0x6101 +#define MASK_C_ADDI16SP 0xef83 +#define MATCH_C_JR 0x8002 +#define MASK_C_JR 0xf07f +#define MATCH_C_JALR 0x9002 +#define MASK_C_JALR 0xf07f +#define MATCH_C_EBREAK 0x9002 +#define MASK_C_EBREAK 0xffff +#define MATCH_C_LD 0x6000 +#define MASK_C_LD 0xe003 +#define MATCH_C_SD 0xe000 +#define MASK_C_SD 0xe003 +#define MATCH_C_ADDIW 0x2001 +#define MASK_C_ADDIW 0xe003 +#define MATCH_C_LDSP 0x6002 +#define MASK_C_LDSP 0xe003 +#define MATCH_C_SDSP 0xe002 +#define MASK_C_SDSP 0xe003 +#define MATCH_C_ADDI4SPN 0x0 +#define MASK_C_ADDI4SPN 0xe003 +#define MATCH_C_FLD 0x2000 +#define MASK_C_FLD 0xe003 +#define MATCH_C_LW 0x4000 +#define MASK_C_LW 0xe003 +#define MATCH_C_FLW 0x6000 +#define MASK_C_FLW 0xe003 +#define MATCH_C_FSD 0xa000 +#define MASK_C_FSD 0xe003 +#define MATCH_C_SW 0xc000 +#define MASK_C_SW 0xe003 +#define MATCH_C_FSW 0xe000 +#define MASK_C_FSW 0xe003 +#define MATCH_C_ADDI 0x1 +#define MASK_C_ADDI 0xe003 +#define MATCH_C_JAL 0x2001 +#define MASK_C_JAL 0xe003 +#define MATCH_C_LI 0x4001 +#define MASK_C_LI 0xe003 +#define MATCH_C_LUI 0x6001 +#define MASK_C_LUI 0xe003 +#define MATCH_C_SRLI 0x8001 +#define MASK_C_SRLI 0xec03 +#define MATCH_C_SRAI 0x8401 +#define MASK_C_SRAI 0xec03 +#define MATCH_C_ANDI 0x8801 +#define MASK_C_ANDI 0xec03 +#define MATCH_C_SUB 0x8c01 +#define MASK_C_SUB 0xfc63 +#define MATCH_C_XOR 0x8c21 +#define MASK_C_XOR 0xfc63 +#define MATCH_C_OR 0x8c41 +#define MASK_C_OR 0xfc63 +#define MATCH_C_AND 0x8c61 +#define MASK_C_AND 0xfc63 +#define MATCH_C_SUBW 0x9c01 +#define MASK_C_SUBW 0xfc63 +#define MATCH_C_ADDW 0x9c21 +#define MASK_C_ADDW 0xfc63 +#define MATCH_C_J 0xa001 +#define MASK_C_J 0xe003 +#define MATCH_C_BEQZ 0xc001 +#define MASK_C_BEQZ 0xe003 +#define MATCH_C_BNEZ 0xe001 +#define MASK_C_BNEZ 0xe003 +#define MATCH_C_SLLI 0x2 +#define MASK_C_SLLI 0xe003 +#define MATCH_C_FLDSP 0x2002 +#define MASK_C_FLDSP 0xe003 +#define MATCH_C_LWSP 0x4002 +#define MASK_C_LWSP 0xe003 +#define MATCH_C_FLWSP 0x6002 +#define MASK_C_FLWSP 0xe003 +#define MATCH_C_MV 0x8002 +#define MASK_C_MV 0xf003 +#define MATCH_C_ADD 0x9002 +#define MASK_C_ADD 0xf003 +#define MATCH_C_FSDSP 0xa002 +#define MASK_C_FSDSP 0xe003 +#define MATCH_C_SWSP 0xc002 +#define MASK_C_SWSP 0xe003 +#define MATCH_C_FSWSP 0xe002 +#define MASK_C_FSWSP 0xe003 +#define MATCH_CUSTOM0 0xb +#define MASK_CUSTOM0 0x707f +#define MATCH_CUSTOM0_RS1 0x200b +#define MASK_CUSTOM0_RS1 0x707f +#define MATCH_CUSTOM0_RS1_RS2 0x300b +#define MASK_CUSTOM0_RS1_RS2 0x707f +#define MATCH_CUSTOM0_RD 0x400b +#define MASK_CUSTOM0_RD 0x707f +#define MATCH_CUSTOM0_RD_RS1 0x600b +#define MASK_CUSTOM0_RD_RS1 0x707f +#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b +#define MASK_CUSTOM0_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM1 0x2b +#define MASK_CUSTOM1 0x707f +#define MATCH_CUSTOM1_RS1 0x202b +#define MASK_CUSTOM1_RS1 0x707f +#define MATCH_CUSTOM1_RS1_RS2 0x302b +#define MASK_CUSTOM1_RS1_RS2 0x707f +#define MATCH_CUSTOM1_RD 0x402b +#define MASK_CUSTOM1_RD 0x707f +#define MATCH_CUSTOM1_RD_RS1 0x602b +#define MASK_CUSTOM1_RD_RS1 0x707f +#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b +#define MASK_CUSTOM1_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM2 0x5b +#define MASK_CUSTOM2 0x707f +#define MATCH_CUSTOM2_RS1 0x205b +#define MASK_CUSTOM2_RS1 0x707f +#define MATCH_CUSTOM2_RS1_RS2 0x305b +#define MASK_CUSTOM2_RS1_RS2 0x707f +#define MATCH_CUSTOM2_RD 0x405b +#define MASK_CUSTOM2_RD 0x707f +#define MATCH_CUSTOM2_RD_RS1 0x605b +#define MASK_CUSTOM2_RD_RS1 0x707f +#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b +#define MASK_CUSTOM2_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM3 0x7b +#define MASK_CUSTOM3 0x707f +#define MATCH_CUSTOM3_RS1 0x207b +#define MASK_CUSTOM3_RS1 0x707f +#define MATCH_CUSTOM3_RS1_RS2 0x307b +#define MASK_CUSTOM3_RS1_RS2 0x707f +#define MATCH_CUSTOM3_RD 0x407b +#define MASK_CUSTOM3_RD 0x707f +#define MATCH_CUSTOM3_RD_RS1 0x607b +#define MASK_CUSTOM3_RD_RS1 0x707f +#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b +#define MASK_CUSTOM3_RD_RS1_RS2 0x707f +#define CSR_FFLAGS 0x1 +#define CSR_FRM 0x2 +#define CSR_FCSR 0x3 +#define CSR_CYCLE 0xc00 +#define CSR_TIME 0xc01 +#define CSR_INSTRET 0xc02 +#define CSR_HPMCOUNTER3 0xc03 +#define CSR_HPMCOUNTER4 0xc04 +#define CSR_HPMCOUNTER5 0xc05 +#define CSR_HPMCOUNTER6 0xc06 +#define CSR_HPMCOUNTER7 0xc07 +#define CSR_HPMCOUNTER8 0xc08 +#define CSR_HPMCOUNTER9 0xc09 +#define CSR_HPMCOUNTER10 0xc0a +#define CSR_HPMCOUNTER11 0xc0b +#define CSR_HPMCOUNTER12 0xc0c +#define CSR_HPMCOUNTER13 0xc0d +#define CSR_HPMCOUNTER14 0xc0e +#define CSR_HPMCOUNTER15 0xc0f +#define CSR_HPMCOUNTER16 0xc10 +#define CSR_HPMCOUNTER17 0xc11 +#define CSR_HPMCOUNTER18 0xc12 +#define CSR_HPMCOUNTER19 0xc13 +#define CSR_HPMCOUNTER20 0xc14 +#define CSR_HPMCOUNTER21 0xc15 +#define CSR_HPMCOUNTER22 0xc16 +#define CSR_HPMCOUNTER23 0xc17 +#define CSR_HPMCOUNTER24 0xc18 +#define CSR_HPMCOUNTER25 0xc19 +#define CSR_HPMCOUNTER26 0xc1a +#define CSR_HPMCOUNTER27 0xc1b +#define CSR_HPMCOUNTER28 0xc1c +#define CSR_HPMCOUNTER29 0xc1d +#define CSR_HPMCOUNTER30 0xc1e +#define CSR_HPMCOUNTER31 0xc1f +#define CSR_SSTATUS 0x100 +#define CSR_SIE 0x104 +#define CSR_STVEC 0x105 +#define CSR_SCOUNTEREN 0x106 +#define CSR_SSCRATCH 0x140 +#define CSR_SEPC 0x141 +#define CSR_SCAUSE 0x142 +#define CSR_STVAL 0x143 +#define CSR_SIP 0x144 +#define CSR_SATP 0x180 +#define CSR_MSTATUS 0x300 +#define CSR_MISA 0x301 +#define CSR_MEDELEG 0x302 +#define CSR_MIDELEG 0x303 +#define CSR_MIE 0x304 +#define CSR_MTVEC 0x305 +#define CSR_MCOUNTEREN 0x306 +#define CSR_MSCRATCH 0x340 +#define CSR_MEPC 0x341 +#define CSR_MCAUSE 0x342 +#define CSR_MTVAL 0x343 +#define CSR_MIP 0x344 +#define CSR_PMPCFG0 0x3a0 +#define CSR_PMPCFG1 0x3a1 +#define CSR_PMPCFG2 0x3a2 +#define CSR_PMPCFG3 0x3a3 +#define CSR_PMPADDR0 0x3b0 +#define CSR_PMPADDR1 0x3b1 +#define CSR_PMPADDR2 0x3b2 +#define CSR_PMPADDR3 0x3b3 +#define CSR_PMPADDR4 0x3b4 +#define CSR_PMPADDR5 0x3b5 +#define CSR_PMPADDR6 0x3b6 +#define CSR_PMPADDR7 0x3b7 +#define CSR_PMPADDR8 0x3b8 +#define CSR_PMPADDR9 0x3b9 +#define CSR_PMPADDR10 0x3ba +#define CSR_PMPADDR11 0x3bb +#define CSR_PMPADDR12 0x3bc +#define CSR_PMPADDR13 0x3bd +#define CSR_PMPADDR14 0x3be +#define CSR_PMPADDR15 0x3bf +#define CSR_TSELECT 0x7a0 +#define CSR_TDATA1 0x7a1 +#define CSR_TDATA2 0x7a2 +#define CSR_TDATA3 0x7a3 +#define CSR_DCSR 0x7b0 +#define CSR_DPC 0x7b1 +#define CSR_DSCRATCH 0x7b2 +#define CSR_DSCRATCH0 CSR_DSCRATCH +#define CSR_DSCRATCH1 0x7b3 +#define CSR_MCYCLE 0xb00 +#define CSR_MINSTRET 0xb02 +#define CSR_MHPMCOUNTER3 0xb03 +#define CSR_MHPMCOUNTER4 0xb04 +#define CSR_MHPMCOUNTER5 0xb05 +#define CSR_MHPMCOUNTER6 0xb06 +#define CSR_MHPMCOUNTER7 0xb07 +#define CSR_MHPMCOUNTER8 0xb08 +#define CSR_MHPMCOUNTER9 0xb09 +#define CSR_MHPMCOUNTER10 0xb0a +#define CSR_MHPMCOUNTER11 0xb0b +#define CSR_MHPMCOUNTER12 0xb0c +#define CSR_MHPMCOUNTER13 0xb0d +#define CSR_MHPMCOUNTER14 0xb0e +#define CSR_MHPMCOUNTER15 0xb0f +#define CSR_MHPMCOUNTER16 0xb10 +#define CSR_MHPMCOUNTER17 0xb11 +#define CSR_MHPMCOUNTER18 0xb12 +#define CSR_MHPMCOUNTER19 0xb13 +#define CSR_MHPMCOUNTER20 0xb14 +#define CSR_MHPMCOUNTER21 0xb15 +#define CSR_MHPMCOUNTER22 0xb16 +#define CSR_MHPMCOUNTER23 0xb17 +#define CSR_MHPMCOUNTER24 0xb18 +#define CSR_MHPMCOUNTER25 0xb19 +#define CSR_MHPMCOUNTER26 0xb1a +#define CSR_MHPMCOUNTER27 0xb1b +#define CSR_MHPMCOUNTER28 0xb1c +#define CSR_MHPMCOUNTER29 0xb1d +#define CSR_MHPMCOUNTER30 0xb1e +#define CSR_MHPMCOUNTER31 0xb1f +#define CSR_MHPMEVENT3 0x323 +#define CSR_MHPMEVENT4 0x324 +#define CSR_MHPMEVENT5 0x325 +#define CSR_MHPMEVENT6 0x326 +#define CSR_MHPMEVENT7 0x327 +#define CSR_MHPMEVENT8 0x328 +#define CSR_MHPMEVENT9 0x329 +#define CSR_MHPMEVENT10 0x32a +#define CSR_MHPMEVENT11 0x32b +#define CSR_MHPMEVENT12 0x32c +#define CSR_MHPMEVENT13 0x32d +#define CSR_MHPMEVENT14 0x32e +#define CSR_MHPMEVENT15 0x32f +#define CSR_MHPMEVENT16 0x330 +#define CSR_MHPMEVENT17 0x331 +#define CSR_MHPMEVENT18 0x332 +#define CSR_MHPMEVENT19 0x333 +#define CSR_MHPMEVENT20 0x334 +#define CSR_MHPMEVENT21 0x335 +#define CSR_MHPMEVENT22 0x336 +#define CSR_MHPMEVENT23 0x337 +#define CSR_MHPMEVENT24 0x338 +#define CSR_MHPMEVENT25 0x339 +#define CSR_MHPMEVENT26 0x33a +#define CSR_MHPMEVENT27 0x33b +#define CSR_MHPMEVENT28 0x33c +#define CSR_MHPMEVENT29 0x33d +#define CSR_MHPMEVENT30 0x33e +#define CSR_MHPMEVENT31 0x33f +#define CSR_MVENDORID 0xf11 +#define CSR_MARCHID 0xf12 +#define CSR_MIMPID 0xf13 +#define CSR_MHARTID 0xf14 +#define CSR_CYCLEH 0xc80 +#define CSR_TIMEH 0xc81 +#define CSR_INSTRETH 0xc82 +#define CSR_HPMCOUNTER3H 0xc83 +#define CSR_HPMCOUNTER4H 0xc84 +#define CSR_HPMCOUNTER5H 0xc85 +#define CSR_HPMCOUNTER6H 0xc86 +#define CSR_HPMCOUNTER7H 0xc87 +#define CSR_HPMCOUNTER8H 0xc88 +#define CSR_HPMCOUNTER9H 0xc89 +#define CSR_HPMCOUNTER10H 0xc8a +#define CSR_HPMCOUNTER11H 0xc8b +#define CSR_HPMCOUNTER12H 0xc8c +#define CSR_HPMCOUNTER13H 0xc8d +#define CSR_HPMCOUNTER14H 0xc8e +#define CSR_HPMCOUNTER15H 0xc8f +#define CSR_HPMCOUNTER16H 0xc90 +#define CSR_HPMCOUNTER17H 0xc91 +#define CSR_HPMCOUNTER18H 0xc92 +#define CSR_HPMCOUNTER19H 0xc93 +#define CSR_HPMCOUNTER20H 0xc94 +#define CSR_HPMCOUNTER21H 0xc95 +#define CSR_HPMCOUNTER22H 0xc96 +#define CSR_HPMCOUNTER23H 0xc97 +#define CSR_HPMCOUNTER24H 0xc98 +#define CSR_HPMCOUNTER25H 0xc99 +#define CSR_HPMCOUNTER26H 0xc9a +#define CSR_HPMCOUNTER27H 0xc9b +#define CSR_HPMCOUNTER28H 0xc9c +#define CSR_HPMCOUNTER29H 0xc9d +#define CSR_HPMCOUNTER30H 0xc9e +#define CSR_HPMCOUNTER31H 0xc9f +#define CSR_MCYCLEH 0xb80 +#define CSR_MINSTRETH 0xb82 +#define CSR_MHPMCOUNTER3H 0xb83 +#define CSR_MHPMCOUNTER4H 0xb84 +#define CSR_MHPMCOUNTER5H 0xb85 +#define CSR_MHPMCOUNTER6H 0xb86 +#define CSR_MHPMCOUNTER7H 0xb87 +#define CSR_MHPMCOUNTER8H 0xb88 +#define CSR_MHPMCOUNTER9H 0xb89 +#define CSR_MHPMCOUNTER10H 0xb8a +#define CSR_MHPMCOUNTER11H 0xb8b +#define CSR_MHPMCOUNTER12H 0xb8c +#define CSR_MHPMCOUNTER13H 0xb8d +#define CSR_MHPMCOUNTER14H 0xb8e +#define CSR_MHPMCOUNTER15H 0xb8f +#define CSR_MHPMCOUNTER16H 0xb90 +#define CSR_MHPMCOUNTER17H 0xb91 +#define CSR_MHPMCOUNTER18H 0xb92 +#define CSR_MHPMCOUNTER19H 0xb93 +#define CSR_MHPMCOUNTER20H 0xb94 +#define CSR_MHPMCOUNTER21H 0xb95 +#define CSR_MHPMCOUNTER22H 0xb96 +#define CSR_MHPMCOUNTER23H 0xb97 +#define CSR_MHPMCOUNTER24H 0xb98 +#define CSR_MHPMCOUNTER25H 0xb99 +#define CSR_MHPMCOUNTER26H 0xb9a +#define CSR_MHPMCOUNTER27H 0xb9b +#define CSR_MHPMCOUNTER28H 0xb9c +#define CSR_MHPMCOUNTER29H 0xb9d +#define CSR_MHPMCOUNTER30H 0xb9e +#define CSR_MHPMCOUNTER31H 0xb9f +#define CAUSE_MISALIGNED_FETCH 0x0 +#define CAUSE_FETCH_ACCESS 0x1 +#define CAUSE_ILLEGAL_INSTRUCTION 0x2 +#define CAUSE_BREAKPOINT 0x3 +#define CAUSE_MISALIGNED_LOAD 0x4 +#define CAUSE_LOAD_ACCESS 0x5 +#define CAUSE_MISALIGNED_STORE 0x6 +#define CAUSE_STORE_ACCESS 0x7 +#define CAUSE_USER_ECALL 0x8 +#define CAUSE_SUPERVISOR_ECALL 0x9 +#define CAUSE_HYPERVISOR_ECALL 0xa +#define CAUSE_MACHINE_ECALL 0xb +#define CAUSE_FETCH_PAGE_FAULT 0xc +#define CAUSE_LOAD_PAGE_FAULT 0xd +#define CAUSE_STORE_PAGE_FAULT 0xf +#endif +#ifdef DECLARE_INSN +DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ) +DECLARE_INSN(bne, MATCH_BNE, MASK_BNE) +DECLARE_INSN(blt, MATCH_BLT, MASK_BLT) +DECLARE_INSN(bge, MATCH_BGE, MASK_BGE) +DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU) +DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU) +DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR) +DECLARE_INSN(jal, MATCH_JAL, MASK_JAL) +DECLARE_INSN(lui, MATCH_LUI, MASK_LUI) +DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC) +DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI) +DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI) +DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI) +DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU) +DECLARE_INSN(xori, MATCH_XORI, MASK_XORI) +DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI) +DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI) +DECLARE_INSN(ori, MATCH_ORI, MASK_ORI) +DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI) +DECLARE_INSN(add, MATCH_ADD, MASK_ADD) +DECLARE_INSN(sub, MATCH_SUB, MASK_SUB) +DECLARE_INSN(sll, MATCH_SLL, MASK_SLL) +DECLARE_INSN(slt, MATCH_SLT, MASK_SLT) +DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU) +DECLARE_INSN(xor, MATCH_XOR, MASK_XOR) +DECLARE_INSN(srl, MATCH_SRL, MASK_SRL) +DECLARE_INSN(sra, MATCH_SRA, MASK_SRA) +DECLARE_INSN(or, MATCH_OR, MASK_OR) +DECLARE_INSN(and, MATCH_AND, MASK_AND) +DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW) +DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW) +DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW) +DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW) +DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW) +DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW) +DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW) +DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW) +DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW) +DECLARE_INSN(lb, MATCH_LB, MASK_LB) +DECLARE_INSN(lh, MATCH_LH, MASK_LH) +DECLARE_INSN(lw, MATCH_LW, MASK_LW) +DECLARE_INSN(ld, MATCH_LD, MASK_LD) +DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU) +DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU) +DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU) +DECLARE_INSN(sb, MATCH_SB, MASK_SB) +DECLARE_INSN(sh, MATCH_SH, MASK_SH) +DECLARE_INSN(sw, MATCH_SW, MASK_SW) +DECLARE_INSN(sd, MATCH_SD, MASK_SD) +DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE) +DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I) +DECLARE_INSN(mul, MATCH_MUL, MASK_MUL) +DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH) +DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU) +DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU) +DECLARE_INSN(div, MATCH_DIV, MASK_DIV) +DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU) +DECLARE_INSN(rem, MATCH_REM, MASK_REM) +DECLARE_INSN(remu, MATCH_REMU, MASK_REMU) +DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW) +DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW) +DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW) +DECLARE_INSN(remw, MATCH_REMW, MASK_REMW) +DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW) +DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W) +DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W) +DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W) +DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W) +DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W) +DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W) +DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W) +DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W) +DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W) +DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W) +DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W) +DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D) +DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D) +DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D) +DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D) +DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D) +DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D) +DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D) +DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D) +DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D) +DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D) +DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D) +DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL) +DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK) +DECLARE_INSN(uret, MATCH_URET, MASK_URET) +DECLARE_INSN(sret, MATCH_SRET, MASK_SRET) +DECLARE_INSN(mret, MATCH_MRET, MASK_MRET) +DECLARE_INSN(dret, MATCH_DRET, MASK_DRET) +DECLARE_INSN(sfence_vma, MATCH_SFENCE_VMA, MASK_SFENCE_VMA) +DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) +DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) +DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS) +DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC) +DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI) +DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI) +DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI) +DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S) +DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S) +DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S) +DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S) +DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S) +DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S) +DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S) +DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S) +DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S) +DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S) +DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D) +DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D) +DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D) +DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D) +DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D) +DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D) +DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D) +DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D) +DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D) +DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D) +DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S) +DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D) +DECLARE_INSN(fadd_q, MATCH_FADD_Q, MASK_FADD_Q) +DECLARE_INSN(fsub_q, MATCH_FSUB_Q, MASK_FSUB_Q) +DECLARE_INSN(fmul_q, MATCH_FMUL_Q, MASK_FMUL_Q) +DECLARE_INSN(fdiv_q, MATCH_FDIV_Q, MASK_FDIV_Q) +DECLARE_INSN(fsgnj_q, MATCH_FSGNJ_Q, MASK_FSGNJ_Q) +DECLARE_INSN(fsgnjn_q, MATCH_FSGNJN_Q, MASK_FSGNJN_Q) +DECLARE_INSN(fsgnjx_q, MATCH_FSGNJX_Q, MASK_FSGNJX_Q) +DECLARE_INSN(fmin_q, MATCH_FMIN_Q, MASK_FMIN_Q) +DECLARE_INSN(fmax_q, MATCH_FMAX_Q, MASK_FMAX_Q) +DECLARE_INSN(fcvt_s_q, MATCH_FCVT_S_Q, MASK_FCVT_S_Q) +DECLARE_INSN(fcvt_q_s, MATCH_FCVT_Q_S, MASK_FCVT_Q_S) +DECLARE_INSN(fcvt_d_q, MATCH_FCVT_D_Q, MASK_FCVT_D_Q) +DECLARE_INSN(fcvt_q_d, MATCH_FCVT_Q_D, MASK_FCVT_Q_D) +DECLARE_INSN(fsqrt_q, MATCH_FSQRT_Q, MASK_FSQRT_Q) +DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S) +DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S) +DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S) +DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D) +DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D) +DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D) +DECLARE_INSN(fle_q, MATCH_FLE_Q, MASK_FLE_Q) +DECLARE_INSN(flt_q, MATCH_FLT_Q, MASK_FLT_Q) +DECLARE_INSN(feq_q, MATCH_FEQ_Q, MASK_FEQ_Q) +DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S) +DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S) +DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S) +DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S) +DECLARE_INSN(fmv_x_w, MATCH_FMV_X_W, MASK_FMV_X_W) +DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S) +DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D) +DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D) +DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D) +DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D) +DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D) +DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D) +DECLARE_INSN(fcvt_w_q, MATCH_FCVT_W_Q, MASK_FCVT_W_Q) +DECLARE_INSN(fcvt_wu_q, MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q) +DECLARE_INSN(fcvt_l_q, MATCH_FCVT_L_Q, MASK_FCVT_L_Q) +DECLARE_INSN(fcvt_lu_q, MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q) +DECLARE_INSN(fmv_x_q, MATCH_FMV_X_Q, MASK_FMV_X_Q) +DECLARE_INSN(fclass_q, MATCH_FCLASS_Q, MASK_FCLASS_Q) +DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) +DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU) +DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L) +DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU) +DECLARE_INSN(fmv_w_x, MATCH_FMV_W_X, MASK_FMV_W_X) +DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W) +DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU) +DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L) +DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU) +DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X) +DECLARE_INSN(fcvt_q_w, MATCH_FCVT_Q_W, MASK_FCVT_Q_W) +DECLARE_INSN(fcvt_q_wu, MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU) +DECLARE_INSN(fcvt_q_l, MATCH_FCVT_Q_L, MASK_FCVT_Q_L) +DECLARE_INSN(fcvt_q_lu, MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU) +DECLARE_INSN(fmv_q_x, MATCH_FMV_Q_X, MASK_FMV_Q_X) +DECLARE_INSN(flw, MATCH_FLW, MASK_FLW) +DECLARE_INSN(fld, MATCH_FLD, MASK_FLD) +DECLARE_INSN(flq, MATCH_FLQ, MASK_FLQ) +DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW) +DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD) +DECLARE_INSN(fsq, MATCH_FSQ, MASK_FSQ) +DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S) +DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S) +DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S) +DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S) +DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D) +DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D) +DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D) +DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D) +DECLARE_INSN(fmadd_q, MATCH_FMADD_Q, MASK_FMADD_Q) +DECLARE_INSN(fmsub_q, MATCH_FMSUB_Q, MASK_FMSUB_Q) +DECLARE_INSN(fnmsub_q, MATCH_FNMSUB_Q, MASK_FNMSUB_Q) +DECLARE_INSN(fnmadd_q, MATCH_FNMADD_Q, MASK_FNMADD_Q) +DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP) +DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP) +DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR) +DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR) +DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK) +DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD) +DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD) +DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW) +DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP) +DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) +DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN) +DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD) +DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW) +DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW) +DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD) +DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW) +DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW) +DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI) +DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL) +DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI) +DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI) +DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI) +DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI) +DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI) +DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB) +DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR) +DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR) +DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND) +DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW) +DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW) +DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J) +DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ) +DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ) +DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI) +DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP) +DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP) +DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP) +DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV) +DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD) +DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP) +DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP) +DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP) +DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0) +DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1) +DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2) +DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD) +DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1) +DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2) +DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1) +DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1) +DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2) +DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD) +DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1) +DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2) +DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2) +DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1) +DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2) +DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD) +DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1) +DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2) +DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3) +DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1) +DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2) +DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD) +DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1) +DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2) +#endif +#ifdef DECLARE_CSR +DECLARE_CSR(fflags, CSR_FFLAGS) +DECLARE_CSR(frm, CSR_FRM) +DECLARE_CSR(fcsr, CSR_FCSR) +DECLARE_CSR(cycle, CSR_CYCLE) +DECLARE_CSR(time, CSR_TIME) +DECLARE_CSR(instret, CSR_INSTRET) +DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3) +DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4) +DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5) +DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6) +DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7) +DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8) +DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9) +DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10) +DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11) +DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12) +DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13) +DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14) +DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15) +DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16) +DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17) +DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18) +DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19) +DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20) +DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21) +DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22) +DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23) +DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24) +DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25) +DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26) +DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27) +DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28) +DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29) +DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30) +DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31) +DECLARE_CSR(sstatus, CSR_SSTATUS) +DECLARE_CSR(sie, CSR_SIE) +DECLARE_CSR(stvec, CSR_STVEC) +DECLARE_CSR(scounteren, CSR_SCOUNTEREN) +DECLARE_CSR(sscratch, CSR_SSCRATCH) +DECLARE_CSR(sepc, CSR_SEPC) +DECLARE_CSR(scause, CSR_SCAUSE) +DECLARE_CSR(stval, CSR_STVAL) +DECLARE_CSR(sip, CSR_SIP) +DECLARE_CSR(satp, CSR_SATP) +DECLARE_CSR(mstatus, CSR_MSTATUS) +DECLARE_CSR(misa, CSR_MISA) +DECLARE_CSR(medeleg, CSR_MEDELEG) +DECLARE_CSR(mideleg, CSR_MIDELEG) +DECLARE_CSR(mie, CSR_MIE) +DECLARE_CSR(mtvec, CSR_MTVEC) +DECLARE_CSR(mcounteren, CSR_MCOUNTEREN) +DECLARE_CSR(mscratch, CSR_MSCRATCH) +DECLARE_CSR(mepc, CSR_MEPC) +DECLARE_CSR(mcause, CSR_MCAUSE) +DECLARE_CSR(mtval, CSR_MTVAL) +DECLARE_CSR(mip, CSR_MIP) +DECLARE_CSR(pmpcfg0, CSR_PMPCFG0) +DECLARE_CSR(pmpcfg1, CSR_PMPCFG1) +DECLARE_CSR(pmpcfg2, CSR_PMPCFG2) +DECLARE_CSR(pmpcfg3, CSR_PMPCFG3) +DECLARE_CSR(pmpaddr0, CSR_PMPADDR0) +DECLARE_CSR(pmpaddr1, CSR_PMPADDR1) +DECLARE_CSR(pmpaddr2, CSR_PMPADDR2) +DECLARE_CSR(pmpaddr3, CSR_PMPADDR3) +DECLARE_CSR(pmpaddr4, CSR_PMPADDR4) +DECLARE_CSR(pmpaddr5, CSR_PMPADDR5) +DECLARE_CSR(pmpaddr6, CSR_PMPADDR6) +DECLARE_CSR(pmpaddr7, CSR_PMPADDR7) +DECLARE_CSR(pmpaddr8, CSR_PMPADDR8) +DECLARE_CSR(pmpaddr9, CSR_PMPADDR9) +DECLARE_CSR(pmpaddr10, CSR_PMPADDR10) +DECLARE_CSR(pmpaddr11, CSR_PMPADDR11) +DECLARE_CSR(pmpaddr12, CSR_PMPADDR12) +DECLARE_CSR(pmpaddr13, CSR_PMPADDR13) +DECLARE_CSR(pmpaddr14, CSR_PMPADDR14) +DECLARE_CSR(pmpaddr15, CSR_PMPADDR15) +DECLARE_CSR(tselect, CSR_TSELECT) +DECLARE_CSR(tdata1, CSR_TDATA1) +DECLARE_CSR(tdata2, CSR_TDATA2) +DECLARE_CSR(tdata3, CSR_TDATA3) +DECLARE_CSR(dcsr, CSR_DCSR) +DECLARE_CSR(dpc, CSR_DPC) +DECLARE_CSR(dscratch, CSR_DSCRATCH) +DECLARE_CSR(dscratch0, CSR_DSCRATCH0) +DECLARE_CSR(dscratch1, CSR_DSCRATCH1) +DECLARE_CSR(mcycle, CSR_MCYCLE) +DECLARE_CSR(minstret, CSR_MINSTRET) +DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3) +DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4) +DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5) +DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6) +DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7) +DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8) +DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9) +DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10) +DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11) +DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12) +DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13) +DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14) +DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15) +DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16) +DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17) +DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18) +DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19) +DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20) +DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21) +DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22) +DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23) +DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24) +DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25) +DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26) +DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27) +DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28) +DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29) +DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30) +DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31) +DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3) +DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4) +DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5) +DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6) +DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7) +DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8) +DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9) +DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10) +DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11) +DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12) +DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13) +DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14) +DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15) +DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16) +DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17) +DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18) +DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19) +DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20) +DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21) +DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22) +DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23) +DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24) +DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25) +DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26) +DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27) +DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28) +DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29) +DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30) +DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31) +DECLARE_CSR(mvendorid, CSR_MVENDORID) +DECLARE_CSR(marchid, CSR_MARCHID) +DECLARE_CSR(mimpid, CSR_MIMPID) +DECLARE_CSR(mhartid, CSR_MHARTID) +DECLARE_CSR(cycleh, CSR_CYCLEH) +DECLARE_CSR(timeh, CSR_TIMEH) +DECLARE_CSR(instreth, CSR_INSTRETH) +DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H) +DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H) +DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H) +DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H) +DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H) +DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H) +DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H) +DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H) +DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H) +DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H) +DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H) +DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H) +DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H) +DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H) +DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H) +DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H) +DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H) +DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H) +DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H) +DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H) +DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H) +DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H) +DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H) +DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H) +DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H) +DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H) +DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H) +DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H) +DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H) +DECLARE_CSR(mcycleh, CSR_MCYCLEH) +DECLARE_CSR(minstreth, CSR_MINSTRETH) +DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H) +DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H) +DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H) +DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H) +DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H) +DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H) +DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H) +DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H) +DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H) +DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H) +DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H) +DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H) +DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H) +DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H) +DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H) +DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H) +DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H) +DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H) +DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H) +DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H) +DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H) +DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H) +DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H) +DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H) +DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H) +DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H) +DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H) +DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H) +DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H) +#endif +#ifdef DECLARE_CAUSE +DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH) +DECLARE_CAUSE("fetch access", CAUSE_FETCH_ACCESS) +DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION) +DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT) +DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD) +DECLARE_CAUSE("load access", CAUSE_LOAD_ACCESS) +DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE) +DECLARE_CAUSE("store access", CAUSE_STORE_ACCESS) +DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL) +DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL) +DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL) +DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL) +DECLARE_CAUSE("fetch page fault", CAUSE_FETCH_PAGE_FAULT) +DECLARE_CAUSE("load page fault", CAUSE_LOAD_PAGE_FAULT) +DECLARE_CAUSE("store page fault", CAUSE_STORE_PAGE_FAULT) +#endif diff --git a/verif/tb/core/bootrom/gen_rom.py b/verif/tb/core/bootrom/gen_rom.py new file mode 100755 index 0000000000..16e4488461 --- /dev/null +++ b/verif/tb/core/bootrom/gen_rom.py @@ -0,0 +1,135 @@ +#!/usr/bin/env python3 + +from string import Template +import argparse +import os.path +import sys +import binascii + + +parser = argparse.ArgumentParser(description='Convert binary file to verilog rom') +parser.add_argument('filename', metavar='filename', nargs=1, + help='filename of input binary') + +args = parser.parse_args() +file = args.filename[0]; + +# check that file exists +if not os.path.isfile(file): + print("File {} does not exist.".format(filename)) + sys.exit(1) + +filename = os.path.splitext(file)[0] + +license = """\ +/* Copyright 2018 ETH Zurich and University of Bologna. + * Copyright and related rights are licensed under the Solderpad Hardware + * License, Version 0.51 (the "License"); you may not use this file except in + * compliance with the License. You may obtain a copy of the License at + * http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law + * or agreed to in writing, software, hardware and materials distributed under + * this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR + * CONDITIONS OF ANY KIND, either express or implied. See the License for the + * specific language governing permissions and limitations under the License. + * + * File: $filename.v + * + * Description: Auto-generated bootrom + */ + +// Auto-generated code +""" + +module = """\ +module $filename ( + input logic clk_i, + input logic req_i, + input logic [63:0] addr_i, + output logic [63:0] rdata_o +); + localparam int RomSize = $size; + + const logic [RomSize-1:0][63:0] mem = { +$content + }; + + logic [$$clog2(RomSize)-1:0] addr_q; + + always_ff @(posedge clk_i) begin + if (req_i) begin + addr_q <= addr_i[$$clog2(RomSize)-1+3:3]; + end + end + + // this prevents spurious Xes from propagating into + // the speculative fetch stage of the core + assign rdata_o = (addr_q < RomSize) ? mem[addr_q] : '0; +endmodule +""" + +c_var = """\ +// Auto-generated code + +const int reset_vec_size = $size; + +uint32_t reset_vec[reset_vec_size] = { +$content +}; +""" + +def read_bin(): + + numlines=0 + with open(filename + ".img", 'rb') as f: + rom = binascii.hexlify(f.read()) + #rom = map(''.join, zip(rom[::2], rom[1::2])) + zipped = zip(rom[::2], rom[1::2]) + #print(zipped) + numlines = numlines+1 + + + #print (numlines) + print (rom) + print (len(rom)) + # align to 64 bit + #mylist = list(rom) + #align = (int((len(rom) + 7) / 8 )) * 8 + + for i in range(len(list(rom)), align): + rom.append("00") + + return rom + +rom = read_bin() + +""" Generate C header file for simulator +""" +with open(filename + ".h", "w") as f: + rom_str = "" + # process in junks of 32 bit (4 byte) + for i in range(0, int(len(rom)/4)): + rom_str += " 0x" + "".join(rom[i*4:i*4+4][::-1]) + ",\n" + + # remove the trailing comma + rom_str = rom_str[:-2] + + s = Template(c_var) + f.write(s.substitute(filename=filename, size=int(len(rom)/4), content=rom_str)) + + f.close() + +""" Generate SystemVerilog bootcode for FPGA and ASIC +""" +with open(filename + ".sv", "w") as f: + rom_str = "" + # process in junks of 64 bit (8 byte) + for i in reversed(range(int(len(rom)/8))): + rom_str += " 64'h" + "".join(rom[i*8+4:i*8+8][::-1]) + "_" + "".join(rom[i*8:i*8+4][::-1]) + ",\n" + + # remove the trailing comma + rom_str = rom_str[:-2] + + f.write(license) + s = Template(module) + f.write(s.substitute(filename=filename, size=int(len(rom)/8), content=rom_str)) + diff --git a/verif/tb/core/bootrom/linker.ld b/verif/tb/core/bootrom/linker.ld new file mode 100644 index 0000000000..43bc012aa8 --- /dev/null +++ b/verif/tb/core/bootrom/linker.ld @@ -0,0 +1,11 @@ +SECTIONS +{ + ROM_BASE = 0x10000; /* ... but actually position independent */ + + . = ROM_BASE; + .text.start : { *(.text.start) } + . = ROM_BASE + 0x40; + .text.hang : { *(.text.hang) } + . = ROM_BASE + 0x80; + .rodata.dtb : { *(.rodata.dtb) } +} diff --git a/verif/tb/core/cva6_tb_verilator.cpp b/verif/tb/core/cva6_tb_verilator.cpp new file mode 100644 index 0000000000..b0ebe688a2 --- /dev/null +++ b/verif/tb/core/cva6_tb_verilator.cpp @@ -0,0 +1,89 @@ +/* + ******************************************************************************* + * + * Copyright 2021 OpenHW Group + * + * Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * https://solderpad.org/licenses/ + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 + * + ******************************************************************************* + * + * Verilator top for the CVA6 "core_only" testbench. + * Genrates clock, reset and optionally dumps waves. + * + ******************************************************************************* + */ + +#include "svdpi.h" +//#include "Vcva6_core_only_tb__Dpi.h" +#include "Vcva6_core_only_tb.h" +#include "verilated_vcd_c.h" +#include "verilated.h" + +#include <iostream> +#include <iomanip> +#include <fstream> +#include <exception> +#include <cstdio> +#include <cstdint> +#include <cerrno> + +double sc_time_stamp(); + +static vluint64_t t = 0; +Vcva6_core_only_tb *top; + +int main(int argc, char **argv, char **env) +{ + + Verilated::commandArgs(argc, argv); + Verilated::traceEverOn(true); + top = new Vcva6_core_only_tb(); + + //svSetScope(svGetScopeFromName( + // "TOP.tb_top_verilator.cv32e40p_tb_wrapper_i.ram_i.dp_ram_i")); + Verilated::scopesDump(); + +#ifdef VCD_TRACE + VerilatedVcdC *tfp = new VerilatedVcdC; + top->trace(tfp, 99); + tfp->open("verilator_tb.vcd"); +#endif + top->verilator_clk_i = 0; + top->verilator_rstn_i = 0; + + top->eval(); + //dump_memory(); + + while (!Verilated::gotFinish()) { + if (t > 40) + top->verilator_rstn_i = 1; + top->verilator_clk_i = !top->verilator_clk_i; + top->eval(); +#ifdef VCD_TRACE + tfp->dump(t); +#endif + t += 5; + } +#ifdef VCD_TRACE + tfp->close(); +#endif + delete top; + exit(0); +} + +double sc_time_stamp() +{ + return t; +} diff --git a/verif/tb/core/tb_components/axi_master_connect.sv b/verif/tb/core/tb_components/axi_master_connect.sv new file mode 100644 index 0000000000..e0e6502d6e --- /dev/null +++ b/verif/tb/core/tb_components/axi_master_connect.sv @@ -0,0 +1,57 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Description: Connects SV AXI interface to structs used by Ariane +// Author: Florian Zaruba <zarubaf@iis.ee.ethz.ch> + +module axi_master_connect ( + input ariane_axi::req_t axi_req_i, + input bit dis_mem, + AXI_BUS.Master master +); + + assign master.aw_id = dis_mem? '0 : axi_req_i.aw.id; + assign master.aw_addr = dis_mem? '0 : axi_req_i.aw.addr; + assign master.aw_len = dis_mem? '0 : axi_req_i.aw.len; + assign master.aw_size = dis_mem? '0 : axi_req_i.aw.size; + assign master.aw_burst = dis_mem? '0 : axi_req_i.aw.burst; + assign master.aw_lock = dis_mem? '0 : axi_req_i.aw.lock; + assign master.aw_cache = dis_mem? '0 : axi_req_i.aw.cache; + assign master.aw_prot = dis_mem? '0 : axi_req_i.aw.prot; + assign master.aw_qos = dis_mem? '0 : axi_req_i.aw.qos; + assign master.aw_atop = dis_mem? '0 : axi_req_i.aw.atop; + assign master.aw_region = dis_mem? '0 : axi_req_i.aw.region; + assign master.aw_user = dis_mem? '0 : '0; + assign master.aw_valid = dis_mem? '0 : axi_req_i.aw_valid; + + assign master.w_data = dis_mem? '0 : axi_req_i.w.data; + assign master.w_strb = dis_mem? '0 : axi_req_i.w.strb; + assign master.w_last = dis_mem? '0 : axi_req_i.w.last; + assign master.w_user = dis_mem? '0 : axi_req_i.w.user; + assign master.w_valid = dis_mem? '0 : axi_req_i.w_valid; + + assign master.b_ready = dis_mem? '0 : axi_req_i.b_ready; + + assign master.ar_id = dis_mem? '0 : axi_req_i.ar.id; + assign master.ar_addr = dis_mem? '0 : axi_req_i.ar.addr; + assign master.ar_len = dis_mem? '0 : axi_req_i.ar.len; + assign master.ar_size = dis_mem? '0 : axi_req_i.ar.size; + assign master.ar_burst = dis_mem? '0 : axi_req_i.ar.burst; + assign master.ar_lock = dis_mem? '0 : axi_req_i.ar.lock; + assign master.ar_cache = dis_mem? '0 : axi_req_i.ar.cache; + assign master.ar_prot = dis_mem? '0 : axi_req_i.ar.prot; + assign master.ar_qos = dis_mem? '0 : axi_req_i.ar.qos; + assign master.ar_region = dis_mem? '0 : axi_req_i.ar.region; + assign master.ar_user = dis_mem? '0 : '0; + assign master.ar_valid = dis_mem? '0 : axi_req_i.ar_valid; + + assign master.r_ready = dis_mem? '0 : axi_req_i.r_ready; + +endmodule diff --git a/verif/tb/uvmt/cva6_tb_wrapper.sv b/verif/tb/uvmt/cva6_tb_wrapper.sv new file mode 100644 index 0000000000..ff16f90c06 --- /dev/null +++ b/verif/tb/uvmt/cva6_tb_wrapper.sv @@ -0,0 +1,276 @@ +/////////////////////////////////////////////////////////////////////////////// +// +// Copyright 2021 OpenHW Group +// Copyright 2021 Thales DIS Design Services SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// +/////////////////////////////////////////////////////////////////////////////// +// +// CVA6 "core_only" testbench wrapper. +// +/////////////////////////////////////////////////////////////////////////////// + +`define MAIN_MEM(P) uvmt_cva6_tb.cva6_dut_wrap.cva6_tb_wrapper_i.i_sram.gen_cut[0].i_tc_sram_wrapper.i_tc_sram.init_val[(``P``)] +`define USER_MEM(P) uvmt_cva6_tb.cva6_dut_wrap.cva6_tb_wrapper_i.i_sram.gen_cut[0].gen_mem_user.i_tc_sram_wrapper_user.i_tc_sram.init_val[(``P``)] + +import uvm_pkg::*; + +`include "uvm_macros.svh" + +import "DPI-C" function read_elf(input string filename); +import "DPI-C" function byte get_section(output longint address, output longint len); +import "DPI-C" context function void read_section(input longint address, inout byte buffer[]); + +module cva6_tb_wrapper import uvmt_cva6_pkg::*; #( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter bit IsRVFI = 1'b0, + parameter type rvfi_instr_t = logic, + // + parameter int unsigned AXI_USER_EN = 0, + parameter int unsigned NUM_WORDS = 2**25 +) ( + input logic clk_i, + input logic rst_ni, + input logic [XLEN-1:0] boot_addr_i, + output logic [31:0] tb_exit_o, + output rvfi_instr_t [CVA6Cfg.NrCommitPorts-1:0] rvfi_o, + input cvxif_pkg::cvxif_resp_t cvxif_resp, + output cvxif_pkg::cvxif_req_t cvxif_req, + uvma_axi_intf axi_slave, + uvmt_axi_switch_intf axi_switch_vif +); + + ariane_axi::req_t axi_ariane_req; + ariane_axi::resp_t axi_ariane_resp; + + static uvm_cmdline_processor uvcl = uvm_cmdline_processor::get_inst(); + string binary = ""; + + rvfi_instr_t [CVA6Cfg.NrCommitPorts-1:0] rvfi; + assign rvfi_o = rvfi; + + cva6 #( + .CVA6Cfg ( CVA6Cfg ), + .IsRVFI ( IsRVFI ), + // + .ArianeCfg ( ariane_soc::ArianeSocCfg ) + ) i_cva6 ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .boot_addr_i ( boot_addr_i ),//Driving the boot_addr value from the core control agent + .hart_id_i ( 64'h0000_0000_0000_0000 ), + .irq_i ( 2'b00 /*irqs*/ ), + .ipi_i ( 1'b0 /*ipi*/ ), + .time_irq_i ( 1'b0 /*timer_irq*/ ), + .debug_req_i ( 1'b0 ), + .rvfi_o ( rvfi ), + .cvxif_req_o ( cvxif_req ), + .cvxif_resp_i ( cvxif_resp ), + .noc_req_o ( axi_ariane_req ), + .noc_resp_i ( axi_ariane_resp ) + ); + + //---------------------------------------------------------------------------- + // RVFI + //---------------------------------------------------------------------------- + + rvfi_tracer #( + .CVA6Cfg(CVA6Cfg), + .rvfi_instr_t(rvfi_instr_t), + // + .HART_ID(8'h0), + .DEBUG_START(0), + .DEBUG_STOP(0) + ) rvfi_tracer_i ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .rvfi_i(rvfi), + .end_of_test_o(tb_exit_o) + ) ; + + //---------------------------------------------------------------------------- + // Memory + //---------------------------------------------------------------------------- + + logic req; + logic we; + logic [CVA6Cfg.AxiAddrWidth-1:0] addr; + logic [CVA6Cfg.AxiDataWidth/8-1:0] be; + logic [CVA6Cfg.AxiDataWidth-1:0] wdata; + logic [CVA6Cfg.AxiUserWidth-1:0] wuser; + logic [CVA6Cfg.AxiDataWidth-1:0] rdata; + logic [CVA6Cfg.AxiUserWidth-1:0] ruser; + + //Response structs + assign axi_ariane_resp.aw_ready = (axi_switch_vif.active) ? axi_slave.aw_ready : cva6_axi_bus.aw_ready; + assign axi_ariane_resp.ar_ready = (axi_switch_vif.active) ? axi_slave.ar_ready : cva6_axi_bus.ar_ready; + assign axi_ariane_resp.w_ready = (axi_switch_vif.active) ? axi_slave.w_ready : cva6_axi_bus.w_ready; + assign axi_ariane_resp.b_valid = (axi_switch_vif.active) ? axi_slave.b_valid : cva6_axi_bus.b_valid; + assign axi_ariane_resp.r_valid = (axi_switch_vif.active) ? axi_slave.r_valid : cva6_axi_bus.r_valid; + // B Channel + assign axi_ariane_resp.b.id = (axi_switch_vif.active) ? axi_slave.b_id : cva6_axi_bus.b_id; + assign axi_ariane_resp.b.resp = (axi_switch_vif.active) ? axi_slave.b_resp : cva6_axi_bus.b_resp; + assign axi_ariane_resp.b.user = (axi_switch_vif.active) ? axi_slave.b_user : cva6_axi_bus.b_user; + // R Channel + assign axi_ariane_resp.r.id = (axi_switch_vif.active) ? axi_slave.r_id : cva6_axi_bus.r_id; + assign axi_ariane_resp.r.data = (axi_switch_vif.active) ? axi_slave.r_data : cva6_axi_bus.r_data; + assign axi_ariane_resp.r.resp = (axi_switch_vif.active) ? axi_slave.r_resp : cva6_axi_bus.r_resp; + assign axi_ariane_resp.r.last = (axi_switch_vif.active) ? axi_slave.r_last : cva6_axi_bus.r_last; + assign axi_ariane_resp.r.user = (axi_switch_vif.active) ? axi_slave.r_user : cva6_axi_bus.r_user; + + assign axi_slave.aw_ready = (axi_switch_vif.active) ? axi_slave.aw_ready : cva6_axi_bus.aw_ready; + assign axi_slave.ar_ready = (axi_switch_vif.active) ? axi_slave.ar_ready : cva6_axi_bus.ar_ready; + assign axi_slave.w_ready = (axi_switch_vif.active) ? axi_slave.w_ready : cva6_axi_bus.w_ready; + assign axi_slave.b_valid = (axi_switch_vif.active) ? axi_slave.b_valid : cva6_axi_bus.b_valid; + assign axi_slave.r_valid = (axi_switch_vif.active) ? axi_slave.r_valid : cva6_axi_bus.r_valid; + + assign axi_slave.b_id = (axi_switch_vif.active) ? axi_slave.b_id : cva6_axi_bus.b_id; + assign axi_slave.b_resp = (axi_switch_vif.active) ? axi_slave.b_resp : cva6_axi_bus.b_resp; + assign axi_slave.b_user = (axi_switch_vif.active) ? axi_slave.b_user : cva6_axi_bus.b_user; + + assign axi_slave.r_id = (axi_switch_vif.active) ? axi_slave.r_id : cva6_axi_bus.r_id; + assign axi_slave.r_data = (axi_switch_vif.active) ? axi_slave.r_data : cva6_axi_bus.r_data; + assign axi_slave.r_resp = (axi_switch_vif.active) ? axi_slave.r_resp : cva6_axi_bus.r_resp; + assign axi_slave.r_last = (axi_switch_vif.active) ? axi_slave.r_last : cva6_axi_bus.r_last; + assign axi_slave.r_user = (axi_switch_vif.active) ? axi_slave.r_user : cva6_axi_bus.r_user; + + // Request structs + assign axi_slave.aw_valid = axi_ariane_req.aw_valid; + assign axi_slave.w_valid = axi_ariane_req.w_valid; + assign axi_slave.b_ready = axi_ariane_req.b_ready; + assign axi_slave.ar_valid = axi_ariane_req.ar_valid; + assign axi_slave.r_ready = axi_ariane_req.r_ready; + // AW Channel + assign axi_slave.aw_id = axi_ariane_req.aw.id; + assign axi_slave.aw_addr = axi_ariane_req.aw.addr; + assign axi_slave.aw_len = axi_ariane_req.aw.len; + assign axi_slave.aw_size = axi_ariane_req.aw.size; + assign axi_slave.aw_burst = axi_ariane_req.aw.burst; + assign axi_slave.aw_lock = axi_ariane_req.aw.lock; + assign axi_slave.aw_cache = axi_ariane_req.aw.cache; + assign axi_slave.aw_prot = axi_ariane_req.aw.prot; + assign axi_slave.aw_qos = axi_ariane_req.aw.qos; + assign axi_slave.aw_region = axi_ariane_req.aw.region; + assign axi_slave.aw_user = 0; + // W Channel + assign axi_slave.w_data = axi_ariane_req.w.data; + assign axi_slave.w_strb = axi_ariane_req.w.strb; + assign axi_slave.w_last = axi_ariane_req.w.last; + assign axi_slave.w_user = 0; + // AR Channel + assign axi_slave.ar_id = axi_ariane_req.ar.id; + assign axi_slave.ar_addr = axi_ariane_req.ar.addr; + assign axi_slave.ar_len = axi_ariane_req.ar.len; + assign axi_slave.ar_size = axi_ariane_req.ar.size; + assign axi_slave.ar_burst = axi_ariane_req.ar.burst; + assign axi_slave.ar_lock = axi_ariane_req.ar.lock; + assign axi_slave.ar_cache = axi_ariane_req.ar.cache; + assign axi_slave.ar_prot = axi_ariane_req.ar.prot; + assign axi_slave.ar_qos = axi_ariane_req.ar.qos; + assign axi_slave.ar_region = axi_ariane_req.ar.region; + assign axi_slave.ar_user = 0; + + + AXI_BUS #( + .AXI_ADDR_WIDTH ( CVA6Cfg.AxiAddrWidth ), + .AXI_DATA_WIDTH ( CVA6Cfg.AxiDataWidth ), + .AXI_ID_WIDTH ( ariane_soc::IdWidthSlave ), + .AXI_USER_WIDTH ( CVA6Cfg.AxiUserWidth ) + ) cva6_axi_bus(); + + axi_master_connect #( + ) i_axi_master_connect_cva6_to_mem ( + .axi_req_i (axi_ariane_req), + .dis_mem (axi_switch_vif.active), + .master (cva6_axi_bus) + ); + + axi2mem #( + .AXI_ID_WIDTH ( ariane_soc::IdWidthSlave ), + .AXI_ADDR_WIDTH ( CVA6Cfg.AxiAddrWidth ), + .AXI_DATA_WIDTH ( CVA6Cfg.AxiDataWidth ), + .AXI_USER_WIDTH ( CVA6Cfg.AxiUserWidth ) + ) i_cva6_axi2mem ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .slave ( cva6_axi_bus ), + .req_o ( req ), + .we_o ( we ), + .addr_o ( addr ), + .be_o ( be ), + .user_o ( wuser ), + .data_o ( wdata ), + .user_i ( ruser ), + .data_i ( rdata ) + ); + + sram #( + .USER_WIDTH ( CVA6Cfg.AxiUserWidth ), + .DATA_WIDTH ( CVA6Cfg.AxiDataWidth ), + .USER_EN ( AXI_USER_EN ), + .SIM_INIT ( "zeros" ), + .NUM_WORDS ( NUM_WORDS ) + ) i_sram ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .req_i ( req ), + .we_i ( we ), + .addr_i ( addr[$clog2(NUM_WORDS)-1+$clog2(CVA6Cfg.AxiDataWidth/8):$clog2(CVA6Cfg.AxiDataWidth/8)] ), + .wuser_i ( wuser ), + .wdata_i ( wdata ), + .be_i ( be ), + .ruser_o ( ruser ), + .rdata_o ( rdata ) + ); + + initial begin + wait ( + !$isunknown(axi_switch_vif.active) + ); + if(!axi_switch_vif.active) begin + automatic logic [7:0][7:0] mem_row; + longint address; + longint len; + byte buffer[]; + void'(uvcl.get_arg_value("+PRELOAD=", binary)); + + if (binary != "") begin + + void'(read_elf(binary)); + + wait(clk_i); + + // while there are more sections to process + while (get_section(address, len)) begin + automatic int num_words0 = (len+7)/8; + `uvm_info( "Core Test", $sformatf("Loading Address: %x, Length: %x", address, len), UVM_LOW) + buffer = new [num_words0*8]; + void'(read_section(address, buffer)); + // preload memories + // 64-bit + for (int i = 0; i < num_words0; i++) begin + mem_row = '0; + for (int j = 0; j < 8; j++) begin + mem_row[j] = buffer[i*8 + j]; + end + `MAIN_MEM((address[23:0] >> 3) + i) = mem_row; + end + end + end + end + end + +endmodule diff --git a/verif/tb/uvmt/uvmt_axi_assert.sv b/verif/tb/uvmt/uvmt_axi_assert.sv new file mode 100644 index 0000000000..843153cdf9 --- /dev/null +++ b/verif/tb/uvmt/uvmt_axi_assert.sv @@ -0,0 +1,52 @@ +// Copyright 2022 Thales DIS SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Alae Eddine EZ ZEJJARI (alae-eddine.ez-zejjari@external.thalesgroup.com) + +module uvmt_axi_assert (uvma_axi_intf.passive axi_assert, input bit clk, input rst_n); + + import uvm_pkg::*; + + + bind uvmt_axi_assert + uvma_axi_aw_assert axi_aw_assert(.axi_assert(axi_assert), + .clk(clk), + .rst_n(rst_n) + ); + + bind uvmt_axi_assert + uvma_axi_ar_assert axi_ar_assert(.axi_assert(axi_assert), + .clk(clk), + .rst_n(rst_n) + ); + + bind uvmt_axi_assert + uvma_axi_w_assert axi_w_assert(.axi_assert(axi_assert), + .clk(clk), + .rst_n(rst_n) + ); + + bind uvmt_axi_assert + uvma_axi_r_assert axi_r_assert(.axi_assert(axi_assert), + .clk(clk), + .rst_n(rst_n) + ); + + bind uvmt_axi_assert + uvma_axi_b_assert axi_b_assert(.axi_assert(axi_assert), + .clk(clk), + .rst_n(rst_n) + ); + + bind uvmt_axi_assert + uvmt_cva6_axi_assert cva6_axi_assert(.axi_assert(axi_assert), + .clk(clk), + .rst_n(rst_n) + ); + + +endmodule : uvmt_axi_assert diff --git a/verif/tb/uvmt/uvmt_axi_switch_intf.sv b/verif/tb/uvmt/uvmt_axi_switch_intf.sv new file mode 100644 index 0000000000..6e9d9d61e4 --- /dev/null +++ b/verif/tb/uvmt/uvmt_axi_switch_intf.sv @@ -0,0 +1,18 @@ +// Copyright 2022 Thales DIS SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Alae Eddine EZ ZEJJARI (alae-eddine.ez-zejjari@external.thalesgroup.com) + +/**** AXI interface to indicate the state of the agent ****/ + + +interface uvmt_axi_switch_intf; + + logic active; + + +endinterface : uvmt_axi_switch_intf diff --git a/verif/tb/uvmt/uvmt_cva6.flist b/verif/tb/uvmt/uvmt_cva6.flist new file mode 100644 index 0000000000..fb5b855e98 --- /dev/null +++ b/verif/tb/uvmt/uvmt_cva6.flist @@ -0,0 +1,53 @@ +// Copyright 2021 Thales DIS Design Services SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 + +// Libraries +-f ${DV_UVML_HRTBT_PATH}/uvml_hrtbt_pkg.flist +-f ${DV_UVML_TRN_PATH}/uvml_trn_pkg.flist +-f ${DV_UVML_LOGS_PATH}/uvml_logs_pkg.flist +-f ${DV_UVML_MEM_PATH}/uvml_mem_pkg.flist +-f ${DV_UVML_SB_PATH}/uvml_sb_pkg.flist + +// Agents +-f ${DV_UVMA_CLKNRST_PATH}/uvma_clknrst_pkg.flist +-f ${DV_UVMA_CVXIF_PATH}/src/uvma_cvxif_pkg.flist +-f ${DV_UVMA_AXI_PATH}/src/uvma_axi_pkg.flist +-f ${DV_UVMA_CORE_CNTRL_PATH}/uvma_core_cntrl_pkg.flist +-f ${DV_UVMA_RVFI_PATH}/uvma_rvfi_pkg.flist +-f ${DV_UVMA_ISACOV_PATH}/uvma_isacov_pkg.flist + +// Environments +-f ${CVA6_UVME_PATH}/uvme_cva6_pkg.flist + +// CVA6 test bench Directories ++incdir+${CVA6_UVME_PATH}/../../tests/uvmt/base-tests ++incdir+${CVA6_UVME_PATH}/../../tests/uvmt/compliance-tests ++incdir+${CVA6_UVMT_PATH} ++incdir+${CVA6_UVMT_PATH}/../../tests/uvmt ++incdir+${CVA6_UVMT_PATH}/../../tests/uvmt/vseq + +// CVA6 tests (includes constants/macros/types meant for test bench) ++incdir+${TBSRC_HOME} +${CVA6_UVMT_DIR}/uvmt_cva6_pkg.sv + +// CVA6 test bench files +${CVA6_UVMT_DIR}/uvmt_cva6_tb_ifs.sv +${CVA6_UVMT_DIR}/uvmt_cva6_tb.sv +${CVA6_UVMT_DIR}/uvmt_cva6_dut_wrap.sv +${CVA6_UVMT_DIR}/cva6_tb_wrapper.sv + +${CVA6_UVMT_DIR}/uvmt_axi_assert.sv +${CVA6_UVMT_DIR}/uvmt_cva6_axi_assert.sv diff --git a/verif/tb/uvmt/uvmt_cva6_axi_assert.sv b/verif/tb/uvmt/uvmt_cva6_axi_assert.sv new file mode 100644 index 0000000000..8e74ad88a4 --- /dev/null +++ b/verif/tb/uvmt/uvmt_cva6_axi_assert.sv @@ -0,0 +1,187 @@ +// Copyright 2022 Thales DIS SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Alae Eddine EZ ZEJJARI (alae-eddine.ez-zejjari@external.thalesgroup.com) + +// *************************** AXI features supported by CVA6 ************************** // + +module uvmt_cva6_axi_assert (uvma_axi_intf axi_assert, input bit clk, input rst_n); + + import uvm_pkg::*; + + + //check if the CVA6 identify read transaction with an ID equal to 0 or 1 + property AXI4_CVA6_ARID; + @(posedge clk) disable iff (!rst_n) axi_assert.ar_valid |-> axi_assert.ar_id == 0 || axi_assert.ar_id == 1; + endproperty + + //check if the CVA6 identify write transaction with an ID equal to 0 or 1 + property AXI4_CVA6_AWID; + @(posedge clk) disable iff (!rst_n) axi_assert.aw_valid |-> axi_assert.aw_id == 1; + endproperty + + //Check if user-defined extension for read address channel is equal to 0b00 + property AXI4_CVA6_ARUSER; + @(posedge clk) disable iff (!rst_n) axi_assert.ar_valid |-> axi_assert.ar_user == 0; + endproperty + + //Check if user-defined extension for write address channel is equal to 0b00 + property AXI4_CVA6_AWUSER; + @(posedge clk) disable iff (!rst_n) axi_assert.aw_valid |-> axi_assert.aw_user == 0; + endproperty + + //Check if Quality of Service identifier for write transaction is equal to 0b0000 + property AXI4_CVA6_AWQOS; + @(posedge clk) disable iff (!rst_n) axi_assert.aw_valid |-> axi_assert.aw_qos == 0; + endproperty + + //Check if Quality of Service identifier for read transaction is equal to 0b0000 + property AXI4_CVA6_ARQOS; + @(posedge clk) disable iff (!rst_n) axi_assert.ar_valid |-> axi_assert.ar_qos == 0; + endproperty + + //Check if Region indicator for write transaction is equal to 0b0000 + property AXI4_CVA6_AWREGION; + @(posedge clk) disable iff (!rst_n) axi_assert.aw_valid |-> axi_assert.aw_region == 0; + endproperty + + //Check if Region indicator for read transaction is equal to 0b0000 + property AXI4_CVA6_ARREGION; + @(posedge clk) disable iff (!rst_n) axi_assert.ar_valid |-> axi_assert.ar_region == 0; + endproperty + + //Check if AWCACHE is always equal to 0b0000 + property AXI4_CVA6_AWCACHE; + @(posedge clk) disable iff (!rst_n) axi_assert.aw_valid |-> axi_assert.aw_cache == 2; + endproperty + + //Check if ARCACHE is always equal to 0b0000 + property AXI4_CVA6_ARCACHE; + @(posedge clk) disable iff (!rst_n) axi_assert.ar_valid |-> axi_assert.ar_cache == 2; + endproperty + + //Check if Protection attributes for write transaction always take the 0b000 + property AXI4_CVA6_AWPROT; + @(posedge clk) disable iff (!rst_n) axi_assert.aw_valid |-> axi_assert.aw_prot == 0; + endproperty + + //Check if Protection attributes for read transaction always take the 0b000 + property AXI4_CVA6_ARPROT; + @(posedge clk) disable iff (!rst_n) axi_assert.ar_valid |-> axi_assert.ar_prot == 0; + endproperty + + //Check if all write transaction performed by CVA6 are of type INCR + property AXI4_CVA6_AWBURST; + @(posedge clk) disable iff (!rst_n) axi_assert.aw_valid |-> axi_assert.aw_burst == 1; + endproperty + + //Check if all read transaction performed by CVA6 are of type INCR + property AXI4_CVA6_ARBURST; + @(posedge clk) disable iff (!rst_n) axi_assert.ar_valid |-> axi_assert.ar_burst == 1; + endproperty + + //Check if all write transaction performed by CVA6 are equal to 0 + property AXI4_CVA6_AWLEN; + @(posedge clk) disable iff (!rst_n) axi_assert.aw_valid |-> axi_assert.aw_len == 0; + endproperty + + //Check if all Read transaction performed by CVA6 are equal to 0 or 1 + property AXI4_CVA6_ARLEN; + @(posedge clk) disable iff (!rst_n) axi_assert.ar_valid |-> axi_assert.ar_len == 0 || axi_assert.ar_len == 1; + endproperty + +/********************************************** Assert Property ******************************************************/ + + cva6_arid : assert property (AXI4_CVA6_ARID) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_CVA6_ARID"); + + cva6_awid : assert property (AXI4_CVA6_AWID) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_CVA6_AWID"); + + cva6_aruser : assert property (AXI4_CVA6_ARUSER) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_CVA6_ARUSER"); + + cva6_awuser : assert property (AXI4_CVA6_AWUSER) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_CVA6_AWUSER"); + + cva6_arqos : assert property (AXI4_CVA6_ARQOS) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_CVA6_ARQOS"); + + cva6_awqos : assert property (AXI4_CVA6_AWQOS) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_CVA6_AWQOS"); + + cva6_arregion : assert property (AXI4_CVA6_ARREGION) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_CVA6_ARREGION"); + + cva6_awregion : assert property (AXI4_CVA6_AWREGION) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_CVA6_AWREGION"); + + cva6_arcache : assert property (AXI4_CVA6_ARCACHE) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_CVA6_ARCAHCE"); + + cva6_awcache : assert property (AXI4_CVA6_AWCACHE) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_CVA6_AWCAHCE"); + + cva6_arprot : assert property (AXI4_CVA6_ARPROT) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_CVA6_ARPROT"); + + cva6_awprot : assert property (AXI4_CVA6_AWPROT) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_CVA6_AWPROT"); + + cva6_arburst : assert property (AXI4_CVA6_ARBURST) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_CVA6_ARBURST"); + + cva6_awburst : assert property (AXI4_CVA6_AWBURST) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_CVA6_AWBURST"); + + cva6_arlen : assert property (AXI4_CVA6_ARLEN) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_CVA6_ARLEN"); + + cva6_awlen : assert property (AXI4_CVA6_AWLEN) + else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_CVA6_AWLEN"); + +/********************************************** Cover Property ******************************************************/ + + + cov_cva6_arid : cover property(AXI4_CVA6_ARID); + + cov_cva6_awid : cover property(AXI4_CVA6_AWID); + + cov_cva6_aruser : cover property(AXI4_CVA6_ARUSER); + + cov_cva6_awuser : cover property(AXI4_CVA6_AWUSER); + + cov_cva6_arqos : cover property(AXI4_CVA6_ARQOS); + + cov_cva6_awqos : cover property(AXI4_CVA6_AWQOS); + + cov_cva6_arregion : cover property(AXI4_CVA6_ARREGION); + + cov_cva6_awregion : cover property(AXI4_CVA6_AWREGION); + + cov_cva6_arcache : cover property(AXI4_CVA6_ARCACHE); + + cov_cva6_awcache : cover property(AXI4_CVA6_AWCACHE); + + cov_cva6_arprot : cover property(AXI4_CVA6_ARPROT); + + cov_cva6_awprot : cover property(AXI4_CVA6_AWPROT); + + cov_cva6_arburst : cover property(AXI4_CVA6_ARBURST); + + cov_cva6_awburst : cover property(AXI4_CVA6_AWBURST); + + cov_cva6_arlen : cover property(AXI4_CVA6_ARLEN); + + cov_cva6_awlen : cover property(AXI4_CVA6_AWLEN); + + + + +endmodule : uvmt_cva6_axi_assert + + diff --git a/verif/tb/uvmt/uvmt_cva6_constants.sv b/verif/tb/uvmt/uvmt_cva6_constants.sv new file mode 100644 index 0000000000..94d0f8e1a6 --- /dev/null +++ b/verif/tb/uvmt/uvmt_cva6_constants.sv @@ -0,0 +1,24 @@ +// Copyright 2020 OpenHW Group +// Copyright 2020 Datum Technologies +// Copyright 2021 Thales DIS Design Services SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 + +`ifndef __UVMT_CVA6_CONSTANTS_SV__ +`define __UVMT_CVA6_CONSTANTS_SV__ + +parameter XLEN = 32; + +`endif // __UVMT_CVA6_CONSTANTS_SV__ diff --git a/verif/tb/uvmt/uvmt_cva6_dut_wrap.sv b/verif/tb/uvmt/uvmt_cva6_dut_wrap.sv new file mode 100644 index 0000000000..ec3e2d4d7a --- /dev/null +++ b/verif/tb/uvmt/uvmt_cva6_dut_wrap.sv @@ -0,0 +1,70 @@ +// Copyright 2021 Thales DIS Design Services SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 + +module uvmt_cva6_dut_wrap # ( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter bit IsRVFI = 1'b0, + parameter type rvfi_instr_t = logic, + // + parameter int unsigned AXI_USER_EN = 0, + parameter int unsigned NUM_WORDS = 2**25 +) + + ( + uvma_clknrst_if clknrst_if, + uvma_cvxif_intf cvxif_if, + uvma_axi_intf axi_if, + uvmt_axi_switch_intf axi_switch_vif, + uvme_cva6_core_cntrl_if core_cntrl_if, + output logic[31:0] tb_exit_o, + output rvfi_instr_t [CVA6Cfg.NrCommitPorts-1:0] rvfi_o + ); + + + + cva6_tb_wrapper #( + .CVA6Cfg ( CVA6Cfg ), + .IsRVFI ( IsRVFI ), + .rvfi_instr_t ( rvfi_instr_t ), + // + .AXI_USER_EN (AXI_USER_EN), + .NUM_WORDS (NUM_WORDS) +) + cva6_tb_wrapper_i ( + .clk_i ( clknrst_if.clk ), + .rst_ni ( clknrst_if.reset_n ), + .boot_addr_i ( core_cntrl_if.boot_addr ), + .cvxif_resp ( cvxif_if.cvxif_resp_o ), + .cvxif_req ( cvxif_if.cvxif_req_i ), + .axi_slave ( axi_if ), + .axi_switch_vif ( axi_switch_vif ), + .tb_exit_o ( tb_exit_o ), + .rvfi_o ( rvfi_o ) +); + + assign cvxif_if.cvxif_resp_o.x_compressed_ready = 0; + assign cvxif_if.cvxif_resp_o.x_compressed_resp = 0; + assign cvxif_if.cvxif_resp_o.x_issue_ready = 1; + assign cvxif_if.cvxif_resp_o.x_issue_resp = 0; + assign cvxif_if.cvxif_resp_o.x_result_valid = 0; + assign cvxif_if.cvxif_resp_o.x_result.id = 0; + assign cvxif_if.cvxif_resp_o.x_result.data = 0; + assign cvxif_if.cvxif_resp_o.x_result.rd = 0; + assign cvxif_if.cvxif_resp_o.x_result.we = 0; + assign cvxif_if.cvxif_resp_o.x_result.exc = 0; + assign cvxif_if.cvxif_resp_o.x_result.exccode = 0; + +endmodule diff --git a/verif/tb/uvmt/uvmt_cva6_macros.sv b/verif/tb/uvmt/uvmt_cva6_macros.sv new file mode 100644 index 0000000000..688cd86d0f --- /dev/null +++ b/verif/tb/uvmt/uvmt_cva6_macros.sv @@ -0,0 +1,23 @@ +// Copyright 2020 OpenHW Group +// Copyright 2020 Datum Technologies +// Copyright 2021 Thales DIS Design Services SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 + +`ifndef __UVMT_CVA6_MACROS_SV__ +`define __UVMT_CVA6_MACROS_SV__ + + +`endif // __UVMT_CVA6_MACROS_SV__ diff --git a/verif/tb/uvmt/uvmt_cva6_pkg.sv b/verif/tb/uvmt/uvmt_cva6_pkg.sv new file mode 100644 index 0000000000..2135ad9640 --- /dev/null +++ b/verif/tb/uvmt/uvmt_cva6_pkg.sv @@ -0,0 +1,65 @@ +// Copyright 2020 OpenHW Group +// Copyright 2020 Datum Technologies +// Copyright 2021 Thales DIS Design Services SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 + + +`ifndef __UVMT_CVA6_PKG_SV__ +`define __UVMT_CVA6_PKG_SV__ + + +// Pre-processor macros +`include "uvm_macros.svh" +`include "uvml_hrtbt_macros.sv" +`include "uvml_logs_macros.sv" +`include "uvmt_cva6_macros.sv" + +`include "uvmt_axi_switch_intf.sv" + +/** + * Encapsulates all the types and test cases for the verification of an + * CVA6 RTL design. + */ +package uvmt_cva6_pkg; + + import uvm_pkg::*; + import uvme_cva6_pkg::*; + import uvml_hrtbt_pkg::*; + import uvml_logs_pkg::*; + + // Constants / Structs / Enums + `include "uvmt_cva6_constants.sv" + `include "uvmt_cva6_tdefs.sv" + + // Virtual sequence library + // TODO Add virtual sequences + // Ex: `include "uvmt_cva6_sanity_vseq.sv" + `include "uvmt_cva6_vseq_lib.sv" + + // Base test case + `include "uvmt_cva6_test_cfg.sv" + `include "uvmt_cva6_base_test.sv" // all testcases should extend from this testcase + //`include "uvmt_cva6_smoke_test.sv" // smoke test has multile XMRs that are illegal according to the LRM + + // Compilance tests + `include "uvmt_cva6_firmware_test.sv" + +endpackage : uvmt_cva6_pkg + +// All Interfaces used by the CVA6 TB are here +//`include "uvmt_cva6_tb_ifs.sv" + +`endif // __UVMT_CVA6_PKG_SV__ diff --git a/verif/tb/uvmt/uvmt_cva6_tb.sv b/verif/tb/uvmt/uvmt_cva6_tb.sv new file mode 100644 index 0000000000..72f4f615a2 --- /dev/null +++ b/verif/tb/uvmt/uvmt_cva6_tb.sv @@ -0,0 +1,389 @@ +// Copyright 2021 Thales DIS Design Services SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 + + +`ifndef __UVMT_CVA6_TB_SV__ +`define __UVMT_CVA6_TB_SV__ + + +/** + * Module encapsulating the CVA6 DUT wrapper, and associated SV interfaces. + * Also provide UVM environment entry and exit points. + */ +`default_nettype none +module uvmt_cva6_tb; + + import uvm_pkg::*; + import uvmt_cva6_pkg::*; + import uvme_cva6_pkg::*; + + // CVA6 config + localparam config_pkg::cva6_cfg_t CVA6Cfg = cva6_config_pkg::cva6_cfg; + localparam bit IsRVFI = bit'(cva6_config_pkg::CVA6ConfigRvfiTrace); + localparam type rvfi_instr_t = struct packed { + logic [config_pkg::NRET-1:0] valid; + logic [config_pkg::NRET*64-1:0] order; + logic [config_pkg::NRET*config_pkg::ILEN-1:0] insn; + logic [config_pkg::NRET-1:0] trap; + logic [config_pkg::NRET*riscv::XLEN-1:0] cause; + logic [config_pkg::NRET-1:0] halt; + logic [config_pkg::NRET-1:0] intr; + logic [config_pkg::NRET*2-1:0] mode; + logic [config_pkg::NRET*2-1:0] ixl; + logic [config_pkg::NRET*5-1:0] rs1_addr; + logic [config_pkg::NRET*5-1:0] rs2_addr; + logic [config_pkg::NRET*riscv::XLEN-1:0] rs1_rdata; + logic [config_pkg::NRET*riscv::XLEN-1:0] rs2_rdata; + logic [config_pkg::NRET*5-1:0] rd_addr; + logic [config_pkg::NRET*riscv::XLEN-1:0] rd_wdata; + logic [config_pkg::NRET*riscv::XLEN-1:0] pc_rdata; + logic [config_pkg::NRET*riscv::XLEN-1:0] pc_wdata; + logic [config_pkg::NRET*riscv::VLEN-1:0] mem_addr; + logic [config_pkg::NRET*riscv::PLEN-1:0] mem_paddr; + logic [config_pkg::NRET*(riscv::XLEN/8)-1:0] mem_rmask; + logic [config_pkg::NRET*(riscv::XLEN/8)-1:0] mem_wmask; + logic [config_pkg::NRET*riscv::XLEN-1:0] mem_rdata; + logic [config_pkg::NRET*riscv::XLEN-1:0] mem_wdata; + }; + + localparam AXI_USER_EN = ariane_pkg::AXI_USER_EN; + localparam NUM_WORDS = 2**24; + + // ENV (testbench) parameters + parameter int ENV_PARAM_INSTR_ADDR_WIDTH = 32; + parameter int ENV_PARAM_INSTR_DATA_WIDTH = 32; + parameter int ENV_PARAM_RAM_ADDR_WIDTH = 22; + + // Agent interfaces + uvma_clknrst_if clknrst_if(); // clock and resets from the clknrst agent + uvma_cvxif_intf cvxif_if( + .clk(clknrst_if.clk), + .reset_n(clknrst_if.reset_n) + ); // cvxif from the cvxif agent + uvma_axi_intf axi_if( + .clk(clknrst_if.clk), + .rst_n(clknrst_if.reset_n) + ); + uvmt_axi_switch_intf axi_switch_vif(); + uvme_cva6_core_cntrl_if core_cntrl_if(); + uvma_rvfi_instr_if #( + uvme_cva6_pkg::ILEN, + uvme_cva6_pkg::XLEN + ) rvfi_instr_if [uvme_cva6_pkg::RVFI_NRET-1:0] (); + + uvma_rvfi_csr_if#(uvme_cva6_pkg::XLEN) rvfi_csr_if [uvme_cva6_pkg::RVFI_NRET-1:0](); + + //bind assertion module for cvxif interface + bind uvmt_cva6_dut_wrap + uvma_cvxif_assert cvxif_assert(.cvxif_assert(cvxif_if), + .clk(clknrst_if.clk), + .reset_n(clknrst_if.reset_n) + ); + //bind assertion module for axi interface + bind uvmt_cva6_dut_wrap + uvmt_axi_assert axi_assert(.axi_assert(axi_if.passive), + .clk(clknrst_if.clk), + .rst_n(clknrst_if.reset_n) + ); + // DUT Wrapper Interfaces + uvmt_rvfi_if #( + // RVFI + .rvfi_instr_t ( rvfi_instr_t ), + .CVA6Cfg ( CVA6Cfg ) + ) rvfi_if( + .rvfi_o(), + .tb_exit_o() + ); // Status information generated by the Virtual Peripherals in the DUT WRAPPER memory. + + /** + * DUT WRAPPER instance + */ + + uvmt_cva6_dut_wrap #( + .CVA6Cfg ( CVA6Cfg ), + .IsRVFI ( IsRVFI ), + .rvfi_instr_t ( rvfi_instr_t ), + // + .AXI_USER_EN (AXI_USER_EN), + .NUM_WORDS (NUM_WORDS) + ) cva6_dut_wrap ( + .clknrst_if(clknrst_if), + .cvxif_if (cvxif_if), + .axi_if (axi_if), + .axi_switch_vif (axi_switch_vif), + .core_cntrl_if(core_cntrl_if), + .tb_exit_o(rvfi_if.tb_exit_o), + .rvfi_o(rvfi_if.rvfi_o) + ); + + for (genvar i = 0; i < uvme_cva6_pkg::RVFI_NRET; i++) begin + assign rvfi_instr_if[i].clk = clknrst_if.clk; + assign rvfi_instr_if[i].reset_n = clknrst_if.reset_n; + assign rvfi_instr_if[i].rvfi_valid = rvfi_if.rvfi_o[i].valid; + assign rvfi_instr_if[i].rvfi_order = rvfi_if.rvfi_o[i].order; + assign rvfi_instr_if[i].rvfi_insn = rvfi_if.rvfi_o[i].insn; + assign rvfi_instr_if[i].rvfi_trap = rvfi_if.rvfi_o[i].trap; + assign rvfi_instr_if[i].rvfi_halt = rvfi_if.rvfi_o[i].halt; + assign rvfi_instr_if[i].rvfi_intr = rvfi_if.rvfi_o[i].intr; + assign rvfi_instr_if[i].rvfi_mode = rvfi_if.rvfi_o[i].mode; + assign rvfi_instr_if[i].rvfi_ixl = rvfi_if.rvfi_o[i].ixl; + assign rvfi_instr_if[i].rvfi_pc_rdata = rvfi_if.rvfi_o[i].pc_rdata; + assign rvfi_instr_if[i].rvfi_pc_wdata = rvfi_if.rvfi_o[i].pc_wdata; + assign rvfi_instr_if[i].rvfi_rs1_addr = rvfi_if.rvfi_o[i].rs1_addr; + assign rvfi_instr_if[i].rvfi_rs1_rdata = rvfi_if.rvfi_o[i].rs1_rdata; + assign rvfi_instr_if[i].rvfi_rs2_addr = rvfi_if.rvfi_o[i].rs2_addr; + assign rvfi_instr_if[i].rvfi_rs2_rdata = rvfi_if.rvfi_o[i].rs2_rdata; + assign rvfi_instr_if[i].rvfi_rd1_addr = rvfi_if.rvfi_o[i].rd_addr; + assign rvfi_instr_if[i].rvfi_rd1_wdata = rvfi_if.rvfi_o[i].rd_wdata; + assign rvfi_instr_if[i].rvfi_mem_addr = rvfi_if.rvfi_o[i].mem_addr; + assign rvfi_instr_if[i].rvfi_mem_rdata = rvfi_if.rvfi_o[i].mem_rdata; + assign rvfi_instr_if[i].rvfi_mem_rmask = rvfi_if.rvfi_o[i].mem_rmask; + assign rvfi_instr_if[i].rvfi_mem_wdata = rvfi_if.rvfi_o[i].mem_wdata; + assign rvfi_instr_if[i].rvfi_mem_wmask = rvfi_if.rvfi_o[i].mem_wmask; + end + + + for (genvar i = 0; i < uvme_cva6_pkg::RVFI_NRET; i++) begin + initial begin + uvm_config_db#(virtual uvma_rvfi_instr_if )::set(null,"*", $sformatf("instr_vif%0d", i), rvfi_instr_if[i]); + + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_marchid_vif%0d", i), rvfi_csr_if[i]); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mcountinhibit_vif%0d", i), rvfi_csr_if[i]); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mstatus_vif%0d", i), rvfi_csr_if[i]); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_ustatus_vif%0d", i), rvfi_csr_if[i]); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mstatush_vif%0d", i), rvfi_csr_if[i]); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_misa_vif%0d", i), rvfi_csr_if[i]); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mtvec_vif%0d", i), rvfi_csr_if[i]); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_utvec_vif%0d", i), rvfi_csr_if[i]); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mtval_vif%0d", i), rvfi_csr_if[i]); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_utval_vif%0d", i), rvfi_csr_if[i]); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mvendorid_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mscratch_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mepc_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_uepc_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mcause_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_ucause_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mip_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_uip_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mie_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_uie_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhartid_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mimpid_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_minstret_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_minstreth_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mcontext_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mcycle_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mcycleh_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_dcsr_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_dpc_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_dscratch0_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_dscratch1_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_uscratch_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_scontext_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_tselect_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_tdata1_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_tdata2_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_tdata3_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_tinfo_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_tcontrol_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmevent3_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmevent4_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmevent5_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmevent6_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmevent7_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmevent8_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmevent9_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmevent10_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmevent11_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmevent12_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmevent13_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmevent14_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmevent15_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmevent16_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmevent17_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmevent18_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmevent19_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmevent20_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmevent21_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmevent22_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmevent23_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmevent24_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmevent25_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmevent26_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmevent27_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmevent28_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmevent28_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmevent29_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmevent30_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmevent31_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter3_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter4_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter5_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter6_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter7_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter8_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter9_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter10_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter11_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter12_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter13_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter14_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter15_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter16_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter17_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter18_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter19_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter20_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter21_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter22_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter23_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter24_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter25_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter26_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter27_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter28_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter29_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter30_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter31_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter3h_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter4h_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter5h_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter6h_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter7h_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter8h_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter9h_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter10h_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter11h_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter12h_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter13h_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter14h_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter15h_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter16h_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter17h_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter18h_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter19h_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter20h_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter21h_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter22h_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter23h_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter24h_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter25h_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter26h_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter27h_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter28h_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter29h_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter30h_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter31h_vif%0d", i), .value(rvfi_csr_if[i])); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mconfigptr_vif%0d", i), .value(rvfi_csr_if[i])); + end + end + /** + * Test bench entry point. + */ + initial begin : test_bench_entry_point + + // Specify time format for simulation (units_number, precision_number, suffix_string, minimum_field_width) + $timeformat(-9, 3, " ns", 8); + + // Add interfaces handles to uvm_config_db + uvm_config_db#(virtual uvma_clknrst_if )::set(.cntxt(null), .inst_name("*.env.clknrst_agent"), .field_name("vif"), .value(clknrst_if)); + uvm_config_db#(virtual uvma_cvxif_intf )::set(.cntxt(null), .inst_name("*.env.cvxif_agent"), .field_name("vif"), .value(cvxif_if) ); + uvm_config_db#(virtual uvma_axi_intf )::set(.cntxt(null), .inst_name("*"), .field_name("axi_vif"), .value(axi_if)); + uvm_config_db#(virtual uvmt_axi_switch_intf )::set(.cntxt(null), .inst_name("*.env"), .field_name("axi_switch_vif"), .value(axi_switch_vif)); + uvm_config_db#(virtual uvmt_rvfi_if )::set(.cntxt(null), .inst_name("*"), .field_name("rvfi_vif"), .value(rvfi_if)); + uvm_config_db#(virtual uvme_cva6_core_cntrl_if)::set(.cntxt(null), .inst_name("*"), .field_name("core_cntrl_vif"), .value(core_cntrl_if)); + + // DUT and ENV parameters + uvm_config_db#(int)::set(.cntxt(null), .inst_name("*"), .field_name("ENV_PARAM_INSTR_ADDR_WIDTH"), .value(ENV_PARAM_INSTR_ADDR_WIDTH) ); + uvm_config_db#(int)::set(.cntxt(null), .inst_name("*"), .field_name("ENV_PARAM_INSTR_DATA_WIDTH"), .value(ENV_PARAM_INSTR_DATA_WIDTH) ); + uvm_config_db#(int)::set(.cntxt(null), .inst_name("*"), .field_name("ENV_PARAM_RAM_ADDR_WIDTH"), .value(ENV_PARAM_RAM_ADDR_WIDTH) ); + + // Run test + uvm_top.enable_print_topology = 0; // ENV coders enable this as a debug aid + uvm_top.finish_on_completion = 1; + uvm_top.run_test(); + end : test_bench_entry_point + + assign core_cntrl_if.clk = clknrst_if.clk; + + /** + * End-of-test summary printout. + */ + final begin: end_of_test + string summary_string; + uvm_report_server rs; + int err_count; + int warning_count; + int fatal_count; + static bit sim_finished = 0; + static int test_exit_code = 0; + + static string red = "\033[31m\033[1m"; + static string green = "\033[32m\033[1m"; + static string reset = "\033[0m"; + + rs = uvm_top.get_report_server(); + err_count = rs.get_severity_count(UVM_ERROR); + warning_count = rs.get_severity_count(UVM_WARNING); + fatal_count = rs.get_severity_count(UVM_FATAL); + + void'(uvm_config_db#(bit)::get(null, "", "sim_finished", sim_finished)); + void'(uvm_config_db#(int)::get(null, "", "test_exit_code", test_exit_code)); + + $display("\n%m: *** Test Summary ***\n"); + + if (sim_finished && (test_exit_code == 0) && (err_count == 0) && (fatal_count == 0)) begin + $display(" PPPPPPP AAAAAA SSSSSS SSSSSS EEEEEEEE DDDDDDD "); + $display(" PP PP AA AA SS SS SS SS EE DD DD "); + $display(" PP PP AA AA SS SS EE DD DD "); + $display(" PPPPPPP AAAAAAAA SSSSSS SSSSSS EEEEE DD DD "); + $display(" PP AA AA SS SS EE DD DD "); + $display(" PP AA AA SS SS SS SS EE DD DD "); + $display(" PP AA AA SSSSSS SSSSSS EEEEEEEE DDDDDDD "); + $display(" ----------------------------------------------------------"); + if (warning_count == 0) begin + $display(" SIMULATION PASSED "); + end + else begin + $display(" SIMULATION PASSED with WARNINGS "); + end + $display(" test exit code = %0d (0x%h)", test_exit_code, test_exit_code); + $display(" ----------------------------------------------------------"); + end + else begin + $display(" FFFFFFFF AAAAAA IIIIII LL EEEEEEEE DDDDDDD "); + $display(" FF AA AA II LL EE DD DD "); + $display(" FF AA AA II LL EE DD DD "); + $display(" FFFFF AAAAAAAA II LL EEEEE DD DD "); + $display(" FF AA AA II LL EE DD DD "); + $display(" FF AA AA II LL EE DD DD "); + $display(" FF AA AA IIIIII LLLLLLLL EEEEEEEE DDDDDDD "); + $display(" ----------------------------------------------------------"); + if (sim_finished == 0) begin + $display(" SIMULATION FAILED - ABORTED "); + end + else begin + $display(" SIMULATION FAILED "); + $display(" test exit code = %0d (0x%h)", test_exit_code, test_exit_code); + end + $display(" ----------------------------------------------------------"); + end + end + +endmodule : uvmt_cva6_tb +`default_nettype wire + +`endif // __UVMT_CVA6_TB_SV__ diff --git a/verif/tb/uvmt/uvmt_cva6_tb_ifs.sv b/verif/tb/uvmt/uvmt_cva6_tb_ifs.sv new file mode 100644 index 0000000000..5bfea4f335 --- /dev/null +++ b/verif/tb/uvmt/uvmt_cva6_tb_ifs.sv @@ -0,0 +1,41 @@ +// Copyright 2021 Thales DIS Design Services SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 + + +// This file specifies all interfaces used by the CVA6 test bench (uvmt_cva6_tb). + +`ifndef __UVMT_CVA6_TB_IFS_SV__ +`define __UVMT_CVA6_TB_IFS_SV__ + + +interface uvmt_rvfi_if #( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type rvfi_instr_t = logic +) ( + output rvfi_instr_t [CVA6Cfg.NrCommitPorts-1:0] rvfi_o, + output logic[31:0] tb_exit_o + ); + + import uvm_pkg::*; + + // TODO: X/Z checks + initial begin + end + +endinterface : uvmt_rvfi_if + + +`endif // __UVMT_CVA6_TB_IFS_SV__ diff --git a/verif/tb/uvmt/uvmt_cva6_tdefs.sv b/verif/tb/uvmt/uvmt_cva6_tdefs.sv new file mode 100644 index 0000000000..6592351287 --- /dev/null +++ b/verif/tb/uvmt/uvmt_cva6_tdefs.sv @@ -0,0 +1,36 @@ +// Copyright 2020 OpenHW Group +// Copyright 2020 Datum Technologies +// Copyright 2021 Thales DIS Design Services SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 + + +`ifndef __UVMT_CVA6_TDEFS_SV__ +`define __UVMT_CVA6_TDEFS_SV__ + + +/** + * Test Program Type. See the Verification Strategy for a discussion of this. + */ +typedef enum { + PREEXISTING_SELFCHECKING, + PREEXISTING_NOTSELFCHECKING, + GENERATED_SELFCHECKING, + GENERATED_NOTSELFCHECKING, + NO_TEST_PROGRAM + } test_program_type; + + +`endif // __UVMT_CVA6_TDEFS_SV__ diff --git a/verif/tests/custom/common/crt.S b/verif/tests/custom/common/crt.S new file mode 100644 index 0000000000..799b82e6c8 --- /dev/null +++ b/verif/tests/custom/common/crt.S @@ -0,0 +1,262 @@ +# See LICENSE for license details. + +#include "encoding.h" + +#if __riscv_xlen == 64 +# define LREG ld +# define SREG sd +# define REGBYTES 8 +#else +# define LREG lw +# define SREG sw +# define REGBYTES 4 +#endif + + .section ".text.init" + .globl _start +_start: + li x1, 0 + li x2, 0 + li x3, 0 + li x4, 0 + li x5, 0 + li x6, 0 + li x7, 0 + li x8, 0 + li x9, 0 + li x10,0 + li x11,0 + li x12,0 + li x13,0 + li x14,0 + li x15,0 + li x16,0 + li x17,0 + li x18,0 + li x19,0 + li x20,0 + li x21,0 + li x22,0 + li x23,0 + li x24,0 + li x25,0 + li x26,0 + li x27,0 + li x28,0 + li x29,0 + li x30,0 + li x31,0 + + # enable FPU and accelerator if present + li t0, MSTATUS_FS | MSTATUS_XS + csrs mstatus, t0 + + # make sure XLEN agrees with compilation choice + li t0, 1 + slli t0, t0, 31 +#if __riscv_xlen == 64 + bgez t0, 1f +#else + bltz t0, 1f +#endif +2: + li a0, 1 + sw a0, tohost, t0 + j 2b +1: + +#ifdef __riscv_flen + # initialize FPU if we have one + la t0, 1f + csrw mtvec, t0 + + fssr x0 + fmv.s.x f0, x0 + fmv.s.x f1, x0 + fmv.s.x f2, x0 + fmv.s.x f3, x0 + fmv.s.x f4, x0 + fmv.s.x f5, x0 + fmv.s.x f6, x0 + fmv.s.x f7, x0 + fmv.s.x f8, x0 + fmv.s.x f9, x0 + fmv.s.x f10,x0 + fmv.s.x f11,x0 + fmv.s.x f12,x0 + fmv.s.x f13,x0 + fmv.s.x f14,x0 + fmv.s.x f15,x0 + fmv.s.x f16,x0 + fmv.s.x f17,x0 + fmv.s.x f18,x0 + fmv.s.x f19,x0 + fmv.s.x f20,x0 + fmv.s.x f21,x0 + fmv.s.x f22,x0 + fmv.s.x f23,x0 + fmv.s.x f24,x0 + fmv.s.x f25,x0 + fmv.s.x f26,x0 + fmv.s.x f27,x0 + fmv.s.x f28,x0 + fmv.s.x f29,x0 + fmv.s.x f30,x0 + fmv.s.x f31,x0 +1: +#endif + + # initialize trap vector + la t0, trap_entry + csrw mtvec, t0 + + # initialize global pointer +.option push +.option norelax + la gp, __global_pointer$ +.option pop + + la tp, _end + 63 + and tp, tp, -64 + + # get core id + csrr a0, mhartid + # for now, assume only 1 core + li a1, 1 +1:bgeu a0, a1, 1b + + # give each core 128KB of stack + TLS +#define STKSHIFT 17 + add sp, a0, 1 + sll sp, sp, STKSHIFT + add sp, sp, tp + sll a2, a0, STKSHIFT + add tp, tp, a2 + + j _init + .size _start, . - _start + + .align 2 +trap_entry: + addi sp, sp, -272 + + SREG x1, 1*REGBYTES(sp) + SREG x2, 2*REGBYTES(sp) + SREG x3, 3*REGBYTES(sp) + SREG x4, 4*REGBYTES(sp) + SREG x5, 5*REGBYTES(sp) + SREG x6, 6*REGBYTES(sp) + SREG x7, 7*REGBYTES(sp) + SREG x8, 8*REGBYTES(sp) + SREG x9, 9*REGBYTES(sp) + SREG x10, 10*REGBYTES(sp) + SREG x11, 11*REGBYTES(sp) + SREG x12, 12*REGBYTES(sp) + SREG x13, 13*REGBYTES(sp) + SREG x14, 14*REGBYTES(sp) + SREG x15, 15*REGBYTES(sp) + SREG x16, 16*REGBYTES(sp) + SREG x17, 17*REGBYTES(sp) + SREG x18, 18*REGBYTES(sp) + SREG x19, 19*REGBYTES(sp) + SREG x20, 20*REGBYTES(sp) + SREG x21, 21*REGBYTES(sp) + SREG x22, 22*REGBYTES(sp) + SREG x23, 23*REGBYTES(sp) + SREG x24, 24*REGBYTES(sp) + SREG x25, 25*REGBYTES(sp) + SREG x26, 26*REGBYTES(sp) + SREG x27, 27*REGBYTES(sp) + SREG x28, 28*REGBYTES(sp) + SREG x29, 29*REGBYTES(sp) + SREG x30, 30*REGBYTES(sp) + SREG x31, 31*REGBYTES(sp) + + csrr a0, mcause + csrr a1, mepc + mv a2, sp + jal handle_trap + csrw mepc, a0 + + # Remain in M-mode after eret + li t0, MSTATUS_MPP + csrs mstatus, t0 + + LREG x1, 1*REGBYTES(sp) + LREG x2, 2*REGBYTES(sp) + LREG x3, 3*REGBYTES(sp) + LREG x4, 4*REGBYTES(sp) + LREG x5, 5*REGBYTES(sp) + LREG x6, 6*REGBYTES(sp) + LREG x7, 7*REGBYTES(sp) + LREG x8, 8*REGBYTES(sp) + LREG x9, 9*REGBYTES(sp) + LREG x10, 10*REGBYTES(sp) + LREG x11, 11*REGBYTES(sp) + LREG x12, 12*REGBYTES(sp) + LREG x13, 13*REGBYTES(sp) + LREG x14, 14*REGBYTES(sp) + LREG x15, 15*REGBYTES(sp) + LREG x16, 16*REGBYTES(sp) + LREG x17, 17*REGBYTES(sp) + LREG x18, 18*REGBYTES(sp) + LREG x19, 19*REGBYTES(sp) + LREG x20, 20*REGBYTES(sp) + LREG x21, 21*REGBYTES(sp) + LREG x22, 22*REGBYTES(sp) + LREG x23, 23*REGBYTES(sp) + LREG x24, 24*REGBYTES(sp) + LREG x25, 25*REGBYTES(sp) + LREG x26, 26*REGBYTES(sp) + LREG x27, 27*REGBYTES(sp) + LREG x28, 28*REGBYTES(sp) + LREG x29, 29*REGBYTES(sp) + LREG x30, 30*REGBYTES(sp) + LREG x31, 31*REGBYTES(sp) + + addi sp, sp, 272 + mret + + // Default definition of handle_trap: Exit with code 0x7ffffff0. + .weak handle_trap + .type handle_trap, @function +handle_trap: + li a0, -32 + j _exit + .size handle_trap, . - handle_trap + + // Default, overrideable definition of _init: + // Call 'main' and jump to '_exit' which never returns. + .weak _init + .type _init, @function +_init: + jal main + j _exit + .size _init, . - _init + + // Default, overrideable definition of 'exit': + // Jump to '_exit' low-level termination function. + .weak exit + .type exit, @function +exit: + j _exit + .size exit, . - exit + + // Minimal low-level exit function. + .global _exit +_exit: + sll a0, a0, 1 # Set up exit code: shift a0 left by 1 + add a0, a0, 1 # and set bit 0. + sw a0, tohost, t5 # Store bits [31:0] of a0 into variable tohost + nop # Leave one cycle of slack before entering endless loop +1: + j 1b; # Wait indefinitely (until the env terminates the simulation) + .size _exit, . - _exit + +.section ".tohost","aw",@progbits +.align 6 +.globl tohost +tohost: .dword 0 +.align 6 +.globl fromhost +fromhost: .dword 0 diff --git a/verif/tests/custom/common/cva6_csr_access_test_32.S b/verif/tests/custom/common/cva6_csr_access_test_32.S new file mode 100644 index 0000000000..1fd207da46 --- /dev/null +++ b/verif/tests/custom/common/cva6_csr_access_test_32.S @@ -0,0 +1,5270 @@ +.macro init +.endm +.section .text.init +.globl _start +.option norvc +_start: + # CSR_DCSR + li x6, 0xa5a5a5a5 + csrrw x12, 1968, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 1968, x6 + li x6, 0x0000a584 + bne x6, x12, csr_fail + li x6, 0xf98bef6d + csrrw x12, 1968, x6 + li x6, 0x00001a52 + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 1968, x6 + li x6, 0x0000af44 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 1968, x6 + li x6, 0x0000afc4 + bne x6, x12, csr_fail + li x6, 0x703ef472 + csrrs x12, 1968, x6 + li x6, 0x0000bfd6 + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 1968, x6 + li x6, 0x0000bfd6 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 1968, x6 + li x6, 0x00001a52 + bne x6, x12, csr_fail + li x6, 0xe1a6b6eb + csrrc x12, 1968, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 1968, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 1968, 0b11010 + li x6, 0x00000004 + bne x6, x12, csr_fail + csrrwi x12, 1968, 0b11000 + li x6, 0x00000012 + bne x6, x12, csr_fail + csrrsi x12, 1968, 0b00101 + li x6, 0x00000010 + bne x6, x12, csr_fail + csrrsi x12, 1968, 0b11010 + li x6, 0x00000014 + bne x6, x12, csr_fail + csrrsi x12, 1968, 0b11101 + li x6, 0x00000016 + bne x6, x12, csr_fail + csrrci x12, 1968, 0b00101 + li x6, 0x00000016 + bne x6, x12, csr_fail + csrrci x12, 1968, 0b11010 + li x6, 0x00000012 + bne x6, x12, csr_fail + csrrci x12, 1968, 0b11000 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_DPC + li x6, 0xa5a5a5a5 + csrrw x12, 1969, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 1969, x6 + li x6, 0xa5a5a5a5 + bne x6, x12, csr_fail + li x6, 0xce6fc9c3 + csrrw x12, 1969, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 1969, x6 + li x6, 0xce6fc9c3 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 1969, x6 + li x6, 0xefefede7 + bne x6, x12, csr_fail + li x6, 0xd2e4b654 + csrrs x12, 1969, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 1969, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 1969, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xde38cc00 + csrrc x12, 1969, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 1969, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 1969, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrwi x12, 1969, 0b00100 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 1969, 0b00101 + li x6, 0x00000004 + bne x6, x12, csr_fail + csrrsi x12, 1969, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrsi x12, 1969, 0b10101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 1969, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 1969, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 1969, 0b01101 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_DSCRATCH0 + li x6, 0xa5a5a5a5 + csrrw x12, 1970, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 1970, x6 + li x6, 0xa5a5a5a5 + bne x6, x12, csr_fail + li x6, 0xb333acc1 + csrrw x12, 1970, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 1970, x6 + li x6, 0xb333acc1 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 1970, x6 + li x6, 0xb7b7ade5 + bne x6, x12, csr_fail + li x6, 0xa1233498 + csrrs x12, 1970, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 1970, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 1970, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0x888d52bc + csrrc x12, 1970, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 1970, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 1970, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrwi x12, 1970, 0b10000 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 1970, 0b00101 + li x6, 0x00000010 + bne x6, x12, csr_fail + csrrsi x12, 1970, 0b11010 + li x6, 0x00000015 + bne x6, x12, csr_fail + csrrsi x12, 1970, 0b00110 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 1970, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 1970, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 1970, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_DSCRATCH1 + li x6, 0xa5a5a5a5 + csrrw x12, 1971, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 1971, x6 + li x6, 0xa5a5a5a5 + bne x6, x12, csr_fail + li x6, 0xb1a692a8 + csrrw x12, 1971, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 1971, x6 + li x6, 0xb1a692a8 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 1971, x6 + li x6, 0xb5a7b7ad + bne x6, x12, csr_fail + li x6, 0x01944b0c + csrrs x12, 1971, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 1971, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 1971, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xbe30d276 + csrrc x12, 1971, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 1971, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 1971, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrwi x12, 1971, 0b10000 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 1971, 0b00101 + li x6, 0x00000010 + bne x6, x12, csr_fail + csrrsi x12, 1971, 0b11010 + li x6, 0x00000015 + bne x6, x12, csr_fail + csrrsi x12, 1971, 0b01011 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 1971, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 1971, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 1971, 0b10000 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_SSTATUS + li x6, 0xa5a5a5a5 + csrrw x12, 256, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 256, x6 + li x6, 0x8005a121 + bne x6, x12, csr_fail + li x6, 0xc51dc272 + csrrw x12, 256, x6 + li x6, 0x00084012 + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 256, x6 + li x6, 0x800dc032 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 256, x6 + li x6, 0x800de133 + bne x6, x12, csr_fail + li x6, 0x4f5f8ca9 + csrrs x12, 256, x6 + li x6, 0x800de133 + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 256, x6 + li x6, 0x800de133 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 256, x6 + li x6, 0x00084012 + bne x6, x12, csr_fail + li x6, 0x251d0a7d + csrrc x12, 256, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 256, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 256, 0b11010 + li x6, 0x00000001 + bne x6, x12, csr_fail + csrrwi x12, 256, 0b01100 + li x6, 0x00000012 + bne x6, x12, csr_fail + csrrsi x12, 256, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrsi x12, 256, 0b11010 + li x6, 0x00000001 + bne x6, x12, csr_fail + csrrsi x12, 256, 0b01001 + li x6, 0x00000013 + bne x6, x12, csr_fail + csrrci x12, 256, 0b00101 + li x6, 0x00000013 + bne x6, x12, csr_fail + csrrci x12, 256, 0b11010 + li x6, 0x00000012 + bne x6, x12, csr_fail + csrrci x12, 256, 0b00111 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_SIE + li x6, 0xa5a5a5a5 + csrrw x12, 260, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 260, x6 + li x6, 0xa5a5a5a5 + bne x6, x12, csr_fail + li x6, 0x7e799466 + csrrw x12, 260, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 260, x6 + li x6, 0x7e799466 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 260, x6 + li x6, 0xfffdb5e7 + bne x6, x12, csr_fail + li x6, 0x0d0a2c4a + csrrs x12, 260, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 260, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 260, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xfc02e64e + csrrc x12, 260, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 260, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 260, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrwi x12, 260, 0b11101 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 260, 0b00101 + li x6, 0x0000001d + bne x6, x12, csr_fail + csrrsi x12, 260, 0b11010 + li x6, 0x0000001d + bne x6, x12, csr_fail + csrrsi x12, 260, 0b00100 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 260, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 260, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 260, 0b10111 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_SIP + li x6, 0xa5a5a5a5 + csrrw x12, 324, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 324, x6 + li x6, 0xa5a5a5a5 + bne x6, x12, csr_fail + li x6, 0x150f7660 + csrrw x12, 324, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 324, x6 + li x6, 0x150f7660 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 324, x6 + li x6, 0xb5aff7e5 + bne x6, x12, csr_fail + li x6, 0xb23ff77b + csrrs x12, 324, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 324, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 324, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xe94e2de8 + csrrc x12, 324, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 324, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 324, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrwi x12, 324, 0b10101 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 324, 0b00101 + li x6, 0x00000015 + bne x6, x12, csr_fail + csrrsi x12, 324, 0b11010 + li x6, 0x00000015 + bne x6, x12, csr_fail + csrrsi x12, 324, 0b10110 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 324, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 324, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 324, 0b11101 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_STVEC + li x6, 0xa5a5a5a5 + csrrw x12, 261, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 261, x6 + li x6, 0xa5a5a5a5 + bne x6, x12, csr_fail + li x6, 0x360c495b + csrrw x12, 261, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 261, x6 + li x6, 0x360c495b + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 261, x6 + li x6, 0xb7adedff + bne x6, x12, csr_fail + li x6, 0xc2abbf8d + csrrs x12, 261, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 261, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 261, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0x7ffb7b05 + csrrc x12, 261, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 261, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 261, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrwi x12, 261, 0b01010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 261, 0b00101 + li x6, 0x0000000a + bne x6, x12, csr_fail + csrrsi x12, 261, 0b11010 + li x6, 0x0000000f + bne x6, x12, csr_fail + csrrsi x12, 261, 0b11000 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 261, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 261, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 261, 0b00110 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_SCOUNTEREN + li x6, 0xa5a5a5a5 + csrrw x12, 262, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 262, x6 + li x6, 0xa5a5a5a5 + bne x6, x12, csr_fail + li x6, 0x8d0cf09d + csrrw x12, 262, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 262, x6 + li x6, 0x8d0cf09d + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 262, x6 + li x6, 0xadadf5bd + bne x6, x12, csr_fail + li x6, 0x2d88a314 + csrrs x12, 262, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 262, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 262, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xba9207f2 + csrrc x12, 262, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 262, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 262, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrwi x12, 262, 0b11101 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 262, 0b00101 + li x6, 0x0000001d + bne x6, x12, csr_fail + csrrsi x12, 262, 0b11010 + li x6, 0x0000001d + bne x6, x12, csr_fail + csrrsi x12, 262, 0b11100 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 262, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 262, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 262, 0b00011 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_SSCRATCH + li x6, 0xa5a5a5a5 + csrrw x12, 320, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 320, x6 + li x6, 0xa5a5a5a5 + bne x6, x12, csr_fail + li x6, 0x67087ba3 + csrrw x12, 320, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 320, x6 + li x6, 0x67087ba3 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 320, x6 + li x6, 0xe7adffa7 + bne x6, x12, csr_fail + li x6, 0xa1f6b125 + csrrs x12, 320, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 320, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 320, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0x9872e7cf + csrrc x12, 320, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 320, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 320, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrwi x12, 320, 0b00110 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 320, 0b00101 + li x6, 0x00000006 + bne x6, x12, csr_fail + csrrsi x12, 320, 0b11010 + li x6, 0x00000007 + bne x6, x12, csr_fail + csrrsi x12, 320, 0b00100 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 320, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 320, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 320, 0b10101 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_SEPC + li x6, 0xa5a5a5a5 + csrrw x12, 321, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 321, x6 + li x6, 0xa5a5a5a5 + bne x6, x12, csr_fail + li x6, 0x6e57e7a7 + csrrw x12, 321, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 321, x6 + li x6, 0x6e57e7a7 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 321, x6 + li x6, 0xeff7e7a7 + bne x6, x12, csr_fail + li x6, 0xb7a9644a + csrrs x12, 321, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 321, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 321, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0x16d18921 + csrrc x12, 321, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 321, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 321, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrwi x12, 321, 0b10110 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 321, 0b00101 + li x6, 0x00000016 + bne x6, x12, csr_fail + csrrsi x12, 321, 0b11010 + li x6, 0x00000017 + bne x6, x12, csr_fail + csrrsi x12, 321, 0b00011 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 321, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 321, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 321, 0b10010 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_SCAUSE + li x6, 0xa5a5a5a5 + csrrw x12, 322, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 322, x6 + li x6, 0xa5a5a5a5 + bne x6, x12, csr_fail + li x6, 0x23305176 + csrrw x12, 322, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 322, x6 + li x6, 0x23305176 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 322, x6 + li x6, 0xa7b5f5f7 + bne x6, x12, csr_fail + li x6, 0x2be07645 + csrrs x12, 322, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 322, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 322, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0x4ae3926e + csrrc x12, 322, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 322, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 322, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrwi x12, 322, 0b10100 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 322, 0b00101 + li x6, 0x00000014 + bne x6, x12, csr_fail + csrrsi x12, 322, 0b11010 + li x6, 0x00000015 + bne x6, x12, csr_fail + csrrsi x12, 322, 0b11010 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 322, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 322, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 322, 0b01101 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_STVAL + li x6, 0xa5a5a5a5 + csrrw x12, 323, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 323, x6 + li x6, 0xa5a5a5a5 + bne x6, x12, csr_fail + li x6, 0xb75ec6a1 + csrrw x12, 323, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 323, x6 + li x6, 0xb75ec6a1 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 323, x6 + li x6, 0xb7ffe7a5 + bne x6, x12, csr_fail + li x6, 0xf87ea7d7 + csrrs x12, 323, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 323, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 323, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xfefe4b1f + csrrc x12, 323, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 323, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 323, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrwi x12, 323, 0b01111 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 323, 0b00101 + li x6, 0x0000000f + bne x6, x12, csr_fail + csrrsi x12, 323, 0b11010 + li x6, 0x0000000f + bne x6, x12, csr_fail + csrrsi x12, 323, 0b01110 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 323, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 323, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 323, 0b00010 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_SATP + li x6, 0xa5a5a5a5 + csrrw x12, 384, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 384, x6 + li x6, 0xa5a5a5a5 + bne x6, x12, csr_fail + li x6, 0x1fc829c6 + csrrw x12, 384, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 384, x6 + li x6, 0x1fc829c6 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 384, x6 + li x6, 0xbfedade7 + bne x6, x12, csr_fail + li x6, 0xb74e3d9b + csrrs x12, 384, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 384, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 384, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0x2de43e33 + csrrc x12, 384, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 384, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 384, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrwi x12, 384, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 384, 0b00101 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 384, 0b11010 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrsi x12, 384, 0b10110 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 384, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 384, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 384, 0b00000 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_MSTATUS + li x6, 0xa5a5a5a5 + csrrw x12, 768, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 768, x6 + li x6, 0x8025a1a1 + bne x6, x12, csr_fail + li x6, 0xd99beb37 + csrrw x12, 768, x6 + li x6, 0x005a581a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 768, x6 + li x6, 0x801be933 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 768, x6 + li x6, 0x803fe9b3 + bne x6, x12, csr_fail + li x6, 0xbc7df450 + csrrs x12, 768, x6 + li x6, 0x807ff9bb + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 768, x6 + li x6, 0x807ff9bb + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 768, x6 + li x6, 0x005a581a + bne x6, x12, csr_fail + li x6, 0x2dcec385 + csrrc x12, 768, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 768, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 768, 0b11010 + li x6, 0x00000001 + bne x6, x12, csr_fail + csrrwi x12, 768, 0b10001 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 768, 0b00101 + li x6, 0x00000011 + bne x6, x12, csr_fail + csrrsi x12, 768, 0b11010 + li x6, 0x00000011 + bne x6, x12, csr_fail + csrrsi x12, 768, 0b10001 + li x6, 0x0000001b + bne x6, x12, csr_fail + csrrci x12, 768, 0b00101 + li x6, 0x0000001b + bne x6, x12, csr_fail + csrrci x12, 768, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 768, 0b10111 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_MISA + li x6, 0xa5a5a5a5 + csrrw x12, 769, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 769, x6 + li x6, 0x81a5a5a5 + bne x6, x12, csr_fail + li x6, 0xc6f9f09d + csrrw x12, 769, x6 + li x6, 0x425a5a5a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 769, x6 + li x6, 0xc2f9f09d + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 769, x6 + li x6, 0xc3fdf5bd + bne x6, x12, csr_fail + li x6, 0x941944c6 + csrrs x12, 769, x6 + li x6, 0xc3ffffff + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 769, x6 + li x6, 0xc3ffffff + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 769, x6 + li x6, 0x425a5a5a + bne x6, x12, csr_fail + li x6, 0x549e01a8 + csrrc x12, 769, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 769, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 769, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrwi x12, 769, 0b01100 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 769, 0b00101 + li x6, 0x0000000c + bne x6, x12, csr_fail + csrrsi x12, 769, 0b11010 + li x6, 0x0000000d + bne x6, x12, csr_fail + csrrsi x12, 769, 0b11100 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 769, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 769, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 769, 0b00000 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_MEDELEG + li x6, 0xa5a5a5a5 + csrrw x12, 770, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 770, x6 + li x6, 0xa5a5a5a5 + bne x6, x12, csr_fail + li x6, 0xd4223b1a + csrrw x12, 770, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 770, x6 + li x6, 0xd4223b1a + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 770, x6 + li x6, 0xf5a7bfbf + bne x6, x12, csr_fail + li x6, 0x8ee01d65 + csrrs x12, 770, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 770, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 770, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xaa8788b6 + csrrc x12, 770, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 770, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 770, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrwi x12, 770, 0b00101 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 770, 0b00101 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrsi x12, 770, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrsi x12, 770, 0b10100 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 770, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 770, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 770, 0b10001 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_MIDELEG + li x6, 0xa5a5a5a5 + csrrw x12, 771, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 771, x6 + li x6, 0xa5a5a5a5 + bne x6, x12, csr_fail + li x6, 0x4c15bb8d + csrrw x12, 771, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 771, x6 + li x6, 0x4c15bb8d + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 771, x6 + li x6, 0xedb5bfad + bne x6, x12, csr_fail + li x6, 0xb2a095a2 + csrrs x12, 771, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 771, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 771, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0x45e27139 + csrrc x12, 771, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 771, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 771, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrwi x12, 771, 0b00001 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 771, 0b00101 + li x6, 0x00000001 + bne x6, x12, csr_fail + csrrsi x12, 771, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrsi x12, 771, 0b01010 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 771, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 771, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 771, 0b10001 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_MIE + li x6, 0xa5a5a5a5 + csrrw x12, 772, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 772, x6 + li x6, 0x000001a1 + bne x6, x12, csr_fail + li x6, 0x162ef63a + csrrw x12, 772, x6 + li x6, 0x00000a1a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 772, x6 + li x6, 0x0000023a + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 772, x6 + li x6, 0x000003bb + bne x6, x12, csr_fail + li x6, 0x6c5fb732 + csrrs x12, 772, x6 + li x6, 0x00000bbb + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 772, x6 + li x6, 0x00000bbb + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 772, x6 + li x6, 0x00000a1a + bne x6, x12, csr_fail + li x6, 0xe60ac531 + csrrc x12, 772, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 772, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 772, 0b11010 + li x6, 0x00000001 + bne x6, x12, csr_fail + csrrwi x12, 772, 0b01100 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 772, 0b00101 + li x6, 0x00000008 + bne x6, x12, csr_fail + csrrsi x12, 772, 0b11010 + li x6, 0x00000009 + bne x6, x12, csr_fail + csrrsi x12, 772, 0b00010 + li x6, 0x0000001b + bne x6, x12, csr_fail + csrrci x12, 772, 0b00101 + li x6, 0x0000001b + bne x6, x12, csr_fail + csrrci x12, 772, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 772, 0b01100 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_MTVEC + li x6, 0xa5a5a5a5 + csrrw x12, 773, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 773, x6 + li x6, 0xa5a5a5a5 + bne x6, x12, csr_fail + li x6, 0x8667081c + csrrw x12, 773, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 773, x6 + li x6, 0x8667081c + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 773, x6 + li x6, 0xa7e7adbd + bne x6, x12, csr_fail + li x6, 0x043d9536 + csrrs x12, 773, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 773, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 773, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0x31d552e8 + csrrc x12, 773, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 773, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 773, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrwi x12, 773, 0b00011 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 773, 0b00101 + li x6, 0x00000003 + bne x6, x12, csr_fail + csrrsi x12, 773, 0b11010 + li x6, 0x00000007 + bne x6, x12, csr_fail + csrrsi x12, 773, 0b11000 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 773, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 773, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 773, 0b00000 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_MCOUNTEREN + li x6, 0xa5a5a5a5 + csrrw x12, 774, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 774, x6 + li x6, 0xa5a5a5a5 + bne x6, x12, csr_fail + li x6, 0x74af0220 + csrrw x12, 774, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 774, x6 + li x6, 0x74af0220 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 774, x6 + li x6, 0xf5afa7a5 + bne x6, x12, csr_fail + li x6, 0x03fbb4a8 + csrrs x12, 774, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 774, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 774, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0x3df8f82e + csrrc x12, 774, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 774, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 774, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrwi x12, 774, 0b11011 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 774, 0b00101 + li x6, 0x0000001b + bne x6, x12, csr_fail + csrrsi x12, 774, 0b11010 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrsi x12, 774, 0b11010 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 774, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 774, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 774, 0b00010 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_MSCRATCH + li x6, 0xa5a5a5a5 + csrrw x12, 832, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 832, x6 + li x6, 0xa5a5a5a5 + bne x6, x12, csr_fail + li x6, 0x130859c9 + csrrw x12, 832, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 832, x6 + li x6, 0x130859c9 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 832, x6 + li x6, 0xb7adfded + bne x6, x12, csr_fail + li x6, 0x4821c2b9 + csrrs x12, 832, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 832, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 832, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0x29c2a6d3 + csrrc x12, 832, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 832, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 832, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrwi x12, 832, 0b01010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 832, 0b00101 + li x6, 0x0000000a + bne x6, x12, csr_fail + csrrsi x12, 832, 0b11010 + li x6, 0x0000000f + bne x6, x12, csr_fail + csrrsi x12, 832, 0b10001 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 832, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 832, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 832, 0b11101 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_MEPC + li x6, 0xa5a5a5a5 + csrrw x12, 833, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 833, x6 + li x6, 0xa5a5a5a5 + bne x6, x12, csr_fail + li x6, 0xfc5e0c24 + csrrw x12, 833, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 833, x6 + li x6, 0xfc5e0c24 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 833, x6 + li x6, 0xfdffada5 + bne x6, x12, csr_fail + li x6, 0xb15c3cf9 + csrrs x12, 833, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 833, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 833, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xc74349c5 + csrrc x12, 833, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 833, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 833, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrwi x12, 833, 0b10001 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 833, 0b00101 + li x6, 0x00000011 + bne x6, x12, csr_fail + csrrsi x12, 833, 0b11010 + li x6, 0x00000015 + bne x6, x12, csr_fail + csrrsi x12, 833, 0b01001 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 833, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 833, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 833, 0b00010 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_MCAUSE + li x6, 0xa5a5a5a5 + csrrw x12, 834, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 834, x6 + li x6, 0xa5a5a5a5 + bne x6, x12, csr_fail + li x6, 0x9a9f401d + csrrw x12, 834, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 834, x6 + li x6, 0x9a9f401d + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 834, x6 + li x6, 0xbfbfe5bd + bne x6, x12, csr_fail + li x6, 0xd3f532ca + csrrs x12, 834, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 834, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 834, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xf266aa31 + csrrc x12, 834, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 834, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 834, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrwi x12, 834, 0b01111 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 834, 0b00101 + li x6, 0x0000000f + bne x6, x12, csr_fail + csrrsi x12, 834, 0b11010 + li x6, 0x0000000f + bne x6, x12, csr_fail + csrrsi x12, 834, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 834, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 834, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 834, 0b10111 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_MTVAL + li x6, 0xa5a5a5a5 + csrrw x12, 835, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 835, x6 + li x6, 0xa5a5a5a5 + bne x6, x12, csr_fail + li x6, 0x473b8d42 + csrrw x12, 835, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 835, x6 + li x6, 0x473b8d42 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 835, x6 + li x6, 0xe7bfade7 + bne x6, x12, csr_fail + li x6, 0x96d3322a + csrrs x12, 835, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 835, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 835, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0x3ab5e9f0 + csrrc x12, 835, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 835, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 835, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrwi x12, 835, 0b11111 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 835, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrsi x12, 835, 0b11010 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrsi x12, 835, 0b01001 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 835, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 835, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 835, 0b00001 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_MIP + li x6, 0xa5a5a5a5 + csrrw x12, 836, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 836, x6 + li x6, 0x00000121 + bne x6, x12, csr_fail + li x6, 0x173cc177 + csrrw x12, 836, x6 + li x6, 0x00000212 + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 836, x6 + li x6, 0x00000133 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 836, x6 + li x6, 0x00000133 + bne x6, x12, csr_fail + li x6, 0xdaa90bd0 + csrrs x12, 836, x6 + li x6, 0x00000333 + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 836, x6 + li x6, 0x00000333 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 836, x6 + li x6, 0x00000212 + bne x6, x12, csr_fail + li x6, 0x602b8a98 + csrrc x12, 836, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 836, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 836, 0b11010 + li x6, 0x00000001 + bne x6, x12, csr_fail + csrrwi x12, 836, 0b11101 + li x6, 0x00000012 + bne x6, x12, csr_fail + csrrsi x12, 836, 0b00101 + li x6, 0x00000011 + bne x6, x12, csr_fail + csrrsi x12, 836, 0b11010 + li x6, 0x00000011 + bne x6, x12, csr_fail + csrrsi x12, 836, 0b11110 + li x6, 0x00000013 + bne x6, x12, csr_fail + csrrci x12, 836, 0b00101 + li x6, 0x00000013 + bne x6, x12, csr_fail + csrrci x12, 836, 0b11010 + li x6, 0x00000012 + bne x6, x12, csr_fail + csrrci x12, 836, 0b01110 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_MVENDORID + li x6, 0xa5a5a5a5 + csrrw x12, 3857, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 3857, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x58980db4 + csrrw x12, 3857, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 3857, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 3857, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x7b9c4992 + csrrs x12, 3857, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 3857, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 3857, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0xa8ae1dce + csrrc x12, 3857, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 3857, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 3857, 0b11010 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 3857, 0b01000 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrsi x12, 3857, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrsi x12, 3857, 0b11010 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrsi x12, 3857, 0b01101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrci x12, 3857, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrci x12, 3857, 0b11010 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrci x12, 3857, 0b11001 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_MARCHID + li x6, 0xa5a5a5a5 + csrrw x12, 3858, x6 + li x6, 0x00000003 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 3858, x6 + li x6, 0x00000003 + bne x6, x12, csr_fail + li x6, 0x26a47a6b + csrrw x12, 3858, x6 + li x6, 0x00000003 + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 3858, x6 + li x6, 0x00000003 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 3858, x6 + li x6, 0x00000003 + bne x6, x12, csr_fail + li x6, 0x50ab9e88 + csrrs x12, 3858, x6 + li x6, 0x00000003 + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 3858, x6 + li x6, 0x00000003 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 3858, x6 + li x6, 0x00000003 + bne x6, x12, csr_fail + li x6, 0xe02f62d0 + csrrc x12, 3858, x6 + li x6, 0x00000003 + bne x6, x12, csr_fail + csrrwi x12, 3858, 0b00101 + li x6, 0x00000003 + bne x6, x12, csr_fail + csrrwi x12, 3858, 0b11010 + li x6, 0x00000003 + bne x6, x12, csr_fail + csrrwi x12, 3858, 0b01010 + li x6, 0x00000003 + bne x6, x12, csr_fail + csrrsi x12, 3858, 0b00101 + li x6, 0x00000003 + bne x6, x12, csr_fail + csrrsi x12, 3858, 0b11010 + li x6, 0x00000003 + bne x6, x12, csr_fail + csrrsi x12, 3858, 0b01010 + li x6, 0x00000003 + bne x6, x12, csr_fail + csrrci x12, 3858, 0b00101 + li x6, 0x00000003 + bne x6, x12, csr_fail + csrrci x12, 3858, 0b11010 + li x6, 0x00000003 + bne x6, x12, csr_fail + csrrci x12, 3858, 0b00000 + li x6, 0x00000003 + bne x6, x12, csr_fail + # CSR_MIMPID + li x6, 0xa5a5a5a5 + csrrw x12, 3859, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 3859, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0xaa338040 + csrrw x12, 3859, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 3859, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 3859, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0xbc407b85 + csrrs x12, 3859, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 3859, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 3859, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0xfe84b59d + csrrc x12, 3859, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 3859, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 3859, 0b11010 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 3859, 0b01111 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrsi x12, 3859, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrsi x12, 3859, 0b11010 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrsi x12, 3859, 0b10011 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrci x12, 3859, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrci x12, 3859, 0b11010 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrci x12, 3859, 0b01000 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_MHARTID + li x6, 0xa5a5a5a5 + csrrw x12, 3860, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 3860, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x7920b2bb + csrrw x12, 3860, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 3860, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 3860, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0xf0e7a5dd + csrrs x12, 3860, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 3860, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 3860, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x467b7f27 + csrrc x12, 3860, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 3860, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 3860, 0b11010 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 3860, 0b01101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrsi x12, 3860, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrsi x12, 3860, 0b11010 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrsi x12, 3860, 0b00111 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrci x12, 3860, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrci x12, 3860, 0b11010 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrci x12, 3860, 0b00000 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_MCYCLE + li x6, 0xa5a5a5a5 + csrrw x12, 2816, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 2816, x6 + li x6, 0xa5a5a5a5 + bne x6, x12, csr_fail + li x6, 0x92fe9536 + csrrw x12, 2816, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 2816, x6 + li x6, 0x92fe9536 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 2816, x6 + li x6, 0xb7ffb5b7 + bne x6, x12, csr_fail + li x6, 0x0702a58a + csrrs x12, 2816, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 2816, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 2816, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xa580e679 + csrrc x12, 2816, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 2816, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 2816, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrwi x12, 2816, 0b00010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 2816, 0b00101 + li x6, 0x00000002 + bne x6, x12, csr_fail + csrrsi x12, 2816, 0b11010 + li x6, 0x00000007 + bne x6, x12, csr_fail + csrrsi x12, 2816, 0b01011 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 2816, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 2816, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 2816, 0b01001 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_MCYCLE_H + li x6, 0xa5a5a5a5 + csrrw x12, 2944, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 2944, x6 + li x6, 0xa5a5a5a5 + bne x6, x12, csr_fail + li x6, 0x2a573677 + csrrw x12, 2944, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 2944, x6 + li x6, 0x2a573677 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 2944, x6 + li x6, 0xaff7b7f7 + bne x6, x12, csr_fail + li x6, 0x6091ef93 + csrrs x12, 2944, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 2944, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 2944, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0x9cd2fd96 + csrrc x12, 2944, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 2944, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 2944, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrwi x12, 2944, 0b01100 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 2944, 0b00101 + li x6, 0x0000000c + bne x6, x12, csr_fail + csrrsi x12, 2944, 0b11010 + li x6, 0x0000000d + bne x6, x12, csr_fail + csrrsi x12, 2944, 0b10010 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 2944, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 2944, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 2944, 0b01101 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_MINSTRET + li x6, 0xa5a5a5a5 + csrrw x12, 2818, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 2818, x6 + li x6, 0xa5a5a5a5 + bne x6, x12, csr_fail + li x6, 0xb6989928 + csrrw x12, 2818, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 2818, x6 + li x6, 0xb6989928 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 2818, x6 + li x6, 0xb7bdbdad + bne x6, x12, csr_fail + li x6, 0xe10009d9 + csrrs x12, 2818, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 2818, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 2818, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0x4a7dcaa2 + csrrc x12, 2818, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 2818, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 2818, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrwi x12, 2818, 0b01001 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 2818, 0b00101 + li x6, 0x00000009 + bne x6, x12, csr_fail + csrrsi x12, 2818, 0b11010 + li x6, 0x0000000d + bne x6, x12, csr_fail + csrrsi x12, 2818, 0b01111 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 2818, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 2818, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 2818, 0b11111 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_MINSTRET_H + li x6, 0xa5a5a5a5 + csrrw x12, 2946, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 2946, x6 + li x6, 0xa5a5a5a5 + bne x6, x12, csr_fail + li x6, 0xa1436b7d + csrrw x12, 2946, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 2946, x6 + li x6, 0xa1436b7d + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 2946, x6 + li x6, 0xa5e7effd + bne x6, x12, csr_fail + li x6, 0x88d4434a + csrrs x12, 2946, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 2946, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 2946, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0x7f48f878 + csrrc x12, 2946, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 2946, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 2946, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrwi x12, 2946, 0b10101 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 2946, 0b00101 + li x6, 0x00000015 + bne x6, x12, csr_fail + csrrsi x12, 2946, 0b11010 + li x6, 0x00000015 + bne x6, x12, csr_fail + csrrsi x12, 2946, 0b10100 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 2946, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 2946, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 2946, 0b10000 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_GPC1 + li x6, 0xa5a5a5a5 + csrrw x12, 2819, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 2819, x6 + li x6, 0xa5a5a5a5 + bne x6, x12, csr_fail + li x6, 0xf29a78cc + csrrw x12, 2819, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 2819, x6 + li x6, 0xf29a78cc + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 2819, x6 + li x6, 0xf7bffded + bne x6, x12, csr_fail + li x6, 0xad9fd44b + csrrs x12, 2819, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 2819, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 2819, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0x768bed2b + csrrc x12, 2819, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 2819, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 2819, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrwi x12, 2819, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 2819, 0b00101 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 2819, 0b11010 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrsi x12, 2819, 0b01100 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 2819, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 2819, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 2819, 0b01101 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_GPC1H + li x6, 0xa5a5a5a5 + csrrw x12, 2947, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 2947, x6 + li x6, 0xa5a5a5a5 + bne x6, x12, csr_fail + li x6, 0xbebb8424 + csrrw x12, 2947, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 2947, x6 + li x6, 0xbebb8424 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 2947, x6 + li x6, 0xbfbfa5a5 + bne x6, x12, csr_fail + li x6, 0x45577ba1 + csrrs x12, 2947, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 2947, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 2947, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xd268996a + csrrc x12, 2947, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 2947, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 2947, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrwi x12, 2947, 0b00100 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 2947, 0b00101 + li x6, 0x00000004 + bne x6, x12, csr_fail + csrrsi x12, 2947, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrsi x12, 2947, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 2947, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 2947, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 2947, 0b00100 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_GPC2 + li x6, 0xa5a5a5a5 + csrrw x12, 2820, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 2820, x6 + li x6, 0xa5a5a5a5 + bne x6, x12, csr_fail + li x6, 0xcafd0058 + csrrw x12, 2820, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 2820, x6 + li x6, 0xcafd0058 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 2820, x6 + li x6, 0xeffda5fd + bne x6, x12, csr_fail + li x6, 0x55c517ca + csrrs x12, 2820, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 2820, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 2820, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xde971dd4 + csrrc x12, 2820, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 2820, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 2820, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrwi x12, 2820, 0b10101 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 2820, 0b00101 + li x6, 0x00000015 + bne x6, x12, csr_fail + csrrsi x12, 2820, 0b11010 + li x6, 0x00000015 + bne x6, x12, csr_fail + csrrsi x12, 2820, 0b00011 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 2820, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 2820, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 2820, 0b10100 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_GPC2H + li x6, 0xa5a5a5a5 + csrrw x12, 2948, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 2948, x6 + li x6, 0xa5a5a5a5 + bne x6, x12, csr_fail + li x6, 0xe564801e + csrrw x12, 2948, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 2948, x6 + li x6, 0xe564801e + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 2948, x6 + li x6, 0xe5e5a5bf + bne x6, x12, csr_fail + li x6, 0x9a6181e9 + csrrs x12, 2948, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 2948, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 2948, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xfebbdf95 + csrrc x12, 2948, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 2948, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 2948, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrwi x12, 2948, 0b10001 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 2948, 0b00101 + li x6, 0x00000011 + bne x6, x12, csr_fail + csrrsi x12, 2948, 0b11010 + li x6, 0x00000015 + bne x6, x12, csr_fail + csrrsi x12, 2948, 0b11000 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 2948, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 2948, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 2948, 0b11010 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_GPC3 + li x6, 0xa5a5a5a5 + csrrw x12, 2821, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 2821, x6 + li x6, 0xa5a5a5a5 + bne x6, x12, csr_fail + li x6, 0x30d793cb + csrrw x12, 2821, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 2821, x6 + li x6, 0x30d793cb + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 2821, x6 + li x6, 0xb5f7b7ef + bne x6, x12, csr_fail + li x6, 0xf052838b + csrrs x12, 2821, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 2821, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 2821, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0x86d5de86 + csrrc x12, 2821, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 2821, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 2821, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrwi x12, 2821, 0b00110 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 2821, 0b00101 + li x6, 0x00000006 + bne x6, x12, csr_fail + csrrsi x12, 2821, 0b11010 + li x6, 0x00000007 + bne x6, x12, csr_fail + csrrsi x12, 2821, 0b10101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 2821, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 2821, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 2821, 0b10110 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_GPC3H + li x6, 0xa5a5a5a5 + csrrw x12, 2949, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 2949, x6 + li x6, 0xa5a5a5a5 + bne x6, x12, csr_fail + li x6, 0xeeb16977 + csrrw x12, 2949, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 2949, x6 + li x6, 0xeeb16977 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 2949, x6 + li x6, 0xefb5edf7 + bne x6, x12, csr_fail + li x6, 0xabfd710b + csrrs x12, 2949, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 2949, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 2949, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xa08eb33b + csrrc x12, 2949, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 2949, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 2949, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrwi x12, 2949, 0b01100 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 2949, 0b00101 + li x6, 0x0000000c + bne x6, x12, csr_fail + csrrsi x12, 2949, 0b11010 + li x6, 0x0000000d + bne x6, x12, csr_fail + csrrsi x12, 2949, 0b01010 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 2949, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 2949, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 2949, 0b00000 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_GPC4 + li x6, 0xa5a5a5a5 + csrrw x12, 2822, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 2822, x6 + li x6, 0xa5a5a5a5 + bne x6, x12, csr_fail + li x6, 0x35680239 + csrrw x12, 2822, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 2822, x6 + li x6, 0x35680239 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 2822, x6 + li x6, 0xb5eda7bd + bne x6, x12, csr_fail + li x6, 0x05561d07 + csrrs x12, 2822, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 2822, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 2822, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0x944ebe73 + csrrc x12, 2822, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 2822, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 2822, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrwi x12, 2822, 0b00110 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 2822, 0b00101 + li x6, 0x00000006 + bne x6, x12, csr_fail + csrrsi x12, 2822, 0b11010 + li x6, 0x00000007 + bne x6, x12, csr_fail + csrrsi x12, 2822, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 2822, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 2822, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 2822, 0b10110 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_GPC4H + li x6, 0xa5a5a5a5 + csrrw x12, 2950, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 2950, x6 + li x6, 0xa5a5a5a5 + bne x6, x12, csr_fail + li x6, 0x2ae4e6d8 + csrrw x12, 2950, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 2950, x6 + li x6, 0x2ae4e6d8 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 2950, x6 + li x6, 0xafe5e7fd + bne x6, x12, csr_fail + li x6, 0xe921f6e1 + csrrs x12, 2950, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 2950, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 2950, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0x19c45173 + csrrc x12, 2950, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 2950, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 2950, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrwi x12, 2950, 0b01110 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 2950, 0b00101 + li x6, 0x0000000e + bne x6, x12, csr_fail + csrrsi x12, 2950, 0b11010 + li x6, 0x0000000f + bne x6, x12, csr_fail + csrrsi x12, 2950, 0b11001 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 2950, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 2950, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 2950, 0b01110 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_GPC5 + li x6, 0xa5a5a5a5 + csrrw x12, 2823, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 2823, x6 + li x6, 0xa5a5a5a5 + bne x6, x12, csr_fail + li x6, 0x837e3a6e + csrrw x12, 2823, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 2823, x6 + li x6, 0x837e3a6e + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 2823, x6 + li x6, 0xa7ffbfef + bne x6, x12, csr_fail + li x6, 0x4411e22c + csrrs x12, 2823, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 2823, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 2823, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xc287ebe5 + csrrc x12, 2823, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 2823, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 2823, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrwi x12, 2823, 0b10011 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 2823, 0b00101 + li x6, 0x00000013 + bne x6, x12, csr_fail + csrrsi x12, 2823, 0b11010 + li x6, 0x00000017 + bne x6, x12, csr_fail + csrrsi x12, 2823, 0b01101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 2823, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 2823, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 2823, 0b01111 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_GPC5H + li x6, 0xa5a5a5a5 + csrrw x12, 2951, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 2951, x6 + li x6, 0xa5a5a5a5 + bne x6, x12, csr_fail + li x6, 0x07536bcf + csrrw x12, 2951, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 2951, x6 + li x6, 0x07536bcf + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 2951, x6 + li x6, 0xa7f7efef + bne x6, x12, csr_fail + li x6, 0x4adeb942 + csrrs x12, 2951, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 2951, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 2951, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0x60f1fb98 + csrrc x12, 2951, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 2951, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 2951, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrwi x12, 2951, 0b00000 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 2951, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrsi x12, 2951, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrsi x12, 2951, 0b01011 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 2951, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 2951, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 2951, 0b10111 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_GPC6 + li x6, 0xa5a5a5a5 + csrrw x12, 2824, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 2824, x6 + li x6, 0xa5a5a5a5 + bne x6, x12, csr_fail + li x6, 0x55bb10bb + csrrw x12, 2824, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 2824, x6 + li x6, 0x55bb10bb + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 2824, x6 + li x6, 0xf5bfb5bf + bne x6, x12, csr_fail + li x6, 0x3ce4dbfe + csrrs x12, 2824, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 2824, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 2824, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0x4c7a4413 + csrrc x12, 2824, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 2824, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 2824, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrwi x12, 2824, 0b01110 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 2824, 0b00101 + li x6, 0x0000000e + bne x6, x12, csr_fail + csrrsi x12, 2824, 0b11010 + li x6, 0x0000000f + bne x6, x12, csr_fail + csrrsi x12, 2824, 0b00000 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 2824, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 2824, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 2824, 0b11010 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_GPC6H + li x6, 0xa5a5a5a5 + csrrw x12, 2952, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 2952, x6 + li x6, 0xa5a5a5a5 + bne x6, x12, csr_fail + li x6, 0xf37a6300 + csrrw x12, 2952, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 2952, x6 + li x6, 0xf37a6300 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 2952, x6 + li x6, 0xf7ffe7a5 + bne x6, x12, csr_fail + li x6, 0xf152af0a + csrrs x12, 2952, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 2952, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 2952, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0x3538af66 + csrrc x12, 2952, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 2952, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 2952, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrwi x12, 2952, 0b00110 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 2952, 0b00101 + li x6, 0x00000006 + bne x6, x12, csr_fail + csrrsi x12, 2952, 0b11010 + li x6, 0x00000007 + bne x6, x12, csr_fail + csrrsi x12, 2952, 0b10101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 2952, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 2952, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 2952, 0b01010 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_GPC1_PMES + li x6, 0xa5a5a5a5 + csrrw x12, 803, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 803, x6 + li x6, 0x00000005 + bne x6, x12, csr_fail + li x6, 0xe41f2cdf + csrrw x12, 803, x6 + li x6, 0x0000001a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 803, x6 + li x6, 0x0000001f + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 803, x6 + li x6, 0x0000001f + bne x6, x12, csr_fail + li x6, 0xb0156aed + csrrs x12, 803, x6 + li x6, 0x0000001f + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 803, x6 + li x6, 0x0000001f + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 803, x6 + li x6, 0x0000001a + bne x6, x12, csr_fail + li x6, 0xc2f3a49c + csrrc x12, 803, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 803, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 803, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrwi x12, 803, 0b01110 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 803, 0b00101 + li x6, 0x0000000e + bne x6, x12, csr_fail + csrrsi x12, 803, 0b11010 + li x6, 0x0000000f + bne x6, x12, csr_fail + csrrsi x12, 803, 0b01111 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 803, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 803, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 803, 0b11010 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_GPC2_PMES + li x6, 0xa5a5a5a5 + csrrw x12, 804, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 804, x6 + li x6, 0x00000005 + bne x6, x12, csr_fail + li x6, 0x93627ff8 + csrrw x12, 804, x6 + li x6, 0x0000001a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 804, x6 + li x6, 0x00000018 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 804, x6 + li x6, 0x0000001d + bne x6, x12, csr_fail + li x6, 0xaa624a7f + csrrs x12, 804, x6 + li x6, 0x0000001f + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 804, x6 + li x6, 0x0000001f + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 804, x6 + li x6, 0x0000001a + bne x6, x12, csr_fail + li x6, 0xf540269b + csrrc x12, 804, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 804, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 804, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrwi x12, 804, 0b01000 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 804, 0b00101 + li x6, 0x00000008 + bne x6, x12, csr_fail + csrrsi x12, 804, 0b11010 + li x6, 0x0000000d + bne x6, x12, csr_fail + csrrsi x12, 804, 0b11111 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 804, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 804, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 804, 0b11010 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_GPC3_PMES + li x6, 0xa5a5a5a5 + csrrw x12, 805, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 805, x6 + li x6, 0x00000005 + bne x6, x12, csr_fail + li x6, 0x2724e603 + csrrw x12, 805, x6 + li x6, 0x0000001a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 805, x6 + li x6, 0x00000003 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 805, x6 + li x6, 0x00000007 + bne x6, x12, csr_fail + li x6, 0x777c5f33 + csrrs x12, 805, x6 + li x6, 0x0000001f + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 805, x6 + li x6, 0x0000001f + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 805, x6 + li x6, 0x0000001a + bne x6, x12, csr_fail + li x6, 0x586b1083 + csrrc x12, 805, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 805, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 805, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrwi x12, 805, 0b11111 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 805, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrsi x12, 805, 0b11010 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrsi x12, 805, 0b01010 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 805, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 805, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 805, 0b10101 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_GPC4_PMES + li x6, 0xa5a5a5a5 + csrrw x12, 806, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 806, x6 + li x6, 0x00000005 + bne x6, x12, csr_fail + li x6, 0xc097a7a0 + csrrw x12, 806, x6 + li x6, 0x0000001a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 806, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 806, x6 + li x6, 0x00000005 + bne x6, x12, csr_fail + li x6, 0xe4073cd5 + csrrs x12, 806, x6 + li x6, 0x0000001f + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 806, x6 + li x6, 0x0000001f + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 806, x6 + li x6, 0x0000001a + bne x6, x12, csr_fail + li x6, 0x57bb5b68 + csrrc x12, 806, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 806, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 806, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrwi x12, 806, 0b01001 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 806, 0b00101 + li x6, 0x00000009 + bne x6, x12, csr_fail + csrrsi x12, 806, 0b11010 + li x6, 0x0000000d + bne x6, x12, csr_fail + csrrsi x12, 806, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 806, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 806, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 806, 0b11010 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_GPC5_PMES + li x6, 0xa5a5a5a5 + csrrw x12, 807, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 807, x6 + li x6, 0x00000005 + bne x6, x12, csr_fail + li x6, 0x1fc7025a + csrrw x12, 807, x6 + li x6, 0x0000001a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 807, x6 + li x6, 0x0000001a + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 807, x6 + li x6, 0x0000001f + bne x6, x12, csr_fail + li x6, 0xebe5fccd + csrrs x12, 807, x6 + li x6, 0x0000001f + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 807, x6 + li x6, 0x0000001f + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 807, x6 + li x6, 0x0000001a + bne x6, x12, csr_fail + li x6, 0x20e31632 + csrrc x12, 807, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 807, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 807, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrwi x12, 807, 0b01010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 807, 0b00101 + li x6, 0x0000000a + bne x6, x12, csr_fail + csrrsi x12, 807, 0b11010 + li x6, 0x0000000f + bne x6, x12, csr_fail + csrrsi x12, 807, 0b01111 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 807, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 807, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 807, 0b01011 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_GPC6_PMES + li x6, 0xa5a5a5a5 + csrrw x12, 808, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 808, x6 + li x6, 0x00000005 + bne x6, x12, csr_fail + li x6, 0x64dcfeb7 + csrrw x12, 808, x6 + li x6, 0x0000001a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 808, x6 + li x6, 0x00000017 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 808, x6 + li x6, 0x00000017 + bne x6, x12, csr_fail + li x6, 0x68881579 + csrrs x12, 808, x6 + li x6, 0x0000001f + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 808, x6 + li x6, 0x0000001f + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 808, x6 + li x6, 0x0000001a + bne x6, x12, csr_fail + li x6, 0x4578638d + csrrc x12, 808, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 808, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 808, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrwi x12, 808, 0b00010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 808, 0b00101 + li x6, 0x00000002 + bne x6, x12, csr_fail + csrrsi x12, 808, 0b11010 + li x6, 0x00000007 + bne x6, x12, csr_fail + csrrsi x12, 808, 0b01110 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 808, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 808, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 808, 0b01110 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_ICACHE + li x6, 0xa5a5a5a5 + csrrw x12, 1984, x6 + li x6, 0x00000001 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 1984, x6 + li x6, 0x00000001 + bne x6, x12, csr_fail + li x6, 0x53ab47b8 + csrrw x12, 1984, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 1984, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 1984, x6 + li x6, 0x00000001 + bne x6, x12, csr_fail + li x6, 0xbc84fe83 + csrrs x12, 1984, x6 + li x6, 0x00000001 + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 1984, x6 + li x6, 0x00000001 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 1984, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x12adc901 + csrrc x12, 1984, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 1984, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 1984, 0b11010 + li x6, 0x00000001 + bne x6, x12, csr_fail + csrrwi x12, 1984, 0b01101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrsi x12, 1984, 0b00101 + li x6, 0x00000001 + bne x6, x12, csr_fail + csrrsi x12, 1984, 0b11010 + li x6, 0x00000001 + bne x6, x12, csr_fail + csrrsi x12, 1984, 0b01000 + li x6, 0x00000001 + bne x6, x12, csr_fail + csrrci x12, 1984, 0b00101 + li x6, 0x00000001 + bne x6, x12, csr_fail + csrrci x12, 1984, 0b11010 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrci x12, 1984, 0b11010 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_DCACHE + li x6, 0xa5a5a5a5 + csrrw x12, 1985, x6 + li x6, 0x00000001 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 1985, x6 + li x6, 0x00000001 + bne x6, x12, csr_fail + li x6, 0x3a1d6896 + csrrw x12, 1985, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 1985, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 1985, x6 + li x6, 0x00000001 + bne x6, x12, csr_fail + li x6, 0x3bc382a6 + csrrs x12, 1985, x6 + li x6, 0x00000001 + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 1985, x6 + li x6, 0x00000001 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 1985, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x643bcc02 + csrrc x12, 1985, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 1985, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 1985, 0b11010 + li x6, 0x00000001 + bne x6, x12, csr_fail + csrrwi x12, 1985, 0b11100 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrsi x12, 1985, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrsi x12, 1985, 0b11010 + li x6, 0x00000001 + bne x6, x12, csr_fail + csrrsi x12, 1985, 0b10100 + li x6, 0x00000001 + bne x6, x12, csr_fail + csrrci x12, 1985, 0b00101 + li x6, 0x00000001 + bne x6, x12, csr_fail + csrrci x12, 1985, 0b11010 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrci x12, 1985, 0b10101 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_PMPCFG0 + li x6, 0xa5a5a5a5 + csrrw x12, 928, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 928, x6 + li x6, 0xa5a5a5a5 + bne x6, x12, csr_fail + li x6, 0x2b4250fc + csrrw x12, 928, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 928, x6 + li x6, 0x2b4250fc + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 928, x6 + li x6, 0xafe7f5fd + bne x6, x12, csr_fail + li x6, 0x81c8bf1c + csrrs x12, 928, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 928, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 928, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xdd640568 + csrrc x12, 928, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 928, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 928, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrwi x12, 928, 0b00000 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 928, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrsi x12, 928, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrsi x12, 928, 0b01111 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 928, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 928, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 928, 0b00111 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_PMPCFG1 + li x6, 0xa5a5a5a5 + csrrw x12, 929, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 929, x6 + li x6, 0xa5a5a5a5 + bne x6, x12, csr_fail + li x6, 0xee2ea5cd + csrrw x12, 929, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 929, x6 + li x6, 0xee2ea5cd + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 929, x6 + li x6, 0xefafa5ed + bne x6, x12, csr_fail + li x6, 0x473fb54e + csrrs x12, 929, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 929, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 929, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xacd1083c + csrrc x12, 929, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 929, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 929, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrwi x12, 929, 0b10000 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 929, 0b00101 + li x6, 0x00000010 + bne x6, x12, csr_fail + csrrsi x12, 929, 0b11010 + li x6, 0x00000015 + bne x6, x12, csr_fail + csrrsi x12, 929, 0b01100 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 929, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 929, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 929, 0b10010 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_PMPCFG2 + li x6, 0xa5a5a5a5 + csrrw x12, 930, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 930, x6 + li x6, 0xa5a5a5a5 + bne x6, x12, csr_fail + li x6, 0xd82f01cf + csrrw x12, 930, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 930, x6 + li x6, 0xd82f01cf + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 930, x6 + li x6, 0xfdafa5ef + bne x6, x12, csr_fail + li x6, 0x09cd46c4 + csrrs x12, 930, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 930, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 930, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0x901fd011 + csrrc x12, 930, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 930, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 930, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrwi x12, 930, 0b00110 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 930, 0b00101 + li x6, 0x00000006 + bne x6, x12, csr_fail + csrrsi x12, 930, 0b11010 + li x6, 0x00000007 + bne x6, x12, csr_fail + csrrsi x12, 930, 0b00011 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 930, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 930, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 930, 0b11011 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_PMPCFG3 + li x6, 0xa5a5a5a5 + csrrw x12, 931, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 931, x6 + li x6, 0xa5a5a5a5 + bne x6, x12, csr_fail + li x6, 0xe12c5746 + csrrw x12, 931, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 931, x6 + li x6, 0xe12c5746 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 931, x6 + li x6, 0xe5adf7e7 + bne x6, x12, csr_fail + li x6, 0xc61666ef + csrrs x12, 931, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 931, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 931, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0x574b39bc + csrrc x12, 931, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 931, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 931, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrwi x12, 931, 0b00100 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 931, 0b00101 + li x6, 0x00000004 + bne x6, x12, csr_fail + csrrsi x12, 931, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrsi x12, 931, 0b01111 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 931, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 931, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 931, 0b10010 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_PMPADDR0 + li x6, 0xa5a5a5a5 + csrrw x12, 944, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 944, x6 + li x6, 0xa5a5a5a5 + bne x6, x12, csr_fail + li x6, 0xceb9cc9f + csrrw x12, 944, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 944, x6 + li x6, 0xceb9cc9f + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 944, x6 + li x6, 0xefbdedbf + bne x6, x12, csr_fail + li x6, 0x30c1e578 + csrrs x12, 944, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 944, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 944, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xd80ce680 + csrrc x12, 944, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 944, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 944, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrwi x12, 944, 0b00010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 944, 0b00101 + li x6, 0x00000002 + bne x6, x12, csr_fail + csrrsi x12, 944, 0b11010 + li x6, 0x00000007 + bne x6, x12, csr_fail + csrrsi x12, 944, 0b01100 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 944, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 944, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 944, 0b10100 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_PMPADDR1 + li x6, 0xa5a5a5a5 + csrrw x12, 945, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 945, x6 + li x6, 0xa5a5a5a5 + bne x6, x12, csr_fail + li x6, 0xb193e032 + csrrw x12, 945, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 945, x6 + li x6, 0xb193e032 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 945, x6 + li x6, 0xb5b7e5b7 + bne x6, x12, csr_fail + li x6, 0x0839e351 + csrrs x12, 945, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 945, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 945, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0x425ecc7e + csrrc x12, 945, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 945, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 945, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrwi x12, 945, 0b10000 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 945, 0b00101 + li x6, 0x00000010 + bne x6, x12, csr_fail + csrrsi x12, 945, 0b11010 + li x6, 0x00000015 + bne x6, x12, csr_fail + csrrsi x12, 945, 0b10100 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 945, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 945, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 945, 0b01110 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_PMPADDR2 + li x6, 0xa5a5a5a5 + csrrw x12, 946, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 946, x6 + li x6, 0xa5a5a5a5 + bne x6, x12, csr_fail + li x6, 0xe6893365 + csrrw x12, 946, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 946, x6 + li x6, 0xe6893365 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 946, x6 + li x6, 0xe7adb7e5 + bne x6, x12, csr_fail + li x6, 0xce9f3535 + csrrs x12, 946, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 946, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 946, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xda0be795 + csrrc x12, 946, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 946, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 946, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrwi x12, 946, 0b11111 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 946, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrsi x12, 946, 0b11010 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrsi x12, 946, 0b01010 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 946, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 946, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 946, 0b10110 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_PMPADDR3 + li x6, 0xa5a5a5a5 + csrrw x12, 947, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 947, x6 + li x6, 0xa5a5a5a5 + bne x6, x12, csr_fail + li x6, 0x202f84b4 + csrrw x12, 947, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 947, x6 + li x6, 0x202f84b4 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 947, x6 + li x6, 0xa5afa5b5 + bne x6, x12, csr_fail + li x6, 0x743f15fb + csrrs x12, 947, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 947, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 947, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xd9511b1b + csrrc x12, 947, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 947, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 947, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrwi x12, 947, 0b01010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 947, 0b00101 + li x6, 0x0000000a + bne x6, x12, csr_fail + csrrsi x12, 947, 0b11010 + li x6, 0x0000000f + bne x6, x12, csr_fail + csrrsi x12, 947, 0b11011 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 947, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 947, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 947, 0b00001 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_PMPADDR4 + li x6, 0xa5a5a5a5 + csrrw x12, 948, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 948, x6 + li x6, 0xa5a5a5a5 + bne x6, x12, csr_fail + li x6, 0x8c7f9c4d + csrrw x12, 948, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 948, x6 + li x6, 0x8c7f9c4d + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 948, x6 + li x6, 0xadffbded + bne x6, x12, csr_fail + li x6, 0x7b56288d + csrrs x12, 948, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 948, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 948, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0x13d22f88 + csrrc x12, 948, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 948, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 948, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrwi x12, 948, 0b00110 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 948, 0b00101 + li x6, 0x00000006 + bne x6, x12, csr_fail + csrrsi x12, 948, 0b11010 + li x6, 0x00000007 + bne x6, x12, csr_fail + csrrsi x12, 948, 0b01011 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 948, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 948, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 948, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_PMPADDR5 + li x6, 0xa5a5a5a5 + csrrw x12, 949, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 949, x6 + li x6, 0xa5a5a5a5 + bne x6, x12, csr_fail + li x6, 0xe27a01ab + csrrw x12, 949, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 949, x6 + li x6, 0xe27a01ab + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 949, x6 + li x6, 0xe7ffa5af + bne x6, x12, csr_fail + li x6, 0x920020c3 + csrrs x12, 949, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 949, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 949, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xf9b95a15 + csrrc x12, 949, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 949, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 949, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrwi x12, 949, 0b00111 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 949, 0b00101 + li x6, 0x00000007 + bne x6, x12, csr_fail + csrrsi x12, 949, 0b11010 + li x6, 0x00000007 + bne x6, x12, csr_fail + csrrsi x12, 949, 0b00111 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 949, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 949, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 949, 0b00010 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_PMPADDR6 + li x6, 0xa5a5a5a5 + csrrw x12, 950, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 950, x6 + li x6, 0xa5a5a5a5 + bne x6, x12, csr_fail + li x6, 0xafb17ed4 + csrrw x12, 950, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 950, x6 + li x6, 0xafb17ed4 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 950, x6 + li x6, 0xafb5fff5 + bne x6, x12, csr_fail + li x6, 0x23ba0067 + csrrs x12, 950, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 950, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 950, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xd5a5a621 + csrrc x12, 950, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 950, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 950, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrwi x12, 950, 0b11100 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 950, 0b00101 + li x6, 0x0000001c + bne x6, x12, csr_fail + csrrsi x12, 950, 0b11010 + li x6, 0x0000001d + bne x6, x12, csr_fail + csrrsi x12, 950, 0b01111 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 950, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 950, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 950, 0b01010 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_PMPADDR7 + li x6, 0xa5a5a5a5 + csrrw x12, 951, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 951, x6 + li x6, 0xa5a5a5a5 + bne x6, x12, csr_fail + li x6, 0x83164a9e + csrrw x12, 951, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 951, x6 + li x6, 0x83164a9e + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 951, x6 + li x6, 0xa7b7efbf + bne x6, x12, csr_fail + li x6, 0xe6429637 + csrrs x12, 951, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 951, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 951, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0x97e1c152 + csrrc x12, 951, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 951, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 951, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrwi x12, 951, 0b11100 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 951, 0b00101 + li x6, 0x0000001c + bne x6, x12, csr_fail + csrrsi x12, 951, 0b11010 + li x6, 0x0000001d + bne x6, x12, csr_fail + csrrsi x12, 951, 0b01100 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 951, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 951, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 951, 0b10101 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_PMPADDR8 + li x6, 0xa5a5a5a5 + csrrw x12, 952, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 952, x6 + li x6, 0xa5a5a5a5 + bne x6, x12, csr_fail + li x6, 0xb5e800ee + csrrw x12, 952, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 952, x6 + li x6, 0xb5e800ee + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 952, x6 + li x6, 0xb5eda5ef + bne x6, x12, csr_fail + li x6, 0x71b06744 + csrrs x12, 952, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 952, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 952, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xb73d11ad + csrrc x12, 952, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 952, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 952, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrwi x12, 952, 0b10100 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 952, 0b00101 + li x6, 0x00000014 + bne x6, x12, csr_fail + csrrsi x12, 952, 0b11010 + li x6, 0x00000015 + bne x6, x12, csr_fail + csrrsi x12, 952, 0b00011 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 952, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 952, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 952, 0b10000 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_PMPADDR9 + li x6, 0xa5a5a5a5 + csrrw x12, 953, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 953, x6 + li x6, 0xa5a5a5a5 + bne x6, x12, csr_fail + li x6, 0x7ce6cf6a + csrrw x12, 953, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 953, x6 + li x6, 0x7ce6cf6a + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 953, x6 + li x6, 0xfde7efef + bne x6, x12, csr_fail + li x6, 0x5db76d50 + csrrs x12, 953, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 953, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 953, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xe039c23f + csrrc x12, 953, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 953, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 953, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrwi x12, 953, 0b01000 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 953, 0b00101 + li x6, 0x00000008 + bne x6, x12, csr_fail + csrrsi x12, 953, 0b11010 + li x6, 0x0000000d + bne x6, x12, csr_fail + csrrsi x12, 953, 0b00000 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 953, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 953, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 953, 0b11110 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_PMPADDR10 + li x6, 0xa5a5a5a5 + csrrw x12, 954, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 954, x6 + li x6, 0xa5a5a5a5 + bne x6, x12, csr_fail + li x6, 0xbe3c7341 + csrrw x12, 954, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 954, x6 + li x6, 0xbe3c7341 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 954, x6 + li x6, 0xbfbdf7e5 + bne x6, x12, csr_fail + li x6, 0x4dcd8566 + csrrs x12, 954, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 954, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 954, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0x81d6f159 + csrrc x12, 954, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 954, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 954, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrwi x12, 954, 0b10000 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 954, 0b00101 + li x6, 0x00000010 + bne x6, x12, csr_fail + csrrsi x12, 954, 0b11010 + li x6, 0x00000015 + bne x6, x12, csr_fail + csrrsi x12, 954, 0b11100 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 954, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 954, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 954, 0b11011 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_PMPADDR11 + li x6, 0xa5a5a5a5 + csrrw x12, 955, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 955, x6 + li x6, 0xa5a5a5a5 + bne x6, x12, csr_fail + li x6, 0x86169bbe + csrrw x12, 955, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 955, x6 + li x6, 0x86169bbe + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 955, x6 + li x6, 0xa7b7bfbf + bne x6, x12, csr_fail + li x6, 0xcbc3510f + csrrs x12, 955, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 955, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 955, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xdcf6ec09 + csrrc x12, 955, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 955, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 955, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrwi x12, 955, 0b10001 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 955, 0b00101 + li x6, 0x00000011 + bne x6, x12, csr_fail + csrrsi x12, 955, 0b11010 + li x6, 0x00000015 + bne x6, x12, csr_fail + csrrsi x12, 955, 0b01000 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 955, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 955, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 955, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_PMPADDR12 + li x6, 0xa5a5a5a5 + csrrw x12, 956, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 956, x6 + li x6, 0xa5a5a5a5 + bne x6, x12, csr_fail + li x6, 0x9a55ab74 + csrrw x12, 956, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 956, x6 + li x6, 0x9a55ab74 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 956, x6 + li x6, 0xbff5aff5 + bne x6, x12, csr_fail + li x6, 0x3ab6f7e7 + csrrs x12, 956, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 956, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 956, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xac7bc980 + csrrc x12, 956, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 956, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 956, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrwi x12, 956, 0b01101 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 956, 0b00101 + li x6, 0x0000000d + bne x6, x12, csr_fail + csrrsi x12, 956, 0b11010 + li x6, 0x0000000d + bne x6, x12, csr_fail + csrrsi x12, 956, 0b11001 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 956, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 956, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 956, 0b10101 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_PMPADDR13 + li x6, 0xa5a5a5a5 + csrrw x12, 957, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 957, x6 + li x6, 0xa5a5a5a5 + bne x6, x12, csr_fail + li x6, 0x4c7bd3a4 + csrrw x12, 957, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 957, x6 + li x6, 0x4c7bd3a4 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 957, x6 + li x6, 0xedfff7a5 + bne x6, x12, csr_fail + li x6, 0x897bd94e + csrrs x12, 957, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 957, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 957, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0x849898ed + csrrc x12, 957, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 957, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 957, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrwi x12, 957, 0b01100 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 957, 0b00101 + li x6, 0x0000000c + bne x6, x12, csr_fail + csrrsi x12, 957, 0b11010 + li x6, 0x0000000d + bne x6, x12, csr_fail + csrrsi x12, 957, 0b00010 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 957, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 957, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 957, 0b01110 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_PMPADDR14 + li x6, 0xa5a5a5a5 + csrrw x12, 958, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 958, x6 + li x6, 0xa5a5a5a5 + bne x6, x12, csr_fail + li x6, 0xb3610a88 + csrrw x12, 958, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 958, x6 + li x6, 0xb3610a88 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 958, x6 + li x6, 0xb7e5afad + bne x6, x12, csr_fail + li x6, 0x1814363b + csrrs x12, 958, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 958, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 958, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0x94122f1d + csrrc x12, 958, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 958, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 958, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrwi x12, 958, 0b01110 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 958, 0b00101 + li x6, 0x0000000e + bne x6, x12, csr_fail + csrrsi x12, 958, 0b11010 + li x6, 0x0000000f + bne x6, x12, csr_fail + csrrsi x12, 958, 0b11001 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 958, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 958, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 958, 0b00001 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_PMPADDR15 + li x6, 0xa5a5a5a5 + csrrw x12, 959, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 959, x6 + li x6, 0xa5a5a5a5 + bne x6, x12, csr_fail + li x6, 0xd7fad917 + csrrw x12, 959, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 959, x6 + li x6, 0xd7fad917 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 959, x6 + li x6, 0xf7fffdb7 + bne x6, x12, csr_fail + li x6, 0x26e15b6e + csrrs x12, 959, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 959, x6 + li x6, 0xffffffff + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 959, x6 + li x6, 0x5a5a5a5a + bne x6, x12, csr_fail + li x6, 0x2e506fd9 + csrrc x12, 959, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 959, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 959, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrwi x12, 959, 0b01111 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 959, 0b00101 + li x6, 0x0000000f + bne x6, x12, csr_fail + csrrsi x12, 959, 0b11010 + li x6, 0x0000000f + bne x6, x12, csr_fail + csrrsi x12, 959, 0b01101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 959, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 959, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 959, 0b11010 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_FFLAGS + li x6, 0xa5a5a5a5 + csrrw x12, 1, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 1, x6 + li x6, 0x00000005 + bne x6, x12, csr_fail + li x6, 0x1002f175 + csrrw x12, 1, x6 + li x6, 0x0000001a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 1, x6 + li x6, 0x00000015 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 1, x6 + li x6, 0x00000015 + bne x6, x12, csr_fail + li x6, 0x5b47b8af + csrrs x12, 1, x6 + li x6, 0x0000001f + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 1, x6 + li x6, 0x0000001f + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 1, x6 + li x6, 0x0000001a + bne x6, x12, csr_fail + li x6, 0xf51acefe + csrrc x12, 1, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 1, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 1, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrwi x12, 1, 0b01001 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 1, 0b00101 + li x6, 0x00000009 + bne x6, x12, csr_fail + csrrsi x12, 1, 0b11010 + li x6, 0x0000000d + bne x6, x12, csr_fail + csrrsi x12, 1, 0b01011 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 1, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 1, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 1, 0b11000 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_FRM + li x6, 0xa5a5a5a5 + csrrw x12, 2, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 2, x6 + li x6, 0x00000005 + bne x6, x12, csr_fail + li x6, 0x2d079f04 + csrrw x12, 2, x6 + li x6, 0x00000002 + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 2, x6 + li x6, 0x00000004 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 2, x6 + li x6, 0x00000005 + bne x6, x12, csr_fail + li x6, 0x45235a4e + csrrs x12, 2, x6 + li x6, 0x00000007 + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 2, x6 + li x6, 0x00000007 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 2, x6 + li x6, 0x00000002 + bne x6, x12, csr_fail + li x6, 0xa7093cbb + csrrc x12, 2, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 2, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 2, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrwi x12, 2, 0b01000 + li x6, 0x00000002 + bne x6, x12, csr_fail + csrrsi x12, 2, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrsi x12, 2, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrsi x12, 2, 0b00110 + li x6, 0x00000007 + bne x6, x12, csr_fail + csrrci x12, 2, 0b00101 + li x6, 0x00000007 + bne x6, x12, csr_fail + csrrci x12, 2, 0b11010 + li x6, 0x00000002 + bne x6, x12, csr_fail + csrrci x12, 2, 0b11100 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_FCSR + li x6, 0xa5a5a5a5 + csrrw x12, 3, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 3, x6 + li x6, 0x000000a5 + bne x6, x12, csr_fail + li x6, 0x6a978105 + csrrw x12, 3, x6 + li x6, 0x0000005a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 3, x6 + li x6, 0x00000005 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 3, x6 + li x6, 0x000000a5 + bne x6, x12, csr_fail + li x6, 0x2f940b9e + csrrs x12, 3, x6 + li x6, 0x000000ff + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 3, x6 + li x6, 0x000000ff + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 3, x6 + li x6, 0x0000005a + bne x6, x12, csr_fail + li x6, 0xfb17c858 + csrrc x12, 3, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 3, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 3, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrwi x12, 3, 0b00011 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 3, 0b00101 + li x6, 0x00000003 + bne x6, x12, csr_fail + csrrsi x12, 3, 0b11010 + li x6, 0x00000007 + bne x6, x12, csr_fail + csrrsi x12, 3, 0b01010 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 3, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 3, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 3, 0b11001 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_FTRAN + li x6, 0xa5a5a5a5 + csrrw x12, 2048, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 2048, x6 + li x6, 0x00000025 + bne x6, x12, csr_fail + li x6, 0x4b092c10 + csrrw x12, 2048, x6 + li x6, 0x0000005a + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 2048, x6 + li x6, 0x00000010 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 2048, x6 + li x6, 0x00000035 + bne x6, x12, csr_fail + li x6, 0x8a9bb6cc + csrrs x12, 2048, x6 + li x6, 0x0000007f + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 2048, x6 + li x6, 0x0000007f + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 2048, x6 + li x6, 0x0000005a + bne x6, x12, csr_fail + li x6, 0xfbaacf1e + csrrc x12, 2048, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 2048, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 2048, 0b11010 + li x6, 0x00000005 + bne x6, x12, csr_fail + csrrwi x12, 2048, 0b10101 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrsi x12, 2048, 0b00101 + li x6, 0x00000015 + bne x6, x12, csr_fail + csrrsi x12, 2048, 0b11010 + li x6, 0x00000015 + bne x6, x12, csr_fail + csrrsi x12, 2048, 0b01110 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 2048, 0b00101 + li x6, 0x0000001f + bne x6, x12, csr_fail + csrrci x12, 2048, 0b11010 + li x6, 0x0000001a + bne x6, x12, csr_fail + csrrci x12, 2048, 0b10010 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_CYCLE + li x6, 0xa5a5a5a5 + csrrw x12, 3072, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 3072, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x682be46b + csrrw x12, 3072, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 3072, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 3072, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0xdbc788f7 + csrrs x12, 3072, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 3072, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 3072, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x0de923f4 + csrrc x12, 3072, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 3072, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 3072, 0b11010 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 3072, 0b00110 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrsi x12, 3072, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrsi x12, 3072, 0b11010 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrsi x12, 3072, 0b00011 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrci x12, 3072, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrci x12, 3072, 0b11010 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrci x12, 3072, 0b10111 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_CYCLE_H + li x6, 0xa5a5a5a5 + csrrw x12, 3200, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 3200, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x6824d2ac + csrrw x12, 3200, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 3200, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 3200, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x9c366129 + csrrs x12, 3200, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 3200, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 3200, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0xa670ab37 + csrrc x12, 3200, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 3200, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 3200, 0b11010 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 3200, 0b01010 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrsi x12, 3200, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrsi x12, 3200, 0b11010 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrsi x12, 3200, 0b00110 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrci x12, 3200, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrci x12, 3200, 0b11010 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrci x12, 3200, 0b11010 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_INSTRET + li x6, 0xa5a5a5a5 + csrrw x12, 3074, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 3074, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0xa0b56aa9 + csrrw x12, 3074, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 3074, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 3074, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x02b9fe61 + csrrs x12, 3074, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 3074, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 3074, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0xa041b540 + csrrc x12, 3074, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 3074, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 3074, 0b11010 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 3074, 0b10101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrsi x12, 3074, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrsi x12, 3074, 0b11010 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrsi x12, 3074, 0b00100 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrci x12, 3074, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrci x12, 3074, 0b11010 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrci x12, 3074, 0b00001 + li x6, 0x00000000 + bne x6, x12, csr_fail + # CSR_INSTRET_H + li x6, 0xa5a5a5a5 + csrrw x12, 3202, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrw x12, 3202, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x81155b50 + csrrw x12, 3202, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrs x12, 3202, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrs x12, 3202, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0xe968b813 + csrrs x12, 3202, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0xa5a5a5a5 + csrrc x12, 3202, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x5a5a5a5a + csrrc x12, 3202, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + li x6, 0x1f878f6c + csrrc x12, 3202, x6 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 3202, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 3202, 0b11010 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrwi x12, 3202, 0b01111 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrsi x12, 3202, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrsi x12, 3202, 0b11010 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrsi x12, 3202, 0b10001 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrci x12, 3202, 0b00101 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrci x12, 3202, 0b11010 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrrci x12, 3202, 0b01011 + li x6, 0x00000000 + bne x6, x12, csr_fail + csrr x12, 3202 + li x6, 0x00000000 + bne x6, x12, csr_fail + +csr_pass: + li x18, 123456789 + li x17, 0x60000000 + sw x18,0(x17) + wfi + +csr_fail: + li x18, 1 + li x17, 0x60000000 + sw x18,0(x17) + wfi + diff --git a/verif/tests/custom/common/cva6_csr_access_test_64.S b/verif/tests/custom/common/cva6_csr_access_test_64.S new file mode 100644 index 0000000000..bf22598611 --- /dev/null +++ b/verif/tests/custom/common/cva6_csr_access_test_64.S @@ -0,0 +1,4503 @@ +.macro init +.endm +.section .text.init +.globl _start +.option norvc +_start: + # CSR_DCSR + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 1968, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 1968, x8 + li x8, 0x000000000000a584 + bne x8, x2, csr_fail + li x8, 0x4d5ec3b200000000 + csrrw x2, 1968, x8 + li x8, 0x0000000000001a52 + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 1968, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 1968, x8 + li x8, 0x000000000000a584 + bne x8, x2, csr_fail + li x8, 0xdadc26d200000000 + csrrs x2, 1968, x8 + li x8, 0x000000000000bfd6 + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 1968, x8 + li x8, 0x000000000000bfd6 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 1968, x8 + li x8, 0x0000000000001a52 + bne x8, x2, csr_fail + li x8, 0x2498478500000000 + csrrc x2, 1968, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 1968, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 1968, 0b11010 + li x8, 0x0000000000000004 + bne x8, x2, csr_fail + csrrwi x2, 1968, 0b00000 + li x8, 0x0000000000000012 + bne x8, x2, csr_fail + csrrsi x2, 1968, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 1968, 0b11010 + li x8, 0x0000000000000004 + bne x8, x2, csr_fail + csrrsi x2, 1968, 0b00000 + li x8, 0x0000000000000016 + bne x8, x2, csr_fail + csrrci x2, 1968, 0b00101 + li x8, 0x0000000000000016 + bne x8, x2, csr_fail + csrrci x2, 1968, 0b11010 + li x8, 0x0000000000000012 + bne x8, x2, csr_fail + csrrci x2, 1968, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_DPC + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 1969, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 1969, x8 + li x8, 0xa5a5a5a5a5a5a5a5 + bne x8, x2, csr_fail + li x8, 0x39422c9800000000 + csrrw x2, 1969, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 1969, x8 + li x8, 0x39422c9800000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 1969, x8 + li x8, 0xbde7adbda5a5a5a5 + bne x8, x2, csr_fail + li x8, 0x4cef0c6900000000 + csrrs x2, 1969, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 1969, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 1969, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0xfd3f1f2100000000 + csrrc x2, 1969, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 1969, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 1969, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrwi x2, 1969, 0b00000 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrsi x2, 1969, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 1969, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrsi x2, 1969, 0b00000 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 1969, 0b00101 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 1969, 0b11010 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrci x2, 1969, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_DSCRATCH0 + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 1970, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 1970, x8 + li x8, 0xa5a5a5a5a5a5a5a5 + bne x8, x2, csr_fail + li x8, 0x5c16715300000000 + csrrw x2, 1970, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 1970, x8 + li x8, 0x5c16715300000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 1970, x8 + li x8, 0xfdb7f5f7a5a5a5a5 + bne x8, x2, csr_fail + li x8, 0x9a278a0a00000000 + csrrs x2, 1970, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 1970, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 1970, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0x69238c3000000000 + csrrc x2, 1970, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 1970, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 1970, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrwi x2, 1970, 0b00000 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrsi x2, 1970, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 1970, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrsi x2, 1970, 0b00000 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 1970, 0b00101 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 1970, 0b11010 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrci x2, 1970, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_DSCRATCH1 + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 1971, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 1971, x8 + li x8, 0xa5a5a5a5a5a5a5a5 + bne x8, x2, csr_fail + li x8, 0x02e7fe1a00000000 + csrrw x2, 1971, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 1971, x8 + li x8, 0x02e7fe1a00000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 1971, x8 + li x8, 0xa7e7ffbfa5a5a5a5 + bne x8, x2, csr_fail + li x8, 0xe5d137e700000000 + csrrs x2, 1971, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 1971, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 1971, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0x5fc1ada400000000 + csrrc x2, 1971, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 1971, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 1971, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrwi x2, 1971, 0b00000 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrsi x2, 1971, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 1971, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrsi x2, 1971, 0b00000 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 1971, 0b00101 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 1971, 0b11010 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrci x2, 1971, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_SSTATUS + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 256, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 256, x8 + li x8, 0x800000010005a121 + bne x8, x2, csr_fail + li x8, 0xc16eddc900000000 + csrrw x2, 256, x8 + li x8, 0x0000000200084012 + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 256, x8 + li x8, 0x8000000100000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 256, x8 + li x8, 0x800000010005a121 + bne x8, x2, csr_fail + li x8, 0x5486cc7400000000 + csrrs x2, 256, x8 + li x8, 0x80000003000de133 + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 256, x8 + li x8, 0x80000003000de133 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 256, x8 + li x8, 0x0000000200084012 + bne x8, x2, csr_fail + li x8, 0x97bac69700000000 + csrrc x2, 256, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 256, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 256, 0b11010 + li x8, 0x0000000000000001 + bne x8, x2, csr_fail + csrrwi x2, 256, 0b00000 + li x8, 0x0000000000000012 + bne x8, x2, csr_fail + csrrsi x2, 256, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 256, 0b11010 + li x8, 0x0000000000000001 + bne x8, x2, csr_fail + csrrsi x2, 256, 0b00000 + li x8, 0x0000000000000013 + bne x8, x2, csr_fail + csrrci x2, 256, 0b00101 + li x8, 0x0000000000000013 + bne x8, x2, csr_fail + csrrci x2, 256, 0b11010 + li x8, 0x0000000000000012 + bne x8, x2, csr_fail + csrrci x2, 256, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_SIE + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 260, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 260, x8 + li x8, 0xa5a5a5a5a5a5a5a5 + bne x8, x2, csr_fail + li x8, 0xa6b3e21a00000000 + csrrw x2, 260, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 260, x8 + li x8, 0xa6b3e21a00000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 260, x8 + li x8, 0xa7b7e7bfa5a5a5a5 + bne x8, x2, csr_fail + li x8, 0xf7dadce600000000 + csrrs x2, 260, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 260, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 260, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0x46ba090700000000 + csrrc x2, 260, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 260, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 260, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrwi x2, 260, 0b00000 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrsi x2, 260, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 260, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrsi x2, 260, 0b00000 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 260, 0b00101 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 260, 0b11010 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrci x2, 260, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_SIP + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 324, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 324, x8 + li x8, 0xa5a5a5a5a5a5a5a5 + bne x8, x2, csr_fail + li x8, 0xb30528ec00000000 + csrrw x2, 324, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 324, x8 + li x8, 0xb30528ec00000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 324, x8 + li x8, 0xb7a5adeda5a5a5a5 + bne x8, x2, csr_fail + li x8, 0xf4b0a7a100000000 + csrrs x2, 324, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 324, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 324, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0x12cb2dcb00000000 + csrrc x2, 324, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 324, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 324, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrwi x2, 324, 0b00000 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrsi x2, 324, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 324, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrsi x2, 324, 0b00000 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 324, 0b00101 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 324, 0b11010 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrci x2, 324, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_STVEC + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 261, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 261, x8 + li x8, 0xa5a5a5a5a5a5a5a5 + bne x8, x2, csr_fail + li x8, 0x1162afb900000000 + csrrw x2, 261, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 261, x8 + li x8, 0x1162afb900000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 261, x8 + li x8, 0xb5e7afbda5a5a5a5 + bne x8, x2, csr_fail + li x8, 0x8e86d23f00000000 + csrrs x2, 261, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 261, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 261, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0xbc421cc400000000 + csrrc x2, 261, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 261, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 261, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrwi x2, 261, 0b00000 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrsi x2, 261, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 261, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrsi x2, 261, 0b00000 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 261, 0b00101 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 261, 0b11010 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrci x2, 261, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_SCOUNTEREN + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 262, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 262, x8 + li x8, 0x00000000a5a5a5a5 + bne x8, x2, csr_fail + li x8, 0xd5083d8e00000000 + csrrw x2, 262, x8 + li x8, 0x000000005a5a5a5a + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 262, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 262, x8 + li x8, 0x00000000a5a5a5a5 + bne x8, x2, csr_fail + li x8, 0x922cf92d00000000 + csrrs x2, 262, x8 + li x8, 0x00000000ffffffff + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 262, x8 + li x8, 0x00000000ffffffff + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 262, x8 + li x8, 0x000000005a5a5a5a + bne x8, x2, csr_fail + li x8, 0xd3d9437200000000 + csrrc x2, 262, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 262, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 262, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrwi x2, 262, 0b00000 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrsi x2, 262, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 262, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrsi x2, 262, 0b00000 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 262, 0b00101 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 262, 0b11010 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrci x2, 262, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_SSCRATCH + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 320, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 320, x8 + li x8, 0xa5a5a5a5a5a5a5a5 + bne x8, x2, csr_fail + li x8, 0x28476cb200000000 + csrrw x2, 320, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 320, x8 + li x8, 0x28476cb200000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 320, x8 + li x8, 0xade7edb7a5a5a5a5 + bne x8, x2, csr_fail + li x8, 0xf7e473f800000000 + csrrs x2, 320, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 320, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 320, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0x225f5f2d00000000 + csrrc x2, 320, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 320, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 320, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrwi x2, 320, 0b00000 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrsi x2, 320, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 320, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrsi x2, 320, 0b00000 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 320, 0b00101 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 320, 0b11010 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrci x2, 320, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_SEPC + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 321, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 321, x8 + li x8, 0xa5a5a5a5a5a5a5a5 + bne x8, x2, csr_fail + li x8, 0x10eae9ca00000000 + csrrw x2, 321, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 321, x8 + li x8, 0x10eae9ca00000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 321, x8 + li x8, 0xb5efedefa5a5a5a5 + bne x8, x2, csr_fail + li x8, 0x29bfeec300000000 + csrrs x2, 321, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 321, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 321, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0x57db1bcf00000000 + csrrc x2, 321, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 321, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 321, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrwi x2, 321, 0b00000 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrsi x2, 321, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 321, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrsi x2, 321, 0b00000 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 321, 0b00101 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 321, 0b11010 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrci x2, 321, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_SCAUSE + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 322, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 322, x8 + li x8, 0xa5a5a5a5a5a5a5a5 + bne x8, x2, csr_fail + li x8, 0xa5ea4b6f00000000 + csrrw x2, 322, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 322, x8 + li x8, 0xa5ea4b6f00000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 322, x8 + li x8, 0xa5efefefa5a5a5a5 + bne x8, x2, csr_fail + li x8, 0xac57fc4d00000000 + csrrs x2, 322, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 322, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 322, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0xd992986500000000 + csrrc x2, 322, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 322, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 322, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrwi x2, 322, 0b00000 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrsi x2, 322, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 322, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrsi x2, 322, 0b00000 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 322, 0b00101 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 322, 0b11010 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrci x2, 322, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_STVAL + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 323, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 323, x8 + li x8, 0xa5a5a5a5a5a5a5a5 + bne x8, x2, csr_fail + li x8, 0xe13d8fbf00000000 + csrrw x2, 323, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 323, x8 + li x8, 0xe13d8fbf00000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 323, x8 + li x8, 0xe5bdafbfa5a5a5a5 + bne x8, x2, csr_fail + li x8, 0x813ddd2d00000000 + csrrs x2, 323, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 323, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 323, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0x5ba8589200000000 + csrrc x2, 323, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 323, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 323, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrwi x2, 323, 0b00000 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrsi x2, 323, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 323, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrsi x2, 323, 0b00000 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 323, 0b00101 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 323, 0b11010 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrci x2, 323, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_SATP + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 384, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 384, x8 + li x8, 0xa5a5a5a5a5a5a5a5 + bne x8, x2, csr_fail + li x8, 0x32e2c6d000000000 + csrrw x2, 384, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 384, x8 + li x8, 0x32e2c6d000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 384, x8 + li x8, 0xb7e7e7f5a5a5a5a5 + bne x8, x2, csr_fail + li x8, 0xa97bc65d00000000 + csrrs x2, 384, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 384, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 384, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0x37ea95ef00000000 + csrrc x2, 384, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 384, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 384, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrwi x2, 384, 0b00000 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrsi x2, 384, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 384, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrsi x2, 384, 0b00000 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 384, 0b00101 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 384, 0b11010 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrci x2, 384, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_MSTATUS + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 768, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 768, x8 + li x8, 0x800000050025a1a1 + bne x8, x2, csr_fail + li x8, 0x08d67a3e00000000 + csrrw x2, 768, x8 + li x8, 0x0000000a005a581a + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 768, x8 + li x8, 0x0000000e00000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 768, x8 + li x8, 0x8000000f0025a1a1 + bne x8, x2, csr_fail + li x8, 0xbf42b48300000000 + csrrs x2, 768, x8 + li x8, 0x8000000f007ff9bb + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 768, x8 + li x8, 0x8000000f007ff9bb + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 768, x8 + li x8, 0x0000000a005a581a + bne x8, x2, csr_fail + li x8, 0x88f18be200000000 + csrrc x2, 768, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 768, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 768, 0b11010 + li x8, 0x0000000000000001 + bne x8, x2, csr_fail + csrrwi x2, 768, 0b00000 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrsi x2, 768, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 768, 0b11010 + li x8, 0x0000000000000001 + bne x8, x2, csr_fail + csrrsi x2, 768, 0b00000 + li x8, 0x000000000000001b + bne x8, x2, csr_fail + csrrci x2, 768, 0b00101 + li x8, 0x000000000000001b + bne x8, x2, csr_fail + csrrci x2, 768, 0b11010 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrci x2, 768, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_MISA + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 769, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 769, x8 + li x8, 0x8000000001a5a5a5 + bne x8, x2, csr_fail + li x8, 0xae6f634100000000 + csrrw x2, 769, x8 + li x8, 0x40000000025a5a5a + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 769, x8 + li x8, 0x8000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 769, x8 + li x8, 0x8000000001a5a5a5 + bne x8, x2, csr_fail + li x8, 0xc8885ab600000000 + csrrs x2, 769, x8 + li x8, 0xc000000003ffffff + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 769, x8 + li x8, 0xc000000003ffffff + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 769, x8 + li x8, 0x40000000025a5a5a + bne x8, x2, csr_fail + li x8, 0x91c631af00000000 + csrrc x2, 769, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 769, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 769, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrwi x2, 769, 0b00000 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrsi x2, 769, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 769, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrsi x2, 769, 0b00000 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 769, 0b00101 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 769, 0b11010 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrci x2, 769, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_MEDELEG + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 770, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 770, x8 + li x8, 0xa5a5a5a5a5a5a5a5 + bne x8, x2, csr_fail + li x8, 0x9bb07b9100000000 + csrrw x2, 770, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 770, x8 + li x8, 0x9bb07b9100000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 770, x8 + li x8, 0xbfb5ffb5a5a5a5a5 + bne x8, x2, csr_fail + li x8, 0x72f5108800000000 + csrrs x2, 770, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 770, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 770, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0x9a40d93600000000 + csrrc x2, 770, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 770, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 770, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrwi x2, 770, 0b00000 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrsi x2, 770, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 770, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrsi x2, 770, 0b00000 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 770, 0b00101 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 770, 0b11010 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrci x2, 770, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_MIDELEG + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 771, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 771, x8 + li x8, 0xa5a5a5a5a5a5a5a5 + bne x8, x2, csr_fail + li x8, 0xcd382f1d00000000 + csrrw x2, 771, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 771, x8 + li x8, 0xcd382f1d00000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 771, x8 + li x8, 0xedbdafbda5a5a5a5 + bne x8, x2, csr_fail + li x8, 0x8b1dd15200000000 + csrrs x2, 771, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 771, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 771, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0x1fe5449f00000000 + csrrc x2, 771, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 771, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 771, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrwi x2, 771, 0b00000 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrsi x2, 771, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 771, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrsi x2, 771, 0b00000 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 771, 0b00101 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 771, 0b11010 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrci x2, 771, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_MIE + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 772, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 772, x8 + li x8, 0x00000000000001a1 + bne x8, x2, csr_fail + li x8, 0x3dc0f6fd00000000 + csrrw x2, 772, x8 + li x8, 0x0000000000000a1a + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 772, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 772, x8 + li x8, 0x00000000000001a1 + bne x8, x2, csr_fail + li x8, 0x92a6f4b900000000 + csrrs x2, 772, x8 + li x8, 0x0000000000000bbb + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 772, x8 + li x8, 0x0000000000000bbb + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 772, x8 + li x8, 0x0000000000000a1a + bne x8, x2, csr_fail + li x8, 0x2dfebe8d00000000 + csrrc x2, 772, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 772, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 772, 0b11010 + li x8, 0x0000000000000001 + bne x8, x2, csr_fail + csrrwi x2, 772, 0b00000 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrsi x2, 772, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 772, 0b11010 + li x8, 0x0000000000000001 + bne x8, x2, csr_fail + csrrsi x2, 772, 0b00000 + li x8, 0x000000000000001b + bne x8, x2, csr_fail + csrrci x2, 772, 0b00101 + li x8, 0x000000000000001b + bne x8, x2, csr_fail + csrrci x2, 772, 0b11010 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrci x2, 772, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_MTVEC + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 773, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 773, x8 + li x8, 0xa5a5a5a5a5a5a5a5 + bne x8, x2, csr_fail + li x8, 0x1967e7b000000000 + csrrw x2, 773, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 773, x8 + li x8, 0x1967e7b000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 773, x8 + li x8, 0xbde7e7b5a5a5a5a5 + bne x8, x2, csr_fail + li x8, 0xc65e47d400000000 + csrrs x2, 773, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 773, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 773, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0x555ad4ed00000000 + csrrc x2, 773, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 773, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 773, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrwi x2, 773, 0b00000 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrsi x2, 773, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 773, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrsi x2, 773, 0b00000 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 773, 0b00101 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 773, 0b11010 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrci x2, 773, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_MCOUNTEREN + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 774, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 774, x8 + li x8, 0x00000000a5a5a5a5 + bne x8, x2, csr_fail + li x8, 0x14c5404400000000 + csrrw x2, 774, x8 + li x8, 0x000000005a5a5a5a + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 774, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 774, x8 + li x8, 0x00000000a5a5a5a5 + bne x8, x2, csr_fail + li x8, 0x4dfa458900000000 + csrrs x2, 774, x8 + li x8, 0x00000000ffffffff + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 774, x8 + li x8, 0x00000000ffffffff + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 774, x8 + li x8, 0x000000005a5a5a5a + bne x8, x2, csr_fail + li x8, 0xe4147e5e00000000 + csrrc x2, 774, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 774, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 774, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrwi x2, 774, 0b00000 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrsi x2, 774, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 774, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrsi x2, 774, 0b00000 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 774, 0b00101 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 774, 0b11010 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrci x2, 774, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_MSCRATCH + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 832, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 832, x8 + li x8, 0xa5a5a5a5a5a5a5a5 + bne x8, x2, csr_fail + li x8, 0x0e64a61700000000 + csrrw x2, 832, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 832, x8 + li x8, 0x0e64a61700000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 832, x8 + li x8, 0xafe5a7b7a5a5a5a5 + bne x8, x2, csr_fail + li x8, 0x7ca8ace800000000 + csrrs x2, 832, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 832, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 832, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0xef2952e300000000 + csrrc x2, 832, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 832, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 832, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrwi x2, 832, 0b00000 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrsi x2, 832, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 832, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrsi x2, 832, 0b00000 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 832, 0b00101 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 832, 0b11010 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrci x2, 832, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_MEPC + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 833, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 833, x8 + li x8, 0xa5a5a5a5a5a5a5a5 + bne x8, x2, csr_fail + li x8, 0x9e12971b00000000 + csrrw x2, 833, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 833, x8 + li x8, 0x9e12971b00000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 833, x8 + li x8, 0xbfb7b7bfa5a5a5a5 + bne x8, x2, csr_fail + li x8, 0xf514389b00000000 + csrrs x2, 833, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 833, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 833, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0x2b202d1900000000 + csrrc x2, 833, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 833, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 833, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrwi x2, 833, 0b00000 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrsi x2, 833, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 833, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrsi x2, 833, 0b00000 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 833, 0b00101 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 833, 0b11010 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrci x2, 833, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_MCAUSE + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 834, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 834, x8 + li x8, 0xa5a5a5a5a5a5a5a5 + bne x8, x2, csr_fail + li x8, 0x7db63f5900000000 + csrrw x2, 834, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 834, x8 + li x8, 0x7db63f5900000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 834, x8 + li x8, 0xfdb7bffda5a5a5a5 + bne x8, x2, csr_fail + li x8, 0x11c27b5c00000000 + csrrs x2, 834, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 834, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 834, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0xe5afe40200000000 + csrrc x2, 834, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 834, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 834, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrwi x2, 834, 0b00000 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrsi x2, 834, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 834, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrsi x2, 834, 0b00000 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 834, 0b00101 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 834, 0b11010 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrci x2, 834, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_MTVAL + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 835, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 835, x8 + li x8, 0xa5a5a5a5a5a5a5a5 + bne x8, x2, csr_fail + li x8, 0x5ebb79d400000000 + csrrw x2, 835, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 835, x8 + li x8, 0x5ebb79d400000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 835, x8 + li x8, 0xffbffdf5a5a5a5a5 + bne x8, x2, csr_fail + li x8, 0x7ec5c5fd00000000 + csrrs x2, 835, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 835, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 835, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0xd270bc0c00000000 + csrrc x2, 835, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 835, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 835, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrwi x2, 835, 0b00000 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrsi x2, 835, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 835, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrsi x2, 835, 0b00000 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 835, 0b00101 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 835, 0b11010 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrci x2, 835, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_MIP + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 836, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 836, x8 + li x8, 0x0000000000000121 + bne x8, x2, csr_fail + li x8, 0x9f7fdfc300000000 + csrrw x2, 836, x8 + li x8, 0x0000000000000212 + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 836, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 836, x8 + li x8, 0x0000000000000121 + bne x8, x2, csr_fail + li x8, 0xbcb82fc400000000 + csrrs x2, 836, x8 + li x8, 0x0000000000000333 + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 836, x8 + li x8, 0x0000000000000333 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 836, x8 + li x8, 0x0000000000000212 + bne x8, x2, csr_fail + li x8, 0x23cabd3e00000000 + csrrc x2, 836, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 836, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 836, 0b11010 + li x8, 0x0000000000000001 + bne x8, x2, csr_fail + csrrwi x2, 836, 0b00000 + li x8, 0x0000000000000012 + bne x8, x2, csr_fail + csrrsi x2, 836, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 836, 0b11010 + li x8, 0x0000000000000001 + bne x8, x2, csr_fail + csrrsi x2, 836, 0b00000 + li x8, 0x0000000000000013 + bne x8, x2, csr_fail + csrrci x2, 836, 0b00101 + li x8, 0x0000000000000013 + bne x8, x2, csr_fail + csrrci x2, 836, 0b11010 + li x8, 0x0000000000000012 + bne x8, x2, csr_fail + csrrci x2, 836, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_MVENDORID + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 3857, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 3857, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0xe1dbc3b600000000 + csrrw x2, 3857, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 3857, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 3857, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x8b421efb00000000 + csrrs x2, 3857, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 3857, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 3857, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0xf636b20900000000 + csrrc x2, 3857, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 3857, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 3857, 0b11010 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 3857, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 3857, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 3857, 0b11010 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 3857, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrci x2, 3857, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrci x2, 3857, 0b11010 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrci x2, 3857, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_MARCHID + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 3858, x8 + li x8, 0x0000000000000003 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 3858, x8 + li x8, 0x0000000000000003 + bne x8, x2, csr_fail + li x8, 0x20a99f2a00000000 + csrrw x2, 3858, x8 + li x8, 0x0000000000000003 + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 3858, x8 + li x8, 0x0000000000000003 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 3858, x8 + li x8, 0x0000000000000003 + bne x8, x2, csr_fail + li x8, 0x1ba648fc00000000 + csrrs x2, 3858, x8 + li x8, 0x0000000000000003 + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 3858, x8 + li x8, 0x0000000000000003 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 3858, x8 + li x8, 0x0000000000000003 + bne x8, x2, csr_fail + li x8, 0x887b030900000000 + csrrc x2, 3858, x8 + li x8, 0x0000000000000003 + bne x8, x2, csr_fail + csrrwi x2, 3858, 0b00101 + li x8, 0x0000000000000003 + bne x8, x2, csr_fail + csrrwi x2, 3858, 0b11010 + li x8, 0x0000000000000003 + bne x8, x2, csr_fail + csrrwi x2, 3858, 0b00000 + li x8, 0x0000000000000003 + bne x8, x2, csr_fail + csrrsi x2, 3858, 0b00101 + li x8, 0x0000000000000003 + bne x8, x2, csr_fail + csrrsi x2, 3858, 0b11010 + li x8, 0x0000000000000003 + bne x8, x2, csr_fail + csrrsi x2, 3858, 0b00000 + li x8, 0x0000000000000003 + bne x8, x2, csr_fail + csrrci x2, 3858, 0b00101 + li x8, 0x0000000000000003 + bne x8, x2, csr_fail + csrrci x2, 3858, 0b11010 + li x8, 0x0000000000000003 + bne x8, x2, csr_fail + csrrci x2, 3858, 0b00000 + li x8, 0x0000000000000003 + bne x8, x2, csr_fail + # CSR_MIMPID + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 3859, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 3859, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x9cc9750100000000 + csrrw x2, 3859, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 3859, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 3859, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0xd84481b100000000 + csrrs x2, 3859, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 3859, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 3859, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x3182b09d00000000 + csrrc x2, 3859, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 3859, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 3859, 0b11010 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 3859, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 3859, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 3859, 0b11010 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 3859, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrci x2, 3859, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrci x2, 3859, 0b11010 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrci x2, 3859, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_MHARTID + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 3860, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 3860, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x775d905300000000 + csrrw x2, 3860, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 3860, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 3860, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x23f0bb3200000000 + csrrs x2, 3860, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 3860, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 3860, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x3e594efe00000000 + csrrc x2, 3860, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 3860, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 3860, 0b11010 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 3860, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 3860, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 3860, 0b11010 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 3860, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrci x2, 3860, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrci x2, 3860, 0b11010 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrci x2, 3860, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_MCYCLE + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 2816, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 2816, x8 + li x8, 0xa5a5a5a5a5a5a5a5 + bne x8, x2, csr_fail + li x8, 0xa0e42def00000000 + csrrw x2, 2816, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 2816, x8 + li x8, 0xa0e42def00000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 2816, x8 + li x8, 0xa5e5adefa5a5a5a5 + bne x8, x2, csr_fail + li x8, 0xafc50dc000000000 + csrrs x2, 2816, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 2816, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 2816, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0xf135c37b00000000 + csrrc x2, 2816, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 2816, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 2816, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrwi x2, 2816, 0b00000 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrsi x2, 2816, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 2816, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrsi x2, 2816, 0b00000 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 2816, 0b00101 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 2816, 0b11010 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrci x2, 2816, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_MINSTRET + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 2818, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 2818, x8 + li x8, 0xa5a5a5a5a5a5a5a5 + bne x8, x2, csr_fail + li x8, 0x9cf2093c00000000 + csrrw x2, 2818, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 2818, x8 + li x8, 0x9cf2093c00000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 2818, x8 + li x8, 0xbdf7adbda5a5a5a5 + bne x8, x2, csr_fail + li x8, 0xd22102e400000000 + csrrs x2, 2818, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 2818, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 2818, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0x85cee42b00000000 + csrrc x2, 2818, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 2818, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 2818, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrwi x2, 2818, 0b00000 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrsi x2, 2818, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 2818, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrsi x2, 2818, 0b00000 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 2818, 0b00101 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 2818, 0b11010 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrci x2, 2818, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_GPC1 + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 2819, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 2819, x8 + li x8, 0xa5a5a5a5a5a5a5a5 + bne x8, x2, csr_fail + li x8, 0xbaefdace00000000 + csrrw x2, 2819, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 2819, x8 + li x8, 0xbaefdace00000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 2819, x8 + li x8, 0xbfefffefa5a5a5a5 + bne x8, x2, csr_fail + li x8, 0xc3945e1700000000 + csrrs x2, 2819, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 2819, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 2819, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0xa1ac3d8900000000 + csrrc x2, 2819, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 2819, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 2819, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrwi x2, 2819, 0b00000 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrsi x2, 2819, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 2819, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrsi x2, 2819, 0b00000 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 2819, 0b00101 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 2819, 0b11010 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrci x2, 2819, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_GPC2 + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 2820, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 2820, x8 + li x8, 0xa5a5a5a5a5a5a5a5 + bne x8, x2, csr_fail + li x8, 0x1d75d81600000000 + csrrw x2, 2820, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 2820, x8 + li x8, 0x1d75d81600000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 2820, x8 + li x8, 0xbdf5fdb7a5a5a5a5 + bne x8, x2, csr_fail + li x8, 0x060f115400000000 + csrrs x2, 2820, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 2820, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 2820, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0xb2b602cb00000000 + csrrc x2, 2820, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 2820, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 2820, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrwi x2, 2820, 0b00000 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrsi x2, 2820, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 2820, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrsi x2, 2820, 0b00000 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 2820, 0b00101 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 2820, 0b11010 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrci x2, 2820, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_GPC3 + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 2821, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 2821, x8 + li x8, 0xa5a5a5a5a5a5a5a5 + bne x8, x2, csr_fail + li x8, 0x698e39dd00000000 + csrrw x2, 2821, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 2821, x8 + li x8, 0x698e39dd00000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 2821, x8 + li x8, 0xedafbdfda5a5a5a5 + bne x8, x2, csr_fail + li x8, 0x816400f800000000 + csrrs x2, 2821, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 2821, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 2821, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0x43a192de00000000 + csrrc x2, 2821, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 2821, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 2821, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrwi x2, 2821, 0b00000 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrsi x2, 2821, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 2821, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrsi x2, 2821, 0b00000 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 2821, 0b00101 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 2821, 0b11010 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrci x2, 2821, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_GPC4 + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 2822, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 2822, x8 + li x8, 0xa5a5a5a5a5a5a5a5 + bne x8, x2, csr_fail + li x8, 0xce0d698500000000 + csrrw x2, 2822, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 2822, x8 + li x8, 0xce0d698500000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 2822, x8 + li x8, 0xefadeda5a5a5a5a5 + bne x8, x2, csr_fail + li x8, 0x874e247e00000000 + csrrs x2, 2822, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 2822, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 2822, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0x8eace03900000000 + csrrc x2, 2822, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 2822, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 2822, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrwi x2, 2822, 0b00000 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrsi x2, 2822, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 2822, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrsi x2, 2822, 0b00000 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 2822, 0b00101 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 2822, 0b11010 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrci x2, 2822, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_GPC5 + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 2823, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 2823, x8 + li x8, 0xa5a5a5a5a5a5a5a5 + bne x8, x2, csr_fail + li x8, 0x9111408000000000 + csrrw x2, 2823, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 2823, x8 + li x8, 0x9111408000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 2823, x8 + li x8, 0xb5b5e5a5a5a5a5a5 + bne x8, x2, csr_fail + li x8, 0x745ebc0300000000 + csrrs x2, 2823, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 2823, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 2823, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0x8a1de30d00000000 + csrrc x2, 2823, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 2823, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 2823, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrwi x2, 2823, 0b00000 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrsi x2, 2823, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 2823, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrsi x2, 2823, 0b00000 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 2823, 0b00101 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 2823, 0b11010 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrci x2, 2823, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_GPC6 + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 2824, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 2824, x8 + li x8, 0xa5a5a5a5a5a5a5a5 + bne x8, x2, csr_fail + li x8, 0x87a1152600000000 + csrrw x2, 2824, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 2824, x8 + li x8, 0x87a1152600000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 2824, x8 + li x8, 0xa7a5b5a7a5a5a5a5 + bne x8, x2, csr_fail + li x8, 0xa4f0a8fb00000000 + csrrs x2, 2824, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 2824, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 2824, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0xbaa5423a00000000 + csrrc x2, 2824, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 2824, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 2824, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrwi x2, 2824, 0b00000 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrsi x2, 2824, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 2824, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrsi x2, 2824, 0b00000 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 2824, 0b00101 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 2824, 0b11010 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrci x2, 2824, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_GPC1_PMES + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 803, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 803, x8 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + li x8, 0x4f1036fa00000000 + csrrw x2, 803, x8 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 803, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 803, x8 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + li x8, 0xbc2b3bd200000000 + csrrs x2, 803, x8 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 803, x8 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 803, x8 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + li x8, 0x9ee7260600000000 + csrrc x2, 803, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 803, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 803, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrwi x2, 803, 0b00000 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrsi x2, 803, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 803, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrsi x2, 803, 0b00000 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 803, 0b00101 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 803, 0b11010 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrci x2, 803, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_GPC2_PMES + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 804, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 804, x8 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + li x8, 0x726443bb00000000 + csrrw x2, 804, x8 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 804, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 804, x8 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + li x8, 0xb1f56a7700000000 + csrrs x2, 804, x8 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 804, x8 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 804, x8 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + li x8, 0x55391e9700000000 + csrrc x2, 804, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 804, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 804, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrwi x2, 804, 0b00000 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrsi x2, 804, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 804, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrsi x2, 804, 0b00000 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 804, 0b00101 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 804, 0b11010 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrci x2, 804, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_GPC3_PMES + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 805, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 805, x8 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + li x8, 0x7ca0f89e00000000 + csrrw x2, 805, x8 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 805, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 805, x8 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + li x8, 0x38c607d900000000 + csrrs x2, 805, x8 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 805, x8 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 805, x8 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + li x8, 0xbf55b5ae00000000 + csrrc x2, 805, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 805, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 805, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrwi x2, 805, 0b00000 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrsi x2, 805, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 805, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrsi x2, 805, 0b00000 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 805, 0b00101 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 805, 0b11010 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrci x2, 805, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_GPC4_PMES + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 806, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 806, x8 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + li x8, 0xe9964fd600000000 + csrrw x2, 806, x8 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 806, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 806, x8 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + li x8, 0xe48b060300000000 + csrrs x2, 806, x8 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 806, x8 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 806, x8 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + li x8, 0xe3a1f16300000000 + csrrc x2, 806, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 806, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 806, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrwi x2, 806, 0b00000 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrsi x2, 806, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 806, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrsi x2, 806, 0b00000 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 806, 0b00101 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 806, 0b11010 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrci x2, 806, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_GPC5_PMES + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 807, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 807, x8 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + li x8, 0x71f0594d00000000 + csrrw x2, 807, x8 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 807, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 807, x8 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + li x8, 0x514b4f1100000000 + csrrs x2, 807, x8 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 807, x8 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 807, x8 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + li x8, 0x96d5f5eb00000000 + csrrc x2, 807, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 807, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 807, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrwi x2, 807, 0b00000 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrsi x2, 807, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 807, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrsi x2, 807, 0b00000 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 807, 0b00101 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 807, 0b11010 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrci x2, 807, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_GPC6_PMES + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 808, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 808, x8 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + li x8, 0xceedcb5500000000 + csrrw x2, 808, x8 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 808, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 808, x8 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + li x8, 0x413b7ab800000000 + csrrs x2, 808, x8 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 808, x8 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 808, x8 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + li x8, 0xef9e8a7b00000000 + csrrc x2, 808, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 808, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 808, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrwi x2, 808, 0b00000 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrsi x2, 808, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 808, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrsi x2, 808, 0b00000 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 808, 0b00101 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 808, 0b11010 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrci x2, 808, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_ICACHE + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 1984, x8 + li x8, 0x0000000000000001 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 1984, x8 + li x8, 0x0000000000000001 + bne x8, x2, csr_fail + li x8, 0xf190fb6900000000 + csrrw x2, 1984, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 1984, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 1984, x8 + li x8, 0x0000000000000001 + bne x8, x2, csr_fail + li x8, 0xd7da3f2900000000 + csrrs x2, 1984, x8 + li x8, 0x0000000000000001 + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 1984, x8 + li x8, 0x0000000000000001 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 1984, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0xee5cf8ae00000000 + csrrc x2, 1984, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 1984, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 1984, 0b11010 + li x8, 0x0000000000000001 + bne x8, x2, csr_fail + csrrwi x2, 1984, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 1984, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 1984, 0b11010 + li x8, 0x0000000000000001 + bne x8, x2, csr_fail + csrrsi x2, 1984, 0b00000 + li x8, 0x0000000000000001 + bne x8, x2, csr_fail + csrrci x2, 1984, 0b00101 + li x8, 0x0000000000000001 + bne x8, x2, csr_fail + csrrci x2, 1984, 0b11010 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrci x2, 1984, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_DCACHE + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 1985, x8 + li x8, 0x0000000000000001 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 1985, x8 + li x8, 0x0000000000000001 + bne x8, x2, csr_fail + li x8, 0x1c68d91500000000 + csrrw x2, 1985, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 1985, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 1985, x8 + li x8, 0x0000000000000001 + bne x8, x2, csr_fail + li x8, 0xe982ae6100000000 + csrrs x2, 1985, x8 + li x8, 0x0000000000000001 + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 1985, x8 + li x8, 0x0000000000000001 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 1985, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x3dbd1fed00000000 + csrrc x2, 1985, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 1985, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 1985, 0b11010 + li x8, 0x0000000000000001 + bne x8, x2, csr_fail + csrrwi x2, 1985, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 1985, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 1985, 0b11010 + li x8, 0x0000000000000001 + bne x8, x2, csr_fail + csrrsi x2, 1985, 0b00000 + li x8, 0x0000000000000001 + bne x8, x2, csr_fail + csrrci x2, 1985, 0b00101 + li x8, 0x0000000000000001 + bne x8, x2, csr_fail + csrrci x2, 1985, 0b11010 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrci x2, 1985, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_PMPCFG0 + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 928, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 928, x8 + li x8, 0xa5a5a5a5a5a5a5a5 + bne x8, x2, csr_fail + li x8, 0x8b043fda00000000 + csrrw x2, 928, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 928, x8 + li x8, 0x8b043fda00000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 928, x8 + li x8, 0xafa5bfffa5a5a5a5 + bne x8, x2, csr_fail + li x8, 0x2dc0e34700000000 + csrrs x2, 928, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 928, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 928, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0x04aa2b7300000000 + csrrc x2, 928, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 928, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 928, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrwi x2, 928, 0b00000 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrsi x2, 928, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 928, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrsi x2, 928, 0b00000 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 928, 0b00101 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 928, 0b11010 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrci x2, 928, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_PMPCFG2 + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 930, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 930, x8 + li x8, 0xa5a5a5a5a5a5a5a5 + bne x8, x2, csr_fail + li x8, 0xdf417a4a00000000 + csrrw x2, 930, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 930, x8 + li x8, 0xdf417a4a00000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 930, x8 + li x8, 0xffe5ffefa5a5a5a5 + bne x8, x2, csr_fail + li x8, 0x4253342300000000 + csrrs x2, 930, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 930, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 930, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0xc82e8b7800000000 + csrrc x2, 930, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 930, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 930, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrwi x2, 930, 0b00000 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrsi x2, 930, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 930, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrsi x2, 930, 0b00000 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 930, 0b00101 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 930, 0b11010 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrci x2, 930, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_PMPADDR0 + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 944, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 944, x8 + li x8, 0xa5a5a5a5a5a5a5a5 + bne x8, x2, csr_fail + li x8, 0xf0d6a74300000000 + csrrw x2, 944, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 944, x8 + li x8, 0xf0d6a74300000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 944, x8 + li x8, 0xf5f7a7e7a5a5a5a5 + bne x8, x2, csr_fail + li x8, 0xda5c19aa00000000 + csrrs x2, 944, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 944, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 944, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0x2bb0431a00000000 + csrrc x2, 944, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 944, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 944, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrwi x2, 944, 0b00000 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrsi x2, 944, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 944, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrsi x2, 944, 0b00000 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 944, 0b00101 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 944, 0b11010 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrci x2, 944, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_PMPADDR1 + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 945, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 945, x8 + li x8, 0xa5a5a5a5a5a5a5a5 + bne x8, x2, csr_fail + li x8, 0x6b6a6c6f00000000 + csrrw x2, 945, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 945, x8 + li x8, 0x6b6a6c6f00000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 945, x8 + li x8, 0xefefedefa5a5a5a5 + bne x8, x2, csr_fail + li x8, 0x445dfddb00000000 + csrrs x2, 945, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 945, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 945, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0xc6ba0b2a00000000 + csrrc x2, 945, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 945, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 945, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrwi x2, 945, 0b00000 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrsi x2, 945, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 945, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrsi x2, 945, 0b00000 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 945, 0b00101 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 945, 0b11010 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrci x2, 945, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_PMPADDR2 + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 946, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 946, x8 + li x8, 0xa5a5a5a5a5a5a5a5 + bne x8, x2, csr_fail + li x8, 0x7812cec300000000 + csrrw x2, 946, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 946, x8 + li x8, 0x7812cec300000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 946, x8 + li x8, 0xfdb7efe7a5a5a5a5 + bne x8, x2, csr_fail + li x8, 0xb829146e00000000 + csrrs x2, 946, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 946, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 946, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0x97f2b76200000000 + csrrc x2, 946, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 946, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 946, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrwi x2, 946, 0b00000 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrsi x2, 946, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 946, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrsi x2, 946, 0b00000 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 946, 0b00101 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 946, 0b11010 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrci x2, 946, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_PMPADDR3 + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 947, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 947, x8 + li x8, 0xa5a5a5a5a5a5a5a5 + bne x8, x2, csr_fail + li x8, 0xf25bc7c000000000 + csrrw x2, 947, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 947, x8 + li x8, 0xf25bc7c000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 947, x8 + li x8, 0xf7ffe7e5a5a5a5a5 + bne x8, x2, csr_fail + li x8, 0xc965dea600000000 + csrrs x2, 947, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 947, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 947, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0xe998675200000000 + csrrc x2, 947, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 947, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 947, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrwi x2, 947, 0b00000 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrsi x2, 947, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 947, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrsi x2, 947, 0b00000 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 947, 0b00101 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 947, 0b11010 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrci x2, 947, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_PMPADDR4 + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 948, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 948, x8 + li x8, 0xa5a5a5a5a5a5a5a5 + bne x8, x2, csr_fail + li x8, 0x50d1af6900000000 + csrrw x2, 948, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 948, x8 + li x8, 0x50d1af6900000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 948, x8 + li x8, 0xf5f5afeda5a5a5a5 + bne x8, x2, csr_fail + li x8, 0x57b2595900000000 + csrrs x2, 948, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 948, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 948, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0x834549b500000000 + csrrc x2, 948, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 948, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 948, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrwi x2, 948, 0b00000 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrsi x2, 948, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 948, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrsi x2, 948, 0b00000 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 948, 0b00101 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 948, 0b11010 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrci x2, 948, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_PMPADDR5 + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 949, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 949, x8 + li x8, 0xa5a5a5a5a5a5a5a5 + bne x8, x2, csr_fail + li x8, 0x2a7916fc00000000 + csrrw x2, 949, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 949, x8 + li x8, 0x2a7916fc00000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 949, x8 + li x8, 0xaffdb7fda5a5a5a5 + bne x8, x2, csr_fail + li x8, 0x83e8428100000000 + csrrs x2, 949, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 949, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 949, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0x9e7537f500000000 + csrrc x2, 949, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 949, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 949, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrwi x2, 949, 0b00000 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrsi x2, 949, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 949, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrsi x2, 949, 0b00000 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 949, 0b00101 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 949, 0b11010 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrci x2, 949, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_PMPADDR6 + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 950, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 950, x8 + li x8, 0xa5a5a5a5a5a5a5a5 + bne x8, x2, csr_fail + li x8, 0xa019770a00000000 + csrrw x2, 950, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 950, x8 + li x8, 0xa019770a00000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 950, x8 + li x8, 0xa5bdf7afa5a5a5a5 + bne x8, x2, csr_fail + li x8, 0xb73ee83e00000000 + csrrs x2, 950, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 950, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 950, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0x5f59ad5800000000 + csrrc x2, 950, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 950, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 950, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrwi x2, 950, 0b00000 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrsi x2, 950, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 950, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrsi x2, 950, 0b00000 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 950, 0b00101 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 950, 0b11010 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrci x2, 950, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_PMPADDR7 + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 951, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 951, x8 + li x8, 0xa5a5a5a5a5a5a5a5 + bne x8, x2, csr_fail + li x8, 0x341b018c00000000 + csrrw x2, 951, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 951, x8 + li x8, 0x341b018c00000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 951, x8 + li x8, 0xb5bfa5ada5a5a5a5 + bne x8, x2, csr_fail + li x8, 0xf0ca8e4500000000 + csrrs x2, 951, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 951, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 951, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0x7efbc56700000000 + csrrc x2, 951, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 951, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 951, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrwi x2, 951, 0b00000 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrsi x2, 951, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 951, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrsi x2, 951, 0b00000 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 951, 0b00101 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 951, 0b11010 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrci x2, 951, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_PMPADDR8 + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 952, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 952, x8 + li x8, 0xa5a5a5a5a5a5a5a5 + bne x8, x2, csr_fail + li x8, 0x1d68f5b000000000 + csrrw x2, 952, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 952, x8 + li x8, 0x1d68f5b000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 952, x8 + li x8, 0xbdedf5b5a5a5a5a5 + bne x8, x2, csr_fail + li x8, 0x6cd7a49d00000000 + csrrs x2, 952, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 952, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 952, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0x0b5b0ac200000000 + csrrc x2, 952, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 952, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 952, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrwi x2, 952, 0b00000 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrsi x2, 952, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 952, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrsi x2, 952, 0b00000 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 952, 0b00101 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 952, 0b11010 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrci x2, 952, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_PMPADDR9 + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 953, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 953, x8 + li x8, 0xa5a5a5a5a5a5a5a5 + bne x8, x2, csr_fail + li x8, 0x3f06fb1d00000000 + csrrw x2, 953, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 953, x8 + li x8, 0x3f06fb1d00000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 953, x8 + li x8, 0xbfa7ffbda5a5a5a5 + bne x8, x2, csr_fail + li x8, 0x478bf3cc00000000 + csrrs x2, 953, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 953, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 953, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0x9d08f95300000000 + csrrc x2, 953, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 953, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 953, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrwi x2, 953, 0b00000 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrsi x2, 953, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 953, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrsi x2, 953, 0b00000 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 953, 0b00101 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 953, 0b11010 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrci x2, 953, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_PMPADDR10 + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 954, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 954, x8 + li x8, 0xa5a5a5a5a5a5a5a5 + bne x8, x2, csr_fail + li x8, 0xa672433800000000 + csrrw x2, 954, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 954, x8 + li x8, 0xa672433800000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 954, x8 + li x8, 0xa7f7e7bda5a5a5a5 + bne x8, x2, csr_fail + li x8, 0xb818918300000000 + csrrs x2, 954, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 954, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 954, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0x5090c63b00000000 + csrrc x2, 954, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 954, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 954, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrwi x2, 954, 0b00000 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrsi x2, 954, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 954, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrsi x2, 954, 0b00000 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 954, 0b00101 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 954, 0b11010 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrci x2, 954, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_PMPADDR11 + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 955, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 955, x8 + li x8, 0xa5a5a5a5a5a5a5a5 + bne x8, x2, csr_fail + li x8, 0xbf12713e00000000 + csrrw x2, 955, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 955, x8 + li x8, 0xbf12713e00000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 955, x8 + li x8, 0xbfb7f5bfa5a5a5a5 + bne x8, x2, csr_fail + li x8, 0x06bba5c300000000 + csrrs x2, 955, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 955, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 955, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0x67ebeac400000000 + csrrc x2, 955, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 955, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 955, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrwi x2, 955, 0b00000 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrsi x2, 955, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 955, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrsi x2, 955, 0b00000 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 955, 0b00101 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 955, 0b11010 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrci x2, 955, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_PMPADDR12 + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 956, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 956, x8 + li x8, 0xa5a5a5a5a5a5a5a5 + bne x8, x2, csr_fail + li x8, 0x84a9f27d00000000 + csrrw x2, 956, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 956, x8 + li x8, 0x84a9f27d00000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 956, x8 + li x8, 0xa5adf7fda5a5a5a5 + bne x8, x2, csr_fail + li x8, 0xf872a5ea00000000 + csrrs x2, 956, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 956, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 956, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0x47cb14e400000000 + csrrc x2, 956, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 956, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 956, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrwi x2, 956, 0b00000 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrsi x2, 956, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 956, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrsi x2, 956, 0b00000 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 956, 0b00101 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 956, 0b11010 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrci x2, 956, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_PMPADDR13 + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 957, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 957, x8 + li x8, 0xa5a5a5a5a5a5a5a5 + bne x8, x2, csr_fail + li x8, 0xa68c906a00000000 + csrrw x2, 957, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 957, x8 + li x8, 0xa68c906a00000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 957, x8 + li x8, 0xa7adb5efa5a5a5a5 + bne x8, x2, csr_fail + li x8, 0xbb09153100000000 + csrrs x2, 957, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 957, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 957, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0x998cad8a00000000 + csrrc x2, 957, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 957, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 957, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrwi x2, 957, 0b00000 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrsi x2, 957, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 957, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrsi x2, 957, 0b00000 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 957, 0b00101 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 957, 0b11010 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrci x2, 957, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_PMPADDR14 + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 958, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 958, x8 + li x8, 0xa5a5a5a5a5a5a5a5 + bne x8, x2, csr_fail + li x8, 0xb94aeeae00000000 + csrrw x2, 958, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 958, x8 + li x8, 0xb94aeeae00000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 958, x8 + li x8, 0xbdefefafa5a5a5a5 + bne x8, x2, csr_fail + li x8, 0x363a565d00000000 + csrrs x2, 958, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 958, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 958, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0x3396cd0a00000000 + csrrc x2, 958, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 958, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 958, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrwi x2, 958, 0b00000 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrsi x2, 958, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 958, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrsi x2, 958, 0b00000 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 958, 0b00101 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 958, 0b11010 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrci x2, 958, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_PMPADDR15 + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 959, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 959, x8 + li x8, 0xa5a5a5a5a5a5a5a5 + bne x8, x2, csr_fail + li x8, 0xfddfcf7200000000 + csrrw x2, 959, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 959, x8 + li x8, 0xfddfcf7200000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 959, x8 + li x8, 0xfdffeff7a5a5a5a5 + bne x8, x2, csr_fail + li x8, 0xcdbde87600000000 + csrrs x2, 959, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 959, x8 + li x8, 0xffffffffffffffff + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 959, x8 + li x8, 0x5a5a5a5a5a5a5a5a + bne x8, x2, csr_fail + li x8, 0x46b4750f00000000 + csrrc x2, 959, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 959, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 959, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrwi x2, 959, 0b00000 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrsi x2, 959, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 959, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrsi x2, 959, 0b00000 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 959, 0b00101 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 959, 0b11010 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrci x2, 959, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_FFLAGS + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 1, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 1, x8 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + li x8, 0xe40c213400000000 + csrrw x2, 1, x8 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 1, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 1, x8 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + li x8, 0x88d2628300000000 + csrrs x2, 1, x8 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 1, x8 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 1, x8 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + li x8, 0xba2cefdd00000000 + csrrc x2, 1, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 1, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 1, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrwi x2, 1, 0b00000 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrsi x2, 1, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 1, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrsi x2, 1, 0b00000 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 1, 0b00101 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 1, 0b11010 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrci x2, 1, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_FRM + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 2, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 2, x8 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + li x8, 0x80391db800000000 + csrrw x2, 2, x8 + li x8, 0x0000000000000002 + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 2, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 2, x8 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + li x8, 0x650e22d800000000 + csrrs x2, 2, x8 + li x8, 0x0000000000000007 + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 2, x8 + li x8, 0x0000000000000007 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 2, x8 + li x8, 0x0000000000000002 + bne x8, x2, csr_fail + li x8, 0x8e7229c000000000 + csrrc x2, 2, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 2, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 2, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrwi x2, 2, 0b00000 + li x8, 0x0000000000000002 + bne x8, x2, csr_fail + csrrsi x2, 2, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 2, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrsi x2, 2, 0b00000 + li x8, 0x0000000000000007 + bne x8, x2, csr_fail + csrrci x2, 2, 0b00101 + li x8, 0x0000000000000007 + bne x8, x2, csr_fail + csrrci x2, 2, 0b11010 + li x8, 0x0000000000000002 + bne x8, x2, csr_fail + csrrci x2, 2, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_FCSR + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 3, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 3, x8 + li x8, 0x00000000000000a5 + bne x8, x2, csr_fail + li x8, 0xa0aca67100000000 + csrrw x2, 3, x8 + li x8, 0x000000000000005a + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 3, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 3, x8 + li x8, 0x00000000000000a5 + bne x8, x2, csr_fail + li x8, 0xcb1fba7f00000000 + csrrs x2, 3, x8 + li x8, 0x00000000000000ff + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 3, x8 + li x8, 0x00000000000000ff + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 3, x8 + li x8, 0x000000000000005a + bne x8, x2, csr_fail + li x8, 0x1a4e8cb300000000 + csrrc x2, 3, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 3, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 3, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrwi x2, 3, 0b00000 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrsi x2, 3, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 3, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrsi x2, 3, 0b00000 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 3, 0b00101 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 3, 0b11010 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrci x2, 3, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_FTRAN + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 2048, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 2048, x8 + li x8, 0x0000000000000025 + bne x8, x2, csr_fail + li x8, 0xcb9ab24000000000 + csrrw x2, 2048, x8 + li x8, 0x000000000000005a + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 2048, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 2048, x8 + li x8, 0x0000000000000025 + bne x8, x2, csr_fail + li x8, 0x0739cab000000000 + csrrs x2, 2048, x8 + li x8, 0x000000000000007f + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 2048, x8 + li x8, 0x000000000000007f + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 2048, x8 + li x8, 0x000000000000005a + bne x8, x2, csr_fail + li x8, 0xe2580c7600000000 + csrrc x2, 2048, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 2048, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 2048, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrwi x2, 2048, 0b00000 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrsi x2, 2048, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 2048, 0b11010 + li x8, 0x0000000000000005 + bne x8, x2, csr_fail + csrrsi x2, 2048, 0b00000 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 2048, 0b00101 + li x8, 0x000000000000001f + bne x8, x2, csr_fail + csrrci x2, 2048, 0b11010 + li x8, 0x000000000000001a + bne x8, x2, csr_fail + csrrci x2, 2048, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_CYCLE + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 3072, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 3072, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x9f03938c00000000 + csrrw x2, 3072, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 3072, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 3072, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x1b2589b700000000 + csrrs x2, 3072, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 3072, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 3072, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x1e9235bf00000000 + csrrc x2, 3072, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 3072, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 3072, 0b11010 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 3072, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 3072, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 3072, 0b11010 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 3072, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrci x2, 3072, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrci x2, 3072, 0b11010 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrci x2, 3072, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + # CSR_INSTRET + li x8, 0xa5a5a5a5a5a5a5a5 + csrrw x2, 3074, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrw x2, 3074, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x8485906a00000000 + csrrw x2, 3074, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrs x2, 3074, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrs x2, 3074, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x936661ee00000000 + csrrs x2, 3074, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0xa5a5a5a5a5a5a5a5 + csrrc x2, 3074, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0x5a5a5a5a5a5a5a5a + csrrc x2, 3074, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + li x8, 0xa185710900000000 + csrrc x2, 3074, x8 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 3074, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 3074, 0b11010 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrwi x2, 3074, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 3074, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 3074, 0b11010 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrsi x2, 3074, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrci x2, 3074, 0b00101 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrci x2, 3074, 0b11010 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrrci x2, 3074, 0b00000 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + csrr x2, 3074 + li x8, 0x0000000000000000 + bne x8, x2, csr_fail + + +csr_pass: + li x18, 123456789 + li x17, 0x60000000 + sw x18,0(x17) + wfi + +csr_fail: + li x18, 1 + li x17, 0x60000000 + sw x18,0(x17) + wfi + diff --git a/verif/tests/custom/common/syscalls.c b/verif/tests/custom/common/syscalls.c new file mode 100644 index 0000000000..ebb9a87275 --- /dev/null +++ b/verif/tests/custom/common/syscalls.c @@ -0,0 +1,521 @@ +// See LICENSE for license details. + +#include <stdint.h> +#include <string.h> +#include <stdarg.h> +#include <stdio.h> +#include <limits.h> +#include <sys/signal.h> +#include "util.h" + +#define SYS_write 64 + +#undef strcmp + +extern volatile uint64_t tohost; +extern volatile uint64_t fromhost; + +// tohost is 64 bits wide, irrespective of XLEN. The structure expected in Spike is: +// - tohost[63:56] == device (syscall: 0) +// - tohost[55:48] == command (syscall: 0) +// - tohost[47:0] == payload (syscall: address of magic_mem) +// +// magic_mem for a syscall contains the following elements (XLEN bits each) +// - syscall index (93 dec for syscall_exit, cf. Spike values in +// riscv-isa-sim/fesvr/syscall.cc:140 and ff.) +// - syscall args in the declaration order of the given syscall + +static uintptr_t syscall(uintptr_t which, uintptr_t arg0, uintptr_t arg1, uintptr_t arg2) +{ + // Arguments in magic_mem have XLEN bits each. + volatile uintptr_t magic_mem[8] __attribute__((aligned(64))); + magic_mem[0] = which; + magic_mem[1] = arg0; + magic_mem[2] = arg1; + magic_mem[3] = arg2; +#ifdef __riscv_atomic // __sync_synchronize requires A extension + __sync_synchronize(); +#endif + + // A WRITE_MEM transaction writing non-zero value to TOHOST triggers + // the environment (Spike or RTL harness). + // - here tohost is guaranteed non-NULL because magic_mem is a valid RISC-V + // pointer. + // - the environment acknowledges the env request by writing 0 into tohost. + // - the completion of the request is signalled by the environment through + // a write of a non-zero value into fromhost. + tohost = (((uint64_t) ((unsigned long int) magic_mem)) << 16) >> 16; // clear the DEV and CMD bytes, clip payload. + while (fromhost == 0) + ; + fromhost = 0; + +#ifdef __riscv_atomic // __sync_synchronize requires A extension + __sync_synchronize(); +#endif + return magic_mem[0]; +} + +#define NUM_COUNTERS 2 +static uintptr_t counters[NUM_COUNTERS]; +static char* counter_names[NUM_COUNTERS]; + +void setStats(int enable) +{ + int i = 0; +#define READ_CTR(name) do { \ + while (i >= NUM_COUNTERS) ; \ + uintptr_t csr = read_csr(name); \ + if (!enable) { csr -= counters[i]; counter_names[i] = #name; } \ + counters[i++] = csr; \ + } while (0) + + READ_CTR(mcycle); + READ_CTR(minstret); + +#undef READ_CTR +} + +uintptr_t getStats(int counterid) +{ + return counters[counterid]; +} + +void __attribute__((noreturn)) tohost_exit(uintptr_t code) +{ + // Simply write PASS/FAIL result into 'tohost'. + // Left shift 'code' by 1 and set bit 0 to 1, but leave the 16 uppermost bits clear + // so that the syscall is properly recognized even if 'code' value is very large. + tohost = ((((uint64_t) code) << 17) >> 16) | 1; + + // Do not care about the value returned by host. + // Leave 1 cycle of slack (one NOP instruction) to help debugging + // the termination mechanism if needed. + __asm__("nop\n\t"); + + // Go into an endless loop if the write into 'tohost' did not terminate the simulation. + while (1); +} + +uintptr_t __attribute__((weak)) handle_trap(uintptr_t cause, uintptr_t epc, uintptr_t regs[32]) +{ + tohost_exit(1337); +} + +void exit(int code) +{ + tohost_exit(code); +} + +void abort() +{ + exit(128 + SIGABRT); +} + +void printstr(const char* s) +{ +#if !NOPRINT + syscall(SYS_write, 1, (uintptr_t)s, strlen(s)); +#endif +} + +void __attribute__((weak)) thread_entry(int cid, int nc) +{ + // multi-threaded programs override this function. + // for the case of single-threaded programs, only let core 0 proceed. + while (cid != 0); +} + +int __attribute__((weak)) main(int argc, char** argv) +{ + // single-threaded programs override this function. + printstr("Implement main(), foo!\n"); + return -1; +} + +static void init_tls() +{ + register void* thread_pointer asm("tp"); + extern char _tdata_begin, _tdata_end, _tbss_end; + size_t tdata_size = &_tdata_end - &_tdata_begin; + memcpy(thread_pointer, &_tdata_begin, tdata_size); + size_t tbss_size = &_tbss_end - &_tdata_end; + memset(thread_pointer + tdata_size, 0, tbss_size); +} + +void _init(int cid, int nc) +{ + init_tls(); + thread_entry(cid, nc); + + // only single-threaded programs should ever get here. + int ret = main(0, 0); + + char buf[NUM_COUNTERS * 32] __attribute__((aligned(64))); + char* pbuf = buf; + for (int i = 0; i < NUM_COUNTERS; i++) + if (counters[i]) + pbuf += sprintf(pbuf, "%s = %d\n", counter_names[i], counters[i]); + if (pbuf != buf) + printstr(buf); + + exit(ret); +} + +int puts(const char *s) +{ + const char *p = s; + + while (*p) + putchar(*p++); + + putchar('\n'); + return 0; +} + +#undef putchar +int putchar(int ch) +{ +#if !NOPRINT + static __thread char buf[64] __attribute__((aligned(64))); + static __thread int buflen = 0; + + buf[buflen++] = ch; + + if (ch == '\n' || buflen == sizeof(buf)) + { + syscall(SYS_write, 1, (uintptr_t)buf, buflen); + buflen = 0; + } +#endif + + return 0; +} + +void printhex(uint64_t x) +{ + char str[17]; + int i; + for (i = 0; i < 16; i++) + { + str[15-i] = (x & 0xF) + ((x & 0xF) < 10 ? '0' : 'a'-10); + x >>= 4; + } + str[16] = 0; + + printstr(str); +} + +static inline void printnum(void (*putch)(int, void**), void **putdat, + unsigned long long num, unsigned base, int width, int padc) +{ + unsigned digs[sizeof(num)*CHAR_BIT]; + int pos = 0; + + while (1) + { + digs[pos++] = num % base; + if (num < base) + break; + num /= base; + } + + while (width-- > pos) + putch(padc, putdat); + + while (pos-- > 0) + putch(digs[pos] + (digs[pos] >= 10 ? 'a' - 10 : '0'), putdat); +} + +static unsigned long long getuint(va_list *ap, int lflag) +{ + if (lflag >= 2) + return va_arg(*ap, unsigned long long); + else if (lflag) + return va_arg(*ap, unsigned long); + else + return va_arg(*ap, unsigned int); +} + +static long long getint(va_list *ap, int lflag) +{ + if (lflag >= 2) + return va_arg(*ap, long long); + else if (lflag) + return va_arg(*ap, long); + else + return va_arg(*ap, int); +} + +static void vprintfmt(void (*putch)(int, void**), void **putdat, const char *fmt, va_list ap) +{ + register const char* p; + const char* last_fmt; + register int ch, err; + unsigned long long num; + int base, lflag, width, precision, altflag; + char padc; + + while (1) { + while ((ch = *(unsigned char *) fmt) != '%') { + if (ch == '\0') + return; + fmt++; + putch(ch, putdat); + } + fmt++; + + // Process a %-escape sequence + last_fmt = fmt; + padc = ' '; + width = -1; + precision = -1; + lflag = 0; + altflag = 0; + reswitch: + switch (ch = *(unsigned char *) fmt++) { + + // flag to pad on the right + case '-': + padc = '-'; + goto reswitch; + + // flag to pad with 0's instead of spaces + case '0': + padc = '0'; + goto reswitch; + + // width field + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + for (precision = 0; ; ++fmt) { + precision = precision * 10 + ch - '0'; + ch = *fmt; + if (ch < '0' || ch > '9') + break; + } + goto process_precision; + + case '*': + precision = va_arg(ap, int); + goto process_precision; + + case '.': + if (width < 0) + width = 0; + goto reswitch; + + case '#': + altflag = 1; + goto reswitch; + + process_precision: + if (width < 0) + width = precision, precision = -1; + goto reswitch; + + // long flag (doubled for long long) + case 'l': + lflag++; + goto reswitch; + + // character + case 'c': + putch(va_arg(ap, int), putdat); + break; + + // string + case 's': + if ((p = va_arg(ap, char *)) == NULL) + p = "(null)"; + if (width > 0 && padc != '-') + for (width -= strnlen(p, precision); width > 0; width--) + putch(padc, putdat); + for (; (ch = *p) != '\0' && (precision < 0 || --precision >= 0); width--) { + putch(ch, putdat); + p++; + } + for (; width > 0; width--) + putch(' ', putdat); + break; + + // (signed) decimal + case 'd': + num = getint(&ap, lflag); + if ((long long) num < 0) { + putch('-', putdat); + num = -(long long) num; + } + base = 10; + goto signed_number; + + // unsigned decimal + case 'u': + base = 10; + goto unsigned_number; + + // (unsigned) octal + case 'o': + // should do something with padding so it's always 3 octits + base = 8; + goto unsigned_number; + + // pointer + case 'p': + static_assert(sizeof(long) == sizeof(void*)); + lflag = 1; + putch('0', putdat); + putch('x', putdat); + /* fall through to 'x' */ + + // (unsigned) hexadecimal + case 'x': + base = 16; + unsigned_number: + num = getuint(&ap, lflag); + signed_number: + printnum(putch, putdat, num, base, width, padc); + break; + + // escaped '%' character + case '%': + putch(ch, putdat); + break; + + // unrecognized escape sequence - just print it literally + default: + putch('%', putdat); + fmt = last_fmt; + break; + } + } +} + +int printf(const char* fmt, ...) +{ + va_list ap; + va_start(ap, fmt); + + vprintfmt((void*)putchar, 0, fmt, ap); + + va_end(ap); + return 0; // incorrect return value, but who cares, anyway? +} + +int sprintf(char* str, const char* fmt, ...) +{ + va_list ap; + char* str0 = str; + va_start(ap, fmt); + + void sprintf_putch(int ch, void** data) + { + char** pstr = (char**)data; + **pstr = ch; + (*pstr)++; + } + + vprintfmt(sprintf_putch, (void**)&str, fmt, ap); + *str = 0; + + va_end(ap); + return str - str0; +} + +void* memcpy(void* dest, const void* src, size_t len) +{ + if ((((uintptr_t)dest | (uintptr_t)src | len) & (sizeof(uintptr_t)-1)) == 0) { + const uintptr_t* s = src; + uintptr_t *d = dest; + while (d < (uintptr_t*)(dest + len)) + *d++ = *s++; + } else { + const char* s = src; + char *d = dest; + while (d < (char*)(dest + len)) + *d++ = *s++; + } + return dest; +} + +void* memset(void* dest, int byte, size_t len) +{ + if ((((uintptr_t)dest | len) & (sizeof(uintptr_t)-1)) == 0) { + uintptr_t word = byte & 0xFF; + word |= word << 8; + word |= word << 16; + word |= word << 16 << 16; + + uintptr_t *d = dest; + while (d < (uintptr_t*)(dest + len)) + *d++ = word; + } else { + char *d = dest; + while (d < (char*)(dest + len)) + *d++ = byte; + } + return dest; +} + +size_t strlen(const char *s) +{ + const char *p = s; + while (*p) + p++; + return p - s; +} + +size_t strnlen(const char *s, size_t n) +{ + const char *p = s; + while (n-- && *p) + p++; + return p - s; +} + +int strcmp(const char* s1, const char* s2) +{ + unsigned char c1, c2; + + do { + c1 = *s1++; + c2 = *s2++; + } while (c1 != 0 && c1 == c2); + + return c1 - c2; +} + +char* strcpy(char* dest, const char* src) +{ + char* d = dest; + while ((*d++ = *src++)) + ; + return dest; +} + +long atol(const char* str) +{ + long res = 0; + int sign = 0; + + while (*str == ' ') + str++; + + if (*str == '-' || *str == '+') { + sign = *str == '-'; + str++; + } + + while (*str) { + res *= 10; + res += *str++ - '0'; + } + + return sign ? -res : res; +} diff --git a/verif/tests/custom/common/test.ld b/verif/tests/custom/common/test.ld new file mode 100644 index 0000000000..a50b017e81 --- /dev/null +++ b/verif/tests/custom/common/test.ld @@ -0,0 +1,66 @@ +/*======================================================================*/ +/* Proxy kernel linker script */ +/*======================================================================*/ +/* This is the linker script used when building the proxy kernel. */ + +/*----------------------------------------------------------------------*/ +/* Setup */ +/*----------------------------------------------------------------------*/ + +/* The OUTPUT_ARCH command specifies the machine architecture where the + argument is one of the names used in the BFD library. More + specifically one of the entires in bfd/cpu-mips.c */ + +OUTPUT_ARCH( "riscv" ) +ENTRY(_start) + +/*----------------------------------------------------------------------*/ +/* Sections */ +/*----------------------------------------------------------------------*/ + +SECTIONS +{ + + /* text: test code section */ + . = 0x80000000; + .text.init : { *(.text.init) } + + . = ALIGN(0x1000); + .tohost : { *(.tohost) } + + . = ALIGN(0x1000); + .text : { *(.text) } + + /* data segment */ + .data : { *(.data) } + + .sdata : { + __global_pointer$ = . + 0x800; + *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata*) + *(.sdata .sdata.* .gnu.linkonce.s.*) + } + + /* bss segment */ + .sbss : { + *(.sbss .sbss.* .gnu.linkonce.sb.*) + *(.scommon) + } + .bss : { *(.bss) } + + /* thread-local data segment */ + .tdata : + { + _tdata_begin = .; + *(.tdata) + _tdata_end = .; + } + .tbss : + { + *(.tbss) + _tbss_end = .; + } + + /* End of uninitalized data segement */ + _end = .; +} + diff --git a/verif/tests/custom/common/util.h b/verif/tests/custom/common/util.h new file mode 100644 index 0000000000..78fa62401a --- /dev/null +++ b/verif/tests/custom/common/util.h @@ -0,0 +1,92 @@ +// See LICENSE for license details. + +#ifndef __UTIL_H +#define __UTIL_H + +extern void setStats(int enable); + +#include <stdint.h> + +#define static_assert(cond) switch(0) { case 0: case !!(long)(cond): ; } + +static int verify(int n, const volatile int* test, const int* verify) +{ + int i; + // Unrolled for faster verification + for (i = 0; i < n/2*2; i+=2) + { + int t0 = test[i], t1 = test[i+1]; + int v0 = verify[i], v1 = verify[i+1]; + if (t0 != v0) return i+1; + if (t1 != v1) return i+2; + } + if (n % 2 != 0 && test[n-1] != verify[n-1]) + return n; + return 0; +} + +static int verifyDouble(int n, const volatile double* test, const double* verify) +{ + int i; + // Unrolled for faster verification + for (i = 0; i < n/2*2; i+=2) + { + double t0 = test[i], t1 = test[i+1]; + double v0 = verify[i], v1 = verify[i+1]; + int eq1 = t0 == v0, eq2 = t1 == v1; + if (!(eq1 & eq2)) return i+1+eq1; + } + if (n % 2 != 0 && test[n-1] != verify[n-1]) + return n; + return 0; +} + +static void __attribute__((noinline)) barrier(int ncores) +{ +#ifdef __riscv_atomic // __sync_* builtins require A extension + static volatile int sense; + static volatile int count; + static __thread int threadsense; + + __sync_synchronize(); + + threadsense = !threadsense; + if (__sync_fetch_and_add(&count, 1) == ncores-1) + { + count = 0; + sense = threadsense; + } + else while(sense != threadsense) + ; + + __sync_synchronize(); +#endif // __riscv_atomic +} + +static uint64_t lfsr(uint64_t x) +{ + uint64_t bit = (x ^ (x >> 1)) & 1; + return (x >> 1) | (bit << 62); +} + +static uintptr_t insn_len(uintptr_t pc) +{ + return (*(unsigned short*)pc & 3) ? 4 : 2; +} + +#ifdef __riscv +#include "encoding.h" +#endif + +#define stringify_1(s) #s +#define stringify(s) stringify_1(s) +#define stats(code, iter) do { \ + unsigned long _c = -read_csr(mcycle), _i = -read_csr(minstret); \ + code; \ + _c += read_csr(mcycle), _i += read_csr(minstret); \ + if (cid == 0) \ + printf("\n%s: %ld cycles, %ld.%ld cycles/iter, %ld.%ld CPI\n", \ + stringify(code), _c, _c/iter, 10*_c/iter%10, _c/_i, 10*_c/_i%10); \ + } while(0) + +#endif //__UTIL_H diff --git a/verif/tests/custom/coremark/LICENSE.md b/verif/tests/custom/coremark/LICENSE.md new file mode 100644 index 0000000000..a146fd8b0c --- /dev/null +++ b/verif/tests/custom/coremark/LICENSE.md @@ -0,0 +1,100 @@ +# COREMARK® ACCEPTABLE USE AGREEMENT + +This ACCEPTABLE USE AGREEMENT (this “Agreement”) is offered by Embedded Microprocessor Benchmark Consortium, a California nonprofit corporation (“Licensor”), to users of its CoreMark® software (“Licensee”) exclusively on the following terms. + +Licensor offers benchmarking software (“Software”) pursuant to an open source license, but carefully controls use of its benchmarks and their associated goodwill. Licensor has registered its trademark in one of the benchmarks available through the Software, COREMARK, Ser. No. 85/487,290; Reg. No. 4,179,307 (the “Trademark”), and promotes the use of a standard metric as a benchmark for assessing the performance of embedded systems. Solely on the terms described herein, Licensee may use and display the Trademark in connection with the generation of data regarding measurement and analysis of computer and embedded system benchmarking via the Software (the “Licensed Use”). + +## Article 1 – License Grant. +1.1. License. Subject to the terms and conditions of this Agreement, Licensor hereby grants to Licensee, and Licensee hereby accepts from Licensor, a personal, non-exclusive, royalty-free, revocable right and license to use and display the Trademark during the term of this Agreement (the “Term”), solely and exclusively in connection with the Licensed Use. During the Term, Licensee (i) shall not modify or otherwise create derivative works of the Trademark, and (ii) may use the Trademark only to the extent permitted under this License. Neither Licensee nor any affiliate or agent thereof shall otherwise use the Trademark without the prior express written consent of Licensor, which may be withheld in its sole and absolute discretion. All rights not expressly granted to Licensee hereunder shall remain the exclusive property of Licensor. + +1.2. Modifications to the Software. Licensee shall not use the Trademark in connection with any use of a modified, derivative, or otherwise altered copy of the Software. + +1.3. Licensor’s Use. Nothing in this Agreement shall preclude Licensor or any of its successors or assigns from using or permitting other entities to use the Trademark, whether or not such entity directly or indirectly competes or conflicts with Licensee’s Licensed Use in any manner. + +1.4. Term and Termination. This Agreement is perpetual unless terminated by either of the parties. Licensee may terminate this Agreement for convenience, without cause or liability, for any reason or for no reason whatsoever, upon ten (10) business days written notice. Licensor may terminate this Agreement effective immediately upon notice of breach. Upon termination, Licensee shall immediately remove all implementations of the Trademark from the Licensed Use, and delete all digitals files and records of all materials related to the Trademark. + +## Article 2 – Ownership. +2.1. Ownership. Licensee acknowledges and agrees that Licensor is the owner of all right, title, and interest in and to the Trademark, and all such right, title, and interest shall remain with Licensor. Licensee shall not contest, dispute, challenge, oppose, or seek to cancel Licensor’s right, title, and interest in and to the Trademark. Licensee shall not prosecute any application for registration of the Trademark. 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This Agreement constitutes the entire agreement between the parties and supersedes all prior and contemporaneous agreements, proposals or representations, written or oral, concerning its subject matter. + + +# Apache License + +Version 2.0, January 2004 + +http://www.apache.org/licenses/ + +## TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + +1. Definitions. + +"License" shall mean the terms and conditions for use, reproduction, and distribution as defined by Sections 1 through 9 of this document. + +"Licensor" shall mean the copyright owner or entity authorized by the copyright owner that is granting the License. + +"Legal Entity" shall mean the union of the acting entity and all other entities that control, are controlled by, or are under common control with that entity. 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You are solely responsible for determining the appropriateness of using or redistributing the Work and assume any risks associated with Your exercise of permissions under this License. + +8. Limitation of Liability. In no event and under no legal theory, whether in tort (including negligence), contract, or otherwise, unless required by applicable law (such as deliberate and grossly negligent acts) or agreed to in writing, shall any Contributor be liable to You for damages, including any direct, indirect, special, incidental, or consequential damages of any character arising as a result of this License or out of the use or inability to use the Work (including but not limited to damages for loss of goodwill, work stoppage, computer failure or malfunction, or any and all other commercial damages or losses), even if such Contributor has been advised of the possibility of such damages. + +9. Accepting Warranty or Additional Liability. While redistributing the Work or Derivative Works thereof, You may choose to offer, and charge a fee for, acceptance of support, warranty, indemnity, or other liability obligations and/or rights consistent with this License. However, in accepting such obligations, You may act only on Your own behalf and on Your sole responsibility, not on behalf of any other Contributor, and only if You agree to indemnify, defend, and hold each Contributor harmless for any liability incurred by, or claims asserted against, such Contributor by reason of your accepting any such warranty or additional liability. + +END OF TERMS AND CONDITIONS diff --git a/verif/tests/custom/coremark/core_list_join.c b/verif/tests/custom/coremark/core_list_join.c new file mode 100644 index 0000000000..c3e1a77130 --- /dev/null +++ b/verif/tests/custom/coremark/core_list_join.c @@ -0,0 +1,613 @@ +/* +Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +Original Author: Shay Gal-on +*/ + +// Copyright 2020 OpenHW Group +// Copyright 2020 Silicon Labs, Inc. +// Copyright 2022 Thales DIS Design Services SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier:Apache-2.0 WITH SHL-2.0 + +#include "coremark.h" +/* +Topic: Description + Benchmark using a linked list. + + Linked list is a common data structure used in many applications. + + For our purposes, this will excercise the memory units of the processor. + In particular, usage of the list pointers to find and alter data. + + We are not using Malloc since some platforms do not support this +library. + + Instead, the memory block being passed in is used to create a list, + and the benchmark takes care not to add more items then can be + accomodated by the memory block. The porting layer will make sure + that we have a valid memory block. + + All operations are done in place, without using any extra memory. + + The list itself contains list pointers and pointers to data items. + Data items contain the following: + + idx - An index that captures the initial order of the list. + data - Variable data initialized based on the input parameters. The 16b +are divided as follows: o Upper 8b are backup of original data. o Bit 7 +indicates if the lower 7 bits are to be used as is or calculated. o Bits 0-2 +indicate type of operation to perform to get a 7b value. o Bits 3-6 provide +input for the operation. + +*/ + +/* local functions */ + +list_head *core_list_find(list_head *list, list_data *info); +list_head *core_list_reverse(list_head *list); +list_head *core_list_remove(list_head *item); +list_head *core_list_undo_remove(list_head *item_removed, + list_head *item_modified); +list_head *core_list_insert_new(list_head * insert_point, + list_data * info, + list_head **memblock, + list_data **datablock, + list_head * memblock_end, + list_data * datablock_end); +typedef ee_s32 (*list_cmp)(list_data *a, list_data *b, core_results *res); +list_head *core_list_mergesort(list_head * list, + list_cmp cmp, + core_results *res); + +ee_s16 +calc_func(ee_s16 *pdata, core_results *res) +{ + ee_s16 data = *pdata; + ee_s16 retval; + ee_u8 optype + = (data >> 7) + & 1; /* bit 7 indicates if the function result has been cached */ + if (optype) /* if cached, use cache */ + return (data & 0x007f); + else + { /* otherwise calculate and cache the result */ + ee_s16 flag = data & 0x7; /* bits 0-2 is type of function to perform */ + ee_s16 dtype + = ((data >> 3) + & 0xf); /* bits 3-6 is specific data for the operation */ + dtype |= dtype << 4; /* replicate the lower 4 bits to get an 8b value */ + switch (flag) + { + case 0: + if (dtype < 0x22) /* set min period for bit corruption */ + dtype = 0x22; + retval = core_bench_state(res->size, + res->memblock[3], + res->seed1, + res->seed2, + dtype, + res->crc); + if (res->crcstate == 0) + res->crcstate = retval; + break; + case 1: + retval = core_bench_matrix(&(res->mat), dtype, res->crc); + if (res->crcmatrix == 0) + res->crcmatrix = retval; + break; + default: + retval = data; + break; + } + res->crc = crcu16(retval, res->crc); + retval &= 0x007f; + *pdata = (data & 0xff00) | 0x0080 | retval; /* cache the result */ + return retval; + } +} +/* Function: cmp_complex + Compare the data item in a list cell. + + Can be used by mergesort. +*/ +ee_s32 +cmp_complex(list_data *a, list_data *b, core_results *res) +{ + ee_s16 val1 = calc_func(&(a->data16), res); + ee_s16 val2 = calc_func(&(b->data16), res); + return val1 - val2; +} + +/* Function: cmp_idx + Compare the idx item in a list cell, and regen the data. + + Can be used by mergesort. +*/ +ee_s32 +cmp_idx(list_data *a, list_data *b, core_results *res) +{ + if (res == NULL) + { + a->data16 = (a->data16 & 0xff00) | (0x00ff & (a->data16 >> 8)); + b->data16 = (b->data16 & 0xff00) | (0x00ff & (b->data16 >> 8)); + } + return a->idx - b->idx; +} + +void +copy_info(list_data *to, list_data *from) +{ + to->data16 = from->data16; + to->idx = from->idx; +} + +/* Benchmark for linked list: + - Try to find multiple data items. + - List sort + - Operate on data from list (crc) + - Single remove/reinsert + * At the end of this function, the list is back to original state +*/ +ee_u16 +core_bench_list(core_results *res, ee_s16 finder_idx) +{ + ee_u16 retval = 0; + ee_u16 found = 0, missed = 0; + list_head *list = res->list; + ee_s16 find_num = res->seed3; + list_head *this_find; + list_head *finder, *remover; + list_data info; + ee_s16 i; + + info.idx = finder_idx; + /* find <find_num> values in the list, and change the list each time + * (reverse and cache if value found) */ + for (i = 0; i < find_num; i++) + { + info.data16 = (i & 0xff); + this_find = core_list_find(list, &info); + list = core_list_reverse(list); + if (this_find == NULL) + { + missed++; + retval += (list->next->info->data16 >> 8) & 1; + } + else + { + found++; + if (this_find->info->data16 & 0x1) /* use found value */ + retval += (this_find->info->data16 >> 9) & 1; + /* and cache next item at the head of the list (if any) */ + if (this_find->next != NULL) + { + finder = this_find->next; + this_find->next = finder->next; + finder->next = list->next; + list->next = finder; + } + } + if (info.idx >= 0) + info.idx++; +#if CORE_DEBUG + ee_printf("List find %d: [%d,%d,%d]\n", i, retval, missed, found); +#endif + } + retval += found * 4 - missed; + /* sort the list by data content and remove one item*/ + if (finder_idx > 0) + list = core_list_mergesort(list, cmp_complex, res); + remover = core_list_remove(list->next); + /* CRC data content of list from location of index N forward, and then undo + * remove */ + finder = core_list_find(list, &info); + if (!finder) + finder = list->next; + while (finder) + { + retval = crc16(list->info->data16, retval); + finder = finder->next; + } +#if CORE_DEBUG + ee_printf("List sort 1: %04x\n", retval); +#endif + remover = core_list_undo_remove(remover, list->next); + /* sort the list by index, in effect returning the list to original state */ + list = core_list_mergesort(list, cmp_idx, NULL); + /* CRC data content of list */ + finder = list->next; + while (finder) + { + retval = crc16(list->info->data16, retval); + finder = finder->next; + } +#if CORE_DEBUG + ee_printf("List sort 2: %04x\n", retval); +#endif + return retval; +} +/* Function: core_list_init + Initialize list with data. + + Parameters: + blksize - Size of memory to be initialized. + memblock - Pointer to memory block. + seed - Actual values chosen depend on the seed parameter. + The seed parameter MUST be supplied from a source that cannot be + determined at compile time + + Returns: + Pointer to the head of the list. + +*/ +list_head * +core_list_init(ee_u32 blksize, list_head *memblock, ee_s16 seed) +{ + /* calculated pointers for the list */ + ee_u32 per_item = 16 + sizeof(struct list_data_s); + ee_u32 size = (blksize / per_item) + - 2; /* to accomodate systems with 64b pointers, and make sure + same code is executed, set max list elements */ + list_head *memblock_end = memblock + size; + list_data *datablock = (list_data *)(memblock_end); + list_data *datablock_end = datablock + size; + /* some useful variables */ + ee_u32 i; + list_head *finder, *list = memblock; + list_data info; + + /* create a fake items for the list head and tail */ + list->next = NULL; + list->info = datablock; + list->info->idx = 0x0000; + list->info->data16 = (ee_s16)0x8080; + memblock++; + datablock++; + info.idx = 0x7fff; + info.data16 = (ee_s16)0xffff; + core_list_insert_new( + list, &info, &memblock, &datablock, memblock_end, datablock_end); + + /* then insert size items */ + for (i = 0; i < size; i++) + { + ee_u16 datpat = ((ee_u16)(seed ^ i) & 0xf); + ee_u16 dat + = (datpat << 3) | (i & 0x7); /* alternate between algorithms */ + info.data16 = (dat << 8) | dat; /* fill the data with actual data and + upper bits with rebuild value */ + core_list_insert_new( + list, &info, &memblock, &datablock, memblock_end, datablock_end); + } + /* and now index the list so we know initial seed order of the list */ + finder = list->next; + i = 1; + while (finder->next != NULL) + { + if (i < size / 5) /* first 20% of the list in order */ + finder->info->idx = i++; + else + { + ee_u16 pat = (ee_u16)(i++ ^ seed); /* get a pseudo random number */ + finder->info->idx = 0x3fff + & (((i & 0x07) << 8) + | pat); /* make sure the mixed items end up + after the ones in sequence */ + } + finder = finder->next; + } + list = core_list_mergesort(list, cmp_idx, NULL); +#if CORE_DEBUG + ee_printf("Initialized list:\n"); + finder = list; + while (finder) + { + ee_printf( + "[%04x,%04x]", finder->info->idx, (ee_u16)finder->info->data16); + finder = finder->next; + } + ee_printf("\n"); +#endif + return list; +} + +/* Function: core_list_insert + Insert an item to the list + + Parameters: + insert_point - where to insert the item. + info - data for the cell. + memblock - pointer for the list header + datablock - pointer for the list data + memblock_end - end of region for list headers + datablock_end - end of region for list data + + Returns: + Pointer to new item. +*/ +list_head * +core_list_insert_new(list_head * insert_point, + list_data * info, + list_head **memblock, + list_data **datablock, + list_head * memblock_end, + list_data * datablock_end) +{ + list_head *newitem; + + if ((*memblock + 1) >= memblock_end) + return NULL; + if ((*datablock + 1) >= datablock_end) + return NULL; + + newitem = *memblock; + (*memblock)++; + newitem->next = insert_point->next; + insert_point->next = newitem; + + newitem->info = *datablock; + (*datablock)++; + copy_info(newitem->info, info); + + return newitem; +} + +/* Function: core_list_remove + Remove an item from the list. + + Operation: + For a singly linked list, remove by copying the data from the next item + over to the current cell, and unlinking the next item. + + Note: + since there is always a fake item at the end of the list, no need to + check for NULL. + + Returns: + Removed item. +*/ +list_head * +core_list_remove(list_head *item) +{ + list_data *tmp; + list_head *ret = item->next; + /* swap data pointers */ + tmp = item->info; + item->info = ret->info; + ret->info = tmp; + /* and eliminate item */ + item->next = item->next->next; + ret->next = NULL; + return ret; +} + +/* Function: core_list_undo_remove + Undo a remove operation. + + Operation: + Since we want each iteration of the benchmark to be exactly the same, + we need to be able to undo a remove. + Link the removed item back into the list, and switch the info items. + + Parameters: + item_removed - Return value from the <core_list_remove> + item_modified - List item that was modified during <core_list_remove> + + Returns: + The item that was linked back to the list. + +*/ +list_head * +core_list_undo_remove(list_head *item_removed, list_head *item_modified) +{ + list_data *tmp; + /* swap data pointers */ + tmp = item_removed->info; + item_removed->info = item_modified->info; + item_modified->info = tmp; + /* and insert item */ + item_removed->next = item_modified->next; + item_modified->next = item_removed; + return item_removed; +} + +/* Function: core_list_find + Find an item in the list + + Operation: + Find an item by idx (if not 0) or specific data value + + Parameters: + list - list head + info - idx or data to find + + Returns: + Found item, or NULL if not found. +*/ +list_head * +core_list_find(list_head *list, list_data *info) +{ + if (info->idx >= 0) + { + while (list && (list->info->idx != info->idx)) + list = list->next; + return list; + } + else + { + while (list && ((list->info->data16 & 0xff) != info->data16)) + list = list->next; + return list; + } +} +/* Function: core_list_reverse + Reverse a list + + Operation: + Rearrange the pointers so the list is reversed. + + Parameters: + list - list head + info - idx or data to find + + Returns: + Found item, or NULL if not found. +*/ + +list_head * +core_list_reverse(list_head *list) +{ + list_head *next = NULL, *tmp; + while (list) + { + tmp = list->next; + list->next = next; + next = list; + list = tmp; + } + return next; +} +/* Function: core_list_mergesort + Sort the list in place without recursion. + + Description: + Use mergesort, as for linked list this is a realistic solution. + Also, since this is aimed at embedded, care was taken to use iterative + rather then recursive algorithm. The sort can either return the list to + original order (by idx) , or use the data item to invoke other other + algorithms and change the order of the list. + + Parameters: + list - list to be sorted. + cmp - cmp function to use + + Returns: + New head of the list. + + Note: + We have a special header for the list that will always be first, + but the algorithm could theoretically modify where the list starts. + + */ +list_head * +core_list_mergesort(list_head *list, list_cmp cmp, core_results *res) +{ + list_head *p, *q, *e, *tail; + ee_s32 insize, nmerges, psize, qsize, i; + + insize = 1; + + while (1) + { + p = list; + list = NULL; + tail = NULL; + + nmerges = 0; /* count number of merges we do in this pass */ + + while (p) + { + nmerges++; /* there exists a merge to be done */ + /* step `insize' places along from p */ + q = p; + psize = 0; + for (i = 0; i < insize; i++) + { + psize++; + q = q->next; + if (!q) + break; + } + + /* if q hasn't fallen off end, we have two lists to merge */ + qsize = insize; + + /* now we have two lists; merge them */ + while (psize > 0 || (qsize > 0 && q)) + { + + /* decide whether next element of merge comes from p or q */ + if (psize == 0) + { + /* p is empty; e must come from q. */ + e = q; + q = q->next; + qsize--; + } + else if (qsize == 0 || !q) + { + /* q is empty; e must come from p. */ + e = p; + p = p->next; + psize--; + } + else if (cmp(p->info, q->info, res) <= 0) + { + /* First element of p is lower (or same); e must come from + * p. */ + e = p; + p = p->next; + psize--; + } + else + { + /* First element of q is lower; e must come from q. */ + e = q; + q = q->next; + qsize--; + } + + /* add the next element to the merged list */ + if (tail) + { + tail->next = e; + } + else + { + list = e; + } + tail = e; + } + + /* now p has stepped `insize' places along, and q has too */ + p = q; + } + + tail->next = NULL; + + /* If we have done only one merge, we're finished. */ + if (nmerges <= 1) /* allow for nmerges==0, the empty list case */ + return list; + + /* Otherwise repeat, merging lists twice the size */ + insize *= 2; + } +#if COMPILER_REQUIRES_SORT_RETURN + return list; +#endif +} diff --git a/verif/tests/custom/coremark/core_main.c b/verif/tests/custom/coremark/core_main.c new file mode 100644 index 0000000000..5ae1331fa6 --- /dev/null +++ b/verif/tests/custom/coremark/core_main.c @@ -0,0 +1,464 @@ +/* +Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +Original Author: Shay Gal-on +*/ + +// Copyright 2020 OpenHW Group +// Copyright 2020 Silicon Labs, Inc. +// Copyright 2022 Thales DIS Design Services SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier:Apache-2.0 WITH SHL-2.0 + +/* File: core_main.c + This file contains the framework to acquire a block of memory, seed + initial parameters, tun t he benchmark and report the results. +*/ +#include "coremark.h" + +/* Function: iterate + Run the benchmark for a specified number of iterations. + + Operation: + For each type of benchmarked algorithm: + a - Initialize the data block for the algorithm. + b - Execute the algorithm N times. + + Returns: + NULL. +*/ +static ee_u16 list_known_crc[] = { (ee_u16)0xd4b0, + (ee_u16)0x3340, + (ee_u16)0x6a79, + (ee_u16)0xe714, + (ee_u16)0xe3c1 }; +static ee_u16 matrix_known_crc[] = { (ee_u16)0xbe52, + (ee_u16)0x1199, + (ee_u16)0x5608, + (ee_u16)0x1fd7, + (ee_u16)0x0747 }; +static ee_u16 state_known_crc[] = { (ee_u16)0x5e47, + (ee_u16)0x39bf, + (ee_u16)0xe5a4, + (ee_u16)0x8e3a, + (ee_u16)0x8d84 }; +void * +iterate(void *pres) +{ + ee_u32 i; + ee_u16 crc; + core_results *res = (core_results *)pres; + ee_u32 iterations = res->iterations; + res->crc = 0; + res->crclist = 0; + res->crcmatrix = 0; + res->crcstate = 0; + + for (i = 0; i < iterations; i++) + { + crc = core_bench_list(res, 1); + res->crc = crcu16(crc, res->crc); + crc = core_bench_list(res, -1); + res->crc = crcu16(crc, res->crc); + if (i == 0) + res->crclist = res->crc; + } + return NULL; +} + +#if (SEED_METHOD == SEED_ARG) +ee_s32 get_seed_args(int i, int argc, char *argv[]); +#define get_seed(x) (ee_s16) get_seed_args(x, argc, argv) +#define get_seed_32(x) get_seed_args(x, argc, argv) +#else /* via function or volatile */ +ee_s32 get_seed_32(int i); +#define get_seed(x) (ee_s16) get_seed_32(x) +#endif + +#if (MEM_METHOD == MEM_STATIC) +ee_u8 static_memblk[TOTAL_DATA_SIZE]; +#endif +char *mem_name[3] = { "Static", "Heap", "Stack" }; +/* Function: main + Main entry routine for the benchmark. + This function is responsible for the following steps: + + 1 - Initialize input seeds from a source that cannot be determined at + compile time. 2 - Initialize memory block for use. 3 - Run and time the + benchmark. 4 - Report results, testing the validity of the output if the + seeds are known. + + Arguments: + 1 - first seed : Any value + 2 - second seed : Must be identical to first for iterations to be + identical 3 - third seed : Any value, should be at least an order of + magnitude less then the input size, but bigger then 32. 4 - Iterations : + Special, if set to 0, iterations will be automatically determined such that + the benchmark will run between 10 to 100 secs + +*/ + +#if MAIN_HAS_NOARGC +MAIN_RETURN_TYPE +main(void) +{ + int argc = 0; + char *argv[1]; +#else +MAIN_RETURN_TYPE +main(int argc, char *argv[]) +{ +#endif + ee_u16 i, j = 0, num_algorithms = 0; + ee_s16 known_id = -1, total_errors = 0; + ee_u16 seedcrc = 0; + CORE_TICKS total_time; + secs_ret total_time_secs; + long unsigned total_iterations, score100; + core_results results[MULTITHREAD]; +#if (MEM_METHOD == MEM_STACK) + ee_u8 stack_memblock[TOTAL_DATA_SIZE * MULTITHREAD]; +#endif + /* first call any initializations needed */ + portable_init(&(results[0].port), &argc, argv); + /* First some checks to make sure benchmark will run ok */ + if (sizeof(struct list_head_s) > 128) + { + ee_printf("list_head structure too big for comparable data!\n"); + return MAIN_RETURN_VAL; + } + results[0].seed1 = get_seed(1); + results[0].seed2 = get_seed(2); + results[0].seed3 = get_seed(3); + results[0].iterations = get_seed_32(4); +#if CORE_DEBUG + results[0].iterations = 1; +#endif + results[0].execs = get_seed_32(5); + if (results[0].execs == 0) + { /* if not supplied, execute all algorithms */ + results[0].execs = ALL_ALGORITHMS_MASK; + } + /* put in some default values based on one seed only for easy testing */ + if ((results[0].seed1 == 0) && (results[0].seed2 == 0) + && (results[0].seed3 == 0)) + { /* perfromance run */ + results[0].seed1 = 0; + results[0].seed2 = 0; + results[0].seed3 = 0x66; + } + if ((results[0].seed1 == 1) && (results[0].seed2 == 0) + && (results[0].seed3 == 0)) + { /* validation run */ + results[0].seed1 = 0x3415; + results[0].seed2 = 0x3415; + results[0].seed3 = 0x66; + } +#if (MEM_METHOD == MEM_STATIC) + results[0].memblock[0] = (void *)static_memblk; + results[0].size = TOTAL_DATA_SIZE; + results[0].err = 0; +#if (MULTITHREAD > 1) +#error "Cannot use a static data area with multiple contexts!" +#endif +#elif (MEM_METHOD == MEM_MALLOC) + for (i = 0; i < MULTITHREAD; i++) + { + ee_s32 malloc_override = get_seed(7); + if (malloc_override != 0) + results[i].size = malloc_override; + else + results[i].size = TOTAL_DATA_SIZE; + results[i].memblock[0] = portable_malloc(results[i].size); + results[i].seed1 = results[0].seed1; + results[i].seed2 = results[0].seed2; + results[i].seed3 = results[0].seed3; + results[i].err = 0; + results[i].execs = results[0].execs; + } +#elif (MEM_METHOD == MEM_STACK) +for (i = 0; i < MULTITHREAD; i++) +{ + results[i].memblock[0] = stack_memblock + i * TOTAL_DATA_SIZE; + results[i].size = TOTAL_DATA_SIZE; + results[i].seed1 = results[0].seed1; + results[i].seed2 = results[0].seed2; + results[i].seed3 = results[0].seed3; + results[i].err = 0; + results[i].execs = results[0].execs; +} +#else +#error "Please define a way to initialize a memory block." +#endif + /* Data init */ + /* Find out how space much we have based on number of algorithms */ + for (i = 0; i < NUM_ALGORITHMS; i++) + { + if ((1 << (ee_u32)i) & results[0].execs) + num_algorithms++; + } + for (i = 0; i < MULTITHREAD; i++) + results[i].size = results[i].size / num_algorithms; + /* Assign pointers */ + for (i = 0; i < NUM_ALGORITHMS; i++) + { + ee_u32 ctx; + if ((1 << (ee_u32)i) & results[0].execs) + { + for (ctx = 0; ctx < MULTITHREAD; ctx++) + results[ctx].memblock[i + 1] + = (char *)(results[ctx].memblock[0]) + results[0].size * j; + j++; + } + } + /* call inits */ + for (i = 0; i < MULTITHREAD; i++) + { + if (results[i].execs & ID_LIST) + { + results[i].list = core_list_init( + results[0].size, results[i].memblock[1], results[i].seed1); + } + if (results[i].execs & ID_MATRIX) + { + core_init_matrix(results[0].size, + results[i].memblock[2], + (ee_s32)results[i].seed1 + | (((ee_s32)results[i].seed2) << 16), + &(results[i].mat)); + } + if (results[i].execs & ID_STATE) + { + core_init_state( + results[0].size, results[i].seed1, results[i].memblock[3]); + } + } + + /* automatically determine number of iterations if not set */ + if (results[0].iterations == 0) + { + secs_ret secs_passed = 0; + ee_u32 divisor; + results[0].iterations = 1; + while (secs_passed < (secs_ret)1) + { + results[0].iterations *= 10; + start_time(); + iterate(&results[0]); + stop_time(); + secs_passed = time_in_secs(get_time()); + } + /* now we know it executes for at least 1 sec, set actual run time at + * about 10 secs */ + divisor = (ee_u32)secs_passed; + if (divisor == 0) /* some machines cast float to int as 0 since this + conversion is not defined by ANSI, but we know at + least one second passed */ + divisor = 1; + results[0].iterations *= 1 + 10 / divisor; + } + /* perform actual benchmark */ + start_time(); +#if (MULTITHREAD > 1) + if (default_num_contexts > MULTITHREAD) + { + default_num_contexts = MULTITHREAD; + } + for (i = 0; i < default_num_contexts; i++) + { + results[i].iterations = results[0].iterations; + results[i].execs = results[0].execs; + core_start_parallel(&results[i]); + } + for (i = 0; i < default_num_contexts; i++) + { + core_stop_parallel(&results[i]); + } +#else + iterate(&results[0]); +#endif + stop_time(); + total_time = get_time(); + total_time_secs = time_in_secs(total_time); + total_iterations = ((long unsigned) default_num_contexts) * ((long unsigned) results[0].iterations); + /* get a function of the input to report */ + seedcrc = crc16(results[0].seed1, seedcrc); + seedcrc = crc16(results[0].seed2, seedcrc); + seedcrc = crc16(results[0].seed3, seedcrc); + seedcrc = crc16(results[0].size, seedcrc); + + switch (seedcrc) + { /* test known output for common seeds */ + case 0x8a02: /* seed1=0, seed2=0, seed3=0x66, size 2000 per algorithm */ + known_id = 0; + ee_printf("6k performance run parameters for coremark.\n"); + break; + case 0x7b05: /* seed1=0x3415, seed2=0x3415, seed3=0x66, size 2000 per + algorithm */ + known_id = 1; + ee_printf("6k validation run parameters for coremark.\n"); + break; + case 0x4eaf: /* seed1=0x8, seed2=0x8, seed3=0x8, size 400 per algorithm + */ + known_id = 2; + ee_printf("Profile generation run parameters for coremark.\n"); + break; + case 0xe9f5: /* seed1=0, seed2=0, seed3=0x66, size 666 per algorithm */ + known_id = 3; + ee_printf("2K performance run parameters for coremark.\n"); + break; + case 0x18f2: /* seed1=0x3415, seed2=0x3415, seed3=0x66, size 666 per + algorithm */ + known_id = 4; + ee_printf("2K validation run parameters for coremark.\n"); + break; + default: + total_errors = -1; + break; + } + if (known_id >= 0) + { + for (i = 0; i < default_num_contexts; i++) + { + results[i].err = 0; + if ((results[i].execs & ID_LIST) + && (results[i].crclist != list_known_crc[known_id])) + { + ee_printf("[%u]ERROR! list crc 0x%04x - should be 0x%04x\n", + i, + results[i].crclist, + list_known_crc[known_id]); + results[i].err++; + } + if ((results[i].execs & ID_MATRIX) + && (results[i].crcmatrix != matrix_known_crc[known_id])) + { + ee_printf("[%u]ERROR! matrix crc 0x%04x - should be 0x%04x\n", + i, + results[i].crcmatrix, + matrix_known_crc[known_id]); + results[i].err++; + } + if ((results[i].execs & ID_STATE) + && (results[i].crcstate != state_known_crc[known_id])) + { + ee_printf("[%u]ERROR! state crc 0x%04x - should be 0x%04x\n", + i, + results[i].crcstate, + state_known_crc[known_id]); + results[i].err++; + } + total_errors += results[i].err; + } + } + total_errors += check_data_types(); + /* and report results */ + ee_printf("CoreMark Size : %lu\n", (long unsigned)results[0].size); + ee_printf("Total ticks : %lu\n", (long unsigned)total_time); +#if HAS_FLOAT + ee_printf("Total time (secs): %f\n", total_time_secs); + if (total_time_secs > 0) + ee_printf("Iterations/Sec : %f\n", total_iterations / total_time_secs); +#else + ee_printf("Total time (secs): %d\n", total_time_secs); + if (total_time_secs > 0) + ee_printf("Iterations/Sec : %d\n", total_iterations / total_time_secs); +#endif +#if !SKIP_TIME_CHECK + if (total_time_secs < 10) + { + ee_printf( + "ERROR! Must execute for at least 10 secs for a valid result!\n"); + total_errors++; + } +#endif + + ee_printf("Iterations : %lu\n", total_iterations); + ee_printf("Compiler version : " COMPILER_VERSION "\n"); + ee_printf("Compiler flags : " COMPILER_FLAGS "\n"); +#if (MULTITHREAD > 1) + ee_printf("Parallel %s : %d\n", PARALLEL_METHOD, default_num_contexts); +#endif + ee_printf("Memory location : " MEM_LOCATION "\n"); + /* output for verification */ + ee_printf("seedcrc : 0x%04x\n", seedcrc); + if (results[0].execs & ID_LIST) + for (i = 0; i < default_num_contexts; i++) + ee_printf("[%d]crclist : 0x%04x\n", i, results[i].crclist); + if (results[0].execs & ID_MATRIX) + for (i = 0; i < default_num_contexts; i++) + ee_printf("[%d]crcmatrix : 0x%04x\n", i, results[i].crcmatrix); + if (results[0].execs & ID_STATE) + for (i = 0; i < default_num_contexts; i++) + ee_printf("[%d]crcstate : 0x%04x\n", i, results[i].crcstate); + for (i = 0; i < default_num_contexts; i++) + ee_printf("[%d]crcfinal : 0x%04x\n", i, results[i].crc); + if (total_errors == 0) + { + ee_printf( + "Correct operation validated. See README.md for run and reporting " + "rules.\n"); + if (known_id == 3) + { + // Scaling results + score100 = total_iterations * 1000000 * 100 / total_time; + ee_printf("CoreMark/MHz 1.0 : %d.%02d / " + COMPILER_VERSION " " COMPILER_FLAGS " / " + SC_MEM_LOCATION "\n", + score100 / 100, score100 % 100); + +#if HAS_FLOAT + ee_printf("CoreMark 1.0 : %f / " COMPILER_VERSION " " COMPILER_FLAGS, + total_iterations / total_time_secs); +#if defined(MEM_LOCATION) && !defined(MEM_LOCATION_UNSPEC) + ee_printf(" / " MEM_LOCATION); +#else + ee_printf(" / %s", mem_name[MEM_METHOD]); +#endif +#if (MULTITHREAD > 1) + ee_printf(" / %d:%s", default_num_contexts, PARALLEL_METHOD); +#endif + ee_printf("\n"); +#endif + } + } + if (total_errors > 0) + ee_printf("Errors detected\n"); + if (total_errors < 0) + ee_printf( + "Cannot validate operation for these seed values, please compare " + "with results on a known platform.\n"); + +#if (MEM_METHOD == MEM_MALLOC) + for (i = 0; i < MULTITHREAD; i++) + portable_free(results[i].memblock[0]); +#endif + /* And last call any target specific code for finalizing */ + portable_fini(&(results[0].port)); + + return MAIN_RETURN_VAL; +} diff --git a/verif/tests/custom/coremark/core_matrix.c b/verif/tests/custom/coremark/core_matrix.c new file mode 100644 index 0000000000..ac3a9595dd --- /dev/null +++ b/verif/tests/custom/coremark/core_matrix.c @@ -0,0 +1,377 @@ +/* +Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +Original Author: Shay Gal-on +*/ + +// Copyright 2020 OpenHW Group +// Copyright 2020 Silicon Labs, Inc. +// Copyright 2022 Thales DIS Design Services SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier:Apache-2.0 WITH SHL-2.0 + +#include "coremark.h" +/* +Topic: Description + Matrix manipulation benchmark + + This very simple algorithm forms the basis of many more complex +algorithms. + + The tight inner loop is the focus of many optimizations (compiler as +well as hardware based) and is thus relevant for embedded processing. + + The total available data space will be divided to 3 parts: + NxN Matrix A - initialized with small values (upper 3/4 of the bits all +zero). NxN Matrix B - initialized with medium values (upper half of the bits all +zero). NxN Matrix C - used for the result. + + The actual values for A and B must be derived based on input that is not +available at compile time. +*/ +ee_s16 matrix_test(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B, MATDAT val); +ee_s16 matrix_sum(ee_u32 N, MATRES *C, MATDAT clipval); +void matrix_mul_const(ee_u32 N, MATRES *C, MATDAT *A, MATDAT val); +void matrix_mul_vect(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B); +void matrix_mul_matrix(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B); +void matrix_mul_matrix_bitextract(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B); +void matrix_add_const(ee_u32 N, MATDAT *A, MATDAT val); + +#define matrix_test_next(x) (x + 1) +#define matrix_clip(x, y) ((y) ? (x)&0x0ff : (x)&0x0ffff) +#define matrix_big(x) (0xf000 | (x)) +#define bit_extract(x, from, to) (((x) >> (from)) & (~(0xffffffff << (to)))) + +#if CORE_DEBUG +void +printmat(MATDAT *A, ee_u32 N, char *name) +{ + ee_u32 i, j; + ee_printf("Matrix %s [%dx%d]:\n", name, N, N); + for (i = 0; i < N; i++) + { + for (j = 0; j < N; j++) + { + if (j != 0) + ee_printf(","); + ee_printf("%d", A[i * N + j]); + } + ee_printf("\n"); + } +} +void +printmatC(MATRES *C, ee_u32 N, char *name) +{ + ee_u32 i, j; + ee_printf("Matrix %s [%dx%d]:\n", name, N, N); + for (i = 0; i < N; i++) + { + for (j = 0; j < N; j++) + { + if (j != 0) + ee_printf(","); + ee_printf("%d", C[i * N + j]); + } + ee_printf("\n"); + } +} +#endif +/* Function: core_bench_matrix + Benchmark function + + Iterate <matrix_test> N times, + changing the matrix values slightly by a constant amount each time. +*/ +ee_u16 +core_bench_matrix(mat_params *p, ee_s16 seed, ee_u16 crc) +{ + ee_u32 N = p->N; + MATRES *C = p->C; + MATDAT *A = p->A; + MATDAT *B = p->B; + MATDAT val = (MATDAT)seed; + + crc = crc16(matrix_test(N, C, A, B, val), crc); + + return crc; +} + +/* Function: matrix_test + Perform matrix manipulation. + + Parameters: + N - Dimensions of the matrix. + C - memory for result matrix. + A - input matrix + B - operator matrix (not changed during operations) + + Returns: + A CRC value that captures all results calculated in the function. + In particular, crc of the value calculated on the result matrix + after each step by <matrix_sum>. + + Operation: + + 1 - Add a constant value to all elements of a matrix. + 2 - Multiply a matrix by a constant. + 3 - Multiply a matrix by a vector. + 4 - Multiply a matrix by a matrix. + 5 - Add a constant value to all elements of a matrix. + + After the last step, matrix A is back to original contents. +*/ +ee_s16 +matrix_test(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B, MATDAT val) +{ + ee_u16 crc = 0; + MATDAT clipval = matrix_big(val); + + matrix_add_const(N, A, val); /* make sure data changes */ +#if CORE_DEBUG + printmat(A, N, "matrix_add_const"); +#endif + matrix_mul_const(N, C, A, val); + crc = crc16(matrix_sum(N, C, clipval), crc); +#if CORE_DEBUG + printmatC(C, N, "matrix_mul_const"); +#endif + matrix_mul_vect(N, C, A, B); + crc = crc16(matrix_sum(N, C, clipval), crc); +#if CORE_DEBUG + printmatC(C, N, "matrix_mul_vect"); +#endif + matrix_mul_matrix(N, C, A, B); + crc = crc16(matrix_sum(N, C, clipval), crc); +#if CORE_DEBUG + printmatC(C, N, "matrix_mul_matrix"); +#endif + matrix_mul_matrix_bitextract(N, C, A, B); + crc = crc16(matrix_sum(N, C, clipval), crc); +#if CORE_DEBUG + printmatC(C, N, "matrix_mul_matrix_bitextract"); +#endif + + matrix_add_const(N, A, -val); /* return matrix to initial value */ + return crc; +} + +/* Function : matrix_init + Initialize the memory block for matrix benchmarking. + + Parameters: + blksize - Size of memory to be initialized. + memblk - Pointer to memory block. + seed - Actual values chosen depend on the seed parameter. + p - pointers to <mat_params> containing initialized matrixes. + + Returns: + Matrix dimensions. + + Note: + The seed parameter MUST be supplied from a source that cannot be + determined at compile time +*/ +ee_u32 +core_init_matrix(ee_u32 blksize, void *memblk, ee_s32 seed, mat_params *p) +{ + ee_u32 N = 0; + MATDAT *A; + MATDAT *B; + ee_s32 order = 1; + MATDAT val; + ee_u32 i = 0, j = 0; + if (seed == 0) + seed = 1; + while (j < blksize) + { + i++; + j = i * i * 2 * 4; + } + N = i - 1; + A = (MATDAT *)align_mem(memblk); + B = A + N * N; + + for (i = 0; i < N; i++) + { + for (j = 0; j < N; j++) + { + seed = ((order * seed) % 65536); + val = (seed + order); + val = matrix_clip(val, 0); + B[i * N + j] = val; + val = (val + order); + val = matrix_clip(val, 1); + A[i * N + j] = val; + order++; + } + } + + p->A = A; + p->B = B; + p->C = (MATRES *)align_mem(B + N * N); + p->N = N; +#if CORE_DEBUG + printmat(A, N, "A"); + printmat(B, N, "B"); +#endif + return N; +} + +/* Function: matrix_sum + Calculate a function that depends on the values of elements in the + matrix. + + For each element, accumulate into a temporary variable. + + As long as this value is under the parameter clipval, + add 1 to the result if the element is bigger then the previous. + + Otherwise, reset the accumulator and add 10 to the result. +*/ +ee_s16 +matrix_sum(ee_u32 N, MATRES *C, MATDAT clipval) +{ + MATRES tmp = 0, prev = 0, cur = 0; + ee_s16 ret = 0; + ee_u32 i, j; + for (i = 0; i < N; i++) + { + for (j = 0; j < N; j++) + { + cur = C[i * N + j]; + tmp += cur; + if (tmp > clipval) + { + ret += 10; + tmp = 0; + } + else + { + ret += (cur > prev) ? 1 : 0; + } + prev = cur; + } + } + return ret; +} + +/* Function: matrix_mul_const + Multiply a matrix by a constant. + This could be used as a scaler for instance. +*/ +void +matrix_mul_const(ee_u32 N, MATRES *C, MATDAT *A, MATDAT val) +{ + ee_u32 i, j; + for (i = 0; i < N; i++) + { + for (j = 0; j < N; j++) + { + C[i * N + j] = (MATRES)A[i * N + j] * (MATRES)val; + } + } +} + +/* Function: matrix_add_const + Add a constant value to all elements of a matrix. +*/ +void +matrix_add_const(ee_u32 N, MATDAT *A, MATDAT val) +{ + ee_u32 i, j; + for (i = 0; i < N; i++) + { + for (j = 0; j < N; j++) + { + A[i * N + j] += val; + } + } +} + +/* Function: matrix_mul_vect + Multiply a matrix by a vector. + This is common in many simple filters (e.g. fir where a vector of + coefficients is applied to the matrix.) +*/ +void +matrix_mul_vect(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B) +{ + ee_u32 i, j; + for (i = 0; i < N; i++) + { + C[i] = 0; + for (j = 0; j < N; j++) + { + C[i] += (MATRES)A[i * N + j] * (MATRES)B[j]; + } + } +} + +/* Function: matrix_mul_matrix + Multiply a matrix by a matrix. + Basic code is used in many algorithms, mostly with minor changes such as + scaling. +*/ +void +matrix_mul_matrix(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B) +{ + ee_u32 i, j, k; + for (i = 0; i < N; i++) + { + for (j = 0; j < N; j++) + { + C[i * N + j] = 0; + for (k = 0; k < N; k++) + { + C[i * N + j] += (MATRES)A[i * N + k] * (MATRES)B[k * N + j]; + } + } + } +} + +/* Function: matrix_mul_matrix_bitextract + Multiply a matrix by a matrix, and extract some bits from the result. + Basic code is used in many algorithms, mostly with minor changes such as + scaling. +*/ +void +matrix_mul_matrix_bitextract(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B) +{ + ee_u32 i, j, k; + for (i = 0; i < N; i++) + { + for (j = 0; j < N; j++) + { + C[i * N + j] = 0; + for (k = 0; k < N; k++) + { + MATRES tmp = (MATRES)A[i * N + k] * (MATRES)B[k * N + j]; + C[i * N + j] += bit_extract(tmp, 2, 4) * bit_extract(tmp, 5, 7); + } + } + } +} diff --git a/verif/tests/custom/coremark/core_portme.c b/verif/tests/custom/coremark/core_portme.c new file mode 100644 index 0000000000..844be020b1 --- /dev/null +++ b/verif/tests/custom/coremark/core_portme.c @@ -0,0 +1,106 @@ +/* +Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +Original Author: Shay Gal-on +*/ + +// Copyright 2020 OpenHW Group +// Copyright 2020 Silicon Labs, Inc. +// Copyright 2022 Thales DIS Design Services SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier:Apache-2.0 WITH SHL-2.0 + +#include "coremark.h" + +ee_u32 default_num_contexts = 1; + +static CORETIMETYPE start_time_val, stop_time_val; + +#if VALIDATION_RUN +volatile ee_s32 seed1_volatile = 0x3415; +volatile ee_s32 seed2_volatile = 0x3415; +volatile ee_s32 seed3_volatile = 0x66; +#endif +#if PERFORMANCE_RUN +volatile ee_s32 seed1_volatile = 0x0; +volatile ee_s32 seed2_volatile = 0x0; +volatile ee_s32 seed3_volatile = 0x66; +#endif +#if PROFILE_RUN +volatile ee_s32 seed1_volatile = 0x8; +volatile ee_s32 seed2_volatile = 0x8; +volatile ee_s32 seed3_volatile = 0x8; +#endif +volatile ee_s32 seed4_volatile = ITERATIONS; +volatile ee_s32 seed5_volatile = 0; + +void +portable_init(core_portable *p, int *argc, char *argv[]) +{ + // Don't need to do anything here atm. + (void)p; + (void)argc; + (void)argv; +} + +void +portable_fini(core_portable *p) +{ + // Don't need to do anything here atm. + (void)p; +} + +// Provided by custom syscalls.c +extern void setStats(int enable); +extern ee_ptr_int getStats(int counterid); + +void +start_time(void) +{ + setStats(1); +} + +void +stop_time(void) +{ + setStats(0); +} + +CORE_TICKS +get_time(void) +{ + ee_ptr_int cycles_lo = getStats(0); // mcycle + // We may need to access mcycleh as well (FORNOW getStats(2)). + + return cycles_lo; +} + +secs_ret +time_in_secs(CORE_TICKS ticks) +{ + return ((secs_ret) ticks)/1000000; // Pretend we use 1 MHz clock. +} diff --git a/verif/tests/custom/coremark/core_portme.h b/verif/tests/custom/coremark/core_portme.h new file mode 100644 index 0000000000..0e08dbcf15 --- /dev/null +++ b/verif/tests/custom/coremark/core_portme.h @@ -0,0 +1,117 @@ +/* +Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +Original Author: Shay Gal-on +*/ + +// Copyright 2020 OpenHW Group +// Copyright 2020 Silicon Labs, Inc. +// Copyright 2022 Thales DIS Design Services SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier:Apache-2.0 WITH SHL-2.0 + +#include <stddef.h> +#include <stdio.h> +#include "uart.h" + +typedef signed short ee_s16; +typedef unsigned short ee_u16; +typedef signed int ee_s32; +typedef double ee_f32; +typedef unsigned char ee_u8; +typedef unsigned int ee_u32; +#if (!defined(XLEN) || (XLEN == 64)) +typedef unsigned long int ee_u64; +typedef ee_u64 ee_ptr_int; +#else +#if (XLEN == 32) +typedef ee_u32 ee_ptr_int; +#else +#error Define XLEN to 32, 64, or leave it undefined (same as defined to 64). +#endif +#endif +typedef size_t ee_size_t; + +typedef ee_ptr_int CORE_TICKS; + +// Use static memory allocation +#define MEM_METHOD MEM_STATIC + +typedef struct CORE_PORTABLE_S +{ + ee_u8 portable_id; +} core_portable; + +#ifndef MULTITHREAD +#define MULTITHREAD 1 // 1 means single-core +#define USE_PTHREAD 0 +#define USE_FORK 0 +#define USE_SOCKET 0 +#endif + +#ifndef COMPILER_VERSION +#ifdef __GNUC__ +#define COMPILER_VERSION "GCC"__VERSION__ +#else +#define COMPILER_VERSION "Undefined non-gcc compiler used" +#endif +#endif + +#ifndef COMPILER_FLAGS +#define COMPILER_FLAGS FLAGS_STR +#endif + +#ifndef MEM_LOCATION +#define MEM_LOCATION "" +#endif + +#ifndef SC_MEM_LOCATION +#define SC_MEM_LOCATION "UNSPECIFIED(" MEM_LOCATION ") RATIOS:1" +#endif + +#ifndef SEED_METHOD +#define SEED_METHOD SEED_VOLATILE +#endif + +#ifndef HAS_PRINTF +#define HAS_PRINTF 1 +#endif + +#define printf(...) do { \ + char text[1024]; \ + sprintf(text, __VA_ARGS__); \ + print_uart(text); \ +} while (0) + +#define align_mem(x) (void *)(4 + (((ee_ptr_int)(x)-1) & ~3)) + +#define CORETIMETYPE ee_u32 + +extern ee_u32 default_num_contexts; + +void portable_init(core_portable *p, int *argc, char *argv[]); +void portable_fini(core_portable *p); diff --git a/verif/tests/custom/coremark/core_state.c b/verif/tests/custom/coremark/core_state.c new file mode 100644 index 0000000000..32a78d7f79 --- /dev/null +++ b/verif/tests/custom/coremark/core_state.c @@ -0,0 +1,351 @@ +/* +Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +Original Author: Shay Gal-on +*/ + +// Copyright 2020 OpenHW Group +// Copyright 2020 Silicon Labs, Inc. +// Copyright 2022 Thales DIS Design Services SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier:Apache-2.0 WITH SHL-2.0 + +#include "coremark.h" +/* local functions */ +enum CORE_STATE core_state_transition(ee_u8 **instr, ee_u32 *transition_count); + +/* +Topic: Description + Simple state machines like this one are used in many embedded products. + + For more complex state machines, sometimes a state transition table +implementation is used instead, trading speed of direct coding for ease of +maintenance. + + Since the main goal of using a state machine in CoreMark is to excercise +the switch/if behaviour, we are using a small moore machine. + + In particular, this machine tests type of string input, + trying to determine whether the input is a number or something else. + (see core_state.png). +*/ + +/* Function: core_bench_state + Benchmark function + + Go over the input twice, once direct, and once after introducing some + corruption. +*/ +ee_u16 +core_bench_state(ee_u32 blksize, + ee_u8 *memblock, + ee_s16 seed1, + ee_s16 seed2, + ee_s16 step, + ee_u16 crc) +{ + ee_u32 final_counts[NUM_CORE_STATES]; + ee_u32 track_counts[NUM_CORE_STATES]; + ee_u8 *p = memblock; + ee_u32 i; + +#if CORE_DEBUG + ee_printf("State Bench: %d,%d,%d,%04x\n", seed1, seed2, step, crc); +#endif + for (i = 0; i < NUM_CORE_STATES; i++) + { + final_counts[i] = track_counts[i] = 0; + } + /* run the state machine over the input */ + while (*p != 0) + { + enum CORE_STATE fstate = core_state_transition(&p, track_counts); + final_counts[fstate]++; +#if CORE_DEBUG + ee_printf("%d,", fstate); + } + ee_printf("\n"); +#else + } +#endif + p = memblock; + while (p < (memblock + blksize)) + { /* insert some corruption */ + if (*p != ',') + *p ^= (ee_u8)seed1; + p += step; + } + p = memblock; + /* run the state machine over the input again */ + while (*p != 0) + { + enum CORE_STATE fstate = core_state_transition(&p, track_counts); + final_counts[fstate]++; +#if CORE_DEBUG + ee_printf("%d,", fstate); + } + ee_printf("\n"); +#else + } +#endif + p = memblock; + while (p < (memblock + blksize)) + { /* undo corruption is seed1 and seed2 are equal */ + if (*p != ',') + *p ^= (ee_u8)seed2; + p += step; + } + /* end timing */ + for (i = 0; i < NUM_CORE_STATES; i++) + { + crc = crcu32(final_counts[i], crc); + crc = crcu32(track_counts[i], crc); + } + return crc; +} + +/* Default initialization patterns */ +static ee_u8 *intpat[4] + = { (ee_u8 *)"5012", (ee_u8 *)"1234", (ee_u8 *)"-874", (ee_u8 *)"+122" }; +static ee_u8 *floatpat[4] = { (ee_u8 *)"35.54400", + (ee_u8 *)".1234500", + (ee_u8 *)"-110.700", + (ee_u8 *)"+0.64400" }; +static ee_u8 *scipat[4] = { (ee_u8 *)"5.500e+3", + (ee_u8 *)"-.123e-2", + (ee_u8 *)"-87e+832", + (ee_u8 *)"+0.6e-12" }; +static ee_u8 *errpat[4] = { (ee_u8 *)"T0.3e-1F", + (ee_u8 *)"-T.T++Tq", + (ee_u8 *)"1T3.4e4z", + (ee_u8 *)"34.0e-T^" }; + +/* Function: core_init_state + Initialize the input data for the state machine. + + Populate the input with several predetermined strings, interspersed. + Actual patterns chosen depend on the seed parameter. + + Note: + The seed parameter MUST be supplied from a source that cannot be + determined at compile time +*/ +void +core_init_state(ee_u32 size, ee_s16 seed, ee_u8 *p) +{ + ee_u32 total = 0, next = 0, i; + ee_u8 *buf = 0; +#if CORE_DEBUG + ee_u8 *start = p; + ee_printf("State: %d,%d\n", size, seed); +#endif + size--; + next = 0; + while ((total + next + 1) < size) + { + if (next > 0) + { + for (i = 0; i < next; i++) + *(p + total + i) = buf[i]; + *(p + total + i) = ','; + total += next + 1; + } + seed++; + switch (seed & 0x7) + { + case 0: /* int */ + case 1: /* int */ + case 2: /* int */ + buf = intpat[(seed >> 3) & 0x3]; + next = 4; + break; + case 3: /* float */ + case 4: /* float */ + buf = floatpat[(seed >> 3) & 0x3]; + next = 8; + break; + case 5: /* scientific */ + case 6: /* scientific */ + buf = scipat[(seed >> 3) & 0x3]; + next = 8; + break; + case 7: /* invalid */ + buf = errpat[(seed >> 3) & 0x3]; + next = 8; + break; + default: /* Never happen, just to make some compilers happy */ + break; + } + } + size++; +#if CORE_DEBUG + ee_printf("core_init_state: total = %d, size = %d\n"); +#endif + while (total < size) + { /* fill the rest with 0 */ + *(p + total) = 0; + total++; + } +#if CORE_DEBUG + ee_printf("State Input: %s\n", start); +#endif +} + +static ee_u8 +ee_isdigit(ee_u8 c) +{ + ee_u8 retval; + retval = ((c >= '0') & (c <= '9')) ? 1 : 0; + return retval; +} + +/* Function: core_state_transition + Actual state machine. + + The state machine will continue scanning until either: + 1 - an invalid input is detcted. + 2 - a valid number has been detected. + + The input pointer is updated to point to the end of the token, and the + end state is returned (either specific format determined or invalid). +*/ + +enum CORE_STATE +core_state_transition(ee_u8 **instr, ee_u32 *transition_count) +{ + ee_u8 * str = *instr; + ee_u8 NEXT_SYMBOL; + enum CORE_STATE state = CORE_START; + for (; *str && state != CORE_INVALID; str++) + { + NEXT_SYMBOL = *str; + if (NEXT_SYMBOL == ',') /* end of this input */ + { + str++; + break; + } + switch (state) + { + case CORE_START: + if (ee_isdigit(NEXT_SYMBOL)) + { + state = CORE_INT; + } + else if (NEXT_SYMBOL == '+' || NEXT_SYMBOL == '-') + { + state = CORE_S1; + } + else if (NEXT_SYMBOL == '.') + { + state = CORE_FLOAT; + } + else + { + state = CORE_INVALID; + transition_count[CORE_INVALID]++; + } + transition_count[CORE_START]++; + break; + case CORE_S1: + if (ee_isdigit(NEXT_SYMBOL)) + { + state = CORE_INT; + transition_count[CORE_S1]++; + } + else if (NEXT_SYMBOL == '.') + { + state = CORE_FLOAT; + transition_count[CORE_S1]++; + } + else + { + state = CORE_INVALID; + transition_count[CORE_S1]++; + } + break; + case CORE_INT: + if (NEXT_SYMBOL == '.') + { + state = CORE_FLOAT; + transition_count[CORE_INT]++; + } + else if (!ee_isdigit(NEXT_SYMBOL)) + { + state = CORE_INVALID; + transition_count[CORE_INT]++; + } + break; + case CORE_FLOAT: + if (NEXT_SYMBOL == 'E' || NEXT_SYMBOL == 'e') + { + state = CORE_S2; + transition_count[CORE_FLOAT]++; + } + else if (!ee_isdigit(NEXT_SYMBOL)) + { + state = CORE_INVALID; + transition_count[CORE_FLOAT]++; + } + break; + case CORE_S2: + if (NEXT_SYMBOL == '+' || NEXT_SYMBOL == '-') + { + state = CORE_EXPONENT; + transition_count[CORE_S2]++; + } + else + { + state = CORE_INVALID; + transition_count[CORE_S2]++; + } + break; + case CORE_EXPONENT: + if (ee_isdigit(NEXT_SYMBOL)) + { + state = CORE_SCIENTIFIC; + transition_count[CORE_EXPONENT]++; + } + else + { + state = CORE_INVALID; + transition_count[CORE_EXPONENT]++; + } + break; + case CORE_SCIENTIFIC: + if (!ee_isdigit(NEXT_SYMBOL)) + { + state = CORE_INVALID; + transition_count[CORE_INVALID]++; + } + break; + default: + break; + } + } + *instr = str; + return state; +} diff --git a/verif/tests/custom/coremark/core_util.c b/verif/tests/custom/coremark/core_util.c new file mode 100644 index 0000000000..9762f5fb7c --- /dev/null +++ b/verif/tests/custom/coremark/core_util.c @@ -0,0 +1,267 @@ +/* +Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +Original Author: Shay Gal-on +*/ + +// Copyright 2020 OpenHW Group +// Copyright 2020 Silicon Labs, Inc. +// Copyright 2022 Thales DIS Design Services SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier:Apache-2.0 WITH SHL-2.0 + +#include "coremark.h" +/* Function: get_seed + Get a values that cannot be determined at compile time. + + Since different embedded systems and compilers are used, 3 different + methods are provided: 1 - Using a volatile variable. This method is only + valid if the compiler is forced to generate code that reads the value of a + volatile variable from memory at run time. Please note, if using this method, + you would need to modify core_portme.c to generate training profile. 2 - + Command line arguments. This is the preferred method if command line + arguments are supported. 3 - System function. If none of the first 2 methods + is available on the platform, a system function which is not a stub can be + used. + + e.g. read the value on GPIO pins connected to switches, or invoke + special simulator functions. +*/ +#if (SEED_METHOD == SEED_VOLATILE) +extern volatile ee_s32 seed1_volatile; +extern volatile ee_s32 seed2_volatile; +extern volatile ee_s32 seed3_volatile; +extern volatile ee_s32 seed4_volatile; +extern volatile ee_s32 seed5_volatile; +ee_s32 +get_seed_32(int i) +{ + ee_s32 retval; + switch (i) + { + case 1: + retval = seed1_volatile; + break; + case 2: + retval = seed2_volatile; + break; + case 3: + retval = seed3_volatile; + break; + case 4: + retval = seed4_volatile; + break; + case 5: + retval = seed5_volatile; + break; + default: + retval = 0; + break; + } + return retval; +} +#elif (SEED_METHOD == SEED_ARG) +ee_s32 +parseval(char *valstring) +{ + ee_s32 retval = 0; + ee_s32 neg = 1; + int hexmode = 0; + if (*valstring == '-') + { + neg = -1; + valstring++; + } + if ((valstring[0] == '0') && (valstring[1] == 'x')) + { + hexmode = 1; + valstring += 2; + } + /* first look for digits */ + if (hexmode) + { + while (((*valstring >= '0') && (*valstring <= '9')) + || ((*valstring >= 'a') && (*valstring <= 'f'))) + { + ee_s32 digit = *valstring - '0'; + if (digit > 9) + digit = 10 + *valstring - 'a'; + retval *= 16; + retval += digit; + valstring++; + } + } + else + { + while ((*valstring >= '0') && (*valstring <= '9')) + { + ee_s32 digit = *valstring - '0'; + retval *= 10; + retval += digit; + valstring++; + } + } + /* now add qualifiers */ + if (*valstring == 'K') + retval *= 1024; + if (*valstring == 'M') + retval *= 1024 * 1024; + + retval *= neg; + return retval; +} + +ee_s32 +get_seed_args(int i, int argc, char *argv[]) +{ + if (argc > i) + return parseval(argv[i]); + return 0; +} + +#elif (SEED_METHOD == SEED_FUNC) +/* If using OS based function, you must define and implement the functions below + * in core_portme.h and core_portme.c ! */ +ee_s32 +get_seed_32(int i) +{ + ee_s32 retval; + switch (i) + { + case 1: + retval = portme_sys1(); + break; + case 2: + retval = portme_sys2(); + break; + case 3: + retval = portme_sys3(); + break; + case 4: + retval = portme_sys4(); + break; + case 5: + retval = portme_sys5(); + break; + default: + retval = 0; + break; + } + return retval; +} +#endif + +/* Function: crc* + Service functions to calculate 16b CRC code. + +*/ +ee_u16 +crcu8(ee_u8 data, ee_u16 crc) +{ + ee_u8 i = 0, x16 = 0, carry = 0; + + for (i = 0; i < 8; i++) + { + x16 = (ee_u8)((data & 1) ^ ((ee_u8)crc & 1)); + data >>= 1; + + if (x16 == 1) + { + crc ^= 0x4002; + carry = 1; + } + else + carry = 0; + crc >>= 1; + if (carry) + crc |= 0x8000; + else + crc &= 0x7fff; + } + return crc; +} +ee_u16 +crcu16(ee_u16 newval, ee_u16 crc) +{ + crc = crcu8((ee_u8)(newval), crc); + crc = crcu8((ee_u8)((newval) >> 8), crc); + return crc; +} +ee_u16 +crcu32(ee_u32 newval, ee_u16 crc) +{ + crc = crc16((ee_s16)newval, crc); + crc = crc16((ee_s16)(newval >> 16), crc); + return crc; +} +ee_u16 +crc16(ee_s16 newval, ee_u16 crc) +{ + return crcu16((ee_u16)newval, crc); +} + +ee_u8 +check_data_types() +{ + ee_u8 retval = 0; + if (sizeof(ee_u8) != 1) + { + ee_printf("ERROR: ee_u8 is not an 8b datatype!\n"); + retval++; + } + if (sizeof(ee_u16) != 2) + { + ee_printf("ERROR: ee_u16 is not a 16b datatype!\n"); + retval++; + } + if (sizeof(ee_s16) != 2) + { + ee_printf("ERROR: ee_s16 is not a 16b datatype!\n"); + retval++; + } + if (sizeof(ee_s32) != 4) + { + ee_printf("ERROR: ee_s32 is not a 32b datatype!\n"); + retval++; + } + if (sizeof(ee_u32) != 4) + { + ee_printf("ERROR: ee_u32 is not a 32b datatype!\n"); + retval++; + } + if (sizeof(ee_ptr_int) != sizeof(int *)) + { + ee_printf( + "ERROR: ee_ptr_int is not a datatype that holds an int pointer!\n"); + retval++; + } + if (retval > 0) + { + ee_printf("ERROR: Please modify the datatypes in core_portme.h!\n"); + } + return retval; +} diff --git a/verif/tests/custom/coremark/coremark.h b/verif/tests/custom/coremark/coremark.h new file mode 100644 index 0000000000..a97c5eeea4 --- /dev/null +++ b/verif/tests/custom/coremark/coremark.h @@ -0,0 +1,203 @@ +/* +Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +Original Author: Shay Gal-on +*/ + +// Copyright 2020 OpenHW Group +// Copyright 2020 Silicon Labs, Inc. +// Copyright 2022 Thales DIS Design Services SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier:Apache-2.0 WITH SHL-2.0 + +/* Topic: Description + This file contains declarations of the various benchmark functions. +*/ + +/* Configuration: TOTAL_DATA_SIZE + Define total size for data algorithms will operate on +*/ +#ifndef TOTAL_DATA_SIZE +#define TOTAL_DATA_SIZE 2 * 1000 +#endif + +#define SEED_ARG 0 +#define SEED_FUNC 1 +#define SEED_VOLATILE 2 + +#define MEM_STATIC 0 +#define MEM_MALLOC 1 +#define MEM_STACK 2 + +#include "core_portme.h" + +#if HAS_STDIO +#include <stdio.h> +#endif +#if HAS_PRINTF +#define ee_printf printf +#else +#define ee_printf(...) +#endif + +/* Actual benchmark execution in iterate */ +void *iterate(void *pres); + +/* Typedef: secs_ret + For machines that have floating point support, get number of seconds as + a double. Otherwise an unsigned int. +*/ +#if HAS_FLOAT +typedef double secs_ret; +#else +typedef ee_u32 secs_ret; +#endif + +#if MAIN_HAS_NORETURN +#define MAIN_RETURN_VAL +#define MAIN_RETURN_TYPE void +#else +#define MAIN_RETURN_VAL 0 +#define MAIN_RETURN_TYPE int +#endif + +void start_time(void); +void stop_time(void); +CORE_TICKS get_time(void); +secs_ret time_in_secs(CORE_TICKS ticks); + +/* Misc useful functions */ +ee_u16 crcu8(ee_u8 data, ee_u16 crc); +ee_u16 crc16(ee_s16 newval, ee_u16 crc); +ee_u16 crcu16(ee_u16 newval, ee_u16 crc); +ee_u16 crcu32(ee_u32 newval, ee_u16 crc); +ee_u8 check_data_types(void); +void * portable_malloc(ee_size_t size); +void portable_free(void *p); +ee_s32 parseval(char *valstring); + +/* Algorithm IDS */ +#define ID_LIST (1 << 0) +#define ID_MATRIX (1 << 1) +#define ID_STATE (1 << 2) +#define ALL_ALGORITHMS_MASK (ID_LIST | ID_MATRIX | ID_STATE) +#define NUM_ALGORITHMS 3 + +/* list data structures */ +typedef struct list_data_s +{ + ee_s16 data16; + ee_s16 idx; +} list_data; + +typedef struct list_head_s +{ + struct list_head_s *next; + struct list_data_s *info; +} list_head; + +/*matrix benchmark related stuff */ +#define MATDAT_INT 1 +#if MATDAT_INT +typedef ee_s16 MATDAT; +typedef ee_s32 MATRES; +#else +typedef ee_f16 MATDAT; +typedef ee_f32 MATRES; +#endif + +typedef struct MAT_PARAMS_S +{ + int N; + MATDAT *A; + MATDAT *B; + MATRES *C; +} mat_params; + +/* state machine related stuff */ +/* List of all the possible states for the FSM */ +typedef enum CORE_STATE +{ + CORE_START = 0, + CORE_INVALID, + CORE_S1, + CORE_S2, + CORE_INT, + CORE_FLOAT, + CORE_EXPONENT, + CORE_SCIENTIFIC, + NUM_CORE_STATES +} core_state_e; + +/* Helper structure to hold results */ +typedef struct RESULTS_S +{ + /* inputs */ + ee_s16 seed1; /* Initializing seed */ + ee_s16 seed2; /* Initializing seed */ + ee_s16 seed3; /* Initializing seed */ + void * memblock[4]; /* Pointer to safe memory location */ + ee_u32 size; /* Size of the data */ + ee_u32 iterations; /* Number of iterations to execute */ + ee_u32 execs; /* Bitmask of operations to execute */ + struct list_head_s *list; + mat_params mat; + /* outputs */ + ee_u16 crc; + ee_u16 crclist; + ee_u16 crcmatrix; + ee_u16 crcstate; + ee_s16 err; + /* ultithread specific */ + core_portable port; +} core_results; + +/* Multicore execution handling */ +#if (MULTITHREAD > 1) +ee_u8 core_start_parallel(core_results *res); +ee_u8 core_stop_parallel(core_results *res); +#endif + +/* list benchmark functions */ +list_head *core_list_init(ee_u32 blksize, list_head *memblock, ee_s16 seed); +ee_u16 core_bench_list(core_results *res, ee_s16 finder_idx); + +/* state benchmark functions */ +void core_init_state(ee_u32 size, ee_s16 seed, ee_u8 *p); +ee_u16 core_bench_state(ee_u32 blksize, + ee_u8 *memblock, + ee_s16 seed1, + ee_s16 seed2, + ee_s16 step, + ee_u16 crc); + +/* matrix benchmark functions */ +ee_u32 core_init_matrix(ee_u32 blksize, + void * memblk, + ee_s32 seed, + mat_params *p); +ee_u16 core_bench_matrix(mat_params *p, ee_s16 seed, ee_u16 crc); diff --git a/verif/tests/custom/coremark/uart.c b/verif/tests/custom/coremark/uart.c new file mode 100644 index 0000000000..b6ab19b7b3 --- /dev/null +++ b/verif/tests/custom/coremark/uart.c @@ -0,0 +1,91 @@ +#include "uart.h" + +void write_reg_u8(uintptr_t addr, uint8_t value) +{ + volatile uint8_t *loc_addr = (volatile uint8_t *)addr; + *loc_addr = value; +} + +uint8_t read_reg_u8(uintptr_t addr) +{ + return *(volatile uint8_t *)addr; +} + +int is_transmit_empty() +{ + return read_reg_u8(UART_LINE_STATUS) & 0x20; +} + +void write_serial(char a) +{ + while (is_transmit_empty() == 0) {}; + + write_reg_u8(UART_THR, a); +} + +void init_uart(uint32_t freq, uint32_t baud) +{ + uint32_t divisor = freq / (baud << 4); + + write_reg_u8(UART_INTERRUPT_ENABLE, 0x00); // Disable all interrupts + write_reg_u8(UART_LINE_CONTROL, 0x80); // Enable DLAB (set baud rate divisor) + write_reg_u8(UART_DLAB_LSB, divisor); // divisor (lo byte) + write_reg_u8(UART_DLAB_MSB, (divisor >> 8) & 0xFF); // divisor (hi byte) + write_reg_u8(UART_LINE_CONTROL, 0x03); // 8 bits, no parity, one stop bit + write_reg_u8(UART_FIFO_CONTROL, 0xC7); // Enable FIFO, clear them, with 14-byte threshold + write_reg_u8(UART_MODEM_CONTROL, 0x20); // Autoflow mode +} + +void print_uart(const char *str) +{ + const char *cur = &str[0]; + while (*cur != '\0') + { + write_serial((uint8_t)*cur); + ++cur; + } +} + +uint8_t bin_to_hex_table[16] = { + '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F'}; + +void bin_to_hex(uint8_t inp, uint8_t res[2]) +{ + res[1] = bin_to_hex_table[inp & 0xf]; + res[0] = bin_to_hex_table[(inp >> 4) & 0xf]; + return; +} + +void print_uart_int(uint32_t addr) +{ + int i; + for (i = 3; i > -1; i--) + { + uint8_t cur = (addr >> (i * 8)) & 0xff; + uint8_t hex[2]; + bin_to_hex(cur, hex); + write_serial(hex[0]); + write_serial(hex[1]); + } +} + +void print_uart_addr(uint64_t addr) +{ + int i; + for (i = 7; i > -1; i--) + { + uint8_t cur = (addr >> (i * 8)) & 0xff; + uint8_t hex[2]; + bin_to_hex(cur, hex); + write_serial(hex[0]); + write_serial(hex[1]); + } +} + +void print_uart_byte(uint8_t byte) +{ + uint8_t hex[2]; + bin_to_hex(byte, hex); + write_serial(hex[0]); + write_serial(hex[1]); +} \ No newline at end of file diff --git a/verif/tests/custom/coremark/uart.h b/verif/tests/custom/coremark/uart.h new file mode 100644 index 0000000000..6505c6bb0e --- /dev/null +++ b/verif/tests/custom/coremark/uart.h @@ -0,0 +1,27 @@ +#pragma once + +#include <stdint.h> + +#define UART_BASE 0x10000000 + +#define UART_RBR UART_BASE + 0 +#define UART_THR UART_BASE + 0 +#define UART_INTERRUPT_ENABLE UART_BASE + 4 +#define UART_INTERRUPT_IDENT UART_BASE + 8 +#define UART_FIFO_CONTROL UART_BASE + 8 +#define UART_LINE_CONTROL UART_BASE + 12 +#define UART_MODEM_CONTROL UART_BASE + 16 +#define UART_LINE_STATUS UART_BASE + 20 +#define UART_MODEM_STATUS UART_BASE + 24 +#define UART_DLAB_LSB UART_BASE + 0 +#define UART_DLAB_MSB UART_BASE + 4 + +void init_uart(); + +void print_uart(const char* str); + +void print_uart_int(uint32_t addr); + +void print_uart_addr(uint64_t addr); + +void print_uart_byte(uint8_t byte); \ No newline at end of file diff --git a/verif/tests/custom/csr_access_tests/riscv_mscratch_csr_test_0.S b/verif/tests/custom/csr_access_tests/riscv_mscratch_csr_test_0.S new file mode 100644 index 0000000000..812036b9e5 --- /dev/null +++ b/verif/tests/custom/csr_access_tests/riscv_mscratch_csr_test_0.S @@ -0,0 +1,92 @@ +#include "model_test.h" +.macro init +.endm +.section .text.init +.globl _start +.option norvc +.org 0x00 +_start: +RVMODEL_BOOT + # CSR_MSCRATCH + li x10, 0xa5a5a5a5 + csrrw x14, 0x340, x10 + li x10, 0x00000000 + bne x10, x14, csr_fail + li x10, 0x5a5a5a5a + csrrw x14, 0x340, x10 + li x10, 0xa5a5a5a5 + bne x10, x14, csr_fail + li x10, 0x6c218674 + csrrw x14, 0x340, x10 + li x10, 0x5a5a5a5a + bne x10, x14, csr_fail + li x10, 0xa5a5a5a5 + csrrs x14, 0x340, x10 + li x10, 0x6c218674 + bne x10, x14, csr_fail + li x10, 0x5a5a5a5a + csrrs x14, 0x340, x10 + li x10, 0xeda5a7f5 + bne x10, x14, csr_fail + li x10, 0xdd2d25a6 + csrrs x14, 0x340, x10 + li x10, 0xffffffff + bne x10, x14, csr_fail + li x10, 0xa5a5a5a5 + csrrc x14, 0x340, x10 + li x10, 0xffffffff + bne x10, x14, csr_fail + li x10, 0x5a5a5a5a + csrrc x14, 0x340, x10 + li x10, 0x5a5a5a5a + bne x10, x14, csr_fail + li x10, 0x8959179c + csrrc x14, 0x340, x10 + li x10, 0x00000000 + bne x10, x14, csr_fail + csrrwi x14, 0x340, 0b00101 + li x10, 0x00000000 + bne x10, x14, csr_fail + csrrwi x14, 0x340, 0b11010 + li x10, 0x00000005 + bne x10, x14, csr_fail + csrrwi x14, 0x340, 0b01110 + li x10, 0x0000001a + bne x10, x14, csr_fail + csrrsi x14, 0x340, 0b00101 + li x10, 0x0000000e + bne x10, x14, csr_fail + csrrsi x14, 0x340, 0b11010 + li x10, 0x0000000f + bne x10, x14, csr_fail + csrrsi x14, 0x340, 0b00000 + li x10, 0x0000001f + bne x10, x14, csr_fail + csrrci x14, 0x340, 0b00101 + li x10, 0x0000001f + bne x10, x14, csr_fail + csrrci x14, 0x340, 0b11010 + li x10, 0x0000001a + bne x10, x14, csr_fail + csrrci x14, 0x340, 0b00100 + li x10, 0x00000000 + bne x10, x14, csr_fail + csrr x14, 0x340 + li x10, 0x00000000 + bne x10, x14, csr_fail +csr_pass: + li x1, 0 + slli x1, x1, 1 + addi x1, x1, 1 + sw x1, tohost, x30 + self_loop: j self_loop + +csr_fail: + li x1, 1 + slli x1, x1, 1 + addi x1, x1, 1 + sw x1, tohost, x30 + self_loop_2: j self_loop_2 + +RVMODEL_DATA_BEGIN +RVMODEL_DATA_END diff --git a/verif/tests/custom/csr_access_yaml/cva6_mscratch_csr_access.yaml b/verif/tests/custom/csr_access_yaml/cva6_mscratch_csr_access.yaml new file mode 100644 index 0000000000..9d5a17d705 --- /dev/null +++ b/verif/tests/custom/csr_access_yaml/cva6_mscratch_csr_access.yaml @@ -0,0 +1,14 @@ +- csr: CSR_MSCRATCH + description: > + Scratch register for machine trap handlers + address: 0x340 + privilege_mode: M + rv32: + - field_name: mscratch + description: > + hold a pointer to a machine-mode hart-local context space and swapped with a user register upon entry to an M-mode trap handler + type: RW + reset_val: 0 + msb: 31 + lsb: 0 + diff --git a/verif/tests/custom/cv_xif/cvxif_add_nop.S b/verif/tests/custom/cv_xif/cvxif_add_nop.S new file mode 100644 index 0000000000..6a88eaa667 --- /dev/null +++ b/verif/tests/custom/cv_xif/cvxif_add_nop.S @@ -0,0 +1,49 @@ +# See LICENSE for license details. + +#***************************************************************************** +# Copyright 2022 Thales DIS design services SAS +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https:#solderpad.org/licenses/ +# +#---------------------------------------------------------------------------------- + +#include "cvxif_macros.h" + + #------------------------------------------------------------- + # Custom tests + #------------------------------------------------------------- + + .globl main +main: + +# core of the test + + LOAD_RS(a0, 0x332211); + LOAD_RS(a1, 0xDEADBEEF); + LOAD_RS(a2, 0xDEADBEEF); + + CUS_ADD(01010,01010,01010,01011); + CUS_NOP(00000,00000,00000,00000); + CUS_NOP(00000,00000,00000,00000); + CUS_ADD(01010,01010,01010,01011); + CUS_NOP(00000,00000,00000,00000); + CUS_ADD(01010,01010,01010,01011); + +# (example of) final self-check test + li a0, 0xCAFE; + li a1, 0xCAFE; + xor a2, a0, a1; + beqz a2, pass; + +fail: + # Failure post-processing (messages, ecall setup etc.) + li a0, 0x0; + jal exit; + +pass: + # Success post-processing (messages, ecall setup etc.) + li a0, 0x0; + jal exit; diff --git a/verif/tests/custom/cv_xif/cvxif_exc.S b/verif/tests/custom/cv_xif/cvxif_exc.S new file mode 100644 index 0000000000..1f015eb7c2 --- /dev/null +++ b/verif/tests/custom/cv_xif/cvxif_exc.S @@ -0,0 +1,48 @@ +# See LICENSE for license details. + +#***************************************************************************** +# Copyright 2021 Thales DIS design services SAS +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https:#solderpad.org/licenses/ +# +#---------------------------------------------------------------------------------- + +#include "cvxif_macros.h" + + #------------------------------------------------------------- + # Custom tests + #------------------------------------------------------------- + + .globl main +main: + +# core of the test + + LOAD_RS(a0, 0x332211); + LOAD_RS(a1, 0xDEADBEEF); + LOAD_RS(a2, 0xDEADBEEF); + + CUS_ADD(01010,01010,01010,01011); + CUS_EXC(01111,00000,00000,00000); + CUS_ADD(01111,00111,00111,00011); + CUS_EXC(01111,00000,00000,00000); + CUS_ADD(01111,00111,00111,00011); + +# (example of) final self-check test + li a0, 0xCAFE; + li a1, 0xCAFE; + xor a2, a0, a1; + beqz a2, pass; + +fail: + # Failure post-processing (messages, ecall setup etc.) + li a0, 0x0; + jal exit; + +pass: + # Success post-processing (messages, ecall setup etc.) + li a0, 0x0; + jal exit; diff --git a/verif/tests/custom/cv_xif/cvxif_illegal.S b/verif/tests/custom/cv_xif/cvxif_illegal.S new file mode 100644 index 0000000000..49173c7ed8 --- /dev/null +++ b/verif/tests/custom/cv_xif/cvxif_illegal.S @@ -0,0 +1,46 @@ +# See LICENSE for license details. + +#***************************************************************************** +# Copyright 2021 Thales DIS design services SAS +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https:#solderpad.org/licenses/ +# +#---------------------------------------------------------------------------------- + +#include "cvxif_macros.h" + + #------------------------------------------------------------- + # Custom tests + #------------------------------------------------------------- + + .globl main +main: + +# core of the test + + LOAD_RS(a0, 0x332211); + LOAD_RS(a1, 0xDEADBEEF); + LOAD_RS(a2, 0xDEADBEEF); + + CUS_ADD(01010,01010,01010,01011); + CUS_ADD(01010,01010,01010,00000); #illegal_instr + CUS_ADD(01010,01010,01010,01011); + +# (example of) final self-check test + li a0, 0xCAFE; + li a1, 0xCAFE; + xor a2, a0, a1; + beqz a2, pass; + +fail: + # Failure post-processing (messages, ecall setup etc.) + li a0, 0x0; + jal exit; + +pass: + # Success post-processing (messages, ecall setup etc.) + li a0, 0x0; + jal exit; diff --git a/verif/tests/custom/cv_xif/cvxif_issexc.S b/verif/tests/custom/cv_xif/cvxif_issexc.S new file mode 100644 index 0000000000..bb521cec70 --- /dev/null +++ b/verif/tests/custom/cv_xif/cvxif_issexc.S @@ -0,0 +1,50 @@ +# See LICENSE for license details. + +#***************************************************************************** +# Copyright 2022 Thales DIS design services SAS +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https:#solderpad.org/licenses/ +# +#---------------------------------------------------------------------------------- + +#include "cvxif_macros.h" + + #------------------------------------------------------------- + # Custom tests + #------------------------------------------------------------- + + .globl main +main: + +# core of the test + + LOAD_RS(a0, 0x332211); + LOAD_RS(a1, 0xDEADBEEF); + LOAD_RS(a2, 0xDEADBEEF); + + CUS_ADD(01010,01010,01010,01011); + CUS_ISS_EXC(00000,00000,00000,00000); + CUS_ADD(01010,01010,01010,01011); + CUS_ADD(01010,01010,01010,01011); + CUS_ISS_EXC(00000,00000,00000,00000); + CUS_ADD(11110,11000,11100,00001); + CUS_ADD(01111,00111,00111,00011); + +# (example of) final self-check test + li a0, 0xCAFE; + li a1, 0xCAFE; + xor a2, a0, a1; + beqz a2, pass; + +fail: + # Failure post-processing (messages, ecall setup etc.) + li a0, 0x0; + jal exit; + +pass: + # Success post-processing (messages, ecall setup etc.) + li a0, 0x0; + jal exit; diff --git a/verif/tests/custom/cv_xif/cvxif_macros.h b/verif/tests/custom/cv_xif/cvxif_macros.h new file mode 100644 index 0000000000..f7e4448ce8 --- /dev/null +++ b/verif/tests/custom/cv_xif/cvxif_macros.h @@ -0,0 +1,19 @@ +// Copyright 2021 Thales DIS design services SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Zineb EL KACIMI (zineb.el-kacimi@external.thalesgroup.com) + + +#define LOAD_RS(rs,value) li rs, value +#define COMP_RS(rs1,rs2,rd) xor rd, rs1, rs2 +#define CUS_ADD(rs1,rs2,rd) .word 0b##0000000##rs2####rs1##001##rd##1111011 +#define CUS_NOP(rs1,rs2,rd) .word 0b##0000000##00000####00000##000##00000##1111011 +#define CUS_ADD_RS3(rs1,rs2,rs3,rd) .word 0b##rs3##01##rs2####rs1##000##rd##1111011 +#define CUS_ADD_MULTI(rs1,rs2,rd) .word 0b##0001000##rs2####rs1##000##rd##1111011 +#define CUS_EXC(rs1,rs2,rs3,rd) .word 0b####1100000##rs2####rs1##010##rd##1111011 +#define CUS_U_ADD(rs1,rs2,rd) .word 0b####0000010##rs2####rs1##000##rd##1111011 +#define CUS_S_ADD(rs1,rs2,rd) .word 0b####0000110##rs2####rs1##000##rd##1111011 diff --git a/verif/tests/custom/cv_xif/cvxif_multi.S b/verif/tests/custom/cv_xif/cvxif_multi.S new file mode 100644 index 0000000000..53308a16e0 --- /dev/null +++ b/verif/tests/custom/cv_xif/cvxif_multi.S @@ -0,0 +1,54 @@ +# See LICENSE for license details. + +#***************************************************************************** +# Copyright 2021 Thales DIS design services SAS +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https:#solderpad.org/licenses/ +# +#---------------------------------------------------------------------------------- + +#include "cvxif_macros.h" + + #------------------------------------------------------------- + # Custom tests + #------------------------------------------------------------- + + .globl main +main: + +# core of the test + + LOAD_RS(a0, 0x332211); + LOAD_RS(a1, 0xDEADBEEF); + LOAD_RS(a2, 0xDEADBEEF); + + CUS_ADD(01010,01010,01010,01011); + CUS_ADD_MULTI(01010,01010,0000001,01011); + CUS_ADD(01111,00111,00111,00011); + CUS_ADD(10100,10010,10001,00100); + CUS_ADD_MULTI(01010,01010,0000001,01011); + CUS_ADD(11010,11001,10110,11011); + CUS_ADD(01010,01010,01010,01011); + CUS_ADD(11101,01100,00110,11111); + CUS_ADD_MULTI(01010,01010,0000001,01011); + CUS_ADD(11110,11000,11100,00001); + CUS_ADD(01111,00111,00111,00011); + +# (example of) final self-check test + li a0, 0xCAFE; + li a1, 0xCAFE; + xor a2, a0, a1; + beqz a2, pass; + +fail: + # Failure post-processing (messages, ecall setup etc.) + li a0, 0x0; + jal exit; + +pass: + # Success post-processing (messages, ecall setup etc.) + li a0, 0x0; + jal exit; diff --git a/verif/tests/custom/cv_xif/cvxif_nopexc.S b/verif/tests/custom/cv_xif/cvxif_nopexc.S new file mode 100644 index 0000000000..fb1c29976e --- /dev/null +++ b/verif/tests/custom/cv_xif/cvxif_nopexc.S @@ -0,0 +1,50 @@ +# See LICENSE for license details. + +#***************************************************************************** +# Copyright 2022 Thales DIS design services SAS +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https:#solderpad.org/licenses/ +# +#---------------------------------------------------------------------------------- + +#include "cvxif_macros.h" + + #------------------------------------------------------------- + # Custom tests + #------------------------------------------------------------- + + .globl main +main: + +# core of the test + + LOAD_RS(a0, 0x332211); + LOAD_RS(a1, 0xDEADBEEF); + LOAD_RS(a2, 0xDEADBEEF); + + CUS_ADD(01010,01010,01010,01011); + CUS_NOP_EXC(00000,00000,00000,00000); + CUS_ADD(01010,01010,01010,01011); + CUS_ADD(01010,01010,01010,01011); + CUS_NOP_EXC(00000,00000,00000,00000); + CUS_ADD(11110,11000,11100,00001); + CUS_ADD(01111,00111,00111,00011); + +# (example of) final self-check test + li a0, 0xCAFE; + li a1, 0xCAFE; + xor a2, a0, a1; + beqz a2, pass; + +fail: + # Failure post-processing (messages, ecall setup etc.) + li a0, 0x0; + jal exit; + +pass: + # Success post-processing (messages, ecall setup etc.) + li a0, 0x0; + jal exit; diff --git a/verif/tests/custom/cv_xif/cvxif_rs3.S b/verif/tests/custom/cv_xif/cvxif_rs3.S new file mode 100644 index 0000000000..9e4b84c821 --- /dev/null +++ b/verif/tests/custom/cv_xif/cvxif_rs3.S @@ -0,0 +1,53 @@ +# See LICENSE for license details. + +#***************************************************************************** +# Copyright 2022 Thales DIS design services SAS +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https:#solderpad.org/licenses/ +# +#---------------------------------------------------------------------------------- + +#include "cvxif_macros.h" + + #------------------------------------------------------------- + # Custom tests + #------------------------------------------------------------- + + .globl main +main: + +# core of the test + + LOAD_RS(a0, 0x332211); + LOAD_RS(a1, 0xDEADBEEF); + LOAD_RS(a2, 0xDEADBEEF); + + CUS_ADD(01010,01010,01010,01011); + CUS_ADD_RS3(01010,01010,01010,01011); + CUS_ADD(01111,00111,00111,00011); + CUS_ADD_RS3(01111,00111,00111,00011); + CUS_ADD_RS3(10100,10010,10001,00100); + CUS_ADD_RS3(11010,11001,10110,11011); + CUS_ADD(01010,01010,01010,01011); + CUS_ADD_RS3(11101,01100,00110,11111); + CUS_ADD(11110,11000,11100,00001); + CUS_ADD_RS3(01111,00111,00111,00011); + +# (example of) final self-check test + li a0, 0xCAFE; + li a1, 0xCAFE; + xor a2, a0, a1; + beqz a2, pass; + +fail: + # Failure post-processing (messages, ecall setup etc.) + li a0, 0x0; + jal exit; + +pass: + # Success post-processing (messages, ecall setup etc.) + li a0, 0x0; + jal exit; diff --git a/verif/tests/custom/cv_xif/cvxif_s_mode.S b/verif/tests/custom/cv_xif/cvxif_s_mode.S new file mode 100644 index 0000000000..2da7522374 --- /dev/null +++ b/verif/tests/custom/cv_xif/cvxif_s_mode.S @@ -0,0 +1,73 @@ +# Copyright 2023 Thales DIS +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Original Author: Ayoub JALALI (ayoub.jalali@external.thalesgroup.com) + +#include "cvxif_macros.h" + +#***************************************************************************** +# cvxif_s_mode.S +#----------------------------------------------------------------------------- +# + + .globl main +main: + ## set start address range t0 x7 + la x7, supervisor_code + li x28, 0x10000 + add x7, x7, x28 + # Enable R,W,X,TOR IN PMPCFG CSR t0 x8 + li x8, 0x0F + #set PMPADDR0 CSR with x7 + csrw 0x3B0, x7 + # set PMPCFG0 CSR with x8 + csrw 0x3A0, x8 + + # Set the MPP field to supervisor mode (1) + li x29, 0b01 + slli x29, x29, 11 + or x28, x28, x29 + + # Write the modified MSTATUS value back to the CSR + csrw 0x300, x28 + + # Load address of supervisor code + la x28, supervisor_code + #set MEPC register to address of supervisor code + csrw 0x341, x28 + + csrr x31, 0x300 + mret +supervisor_code: + + CUS_S_ADD(01010,01010,01011); + CUS_S_ADD(01010,11111,11010); + CUS_ADD_MULTI(01010,01010,01011); + CUS_ADD(11010,11001,11011); + CUS_ADD(01010,01010,01011); + CUS_S_ADD(10000,00010,00000); + CUS_S_ADD(11111,11110,11111); + CUS_S_ADD(00000,01010,01011); + CUS_S_ADD(01010,01010,01011); + CUS_ADD_MULTI(01010,00000,01011); + CUS_S_ADD(11111,11111,01011); + +# (example of) final self-check test + li a0, 0xCAFE; + li a1, 0xCAFE; + xor a2, a0, a1; + beqz a2, pass; + +fail: + # Failure post-processing (messages, ecall setup etc.) + li a0, 0x0; + jal exit; + +pass: + # Success post-processing (messages, ecall setup etc.) + li a0, 0x0; + jal exit; diff --git a/verif/tests/custom/cv_xif/cvxif_u_mode.S b/verif/tests/custom/cv_xif/cvxif_u_mode.S new file mode 100644 index 0000000000..fd03ebe8b4 --- /dev/null +++ b/verif/tests/custom/cv_xif/cvxif_u_mode.S @@ -0,0 +1,73 @@ +# Copyright 2023 Thales DIS +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Original Author: Ayoub JALALI (ayoub.jalali@external.thalesgroup.com) + +#include "cvxif_macros.h" + +#***************************************************************************** +# cvxif_s_mode.S +#----------------------------------------------------------------------------- +# + + .globl main +main: + ## set start address range t0 x7 + la x7, user_code + li x28, 0x10000 + add x7, x7, x28 + # Enable R,W,X,TOR IN PMPCFG CSR t0 x8 + li x8, 0x0F + #set PMPADDR0 CSR with x7 + csrw 0x3B0, x7 + # set PMPCFG0 CSR with x8 + csrw 0x3A0, x8 + + # Set the MPP field to user mode (0) + li x29, 0b00 + slli x29, x29, 11 + or x28, x28, x29 + + # Write the modified MSTATUS value back to the CSR + csrw 0x300, x28 + + # Load address of user code + la x28, user_code + #set MEPC register to address of user code + csrw 0x341, x28 + + csrr x31, 0x300 + mret +user_code: + + CUS_U_ADD(01010,01010,01011); + CUS_U_ADD(01010,11111,11010); + CUS_ADD_MULTI(01010,01010,01011); + CUS_ADD(11010,11001,11011); + CUS_ADD(01010,01010,01011); + CUS_U_ADD(10000,00010,00000); + CUS_U_ADD(11111,11110,11111); + CUS_U_ADD(00000,01010,01011); + CUS_U_ADD(01010,01010,01011); + CUS_ADD_MULTI(01010,00000,01011); + CUS_U_ADD(11111,11111,01011); + +# (example of) final self-check test + li a0, 0xCAFE; + li a1, 0xCAFE; + xor a2, a0, a1; + beqz a2, pass; + +fail: + # Failure post-processing (messages, ecall setup etc.) + li a0, 0x0; + jal exit; + +pass: + # Success post-processing (messages, ecall setup etc.) + li a0, 0x0; + jal exit; diff --git a/verif/tests/custom/env/LICENSE b/verif/tests/custom/env/LICENSE new file mode 100644 index 0000000000..48fe522ac5 --- /dev/null +++ b/verif/tests/custom/env/LICENSE @@ -0,0 +1,24 @@ +Copyright (c) 2012-2015, The Regents of the University of California (Regents). +All Rights Reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. Neither the name of the Regents nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + +IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, +SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING +OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS +BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED +HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE +MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. diff --git a/verif/tests/custom/env/encoding.h b/verif/tests/custom/env/encoding.h new file mode 100644 index 0000000000..584bc272a1 --- /dev/null +++ b/verif/tests/custom/env/encoding.h @@ -0,0 +1,2828 @@ +/* See LICENSE for license details. */ + +#ifndef RISCV_CSR_ENCODING_H +#define RISCV_CSR_ENCODING_H + +#define MSTATUS_UIE 0x00000001 +#define MSTATUS_SIE 0x00000002 +#define MSTATUS_HIE 0x00000004 +#define MSTATUS_MIE 0x00000008 +#define MSTATUS_UPIE 0x00000010 +#define MSTATUS_SPIE 0x00000020 +#define MSTATUS_HPIE 0x00000040 +#define MSTATUS_MPIE 0x00000080 +#define MSTATUS_SPP 0x00000100 +#define MSTATUS_VS 0x00000600 +#define MSTATUS_MPP 0x00001800 +#define MSTATUS_FS 0x00006000 +#define MSTATUS_XS 0x00018000 +#define MSTATUS_MPRV 0x00020000 +#define MSTATUS_SUM 0x00040000 +#define MSTATUS_MXR 0x00080000 +#define MSTATUS_TVM 0x00100000 +#define MSTATUS_TW 0x00200000 +#define MSTATUS_TSR 0x00400000 +#define MSTATUS32_SD 0x80000000 +#define MSTATUS_UXL 0x0000000300000000 +#define MSTATUS_SXL 0x0000000C00000000 +#define MSTATUS64_SD 0x8000000000000000 + +#define SSTATUS_UIE 0x00000001 +#define SSTATUS_SIE 0x00000002 +#define SSTATUS_UPIE 0x00000010 +#define SSTATUS_SPIE 0x00000020 +#define SSTATUS_SPP 0x00000100 +#define SSTATUS_VS 0x00000600 +#define SSTATUS_FS 0x00006000 +#define SSTATUS_XS 0x00018000 +#define SSTATUS_SUM 0x00040000 +#define SSTATUS_MXR 0x00080000 +#define SSTATUS32_SD 0x80000000 +#define SSTATUS_UXL 0x0000000300000000 +#define SSTATUS64_SD 0x8000000000000000 + +#define USTATUS_UIE 0x00000001 +#define USTATUS_UPIE 0x00000010 + +#define DCSR_XDEBUGVER (3U<<30) +#define DCSR_NDRESET (1<<29) +#define DCSR_FULLRESET (1<<28) +#define DCSR_EBREAKM (1<<15) +#define DCSR_EBREAKH (1<<14) +#define DCSR_EBREAKS (1<<13) +#define DCSR_EBREAKU (1<<12) +#define DCSR_STOPCYCLE (1<<10) +#define DCSR_STOPTIME (1<<9) +#define DCSR_CAUSE (7<<6) +#define DCSR_DEBUGINT (1<<5) +#define DCSR_HALT (1<<3) +#define DCSR_STEP (1<<2) +#define DCSR_PRV (3<<0) + +#define DCSR_CAUSE_NONE 0 +#define DCSR_CAUSE_SWBP 1 +#define DCSR_CAUSE_HWBP 2 +#define DCSR_CAUSE_DEBUGINT 3 +#define DCSR_CAUSE_STEP 4 +#define DCSR_CAUSE_HALT 5 + +#define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4)) +#define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5)) +#define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11)) + +#define MCONTROL_SELECT (1<<19) +#define MCONTROL_TIMING (1<<18) +#define MCONTROL_ACTION (0x3f<<12) +#define MCONTROL_CHAIN (1<<11) +#define MCONTROL_MATCH (0xf<<7) +#define MCONTROL_M (1<<6) +#define MCONTROL_H (1<<5) +#define MCONTROL_S (1<<4) +#define MCONTROL_U (1<<3) +#define MCONTROL_EXECUTE (1<<2) +#define MCONTROL_STORE (1<<1) +#define MCONTROL_LOAD (1<<0) + +#define MCONTROL_TYPE_NONE 0 +#define MCONTROL_TYPE_MATCH 2 + +#define MCONTROL_ACTION_DEBUG_EXCEPTION 0 +#define MCONTROL_ACTION_DEBUG_MODE 1 +#define MCONTROL_ACTION_TRACE_START 2 +#define MCONTROL_ACTION_TRACE_STOP 3 +#define MCONTROL_ACTION_TRACE_EMIT 4 + +#define MCONTROL_MATCH_EQUAL 0 +#define MCONTROL_MATCH_NAPOT 1 +#define MCONTROL_MATCH_GE 2 +#define MCONTROL_MATCH_LT 3 +#define MCONTROL_MATCH_MASK_LOW 4 +#define MCONTROL_MATCH_MASK_HIGH 5 + +#define MIP_USIP (1 << IRQ_U_SOFT) +#define MIP_SSIP (1 << IRQ_S_SOFT) +#define MIP_HSIP (1 << IRQ_H_SOFT) +#define MIP_MSIP (1 << IRQ_M_SOFT) +#define MIP_UTIP (1 << IRQ_U_TIMER) +#define MIP_STIP (1 << IRQ_S_TIMER) +#define MIP_HTIP (1 << IRQ_H_TIMER) +#define MIP_MTIP (1 << IRQ_M_TIMER) +#define MIP_UEIP (1 << IRQ_U_EXT) +#define MIP_SEIP (1 << IRQ_S_EXT) +#define MIP_HEIP (1 << IRQ_H_EXT) +#define MIP_MEIP (1 << IRQ_M_EXT) + +#define SIP_SSIP MIP_SSIP +#define SIP_STIP MIP_STIP + +#define PRV_U 0 +#define PRV_S 1 +#define PRV_H 2 +#define PRV_M 3 + +#define SATP32_MODE 0x80000000 +#define SATP32_ASID 0x7FC00000 +#define SATP32_PPN 0x003FFFFF +#define SATP64_MODE 0xF000000000000000 +#define SATP64_ASID 0x0FFFF00000000000 +#define SATP64_PPN 0x00000FFFFFFFFFFF + +#define SATP_MODE_OFF 0 +#define SATP_MODE_SV32 1 +#define SATP_MODE_SV39 8 +#define SATP_MODE_SV48 9 +#define SATP_MODE_SV57 10 +#define SATP_MODE_SV64 11 + +#define PMP_R 0x01 +#define PMP_W 0x02 +#define PMP_X 0x04 +#define PMP_A 0x18 +#define PMP_L 0x80 +#define PMP_SHIFT 2 + +#define PMP_TOR 0x08 +#define PMP_NA4 0x10 +#define PMP_NAPOT 0x18 + +#define IRQ_U_SOFT 0 +#define IRQ_S_SOFT 1 +#define IRQ_H_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_U_TIMER 4 +#define IRQ_S_TIMER 5 +#define IRQ_H_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_U_EXT 8 +#define IRQ_S_EXT 9 +#define IRQ_H_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_COP 12 +#define IRQ_HOST 13 + +#define DEFAULT_RSTVEC 0x00001000 +#define CLINT_BASE 0x02000000 +#define CLINT_SIZE 0x000c0000 +#define EXT_IO_BASE 0x40000000 +#define DRAM_BASE 0x80000000 + +/* page table entry (PTE) fields */ +#define PTE_V 0x001 /* Valid */ +#define PTE_R 0x002 /* Read */ +#define PTE_W 0x004 /* Write */ +#define PTE_X 0x008 /* Execute */ +#define PTE_U 0x010 /* User */ +#define PTE_G 0x020 /* Global */ +#define PTE_A 0x040 /* Accessed */ +#define PTE_D 0x080 /* Dirty */ +#define PTE_SOFT 0x300 /* Reserved for Software */ + +#define PTE_PPN_SHIFT 10 + +#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V) + +#ifdef __riscv + +#if __riscv_xlen == 64 +# define MSTATUS_SD MSTATUS64_SD +# define SSTATUS_SD SSTATUS64_SD +# define RISCV_PGLEVEL_BITS 9 +# define SATP_MODE SATP64_MODE +#else +# define MSTATUS_SD MSTATUS32_SD +# define SSTATUS_SD SSTATUS32_SD +# define RISCV_PGLEVEL_BITS 10 +# define SATP_MODE SATP32_MODE +#endif +#define RISCV_PGSHIFT 12 +#define RISCV_PGSIZE (1 << RISCV_PGSHIFT) + +#ifndef __ASSEMBLER__ + +#ifdef __GNUC__ + +#define read_csr(reg) ({ unsigned long __tmp; \ + asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ + __tmp; }) + +#define write_csr(reg, val) ({ \ + asm volatile ("csrw " #reg ", %0" :: "rK"(val)); }) + +#define swap_csr(reg, val) ({ unsigned long __tmp; \ + asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "rK"(val)); \ + __tmp; }) + +#define set_csr(reg, bit) ({ unsigned long __tmp; \ + asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ + __tmp; }) + +#define clear_csr(reg, bit) ({ unsigned long __tmp; \ + asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ + __tmp; }) + +#define rdtime() read_csr(time) +#define rdcycle() read_csr(cycle) +#define rdinstret() read_csr(instret) + +#endif + +#endif + +#endif + +#endif +/* Automatically generated by parse_opcodes. */ +#ifndef RISCV_ENCODING_H +#define RISCV_ENCODING_H +#define MATCH_SLLI_RV32 0x1013 +#define MASK_SLLI_RV32 0xfe00707f +#define MATCH_SRLI_RV32 0x5013 +#define MASK_SRLI_RV32 0xfe00707f +#define MATCH_SRAI_RV32 0x40005013 +#define MASK_SRAI_RV32 0xfe00707f +#define MATCH_FRFLAGS 0x102073 +#define MASK_FRFLAGS 0xfffff07f +#define MATCH_FSFLAGS 0x101073 +#define MASK_FSFLAGS 0xfff0707f +#define MATCH_FSFLAGSI 0x105073 +#define MASK_FSFLAGSI 0xfff0707f +#define MATCH_FRRM 0x202073 +#define MASK_FRRM 0xfffff07f +#define MATCH_FSRM 0x201073 +#define MASK_FSRM 0xfff0707f +#define MATCH_FSRMI 0x205073 +#define MASK_FSRMI 0xfff0707f +#define MATCH_FSCSR 0x301073 +#define MASK_FSCSR 0xfff0707f +#define MATCH_FRCSR 0x302073 +#define MASK_FRCSR 0xfffff07f +#define MATCH_RDCYCLE 0xc0002073 +#define MASK_RDCYCLE 0xfffff07f +#define MATCH_RDTIME 0xc0102073 +#define MASK_RDTIME 0xfffff07f +#define MATCH_RDINSTRET 0xc0202073 +#define MASK_RDINSTRET 0xfffff07f +#define MATCH_RDCYCLEH 0xc8002073 +#define MASK_RDCYCLEH 0xfffff07f +#define MATCH_RDTIMEH 0xc8102073 +#define MASK_RDTIMEH 0xfffff07f +#define MATCH_RDINSTRETH 0xc8202073 +#define MASK_RDINSTRETH 0xfffff07f +#define MATCH_SCALL 0x73 +#define MASK_SCALL 0xffffffff +#define MATCH_SBREAK 0x100073 +#define MASK_SBREAK 0xffffffff +#define MATCH_FMV_X_S 0xe0000053 +#define MASK_FMV_X_S 0xfff0707f +#define MATCH_FMV_S_X 0xf0000053 +#define MASK_FMV_S_X 0xfff0707f +#define MATCH_FENCE_TSO 0x8330000f +#define MASK_FENCE_TSO 0xfff0707f +#define MATCH_PAUSE 0x100000f +#define MASK_PAUSE 0xffffffff +#define MATCH_BEQ 0x63 +#define MASK_BEQ 0x707f +#define MATCH_BNE 0x1063 +#define MASK_BNE 0x707f +#define MATCH_BLT 0x4063 +#define MASK_BLT 0x707f +#define MATCH_BGE 0x5063 +#define MASK_BGE 0x707f +#define MATCH_BLTU 0x6063 +#define MASK_BLTU 0x707f +#define MATCH_BGEU 0x7063 +#define MASK_BGEU 0x707f +#define MATCH_JALR 0x67 +#define MASK_JALR 0x707f +#define MATCH_JAL 0x6f +#define MASK_JAL 0x7f +#define MATCH_LUI 0x37 +#define MASK_LUI 0x7f +#define MATCH_AUIPC 0x17 +#define MASK_AUIPC 0x7f +#define MATCH_ADDI 0x13 +#define MASK_ADDI 0x707f +#define MATCH_SLLI 0x1013 +#define MASK_SLLI 0xfc00707f +#define MATCH_SLTI 0x2013 +#define MASK_SLTI 0x707f +#define MATCH_SLTIU 0x3013 +#define MASK_SLTIU 0x707f +#define MATCH_XORI 0x4013 +#define MASK_XORI 0x707f +#define MATCH_SRLI 0x5013 +#define MASK_SRLI 0xfc00707f +#define MATCH_SRAI 0x40005013 +#define MASK_SRAI 0xfc00707f +#define MATCH_ORI 0x6013 +#define MASK_ORI 0x707f +#define MATCH_ANDI 0x7013 +#define MASK_ANDI 0x707f +#define MATCH_ADD 0x33 +#define MASK_ADD 0xfe00707f +#define MATCH_SUB 0x40000033 +#define MASK_SUB 0xfe00707f +#define MATCH_SLL 0x1033 +#define MASK_SLL 0xfe00707f +#define MATCH_SLT 0x2033 +#define MASK_SLT 0xfe00707f +#define MATCH_SLTU 0x3033 +#define MASK_SLTU 0xfe00707f +#define MATCH_XOR 0x4033 +#define MASK_XOR 0xfe00707f +#define MATCH_SRL 0x5033 +#define MASK_SRL 0xfe00707f +#define MATCH_SRA 0x40005033 +#define MASK_SRA 0xfe00707f +#define MATCH_OR 0x6033 +#define MASK_OR 0xfe00707f +#define MATCH_AND 0x7033 +#define MASK_AND 0xfe00707f +#define MATCH_LB 0x3 +#define MASK_LB 0x707f +#define MATCH_LH 0x1003 +#define MASK_LH 0x707f +#define MATCH_LW 0x2003 +#define MASK_LW 0x707f +#define MATCH_LBU 0x4003 +#define MASK_LBU 0x707f +#define MATCH_LHU 0x5003 +#define MASK_LHU 0x707f +#define MATCH_SB 0x23 +#define MASK_SB 0x707f +#define MATCH_SH 0x1023 +#define MASK_SH 0x707f +#define MATCH_SW 0x2023 +#define MASK_SW 0x707f +#define MATCH_FENCE 0xf +#define MASK_FENCE 0x707f +#define MATCH_FENCE_I 0x100f +#define MASK_FENCE_I 0x707f +#define MATCH_ADDIW 0x1b +#define MASK_ADDIW 0x707f +#define MATCH_SLLIW 0x101b +#define MASK_SLLIW 0xfe00707f +#define MATCH_SRLIW 0x501b +#define MASK_SRLIW 0xfe00707f +#define MATCH_SRAIW 0x4000501b +#define MASK_SRAIW 0xfe00707f +#define MATCH_ADDW 0x3b +#define MASK_ADDW 0xfe00707f +#define MATCH_SUBW 0x4000003b +#define MASK_SUBW 0xfe00707f +#define MATCH_SLLW 0x103b +#define MASK_SLLW 0xfe00707f +#define MATCH_SRLW 0x503b +#define MASK_SRLW 0xfe00707f +#define MATCH_SRAW 0x4000503b +#define MASK_SRAW 0xfe00707f +#define MATCH_LD 0x3003 +#define MASK_LD 0x707f +#define MATCH_LWU 0x6003 +#define MASK_LWU 0x707f +#define MATCH_SD 0x3023 +#define MASK_SD 0x707f +#define MATCH_MUL 0x2000033 +#define MASK_MUL 0xfe00707f +#define MATCH_MULH 0x2001033 +#define MASK_MULH 0xfe00707f +#define MATCH_MULHSU 0x2002033 +#define MASK_MULHSU 0xfe00707f +#define MATCH_MULHU 0x2003033 +#define MASK_MULHU 0xfe00707f +#define MATCH_DIV 0x2004033 +#define MASK_DIV 0xfe00707f +#define MATCH_DIVU 0x2005033 +#define MASK_DIVU 0xfe00707f +#define MATCH_REM 0x2006033 +#define MASK_REM 0xfe00707f +#define MATCH_REMU 0x2007033 +#define MASK_REMU 0xfe00707f +#define MATCH_MULW 0x200003b +#define MASK_MULW 0xfe00707f +#define MATCH_DIVW 0x200403b +#define MASK_DIVW 0xfe00707f +#define MATCH_DIVUW 0x200503b +#define MASK_DIVUW 0xfe00707f +#define MATCH_REMW 0x200603b +#define MASK_REMW 0xfe00707f +#define MATCH_REMUW 0x200703b +#define MASK_REMUW 0xfe00707f +#define MATCH_AMOADD_W 0x202f +#define MASK_AMOADD_W 0xf800707f +#define MATCH_AMOXOR_W 0x2000202f +#define MASK_AMOXOR_W 0xf800707f +#define MATCH_AMOOR_W 0x4000202f +#define MASK_AMOOR_W 0xf800707f +#define MATCH_AMOAND_W 0x6000202f +#define MASK_AMOAND_W 0xf800707f +#define MATCH_AMOMIN_W 0x8000202f +#define MASK_AMOMIN_W 0xf800707f +#define MATCH_AMOMAX_W 0xa000202f +#define MASK_AMOMAX_W 0xf800707f +#define MATCH_AMOMINU_W 0xc000202f +#define MASK_AMOMINU_W 0xf800707f +#define MATCH_AMOMAXU_W 0xe000202f +#define MASK_AMOMAXU_W 0xf800707f +#define MATCH_AMOSWAP_W 0x800202f +#define MASK_AMOSWAP_W 0xf800707f +#define MATCH_LR_W 0x1000202f +#define MASK_LR_W 0xf9f0707f +#define MATCH_SC_W 0x1800202f +#define MASK_SC_W 0xf800707f +#define MATCH_AMOADD_D 0x302f +#define MASK_AMOADD_D 0xf800707f +#define MATCH_AMOXOR_D 0x2000302f +#define MASK_AMOXOR_D 0xf800707f +#define MATCH_AMOOR_D 0x4000302f +#define MASK_AMOOR_D 0xf800707f +#define MATCH_AMOAND_D 0x6000302f +#define MASK_AMOAND_D 0xf800707f +#define MATCH_AMOMIN_D 0x8000302f +#define MASK_AMOMIN_D 0xf800707f +#define MATCH_AMOMAX_D 0xa000302f +#define MASK_AMOMAX_D 0xf800707f +#define MATCH_AMOMINU_D 0xc000302f +#define MASK_AMOMINU_D 0xf800707f +#define MATCH_AMOMAXU_D 0xe000302f +#define MASK_AMOMAXU_D 0xf800707f +#define MATCH_AMOSWAP_D 0x800302f +#define MASK_AMOSWAP_D 0xf800707f +#define MATCH_LR_D 0x1000302f +#define MASK_LR_D 0xf9f0707f +#define MATCH_SC_D 0x1800302f +#define MASK_SC_D 0xf800707f +#define MATCH_FADD_S 0x53 +#define MASK_FADD_S 0xfe00007f +#define MATCH_FSUB_S 0x8000053 +#define MASK_FSUB_S 0xfe00007f +#define MATCH_FMUL_S 0x10000053 +#define MASK_FMUL_S 0xfe00007f +#define MATCH_FDIV_S 0x18000053 +#define MASK_FDIV_S 0xfe00007f +#define MATCH_FSGNJ_S 0x20000053 +#define MASK_FSGNJ_S 0xfe00707f +#define MATCH_FSGNJN_S 0x20001053 +#define MASK_FSGNJN_S 0xfe00707f +#define MATCH_FSGNJX_S 0x20002053 +#define MASK_FSGNJX_S 0xfe00707f +#define MATCH_FMIN_S 0x28000053 +#define MASK_FMIN_S 0xfe00707f +#define MATCH_FMAX_S 0x28001053 +#define MASK_FMAX_S 0xfe00707f +#define MATCH_FSQRT_S 0x58000053 +#define MASK_FSQRT_S 0xfff0007f +#define MATCH_FLE_S 0xa0000053 +#define MASK_FLE_S 0xfe00707f +#define MATCH_FLT_S 0xa0001053 +#define MASK_FLT_S 0xfe00707f +#define MATCH_FEQ_S 0xa0002053 +#define MASK_FEQ_S 0xfe00707f +#define MATCH_FCVT_W_S 0xc0000053 +#define MASK_FCVT_W_S 0xfff0007f +#define MATCH_FCVT_WU_S 0xc0100053 +#define MASK_FCVT_WU_S 0xfff0007f +#define MATCH_FMV_X_W 0xe0000053 +#define MASK_FMV_X_W 0xfff0707f +#define MATCH_FCLASS_S 0xe0001053 +#define MASK_FCLASS_S 0xfff0707f +#define MATCH_FCVT_S_W 0xd0000053 +#define MASK_FCVT_S_W 0xfff0007f +#define MATCH_FCVT_S_WU 0xd0100053 +#define MASK_FCVT_S_WU 0xfff0007f +#define MATCH_FMV_W_X 0xf0000053 +#define MASK_FMV_W_X 0xfff0707f +#define MATCH_FLW 0x2007 +#define MASK_FLW 0x707f +#define MATCH_FSW 0x2027 +#define MASK_FSW 0x707f +#define MATCH_FMADD_S 0x43 +#define MASK_FMADD_S 0x600007f +#define MATCH_FMSUB_S 0x47 +#define MASK_FMSUB_S 0x600007f +#define MATCH_FNMSUB_S 0x4b +#define MASK_FNMSUB_S 0x600007f +#define MATCH_FNMADD_S 0x4f +#define MASK_FNMADD_S 0x600007f +#define MATCH_FCVT_L_S 0xc0200053 +#define MASK_FCVT_L_S 0xfff0007f +#define MATCH_FCVT_LU_S 0xc0300053 +#define MASK_FCVT_LU_S 0xfff0007f +#define MATCH_FCVT_S_L 0xd0200053 +#define MASK_FCVT_S_L 0xfff0007f +#define MATCH_FCVT_S_LU 0xd0300053 +#define MASK_FCVT_S_LU 0xfff0007f +#define MATCH_FADD_D 0x2000053 +#define MASK_FADD_D 0xfe00007f +#define MATCH_FSUB_D 0xa000053 +#define MASK_FSUB_D 0xfe00007f +#define MATCH_FMUL_D 0x12000053 +#define MASK_FMUL_D 0xfe00007f +#define MATCH_FDIV_D 0x1a000053 +#define MASK_FDIV_D 0xfe00007f +#define MATCH_FSGNJ_D 0x22000053 +#define MASK_FSGNJ_D 0xfe00707f +#define MATCH_FSGNJN_D 0x22001053 +#define MASK_FSGNJN_D 0xfe00707f +#define MATCH_FSGNJX_D 0x22002053 +#define MASK_FSGNJX_D 0xfe00707f +#define MATCH_FMIN_D 0x2a000053 +#define MASK_FMIN_D 0xfe00707f +#define MATCH_FMAX_D 0x2a001053 +#define MASK_FMAX_D 0xfe00707f +#define MATCH_FCVT_S_D 0x40100053 +#define MASK_FCVT_S_D 0xfff0007f +#define MATCH_FCVT_D_S 0x42000053 +#define MASK_FCVT_D_S 0xfff0007f +#define MATCH_FSQRT_D 0x5a000053 +#define MASK_FSQRT_D 0xfff0007f +#define MATCH_FLE_D 0xa2000053 +#define MASK_FLE_D 0xfe00707f +#define MATCH_FLT_D 0xa2001053 +#define MASK_FLT_D 0xfe00707f +#define MATCH_FEQ_D 0xa2002053 +#define MASK_FEQ_D 0xfe00707f +#define MATCH_FCVT_W_D 0xc2000053 +#define MASK_FCVT_W_D 0xfff0007f +#define MATCH_FCVT_WU_D 0xc2100053 +#define MASK_FCVT_WU_D 0xfff0007f +#define MATCH_FCLASS_D 0xe2001053 +#define MASK_FCLASS_D 0xfff0707f +#define MATCH_FCVT_D_W 0xd2000053 +#define MASK_FCVT_D_W 0xfff0007f +#define MATCH_FCVT_D_WU 0xd2100053 +#define MASK_FCVT_D_WU 0xfff0007f +#define MATCH_FLD 0x3007 +#define MASK_FLD 0x707f +#define MATCH_FSD 0x3027 +#define MASK_FSD 0x707f +#define MATCH_FMADD_D 0x2000043 +#define MASK_FMADD_D 0x600007f +#define MATCH_FMSUB_D 0x2000047 +#define MASK_FMSUB_D 0x600007f +#define MATCH_FNMSUB_D 0x200004b +#define MASK_FNMSUB_D 0x600007f +#define MATCH_FNMADD_D 0x200004f +#define MASK_FNMADD_D 0x600007f +#define MATCH_FCVT_L_D 0xc2200053 +#define MASK_FCVT_L_D 0xfff0007f +#define MATCH_FCVT_LU_D 0xc2300053 +#define MASK_FCVT_LU_D 0xfff0007f +#define MATCH_FMV_X_D 0xe2000053 +#define MASK_FMV_X_D 0xfff0707f +#define MATCH_FCVT_D_L 0xd2200053 +#define MASK_FCVT_D_L 0xfff0007f +#define MATCH_FCVT_D_LU 0xd2300053 +#define MASK_FCVT_D_LU 0xfff0007f +#define MATCH_FMV_D_X 0xf2000053 +#define MASK_FMV_D_X 0xfff0707f +#define MATCH_FADD_Q 0x6000053 +#define MASK_FADD_Q 0xfe00007f +#define MATCH_FSUB_Q 0xe000053 +#define MASK_FSUB_Q 0xfe00007f +#define MATCH_FMUL_Q 0x16000053 +#define MASK_FMUL_Q 0xfe00007f +#define MATCH_FDIV_Q 0x1e000053 +#define MASK_FDIV_Q 0xfe00007f +#define MATCH_FSGNJ_Q 0x26000053 +#define MASK_FSGNJ_Q 0xfe00707f +#define MATCH_FSGNJN_Q 0x26001053 +#define MASK_FSGNJN_Q 0xfe00707f +#define MATCH_FSGNJX_Q 0x26002053 +#define MASK_FSGNJX_Q 0xfe00707f +#define MATCH_FMIN_Q 0x2e000053 +#define MASK_FMIN_Q 0xfe00707f +#define MATCH_FMAX_Q 0x2e001053 +#define MASK_FMAX_Q 0xfe00707f +#define MATCH_FCVT_S_Q 0x40300053 +#define MASK_FCVT_S_Q 0xfff0007f +#define MATCH_FCVT_Q_S 0x46000053 +#define MASK_FCVT_Q_S 0xfff0007f +#define MATCH_FCVT_D_Q 0x42300053 +#define MASK_FCVT_D_Q 0xfff0007f +#define MATCH_FCVT_Q_D 0x46100053 +#define MASK_FCVT_Q_D 0xfff0007f +#define MATCH_FSQRT_Q 0x5e000053 +#define MASK_FSQRT_Q 0xfff0007f +#define MATCH_FLE_Q 0xa6000053 +#define MASK_FLE_Q 0xfe00707f +#define MATCH_FLT_Q 0xa6001053 +#define MASK_FLT_Q 0xfe00707f +#define MATCH_FEQ_Q 0xa6002053 +#define MASK_FEQ_Q 0xfe00707f +#define MATCH_FCVT_W_Q 0xc6000053 +#define MASK_FCVT_W_Q 0xfff0007f +#define MATCH_FCVT_WU_Q 0xc6100053 +#define MASK_FCVT_WU_Q 0xfff0007f +#define MATCH_FCLASS_Q 0xe6001053 +#define MASK_FCLASS_Q 0xfff0707f +#define MATCH_FCVT_Q_W 0xd6000053 +#define MASK_FCVT_Q_W 0xfff0007f +#define MATCH_FCVT_Q_WU 0xd6100053 +#define MASK_FCVT_Q_WU 0xfff0007f +#define MATCH_FLQ 0x4007 +#define MASK_FLQ 0x707f +#define MATCH_FSQ 0x4027 +#define MASK_FSQ 0x707f +#define MATCH_FMADD_Q 0x6000043 +#define MASK_FMADD_Q 0x600007f +#define MATCH_FMSUB_Q 0x6000047 +#define MASK_FMSUB_Q 0x600007f +#define MATCH_FNMSUB_Q 0x600004b +#define MASK_FNMSUB_Q 0x600007f +#define MATCH_FNMADD_Q 0x600004f +#define MASK_FNMADD_Q 0x600007f +#define MATCH_FCVT_L_Q 0xc6200053 +#define MASK_FCVT_L_Q 0xfff0007f +#define MATCH_FCVT_LU_Q 0xc6300053 +#define MASK_FCVT_LU_Q 0xfff0007f +#define MATCH_FCVT_Q_L 0xd6200053 +#define MASK_FCVT_Q_L 0xfff0007f +#define MATCH_FCVT_Q_LU 0xd6300053 +#define MASK_FCVT_Q_LU 0xfff0007f +#define MATCH_FMV_X_Q 0xe6000053 +#define MASK_FMV_X_Q 0xfff0707f +#define MATCH_FMV_Q_X 0xf6000053 +#define MASK_FMV_Q_X 0xfff0707f +#define MATCH_ECALL 0x73 +#define MASK_ECALL 0xffffffff +#define MATCH_EBREAK 0x100073 +#define MASK_EBREAK 0xffffffff +#define MATCH_URET 0x200073 +#define MASK_URET 0xffffffff +#define MATCH_SRET 0x10200073 +#define MASK_SRET 0xffffffff +#define MATCH_MRET 0x30200073 +#define MASK_MRET 0xffffffff +#define MATCH_DRET 0x7b200073 +#define MASK_DRET 0xffffffff +#define MATCH_SFENCE_VMA 0x12000073 +#define MASK_SFENCE_VMA 0xfe007fff +#define MATCH_WFI 0x10500073 +#define MASK_WFI 0xffffffff +#define MATCH_CSRRW 0x1073 +#define MASK_CSRRW 0x707f +#define MATCH_CSRRS 0x2073 +#define MASK_CSRRS 0x707f +#define MATCH_CSRRC 0x3073 +#define MASK_CSRRC 0x707f +#define MATCH_CSRRWI 0x5073 +#define MASK_CSRRWI 0x707f +#define MATCH_CSRRSI 0x6073 +#define MASK_CSRRSI 0x707f +#define MATCH_CSRRCI 0x7073 +#define MASK_CSRRCI 0x707f +#define MATCH_HFENCE_VVMA 0x22000073 +#define MASK_HFENCE_VVMA 0xfe007fff +#define MATCH_HFENCE_GVMA 0x62000073 +#define MASK_HFENCE_GVMA 0xfe007fff +#define MATCH_C_NOP 0x1 +#define MASK_C_NOP 0xffff +#define MATCH_C_ADDI16SP 0x6101 +#define MASK_C_ADDI16SP 0xef83 +#define MATCH_C_JR 0x8002 +#define MASK_C_JR 0xf07f +#define MATCH_C_JALR 0x9002 +#define MASK_C_JALR 0xf07f +#define MATCH_C_EBREAK 0x9002 +#define MASK_C_EBREAK 0xffff +#define MATCH_C_ADDI4SPN 0x0 +#define MASK_C_ADDI4SPN 0xe003 +#define MATCH_C_FLD 0x2000 +#define MASK_C_FLD 0xe003 +#define MATCH_C_LW 0x4000 +#define MASK_C_LW 0xe003 +#define MATCH_C_FLW 0x6000 +#define MASK_C_FLW 0xe003 +#define MATCH_C_FSD 0xa000 +#define MASK_C_FSD 0xe003 +#define MATCH_C_SW 0xc000 +#define MASK_C_SW 0xe003 +#define MATCH_C_FSW 0xe000 +#define MASK_C_FSW 0xe003 +#define MATCH_C_ADDI 0x1 +#define MASK_C_ADDI 0xe003 +#define MATCH_C_JAL 0x2001 +#define MASK_C_JAL 0xe003 +#define MATCH_C_LI 0x4001 +#define MASK_C_LI 0xe003 +#define MATCH_C_LUI 0x6001 +#define MASK_C_LUI 0xe003 +#define MATCH_C_SRLI 0x8001 +#define MASK_C_SRLI 0xec03 +#define MATCH_C_SRAI 0x8401 +#define MASK_C_SRAI 0xec03 +#define MATCH_C_ANDI 0x8801 +#define MASK_C_ANDI 0xec03 +#define MATCH_C_SUB 0x8c01 +#define MASK_C_SUB 0xfc63 +#define MATCH_C_XOR 0x8c21 +#define MASK_C_XOR 0xfc63 +#define MATCH_C_OR 0x8c41 +#define MASK_C_OR 0xfc63 +#define MATCH_C_AND 0x8c61 +#define MASK_C_AND 0xfc63 +#define MATCH_C_J 0xa001 +#define MASK_C_J 0xe003 +#define MATCH_C_BEQZ 0xc001 +#define MASK_C_BEQZ 0xe003 +#define MATCH_C_BNEZ 0xe001 +#define MASK_C_BNEZ 0xe003 +#define MATCH_C_SLLI 0x2 +#define MASK_C_SLLI 0xe003 +#define MATCH_C_FLDSP 0x2002 +#define MASK_C_FLDSP 0xe003 +#define MATCH_C_LWSP 0x4002 +#define MASK_C_LWSP 0xe003 +#define MATCH_C_FLWSP 0x6002 +#define MASK_C_FLWSP 0xe003 +#define MATCH_C_MV 0x8002 +#define MASK_C_MV 0xf003 +#define MATCH_C_ADD 0x9002 +#define MASK_C_ADD 0xf003 +#define MATCH_C_FSDSP 0xa002 +#define MASK_C_FSDSP 0xe003 +#define MATCH_C_SWSP 0xc002 +#define MASK_C_SWSP 0xe003 +#define MATCH_C_FSWSP 0xe002 +#define MASK_C_FSWSP 0xe003 +#define MATCH_C_SRLI_RV32 0x8001 +#define MASK_C_SRLI_RV32 0xfc03 +#define MATCH_C_SRAI_RV32 0x8401 +#define MASK_C_SRAI_RV32 0xfc03 +#define MATCH_C_SLLI_RV32 0x2 +#define MASK_C_SLLI_RV32 0xf003 +#define MATCH_C_LD 0x6000 +#define MASK_C_LD 0xe003 +#define MATCH_C_SD 0xe000 +#define MASK_C_SD 0xe003 +#define MATCH_C_SUBW 0x9c01 +#define MASK_C_SUBW 0xfc63 +#define MATCH_C_ADDW 0x9c21 +#define MASK_C_ADDW 0xfc63 +#define MATCH_C_ADDIW 0x2001 +#define MASK_C_ADDIW 0xe003 +#define MATCH_C_LDSP 0x6002 +#define MASK_C_LDSP 0xe003 +#define MATCH_C_SDSP 0xe002 +#define MASK_C_SDSP 0xe003 +#define MATCH_C_LQ 0x2000 +#define MASK_C_LQ 0xe003 +#define MATCH_C_SQ 0xa000 +#define MASK_C_SQ 0xe003 +#define MATCH_C_LQSP 0x2002 +#define MASK_C_LQSP 0xe003 +#define MATCH_C_SQSP 0xa002 +#define MASK_C_SQSP 0xe003 +#define MATCH_CUSTOM0 0xb +#define MASK_CUSTOM0 0x707f +#define MATCH_CUSTOM0_RS1 0x200b +#define MASK_CUSTOM0_RS1 0x707f +#define MATCH_CUSTOM0_RS1_RS2 0x300b +#define MASK_CUSTOM0_RS1_RS2 0x707f +#define MATCH_CUSTOM0_RD 0x400b +#define MASK_CUSTOM0_RD 0x707f +#define MATCH_CUSTOM0_RD_RS1 0x600b +#define MASK_CUSTOM0_RD_RS1 0x707f +#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b +#define MASK_CUSTOM0_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM1 0x2b +#define MASK_CUSTOM1 0x707f +#define MATCH_CUSTOM1_RS1 0x202b +#define MASK_CUSTOM1_RS1 0x707f +#define MATCH_CUSTOM1_RS1_RS2 0x302b +#define MASK_CUSTOM1_RS1_RS2 0x707f +#define MATCH_CUSTOM1_RD 0x402b +#define MASK_CUSTOM1_RD 0x707f +#define MATCH_CUSTOM1_RD_RS1 0x602b +#define MASK_CUSTOM1_RD_RS1 0x707f +#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b +#define MASK_CUSTOM1_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM2 0x5b +#define MASK_CUSTOM2 0x707f +#define MATCH_CUSTOM2_RS1 0x205b +#define MASK_CUSTOM2_RS1 0x707f +#define MATCH_CUSTOM2_RS1_RS2 0x305b +#define MASK_CUSTOM2_RS1_RS2 0x707f +#define MATCH_CUSTOM2_RD 0x405b +#define MASK_CUSTOM2_RD 0x707f +#define MATCH_CUSTOM2_RD_RS1 0x605b +#define MASK_CUSTOM2_RD_RS1 0x707f +#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b +#define MASK_CUSTOM2_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM3 0x7b +#define MASK_CUSTOM3 0x707f +#define MATCH_CUSTOM3_RS1 0x207b +#define MASK_CUSTOM3_RS1 0x707f +#define MATCH_CUSTOM3_RS1_RS2 0x307b +#define MASK_CUSTOM3_RS1_RS2 0x707f +#define MATCH_CUSTOM3_RD 0x407b +#define MASK_CUSTOM3_RD 0x707f +#define MATCH_CUSTOM3_RD_RS1 0x607b +#define MASK_CUSTOM3_RD_RS1 0x707f +#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b +#define MASK_CUSTOM3_RD_RS1_RS2 0x707f +#define MATCH_VSETVLI 0x7057 +#define MASK_VSETVLI 0x8000707f +#define MATCH_VSETVL 0x80007057 +#define MASK_VSETVL 0xfe00707f +#define MATCH_VLB_V 0x10000007 +#define MASK_VLB_V 0x1df0707f +#define MATCH_VLH_V 0x10005007 +#define MASK_VLH_V 0x1df0707f +#define MATCH_VLW_V 0x10006007 +#define MASK_VLW_V 0x1df0707f +#define MATCH_VLE_V 0x7007 +#define MASK_VLE_V 0x1df0707f +#define MATCH_VLBU_V 0x7 +#define MASK_VLBU_V 0x1df0707f +#define MATCH_VLHU_V 0x5007 +#define MASK_VLHU_V 0x1df0707f +#define MATCH_VLWU_V 0x6007 +#define MASK_VLWU_V 0x1df0707f +#define MATCH_VSB_V 0x27 +#define MASK_VSB_V 0x1df0707f +#define MATCH_VSH_V 0x5027 +#define MASK_VSH_V 0x1df0707f +#define MATCH_VSW_V 0x6027 +#define MASK_VSW_V 0x1df0707f +#define MATCH_VSE_V 0x7027 +#define MASK_VSE_V 0x1df0707f +#define MATCH_VLSB_V 0x18000007 +#define MASK_VLSB_V 0x1c00707f +#define MATCH_VLSH_V 0x18005007 +#define MASK_VLSH_V 0x1c00707f +#define MATCH_VLSW_V 0x18006007 +#define MASK_VLSW_V 0x1c00707f +#define MATCH_VLSE_V 0x8007007 +#define MASK_VLSE_V 0x1c00707f +#define MATCH_VLSBU_V 0x8000007 +#define MASK_VLSBU_V 0x1c00707f +#define MATCH_VLSHU_V 0x8005007 +#define MASK_VLSHU_V 0x1c00707f +#define MATCH_VLSWU_V 0x8006007 +#define MASK_VLSWU_V 0x1c00707f +#define MATCH_VSSB_V 0x8000027 +#define MASK_VSSB_V 0x1c00707f +#define MATCH_VSSH_V 0x8005027 +#define MASK_VSSH_V 0x1c00707f +#define MATCH_VSSW_V 0x8006027 +#define MASK_VSSW_V 0x1c00707f +#define MATCH_VSSE_V 0x8007027 +#define MASK_VSSE_V 0x1c00707f +#define MATCH_VLXB_V 0x1c000007 +#define MASK_VLXB_V 0x1c00707f +#define MATCH_VLXH_V 0x1c005007 +#define MASK_VLXH_V 0x1c00707f +#define MATCH_VLXW_V 0x1c006007 +#define MASK_VLXW_V 0x1c00707f +#define MATCH_VLXE_V 0xc007007 +#define MASK_VLXE_V 0x1c00707f +#define MATCH_VLXBU_V 0xc000007 +#define MASK_VLXBU_V 0x1c00707f +#define MATCH_VLXHU_V 0xc005007 +#define MASK_VLXHU_V 0x1c00707f +#define MATCH_VLXWU_V 0xc006007 +#define MASK_VLXWU_V 0x1c00707f +#define MATCH_VSXB_V 0xc000027 +#define MASK_VSXB_V 0x1c00707f +#define MATCH_VSXH_V 0xc005027 +#define MASK_VSXH_V 0x1c00707f +#define MATCH_VSXW_V 0xc006027 +#define MASK_VSXW_V 0x1c00707f +#define MATCH_VSXE_V 0xc007027 +#define MASK_VSXE_V 0x1c00707f +#define MATCH_VSUXB_V 0x1c000027 +#define MASK_VSUXB_V 0xfc00707f +#define MATCH_VSUXH_V 0x1c005027 +#define MASK_VSUXH_V 0xfc00707f +#define MATCH_VSUXW_V 0x1c006027 +#define MASK_VSUXW_V 0xfc00707f +#define MATCH_VSUXE_V 0x1c007027 +#define MASK_VSUXE_V 0xfc00707f +#define MATCH_VLBFF_V 0x11000007 +#define MASK_VLBFF_V 0x1df0707f +#define MATCH_VLHFF_V 0x11005007 +#define MASK_VLHFF_V 0x1df0707f +#define MATCH_VLWFF_V 0x11006007 +#define MASK_VLWFF_V 0x1df0707f +#define MATCH_VLEFF_V 0x1007007 +#define MASK_VLEFF_V 0x1df0707f +#define MATCH_VLBUFF_V 0x1000007 +#define MASK_VLBUFF_V 0x1df0707f +#define MATCH_VLHUFF_V 0x1005007 +#define MASK_VLHUFF_V 0x1df0707f +#define MATCH_VLWUFF_V 0x1006007 +#define MASK_VLWUFF_V 0x1df0707f +#define MATCH_VL1R_V 0x2807007 +#define MASK_VL1R_V 0xfff0707f +#define MATCH_VS1R_V 0x2807027 +#define MASK_VS1R_V 0xfff0707f +#define MATCH_VFADD_VF 0x5057 +#define MASK_VFADD_VF 0xfc00707f +#define MATCH_VFSUB_VF 0x8005057 +#define MASK_VFSUB_VF 0xfc00707f +#define MATCH_VFMIN_VF 0x10005057 +#define MASK_VFMIN_VF 0xfc00707f +#define MATCH_VFMAX_VF 0x18005057 +#define MASK_VFMAX_VF 0xfc00707f +#define MATCH_VFSGNJ_VF 0x20005057 +#define MASK_VFSGNJ_VF 0xfc00707f +#define MATCH_VFSGNJN_VF 0x24005057 +#define MASK_VFSGNJN_VF 0xfc00707f +#define MATCH_VFSGNJX_VF 0x28005057 +#define MASK_VFSGNJX_VF 0xfc00707f +#define MATCH_VFSLIDE1UP_VF 0x38005057 +#define MASK_VFSLIDE1UP_VF 0xfc00707f +#define MATCH_VFSLIDE1DOWN_VF 0x3c005057 +#define MASK_VFSLIDE1DOWN_VF 0xfc00707f +#define MATCH_VFMV_S_F 0x42005057 +#define MASK_VFMV_S_F 0xfff0707f +#define MATCH_VFMERGE_VFM 0x5c005057 +#define MASK_VFMERGE_VFM 0xfe00707f +#define MATCH_VFMV_V_F 0x5e005057 +#define MASK_VFMV_V_F 0xfff0707f +#define MATCH_VMFEQ_VF 0x60005057 +#define MASK_VMFEQ_VF 0xfc00707f +#define MATCH_VMFLE_VF 0x64005057 +#define MASK_VMFLE_VF 0xfc00707f +#define MATCH_VMFLT_VF 0x6c005057 +#define MASK_VMFLT_VF 0xfc00707f +#define MATCH_VMFNE_VF 0x70005057 +#define MASK_VMFNE_VF 0xfc00707f +#define MATCH_VMFGT_VF 0x74005057 +#define MASK_VMFGT_VF 0xfc00707f +#define MATCH_VMFGE_VF 0x7c005057 +#define MASK_VMFGE_VF 0xfc00707f +#define MATCH_VFDIV_VF 0x80005057 +#define MASK_VFDIV_VF 0xfc00707f +#define MATCH_VFRDIV_VF 0x84005057 +#define MASK_VFRDIV_VF 0xfc00707f +#define MATCH_VFMUL_VF 0x90005057 +#define MASK_VFMUL_VF 0xfc00707f +#define MATCH_VFRSUB_VF 0x9c005057 +#define MASK_VFRSUB_VF 0xfc00707f +#define MATCH_VFMADD_VF 0xa0005057 +#define MASK_VFMADD_VF 0xfc00707f +#define MATCH_VFNMADD_VF 0xa4005057 +#define MASK_VFNMADD_VF 0xfc00707f +#define MATCH_VFMSUB_VF 0xa8005057 +#define MASK_VFMSUB_VF 0xfc00707f +#define MATCH_VFNMSUB_VF 0xac005057 +#define MASK_VFNMSUB_VF 0xfc00707f +#define MATCH_VFMACC_VF 0xb0005057 +#define MASK_VFMACC_VF 0xfc00707f +#define MATCH_VFNMACC_VF 0xb4005057 +#define MASK_VFNMACC_VF 0xfc00707f +#define MATCH_VFMSAC_VF 0xb8005057 +#define MASK_VFMSAC_VF 0xfc00707f +#define MATCH_VFNMSAC_VF 0xbc005057 +#define MASK_VFNMSAC_VF 0xfc00707f +#define MATCH_VFWADD_VF 0xc0005057 +#define MASK_VFWADD_VF 0xfc00707f +#define MATCH_VFWSUB_VF 0xc8005057 +#define MASK_VFWSUB_VF 0xfc00707f +#define MATCH_VFWADD_WF 0xd0005057 +#define MASK_VFWADD_WF 0xfc00707f +#define MATCH_VFWSUB_WF 0xd8005057 +#define MASK_VFWSUB_WF 0xfc00707f +#define MATCH_VFWMUL_VF 0xe0005057 +#define MASK_VFWMUL_VF 0xfc00707f +#define MATCH_VFWMACC_VF 0xf0005057 +#define MASK_VFWMACC_VF 0xfc00707f +#define MATCH_VFWNMACC_VF 0xf4005057 +#define MASK_VFWNMACC_VF 0xfc00707f +#define MATCH_VFWMSAC_VF 0xf8005057 +#define MASK_VFWMSAC_VF 0xfc00707f +#define MATCH_VFWNMSAC_VF 0xfc005057 +#define MASK_VFWNMSAC_VF 0xfc00707f +#define MATCH_VFADD_VV 0x1057 +#define MASK_VFADD_VV 0xfc00707f +#define MATCH_VFREDSUM_VS 0x4001057 +#define MASK_VFREDSUM_VS 0xfc00707f +#define MATCH_VFSUB_VV 0x8001057 +#define MASK_VFSUB_VV 0xfc00707f +#define MATCH_VFREDOSUM_VS 0xc001057 +#define MASK_VFREDOSUM_VS 0xfc00707f +#define MATCH_VFMIN_VV 0x10001057 +#define MASK_VFMIN_VV 0xfc00707f +#define MATCH_VFREDMIN_VS 0x14001057 +#define MASK_VFREDMIN_VS 0xfc00707f +#define MATCH_VFMAX_VV 0x18001057 +#define MASK_VFMAX_VV 0xfc00707f +#define MATCH_VFREDMAX_VS 0x1c001057 +#define MASK_VFREDMAX_VS 0xfc00707f +#define MATCH_VFSGNJ_VV 0x20001057 +#define MASK_VFSGNJ_VV 0xfc00707f +#define MATCH_VFSGNJN_VV 0x24001057 +#define MASK_VFSGNJN_VV 0xfc00707f +#define MATCH_VFSGNJX_VV 0x28001057 +#define MASK_VFSGNJX_VV 0xfc00707f +#define MATCH_VFMV_F_S 0x42001057 +#define MASK_VFMV_F_S 0xfe0ff07f +#define MATCH_VMFEQ_VV 0x60001057 +#define MASK_VMFEQ_VV 0xfc00707f +#define MATCH_VMFLE_VV 0x64001057 +#define MASK_VMFLE_VV 0xfc00707f +#define MATCH_VMFLT_VV 0x6c001057 +#define MASK_VMFLT_VV 0xfc00707f +#define MATCH_VMFNE_VV 0x70001057 +#define MASK_VMFNE_VV 0xfc00707f +#define MATCH_VFDIV_VV 0x80001057 +#define MASK_VFDIV_VV 0xfc00707f +#define MATCH_VFMUL_VV 0x90001057 +#define MASK_VFMUL_VV 0xfc00707f +#define MATCH_VFMADD_VV 0xa0001057 +#define MASK_VFMADD_VV 0xfc00707f +#define MATCH_VFNMADD_VV 0xa4001057 +#define MASK_VFNMADD_VV 0xfc00707f +#define MATCH_VFMSUB_VV 0xa8001057 +#define MASK_VFMSUB_VV 0xfc00707f +#define MATCH_VFNMSUB_VV 0xac001057 +#define MASK_VFNMSUB_VV 0xfc00707f +#define MATCH_VFMACC_VV 0xb0001057 +#define MASK_VFMACC_VV 0xfc00707f +#define MATCH_VFNMACC_VV 0xb4001057 +#define MASK_VFNMACC_VV 0xfc00707f +#define MATCH_VFMSAC_VV 0xb8001057 +#define MASK_VFMSAC_VV 0xfc00707f +#define MATCH_VFNMSAC_VV 0xbc001057 +#define MASK_VFNMSAC_VV 0xfc00707f +#define MATCH_VFCVT_XU_F_V 0x88001057 +#define MASK_VFCVT_XU_F_V 0xfc0ff07f +#define MATCH_VFCVT_X_F_V 0x88009057 +#define MASK_VFCVT_X_F_V 0xfc0ff07f +#define MATCH_VFCVT_F_XU_V 0x88011057 +#define MASK_VFCVT_F_XU_V 0xfc0ff07f +#define MATCH_VFCVT_F_X_V 0x88019057 +#define MASK_VFCVT_F_X_V 0xfc0ff07f +#define MATCH_VFCVT_RTZ_XU_F_V 0x88031057 +#define MASK_VFCVT_RTZ_XU_F_V 0xfc0ff07f +#define MATCH_VFCVT_RTZ_X_F_V 0x88039057 +#define MASK_VFCVT_RTZ_X_F_V 0xfc0ff07f +#define MATCH_VFWCVT_XU_F_V 0x88041057 +#define MASK_VFWCVT_XU_F_V 0xfc0ff07f +#define MATCH_VFWCVT_X_F_V 0x88049057 +#define MASK_VFWCVT_X_F_V 0xfc0ff07f +#define MATCH_VFWCVT_F_XU_V 0x88051057 +#define MASK_VFWCVT_F_XU_V 0xfc0ff07f +#define MATCH_VFWCVT_F_X_V 0x88059057 +#define MASK_VFWCVT_F_X_V 0xfc0ff07f +#define MATCH_VFWCVT_F_F_V 0x88061057 +#define MASK_VFWCVT_F_F_V 0xfc0ff07f +#define MATCH_VFWCVT_RTZ_XU_F_V 0x88071057 +#define MASK_VFWCVT_RTZ_XU_F_V 0xfc0ff07f +#define MATCH_VFWCVT_RTZ_X_F_V 0x88079057 +#define MASK_VFWCVT_RTZ_X_F_V 0xfc0ff07f +#define MATCH_VFNCVT_XU_F_W 0x88081057 +#define MASK_VFNCVT_XU_F_W 0xfc0ff07f +#define MATCH_VFNCVT_X_F_W 0x88089057 +#define MASK_VFNCVT_X_F_W 0xfc0ff07f +#define MATCH_VFNCVT_F_XU_W 0x88091057 +#define MASK_VFNCVT_F_XU_W 0xfc0ff07f +#define MATCH_VFNCVT_F_X_W 0x88099057 +#define MASK_VFNCVT_F_X_W 0xfc0ff07f +#define MATCH_VFNCVT_F_F_W 0x880a1057 +#define MASK_VFNCVT_F_F_W 0xfc0ff07f +#define MATCH_VFNCVT_ROD_F_F_W 0x880a9057 +#define MASK_VFNCVT_ROD_F_F_W 0xfc0ff07f +#define MATCH_VFNCVT_RTZ_XU_F_W 0x880b1057 +#define MASK_VFNCVT_RTZ_XU_F_W 0xfc0ff07f +#define MATCH_VFNCVT_RTZ_X_F_W 0x880b9057 +#define MASK_VFNCVT_RTZ_X_F_W 0xfc0ff07f +#define MATCH_VFSQRT_V 0x8c001057 +#define MASK_VFSQRT_V 0xfc0ff07f +#define MATCH_VFCLASS_V 0x8c081057 +#define MASK_VFCLASS_V 0xfc0ff07f +#define MATCH_VFWADD_VV 0xc0001057 +#define MASK_VFWADD_VV 0xfc00707f +#define MATCH_VFWREDSUM_VS 0xc4001057 +#define MASK_VFWREDSUM_VS 0xfc00707f +#define MATCH_VFWSUB_VV 0xc8001057 +#define MASK_VFWSUB_VV 0xfc00707f +#define MATCH_VFWREDOSUM_VS 0xcc001057 +#define MASK_VFWREDOSUM_VS 0xfc00707f +#define MATCH_VFWADD_WV 0xd0001057 +#define MASK_VFWADD_WV 0xfc00707f +#define MATCH_VFWSUB_WV 0xd8001057 +#define MASK_VFWSUB_WV 0xfc00707f +#define MATCH_VFWMUL_VV 0xe0001057 +#define MASK_VFWMUL_VV 0xfc00707f +#define MATCH_VFDOT_VV 0xe4001057 +#define MASK_VFDOT_VV 0xfc00707f +#define MATCH_VFWMACC_VV 0xf0001057 +#define MASK_VFWMACC_VV 0xfc00707f +#define MATCH_VFWNMACC_VV 0xf4001057 +#define MASK_VFWNMACC_VV 0xfc00707f +#define MATCH_VFWMSAC_VV 0xf8001057 +#define MASK_VFWMSAC_VV 0xfc00707f +#define MATCH_VFWNMSAC_VV 0xfc001057 +#define MASK_VFWNMSAC_VV 0xfc00707f +#define MATCH_VADD_VX 0x4057 +#define MASK_VADD_VX 0xfc00707f +#define MATCH_VSUB_VX 0x8004057 +#define MASK_VSUB_VX 0xfc00707f +#define MATCH_VRSUB_VX 0xc004057 +#define MASK_VRSUB_VX 0xfc00707f +#define MATCH_VMINU_VX 0x10004057 +#define MASK_VMINU_VX 0xfc00707f +#define MATCH_VMIN_VX 0x14004057 +#define MASK_VMIN_VX 0xfc00707f +#define MATCH_VMAXU_VX 0x18004057 +#define MASK_VMAXU_VX 0xfc00707f +#define MATCH_VMAX_VX 0x1c004057 +#define MASK_VMAX_VX 0xfc00707f +#define MATCH_VAND_VX 0x24004057 +#define MASK_VAND_VX 0xfc00707f +#define MATCH_VOR_VX 0x28004057 +#define MASK_VOR_VX 0xfc00707f +#define MATCH_VXOR_VX 0x2c004057 +#define MASK_VXOR_VX 0xfc00707f +#define MATCH_VRGATHER_VX 0x30004057 +#define MASK_VRGATHER_VX 0xfc00707f +#define MATCH_VSLIDEUP_VX 0x38004057 +#define MASK_VSLIDEUP_VX 0xfc00707f +#define MATCH_VSLIDEDOWN_VX 0x3c004057 +#define MASK_VSLIDEDOWN_VX 0xfc00707f +#define MATCH_VADC_VXM 0x40004057 +#define MASK_VADC_VXM 0xfe00707f +#define MATCH_VMADC_VXM 0x44004057 +#define MASK_VMADC_VXM 0xfc00707f +#define MATCH_VSBC_VXM 0x48004057 +#define MASK_VSBC_VXM 0xfe00707f +#define MATCH_VMSBC_VXM 0x4c004057 +#define MASK_VMSBC_VXM 0xfc00707f +#define MATCH_VMERGE_VXM 0x5c004057 +#define MASK_VMERGE_VXM 0xfe00707f +#define MATCH_VMV_V_X 0x5e004057 +#define MASK_VMV_V_X 0xfff0707f +#define MATCH_VMSEQ_VX 0x60004057 +#define MASK_VMSEQ_VX 0xfc00707f +#define MATCH_VMSNE_VX 0x64004057 +#define MASK_VMSNE_VX 0xfc00707f +#define MATCH_VMSLTU_VX 0x68004057 +#define MASK_VMSLTU_VX 0xfc00707f +#define MATCH_VMSLT_VX 0x6c004057 +#define MASK_VMSLT_VX 0xfc00707f +#define MATCH_VMSLEU_VX 0x70004057 +#define MASK_VMSLEU_VX 0xfc00707f +#define MATCH_VMSLE_VX 0x74004057 +#define MASK_VMSLE_VX 0xfc00707f +#define MATCH_VMSGTU_VX 0x78004057 +#define MASK_VMSGTU_VX 0xfc00707f +#define MATCH_VMSGT_VX 0x7c004057 +#define MASK_VMSGT_VX 0xfc00707f +#define MATCH_VSADDU_VX 0x80004057 +#define MASK_VSADDU_VX 0xfc00707f +#define MATCH_VSADD_VX 0x84004057 +#define MASK_VSADD_VX 0xfc00707f +#define MATCH_VSSUBU_VX 0x88004057 +#define MASK_VSSUBU_VX 0xfc00707f +#define MATCH_VSSUB_VX 0x8c004057 +#define MASK_VSSUB_VX 0xfc00707f +#define MATCH_VSLL_VX 0x94004057 +#define MASK_VSLL_VX 0xfc00707f +#define MATCH_VSMUL_VX 0x9c004057 +#define MASK_VSMUL_VX 0xfc00707f +#define MATCH_VSRL_VX 0xa0004057 +#define MASK_VSRL_VX 0xfc00707f +#define MATCH_VSRA_VX 0xa4004057 +#define MASK_VSRA_VX 0xfc00707f +#define MATCH_VSSRL_VX 0xa8004057 +#define MASK_VSSRL_VX 0xfc00707f +#define MATCH_VSSRA_VX 0xac004057 +#define MASK_VSSRA_VX 0xfc00707f +#define MATCH_VNSRL_WX 0xb0004057 +#define MASK_VNSRL_WX 0xfc00707f +#define MATCH_VNSRA_WX 0xb4004057 +#define MASK_VNSRA_WX 0xfc00707f +#define MATCH_VNCLIPU_WX 0xb8004057 +#define MASK_VNCLIPU_WX 0xfc00707f +#define MATCH_VNCLIP_WX 0xbc004057 +#define MASK_VNCLIP_WX 0xfc00707f +#define MATCH_VQMACCU_VX 0xf0004057 +#define MASK_VQMACCU_VX 0xfc00707f +#define MATCH_VQMACC_VX 0xf4004057 +#define MASK_VQMACC_VX 0xfc00707f +#define MATCH_VQMACCUS_VX 0xf8004057 +#define MASK_VQMACCUS_VX 0xfc00707f +#define MATCH_VQMACCSU_VX 0xfc004057 +#define MASK_VQMACCSU_VX 0xfc00707f +#define MATCH_VADD_VV 0x57 +#define MASK_VADD_VV 0xfc00707f +#define MATCH_VSUB_VV 0x8000057 +#define MASK_VSUB_VV 0xfc00707f +#define MATCH_VMINU_VV 0x10000057 +#define MASK_VMINU_VV 0xfc00707f +#define MATCH_VMIN_VV 0x14000057 +#define MASK_VMIN_VV 0xfc00707f +#define MATCH_VMAXU_VV 0x18000057 +#define MASK_VMAXU_VV 0xfc00707f +#define MATCH_VMAX_VV 0x1c000057 +#define MASK_VMAX_VV 0xfc00707f +#define MATCH_VAND_VV 0x24000057 +#define MASK_VAND_VV 0xfc00707f +#define MATCH_VOR_VV 0x28000057 +#define MASK_VOR_VV 0xfc00707f +#define MATCH_VXOR_VV 0x2c000057 +#define MASK_VXOR_VV 0xfc00707f +#define MATCH_VRGATHER_VV 0x30000057 +#define MASK_VRGATHER_VV 0xfc00707f +#define MATCH_VADC_VVM 0x40000057 +#define MASK_VADC_VVM 0xfe00707f +#define MATCH_VMADC_VVM 0x44000057 +#define MASK_VMADC_VVM 0xfc00707f +#define MATCH_VSBC_VVM 0x48000057 +#define MASK_VSBC_VVM 0xfe00707f +#define MATCH_VMSBC_VVM 0x4c000057 +#define MASK_VMSBC_VVM 0xfc00707f +#define MATCH_VMERGE_VVM 0x5c000057 +#define MASK_VMERGE_VVM 0xfe00707f +#define MATCH_VMV_V_V 0x5e000057 +#define MASK_VMV_V_V 0xfff0707f +#define MATCH_VMSEQ_VV 0x60000057 +#define MASK_VMSEQ_VV 0xfc00707f +#define MATCH_VMSNE_VV 0x64000057 +#define MASK_VMSNE_VV 0xfc00707f +#define MATCH_VMSLTU_VV 0x68000057 +#define MASK_VMSLTU_VV 0xfc00707f +#define MATCH_VMSLT_VV 0x6c000057 +#define MASK_VMSLT_VV 0xfc00707f +#define MATCH_VMSLEU_VV 0x70000057 +#define MASK_VMSLEU_VV 0xfc00707f +#define MATCH_VMSLE_VV 0x74000057 +#define MASK_VMSLE_VV 0xfc00707f +#define MATCH_VSADDU_VV 0x80000057 +#define MASK_VSADDU_VV 0xfc00707f +#define MATCH_VSADD_VV 0x84000057 +#define MASK_VSADD_VV 0xfc00707f +#define MATCH_VSSUBU_VV 0x88000057 +#define MASK_VSSUBU_VV 0xfc00707f +#define MATCH_VSSUB_VV 0x8c000057 +#define MASK_VSSUB_VV 0xfc00707f +#define MATCH_VSLL_VV 0x94000057 +#define MASK_VSLL_VV 0xfc00707f +#define MATCH_VSMUL_VV 0x9c000057 +#define MASK_VSMUL_VV 0xfc00707f +#define MATCH_VSRL_VV 0xa0000057 +#define MASK_VSRL_VV 0xfc00707f +#define MATCH_VSRA_VV 0xa4000057 +#define MASK_VSRA_VV 0xfc00707f +#define MATCH_VSSRL_VV 0xa8000057 +#define MASK_VSSRL_VV 0xfc00707f +#define MATCH_VSSRA_VV 0xac000057 +#define MASK_VSSRA_VV 0xfc00707f +#define MATCH_VNSRL_WV 0xb0000057 +#define MASK_VNSRL_WV 0xfc00707f +#define MATCH_VNSRA_WV 0xb4000057 +#define MASK_VNSRA_WV 0xfc00707f +#define MATCH_VNCLIPU_WV 0xb8000057 +#define MASK_VNCLIPU_WV 0xfc00707f +#define MATCH_VNCLIP_WV 0xbc000057 +#define MASK_VNCLIP_WV 0xfc00707f +#define MATCH_VWREDSUMU_VS 0xc0000057 +#define MASK_VWREDSUMU_VS 0xfc00707f +#define MATCH_VWREDSUM_VS 0xc4000057 +#define MASK_VWREDSUM_VS 0xfc00707f +#define MATCH_VDOTU_VV 0xe0000057 +#define MASK_VDOTU_VV 0xfc00707f +#define MATCH_VDOT_VV 0xe4000057 +#define MASK_VDOT_VV 0xfc00707f +#define MATCH_VQMACCU_VV 0xf0000057 +#define MASK_VQMACCU_VV 0xfc00707f +#define MATCH_VQMACC_VV 0xf4000057 +#define MASK_VQMACC_VV 0xfc00707f +#define MATCH_VQMACCSU_VV 0xfc000057 +#define MASK_VQMACCSU_VV 0xfc00707f +#define MATCH_VADD_VI 0x3057 +#define MASK_VADD_VI 0xfc00707f +#define MATCH_VRSUB_VI 0xc003057 +#define MASK_VRSUB_VI 0xfc00707f +#define MATCH_VAND_VI 0x24003057 +#define MASK_VAND_VI 0xfc00707f +#define MATCH_VOR_VI 0x28003057 +#define MASK_VOR_VI 0xfc00707f +#define MATCH_VXOR_VI 0x2c003057 +#define MASK_VXOR_VI 0xfc00707f +#define MATCH_VRGATHER_VI 0x30003057 +#define MASK_VRGATHER_VI 0xfc00707f +#define MATCH_VSLIDEUP_VI 0x38003057 +#define MASK_VSLIDEUP_VI 0xfc00707f +#define MATCH_VSLIDEDOWN_VI 0x3c003057 +#define MASK_VSLIDEDOWN_VI 0xfc00707f +#define MATCH_VADC_VIM 0x40003057 +#define MASK_VADC_VIM 0xfe00707f +#define MATCH_VMADC_VIM 0x44003057 +#define MASK_VMADC_VIM 0xfc00707f +#define MATCH_VMERGE_VIM 0x5c003057 +#define MASK_VMERGE_VIM 0xfe00707f +#define MATCH_VMV_V_I 0x5e003057 +#define MASK_VMV_V_I 0xfff0707f +#define MATCH_VMSEQ_VI 0x60003057 +#define MASK_VMSEQ_VI 0xfc00707f +#define MATCH_VMSNE_VI 0x64003057 +#define MASK_VMSNE_VI 0xfc00707f +#define MATCH_VMSLEU_VI 0x70003057 +#define MASK_VMSLEU_VI 0xfc00707f +#define MATCH_VMSLE_VI 0x74003057 +#define MASK_VMSLE_VI 0xfc00707f +#define MATCH_VMSGTU_VI 0x78003057 +#define MASK_VMSGTU_VI 0xfc00707f +#define MATCH_VMSGT_VI 0x7c003057 +#define MASK_VMSGT_VI 0xfc00707f +#define MATCH_VSADDU_VI 0x80003057 +#define MASK_VSADDU_VI 0xfc00707f +#define MATCH_VSADD_VI 0x84003057 +#define MASK_VSADD_VI 0xfc00707f +#define MATCH_VSLL_VI 0x94003057 +#define MASK_VSLL_VI 0xfc00707f +#define MATCH_VMV1R_V 0x9e003057 +#define MASK_VMV1R_V 0xfe0ff07f +#define MATCH_VMV2R_V 0x9e00b057 +#define MASK_VMV2R_V 0xfe0ff07f +#define MATCH_VMV4R_V 0x9e01b057 +#define MASK_VMV4R_V 0xfe0ff07f +#define MATCH_VMV8R_V 0x9e03b057 +#define MASK_VMV8R_V 0xfe0ff07f +#define MATCH_VSRL_VI 0xa0003057 +#define MASK_VSRL_VI 0xfc00707f +#define MATCH_VSRA_VI 0xa4003057 +#define MASK_VSRA_VI 0xfc00707f +#define MATCH_VSSRL_VI 0xa8003057 +#define MASK_VSSRL_VI 0xfc00707f +#define MATCH_VSSRA_VI 0xac003057 +#define MASK_VSSRA_VI 0xfc00707f +#define MATCH_VNSRL_WI 0xb0003057 +#define MASK_VNSRL_WI 0xfc00707f +#define MATCH_VNSRA_WI 0xb4003057 +#define MASK_VNSRA_WI 0xfc00707f +#define MATCH_VNCLIPU_WI 0xb8003057 +#define MASK_VNCLIPU_WI 0xfc00707f +#define MATCH_VNCLIP_WI 0xbc003057 +#define MASK_VNCLIP_WI 0xfc00707f +#define MATCH_VREDSUM_VS 0x2057 +#define MASK_VREDSUM_VS 0xfc00707f +#define MATCH_VREDAND_VS 0x4002057 +#define MASK_VREDAND_VS 0xfc00707f +#define MATCH_VREDOR_VS 0x8002057 +#define MASK_VREDOR_VS 0xfc00707f +#define MATCH_VREDXOR_VS 0xc002057 +#define MASK_VREDXOR_VS 0xfc00707f +#define MATCH_VREDMINU_VS 0x10002057 +#define MASK_VREDMINU_VS 0xfc00707f +#define MATCH_VREDMIN_VS 0x14002057 +#define MASK_VREDMIN_VS 0xfc00707f +#define MATCH_VREDMAXU_VS 0x18002057 +#define MASK_VREDMAXU_VS 0xfc00707f +#define MATCH_VREDMAX_VS 0x1c002057 +#define MASK_VREDMAX_VS 0xfc00707f +#define MATCH_VAADDU_VV 0x20002057 +#define MASK_VAADDU_VV 0xfc00707f +#define MATCH_VAADD_VV 0x24002057 +#define MASK_VAADD_VV 0xfc00707f +#define MATCH_VASUBU_VV 0x28002057 +#define MASK_VASUBU_VV 0xfc00707f +#define MATCH_VASUB_VV 0x2c002057 +#define MASK_VASUB_VV 0xfc00707f +#define MATCH_VMV_X_S 0x42002057 +#define MASK_VMV_X_S 0xfe0ff07f +#define MATCH_VCOMPRESS_VM 0x5e002057 +#define MASK_VCOMPRESS_VM 0xfe00707f +#define MATCH_VMANDNOT_MM 0x60002057 +#define MASK_VMANDNOT_MM 0xfc00707f +#define MATCH_VMAND_MM 0x64002057 +#define MASK_VMAND_MM 0xfc00707f +#define MATCH_VMOR_MM 0x68002057 +#define MASK_VMOR_MM 0xfc00707f +#define MATCH_VMXOR_MM 0x6c002057 +#define MASK_VMXOR_MM 0xfc00707f +#define MATCH_VMORNOT_MM 0x70002057 +#define MASK_VMORNOT_MM 0xfc00707f +#define MATCH_VMNAND_MM 0x74002057 +#define MASK_VMNAND_MM 0xfc00707f +#define MATCH_VMNOR_MM 0x78002057 +#define MASK_VMNOR_MM 0xfc00707f +#define MATCH_VMXNOR_MM 0x7c002057 +#define MASK_VMXNOR_MM 0xfc00707f +#define MATCH_VMSBF_M 0x5000a057 +#define MASK_VMSBF_M 0xfc0ff07f +#define MATCH_VMSOF_M 0x50012057 +#define MASK_VMSOF_M 0xfc0ff07f +#define MATCH_VMSIF_M 0x5001a057 +#define MASK_VMSIF_M 0xfc0ff07f +#define MATCH_VIOTA_M 0x50082057 +#define MASK_VIOTA_M 0xfc0ff07f +#define MATCH_VID_V 0x5008a057 +#define MASK_VID_V 0xfdfff07f +#define MATCH_VPOPC_M 0x40082057 +#define MASK_VPOPC_M 0xfc0ff07f +#define MATCH_VFIRST_M 0x4008a057 +#define MASK_VFIRST_M 0xfc0ff07f +#define MATCH_VDIVU_VV 0x80002057 +#define MASK_VDIVU_VV 0xfc00707f +#define MATCH_VDIV_VV 0x84002057 +#define MASK_VDIV_VV 0xfc00707f +#define MATCH_VREMU_VV 0x88002057 +#define MASK_VREMU_VV 0xfc00707f +#define MATCH_VREM_VV 0x8c002057 +#define MASK_VREM_VV 0xfc00707f +#define MATCH_VMULHU_VV 0x90002057 +#define MASK_VMULHU_VV 0xfc00707f +#define MATCH_VMUL_VV 0x94002057 +#define MASK_VMUL_VV 0xfc00707f +#define MATCH_VMULHSU_VV 0x98002057 +#define MASK_VMULHSU_VV 0xfc00707f +#define MATCH_VMULH_VV 0x9c002057 +#define MASK_VMULH_VV 0xfc00707f +#define MATCH_VMADD_VV 0xa4002057 +#define MASK_VMADD_VV 0xfc00707f +#define MATCH_VNMSUB_VV 0xac002057 +#define MASK_VNMSUB_VV 0xfc00707f +#define MATCH_VMACC_VV 0xb4002057 +#define MASK_VMACC_VV 0xfc00707f +#define MATCH_VNMSAC_VV 0xbc002057 +#define MASK_VNMSAC_VV 0xfc00707f +#define MATCH_VWADDU_VV 0xc0002057 +#define MASK_VWADDU_VV 0xfc00707f +#define MATCH_VWADD_VV 0xc4002057 +#define MASK_VWADD_VV 0xfc00707f +#define MATCH_VWSUBU_VV 0xc8002057 +#define MASK_VWSUBU_VV 0xfc00707f +#define MATCH_VWSUB_VV 0xcc002057 +#define MASK_VWSUB_VV 0xfc00707f +#define MATCH_VWADDU_WV 0xd0002057 +#define MASK_VWADDU_WV 0xfc00707f +#define MATCH_VWADD_WV 0xd4002057 +#define MASK_VWADD_WV 0xfc00707f +#define MATCH_VWSUBU_WV 0xd8002057 +#define MASK_VWSUBU_WV 0xfc00707f +#define MATCH_VWSUB_WV 0xdc002057 +#define MASK_VWSUB_WV 0xfc00707f +#define MATCH_VWMULU_VV 0xe0002057 +#define MASK_VWMULU_VV 0xfc00707f +#define MATCH_VWMULSU_VV 0xe8002057 +#define MASK_VWMULSU_VV 0xfc00707f +#define MATCH_VWMUL_VV 0xec002057 +#define MASK_VWMUL_VV 0xfc00707f +#define MATCH_VWMACCU_VV 0xf0002057 +#define MASK_VWMACCU_VV 0xfc00707f +#define MATCH_VWMACC_VV 0xf4002057 +#define MASK_VWMACC_VV 0xfc00707f +#define MATCH_VWMACCSU_VV 0xfc002057 +#define MASK_VWMACCSU_VV 0xfc00707f +#define MATCH_VAADDU_VX 0x20006057 +#define MASK_VAADDU_VX 0xfc00707f +#define MATCH_VAADD_VX 0x24006057 +#define MASK_VAADD_VX 0xfc00707f +#define MATCH_VASUBU_VX 0x28006057 +#define MASK_VASUBU_VX 0xfc00707f +#define MATCH_VASUB_VX 0x2c006057 +#define MASK_VASUB_VX 0xfc00707f +#define MATCH_VMV_S_X 0x42006057 +#define MASK_VMV_S_X 0xfff0707f +#define MATCH_VSLIDE1UP_VX 0x38006057 +#define MASK_VSLIDE1UP_VX 0xfc00707f +#define MATCH_VSLIDE1DOWN_VX 0x3c006057 +#define MASK_VSLIDE1DOWN_VX 0xfc00707f +#define MATCH_VDIVU_VX 0x80006057 +#define MASK_VDIVU_VX 0xfc00707f +#define MATCH_VDIV_VX 0x84006057 +#define MASK_VDIV_VX 0xfc00707f +#define MATCH_VREMU_VX 0x88006057 +#define MASK_VREMU_VX 0xfc00707f +#define MATCH_VREM_VX 0x8c006057 +#define MASK_VREM_VX 0xfc00707f +#define MATCH_VMULHU_VX 0x90006057 +#define MASK_VMULHU_VX 0xfc00707f +#define MATCH_VMUL_VX 0x94006057 +#define MASK_VMUL_VX 0xfc00707f +#define MATCH_VMULHSU_VX 0x98006057 +#define MASK_VMULHSU_VX 0xfc00707f +#define MATCH_VMULH_VX 0x9c006057 +#define MASK_VMULH_VX 0xfc00707f +#define MATCH_VMADD_VX 0xa4006057 +#define MASK_VMADD_VX 0xfc00707f +#define MATCH_VNMSUB_VX 0xac006057 +#define MASK_VNMSUB_VX 0xfc00707f +#define MATCH_VMACC_VX 0xb4006057 +#define MASK_VMACC_VX 0xfc00707f +#define MATCH_VNMSAC_VX 0xbc006057 +#define MASK_VNMSAC_VX 0xfc00707f +#define MATCH_VWADDU_VX 0xc0006057 +#define MASK_VWADDU_VX 0xfc00707f +#define MATCH_VWADD_VX 0xc4006057 +#define MASK_VWADD_VX 0xfc00707f +#define MATCH_VWSUBU_VX 0xc8006057 +#define MASK_VWSUBU_VX 0xfc00707f +#define MATCH_VWSUB_VX 0xcc006057 +#define MASK_VWSUB_VX 0xfc00707f +#define MATCH_VWADDU_WX 0xd0006057 +#define MASK_VWADDU_WX 0xfc00707f +#define MATCH_VWADD_WX 0xd4006057 +#define MASK_VWADD_WX 0xfc00707f +#define MATCH_VWSUBU_WX 0xd8006057 +#define MASK_VWSUBU_WX 0xfc00707f +#define MATCH_VWSUB_WX 0xdc006057 +#define MASK_VWSUB_WX 0xfc00707f +#define MATCH_VWMULU_VX 0xe0006057 +#define MASK_VWMULU_VX 0xfc00707f +#define MATCH_VWMULSU_VX 0xe8006057 +#define MASK_VWMULSU_VX 0xfc00707f +#define MATCH_VWMUL_VX 0xec006057 +#define MASK_VWMUL_VX 0xfc00707f +#define MATCH_VWMACCU_VX 0xf0006057 +#define MASK_VWMACCU_VX 0xfc00707f +#define MATCH_VWMACC_VX 0xf4006057 +#define MASK_VWMACC_VX 0xfc00707f +#define MATCH_VWMACCUS_VX 0xf8006057 +#define MASK_VWMACCUS_VX 0xfc00707f +#define MATCH_VWMACCSU_VX 0xfc006057 +#define MASK_VWMACCSU_VX 0xfc00707f +#define MATCH_VAMOSWAPW_V 0x800602f +#define MASK_VAMOSWAPW_V 0xf800707f +#define MATCH_VAMOADDW_V 0x602f +#define MASK_VAMOADDW_V 0xf800707f +#define MATCH_VAMOXORW_V 0x2000602f +#define MASK_VAMOXORW_V 0xf800707f +#define MATCH_VAMOANDW_V 0x6000602f +#define MASK_VAMOANDW_V 0xf800707f +#define MATCH_VAMOORW_V 0x4000602f +#define MASK_VAMOORW_V 0xf800707f +#define MATCH_VAMOMINW_V 0x8000602f +#define MASK_VAMOMINW_V 0xf800707f +#define MATCH_VAMOMAXW_V 0xa000602f +#define MASK_VAMOMAXW_V 0xf800707f +#define MATCH_VAMOMINUW_V 0xc000602f +#define MASK_VAMOMINUW_V 0xf800707f +#define MATCH_VAMOMAXUW_V 0xe000602f +#define MASK_VAMOMAXUW_V 0xf800707f +#define MATCH_VAMOSWAPE_V 0x800702f +#define MASK_VAMOSWAPE_V 0xf800707f +#define MATCH_VAMOADDE_V 0x702f +#define MASK_VAMOADDE_V 0xf800707f +#define MATCH_VAMOXORE_V 0x2000702f +#define MASK_VAMOXORE_V 0xf800707f +#define MATCH_VAMOANDE_V 0x6000702f +#define MASK_VAMOANDE_V 0xf800707f +#define MATCH_VAMOORE_V 0x4000702f +#define MASK_VAMOORE_V 0xf800707f +#define MATCH_VAMOMINE_V 0x8000702f +#define MASK_VAMOMINE_V 0xf800707f +#define MATCH_VAMOMAXE_V 0xa000702f +#define MASK_VAMOMAXE_V 0xf800707f +#define MATCH_VAMOMINUE_V 0xc000702f +#define MASK_VAMOMINUE_V 0xf800707f +#define MATCH_VAMOMAXUE_V 0xe000702f +#define MASK_VAMOMAXUE_V 0xf800707f +#define MATCH_VMVNFR_V 0x9e003057 +#define MASK_VMVNFR_V 0xfe00707f +#define CSR_FFLAGS 0x1 +#define CSR_FRM 0x2 +#define CSR_FCSR 0x3 +#define CSR_USTATUS 0x0 +#define CSR_UIE 0x4 +#define CSR_UTVEC 0x5 +#define CSR_VSTART 0x8 +#define CSR_VXSAT 0x9 +#define CSR_VXRM 0xa +#define CSR_VCSR 0xf +#define CSR_USCRATCH 0x40 +#define CSR_UEPC 0x41 +#define CSR_UCAUSE 0x42 +#define CSR_UTVAL 0x43 +#define CSR_UIP 0x44 +#define CSR_CYCLE 0xc00 +#define CSR_TIME 0xc01 +#define CSR_INSTRET 0xc02 +#define CSR_HPMCOUNTER3 0xc03 +#define CSR_HPMCOUNTER4 0xc04 +#define CSR_HPMCOUNTER5 0xc05 +#define CSR_HPMCOUNTER6 0xc06 +#define CSR_HPMCOUNTER7 0xc07 +#define CSR_HPMCOUNTER8 0xc08 +#define CSR_HPMCOUNTER9 0xc09 +#define CSR_HPMCOUNTER10 0xc0a +#define CSR_HPMCOUNTER11 0xc0b +#define CSR_HPMCOUNTER12 0xc0c +#define CSR_HPMCOUNTER13 0xc0d +#define CSR_HPMCOUNTER14 0xc0e +#define CSR_HPMCOUNTER15 0xc0f +#define CSR_HPMCOUNTER16 0xc10 +#define CSR_HPMCOUNTER17 0xc11 +#define CSR_HPMCOUNTER18 0xc12 +#define CSR_HPMCOUNTER19 0xc13 +#define CSR_HPMCOUNTER20 0xc14 +#define CSR_HPMCOUNTER21 0xc15 +#define CSR_HPMCOUNTER22 0xc16 +#define CSR_HPMCOUNTER23 0xc17 +#define CSR_HPMCOUNTER24 0xc18 +#define CSR_HPMCOUNTER25 0xc19 +#define CSR_HPMCOUNTER26 0xc1a +#define CSR_HPMCOUNTER27 0xc1b +#define CSR_HPMCOUNTER28 0xc1c +#define CSR_HPMCOUNTER29 0xc1d +#define CSR_HPMCOUNTER30 0xc1e +#define CSR_HPMCOUNTER31 0xc1f +#define CSR_VL 0xc20 +#define CSR_VTYPE 0xc21 +#define CSR_VLENB 0xc22 +#define CSR_SSTATUS 0x100 +#define CSR_SEDELEG 0x102 +#define CSR_SIDELEG 0x103 +#define CSR_SIE 0x104 +#define CSR_STVEC 0x105 +#define CSR_SCOUNTEREN 0x106 +#define CSR_SSCRATCH 0x140 +#define CSR_SEPC 0x141 +#define CSR_SCAUSE 0x142 +#define CSR_STVAL 0x143 +#define CSR_SIP 0x144 +#define CSR_SATP 0x180 +#define CSR_VSSTATUS 0x200 +#define CSR_VSIE 0x204 +#define CSR_VSTVEC 0x205 +#define CSR_VSSCRATCH 0x240 +#define CSR_VSEPC 0x241 +#define CSR_VSCAUSE 0x242 +#define CSR_VSTVAL 0x243 +#define CSR_VSIP 0x244 +#define CSR_VSATP 0x280 +#define CSR_HSTATUS 0x600 +#define CSR_HEDELEG 0x602 +#define CSR_HIDELEG 0x603 +#define CSR_HIE 0x604 +#define CSR_HTIMEDELTA 0x605 +#define CSR_HCOUNTEREN 0x606 +#define CSR_HGEIE 0x607 +#define CSR_HTVAL 0x643 +#define CSR_HIP 0x644 +#define CSR_HVIP 0x645 +#define CSR_HTINST 0x64a +#define CSR_HGATP 0x680 +#define CSR_HGEIP 0xe12 +#define CSR_UTVT 0x7 +#define CSR_UNXTI 0x45 +#define CSR_UINTSTATUS 0x46 +#define CSR_USCRATCHCSW 0x48 +#define CSR_USCRATCHCSWL 0x49 +#define CSR_STVT 0x107 +#define CSR_SNXTI 0x145 +#define CSR_SINTSTATUS 0x146 +#define CSR_SSCRATCHCSW 0x148 +#define CSR_SSCRATCHCSWL 0x149 +#define CSR_MTVT 0x307 +#define CSR_MNXTI 0x345 +#define CSR_MINTSTATUS 0x346 +#define CSR_MSCRATCHCSW 0x348 +#define CSR_MSCRATCHCSWL 0x349 +#define CSR_MSTATUS 0x300 +#define CSR_MISA 0x301 +#define CSR_MEDELEG 0x302 +#define CSR_MIDELEG 0x303 +#define CSR_MIE 0x304 +#define CSR_MTVEC 0x305 +#define CSR_MCOUNTEREN 0x306 +#define CSR_MCOUNTINHIBIT 0x320 +#define CSR_MSCRATCH 0x340 +#define CSR_MEPC 0x341 +#define CSR_MCAUSE 0x342 +#define CSR_MTVAL 0x343 +#define CSR_MIP 0x344 +#define CSR_MTINST 0x34a +#define CSR_MTVAL2 0x34b +#define CSR_PMPCFG0 0x3a0 +#define CSR_PMPCFG1 0x3a1 +#define CSR_PMPCFG2 0x3a2 +#define CSR_PMPCFG3 0x3a3 +#define CSR_PMPADDR0 0x3b0 +#define CSR_PMPADDR1 0x3b1 +#define CSR_PMPADDR2 0x3b2 +#define CSR_PMPADDR3 0x3b3 +#define CSR_PMPADDR4 0x3b4 +#define CSR_PMPADDR5 0x3b5 +#define CSR_PMPADDR6 0x3b6 +#define CSR_PMPADDR7 0x3b7 +#define CSR_PMPADDR8 0x3b8 +#define CSR_PMPADDR9 0x3b9 +#define CSR_PMPADDR10 0x3ba +#define CSR_PMPADDR11 0x3bb +#define CSR_PMPADDR12 0x3bc +#define CSR_PMPADDR13 0x3bd +#define CSR_PMPADDR14 0x3be +#define CSR_PMPADDR15 0x3bf +#define CSR_TSELECT 0x7a0 +#define CSR_TDATA1 0x7a1 +#define CSR_TDATA2 0x7a2 +#define CSR_TDATA3 0x7a3 +#define CSR_DCSR 0x7b0 +#define CSR_DPC 0x7b1 +#define CSR_DSCRATCH0 0x7b2 +#define CSR_DSCRATCH1 0x7b3 +#define CSR_MCYCLE 0xb00 +#define CSR_MINSTRET 0xb02 +#define CSR_MHPMCOUNTER3 0xb03 +#define CSR_MHPMCOUNTER4 0xb04 +#define CSR_MHPMCOUNTER5 0xb05 +#define CSR_MHPMCOUNTER6 0xb06 +#define CSR_MHPMCOUNTER7 0xb07 +#define CSR_MHPMCOUNTER8 0xb08 +#define CSR_MHPMCOUNTER9 0xb09 +#define CSR_MHPMCOUNTER10 0xb0a +#define CSR_MHPMCOUNTER11 0xb0b +#define CSR_MHPMCOUNTER12 0xb0c +#define CSR_MHPMCOUNTER13 0xb0d +#define CSR_MHPMCOUNTER14 0xb0e +#define CSR_MHPMCOUNTER15 0xb0f +#define CSR_MHPMCOUNTER16 0xb10 +#define CSR_MHPMCOUNTER17 0xb11 +#define CSR_MHPMCOUNTER18 0xb12 +#define CSR_MHPMCOUNTER19 0xb13 +#define CSR_MHPMCOUNTER20 0xb14 +#define CSR_MHPMCOUNTER21 0xb15 +#define CSR_MHPMCOUNTER22 0xb16 +#define CSR_MHPMCOUNTER23 0xb17 +#define CSR_MHPMCOUNTER24 0xb18 +#define CSR_MHPMCOUNTER25 0xb19 +#define CSR_MHPMCOUNTER26 0xb1a +#define CSR_MHPMCOUNTER27 0xb1b +#define CSR_MHPMCOUNTER28 0xb1c +#define CSR_MHPMCOUNTER29 0xb1d +#define CSR_MHPMCOUNTER30 0xb1e +#define CSR_MHPMCOUNTER31 0xb1f +#define CSR_MHPMEVENT3 0x323 +#define CSR_MHPMEVENT4 0x324 +#define CSR_MHPMEVENT5 0x325 +#define CSR_MHPMEVENT6 0x326 +#define CSR_MHPMEVENT7 0x327 +#define CSR_MHPMEVENT8 0x328 +#define CSR_MHPMEVENT9 0x329 +#define CSR_MHPMEVENT10 0x32a +#define CSR_MHPMEVENT11 0x32b +#define CSR_MHPMEVENT12 0x32c +#define CSR_MHPMEVENT13 0x32d +#define CSR_MHPMEVENT14 0x32e +#define CSR_MHPMEVENT15 0x32f +#define CSR_MHPMEVENT16 0x330 +#define CSR_MHPMEVENT17 0x331 +#define CSR_MHPMEVENT18 0x332 +#define CSR_MHPMEVENT19 0x333 +#define CSR_MHPMEVENT20 0x334 +#define CSR_MHPMEVENT21 0x335 +#define CSR_MHPMEVENT22 0x336 +#define CSR_MHPMEVENT23 0x337 +#define CSR_MHPMEVENT24 0x338 +#define CSR_MHPMEVENT25 0x339 +#define CSR_MHPMEVENT26 0x33a +#define CSR_MHPMEVENT27 0x33b +#define CSR_MHPMEVENT28 0x33c +#define CSR_MHPMEVENT29 0x33d +#define CSR_MHPMEVENT30 0x33e +#define CSR_MHPMEVENT31 0x33f +#define CSR_MVENDORID 0xf11 +#define CSR_MARCHID 0xf12 +#define CSR_MIMPID 0xf13 +#define CSR_MHARTID 0xf14 +#define CSR_HTIMEDELTAH 0x615 +#define CSR_CYCLEH 0xc80 +#define CSR_TIMEH 0xc81 +#define CSR_INSTRETH 0xc82 +#define CSR_HPMCOUNTER3H 0xc83 +#define CSR_HPMCOUNTER4H 0xc84 +#define CSR_HPMCOUNTER5H 0xc85 +#define CSR_HPMCOUNTER6H 0xc86 +#define CSR_HPMCOUNTER7H 0xc87 +#define CSR_HPMCOUNTER8H 0xc88 +#define CSR_HPMCOUNTER9H 0xc89 +#define CSR_HPMCOUNTER10H 0xc8a +#define CSR_HPMCOUNTER11H 0xc8b +#define CSR_HPMCOUNTER12H 0xc8c +#define CSR_HPMCOUNTER13H 0xc8d +#define CSR_HPMCOUNTER14H 0xc8e +#define CSR_HPMCOUNTER15H 0xc8f +#define CSR_HPMCOUNTER16H 0xc90 +#define CSR_HPMCOUNTER17H 0xc91 +#define CSR_HPMCOUNTER18H 0xc92 +#define CSR_HPMCOUNTER19H 0xc93 +#define CSR_HPMCOUNTER20H 0xc94 +#define CSR_HPMCOUNTER21H 0xc95 +#define CSR_HPMCOUNTER22H 0xc96 +#define CSR_HPMCOUNTER23H 0xc97 +#define CSR_HPMCOUNTER24H 0xc98 +#define CSR_HPMCOUNTER25H 0xc99 +#define CSR_HPMCOUNTER26H 0xc9a +#define CSR_HPMCOUNTER27H 0xc9b +#define CSR_HPMCOUNTER28H 0xc9c +#define CSR_HPMCOUNTER29H 0xc9d +#define CSR_HPMCOUNTER30H 0xc9e +#define CSR_HPMCOUNTER31H 0xc9f +#define CSR_MSTATUSH 0x310 +#define CSR_MCYCLEH 0xb80 +#define CSR_MINSTRETH 0xb82 +#define CSR_MHPMCOUNTER3H 0xb83 +#define CSR_MHPMCOUNTER4H 0xb84 +#define CSR_MHPMCOUNTER5H 0xb85 +#define CSR_MHPMCOUNTER6H 0xb86 +#define CSR_MHPMCOUNTER7H 0xb87 +#define CSR_MHPMCOUNTER8H 0xb88 +#define CSR_MHPMCOUNTER9H 0xb89 +#define CSR_MHPMCOUNTER10H 0xb8a +#define CSR_MHPMCOUNTER11H 0xb8b +#define CSR_MHPMCOUNTER12H 0xb8c +#define CSR_MHPMCOUNTER13H 0xb8d +#define CSR_MHPMCOUNTER14H 0xb8e +#define CSR_MHPMCOUNTER15H 0xb8f +#define CSR_MHPMCOUNTER16H 0xb90 +#define CSR_MHPMCOUNTER17H 0xb91 +#define CSR_MHPMCOUNTER18H 0xb92 +#define CSR_MHPMCOUNTER19H 0xb93 +#define CSR_MHPMCOUNTER20H 0xb94 +#define CSR_MHPMCOUNTER21H 0xb95 +#define CSR_MHPMCOUNTER22H 0xb96 +#define CSR_MHPMCOUNTER23H 0xb97 +#define CSR_MHPMCOUNTER24H 0xb98 +#define CSR_MHPMCOUNTER25H 0xb99 +#define CSR_MHPMCOUNTER26H 0xb9a +#define CSR_MHPMCOUNTER27H 0xb9b +#define CSR_MHPMCOUNTER28H 0xb9c +#define CSR_MHPMCOUNTER29H 0xb9d +#define CSR_MHPMCOUNTER30H 0xb9e +#define CSR_MHPMCOUNTER31H 0xb9f +#define CAUSE_MISALIGNED_FETCH 0x0 +#define CAUSE_FETCH_ACCESS 0x1 +#define CAUSE_ILLEGAL_INSTRUCTION 0x2 +#define CAUSE_BREAKPOINT 0x3 +#define CAUSE_MISALIGNED_LOAD 0x4 +#define CAUSE_LOAD_ACCESS 0x5 +#define CAUSE_MISALIGNED_STORE 0x6 +#define CAUSE_STORE_ACCESS 0x7 +#define CAUSE_USER_ECALL 0x8 +#define CAUSE_SUPERVISOR_ECALL 0x9 +#define CAUSE_HYPERVISOR_ECALL 0xa +#define CAUSE_MACHINE_ECALL 0xb +#define CAUSE_FETCH_PAGE_FAULT 0xc +#define CAUSE_LOAD_PAGE_FAULT 0xd +#define CAUSE_STORE_PAGE_FAULT 0xf +#endif +#ifdef DECLARE_INSN +DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32) +DECLARE_INSN(srli_rv32, MATCH_SRLI_RV32, MASK_SRLI_RV32) +DECLARE_INSN(srai_rv32, MATCH_SRAI_RV32, MASK_SRAI_RV32) +DECLARE_INSN(frflags, MATCH_FRFLAGS, MASK_FRFLAGS) +DECLARE_INSN(fsflags, MATCH_FSFLAGS, MASK_FSFLAGS) +DECLARE_INSN(fsflagsi, MATCH_FSFLAGSI, MASK_FSFLAGSI) +DECLARE_INSN(frrm, MATCH_FRRM, MASK_FRRM) +DECLARE_INSN(fsrm, MATCH_FSRM, MASK_FSRM) +DECLARE_INSN(fsrmi, MATCH_FSRMI, MASK_FSRMI) +DECLARE_INSN(fscsr, MATCH_FSCSR, MASK_FSCSR) +DECLARE_INSN(frcsr, MATCH_FRCSR, MASK_FRCSR) +DECLARE_INSN(rdcycle, MATCH_RDCYCLE, MASK_RDCYCLE) +DECLARE_INSN(rdtime, MATCH_RDTIME, MASK_RDTIME) +DECLARE_INSN(rdinstret, MATCH_RDINSTRET, MASK_RDINSTRET) +DECLARE_INSN(rdcycleh, MATCH_RDCYCLEH, MASK_RDCYCLEH) +DECLARE_INSN(rdtimeh, MATCH_RDTIMEH, MASK_RDTIMEH) +DECLARE_INSN(rdinstreth, MATCH_RDINSTRETH, MASK_RDINSTRETH) +DECLARE_INSN(scall, MATCH_SCALL, MASK_SCALL) +DECLARE_INSN(sbreak, MATCH_SBREAK, MASK_SBREAK) +DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S) +DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X) +DECLARE_INSN(fence_tso, MATCH_FENCE_TSO, MASK_FENCE_TSO) +DECLARE_INSN(pause, MATCH_PAUSE, MASK_PAUSE) +DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ) +DECLARE_INSN(bne, MATCH_BNE, MASK_BNE) +DECLARE_INSN(blt, MATCH_BLT, MASK_BLT) +DECLARE_INSN(bge, MATCH_BGE, MASK_BGE) +DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU) +DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU) +DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR) +DECLARE_INSN(jal, MATCH_JAL, MASK_JAL) +DECLARE_INSN(lui, MATCH_LUI, MASK_LUI) +DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC) +DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI) +DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI) +DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI) +DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU) +DECLARE_INSN(xori, MATCH_XORI, MASK_XORI) +DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI) +DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI) +DECLARE_INSN(ori, MATCH_ORI, MASK_ORI) +DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI) +DECLARE_INSN(add, MATCH_ADD, MASK_ADD) +DECLARE_INSN(sub, MATCH_SUB, MASK_SUB) +DECLARE_INSN(sll, MATCH_SLL, MASK_SLL) +DECLARE_INSN(slt, MATCH_SLT, MASK_SLT) +DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU) +DECLARE_INSN(xor, MATCH_XOR, MASK_XOR) +DECLARE_INSN(srl, MATCH_SRL, MASK_SRL) +DECLARE_INSN(sra, MATCH_SRA, MASK_SRA) +DECLARE_INSN(or, MATCH_OR, MASK_OR) +DECLARE_INSN(and, MATCH_AND, MASK_AND) +DECLARE_INSN(lb, MATCH_LB, MASK_LB) +DECLARE_INSN(lh, MATCH_LH, MASK_LH) +DECLARE_INSN(lw, MATCH_LW, MASK_LW) +DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU) +DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU) +DECLARE_INSN(sb, MATCH_SB, MASK_SB) +DECLARE_INSN(sh, MATCH_SH, MASK_SH) +DECLARE_INSN(sw, MATCH_SW, MASK_SW) +DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE) +DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I) +DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW) +DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW) +DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW) +DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW) +DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW) +DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW) +DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW) +DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW) +DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW) +DECLARE_INSN(ld, MATCH_LD, MASK_LD) +DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU) +DECLARE_INSN(sd, MATCH_SD, MASK_SD) +DECLARE_INSN(mul, MATCH_MUL, MASK_MUL) +DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH) +DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU) +DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU) +DECLARE_INSN(div, MATCH_DIV, MASK_DIV) +DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU) +DECLARE_INSN(rem, MATCH_REM, MASK_REM) +DECLARE_INSN(remu, MATCH_REMU, MASK_REMU) +DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW) +DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW) +DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW) +DECLARE_INSN(remw, MATCH_REMW, MASK_REMW) +DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW) +DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W) +DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W) +DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W) +DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W) +DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W) +DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W) +DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W) +DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W) +DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W) +DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W) +DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W) +DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D) +DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D) +DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D) +DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D) +DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D) +DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D) +DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D) +DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D) +DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D) +DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D) +DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D) +DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S) +DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S) +DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S) +DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S) +DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S) +DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S) +DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S) +DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S) +DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S) +DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S) +DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S) +DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S) +DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S) +DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S) +DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S) +DECLARE_INSN(fmv_x_w, MATCH_FMV_X_W, MASK_FMV_X_W) +DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S) +DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) +DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU) +DECLARE_INSN(fmv_w_x, MATCH_FMV_W_X, MASK_FMV_W_X) +DECLARE_INSN(flw, MATCH_FLW, MASK_FLW) +DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW) +DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S) +DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S) +DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S) +DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S) +DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S) +DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S) +DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L) +DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU) +DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D) +DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D) +DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D) +DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D) +DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D) +DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D) +DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D) +DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D) +DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D) +DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D) +DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S) +DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D) +DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D) +DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D) +DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D) +DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D) +DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D) +DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D) +DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W) +DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU) +DECLARE_INSN(fld, MATCH_FLD, MASK_FLD) +DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD) +DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D) +DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D) +DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D) +DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D) +DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D) +DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D) +DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D) +DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L) +DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU) +DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X) +DECLARE_INSN(fadd_q, MATCH_FADD_Q, MASK_FADD_Q) +DECLARE_INSN(fsub_q, MATCH_FSUB_Q, MASK_FSUB_Q) +DECLARE_INSN(fmul_q, MATCH_FMUL_Q, MASK_FMUL_Q) +DECLARE_INSN(fdiv_q, MATCH_FDIV_Q, MASK_FDIV_Q) +DECLARE_INSN(fsgnj_q, MATCH_FSGNJ_Q, MASK_FSGNJ_Q) +DECLARE_INSN(fsgnjn_q, MATCH_FSGNJN_Q, MASK_FSGNJN_Q) +DECLARE_INSN(fsgnjx_q, MATCH_FSGNJX_Q, MASK_FSGNJX_Q) +DECLARE_INSN(fmin_q, MATCH_FMIN_Q, MASK_FMIN_Q) +DECLARE_INSN(fmax_q, MATCH_FMAX_Q, MASK_FMAX_Q) +DECLARE_INSN(fcvt_s_q, MATCH_FCVT_S_Q, MASK_FCVT_S_Q) +DECLARE_INSN(fcvt_q_s, MATCH_FCVT_Q_S, MASK_FCVT_Q_S) +DECLARE_INSN(fcvt_d_q, MATCH_FCVT_D_Q, MASK_FCVT_D_Q) +DECLARE_INSN(fcvt_q_d, MATCH_FCVT_Q_D, MASK_FCVT_Q_D) +DECLARE_INSN(fsqrt_q, MATCH_FSQRT_Q, MASK_FSQRT_Q) +DECLARE_INSN(fle_q, MATCH_FLE_Q, MASK_FLE_Q) +DECLARE_INSN(flt_q, MATCH_FLT_Q, MASK_FLT_Q) +DECLARE_INSN(feq_q, MATCH_FEQ_Q, MASK_FEQ_Q) +DECLARE_INSN(fcvt_w_q, MATCH_FCVT_W_Q, MASK_FCVT_W_Q) +DECLARE_INSN(fcvt_wu_q, MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q) +DECLARE_INSN(fclass_q, MATCH_FCLASS_Q, MASK_FCLASS_Q) +DECLARE_INSN(fcvt_q_w, MATCH_FCVT_Q_W, MASK_FCVT_Q_W) +DECLARE_INSN(fcvt_q_wu, MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU) +DECLARE_INSN(flq, MATCH_FLQ, MASK_FLQ) +DECLARE_INSN(fsq, MATCH_FSQ, MASK_FSQ) +DECLARE_INSN(fmadd_q, MATCH_FMADD_Q, MASK_FMADD_Q) +DECLARE_INSN(fmsub_q, MATCH_FMSUB_Q, MASK_FMSUB_Q) +DECLARE_INSN(fnmsub_q, MATCH_FNMSUB_Q, MASK_FNMSUB_Q) +DECLARE_INSN(fnmadd_q, MATCH_FNMADD_Q, MASK_FNMADD_Q) +DECLARE_INSN(fcvt_l_q, MATCH_FCVT_L_Q, MASK_FCVT_L_Q) +DECLARE_INSN(fcvt_lu_q, MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q) +DECLARE_INSN(fcvt_q_l, MATCH_FCVT_Q_L, MASK_FCVT_Q_L) +DECLARE_INSN(fcvt_q_lu, MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU) +DECLARE_INSN(fmv_x_q, MATCH_FMV_X_Q, MASK_FMV_X_Q) +DECLARE_INSN(fmv_q_x, MATCH_FMV_Q_X, MASK_FMV_Q_X) +DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL) +DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK) +DECLARE_INSN(uret, MATCH_URET, MASK_URET) +DECLARE_INSN(sret, MATCH_SRET, MASK_SRET) +DECLARE_INSN(mret, MATCH_MRET, MASK_MRET) +DECLARE_INSN(dret, MATCH_DRET, MASK_DRET) +DECLARE_INSN(sfence_vma, MATCH_SFENCE_VMA, MASK_SFENCE_VMA) +DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) +DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) +DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS) +DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC) +DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI) +DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI) +DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI) +DECLARE_INSN(hfence_vvma, MATCH_HFENCE_VVMA, MASK_HFENCE_VVMA) +DECLARE_INSN(hfence_gvma, MATCH_HFENCE_GVMA, MASK_HFENCE_GVMA) +DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP) +DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP) +DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR) +DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR) +DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK) +DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN) +DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD) +DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW) +DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW) +DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD) +DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW) +DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW) +DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI) +DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL) +DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI) +DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI) +DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI) +DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI) +DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI) +DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB) +DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR) +DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR) +DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND) +DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J) +DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ) +DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ) +DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI) +DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP) +DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP) +DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP) +DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV) +DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD) +DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP) +DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP) +DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP) +DECLARE_INSN(c_srli_rv32, MATCH_C_SRLI_RV32, MASK_C_SRLI_RV32) +DECLARE_INSN(c_srai_rv32, MATCH_C_SRAI_RV32, MASK_C_SRAI_RV32) +DECLARE_INSN(c_slli_rv32, MATCH_C_SLLI_RV32, MASK_C_SLLI_RV32) +DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD) +DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD) +DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW) +DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW) +DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW) +DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP) +DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) +DECLARE_INSN(c_lq, MATCH_C_LQ, MASK_C_LQ) +DECLARE_INSN(c_sq, MATCH_C_SQ, MASK_C_SQ) +DECLARE_INSN(c_lqsp, MATCH_C_LQSP, MASK_C_LQSP) +DECLARE_INSN(c_sqsp, MATCH_C_SQSP, MASK_C_SQSP) +DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0) +DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1) +DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2) +DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD) +DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1) +DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2) +DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1) +DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1) +DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2) +DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD) +DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1) +DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2) +DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2) +DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1) +DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2) +DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD) +DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1) +DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2) +DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3) +DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1) +DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2) +DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD) +DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1) +DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2) +DECLARE_INSN(vsetvli, MATCH_VSETVLI, MASK_VSETVLI) +DECLARE_INSN(vsetvl, MATCH_VSETVL, MASK_VSETVL) +DECLARE_INSN(vlb_v, MATCH_VLB_V, MASK_VLB_V) +DECLARE_INSN(vlh_v, MATCH_VLH_V, MASK_VLH_V) +DECLARE_INSN(vlw_v, MATCH_VLW_V, MASK_VLW_V) +DECLARE_INSN(vle_v, MATCH_VLE_V, MASK_VLE_V) +DECLARE_INSN(vlbu_v, MATCH_VLBU_V, MASK_VLBU_V) +DECLARE_INSN(vlhu_v, MATCH_VLHU_V, MASK_VLHU_V) +DECLARE_INSN(vlwu_v, MATCH_VLWU_V, MASK_VLWU_V) +DECLARE_INSN(vsb_v, MATCH_VSB_V, MASK_VSB_V) +DECLARE_INSN(vsh_v, MATCH_VSH_V, MASK_VSH_V) +DECLARE_INSN(vsw_v, MATCH_VSW_V, MASK_VSW_V) +DECLARE_INSN(vse_v, MATCH_VSE_V, MASK_VSE_V) +DECLARE_INSN(vlsb_v, MATCH_VLSB_V, MASK_VLSB_V) +DECLARE_INSN(vlsh_v, MATCH_VLSH_V, MASK_VLSH_V) +DECLARE_INSN(vlsw_v, MATCH_VLSW_V, MASK_VLSW_V) +DECLARE_INSN(vlse_v, MATCH_VLSE_V, MASK_VLSE_V) +DECLARE_INSN(vlsbu_v, MATCH_VLSBU_V, MASK_VLSBU_V) +DECLARE_INSN(vlshu_v, MATCH_VLSHU_V, MASK_VLSHU_V) +DECLARE_INSN(vlswu_v, MATCH_VLSWU_V, MASK_VLSWU_V) +DECLARE_INSN(vssb_v, MATCH_VSSB_V, MASK_VSSB_V) +DECLARE_INSN(vssh_v, MATCH_VSSH_V, MASK_VSSH_V) +DECLARE_INSN(vssw_v, MATCH_VSSW_V, MASK_VSSW_V) +DECLARE_INSN(vsse_v, MATCH_VSSE_V, MASK_VSSE_V) +DECLARE_INSN(vlxb_v, MATCH_VLXB_V, MASK_VLXB_V) +DECLARE_INSN(vlxh_v, MATCH_VLXH_V, MASK_VLXH_V) +DECLARE_INSN(vlxw_v, MATCH_VLXW_V, MASK_VLXW_V) +DECLARE_INSN(vlxe_v, MATCH_VLXE_V, MASK_VLXE_V) +DECLARE_INSN(vlxbu_v, MATCH_VLXBU_V, MASK_VLXBU_V) +DECLARE_INSN(vlxhu_v, MATCH_VLXHU_V, MASK_VLXHU_V) +DECLARE_INSN(vlxwu_v, MATCH_VLXWU_V, MASK_VLXWU_V) +DECLARE_INSN(vsxb_v, MATCH_VSXB_V, MASK_VSXB_V) +DECLARE_INSN(vsxh_v, MATCH_VSXH_V, MASK_VSXH_V) +DECLARE_INSN(vsxw_v, MATCH_VSXW_V, MASK_VSXW_V) +DECLARE_INSN(vsxe_v, MATCH_VSXE_V, MASK_VSXE_V) +DECLARE_INSN(vsuxb_v, MATCH_VSUXB_V, MASK_VSUXB_V) +DECLARE_INSN(vsuxh_v, MATCH_VSUXH_V, MASK_VSUXH_V) +DECLARE_INSN(vsuxw_v, MATCH_VSUXW_V, MASK_VSUXW_V) +DECLARE_INSN(vsuxe_v, MATCH_VSUXE_V, MASK_VSUXE_V) +DECLARE_INSN(vlbff_v, MATCH_VLBFF_V, MASK_VLBFF_V) +DECLARE_INSN(vlhff_v, MATCH_VLHFF_V, MASK_VLHFF_V) +DECLARE_INSN(vlwff_v, MATCH_VLWFF_V, MASK_VLWFF_V) +DECLARE_INSN(vleff_v, MATCH_VLEFF_V, MASK_VLEFF_V) +DECLARE_INSN(vlbuff_v, MATCH_VLBUFF_V, MASK_VLBUFF_V) +DECLARE_INSN(vlhuff_v, MATCH_VLHUFF_V, MASK_VLHUFF_V) +DECLARE_INSN(vlwuff_v, MATCH_VLWUFF_V, MASK_VLWUFF_V) +DECLARE_INSN(vl1r_v, MATCH_VL1R_V, MASK_VL1R_V) +DECLARE_INSN(vs1r_v, MATCH_VS1R_V, MASK_VS1R_V) +DECLARE_INSN(vfadd_vf, MATCH_VFADD_VF, MASK_VFADD_VF) +DECLARE_INSN(vfsub_vf, MATCH_VFSUB_VF, MASK_VFSUB_VF) +DECLARE_INSN(vfmin_vf, MATCH_VFMIN_VF, MASK_VFMIN_VF) +DECLARE_INSN(vfmax_vf, MATCH_VFMAX_VF, MASK_VFMAX_VF) +DECLARE_INSN(vfsgnj_vf, MATCH_VFSGNJ_VF, MASK_VFSGNJ_VF) +DECLARE_INSN(vfsgnjn_vf, MATCH_VFSGNJN_VF, MASK_VFSGNJN_VF) +DECLARE_INSN(vfsgnjx_vf, MATCH_VFSGNJX_VF, MASK_VFSGNJX_VF) +DECLARE_INSN(vfslide1up_vf, MATCH_VFSLIDE1UP_VF, MASK_VFSLIDE1UP_VF) +DECLARE_INSN(vfslide1down_vf, MATCH_VFSLIDE1DOWN_VF, MASK_VFSLIDE1DOWN_VF) +DECLARE_INSN(vfmv_s_f, MATCH_VFMV_S_F, MASK_VFMV_S_F) +DECLARE_INSN(vfmerge_vfm, MATCH_VFMERGE_VFM, MASK_VFMERGE_VFM) +DECLARE_INSN(vfmv_v_f, MATCH_VFMV_V_F, MASK_VFMV_V_F) +DECLARE_INSN(vmfeq_vf, MATCH_VMFEQ_VF, MASK_VMFEQ_VF) +DECLARE_INSN(vmfle_vf, MATCH_VMFLE_VF, MASK_VMFLE_VF) +DECLARE_INSN(vmflt_vf, MATCH_VMFLT_VF, MASK_VMFLT_VF) +DECLARE_INSN(vmfne_vf, MATCH_VMFNE_VF, MASK_VMFNE_VF) +DECLARE_INSN(vmfgt_vf, MATCH_VMFGT_VF, MASK_VMFGT_VF) +DECLARE_INSN(vmfge_vf, MATCH_VMFGE_VF, MASK_VMFGE_VF) +DECLARE_INSN(vfdiv_vf, MATCH_VFDIV_VF, MASK_VFDIV_VF) +DECLARE_INSN(vfrdiv_vf, MATCH_VFRDIV_VF, MASK_VFRDIV_VF) +DECLARE_INSN(vfmul_vf, MATCH_VFMUL_VF, MASK_VFMUL_VF) +DECLARE_INSN(vfrsub_vf, MATCH_VFRSUB_VF, MASK_VFRSUB_VF) +DECLARE_INSN(vfmadd_vf, MATCH_VFMADD_VF, MASK_VFMADD_VF) +DECLARE_INSN(vfnmadd_vf, MATCH_VFNMADD_VF, MASK_VFNMADD_VF) +DECLARE_INSN(vfmsub_vf, MATCH_VFMSUB_VF, MASK_VFMSUB_VF) +DECLARE_INSN(vfnmsub_vf, MATCH_VFNMSUB_VF, MASK_VFNMSUB_VF) +DECLARE_INSN(vfmacc_vf, MATCH_VFMACC_VF, MASK_VFMACC_VF) +DECLARE_INSN(vfnmacc_vf, MATCH_VFNMACC_VF, MASK_VFNMACC_VF) +DECLARE_INSN(vfmsac_vf, MATCH_VFMSAC_VF, MASK_VFMSAC_VF) +DECLARE_INSN(vfnmsac_vf, MATCH_VFNMSAC_VF, MASK_VFNMSAC_VF) +DECLARE_INSN(vfwadd_vf, MATCH_VFWADD_VF, MASK_VFWADD_VF) +DECLARE_INSN(vfwsub_vf, MATCH_VFWSUB_VF, MASK_VFWSUB_VF) +DECLARE_INSN(vfwadd_wf, MATCH_VFWADD_WF, MASK_VFWADD_WF) +DECLARE_INSN(vfwsub_wf, MATCH_VFWSUB_WF, MASK_VFWSUB_WF) +DECLARE_INSN(vfwmul_vf, MATCH_VFWMUL_VF, MASK_VFWMUL_VF) +DECLARE_INSN(vfwmacc_vf, MATCH_VFWMACC_VF, MASK_VFWMACC_VF) +DECLARE_INSN(vfwnmacc_vf, MATCH_VFWNMACC_VF, MASK_VFWNMACC_VF) +DECLARE_INSN(vfwmsac_vf, MATCH_VFWMSAC_VF, MASK_VFWMSAC_VF) +DECLARE_INSN(vfwnmsac_vf, MATCH_VFWNMSAC_VF, MASK_VFWNMSAC_VF) +DECLARE_INSN(vfadd_vv, MATCH_VFADD_VV, MASK_VFADD_VV) +DECLARE_INSN(vfredsum_vs, MATCH_VFREDSUM_VS, MASK_VFREDSUM_VS) +DECLARE_INSN(vfsub_vv, MATCH_VFSUB_VV, MASK_VFSUB_VV) +DECLARE_INSN(vfredosum_vs, MATCH_VFREDOSUM_VS, MASK_VFREDOSUM_VS) +DECLARE_INSN(vfmin_vv, MATCH_VFMIN_VV, MASK_VFMIN_VV) +DECLARE_INSN(vfredmin_vs, MATCH_VFREDMIN_VS, MASK_VFREDMIN_VS) +DECLARE_INSN(vfmax_vv, MATCH_VFMAX_VV, MASK_VFMAX_VV) +DECLARE_INSN(vfredmax_vs, MATCH_VFREDMAX_VS, MASK_VFREDMAX_VS) +DECLARE_INSN(vfsgnj_vv, MATCH_VFSGNJ_VV, MASK_VFSGNJ_VV) +DECLARE_INSN(vfsgnjn_vv, MATCH_VFSGNJN_VV, MASK_VFSGNJN_VV) +DECLARE_INSN(vfsgnjx_vv, MATCH_VFSGNJX_VV, MASK_VFSGNJX_VV) +DECLARE_INSN(vfmv_f_s, MATCH_VFMV_F_S, MASK_VFMV_F_S) +DECLARE_INSN(vmfeq_vv, MATCH_VMFEQ_VV, MASK_VMFEQ_VV) +DECLARE_INSN(vmfle_vv, MATCH_VMFLE_VV, MASK_VMFLE_VV) +DECLARE_INSN(vmflt_vv, MATCH_VMFLT_VV, MASK_VMFLT_VV) +DECLARE_INSN(vmfne_vv, MATCH_VMFNE_VV, MASK_VMFNE_VV) +DECLARE_INSN(vfdiv_vv, MATCH_VFDIV_VV, MASK_VFDIV_VV) +DECLARE_INSN(vfmul_vv, MATCH_VFMUL_VV, MASK_VFMUL_VV) +DECLARE_INSN(vfmadd_vv, MATCH_VFMADD_VV, MASK_VFMADD_VV) +DECLARE_INSN(vfnmadd_vv, MATCH_VFNMADD_VV, MASK_VFNMADD_VV) +DECLARE_INSN(vfmsub_vv, MATCH_VFMSUB_VV, MASK_VFMSUB_VV) +DECLARE_INSN(vfnmsub_vv, MATCH_VFNMSUB_VV, MASK_VFNMSUB_VV) +DECLARE_INSN(vfmacc_vv, MATCH_VFMACC_VV, MASK_VFMACC_VV) +DECLARE_INSN(vfnmacc_vv, MATCH_VFNMACC_VV, MASK_VFNMACC_VV) +DECLARE_INSN(vfmsac_vv, MATCH_VFMSAC_VV, MASK_VFMSAC_VV) +DECLARE_INSN(vfnmsac_vv, MATCH_VFNMSAC_VV, MASK_VFNMSAC_VV) +DECLARE_INSN(vfcvt_xu_f_v, MATCH_VFCVT_XU_F_V, MASK_VFCVT_XU_F_V) +DECLARE_INSN(vfcvt_x_f_v, MATCH_VFCVT_X_F_V, MASK_VFCVT_X_F_V) +DECLARE_INSN(vfcvt_f_xu_v, MATCH_VFCVT_F_XU_V, MASK_VFCVT_F_XU_V) +DECLARE_INSN(vfcvt_f_x_v, MATCH_VFCVT_F_X_V, MASK_VFCVT_F_X_V) +DECLARE_INSN(vfcvt_rtz_xu_f_v, MATCH_VFCVT_RTZ_XU_F_V, MASK_VFCVT_RTZ_XU_F_V) +DECLARE_INSN(vfcvt_rtz_x_f_v, MATCH_VFCVT_RTZ_X_F_V, MASK_VFCVT_RTZ_X_F_V) +DECLARE_INSN(vfwcvt_xu_f_v, MATCH_VFWCVT_XU_F_V, MASK_VFWCVT_XU_F_V) +DECLARE_INSN(vfwcvt_x_f_v, MATCH_VFWCVT_X_F_V, MASK_VFWCVT_X_F_V) +DECLARE_INSN(vfwcvt_f_xu_v, MATCH_VFWCVT_F_XU_V, MASK_VFWCVT_F_XU_V) +DECLARE_INSN(vfwcvt_f_x_v, MATCH_VFWCVT_F_X_V, MASK_VFWCVT_F_X_V) +DECLARE_INSN(vfwcvt_f_f_v, MATCH_VFWCVT_F_F_V, MASK_VFWCVT_F_F_V) +DECLARE_INSN(vfwcvt_rtz_xu_f_v, MATCH_VFWCVT_RTZ_XU_F_V, MASK_VFWCVT_RTZ_XU_F_V) +DECLARE_INSN(vfwcvt_rtz_x_f_v, MATCH_VFWCVT_RTZ_X_F_V, MASK_VFWCVT_RTZ_X_F_V) +DECLARE_INSN(vfncvt_xu_f_w, MATCH_VFNCVT_XU_F_W, MASK_VFNCVT_XU_F_W) +DECLARE_INSN(vfncvt_x_f_w, MATCH_VFNCVT_X_F_W, MASK_VFNCVT_X_F_W) +DECLARE_INSN(vfncvt_f_xu_w, MATCH_VFNCVT_F_XU_W, MASK_VFNCVT_F_XU_W) +DECLARE_INSN(vfncvt_f_x_w, MATCH_VFNCVT_F_X_W, MASK_VFNCVT_F_X_W) +DECLARE_INSN(vfncvt_f_f_w, MATCH_VFNCVT_F_F_W, MASK_VFNCVT_F_F_W) +DECLARE_INSN(vfncvt_rod_f_f_w, MATCH_VFNCVT_ROD_F_F_W, MASK_VFNCVT_ROD_F_F_W) +DECLARE_INSN(vfncvt_rtz_xu_f_w, MATCH_VFNCVT_RTZ_XU_F_W, MASK_VFNCVT_RTZ_XU_F_W) +DECLARE_INSN(vfncvt_rtz_x_f_w, MATCH_VFNCVT_RTZ_X_F_W, MASK_VFNCVT_RTZ_X_F_W) +DECLARE_INSN(vfsqrt_v, MATCH_VFSQRT_V, MASK_VFSQRT_V) +DECLARE_INSN(vfclass_v, MATCH_VFCLASS_V, MASK_VFCLASS_V) +DECLARE_INSN(vfwadd_vv, MATCH_VFWADD_VV, MASK_VFWADD_VV) +DECLARE_INSN(vfwredsum_vs, MATCH_VFWREDSUM_VS, MASK_VFWREDSUM_VS) +DECLARE_INSN(vfwsub_vv, MATCH_VFWSUB_VV, MASK_VFWSUB_VV) +DECLARE_INSN(vfwredosum_vs, MATCH_VFWREDOSUM_VS, MASK_VFWREDOSUM_VS) +DECLARE_INSN(vfwadd_wv, MATCH_VFWADD_WV, MASK_VFWADD_WV) +DECLARE_INSN(vfwsub_wv, MATCH_VFWSUB_WV, MASK_VFWSUB_WV) +DECLARE_INSN(vfwmul_vv, MATCH_VFWMUL_VV, MASK_VFWMUL_VV) +DECLARE_INSN(vfdot_vv, MATCH_VFDOT_VV, MASK_VFDOT_VV) +DECLARE_INSN(vfwmacc_vv, MATCH_VFWMACC_VV, MASK_VFWMACC_VV) +DECLARE_INSN(vfwnmacc_vv, MATCH_VFWNMACC_VV, MASK_VFWNMACC_VV) +DECLARE_INSN(vfwmsac_vv, MATCH_VFWMSAC_VV, MASK_VFWMSAC_VV) +DECLARE_INSN(vfwnmsac_vv, MATCH_VFWNMSAC_VV, MASK_VFWNMSAC_VV) +DECLARE_INSN(vadd_vx, MATCH_VADD_VX, MASK_VADD_VX) +DECLARE_INSN(vsub_vx, MATCH_VSUB_VX, MASK_VSUB_VX) +DECLARE_INSN(vrsub_vx, MATCH_VRSUB_VX, MASK_VRSUB_VX) +DECLARE_INSN(vminu_vx, MATCH_VMINU_VX, MASK_VMINU_VX) +DECLARE_INSN(vmin_vx, MATCH_VMIN_VX, MASK_VMIN_VX) +DECLARE_INSN(vmaxu_vx, MATCH_VMAXU_VX, MASK_VMAXU_VX) +DECLARE_INSN(vmax_vx, MATCH_VMAX_VX, MASK_VMAX_VX) +DECLARE_INSN(vand_vx, MATCH_VAND_VX, MASK_VAND_VX) +DECLARE_INSN(vor_vx, MATCH_VOR_VX, MASK_VOR_VX) +DECLARE_INSN(vxor_vx, MATCH_VXOR_VX, MASK_VXOR_VX) +DECLARE_INSN(vrgather_vx, MATCH_VRGATHER_VX, MASK_VRGATHER_VX) +DECLARE_INSN(vslideup_vx, MATCH_VSLIDEUP_VX, MASK_VSLIDEUP_VX) +DECLARE_INSN(vslidedown_vx, MATCH_VSLIDEDOWN_VX, MASK_VSLIDEDOWN_VX) +DECLARE_INSN(vadc_vxm, MATCH_VADC_VXM, MASK_VADC_VXM) +DECLARE_INSN(vmadc_vxm, MATCH_VMADC_VXM, MASK_VMADC_VXM) +DECLARE_INSN(vsbc_vxm, MATCH_VSBC_VXM, MASK_VSBC_VXM) +DECLARE_INSN(vmsbc_vxm, MATCH_VMSBC_VXM, MASK_VMSBC_VXM) +DECLARE_INSN(vmerge_vxm, MATCH_VMERGE_VXM, MASK_VMERGE_VXM) +DECLARE_INSN(vmv_v_x, MATCH_VMV_V_X, MASK_VMV_V_X) +DECLARE_INSN(vmseq_vx, MATCH_VMSEQ_VX, MASK_VMSEQ_VX) +DECLARE_INSN(vmsne_vx, MATCH_VMSNE_VX, MASK_VMSNE_VX) +DECLARE_INSN(vmsltu_vx, MATCH_VMSLTU_VX, MASK_VMSLTU_VX) +DECLARE_INSN(vmslt_vx, MATCH_VMSLT_VX, MASK_VMSLT_VX) +DECLARE_INSN(vmsleu_vx, MATCH_VMSLEU_VX, MASK_VMSLEU_VX) +DECLARE_INSN(vmsle_vx, MATCH_VMSLE_VX, MASK_VMSLE_VX) +DECLARE_INSN(vmsgtu_vx, MATCH_VMSGTU_VX, MASK_VMSGTU_VX) +DECLARE_INSN(vmsgt_vx, MATCH_VMSGT_VX, MASK_VMSGT_VX) +DECLARE_INSN(vsaddu_vx, MATCH_VSADDU_VX, MASK_VSADDU_VX) +DECLARE_INSN(vsadd_vx, MATCH_VSADD_VX, MASK_VSADD_VX) +DECLARE_INSN(vssubu_vx, MATCH_VSSUBU_VX, MASK_VSSUBU_VX) +DECLARE_INSN(vssub_vx, MATCH_VSSUB_VX, MASK_VSSUB_VX) +DECLARE_INSN(vsll_vx, MATCH_VSLL_VX, MASK_VSLL_VX) +DECLARE_INSN(vsmul_vx, MATCH_VSMUL_VX, MASK_VSMUL_VX) +DECLARE_INSN(vsrl_vx, MATCH_VSRL_VX, MASK_VSRL_VX) +DECLARE_INSN(vsra_vx, MATCH_VSRA_VX, MASK_VSRA_VX) +DECLARE_INSN(vssrl_vx, MATCH_VSSRL_VX, MASK_VSSRL_VX) +DECLARE_INSN(vssra_vx, MATCH_VSSRA_VX, MASK_VSSRA_VX) +DECLARE_INSN(vnsrl_wx, MATCH_VNSRL_WX, MASK_VNSRL_WX) +DECLARE_INSN(vnsra_wx, MATCH_VNSRA_WX, MASK_VNSRA_WX) +DECLARE_INSN(vnclipu_wx, MATCH_VNCLIPU_WX, MASK_VNCLIPU_WX) +DECLARE_INSN(vnclip_wx, MATCH_VNCLIP_WX, MASK_VNCLIP_WX) +DECLARE_INSN(vqmaccu_vx, MATCH_VQMACCU_VX, MASK_VQMACCU_VX) +DECLARE_INSN(vqmacc_vx, MATCH_VQMACC_VX, MASK_VQMACC_VX) +DECLARE_INSN(vqmaccus_vx, MATCH_VQMACCUS_VX, MASK_VQMACCUS_VX) +DECLARE_INSN(vqmaccsu_vx, MATCH_VQMACCSU_VX, MASK_VQMACCSU_VX) +DECLARE_INSN(vadd_vv, MATCH_VADD_VV, MASK_VADD_VV) +DECLARE_INSN(vsub_vv, MATCH_VSUB_VV, MASK_VSUB_VV) +DECLARE_INSN(vminu_vv, MATCH_VMINU_VV, MASK_VMINU_VV) +DECLARE_INSN(vmin_vv, MATCH_VMIN_VV, MASK_VMIN_VV) +DECLARE_INSN(vmaxu_vv, MATCH_VMAXU_VV, MASK_VMAXU_VV) +DECLARE_INSN(vmax_vv, MATCH_VMAX_VV, MASK_VMAX_VV) +DECLARE_INSN(vand_vv, MATCH_VAND_VV, MASK_VAND_VV) +DECLARE_INSN(vor_vv, MATCH_VOR_VV, MASK_VOR_VV) +DECLARE_INSN(vxor_vv, MATCH_VXOR_VV, MASK_VXOR_VV) +DECLARE_INSN(vrgather_vv, MATCH_VRGATHER_VV, MASK_VRGATHER_VV) +DECLARE_INSN(vadc_vvm, MATCH_VADC_VVM, MASK_VADC_VVM) +DECLARE_INSN(vmadc_vvm, MATCH_VMADC_VVM, MASK_VMADC_VVM) +DECLARE_INSN(vsbc_vvm, MATCH_VSBC_VVM, MASK_VSBC_VVM) +DECLARE_INSN(vmsbc_vvm, MATCH_VMSBC_VVM, MASK_VMSBC_VVM) +DECLARE_INSN(vmerge_vvm, MATCH_VMERGE_VVM, MASK_VMERGE_VVM) +DECLARE_INSN(vmv_v_v, MATCH_VMV_V_V, MASK_VMV_V_V) +DECLARE_INSN(vmseq_vv, MATCH_VMSEQ_VV, MASK_VMSEQ_VV) +DECLARE_INSN(vmsne_vv, MATCH_VMSNE_VV, MASK_VMSNE_VV) +DECLARE_INSN(vmsltu_vv, MATCH_VMSLTU_VV, MASK_VMSLTU_VV) +DECLARE_INSN(vmslt_vv, MATCH_VMSLT_VV, MASK_VMSLT_VV) +DECLARE_INSN(vmsleu_vv, MATCH_VMSLEU_VV, MASK_VMSLEU_VV) +DECLARE_INSN(vmsle_vv, MATCH_VMSLE_VV, MASK_VMSLE_VV) +DECLARE_INSN(vsaddu_vv, MATCH_VSADDU_VV, MASK_VSADDU_VV) +DECLARE_INSN(vsadd_vv, MATCH_VSADD_VV, MASK_VSADD_VV) +DECLARE_INSN(vssubu_vv, MATCH_VSSUBU_VV, MASK_VSSUBU_VV) +DECLARE_INSN(vssub_vv, MATCH_VSSUB_VV, MASK_VSSUB_VV) +DECLARE_INSN(vsll_vv, MATCH_VSLL_VV, MASK_VSLL_VV) +DECLARE_INSN(vsmul_vv, MATCH_VSMUL_VV, MASK_VSMUL_VV) +DECLARE_INSN(vsrl_vv, MATCH_VSRL_VV, MASK_VSRL_VV) +DECLARE_INSN(vsra_vv, MATCH_VSRA_VV, MASK_VSRA_VV) +DECLARE_INSN(vssrl_vv, MATCH_VSSRL_VV, MASK_VSSRL_VV) +DECLARE_INSN(vssra_vv, MATCH_VSSRA_VV, MASK_VSSRA_VV) +DECLARE_INSN(vnsrl_wv, MATCH_VNSRL_WV, MASK_VNSRL_WV) +DECLARE_INSN(vnsra_wv, MATCH_VNSRA_WV, MASK_VNSRA_WV) +DECLARE_INSN(vnclipu_wv, MATCH_VNCLIPU_WV, MASK_VNCLIPU_WV) +DECLARE_INSN(vnclip_wv, MATCH_VNCLIP_WV, MASK_VNCLIP_WV) +DECLARE_INSN(vwredsumu_vs, MATCH_VWREDSUMU_VS, MASK_VWREDSUMU_VS) +DECLARE_INSN(vwredsum_vs, MATCH_VWREDSUM_VS, MASK_VWREDSUM_VS) +DECLARE_INSN(vdotu_vv, MATCH_VDOTU_VV, MASK_VDOTU_VV) +DECLARE_INSN(vdot_vv, MATCH_VDOT_VV, MASK_VDOT_VV) +DECLARE_INSN(vqmaccu_vv, MATCH_VQMACCU_VV, MASK_VQMACCU_VV) +DECLARE_INSN(vqmacc_vv, MATCH_VQMACC_VV, MASK_VQMACC_VV) +DECLARE_INSN(vqmaccsu_vv, MATCH_VQMACCSU_VV, MASK_VQMACCSU_VV) +DECLARE_INSN(vadd_vi, MATCH_VADD_VI, MASK_VADD_VI) +DECLARE_INSN(vrsub_vi, MATCH_VRSUB_VI, MASK_VRSUB_VI) +DECLARE_INSN(vand_vi, MATCH_VAND_VI, MASK_VAND_VI) +DECLARE_INSN(vor_vi, MATCH_VOR_VI, MASK_VOR_VI) +DECLARE_INSN(vxor_vi, MATCH_VXOR_VI, MASK_VXOR_VI) +DECLARE_INSN(vrgather_vi, MATCH_VRGATHER_VI, MASK_VRGATHER_VI) +DECLARE_INSN(vslideup_vi, MATCH_VSLIDEUP_VI, MASK_VSLIDEUP_VI) +DECLARE_INSN(vslidedown_vi, MATCH_VSLIDEDOWN_VI, MASK_VSLIDEDOWN_VI) +DECLARE_INSN(vadc_vim, MATCH_VADC_VIM, MASK_VADC_VIM) +DECLARE_INSN(vmadc_vim, MATCH_VMADC_VIM, MASK_VMADC_VIM) +DECLARE_INSN(vmerge_vim, MATCH_VMERGE_VIM, MASK_VMERGE_VIM) +DECLARE_INSN(vmv_v_i, MATCH_VMV_V_I, MASK_VMV_V_I) +DECLARE_INSN(vmseq_vi, MATCH_VMSEQ_VI, MASK_VMSEQ_VI) +DECLARE_INSN(vmsne_vi, MATCH_VMSNE_VI, MASK_VMSNE_VI) +DECLARE_INSN(vmsleu_vi, MATCH_VMSLEU_VI, MASK_VMSLEU_VI) +DECLARE_INSN(vmsle_vi, MATCH_VMSLE_VI, MASK_VMSLE_VI) +DECLARE_INSN(vmsgtu_vi, MATCH_VMSGTU_VI, MASK_VMSGTU_VI) +DECLARE_INSN(vmsgt_vi, MATCH_VMSGT_VI, MASK_VMSGT_VI) +DECLARE_INSN(vsaddu_vi, MATCH_VSADDU_VI, MASK_VSADDU_VI) +DECLARE_INSN(vsadd_vi, MATCH_VSADD_VI, MASK_VSADD_VI) +DECLARE_INSN(vsll_vi, MATCH_VSLL_VI, MASK_VSLL_VI) +DECLARE_INSN(vmv1r_v, MATCH_VMV1R_V, MASK_VMV1R_V) +DECLARE_INSN(vmv2r_v, MATCH_VMV2R_V, MASK_VMV2R_V) +DECLARE_INSN(vmv4r_v, MATCH_VMV4R_V, MASK_VMV4R_V) +DECLARE_INSN(vmv8r_v, MATCH_VMV8R_V, MASK_VMV8R_V) +DECLARE_INSN(vsrl_vi, MATCH_VSRL_VI, MASK_VSRL_VI) +DECLARE_INSN(vsra_vi, MATCH_VSRA_VI, MASK_VSRA_VI) +DECLARE_INSN(vssrl_vi, MATCH_VSSRL_VI, MASK_VSSRL_VI) +DECLARE_INSN(vssra_vi, MATCH_VSSRA_VI, MASK_VSSRA_VI) +DECLARE_INSN(vnsrl_wi, MATCH_VNSRL_WI, MASK_VNSRL_WI) +DECLARE_INSN(vnsra_wi, MATCH_VNSRA_WI, MASK_VNSRA_WI) +DECLARE_INSN(vnclipu_wi, MATCH_VNCLIPU_WI, MASK_VNCLIPU_WI) +DECLARE_INSN(vnclip_wi, MATCH_VNCLIP_WI, MASK_VNCLIP_WI) +DECLARE_INSN(vredsum_vs, MATCH_VREDSUM_VS, MASK_VREDSUM_VS) +DECLARE_INSN(vredand_vs, MATCH_VREDAND_VS, MASK_VREDAND_VS) +DECLARE_INSN(vredor_vs, MATCH_VREDOR_VS, MASK_VREDOR_VS) +DECLARE_INSN(vredxor_vs, MATCH_VREDXOR_VS, MASK_VREDXOR_VS) +DECLARE_INSN(vredminu_vs, MATCH_VREDMINU_VS, MASK_VREDMINU_VS) +DECLARE_INSN(vredmin_vs, MATCH_VREDMIN_VS, MASK_VREDMIN_VS) +DECLARE_INSN(vredmaxu_vs, MATCH_VREDMAXU_VS, MASK_VREDMAXU_VS) +DECLARE_INSN(vredmax_vs, MATCH_VREDMAX_VS, MASK_VREDMAX_VS) +DECLARE_INSN(vaaddu_vv, MATCH_VAADDU_VV, MASK_VAADDU_VV) +DECLARE_INSN(vaadd_vv, MATCH_VAADD_VV, MASK_VAADD_VV) +DECLARE_INSN(vasubu_vv, MATCH_VASUBU_VV, MASK_VASUBU_VV) +DECLARE_INSN(vasub_vv, MATCH_VASUB_VV, MASK_VASUB_VV) +DECLARE_INSN(vmv_x_s, MATCH_VMV_X_S, MASK_VMV_X_S) +DECLARE_INSN(vcompress_vm, MATCH_VCOMPRESS_VM, MASK_VCOMPRESS_VM) +DECLARE_INSN(vmandnot_mm, MATCH_VMANDNOT_MM, MASK_VMANDNOT_MM) +DECLARE_INSN(vmand_mm, MATCH_VMAND_MM, MASK_VMAND_MM) +DECLARE_INSN(vmor_mm, MATCH_VMOR_MM, MASK_VMOR_MM) +DECLARE_INSN(vmxor_mm, MATCH_VMXOR_MM, MASK_VMXOR_MM) +DECLARE_INSN(vmornot_mm, MATCH_VMORNOT_MM, MASK_VMORNOT_MM) +DECLARE_INSN(vmnand_mm, MATCH_VMNAND_MM, MASK_VMNAND_MM) +DECLARE_INSN(vmnor_mm, MATCH_VMNOR_MM, MASK_VMNOR_MM) +DECLARE_INSN(vmxnor_mm, MATCH_VMXNOR_MM, MASK_VMXNOR_MM) +DECLARE_INSN(vmsbf_m, MATCH_VMSBF_M, MASK_VMSBF_M) +DECLARE_INSN(vmsof_m, MATCH_VMSOF_M, MASK_VMSOF_M) +DECLARE_INSN(vmsif_m, MATCH_VMSIF_M, MASK_VMSIF_M) +DECLARE_INSN(viota_m, MATCH_VIOTA_M, MASK_VIOTA_M) +DECLARE_INSN(vid_v, MATCH_VID_V, MASK_VID_V) +DECLARE_INSN(vpopc_m, MATCH_VPOPC_M, MASK_VPOPC_M) +DECLARE_INSN(vfirst_m, MATCH_VFIRST_M, MASK_VFIRST_M) +DECLARE_INSN(vdivu_vv, MATCH_VDIVU_VV, MASK_VDIVU_VV) +DECLARE_INSN(vdiv_vv, MATCH_VDIV_VV, MASK_VDIV_VV) +DECLARE_INSN(vremu_vv, MATCH_VREMU_VV, MASK_VREMU_VV) +DECLARE_INSN(vrem_vv, MATCH_VREM_VV, MASK_VREM_VV) +DECLARE_INSN(vmulhu_vv, MATCH_VMULHU_VV, MASK_VMULHU_VV) +DECLARE_INSN(vmul_vv, MATCH_VMUL_VV, MASK_VMUL_VV) +DECLARE_INSN(vmulhsu_vv, MATCH_VMULHSU_VV, MASK_VMULHSU_VV) +DECLARE_INSN(vmulh_vv, MATCH_VMULH_VV, MASK_VMULH_VV) +DECLARE_INSN(vmadd_vv, MATCH_VMADD_VV, MASK_VMADD_VV) +DECLARE_INSN(vnmsub_vv, MATCH_VNMSUB_VV, MASK_VNMSUB_VV) +DECLARE_INSN(vmacc_vv, MATCH_VMACC_VV, MASK_VMACC_VV) +DECLARE_INSN(vnmsac_vv, MATCH_VNMSAC_VV, MASK_VNMSAC_VV) +DECLARE_INSN(vwaddu_vv, MATCH_VWADDU_VV, MASK_VWADDU_VV) +DECLARE_INSN(vwadd_vv, MATCH_VWADD_VV, MASK_VWADD_VV) +DECLARE_INSN(vwsubu_vv, MATCH_VWSUBU_VV, MASK_VWSUBU_VV) +DECLARE_INSN(vwsub_vv, MATCH_VWSUB_VV, MASK_VWSUB_VV) +DECLARE_INSN(vwaddu_wv, MATCH_VWADDU_WV, MASK_VWADDU_WV) +DECLARE_INSN(vwadd_wv, MATCH_VWADD_WV, MASK_VWADD_WV) +DECLARE_INSN(vwsubu_wv, MATCH_VWSUBU_WV, MASK_VWSUBU_WV) +DECLARE_INSN(vwsub_wv, MATCH_VWSUB_WV, MASK_VWSUB_WV) +DECLARE_INSN(vwmulu_vv, MATCH_VWMULU_VV, MASK_VWMULU_VV) +DECLARE_INSN(vwmulsu_vv, MATCH_VWMULSU_VV, MASK_VWMULSU_VV) +DECLARE_INSN(vwmul_vv, MATCH_VWMUL_VV, MASK_VWMUL_VV) +DECLARE_INSN(vwmaccu_vv, MATCH_VWMACCU_VV, MASK_VWMACCU_VV) +DECLARE_INSN(vwmacc_vv, MATCH_VWMACC_VV, MASK_VWMACC_VV) +DECLARE_INSN(vwmaccsu_vv, MATCH_VWMACCSU_VV, MASK_VWMACCSU_VV) +DECLARE_INSN(vaaddu_vx, MATCH_VAADDU_VX, MASK_VAADDU_VX) +DECLARE_INSN(vaadd_vx, MATCH_VAADD_VX, MASK_VAADD_VX) +DECLARE_INSN(vasubu_vx, MATCH_VASUBU_VX, MASK_VASUBU_VX) +DECLARE_INSN(vasub_vx, MATCH_VASUB_VX, MASK_VASUB_VX) +DECLARE_INSN(vmv_s_x, MATCH_VMV_S_X, MASK_VMV_S_X) +DECLARE_INSN(vslide1up_vx, MATCH_VSLIDE1UP_VX, MASK_VSLIDE1UP_VX) +DECLARE_INSN(vslide1down_vx, MATCH_VSLIDE1DOWN_VX, MASK_VSLIDE1DOWN_VX) +DECLARE_INSN(vdivu_vx, MATCH_VDIVU_VX, MASK_VDIVU_VX) +DECLARE_INSN(vdiv_vx, MATCH_VDIV_VX, MASK_VDIV_VX) +DECLARE_INSN(vremu_vx, MATCH_VREMU_VX, MASK_VREMU_VX) +DECLARE_INSN(vrem_vx, MATCH_VREM_VX, MASK_VREM_VX) +DECLARE_INSN(vmulhu_vx, MATCH_VMULHU_VX, MASK_VMULHU_VX) +DECLARE_INSN(vmul_vx, MATCH_VMUL_VX, MASK_VMUL_VX) +DECLARE_INSN(vmulhsu_vx, MATCH_VMULHSU_VX, MASK_VMULHSU_VX) +DECLARE_INSN(vmulh_vx, MATCH_VMULH_VX, MASK_VMULH_VX) +DECLARE_INSN(vmadd_vx, MATCH_VMADD_VX, MASK_VMADD_VX) +DECLARE_INSN(vnmsub_vx, MATCH_VNMSUB_VX, MASK_VNMSUB_VX) +DECLARE_INSN(vmacc_vx, MATCH_VMACC_VX, MASK_VMACC_VX) +DECLARE_INSN(vnmsac_vx, MATCH_VNMSAC_VX, MASK_VNMSAC_VX) +DECLARE_INSN(vwaddu_vx, MATCH_VWADDU_VX, MASK_VWADDU_VX) +DECLARE_INSN(vwadd_vx, MATCH_VWADD_VX, MASK_VWADD_VX) +DECLARE_INSN(vwsubu_vx, MATCH_VWSUBU_VX, MASK_VWSUBU_VX) +DECLARE_INSN(vwsub_vx, MATCH_VWSUB_VX, MASK_VWSUB_VX) +DECLARE_INSN(vwaddu_wx, MATCH_VWADDU_WX, MASK_VWADDU_WX) +DECLARE_INSN(vwadd_wx, MATCH_VWADD_WX, MASK_VWADD_WX) +DECLARE_INSN(vwsubu_wx, MATCH_VWSUBU_WX, MASK_VWSUBU_WX) +DECLARE_INSN(vwsub_wx, MATCH_VWSUB_WX, MASK_VWSUB_WX) +DECLARE_INSN(vwmulu_vx, MATCH_VWMULU_VX, MASK_VWMULU_VX) +DECLARE_INSN(vwmulsu_vx, MATCH_VWMULSU_VX, MASK_VWMULSU_VX) +DECLARE_INSN(vwmul_vx, MATCH_VWMUL_VX, MASK_VWMUL_VX) +DECLARE_INSN(vwmaccu_vx, MATCH_VWMACCU_VX, MASK_VWMACCU_VX) +DECLARE_INSN(vwmacc_vx, MATCH_VWMACC_VX, MASK_VWMACC_VX) +DECLARE_INSN(vwmaccus_vx, MATCH_VWMACCUS_VX, MASK_VWMACCUS_VX) +DECLARE_INSN(vwmaccsu_vx, MATCH_VWMACCSU_VX, MASK_VWMACCSU_VX) +DECLARE_INSN(vamoswapw_v, MATCH_VAMOSWAPW_V, MASK_VAMOSWAPW_V) +DECLARE_INSN(vamoaddw_v, MATCH_VAMOADDW_V, MASK_VAMOADDW_V) +DECLARE_INSN(vamoxorw_v, MATCH_VAMOXORW_V, MASK_VAMOXORW_V) +DECLARE_INSN(vamoandw_v, MATCH_VAMOANDW_V, MASK_VAMOANDW_V) +DECLARE_INSN(vamoorw_v, MATCH_VAMOORW_V, MASK_VAMOORW_V) +DECLARE_INSN(vamominw_v, MATCH_VAMOMINW_V, MASK_VAMOMINW_V) +DECLARE_INSN(vamomaxw_v, MATCH_VAMOMAXW_V, MASK_VAMOMAXW_V) +DECLARE_INSN(vamominuw_v, MATCH_VAMOMINUW_V, MASK_VAMOMINUW_V) +DECLARE_INSN(vamomaxuw_v, MATCH_VAMOMAXUW_V, MASK_VAMOMAXUW_V) +DECLARE_INSN(vamoswape_v, MATCH_VAMOSWAPE_V, MASK_VAMOSWAPE_V) +DECLARE_INSN(vamoadde_v, MATCH_VAMOADDE_V, MASK_VAMOADDE_V) +DECLARE_INSN(vamoxore_v, MATCH_VAMOXORE_V, MASK_VAMOXORE_V) +DECLARE_INSN(vamoande_v, MATCH_VAMOANDE_V, MASK_VAMOANDE_V) +DECLARE_INSN(vamoore_v, MATCH_VAMOORE_V, MASK_VAMOORE_V) +DECLARE_INSN(vamomine_v, MATCH_VAMOMINE_V, MASK_VAMOMINE_V) +DECLARE_INSN(vamomaxe_v, MATCH_VAMOMAXE_V, MASK_VAMOMAXE_V) +DECLARE_INSN(vamominue_v, MATCH_VAMOMINUE_V, MASK_VAMOMINUE_V) +DECLARE_INSN(vamomaxue_v, MATCH_VAMOMAXUE_V, MASK_VAMOMAXUE_V) +DECLARE_INSN(vmvnfr_v, MATCH_VMVNFR_V, MASK_VMVNFR_V) +#endif +#ifdef DECLARE_CSR +DECLARE_CSR(fflags, CSR_FFLAGS) +DECLARE_CSR(frm, CSR_FRM) +DECLARE_CSR(fcsr, CSR_FCSR) +DECLARE_CSR(ustatus, CSR_USTATUS) +DECLARE_CSR(uie, CSR_UIE) +DECLARE_CSR(utvec, CSR_UTVEC) +DECLARE_CSR(vstart, CSR_VSTART) +DECLARE_CSR(vxsat, CSR_VXSAT) +DECLARE_CSR(vxrm, CSR_VXRM) +DECLARE_CSR(vcsr, CSR_VCSR) +DECLARE_CSR(uscratch, CSR_USCRATCH) +DECLARE_CSR(uepc, CSR_UEPC) +DECLARE_CSR(ucause, CSR_UCAUSE) +DECLARE_CSR(utval, CSR_UTVAL) +DECLARE_CSR(uip, CSR_UIP) +DECLARE_CSR(cycle, CSR_CYCLE) +DECLARE_CSR(time, CSR_TIME) +DECLARE_CSR(instret, CSR_INSTRET) +DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3) +DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4) +DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5) +DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6) +DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7) +DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8) +DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9) +DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10) +DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11) +DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12) +DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13) +DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14) +DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15) +DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16) +DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17) +DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18) +DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19) +DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20) +DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21) +DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22) +DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23) +DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24) +DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25) +DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26) +DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27) +DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28) +DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29) +DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30) +DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31) +DECLARE_CSR(vl, CSR_VL) +DECLARE_CSR(vtype, CSR_VTYPE) +DECLARE_CSR(vlenb, CSR_VLENB) +DECLARE_CSR(sstatus, CSR_SSTATUS) +DECLARE_CSR(sedeleg, CSR_SEDELEG) +DECLARE_CSR(sideleg, CSR_SIDELEG) +DECLARE_CSR(sie, CSR_SIE) +DECLARE_CSR(stvec, CSR_STVEC) +DECLARE_CSR(scounteren, CSR_SCOUNTEREN) +DECLARE_CSR(sscratch, CSR_SSCRATCH) +DECLARE_CSR(sepc, CSR_SEPC) +DECLARE_CSR(scause, CSR_SCAUSE) +DECLARE_CSR(stval, CSR_STVAL) +DECLARE_CSR(sip, CSR_SIP) +DECLARE_CSR(satp, CSR_SATP) +DECLARE_CSR(vsstatus, CSR_VSSTATUS) +DECLARE_CSR(vsie, CSR_VSIE) +DECLARE_CSR(vstvec, CSR_VSTVEC) +DECLARE_CSR(vsscratch, CSR_VSSCRATCH) +DECLARE_CSR(vsepc, CSR_VSEPC) +DECLARE_CSR(vscause, CSR_VSCAUSE) +DECLARE_CSR(vstval, CSR_VSTVAL) +DECLARE_CSR(vsip, CSR_VSIP) +DECLARE_CSR(vsatp, CSR_VSATP) +DECLARE_CSR(hstatus, CSR_HSTATUS) +DECLARE_CSR(hedeleg, CSR_HEDELEG) +DECLARE_CSR(hideleg, CSR_HIDELEG) +DECLARE_CSR(hie, CSR_HIE) +DECLARE_CSR(htimedelta, CSR_HTIMEDELTA) +DECLARE_CSR(hcounteren, CSR_HCOUNTEREN) +DECLARE_CSR(hgeie, CSR_HGEIE) +DECLARE_CSR(htval, CSR_HTVAL) +DECLARE_CSR(hip, CSR_HIP) +DECLARE_CSR(hvip, CSR_HVIP) +DECLARE_CSR(htinst, CSR_HTINST) +DECLARE_CSR(hgatp, CSR_HGATP) +DECLARE_CSR(hgeip, CSR_HGEIP) +DECLARE_CSR(utvt, CSR_UTVT) +DECLARE_CSR(unxti, CSR_UNXTI) +DECLARE_CSR(uintstatus, CSR_UINTSTATUS) +DECLARE_CSR(uscratchcsw, CSR_USCRATCHCSW) +DECLARE_CSR(uscratchcswl, CSR_USCRATCHCSWL) +DECLARE_CSR(stvt, CSR_STVT) +DECLARE_CSR(snxti, CSR_SNXTI) +DECLARE_CSR(sintstatus, CSR_SINTSTATUS) +DECLARE_CSR(sscratchcsw, CSR_SSCRATCHCSW) +DECLARE_CSR(sscratchcswl, CSR_SSCRATCHCSWL) +DECLARE_CSR(mtvt, CSR_MTVT) +DECLARE_CSR(mnxti, CSR_MNXTI) +DECLARE_CSR(mintstatus, CSR_MINTSTATUS) +DECLARE_CSR(mscratchcsw, CSR_MSCRATCHCSW) +DECLARE_CSR(mscratchcswl, CSR_MSCRATCHCSWL) +DECLARE_CSR(mstatus, CSR_MSTATUS) +DECLARE_CSR(misa, CSR_MISA) +DECLARE_CSR(medeleg, CSR_MEDELEG) +DECLARE_CSR(mideleg, CSR_MIDELEG) +DECLARE_CSR(mie, CSR_MIE) +DECLARE_CSR(mtvec, CSR_MTVEC) +DECLARE_CSR(mcounteren, CSR_MCOUNTEREN) +DECLARE_CSR(mcountinhibit, CSR_MCOUNTINHIBIT) +DECLARE_CSR(mscratch, CSR_MSCRATCH) +DECLARE_CSR(mepc, CSR_MEPC) +DECLARE_CSR(mcause, CSR_MCAUSE) +DECLARE_CSR(mtval, CSR_MTVAL) +DECLARE_CSR(mip, CSR_MIP) +DECLARE_CSR(mtinst, CSR_MTINST) +DECLARE_CSR(mtval2, CSR_MTVAL2) +DECLARE_CSR(pmpcfg0, CSR_PMPCFG0) +DECLARE_CSR(pmpcfg1, CSR_PMPCFG1) +DECLARE_CSR(pmpcfg2, CSR_PMPCFG2) +DECLARE_CSR(pmpcfg3, CSR_PMPCFG3) +DECLARE_CSR(pmpaddr0, CSR_PMPADDR0) +DECLARE_CSR(pmpaddr1, CSR_PMPADDR1) +DECLARE_CSR(pmpaddr2, CSR_PMPADDR2) +DECLARE_CSR(pmpaddr3, CSR_PMPADDR3) +DECLARE_CSR(pmpaddr4, CSR_PMPADDR4) +DECLARE_CSR(pmpaddr5, CSR_PMPADDR5) +DECLARE_CSR(pmpaddr6, CSR_PMPADDR6) +DECLARE_CSR(pmpaddr7, CSR_PMPADDR7) +DECLARE_CSR(pmpaddr8, CSR_PMPADDR8) +DECLARE_CSR(pmpaddr9, CSR_PMPADDR9) +DECLARE_CSR(pmpaddr10, CSR_PMPADDR10) +DECLARE_CSR(pmpaddr11, CSR_PMPADDR11) +DECLARE_CSR(pmpaddr12, CSR_PMPADDR12) +DECLARE_CSR(pmpaddr13, CSR_PMPADDR13) +DECLARE_CSR(pmpaddr14, CSR_PMPADDR14) +DECLARE_CSR(pmpaddr15, CSR_PMPADDR15) +DECLARE_CSR(tselect, CSR_TSELECT) +DECLARE_CSR(tdata1, CSR_TDATA1) +DECLARE_CSR(tdata2, CSR_TDATA2) +DECLARE_CSR(tdata3, CSR_TDATA3) +DECLARE_CSR(dcsr, CSR_DCSR) +DECLARE_CSR(dpc, CSR_DPC) +DECLARE_CSR(dscratch0, CSR_DSCRATCH0) +DECLARE_CSR(dscratch1, CSR_DSCRATCH1) +DECLARE_CSR(mcycle, CSR_MCYCLE) +DECLARE_CSR(minstret, CSR_MINSTRET) +DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3) +DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4) +DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5) +DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6) +DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7) +DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8) +DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9) +DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10) +DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11) +DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12) +DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13) +DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14) +DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15) +DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16) +DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17) +DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18) +DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19) +DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20) +DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21) +DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22) +DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23) +DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24) +DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25) +DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26) +DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27) +DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28) +DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29) +DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30) +DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31) +DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3) +DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4) +DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5) +DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6) +DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7) +DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8) +DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9) +DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10) +DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11) +DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12) +DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13) +DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14) +DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15) +DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16) +DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17) +DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18) +DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19) +DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20) +DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21) +DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22) +DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23) +DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24) +DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25) +DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26) +DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27) +DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28) +DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29) +DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30) +DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31) +DECLARE_CSR(mvendorid, CSR_MVENDORID) +DECLARE_CSR(marchid, CSR_MARCHID) +DECLARE_CSR(mimpid, CSR_MIMPID) +DECLARE_CSR(mhartid, CSR_MHARTID) +DECLARE_CSR(htimedeltah, CSR_HTIMEDELTAH) +DECLARE_CSR(cycleh, CSR_CYCLEH) +DECLARE_CSR(timeh, CSR_TIMEH) +DECLARE_CSR(instreth, CSR_INSTRETH) +DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H) +DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H) +DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H) +DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H) +DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H) +DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H) +DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H) +DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H) +DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H) +DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H) +DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H) +DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H) +DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H) +DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H) +DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H) +DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H) +DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H) +DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H) +DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H) +DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H) +DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H) +DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H) +DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H) +DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H) +DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H) +DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H) +DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H) +DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H) +DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H) +DECLARE_CSR(mstatush, CSR_MSTATUSH) +DECLARE_CSR(mcycleh, CSR_MCYCLEH) +DECLARE_CSR(minstreth, CSR_MINSTRETH) +DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H) +DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H) +DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H) +DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H) +DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H) +DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H) +DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H) +DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H) +DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H) +DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H) +DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H) +DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H) +DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H) +DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H) +DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H) +DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H) +DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H) +DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H) +DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H) +DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H) +DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H) +DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H) +DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H) +DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H) +DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H) +DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H) +DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H) +DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H) +DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H) +#endif +#ifdef DECLARE_CAUSE +DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH) +DECLARE_CAUSE("fetch access", CAUSE_FETCH_ACCESS) +DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION) +DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT) +DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD) +DECLARE_CAUSE("load access", CAUSE_LOAD_ACCESS) +DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE) +DECLARE_CAUSE("store access", CAUSE_STORE_ACCESS) +DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL) +DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL) +DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL) +DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL) +DECLARE_CAUSE("fetch page fault", CAUSE_FETCH_PAGE_FAULT) +DECLARE_CAUSE("load page fault", CAUSE_LOAD_PAGE_FAULT) +DECLARE_CAUSE("store page fault", CAUSE_STORE_PAGE_FAULT) +#endif diff --git a/verif/tests/custom/hello_world/custom_test_template.S b/verif/tests/custom/hello_world/custom_test_template.S new file mode 100644 index 0000000000..9636395a49 --- /dev/null +++ b/verif/tests/custom/hello_world/custom_test_template.S @@ -0,0 +1,33 @@ +# Copyright 2022 Thales DIS design services SAS +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Original Author: Guillaume Chauvon (guillaume.chauvon@thalesgroup.fr) + +#***************************************************************************** +# custom_test_template.S +#----------------------------------------------------------------------------- +# + + .globl main +main: +# core of the test +# (example of) final self-check test + li a0, 0xCAFE; + li a1, 0xCAFE; + xor a2, a0, a1; + beqz a2, pass; + +fail: + # Failure post-processing (messages, ecall setup etc.) + li a0, 0x0; + jal exit; + +pass: + # Success post-processing (messages, ecall setup etc.) + li a0, 0x0; + jal exit; + diff --git a/verif/tests/custom/hello_world/hello_world.c b/verif/tests/custom/hello_world/hello_world.c new file mode 100644 index 0000000000..d59802c237 --- /dev/null +++ b/verif/tests/custom/hello_world/hello_world.c @@ -0,0 +1,32 @@ +/* +** +** Copyright 2020 OpenHW Group +** +** Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +** you may not use this file except in compliance with the License. +** You may obtain a copy of the License at +** +** https://solderpad.org/licenses/ +** +** Unless required by applicable law or agreed to in writing, software +** distributed under the License is distributed on an "AS IS" BASIS, +** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +** See the License for the specific language governing permissions and +** limitations under the License. +** +*/ + +#include <stdint.h> +#include <stdio.h> + +int main(int argc, char* arg[]) { + + printf("%d: Hello World !", 0); + + int a = 0; + for (int i = 0; i < 5; i++) + { + a += i; + } + return 0; +} diff --git a/verif/tests/custom/isacov/branch_to_zero.S b/verif/tests/custom/isacov/branch_to_zero.S new file mode 100644 index 0000000000..a3568be9cc --- /dev/null +++ b/verif/tests/custom/isacov/branch_to_zero.S @@ -0,0 +1,66 @@ +# Copyright 2023 Thales DIS design services SAS +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Original Author: Ayoub JALALI (ayoub.jalali@external.thalesgroup.com) + +#***************************************************************************** +# branch.S +#----------------------------------------------------------------------------- +# + + .globl main +main: +# core of the test + blt zero, t3, main # BRANCH TO ZERO + csrrs s8, 0x340, a5 + li a1, 0x1 + li t0, 0x0 + beq a1, t0, main + bne t0, t0, main + blt t0, t0, main + bltu a1, a1, main + add t5, a1 ,s6 + bge zero, t5, main + bgeu zero, t5, main + c.beqz s0, main + add s1, zero ,zero + c.bnez s1, main + add s1, zero ,zero +branch: + c.bnez s1, branch +branch1: + c.beqz s0, branch1 +branch2: + bge zero, t5, branch2 +branch3: + bltu a1, a1, branch3 +branch4: + beq zero, a1, branch4 +branch5: + bne t5, t5, branch5 + addi a0, a0, 22 + srl a4, a5, a0 + csrrsi t4, 0x340, 0 + sltiu t4, s9, 236 + remu t4, tp, a1 + c.andi a5, -1 + lui zero, 0 +# (example of) final self-check test + li a0, 0xCAFE; + li a1, 0xCAFE; + xor a2, a0, a1; + beqz a2, pass; + +fail: + # Failure post-processing (messages, ecall setup etc.) + li a0, 0x0; + jal exit; + +pass: + # Success post-processing (messages, ecall setup etc.) + li a0, 0x0; + jal exit; diff --git a/verif/tests/custom/isacov/csr_test.S b/verif/tests/custom/isacov/csr_test.S new file mode 100644 index 0000000000..ac9fbdcc07 --- /dev/null +++ b/verif/tests/custom/isacov/csr_test.S @@ -0,0 +1,73 @@ +# Copyright 2023 Thales DIS France SAS +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# + +#include "csrrw_test.S" +#include "csrrwi_test.S" +#include "csrcs_test.S" +#include "csrcsi_test.S" + +.globl main +main: + #Start CSR tests: all tests + #Handle exceptions + la x6, exception_handler + csrw mtvec, x6 ## Load the address of the exception handler into MTVEC + csrw 0x341, x0 ## Writing Zero to MEPC CSR + csrw 0x342, x0 ## Writing Zero to MCAUSE CSR + #End Handle exceptions + call csrrw + call csrrwi + call csrcs + call csrcsi + + #End of csr test + j csr_pass + +csr_pass: + li x1, 0xBEEFBEEF + li x1, 0 + slli x1, x1, 1 + addi x1, x1, 1 + sw x1, tohost, x30 + self_loop: j self_loop + +csr_fail: + li x1, 0xBADBAD + li x1, 1 + slli x1, x1, 1 + addi x1, x1, 1 + sw x1, tohost, x30 + self_loop_2: j self_loop_2 + +exception_handler: + #addi x10, x10, 1 ##Increment number of exceptions + li x1, 0xABCDEF + csrr x3, 0x300 + srli x3, x3, 11 + andi x3, x3, 0b11 + li x8, 3 + li x9, 1 + beq x3, x8, machine_exception_handler + #beqz x3, user_exception_handler + #beq x3, x9, supervisor_exception_handler + j csr_fail + +machine_exception_handler: + csrr x6, 0x300 + csrr x30, 0x341 ## Reading MEPC CSR which holds exception origin Address + csrr x31, 0x342 ## Reading MCAUSE CSR which holds the cause of exception + li x2 ,2 ## MCAUSE == Illegal instruction + beq x31, x2, goto_next_instr ## Checking if exception is illegal instruction + j csr_fail + +goto_next_instr: + csrw 0x342, 0 ## Reseting MCAUSE value to 0 before handling new exception + beq x30, x0, csr_fail + addi x7, x30, 4 + jr x7 ## Jump to latest instruction: MEPC + 4 Address location + j csr_fail diff --git a/verif/tests/custom/isacov/csrcs_test.S b/verif/tests/custom/isacov/csrcs_test.S new file mode 100644 index 0000000000..ce07ffb886 --- /dev/null +++ b/verif/tests/custom/isacov/csrcs_test.S @@ -0,0 +1,684 @@ +# Copyright 2023 Thales DIS France SAS +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# + +csrcs: + #Start CSR tests: Write/Read all registers using Clear/Set instructions + #User ignored registers: MHPMEVENT3 ,MHPMEVENT4 ,MHPMEVENT5 ,MHPMEVENT6 ,MHPMEVENT7 ,MHPMEVENT8 ,MHPMEVENT9 ,MHPMEVENT10 ,MHPMEVENT11 ,MHPMEVENT12 ,MHPMEVENT13 ,MHPMEVENT14 ,MHPMEVENT15 ,MHPMEVENT16 ,MHPMEVENT17 ,MHPMEVENT18 ,MHPMEVENT19 ,MHPMEVENT20 ,MHPMEVENT21 ,MHPMEVENT22 ,MHPMEVENT23 ,MHPMEVENT24 ,MHPMEVENT25 ,MHPMEVENT26 ,MHPMEVENT27 ,MHPMEVENT28 ,MHPMEVENT29 ,MHPMEVENT30 ,MHPMEVENT31 ,PMPCFG0 ,PMPCFG1 ,PMPCFG2 ,PMPCFG3 ,PMPADDR0 ,PMPADDR1 ,PMPADDR2 ,PMPADDR3 ,PMPADDR4 ,PMPADDR5 ,PMPADDR6 ,PMPADDR7 ,PMPADDR8 ,PMPADDR9 ,PMPADDR10 ,PMPADDR11 ,PMPADDR12 ,PMPADDR13 ,PMPADDR14 ,PMPADDR15 ,ICACHE ,MHPMCOUNTER3 ,MHPMCOUNTER4 ,MHPMCOUNTER5 ,MHPMCOUNTER6 ,MHPMCOUNTER7 ,MHPMCOUNTER8 ,MHPMCOUNTER9 ,MHPMCOUNTER10 ,MHPMCOUNTER11 ,MHPMCOUNTER12 ,MHPMCOUNTER13 ,MHPMCOUNTER14 ,MHPMCOUNTER15 ,MHPMCOUNTER16 ,MHPMCOUNTER17 ,MHPMCOUNTER18 ,MHPMCOUNTER19 ,MHPMCOUNTER20 ,MHPMCOUNTER21 ,MHPMCOUNTER22 ,MHPMCOUNTER23 ,MHPMCOUNTER24 ,MHPMCOUNTER25 ,MHPMCOUNTER26 ,MHPMCOUNTER27 ,MHPMCOUNTER28 ,MHPMCOUNTER29 ,MHPMCOUNTER30 ,MHPMCOUNTER31 ,MHPMCOUNTERH3 ,MHPMCOUNTERH4 ,MHPMCOUNTERH5 ,MHPMCOUNTERH6 ,MHPMCOUNTERH7 ,MHPMCOUNTERH8 ,MHPMCOUNTERH9 ,MHPMCOUNTERH10 ,MHPMCOUNTERH11 ,MHPMCOUNTERH12 ,MHPMCOUNTERH13 ,MHPMCOUNTERH14 ,MHPMCOUNTERH15 ,MHPMCOUNTERH16 ,MHPMCOUNTERH17 ,MHPMCOUNTERH18 ,MHPMCOUNTERH19 ,MHPMCOUNTERH20 ,MHPMCOUNTERH21 ,MHPMCOUNTERH22 ,MHPMCOUNTERH23 ,MHPMCOUNTERH24 ,MHPMCOUNTERH25 ,MHPMCOUNTERH26 ,MHPMCOUNTERH27 ,MHPMCOUNTERH28 ,MHPMCOUNTERH29 ,MHPMCOUNTERH30 ,MHPMCOUNTERH31 , + ########################## + #MSTATUS testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h18} + ########################## + #MSTATUS Write clear/set value 0x1f + li x3, 0x7ffe19e0 + csrrc x14, 0x300, x3 + li x3, 0x1f + csrrs x14, 0x300, x3 + + #MSTATUS read value, expected 0xa + csrr x14, 0x300 + + #MSTATUS Write clear/set value 0x0 + li x3, 0x7ffe19ff + csrrc x14, 0x300, x3 + li x3, 0x0 + csrrs x14, 0x300, x3 + + #MSTATUS read value, expected 0x0 + csrr x14, 0x300 + + #MSTATUS Write clear/set value 0x15 + li x3, 0x7ffe19ea + csrrc x14, 0x300, x3 + li x3, 0x15 + csrrs x14, 0x300, x3 + + #MSTATUS read value, expected 0x0 + csrr x14, 0x300 + + #MSTATUS Write clear/set value 0xa + li x3, 0x7ffe19f5 + csrrc x14, 0x300, x3 + li x3, 0xa + csrrs x14, 0x300, x3 + + #MSTATUS read value, expected 0xa + csrr x14, 0x300 + + #MSTATUS Write clear/set value 0x18 + li x3, 0x7ffe19e7 + csrrc x14, 0x300, x3 + li x3, 0x18 + csrrs x14, 0x300, x3 + + #MSTATUS read value, expected 0x8 + csrr x14, 0x300 + + ########################## + #MTVEC testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h4} + ########################## + #MTVEC Write clear/set value 0x1f + li x3, 0xffffffe0 + csrrc x14, 0x305, x3 + li x3, 0x1f + csrrs x14, 0x305, x3 + + #MTVEC read value, expected 0x1f + csrr x14, 0x305 + + #MTVEC Write clear/set value 0x0 + li x3, 0xffffffff + csrrc x14, 0x305, x3 + li x3, 0x0 + csrrs x14, 0x305, x3 + + #MTVEC read value, expected 0x0 + csrr x14, 0x305 + + #MTVEC Write clear/set value 0x15 + li x3, 0xffffffea + csrrc x14, 0x305, x3 + li x3, 0x15 + csrrs x14, 0x305, x3 + + #MTVEC read value, expected 0x15 + csrr x14, 0x305 + + #MTVEC Write clear/set value 0xa + li x3, 0xfffffff5 + csrrc x14, 0x305, x3 + li x3, 0xa + csrrs x14, 0x305, x3 + + #MTVEC read value, expected 0xa + csrr x14, 0x305 + + #MTVEC Write clear/set value 0x4 + li x3, 0xfffffffb + csrrc x14, 0x305, x3 + li x3, 0x4 + csrrs x14, 0x305, x3 + + #MTVEC read value, expected 0x4 + csrr x14, 0x305 + + ########################## + #MSTATUSH testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h1} + ########################## + #MSTATUSH Write clear/set value 0x1f + li x3, 0xffffffe0 + csrrc x14, 0x310, x3 + li x3, 0x1f + csrrs x14, 0x310, x3 + + #MSTATUSH read value, expected 0x10 + csrr x14, 0x310 + + #MSTATUSH Write clear/set value 0x0 + li x3, 0xffffffff + csrrc x14, 0x310, x3 + li x3, 0x0 + csrrs x14, 0x310, x3 + + #MSTATUSH read value, expected 0x0 + csrr x14, 0x310 + + #MSTATUSH Write clear/set value 0x15 + li x3, 0xffffffea + csrrc x14, 0x310, x3 + li x3, 0x15 + csrrs x14, 0x310, x3 + + #MSTATUSH read value, expected 0x10 + csrr x14, 0x310 + + #MSTATUSH Write clear/set value 0xa + li x3, 0xfffffff5 + csrrc x14, 0x310, x3 + li x3, 0xa + csrrs x14, 0x310, x3 + + #MSTATUSH read value, expected 0x0 + csrr x14, 0x310 + + #MSTATUSH Write clear/set value 0x1 + li x3, 0xfffffffe + csrrc x14, 0x310, x3 + li x3, 0x1 + csrrs x14, 0x310, x3 + + #MSTATUSH read value, expected 0x0 + csrr x14, 0x310 + + ########################## + #MCYCLEH testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h2} + ########################## + #MCYCLEH Write clear/set value 0x1f + li x3, 0xffffffe0 + csrrc x14, 0xb80, x3 + li x3, 0x1f + csrrs x14, 0xb80, x3 + + #MCYCLEH read value, expected 0x1f + csrr x14, 0xb80 + + #MCYCLEH Write clear/set value 0x0 + li x3, 0xffffffff + csrrc x14, 0xb80, x3 + li x3, 0x0 + csrrs x14, 0xb80, x3 + + #MCYCLEH read value, expected 0x0 + csrr x14, 0xb80 + + #MCYCLEH Write clear/set value 0x15 + li x3, 0xffffffea + csrrc x14, 0xb80, x3 + li x3, 0x15 + csrrs x14, 0xb80, x3 + + #MCYCLEH read value, expected 0x15 + csrr x14, 0xb80 + + #MCYCLEH Write clear/set value 0xa + li x3, 0xfffffff5 + csrrc x14, 0xb80, x3 + li x3, 0xa + csrrs x14, 0xb80, x3 + + #MCYCLEH read value, expected 0xa + csrr x14, 0xb80 + + #MCYCLEH Write clear/set value 0x2 + li x3, 0xfffffffd + csrrc x14, 0xb80, x3 + li x3, 0x2 + csrrs x14, 0xb80, x3 + + #MCYCLEH read value, expected 0x2 + csrr x14, 0xb80 + + ########################## + #MSCRATCH testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'hd} + ########################## + #MSCRATCH Write clear/set value 0x1f + li x3, 0xffffffe0 + csrrc x14, 0x340, x3 + li x3, 0x1f + csrrs x14, 0x340, x3 + + #MSCRATCH read value, expected 0x1f + csrr x14, 0x340 + + #MSCRATCH Write clear/set value 0x0 + li x3, 0xffffffff + csrrc x14, 0x340, x3 + li x3, 0x0 + csrrs x14, 0x340, x3 + + #MSCRATCH read value, expected 0x0 + csrr x14, 0x340 + + #MSCRATCH Write clear/set value 0x15 + li x3, 0xffffffea + csrrc x14, 0x340, x3 + li x3, 0x15 + csrrs x14, 0x340, x3 + + #MSCRATCH read value, expected 0x15 + csrr x14, 0x340 + + #MSCRATCH Write clear/set value 0xa + li x3, 0xfffffff5 + csrrc x14, 0x340, x3 + li x3, 0xa + csrrs x14, 0x340, x3 + + #MSCRATCH read value, expected 0xa + csrr x14, 0x340 + + #MSCRATCH Write clear/set value 0xd + li x3, 0xfffffff2 + csrrc x14, 0x340, x3 + li x3, 0xd + csrrs x14, 0x340, x3 + + #MSCRATCH read value, expected 0xd + csrr x14, 0x340 + + ########################## + #MINSTRET testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h15} + ########################## + #MINSTRET Write clear/set value 0x1f + li x3, 0xffffffe0 + csrrc x14, 0xb02, x3 + li x3, 0x1f + csrrs x14, 0xb02, x3 + + #MINSTRET read value, expected 0x1f + csrr x14, 0xb02 + + #MINSTRET Write clear/set value 0x0 + li x3, 0xffffffff + csrrc x14, 0xb02, x3 + li x3, 0x0 + csrrs x14, 0xb02, x3 + + #MINSTRET read value, expected 0x0 + csrr x14, 0xb02 + + #MINSTRET Write clear/set value 0x15 + li x3, 0xffffffea + csrrc x14, 0xb02, x3 + li x3, 0x15 + csrrs x14, 0xb02, x3 + + #MINSTRET read value, expected 0x15 + csrr x14, 0xb02 + + #MINSTRET Write clear/set value 0xa + li x3, 0xfffffff5 + csrrc x14, 0xb02, x3 + li x3, 0xa + csrrs x14, 0xb02, x3 + + #MINSTRET read value, expected 0xa + csrr x14, 0xb02 + + #MINSTRET Write clear/set value 0x15 + li x3, 0xffffffea + csrrc x14, 0xb02, x3 + li x3, 0x15 + csrrs x14, 0xb02, x3 + + #MINSTRET read value, expected 0x15 + csrr x14, 0xb02 + + ########################## + #MIP testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h4} + ########################## + #MIP Write clear/set value 0x1f + li x3, 0xfffff760 + csrrc x14, 0x344, x3 + li x3, 0x1f + csrrs x14, 0x344, x3 + + #MIP read value, expected 0x1b + csrr x14, 0x344 + + #MIP Write clear/set value 0x0 + li x3, 0xfffff777 + csrrc x14, 0x344, x3 + li x3, 0x0 + csrrs x14, 0x344, x3 + + #MIP read value, expected 0x0 + csrr x14, 0x344 + + #MIP Write clear/set value 0x15 + li x3, 0xfffff762 + csrrc x14, 0x344, x3 + li x3, 0x15 + csrrs x14, 0x344, x3 + + #MIP read value, expected 0x11 + csrr x14, 0x344 + + #MIP Write clear/set value 0xa + li x3, 0xfffff775 + csrrc x14, 0x344, x3 + li x3, 0xa + csrrs x14, 0x344, x3 + + #MIP read value, expected 0xa + csrr x14, 0x344 + + #MIP Write clear/set value 0x4 + li x3, 0xfffff773 + csrrc x14, 0x344, x3 + li x3, 0x4 + csrrs x14, 0x344, x3 + + #MIP read value, expected 0x0 + csrr x14, 0x344 + + ########################## + #MEPC testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h1b} + ########################## + #MEPC Write clear/set value 0x1f + li x3, 0xffffffe0 + csrrc x14, 0x341, x3 + li x3, 0x1f + csrrs x14, 0x341, x3 + + #MEPC read value, expected 0x1f + csrr x14, 0x341 + + #MEPC Write clear/set value 0x0 + li x3, 0xffffffff + csrrc x14, 0x341, x3 + li x3, 0x0 + csrrs x14, 0x341, x3 + + #MEPC read value, expected 0x0 + csrr x14, 0x341 + + #MEPC Write clear/set value 0x15 + li x3, 0xffffffea + csrrc x14, 0x341, x3 + li x3, 0x15 + csrrs x14, 0x341, x3 + + #MEPC read value, expected 0x15 + csrr x14, 0x341 + + #MEPC Write clear/set value 0xa + li x3, 0xfffffff5 + csrrc x14, 0x341, x3 + li x3, 0xa + csrrs x14, 0x341, x3 + + #MEPC read value, expected 0xa + csrr x14, 0x341 + + #MEPC Write clear/set value 0x1b + li x3, 0xffffffe4 + csrrc x14, 0x341, x3 + li x3, 0x1b + csrrs x14, 0x341, x3 + + #MEPC read value, expected 0x1b + csrr x14, 0x341 + + ########################## + #MCYCLE testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h1d} + ########################## + #MCYCLE Write clear/set value 0x1f + li x3, 0xffffffe0 + csrrc x14, 0xb00, x3 + li x3, 0x1f + csrrs x14, 0xb00, x3 + + #MCYCLE read value, expected 0x1f + csrr x14, 0xb00 + + #MCYCLE Write clear/set value 0x0 + li x3, 0xffffffff + csrrc x14, 0xb00, x3 + li x3, 0x0 + csrrs x14, 0xb00, x3 + + #MCYCLE read value, expected 0x0 + csrr x14, 0xb00 + + #MCYCLE Write clear/set value 0x15 + li x3, 0xffffffea + csrrc x14, 0xb00, x3 + li x3, 0x15 + csrrs x14, 0xb00, x3 + + #MCYCLE read value, expected 0x15 + csrr x14, 0xb00 + + #MCYCLE Write clear/set value 0xa + li x3, 0xfffffff5 + csrrc x14, 0xb00, x3 + li x3, 0xa + csrrs x14, 0xb00, x3 + + #MCYCLE read value, expected 0xa + csrr x14, 0xb00 + + #MCYCLE Write clear/set value 0x1d + li x3, 0xffffffe2 + csrrc x14, 0xb00, x3 + li x3, 0x1d + csrrs x14, 0xb00, x3 + + #MCYCLE read value, expected 0x1d + csrr x14, 0xb00 + + ########################## + #MINSTRETH testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h1a} + ########################## + #MINSTRETH Write clear/set value 0x1f + li x3, 0xffffffe0 + csrrc x14, 0xb82, x3 + li x3, 0x1f + csrrs x14, 0xb82, x3 + + #MINSTRETH read value, expected 0x1f + csrr x14, 0xb82 + + #MINSTRETH Write clear/set value 0x0 + li x3, 0xffffffff + csrrc x14, 0xb82, x3 + li x3, 0x0 + csrrs x14, 0xb82, x3 + + #MINSTRETH read value, expected 0x0 + csrr x14, 0xb82 + + #MINSTRETH Write clear/set value 0x15 + li x3, 0xffffffea + csrrc x14, 0xb82, x3 + li x3, 0x15 + csrrs x14, 0xb82, x3 + + #MINSTRETH read value, expected 0x15 + csrr x14, 0xb82 + + #MINSTRETH Write clear/set value 0xa + li x3, 0xfffffff5 + csrrc x14, 0xb82, x3 + li x3, 0xa + csrrs x14, 0xb82, x3 + + #MINSTRETH read value, expected 0xa + csrr x14, 0xb82 + + #MINSTRETH Write clear/set value 0x1a + li x3, 0xffffffe5 + csrrc x14, 0xb82, x3 + li x3, 0x1a + csrrs x14, 0xb82, x3 + + #MINSTRETH read value, expected 0x1a + csrr x14, 0xb82 + + ########################## + #MCAUSE testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h16} + ########################## + #MCAUSE Write clear/set value 0x1f + li x3, 0xffffffe0 + csrrc x14, 0x342, x3 + li x3, 0x1f + csrrs x14, 0x342, x3 + + #MCAUSE read value, expected 0x1f + csrr x14, 0x342 + + #MCAUSE Write clear/set value 0x0 + li x3, 0xffffffff + csrrc x14, 0x342, x3 + li x3, 0x0 + csrrs x14, 0x342, x3 + + #MCAUSE read value, expected 0x0 + csrr x14, 0x342 + + #MCAUSE Write clear/set value 0x15 + li x3, 0xffffffea + csrrc x14, 0x342, x3 + li x3, 0x15 + csrrs x14, 0x342, x3 + + #MCAUSE read value, expected 0x15 + csrr x14, 0x342 + + #MCAUSE Write clear/set value 0xa + li x3, 0xfffffff5 + csrrc x14, 0x342, x3 + li x3, 0xa + csrrs x14, 0x342, x3 + + #MCAUSE read value, expected 0xa + csrr x14, 0x342 + + #MCAUSE Write clear/set value 0x16 + li x3, 0xffffffe9 + csrrc x14, 0x342, x3 + li x3, 0x16 + csrrs x14, 0x342, x3 + + #MCAUSE read value, expected 0x16 + csrr x14, 0x342 + + ########################## + #MISA testing W/R values '{'h1b, 'h4, 'h15, 'ha, 'h8} + ########################## + #MISA Write clear/set value 0x1b + li x3, 0xffffffe4 + csrrc x14, 0x301, x3 + li x3, 0x1b + csrrs x14, 0x301, x3 + + #MISA read value, expected 0x1b + csrr x14, 0x301 + + #MISA Write clear/set value 0x4 + li x3, 0xfffffffb + csrrc x14, 0x301, x3 + li x3, 0x4 + csrrs x14, 0x301, x3 + + #MISA read value, expected 0x4 + csrr x14, 0x301 + + #MISA Write clear/set value 0x15 + li x3, 0xffffffea + csrrc x14, 0x301, x3 + li x3, 0x15 + csrrs x14, 0x301, x3 + + #MISA read value, expected 0x15 + csrr x14, 0x301 + + #MISA Write clear/set value 0xa + li x3, 0xfffffff5 + csrrc x14, 0x301, x3 + li x3, 0xa + csrrs x14, 0x301, x3 + + #MISA read value, expected 0xa + csrr x14, 0x301 + + #MISA Write clear/set value 0x8 + li x3, 0xfffffff7 + csrrc x14, 0x301, x3 + li x3, 0x8 + csrrs x14, 0x301, x3 + + #MISA read value, expected 0x8 + csrr x14, 0x301 + + ########################## + #MTVAL testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h1e} + ########################## + #MTVAL Write clear/set value 0x1f + li x3, 0xffffffe0 + csrrc x14, 0x343, x3 + li x3, 0x1f + csrrs x14, 0x343, x3 + + #MTVAL read value, expected 0x1f + csrr x14, 0x343 + + #MTVAL Write clear/set value 0x0 + li x3, 0xffffffff + csrrc x14, 0x343, x3 + li x3, 0x0 + csrrs x14, 0x343, x3 + + #MTVAL read value, expected 0x0 + csrr x14, 0x343 + + #MTVAL Write clear/set value 0x15 + li x3, 0xffffffea + csrrc x14, 0x343, x3 + li x3, 0x15 + csrrs x14, 0x343, x3 + + #MTVAL read value, expected 0x15 + csrr x14, 0x343 + + #MTVAL Write clear/set value 0xa + li x3, 0xfffffff5 + csrrc x14, 0x343, x3 + li x3, 0xa + csrrs x14, 0x343, x3 + + #MTVAL read value, expected 0xa + csrr x14, 0x343 + + #MTVAL Write clear/set value 0x1e + li x3, 0xffffffe1 + csrrc x14, 0x343, x3 + li x3, 0x1e + csrrs x14, 0x343, x3 + + #MTVAL read value, expected 0x1e + csrr x14, 0x343 + + ########################## + #MIE testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h1a} + ########################## + #MIE Write clear/set value 0x1f + li x3, 0xffffffe0 + csrrc x14, 0x304, x3 + li x3, 0x1f + csrrs x14, 0x304, x3 + + #MIE read value, expected 0x1b + csrr x14, 0x304 + + #MIE Write clear/set value 0x0 + li x3, 0xffffffff + csrrc x14, 0x304, x3 + li x3, 0x0 + csrrs x14, 0x304, x3 + + #MIE read value, expected 0x0 + csrr x14, 0x304 + + #MIE Write clear/set value 0x15 + li x3, 0xffffffea + csrrc x14, 0x304, x3 + li x3, 0x15 + csrrs x14, 0x304, x3 + + #MIE read value, expected 0x11 + csrr x14, 0x304 + + #MIE Write clear/set value 0xa + li x3, 0xfffffff5 + csrrc x14, 0x304, x3 + li x3, 0xa + csrrs x14, 0x304, x3 + + #MIE read value, expected 0xa + csrr x14, 0x304 + + #MIE Write clear/set value 0x1a + li x3, 0xffffffe5 + csrrc x14, 0x304, x3 + li x3, 0x1a + csrrs x14, 0x304, x3 + + #MIE read value, expected 0x1a + csrr x14, 0x304 + + ret diff --git a/verif/tests/custom/isacov/csrcsi_test.S b/verif/tests/custom/isacov/csrcsi_test.S new file mode 100644 index 0000000000..9943837096 --- /dev/null +++ b/verif/tests/custom/isacov/csrcsi_test.S @@ -0,0 +1,544 @@ +# Copyright 2023 Thales DIS France SAS +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# + +csrcsi: + #Start CSR tests: Write/Read all registers using Clear/Set immediate instructions + #User ignored registers: MHPMEVENT3 ,MHPMEVENT4 ,MHPMEVENT5 ,MHPMEVENT6 ,MHPMEVENT7 ,MHPMEVENT8 ,MHPMEVENT9 ,MHPMEVENT10 ,MHPMEVENT11 ,MHPMEVENT12 ,MHPMEVENT13 ,MHPMEVENT14 ,MHPMEVENT15 ,MHPMEVENT16 ,MHPMEVENT17 ,MHPMEVENT18 ,MHPMEVENT19 ,MHPMEVENT20 ,MHPMEVENT21 ,MHPMEVENT22 ,MHPMEVENT23 ,MHPMEVENT24 ,MHPMEVENT25 ,MHPMEVENT26 ,MHPMEVENT27 ,MHPMEVENT28 ,MHPMEVENT29 ,MHPMEVENT30 ,MHPMEVENT31 ,PMPCFG0 ,PMPCFG1 ,PMPCFG2 ,PMPCFG3 ,PMPADDR0 ,PMPADDR1 ,PMPADDR2 ,PMPADDR3 ,PMPADDR4 ,PMPADDR5 ,PMPADDR6 ,PMPADDR7 ,PMPADDR8 ,PMPADDR9 ,PMPADDR10 ,PMPADDR11 ,PMPADDR12 ,PMPADDR13 ,PMPADDR14 ,PMPADDR15 ,ICACHE ,MHPMCOUNTER3 ,MHPMCOUNTER4 ,MHPMCOUNTER5 ,MHPMCOUNTER6 ,MHPMCOUNTER7 ,MHPMCOUNTER8 ,MHPMCOUNTER9 ,MHPMCOUNTER10 ,MHPMCOUNTER11 ,MHPMCOUNTER12 ,MHPMCOUNTER13 ,MHPMCOUNTER14 ,MHPMCOUNTER15 ,MHPMCOUNTER16 ,MHPMCOUNTER17 ,MHPMCOUNTER18 ,MHPMCOUNTER19 ,MHPMCOUNTER20 ,MHPMCOUNTER21 ,MHPMCOUNTER22 ,MHPMCOUNTER23 ,MHPMCOUNTER24 ,MHPMCOUNTER25 ,MHPMCOUNTER26 ,MHPMCOUNTER27 ,MHPMCOUNTER28 ,MHPMCOUNTER29 ,MHPMCOUNTER30 ,MHPMCOUNTER31 ,MHPMCOUNTERH3 ,MHPMCOUNTERH4 ,MHPMCOUNTERH5 ,MHPMCOUNTERH6 ,MHPMCOUNTERH7 ,MHPMCOUNTERH8 ,MHPMCOUNTERH9 ,MHPMCOUNTERH10 ,MHPMCOUNTERH11 ,MHPMCOUNTERH12 ,MHPMCOUNTERH13 ,MHPMCOUNTERH14 ,MHPMCOUNTERH15 ,MHPMCOUNTERH16 ,MHPMCOUNTERH17 ,MHPMCOUNTERH18 ,MHPMCOUNTERH19 ,MHPMCOUNTERH20 ,MHPMCOUNTERH21 ,MHPMCOUNTERH22 ,MHPMCOUNTERH23 ,MHPMCOUNTERH24 ,MHPMCOUNTERH25 ,MHPMCOUNTERH26 ,MHPMCOUNTERH27 ,MHPMCOUNTERH28 ,MHPMCOUNTERH29 ,MHPMCOUNTERH30 ,MHPMCOUNTERH31 , + ########################## + #MSTATUS testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h16} + ########################## + #MSTATUS Write clear/set value 0x1f + csrrci x14, 0x300, 0x0 + csrrsi x14, 0x300, 0x1f + + #MSTATUS read value, expected 0xa + csrr x14, 0x300 + + #MSTATUS Write clear/set value 0x0 + csrrci x14, 0x300, 0x1f + csrrsi x14, 0x300, 0x0 + + #MSTATUS read value, expected 0x0 + csrr x14, 0x300 + + #MSTATUS Write clear/set value 0x15 + csrrci x14, 0x300, 0xa + csrrsi x14, 0x300, 0x15 + + #MSTATUS read value, expected 0x0 + csrr x14, 0x300 + + #MSTATUS Write clear/set value 0xa + csrrci x14, 0x300, 0x15 + csrrsi x14, 0x300, 0xa + + #MSTATUS read value, expected 0xa + csrr x14, 0x300 + + #MSTATUS Write clear/set value 0x16 + csrrci x14, 0x300, 0x9 + csrrsi x14, 0x300, 0x16 + + #MSTATUS read value, expected 0x2 + csrr x14, 0x300 + + ########################## + #MTVAL testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h18} + ########################## + #MTVAL Write clear/set value 0x1f + csrrci x14, 0x343, 0x0 + csrrsi x14, 0x343, 0x1f + + #MTVAL read value, expected 0x1f + csrr x14, 0x343 + + #MTVAL Write clear/set value 0x0 + csrrci x14, 0x343, 0x1f + csrrsi x14, 0x343, 0x0 + + #MTVAL read value, expected 0x0 + csrr x14, 0x343 + + #MTVAL Write clear/set value 0x15 + csrrci x14, 0x343, 0xa + csrrsi x14, 0x343, 0x15 + + #MTVAL read value, expected 0x15 + csrr x14, 0x343 + + #MTVAL Write clear/set value 0xa + csrrci x14, 0x343, 0x15 + csrrsi x14, 0x343, 0xa + + #MTVAL read value, expected 0xa + csrr x14, 0x343 + + #MTVAL Write clear/set value 0x18 + csrrci x14, 0x343, 0x7 + csrrsi x14, 0x343, 0x18 + + #MTVAL read value, expected 0x18 + csrr x14, 0x343 + + ########################## + #MSCRATCH testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h9} + ########################## + #MSCRATCH Write clear/set value 0x1f + csrrci x14, 0x340, 0x0 + csrrsi x14, 0x340, 0x1f + + #MSCRATCH read value, expected 0x1f + csrr x14, 0x340 + + #MSCRATCH Write clear/set value 0x0 + csrrci x14, 0x340, 0x1f + csrrsi x14, 0x340, 0x0 + + #MSCRATCH read value, expected 0x0 + csrr x14, 0x340 + + #MSCRATCH Write clear/set value 0x15 + csrrci x14, 0x340, 0xa + csrrsi x14, 0x340, 0x15 + + #MSCRATCH read value, expected 0x15 + csrr x14, 0x340 + + #MSCRATCH Write clear/set value 0xa + csrrci x14, 0x340, 0x15 + csrrsi x14, 0x340, 0xa + + #MSCRATCH read value, expected 0xa + csrr x14, 0x340 + + #MSCRATCH Write clear/set value 0x9 + csrrci x14, 0x340, 0x16 + csrrsi x14, 0x340, 0x9 + + #MSCRATCH read value, expected 0x9 + csrr x14, 0x340 + + ########################## + #MCYCLE testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h2} + ########################## + #MCYCLE Write clear/set value 0x1f + csrrci x14, 0xb00, 0x0 + csrrsi x14, 0xb00, 0x1f + + #MCYCLE read value, expected 0x1f + csrr x14, 0xb00 + + #MCYCLE Write clear/set value 0x0 + csrrci x14, 0xb00, 0x1f + csrrsi x14, 0xb00, 0x0 + + #MCYCLE read value, expected 0x0 + csrr x14, 0xb00 + + #MCYCLE Write clear/set value 0x15 + csrrci x14, 0xb00, 0xa + csrrsi x14, 0xb00, 0x15 + + #MCYCLE read value, expected 0x15 + csrr x14, 0xb00 + + #MCYCLE Write clear/set value 0xa + csrrci x14, 0xb00, 0x15 + csrrsi x14, 0xb00, 0xa + + #MCYCLE read value, expected 0xa + csrr x14, 0xb00 + + #MCYCLE Write clear/set value 0x2 + csrrci x14, 0xb00, 0x1d + csrrsi x14, 0xb00, 0x2 + + #MCYCLE read value, expected 0x2 + csrr x14, 0xb00 + + ########################## + #MTVEC testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h7} + ########################## + #MTVEC Write clear/set value 0x1f + csrrci x14, 0x305, 0x0 + csrrsi x14, 0x305, 0x1f + + #MTVEC read value, expected 0x1f + csrr x14, 0x305 + + #MTVEC Write clear/set value 0x0 + csrrci x14, 0x305, 0x1f + csrrsi x14, 0x305, 0x0 + + #MTVEC read value, expected 0x0 + csrr x14, 0x305 + + #MTVEC Write clear/set value 0x15 + csrrci x14, 0x305, 0xa + csrrsi x14, 0x305, 0x15 + + #MTVEC read value, expected 0x15 + csrr x14, 0x305 + + #MTVEC Write clear/set value 0xa + csrrci x14, 0x305, 0x15 + csrrsi x14, 0x305, 0xa + + #MTVEC read value, expected 0xa + csrr x14, 0x305 + + #MTVEC Write clear/set value 0x7 + csrrci x14, 0x305, 0x18 + csrrsi x14, 0x305, 0x7 + + #MTVEC read value, expected 0x7 + csrr x14, 0x305 + + ########################## + #MCAUSE testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h16} + ########################## + #MCAUSE Write clear/set value 0x1f + csrrci x14, 0x342, 0x0 + csrrsi x14, 0x342, 0x1f + + #MCAUSE read value, expected 0x1f + csrr x14, 0x342 + + #MCAUSE Write clear/set value 0x0 + csrrci x14, 0x342, 0x1f + csrrsi x14, 0x342, 0x0 + + #MCAUSE read value, expected 0x0 + csrr x14, 0x342 + + #MCAUSE Write clear/set value 0x15 + csrrci x14, 0x342, 0xa + csrrsi x14, 0x342, 0x15 + + #MCAUSE read value, expected 0x15 + csrr x14, 0x342 + + #MCAUSE Write clear/set value 0xa + csrrci x14, 0x342, 0x15 + csrrsi x14, 0x342, 0xa + + #MCAUSE read value, expected 0xa + csrr x14, 0x342 + + #MCAUSE Write clear/set value 0x16 + csrrci x14, 0x342, 0x9 + csrrsi x14, 0x342, 0x16 + + #MCAUSE read value, expected 0x16 + csrr x14, 0x342 + + ########################## + #MINSTRETH testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h1f} + ########################## + #MINSTRETH Write clear/set value 0x1f + csrrci x14, 0xb82, 0x0 + csrrsi x14, 0xb82, 0x1f + + #MINSTRETH read value, expected 0x1f + csrr x14, 0xb82 + + #MINSTRETH Write clear/set value 0x0 + csrrci x14, 0xb82, 0x1f + csrrsi x14, 0xb82, 0x0 + + #MINSTRETH read value, expected 0x0 + csrr x14, 0xb82 + + #MINSTRETH Write clear/set value 0x15 + csrrci x14, 0xb82, 0xa + csrrsi x14, 0xb82, 0x15 + + #MINSTRETH read value, expected 0x15 + csrr x14, 0xb82 + + #MINSTRETH Write clear/set value 0xa + csrrci x14, 0xb82, 0x15 + csrrsi x14, 0xb82, 0xa + + #MINSTRETH read value, expected 0xa + csrr x14, 0xb82 + + #MINSTRETH Write clear/set value 0x1f + csrrci x14, 0xb82, 0x0 + csrrsi x14, 0xb82, 0x1f + + #MINSTRETH read value, expected 0x1f + csrr x14, 0xb82 + + ########################## + #MIP testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h10} + ########################## + #MIP Write clear/set value 0x1f + csrrci x14, 0x344, 0x0 + csrrsi x14, 0x344, 0x1f + + #MIP read value, expected 0x1b + csrr x14, 0x344 + + #MIP Write clear/set value 0x0 + csrrci x14, 0x344, 0x17 + csrrsi x14, 0x344, 0x0 + + #MIP read value, expected 0x0 + csrr x14, 0x344 + + #MIP Write clear/set value 0x15 + csrrci x14, 0x344, 0x2 + csrrsi x14, 0x344, 0x15 + + #MIP read value, expected 0x11 + csrr x14, 0x344 + + #MIP Write clear/set value 0xa + csrrci x14, 0x344, 0x15 + csrrsi x14, 0x344, 0xa + + #MIP read value, expected 0xa + csrr x14, 0x344 + + #MIP Write clear/set value 0x10 + csrrci x14, 0x344, 0x7 + csrrsi x14, 0x344, 0x10 + + #MIP read value, expected 0x10 + csrr x14, 0x344 + + ########################## + #MISA testing W/R values '{'h1b, 'h4, 'h15, 'ha, 'h3} + ########################## + #MISA Write clear/set value 0x1b + csrrci x14, 0x301, 0x4 + csrrsi x14, 0x301, 0x1b + + #MISA read value, expected 0x1b + csrr x14, 0x301 + + #MISA Write clear/set value 0x4 + csrrci x14, 0x301, 0x1b + csrrsi x14, 0x301, 0x4 + + #MISA read value, expected 0x4 + csrr x14, 0x301 + + #MISA Write clear/set value 0x15 + csrrci x14, 0x301, 0xa + csrrsi x14, 0x301, 0x15 + + #MISA read value, expected 0x15 + csrr x14, 0x301 + + #MISA Write clear/set value 0xa + csrrci x14, 0x301, 0x15 + csrrsi x14, 0x301, 0xa + + #MISA read value, expected 0xa + csrr x14, 0x301 + + #MISA Write clear/set value 0x3 + csrrci x14, 0x301, 0x1c + csrrsi x14, 0x301, 0x3 + + #MISA read value, expected 0x3 + csrr x14, 0x301 + + ########################## + #MSTATUSH testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h2} + ########################## + #MSTATUSH Write clear/set value 0x1f + csrrci x14, 0x310, 0x0 + csrrsi x14, 0x310, 0x1f + + #MSTATUSH read value, expected 0x10 + csrr x14, 0x310 + + #MSTATUSH Write clear/set value 0x0 + csrrci x14, 0x310, 0x1f + csrrsi x14, 0x310, 0x0 + + #MSTATUSH read value, expected 0x0 + csrr x14, 0x310 + + #MSTATUSH Write clear/set value 0x15 + csrrci x14, 0x310, 0xa + csrrsi x14, 0x310, 0x15 + + #MSTATUSH read value, expected 0x10 + csrr x14, 0x310 + + #MSTATUSH Write clear/set value 0xa + csrrci x14, 0x310, 0x15 + csrrsi x14, 0x310, 0xa + + #MSTATUSH read value, expected 0x0 + csrr x14, 0x310 + + #MSTATUSH Write clear/set value 0x2 + csrrci x14, 0x310, 0x1d + csrrsi x14, 0x310, 0x2 + + #MSTATUSH read value, expected 0x0 + csrr x14, 0x310 + + ########################## + #MCYCLEH testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'hd} + ########################## + #MCYCLEH Write clear/set value 0x1f + csrrci x14, 0xb80, 0x0 + csrrsi x14, 0xb80, 0x1f + + #MCYCLEH read value, expected 0x1f + csrr x14, 0xb80 + + #MCYCLEH Write clear/set value 0x0 + csrrci x14, 0xb80, 0x1f + csrrsi x14, 0xb80, 0x0 + + #MCYCLEH read value, expected 0x0 + csrr x14, 0xb80 + + #MCYCLEH Write clear/set value 0x15 + csrrci x14, 0xb80, 0xa + csrrsi x14, 0xb80, 0x15 + + #MCYCLEH read value, expected 0x15 + csrr x14, 0xb80 + + #MCYCLEH Write clear/set value 0xa + csrrci x14, 0xb80, 0x15 + csrrsi x14, 0xb80, 0xa + + #MCYCLEH read value, expected 0xa + csrr x14, 0xb80 + + #MCYCLEH Write clear/set value 0xd + csrrci x14, 0xb80, 0x12 + csrrsi x14, 0xb80, 0xd + + #MCYCLEH read value, expected 0xd + csrr x14, 0xb80 + + ########################## + #MIE testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h6} + ########################## + #MIE Write clear/set value 0x1f + csrrci x14, 0x304, 0x0 + csrrsi x14, 0x304, 0x1f + + #MIE read value, expected 0x1b + csrr x14, 0x304 + + #MIE Write clear/set value 0x0 + csrrci x14, 0x304, 0x1f + csrrsi x14, 0x304, 0x0 + + #MIE read value, expected 0x0 + csrr x14, 0x304 + + #MIE Write clear/set value 0x15 + csrrci x14, 0x304, 0xa + csrrsi x14, 0x304, 0x15 + + #MIE read value, expected 0x11 + csrr x14, 0x304 + + #MIE Write clear/set value 0xa + csrrci x14, 0x304, 0x15 + csrrsi x14, 0x304, 0xa + + #MIE read value, expected 0xa + csrr x14, 0x304 + + #MIE Write clear/set value 0x6 + csrrci x14, 0x304, 0x19 + csrrsi x14, 0x304, 0x6 + + #MIE read value, expected 0x2 + csrr x14, 0x304 + + ########################## + #MEPC testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h1c} + ########################## + #MEPC Write clear/set value 0x1f + csrrci x14, 0x341, 0x0 + csrrsi x14, 0x341, 0x1f + + #MEPC read value, expected 0x1f + csrr x14, 0x341 + + #MEPC Write clear/set value 0x0 + csrrci x14, 0x341, 0x1f + csrrsi x14, 0x341, 0x0 + + #MEPC read value, expected 0x0 + csrr x14, 0x341 + + #MEPC Write clear/set value 0x15 + csrrci x14, 0x341, 0xa + csrrsi x14, 0x341, 0x15 + + #MEPC read value, expected 0x15 + csrr x14, 0x341 + + #MEPC Write clear/set value 0xa + csrrci x14, 0x341, 0x15 + csrrsi x14, 0x341, 0xa + + #MEPC read value, expected 0xa + csrr x14, 0x341 + + #MEPC Write clear/set value 0x1c + csrrci x14, 0x341, 0x3 + csrrsi x14, 0x341, 0x1c + + #MEPC read value, expected 0x1c + csrr x14, 0x341 + + ########################## + #MINSTRET testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h1} + ########################## + #MINSTRET Write clear/set value 0x1f + csrrci x14, 0xb02, 0x0 + csrrsi x14, 0xb02, 0x1f + + #MINSTRET read value, expected 0x1f + csrr x14, 0xb02 + + #MINSTRET Write clear/set value 0x0 + csrrci x14, 0xb02, 0x1f + csrrsi x14, 0xb02, 0x0 + + #MINSTRET read value, expected 0x0 + csrr x14, 0xb02 + + #MINSTRET Write clear/set value 0x15 + csrrci x14, 0xb02, 0xa + csrrsi x14, 0xb02, 0x15 + + #MINSTRET read value, expected 0x15 + csrr x14, 0xb02 + + #MINSTRET Write clear/set value 0xa + csrrci x14, 0xb02, 0x15 + csrrsi x14, 0xb02, 0xa + + #MINSTRET read value, expected 0xa + csrr x14, 0xb02 + + #MINSTRET Write clear/set value 0x1 + csrrci x14, 0xb02, 0x1e + csrrsi x14, 0xb02, 0x1 + + #MINSTRET read value, expected 0x1 + csrr x14, 0xb02 + + ret diff --git a/verif/tests/custom/isacov/csrrw_test.S b/verif/tests/custom/isacov/csrrw_test.S new file mode 100644 index 0000000000..db3a9b42e4 --- /dev/null +++ b/verif/tests/custom/isacov/csrrw_test.S @@ -0,0 +1,544 @@ +# Copyright 2023 Thales DIS France SAS +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# + +csrrw: + #Start CSR tests: Write/Read all registers + #User ignored registers: MHPMEVENT3 ,MHPMEVENT4 ,MHPMEVENT5 ,MHPMEVENT6 ,MHPMEVENT7 ,MHPMEVENT8 ,MHPMEVENT9 ,MHPMEVENT10 ,MHPMEVENT11 ,MHPMEVENT12 ,MHPMEVENT13 ,MHPMEVENT14 ,MHPMEVENT15 ,MHPMEVENT16 ,MHPMEVENT17 ,MHPMEVENT18 ,MHPMEVENT19 ,MHPMEVENT20 ,MHPMEVENT21 ,MHPMEVENT22 ,MHPMEVENT23 ,MHPMEVENT24 ,MHPMEVENT25 ,MHPMEVENT26 ,MHPMEVENT27 ,MHPMEVENT28 ,MHPMEVENT29 ,MHPMEVENT30 ,MHPMEVENT31 ,PMPCFG0 ,PMPCFG1 ,PMPCFG2 ,PMPCFG3 ,PMPADDR0 ,PMPADDR1 ,PMPADDR2 ,PMPADDR3 ,PMPADDR4 ,PMPADDR5 ,PMPADDR6 ,PMPADDR7 ,PMPADDR8 ,PMPADDR9 ,PMPADDR10 ,PMPADDR11 ,PMPADDR12 ,PMPADDR13 ,PMPADDR14 ,PMPADDR15 ,ICACHE ,MHPMCOUNTER3 ,MHPMCOUNTER4 ,MHPMCOUNTER5 ,MHPMCOUNTER6 ,MHPMCOUNTER7 ,MHPMCOUNTER8 ,MHPMCOUNTER9 ,MHPMCOUNTER10 ,MHPMCOUNTER11 ,MHPMCOUNTER12 ,MHPMCOUNTER13 ,MHPMCOUNTER14 ,MHPMCOUNTER15 ,MHPMCOUNTER16 ,MHPMCOUNTER17 ,MHPMCOUNTER18 ,MHPMCOUNTER19 ,MHPMCOUNTER20 ,MHPMCOUNTER21 ,MHPMCOUNTER22 ,MHPMCOUNTER23 ,MHPMCOUNTER24 ,MHPMCOUNTER25 ,MHPMCOUNTER26 ,MHPMCOUNTER27 ,MHPMCOUNTER28 ,MHPMCOUNTER29 ,MHPMCOUNTER30 ,MHPMCOUNTER31 ,MHPMCOUNTERH3 ,MHPMCOUNTERH4 ,MHPMCOUNTERH5 ,MHPMCOUNTERH6 ,MHPMCOUNTERH7 ,MHPMCOUNTERH8 ,MHPMCOUNTERH9 ,MHPMCOUNTERH10 ,MHPMCOUNTERH11 ,MHPMCOUNTERH12 ,MHPMCOUNTERH13 ,MHPMCOUNTERH14 ,MHPMCOUNTERH15 ,MHPMCOUNTERH16 ,MHPMCOUNTERH17 ,MHPMCOUNTERH18 ,MHPMCOUNTERH19 ,MHPMCOUNTERH20 ,MHPMCOUNTERH21 ,MHPMCOUNTERH22 ,MHPMCOUNTERH23 ,MHPMCOUNTERH24 ,MHPMCOUNTERH25 ,MHPMCOUNTERH26 ,MHPMCOUNTERH27 ,MHPMCOUNTERH28 ,MHPMCOUNTERH29 ,MHPMCOUNTERH30 ,MHPMCOUNTERH31 , + ########################## + #MSTATUS testing W/R values '{'hffffffff, 'h0, 'h55555555, 'haaaaaaaa, 'hd13933c1} + ########################## + #MSTATUS Write value 0xffffffff + li x3, 0xffffffff + csrw 0x300, x3 + + #MSTATUS read value, expected 0x807fffea + csrr x14, 0x300 + + #MSTATUS Write value 0x0 + li x3, 0x0 + csrw 0x300, x3 + + #MSTATUS read value, expected 0x0 + csrr x14, 0x300 + + #MSTATUS Write value 0x55555555 + li x3, 0x55555555 + csrw 0x300, x3 + + #MSTATUS read value, expected 0x555540 + csrr x14, 0x300 + + #MSTATUS Write value 0xaaaaaaaa + li x3, 0xaaaaaaaa + csrw 0x300, x3 + + #MSTATUS read value, expected 0x802aaaaa + csrr x14, 0x300 + + #MSTATUS Write value 0xd13933c1 + li x3, 0xd13933c1 + csrw 0x300, x3 + + #MSTATUS read value, expected 0x803933c0 + csrr x14, 0x300 + + ########################## + #MTVEC testing W/R values '{'hffffffff, 'h0, 'h55555555, 'haaaaaaaa, 'h30d053db} + ########################## + #MTVEC Write value 0xffffffff + li x3, 0xffffffff + csrw 0x305, x3 + + #MTVEC read value, expected 0xffffffff + csrr x14, 0x305 + + #MTVEC Write value 0x0 + li x3, 0x0 + csrw 0x305, x3 + + #MTVEC read value, expected 0x0 + csrr x14, 0x305 + + #MTVEC Write value 0x55555555 + li x3, 0x55555555 + csrw 0x305, x3 + + #MTVEC read value, expected 0x55555555 + csrr x14, 0x305 + + #MTVEC Write value 0xaaaaaaaa + li x3, 0xaaaaaaaa + csrw 0x305, x3 + + #MTVEC read value, expected 0xaaaaaaaa + csrr x14, 0x305 + + #MTVEC Write value 0x30d053db + li x3, 0x30d053db + csrw 0x305, x3 + + #MTVEC read value, expected 0x30d053db + csrr x14, 0x305 + + ########################## + #MINSTRET testing W/R values '{'hffffffff, 'h0, 'h55555555, 'haaaaaaaa, 'hb88086b0} + ########################## + #MINSTRET Write value 0xffffffff + li x3, 0xffffffff + csrw 0xb02, x3 + + #MINSTRET read value, expected 0xffffffff + csrr x14, 0xb02 + + #MINSTRET Write value 0x0 + li x3, 0x0 + csrw 0xb02, x3 + + #MINSTRET read value, expected 0x0 + csrr x14, 0xb02 + + #MINSTRET Write value 0x55555555 + li x3, 0x55555555 + csrw 0xb02, x3 + + #MINSTRET read value, expected 0x55555555 + csrr x14, 0xb02 + + #MINSTRET Write value 0xaaaaaaaa + li x3, 0xaaaaaaaa + csrw 0xb02, x3 + + #MINSTRET read value, expected 0xaaaaaaaa + csrr x14, 0xb02 + + #MINSTRET Write value 0xb88086b0 + li x3, 0xb88086b0 + csrw 0xb02, x3 + + #MINSTRET read value, expected 0xb88086b0 + csrr x14, 0xb02 + + ########################## + #MIE testing W/R values '{'hffffffff, 'h0, 'h55555555, 'haaaaaaaa, 'hfef91206} + ########################## + #MIE Write value 0xffffffff + li x3, 0xffffffff + csrw 0x304, x3 + + #MIE read value, expected 0xbbb + csrr x14, 0x304 + + #MIE Write value 0x0 + li x3, 0x0 + csrw 0x304, x3 + + #MIE read value, expected 0x0 + csrr x14, 0x304 + + #MIE Write value 0x55555555 + li x3, 0x55555555 + csrw 0x304, x3 + + #MIE read value, expected 0x111 + csrr x14, 0x304 + + #MIE Write value 0xaaaaaaaa + li x3, 0xaaaaaaaa + csrw 0x304, x3 + + #MIE read value, expected 0xaaa + csrr x14, 0x304 + + #MIE Write value 0xfef91206 + li x3, 0xfef91206 + csrw 0x304, x3 + + #MIE read value, expected 0x202 + csrr x14, 0x304 + + ########################## + #MIP testing W/R values '{'hffffffff, 'h0, 'h55555555, 'haaaaaaaa, 'hd3052355} + ########################## + #MIP Write value 0xffffffff + li x3, 0xffffffff + csrw 0x344, x3 + + #MIP read value, expected 0xbbb + csrr x14, 0x344 + + #MIP Write value 0x0 + li x3, 0x0 + csrw 0x344, x3 + + #MIP read value, expected 0x0 + csrr x14, 0x344 + + #MIP Write value 0x55555555 + li x3, 0x55555555 + csrw 0x344, x3 + + #MIP read value, expected 0x111 + csrr x14, 0x344 + + #MIP Write value 0xaaaaaaaa + li x3, 0xaaaaaaaa + csrw 0x344, x3 + + #MIP read value, expected 0xaaa + csrr x14, 0x344 + + #MIP Write value 0xd3052355 + li x3, 0xd3052355 + csrw 0x344, x3 + + #MIP read value, expected 0x311 + csrr x14, 0x344 + + ########################## + #MEPC testing W/R values '{'hffffffff, 'h0, 'h55555555, 'haaaaaaaa, 'h7238da3e} + ########################## + #MEPC Write value 0xffffffff + li x3, 0xffffffff + csrw 0x341, x3 + + #MEPC read value, expected 0xffffffff + csrr x14, 0x341 + + #MEPC Write value 0x0 + li x3, 0x0 + csrw 0x341, x3 + + #MEPC read value, expected 0x0 + csrr x14, 0x341 + + #MEPC Write value 0x55555555 + li x3, 0x55555555 + csrw 0x341, x3 + + #MEPC read value, expected 0x55555555 + csrr x14, 0x341 + + #MEPC Write value 0xaaaaaaaa + li x3, 0xaaaaaaaa + csrw 0x341, x3 + + #MEPC read value, expected 0xaaaaaaaa + csrr x14, 0x341 + + #MEPC Write value 0x7238da3e + li x3, 0x7238da3e + csrw 0x341, x3 + + #MEPC read value, expected 0x7238da3e + csrr x14, 0x341 + + ########################## + #MCYCLEH testing W/R values '{'hffffffff, 'h0, 'h55555555, 'haaaaaaaa, 'h7572495f} + ########################## + #MCYCLEH Write value 0xffffffff + li x3, 0xffffffff + csrw 0xb80, x3 + + #MCYCLEH read value, expected 0xffffffff + csrr x14, 0xb80 + + #MCYCLEH Write value 0x0 + li x3, 0x0 + csrw 0xb80, x3 + + #MCYCLEH read value, expected 0x0 + csrr x14, 0xb80 + + #MCYCLEH Write value 0x55555555 + li x3, 0x55555555 + csrw 0xb80, x3 + + #MCYCLEH read value, expected 0x55555555 + csrr x14, 0xb80 + + #MCYCLEH Write value 0xaaaaaaaa + li x3, 0xaaaaaaaa + csrw 0xb80, x3 + + #MCYCLEH read value, expected 0xaaaaaaaa + csrr x14, 0xb80 + + #MCYCLEH Write value 0x7572495f + li x3, 0x7572495f + csrw 0xb80, x3 + + #MCYCLEH read value, expected 0x7572495f + csrr x14, 0xb80 + + ########################## + #MINSTRETH testing W/R values '{'hffffffff, 'h0, 'h55555555, 'haaaaaaaa, 'he0f0095e} + ########################## + #MINSTRETH Write value 0xffffffff + li x3, 0xffffffff + csrw 0xb82, x3 + + #MINSTRETH read value, expected 0xffffffff + csrr x14, 0xb82 + + #MINSTRETH Write value 0x0 + li x3, 0x0 + csrw 0xb82, x3 + + #MINSTRETH read value, expected 0x0 + csrr x14, 0xb82 + + #MINSTRETH Write value 0x55555555 + li x3, 0x55555555 + csrw 0xb82, x3 + + #MINSTRETH read value, expected 0x55555555 + csrr x14, 0xb82 + + #MINSTRETH Write value 0xaaaaaaaa + li x3, 0xaaaaaaaa + csrw 0xb82, x3 + + #MINSTRETH read value, expected 0xaaaaaaaa + csrr x14, 0xb82 + + #MINSTRETH Write value 0xe0f0095e + li x3, 0xe0f0095e + csrw 0xb82, x3 + + #MINSTRETH read value, expected 0xe0f0095e + csrr x14, 0xb82 + + ########################## + #MCAUSE testing W/R values '{'hffffffff, 'h0, 'h55555555, 'haaaaaaaa, 'hd43e7a20} + ########################## + #MCAUSE Write value 0xffffffff + li x3, 0xffffffff + csrw 0x342, x3 + + #MCAUSE read value, expected 0xffffffff + csrr x14, 0x342 + + #MCAUSE Write value 0x0 + li x3, 0x0 + csrw 0x342, x3 + + #MCAUSE read value, expected 0x0 + csrr x14, 0x342 + + #MCAUSE Write value 0x55555555 + li x3, 0x55555555 + csrw 0x342, x3 + + #MCAUSE read value, expected 0x55555555 + csrr x14, 0x342 + + #MCAUSE Write value 0xaaaaaaaa + li x3, 0xaaaaaaaa + csrw 0x342, x3 + + #MCAUSE read value, expected 0xaaaaaaaa + csrr x14, 0x342 + + #MCAUSE Write value 0xd43e7a20 + li x3, 0xd43e7a20 + csrw 0x342, x3 + + #MCAUSE read value, expected 0xd43e7a20 + csrr x14, 0x342 + + ########################## + #MISA testing W/R values '{'hfdbf7bfb, 'h2408404, 'h55555555, 'haaaaaaaa, 'h2f0d4a6b} + ########################## + #MISA Write value 0xfdbf7bfb + li x3, 0xfdbf7bfb + csrw 0x301, x3 + + #MISA read value, expected 0xc1bf7bfb + csrr x14, 0x301 + + #MISA Write value 0x2408404 + li x3, 0x2408404 + csrw 0x301, x3 + + #MISA read value, expected 0x2408404 + csrr x14, 0x301 + + #MISA Write value 0x55555555 + li x3, 0x55555555 + csrw 0x301, x3 + + #MISA read value, expected 0x41555555 + csrr x14, 0x301 + + #MISA Write value 0xaaaaaaaa + li x3, 0xaaaaaaaa + csrw 0x301, x3 + + #MISA read value, expected 0x82aaaaaa + csrr x14, 0x301 + + #MISA Write value 0x2f0d4a6b + li x3, 0x2f0d4a6b + csrw 0x301, x3 + + #MISA read value, expected 0x30d4a6b + csrr x14, 0x301 + + ########################## + #MCYCLE testing W/R values '{'hffffffff, 'h0, 'h55555555, 'haaaaaaaa, 'hbfbcce35} + ########################## + #MCYCLE Write value 0xffffffff + li x3, 0xffffffff + csrw 0xb00, x3 + + #MCYCLE read value, expected 0xffffffff + csrr x14, 0xb00 + + #MCYCLE Write value 0x0 + li x3, 0x0 + csrw 0xb00, x3 + + #MCYCLE read value, expected 0x0 + csrr x14, 0xb00 + + #MCYCLE Write value 0x55555555 + li x3, 0x55555555 + csrw 0xb00, x3 + + #MCYCLE read value, expected 0x55555555 + csrr x14, 0xb00 + + #MCYCLE Write value 0xaaaaaaaa + li x3, 0xaaaaaaaa + csrw 0xb00, x3 + + #MCYCLE read value, expected 0xaaaaaaaa + csrr x14, 0xb00 + + #MCYCLE Write value 0xbfbcce35 + li x3, 0xbfbcce35 + csrw 0xb00, x3 + + #MCYCLE read value, expected 0xbfbcce35 + csrr x14, 0xb00 + + ########################## + #MSCRATCH testing W/R values '{'hffffffff, 'h0, 'h55555555, 'haaaaaaaa, 'h5334c7f3} + ########################## + #MSCRATCH Write value 0xffffffff + li x3, 0xffffffff + csrw 0x340, x3 + + #MSCRATCH read value, expected 0xffffffff + csrr x14, 0x340 + + #MSCRATCH Write value 0x0 + li x3, 0x0 + csrw 0x340, x3 + + #MSCRATCH read value, expected 0x0 + csrr x14, 0x340 + + #MSCRATCH Write value 0x55555555 + li x3, 0x55555555 + csrw 0x340, x3 + + #MSCRATCH read value, expected 0x55555555 + csrr x14, 0x340 + + #MSCRATCH Write value 0xaaaaaaaa + li x3, 0xaaaaaaaa + csrw 0x340, x3 + + #MSCRATCH read value, expected 0xaaaaaaaa + csrr x14, 0x340 + + #MSCRATCH Write value 0x5334c7f3 + li x3, 0x5334c7f3 + csrw 0x340, x3 + + #MSCRATCH read value, expected 0x5334c7f3 + csrr x14, 0x340 + + ########################## + #MSTATUSH testing W/R values '{'hffffffff, 'h0, 'h55555555, 'haaaaaaaa, 'h6391f8b7} + ########################## + #MSTATUSH Write value 0xffffffff + li x3, 0xffffffff + csrw 0x310, x3 + + #MSTATUSH read value, expected 0x30 + csrr x14, 0x310 + + #MSTATUSH Write value 0x0 + li x3, 0x0 + csrw 0x310, x3 + + #MSTATUSH read value, expected 0x0 + csrr x14, 0x310 + + #MSTATUSH Write value 0x55555555 + li x3, 0x55555555 + csrw 0x310, x3 + + #MSTATUSH read value, expected 0x10 + csrr x14, 0x310 + + #MSTATUSH Write value 0xaaaaaaaa + li x3, 0xaaaaaaaa + csrw 0x310, x3 + + #MSTATUSH read value, expected 0x20 + csrr x14, 0x310 + + #MSTATUSH Write value 0x6391f8b7 + li x3, 0x6391f8b7 + csrw 0x310, x3 + + #MSTATUSH read value, expected 0x30 + csrr x14, 0x310 + + ########################## + #MTVAL testing W/R values '{'hffffffff, 'h0, 'h55555555, 'haaaaaaaa, 'h973a306b} + ########################## + #MTVAL Write value 0xffffffff + li x3, 0xffffffff + csrw 0x343, x3 + + #MTVAL read value, expected 0xffffffff + csrr x14, 0x343 + + #MTVAL Write value 0x0 + li x3, 0x0 + csrw 0x343, x3 + + #MTVAL read value, expected 0x0 + csrr x14, 0x343 + + #MTVAL Write value 0x55555555 + li x3, 0x55555555 + csrw 0x343, x3 + + #MTVAL read value, expected 0x55555555 + csrr x14, 0x343 + + #MTVAL Write value 0xaaaaaaaa + li x3, 0xaaaaaaaa + csrw 0x343, x3 + + #MTVAL read value, expected 0xaaaaaaaa + csrr x14, 0x343 + + #MTVAL Write value 0x973a306b + li x3, 0x973a306b + csrw 0x343, x3 + + #MTVAL read value, expected 0x973a306b + csrr x14, 0x343 + + ret diff --git a/verif/tests/custom/isacov/csrrwi_test.S b/verif/tests/custom/isacov/csrrwi_test.S new file mode 100644 index 0000000000..a406145afa --- /dev/null +++ b/verif/tests/custom/isacov/csrrwi_test.S @@ -0,0 +1,474 @@ +# Copyright 2023 Thales DIS France SAS +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# + +csrrwi: + #Start CSR tests: Write/Read all registers using immediate instructions + #User ignored registers: MHPMEVENT3 ,MHPMEVENT4 ,MHPMEVENT5 ,MHPMEVENT6 ,MHPMEVENT7 ,MHPMEVENT8 ,MHPMEVENT9 ,MHPMEVENT10 ,MHPMEVENT11 ,MHPMEVENT12 ,MHPMEVENT13 ,MHPMEVENT14 ,MHPMEVENT15 ,MHPMEVENT16 ,MHPMEVENT17 ,MHPMEVENT18 ,MHPMEVENT19 ,MHPMEVENT20 ,MHPMEVENT21 ,MHPMEVENT22 ,MHPMEVENT23 ,MHPMEVENT24 ,MHPMEVENT25 ,MHPMEVENT26 ,MHPMEVENT27 ,MHPMEVENT28 ,MHPMEVENT29 ,MHPMEVENT30 ,MHPMEVENT31 ,PMPCFG0 ,PMPCFG1 ,PMPCFG2 ,PMPCFG3 ,PMPADDR0 ,PMPADDR1 ,PMPADDR2 ,PMPADDR3 ,PMPADDR4 ,PMPADDR5 ,PMPADDR6 ,PMPADDR7 ,PMPADDR8 ,PMPADDR9 ,PMPADDR10 ,PMPADDR11 ,PMPADDR12 ,PMPADDR13 ,PMPADDR14 ,PMPADDR15 ,ICACHE ,MHPMCOUNTER3 ,MHPMCOUNTER4 ,MHPMCOUNTER5 ,MHPMCOUNTER6 ,MHPMCOUNTER7 ,MHPMCOUNTER8 ,MHPMCOUNTER9 ,MHPMCOUNTER10 ,MHPMCOUNTER11 ,MHPMCOUNTER12 ,MHPMCOUNTER13 ,MHPMCOUNTER14 ,MHPMCOUNTER15 ,MHPMCOUNTER16 ,MHPMCOUNTER17 ,MHPMCOUNTER18 ,MHPMCOUNTER19 ,MHPMCOUNTER20 ,MHPMCOUNTER21 ,MHPMCOUNTER22 ,MHPMCOUNTER23 ,MHPMCOUNTER24 ,MHPMCOUNTER25 ,MHPMCOUNTER26 ,MHPMCOUNTER27 ,MHPMCOUNTER28 ,MHPMCOUNTER29 ,MHPMCOUNTER30 ,MHPMCOUNTER31 ,MHPMCOUNTERH3 ,MHPMCOUNTERH4 ,MHPMCOUNTERH5 ,MHPMCOUNTERH6 ,MHPMCOUNTERH7 ,MHPMCOUNTERH8 ,MHPMCOUNTERH9 ,MHPMCOUNTERH10 ,MHPMCOUNTERH11 ,MHPMCOUNTERH12 ,MHPMCOUNTERH13 ,MHPMCOUNTERH14 ,MHPMCOUNTERH15 ,MHPMCOUNTERH16 ,MHPMCOUNTERH17 ,MHPMCOUNTERH18 ,MHPMCOUNTERH19 ,MHPMCOUNTERH20 ,MHPMCOUNTERH21 ,MHPMCOUNTERH22 ,MHPMCOUNTERH23 ,MHPMCOUNTERH24 ,MHPMCOUNTERH25 ,MHPMCOUNTERH26 ,MHPMCOUNTERH27 ,MHPMCOUNTERH28 ,MHPMCOUNTERH29 ,MHPMCOUNTERH30 ,MHPMCOUNTERH31 , + ########################## + #MSTATUSH testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h1e} + ########################## + #MSTATUSH Write immediate value 0x1f + csrrwi x14, 0x310, 0x1f + + #MSTATUSH read value, expected 0x10 + csrr x14, 0x310 + + #MSTATUSH Write immediate value 0x0 + csrrwi x14, 0x310, 0x0 + + #MSTATUSH read value, expected 0x0 + csrr x14, 0x310 + + #MSTATUSH Write immediate value 0x15 + csrrwi x14, 0x310, 0x15 + + #MSTATUSH read value, expected 0x10 + csrr x14, 0x310 + + #MSTATUSH Write immediate value 0xa + csrrwi x14, 0x310, 0xa + + #MSTATUSH read value, expected 0x0 + csrr x14, 0x310 + + #MSTATUSH Write immediate value 0x1e + csrrwi x14, 0x310, 0x1e + + #MSTATUSH read value, expected 0x10 + csrr x14, 0x310 + + ########################## + #MIE testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h1c} + ########################## + #MIE Write immediate value 0x1f + csrrwi x14, 0x304, 0x1f + + #MIE read value, expected 0x1b + csrr x14, 0x304 + + #MIE Write immediate value 0x0 + csrrwi x14, 0x304, 0x0 + + #MIE read value, expected 0x0 + csrr x14, 0x304 + + #MIE Write immediate value 0x15 + csrrwi x14, 0x304, 0x15 + + #MIE read value, expected 0x11 + csrr x14, 0x304 + + #MIE Write immediate value 0xa + csrrwi x14, 0x304, 0xa + + #MIE read value, expected 0xa + csrr x14, 0x304 + + #MIE Write immediate value 0x1c + csrrwi x14, 0x304, 0x1c + + #MIE read value, expected 0x18 + csrr x14, 0x304 + + ########################## + #MCYCLEH testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'hc} + ########################## + #MCYCLEH Write immediate value 0x1f + csrrwi x14, 0xb80, 0x1f + + #MCYCLEH read value, expected 0x1f + csrr x14, 0xb80 + + #MCYCLEH Write immediate value 0x0 + csrrwi x14, 0xb80, 0x0 + + #MCYCLEH read value, expected 0x0 + csrr x14, 0xb80 + + #MCYCLEH Write immediate value 0x15 + csrrwi x14, 0xb80, 0x15 + + #MCYCLEH read value, expected 0x15 + csrr x14, 0xb80 + + #MCYCLEH Write immediate value 0xa + csrrwi x14, 0xb80, 0xa + + #MCYCLEH read value, expected 0xa + csrr x14, 0xb80 + + #MCYCLEH Write immediate value 0xc + csrrwi x14, 0xb80, 0xc + + #MCYCLEH read value, expected 0xc + csrr x14, 0xb80 + + ########################## + #MSCRATCH testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h1c} + ########################## + #MSCRATCH Write immediate value 0x1f + csrrwi x14, 0x340, 0x1f + + #MSCRATCH read value, expected 0x1f + csrr x14, 0x340 + + #MSCRATCH Write immediate value 0x0 + csrrwi x14, 0x340, 0x0 + + #MSCRATCH read value, expected 0x0 + csrr x14, 0x340 + + #MSCRATCH Write immediate value 0x15 + csrrwi x14, 0x340, 0x15 + + #MSCRATCH read value, expected 0x15 + csrr x14, 0x340 + + #MSCRATCH Write immediate value 0xa + csrrwi x14, 0x340, 0xa + + #MSCRATCH read value, expected 0xa + csrr x14, 0x340 + + #MSCRATCH Write immediate value 0x1c + csrrwi x14, 0x340, 0x1c + + #MSCRATCH read value, expected 0x1c + csrr x14, 0x340 + + ########################## + #MINSTRET testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h14} + ########################## + #MINSTRET Write immediate value 0x1f + csrrwi x14, 0xb02, 0x1f + + #MINSTRET read value, expected 0x1f + csrr x14, 0xb02 + + #MINSTRET Write immediate value 0x0 + csrrwi x14, 0xb02, 0x0 + + #MINSTRET read value, expected 0x0 + csrr x14, 0xb02 + + #MINSTRET Write immediate value 0x15 + csrrwi x14, 0xb02, 0x15 + + #MINSTRET read value, expected 0x15 + csrr x14, 0xb02 + + #MINSTRET Write immediate value 0xa + csrrwi x14, 0xb02, 0xa + + #MINSTRET read value, expected 0xa + csrr x14, 0xb02 + + #MINSTRET Write immediate value 0x14 + csrrwi x14, 0xb02, 0x14 + + #MINSTRET read value, expected 0x14 + csrr x14, 0xb02 + + ########################## + #MIP testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h2} + ########################## + #MIP Write immediate value 0x1f + csrrwi x14, 0x344, 0x1f + + #MIP read value, expected 0x1b + csrr x14, 0x344 + + #MIP Write immediate value 0x0 + csrrwi x14, 0x344, 0x0 + + #MIP read value, expected 0x0 + csrr x14, 0x344 + + #MIP Write immediate value 0x15 + csrrwi x14, 0x344, 0x15 + + #MIP read value, expected 0x11 + csrr x14, 0x344 + + #MIP Write immediate value 0xa + csrrwi x14, 0x344, 0xa + + #MIP read value, expected 0xa + csrr x14, 0x344 + + #MIP Write immediate value 0x2 + csrrwi x14, 0x344, 0x2 + + #MIP read value, expected 0x2 + csrr x14, 0x344 + + ########################## + #MTVEC testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h19} + ########################## + #MTVEC Write immediate value 0x1f + csrrwi x14, 0x305, 0x1f + + #MTVEC read value, expected 0x1f + csrr x14, 0x305 + + #MTVEC Write immediate value 0x0 + csrrwi x14, 0x305, 0x0 + + #MTVEC read value, expected 0x0 + csrr x14, 0x305 + + #MTVEC Write immediate value 0x15 + csrrwi x14, 0x305, 0x15 + + #MTVEC read value, expected 0x15 + csrr x14, 0x305 + + #MTVEC Write immediate value 0xa + csrrwi x14, 0x305, 0xa + + #MTVEC read value, expected 0xa + csrr x14, 0x305 + + #MTVEC Write immediate value 0x19 + csrrwi x14, 0x305, 0x19 + + #MTVEC read value, expected 0x19 + csrr x14, 0x305 + + ########################## + #MEPC testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h18} + ########################## + #MEPC Write immediate value 0x1f + csrrwi x14, 0x341, 0x1f + + #MEPC read value, expected 0x1f + csrr x14, 0x341 + + #MEPC Write immediate value 0x0 + csrrwi x14, 0x341, 0x0 + + #MEPC read value, expected 0x0 + csrr x14, 0x341 + + #MEPC Write immediate value 0x15 + csrrwi x14, 0x341, 0x15 + + #MEPC read value, expected 0x15 + csrr x14, 0x341 + + #MEPC Write immediate value 0xa + csrrwi x14, 0x341, 0xa + + #MEPC read value, expected 0xa + csrr x14, 0x341 + + #MEPC Write immediate value 0x18 + csrrwi x14, 0x341, 0x18 + + #MEPC read value, expected 0x18 + csrr x14, 0x341 + + ########################## + #MCYCLE testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h1} + ########################## + #MCYCLE Write immediate value 0x1f + csrrwi x14, 0xb00, 0x1f + + #MCYCLE read value, expected 0x1f + csrr x14, 0xb00 + + #MCYCLE Write immediate value 0x0 + csrrwi x14, 0xb00, 0x0 + + #MCYCLE read value, expected 0x0 + csrr x14, 0xb00 + + #MCYCLE Write immediate value 0x15 + csrrwi x14, 0xb00, 0x15 + + #MCYCLE read value, expected 0x15 + csrr x14, 0xb00 + + #MCYCLE Write immediate value 0xa + csrrwi x14, 0xb00, 0xa + + #MCYCLE read value, expected 0xa + csrr x14, 0xb00 + + #MCYCLE Write immediate value 0x1 + csrrwi x14, 0xb00, 0x1 + + #MCYCLE read value, expected 0x1 + csrr x14, 0xb00 + + ########################## + #MINSTRETH testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h6} + ########################## + #MINSTRETH Write immediate value 0x1f + csrrwi x14, 0xb82, 0x1f + + #MINSTRETH read value, expected 0x1f + csrr x14, 0xb82 + + #MINSTRETH Write immediate value 0x0 + csrrwi x14, 0xb82, 0x0 + + #MINSTRETH read value, expected 0x0 + csrr x14, 0xb82 + + #MINSTRETH Write immediate value 0x15 + csrrwi x14, 0xb82, 0x15 + + #MINSTRETH read value, expected 0x15 + csrr x14, 0xb82 + + #MINSTRETH Write immediate value 0xa + csrrwi x14, 0xb82, 0xa + + #MINSTRETH read value, expected 0xa + csrr x14, 0xb82 + + #MINSTRETH Write immediate value 0x6 + csrrwi x14, 0xb82, 0x6 + + #MINSTRETH read value, expected 0x6 + csrr x14, 0xb82 + + ########################## + #MCAUSE testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h7} + ########################## + #MCAUSE Write immediate value 0x1f + csrrwi x14, 0x342, 0x1f + + #MCAUSE read value, expected 0x1f + csrr x14, 0x342 + + #MCAUSE Write immediate value 0x0 + csrrwi x14, 0x342, 0x0 + + #MCAUSE read value, expected 0x0 + csrr x14, 0x342 + + #MCAUSE Write immediate value 0x15 + csrrwi x14, 0x342, 0x15 + + #MCAUSE read value, expected 0x15 + csrr x14, 0x342 + + #MCAUSE Write immediate value 0xa + csrrwi x14, 0x342, 0xa + + #MCAUSE read value, expected 0xa + csrr x14, 0x342 + + #MCAUSE Write immediate value 0x7 + csrrwi x14, 0x342, 0x7 + + #MCAUSE read value, expected 0x7 + csrr x14, 0x342 + + ########################## + #MISA testing W/R values '{'h1b, 'h4, 'h15, 'ha, 'h4} + ########################## + #MISA Write immediate value 0x1b + csrrwi x14, 0x301, 0x1b + + #MISA read value, expected 0x1b + csrr x14, 0x301 + + #MISA Write immediate value 0x4 + csrrwi x14, 0x301, 0x4 + + #MISA read value, expected 0x4 + csrr x14, 0x301 + + #MISA Write immediate value 0x15 + csrrwi x14, 0x301, 0x15 + + #MISA read value, expected 0x15 + csrr x14, 0x301 + + #MISA Write immediate value 0xa + csrrwi x14, 0x301, 0xa + + #MISA read value, expected 0xa + csrr x14, 0x301 + + #MISA Write immediate value 0x4 + csrrwi x14, 0x301, 0x4 + + #MISA read value, expected 0x4 + csrr x14, 0x301 + + ########################## + #MTVAL testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h3} + ########################## + #MTVAL Write immediate value 0x1f + csrrwi x14, 0x343, 0x1f + + #MTVAL read value, expected 0x1f + csrr x14, 0x343 + + #MTVAL Write immediate value 0x0 + csrrwi x14, 0x343, 0x0 + + #MTVAL read value, expected 0x0 + csrr x14, 0x343 + + #MTVAL Write immediate value 0x15 + csrrwi x14, 0x343, 0x15 + + #MTVAL read value, expected 0x15 + csrr x14, 0x343 + + #MTVAL Write immediate value 0xa + csrrwi x14, 0x343, 0xa + + #MTVAL read value, expected 0xa + csrr x14, 0x343 + + #MTVAL Write immediate value 0x3 + csrrwi x14, 0x343, 0x3 + + #MTVAL read value, expected 0x3 + csrr x14, 0x343 + + ########################## + #MSTATUS testing W/R values '{'h1f, 'h0, 'h15, 'ha, 'h18} + ########################## + #MSTATUS Write immediate value 0x1f + csrrwi x14, 0x300, 0x1f + + #MSTATUS read value, expected 0xa + csrr x14, 0x300 + + #MSTATUS Write immediate value 0x0 + csrrwi x14, 0x300, 0x0 + + #MSTATUS read value, expected 0x0 + csrr x14, 0x300 + + #MSTATUS Write immediate value 0x15 + csrrwi x14, 0x300, 0x15 + + #MSTATUS read value, expected 0x0 + csrr x14, 0x300 + + #MSTATUS Write immediate value 0xa + csrrwi x14, 0x300, 0xa + + #MSTATUS read value, expected 0xa + csrr x14, 0x300 + + #MSTATUS Write immediate value 0x18 + csrrwi x14, 0x300, 0x18 + + #MSTATUS read value, expected 0x8 + csrr x14, 0x300 + + ret diff --git a/verif/tests/custom/isacov/load_reg_hazard.S b/verif/tests/custom/isacov/load_reg_hazard.S new file mode 100644 index 0000000000..eb03114946 --- /dev/null +++ b/verif/tests/custom/isacov/load_reg_hazard.S @@ -0,0 +1,349 @@ +# Copyright 2023 Thales DIS design services SAS +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Original Author: Ayoub JALALI (ayoub.jalali@external.thalesgroup.com) + +#***************************************************************************** +# load_reg_hazard.S +#----------------------------------------------------------------------------- +# + + .globl main +main: + li ra, 0x80000000 + li sp, 0x80000000 + li gp, 0x80000000 + li tp, 0x80000000 + li t0, 0x80000000 + li t1, 0x80000000 + li t2, 0x80000000 + li s0, 0x80000000 + li s1, 0x80000000 + li a0, 0x80000000 + li a1, 0x80000000 + li a2, 0x80000000 + li a3, 0x80000000 + li a4, 0x80000000 + li a5, 0x80000000 + li a6, 0x80000000 + li a7, 0x80000000 + li s2, 0x80000000 + li s3, 0x80000000 + li s4, 0x80000000 + li s5, 0x80000000 + li s6, 0x80000000 + li s7, 0x80000000 + li s8, 0x80000000 + li s9, 0x80000000 + li s10, 0x80000000 + li s11, 0x80000000 + li t3, 0x80000000 + li t4, 0x80000000 + li t5, 0x80000000 + li t6, 0x80000000 + lw zero, -16(zero) + lw sp, 1024(sp) + lw ra, 52(ra) + lw gp, 52(gp) + lw tp, 52(tp) + lw t0, 52(t0) + lw t1, 52(t1) + lw t2, 52(t2) + lw s0, 1024(s0) + lw s1, 1024(s1) + lw a0, 1024(a0) + lw a1, 1024(a1) + lw a2, 1024(a2) + lw a3, 1024(a3) + lw a4, 1024(a4) + lw a5, 1024(a5) + lw a6, 1024(a6) + lw a7, 1024(a7) + lw s2, 52(s2) + lw s3, 52(s3) + lw s4, 52(s4) + lw s5, 72(s5) + lw s6, 76(s6) + lw s7, 80(s7) + lw s8, 84(s8) + lw s9, 88(s9) + lw s10, 92(s10) + lw s11, 96(s11) + lw t3, 12(t3) + lw t4, 16(t4) + lw t5, 12(t5) + lw t6, 16(t6) + li ra, 0x80000000 + li sp, 0x80000000 + li gp, 0x80000000 + li tp, 0x80000000 + li t0, 0x80000000 + li t1, 0x80000000 + li t2, 0x80000000 + li s0, 0x80000000 + li s1, 0x80000000 + li a0, 0x80000000 + li a1, 0x80000000 + li a2, 0x80000000 + li a3, 0x80000000 + li a4, 0x80000000 + li a5, 0x80000000 + li a6, 0x80000000 + li a7, 0x80000000 + li s2, 0x80000000 + li s3, 0x80000000 + li s4, 0x80000000 + li s5, 0x80000000 + li s6, 0x80000000 + li s7, 0x80000000 + li s8, 0x80000000 + li s9, 0x80000000 + li s10, 0x80000000 + li s11, 0x80000000 + li t3, 0x80000000 + li t4, 0x80000000 + li t5, 0x80000000 + li t6, 0x80000000 + lh zero, -16(zero) + lh sp, 1024(sp) + lh ra, 52(ra) + lh gp, 52(gp) + lh tp, 52(tp) + lh t0, 52(t0) + lh t1, 52(t1) + lh t2, 52(t2) + lh s0, 1024(s0) + lh s1, 1024(s1) + lh a0, 1024(a0) + lh a1, 1024(a1) + lh a2, 1024(a2) + lh a3, 1024(a3) + lh a4, 1024(a4) + lh a5, 1024(a5) + lh a6, 1024(a6) + lh a7, 1024(a7) + lh s2, 52(s2) + lh s3, 52(s3) + lh s4, 52(s4) + lh s5, 72(s5) + lh s6, 76(s6) + lh s7, 80(s7) + lh s8, 84(s8) + lh s9, 88(s9) + lh s10, 92(s10) + lh s11, 96(s11) + lh t3, 12(t3) + lh t4, 16(t4) + lh t5, 12(t5) + lh t6, 16(t6) + li ra, 0x80000000 + li sp, 0x80000000 + li gp, 0x80000000 + li tp, 0x80000000 + li t0, 0x80000000 + li t1, 0x80000000 + li t2, 0x80000000 + li s0, 0x80000000 + li s1, 0x80000000 + li a0, 0x80000000 + li a1, 0x80000000 + li a2, 0x80000000 + li a3, 0x80000000 + li a4, 0x80000000 + li a5, 0x80000000 + li a6, 0x80000000 + li a7, 0x80000000 + li s2, 0x80000000 + li s3, 0x80000000 + li s4, 0x80000000 + li s5, 0x80000000 + li s6, 0x80000000 + li s7, 0x80000000 + li s8, 0x80000000 + li s9, 0x80000000 + li s10, 0x80000000 + li s11, 0x80000000 + li t3, 0x80000000 + li t4, 0x80000000 + li t5, 0x80000000 + li t6, 0x80000000 + lb zero, -16(zero) + lb sp, 1024(sp) + lb ra, 52(ra) + lb gp, 52(gp) + lb tp, 52(tp) + lb t0, 52(t0) + lb t1, 52(t1) + lb t2, 52(t2) + lb s0, 1024(s0) + lb s1, 1024(s1) + lb a0, 1024(a0) + lb a1, 1024(a1) + lb a2, 1024(a2) + lb a3, 1024(a3) + lb a4, 1024(a4) + lb a5, 1024(a5) + lb a6, 1024(a6) + lb a7, 1024(a7) + lb s2, 52(s2) + lb s3, 52(s3) + lb s4, 52(s4) + lb s5, 72(s5) + lb s6, 76(s6) + lb s7, 80(s7) + lb s8, 84(s8) + lb s9, 88(s9) + lb s10, 92(s10) + lb s11, 96(s11) + lb t3, 12(t3) + lb t4, 16(t4) + lb t5, 12(t5) + lb t6, 16(t6) + li ra, 0x80000000 + li sp, 0x80000000 + li gp, 0x80000000 + li tp, 0x80000000 + li t0, 0x80000000 + li t1, 0x80000000 + li t2, 0x80000000 + li s0, 0x80000000 + li s1, 0x80000000 + li a0, 0x80000000 + li a1, 0x80000000 + li a2, 0x80000000 + li a3, 0x80000000 + li a4, 0x80000000 + li a5, 0x80000000 + li a6, 0x80000000 + li a7, 0x80000000 + li s2, 0x80000000 + li s3, 0x80000000 + li s4, 0x80000000 + li s5, 0x80000000 + li s6, 0x80000000 + li s7, 0x80000000 + li s8, 0x80000000 + li s9, 0x80000000 + li s10, 0x80000000 + li s11, 0x80000000 + li t3, 0x80000000 + li t4, 0x80000000 + li t5, 0x80000000 + li t6, 0x80000000 + lbu zero, -16(zero) + lbu sp, 1024(sp) + lbu ra, 52(ra) + lbu gp, 52(gp) + lbu tp, 52(tp) + lbu t0, 52(t0) + lbu t1, 52(t1) + lbu t2, 52(t2) + lbu s0, 1024(s0) + lbu s1, 1024(s1) + lbu a0, 1024(a0) + lbu a1, 1024(a1) + lbu a2, 1024(a2) + lbu a3, 1024(a3) + lbu a4, 1024(a4) + lbu a5, 1024(a5) + lbu a6, 1024(a6) + lbu a7, 1024(a7) + lbu s2, 52(s2) + lbu s3, 52(s3) + lbu s4, 52(s4) + lbu s5, 72(s5) + lbu s6, 76(s6) + lbu s7, 80(s7) + lbu s8, 84(s8) + lbu s9, 88(s9) + lbu s10, 92(s10) + lbu s11, 96(s11) + lbu t3, 12(t3) + lbu t4, 16(t4) + lbu t5, 12(t5) + lbu t6, 16(t6) + li ra, 0x80000000 + li sp, 0x80000000 + li gp, 0x80000000 + li tp, 0x80000000 + li t0, 0x80000000 + li t1, 0x80000000 + li t2, 0x80000000 + li s0, 0x80000000 + li s1, 0x80000000 + li a0, 0x80000000 + li a1, 0x80000000 + li a2, 0x80000000 + li a3, 0x80000000 + li a4, 0x80000000 + li a5, 0x80000000 + li a6, 0x80000000 + li a7, 0x80000000 + li s2, 0x80000000 + li s3, 0x80000000 + li s4, 0x80000000 + li s5, 0x80000000 + li s6, 0x80000000 + li s7, 0x80000000 + li s8, 0x80000000 + li s9, 0x80000000 + li s10, 0x80000000 + li s11, 0x80000000 + li t3, 0x80000000 + li t4, 0x80000000 + li t5, 0x80000000 + li t6, 0x80000000 + lhu zero, -16(zero) + lhu sp, 1024(sp) + lhu ra, 52(ra) + lhu gp, 52(gp) + lhu tp, 52(tp) + lhu t0, 52(t0) + lhu t1, 52(t1) + lhu t2, 52(t2) + lhu s0, 1024(s0) + lhu s1, 1024(s1) + lhu a0, 1024(a0) + lhu a1, 1024(a1) + lhu a2, 1024(a2) + lhu a3, 1024(a3) + lhu a4, 1024(a4) + lhu a5, 1024(a5) + lhu a6, 1024(a6) + lhu a7, 1024(a7) + lhu s2, 52(s2) + lhu s3, 52(s3) + lhu s4, 52(s4) + lhu s5, 72(s5) + lhu s6, 76(s6) + lhu s7, 80(s7) + lhu s8, 84(s8) + lhu s9, 88(s9) + lhu s10, 92(s10) + lhu s11, 96(s11) + lhu t3, 12(t3) + lhu t4, 16(t4) + lhu t5, 12(t5) + lhu t6, 16(t6) + add t0, s8, t0 + addi s8, t0, -420 + lui s8, 902640 +# (example of) final self-check test + li a0, 0xCAFE; + li a1, 0xCAFE; + xor a2, a0, a1; + beqz a2, pass; + +fail: + # Failure post-processing (messages, ecall setup etc.) + li a0, 0x0; + jal exit; + +pass: + # Success post-processing (messages, ecall setup etc.) + li a0, 0x0; + jal exit; diff --git a/verif/tests/custom/isacov/load_store_test.S b/verif/tests/custom/isacov/load_store_test.S new file mode 100644 index 0000000000..c3b14ce5ff --- /dev/null +++ b/verif/tests/custom/isacov/load_store_test.S @@ -0,0 +1,71 @@ +# Copyright 2023 Thales DIS design services SAS +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Original Author: Ayoub JALALI (ayoub.jalali@external.thalesgroup.com) + +#***************************************************************************** +# load_reg_hazard.S +#----------------------------------------------------------------------------- +# + + .globl main +main: + mulhu s11, t3, s3 + srl a3, s2, gp + c.mv sp, s5 + addi a1, a1, -856 + or s7, t0, a5 + remu a3, s5, t5 + c.nop + li s3, 0x0 #start riscv_int_numeric_corner_stream_0 + li s1, 0xffffffff + li a5, 0x80000000 + li sp, 0x80000000 + li s10, 0x80000000 + li t2, 0xffffffff + li t0, 0x0 + li s6, 0x80000000 + li tp, 0xffffffff + li ra, 0x0 + addi s1, zero,0xffffff00 + c.lwsp sp, 0(sp) + lb t0, 0(s1) + lh t0, 0(s1) + lw t0, 0(s1) + lbu t0, 0(s1) + lhu t0, 0(s1) + sb t0, 0(s1) + sh t0, 0(s1) + sw t0, 0(s1) + sb t0, -16(zero) + sh t0, -16(zero) + sw t0, -16(zero) + addi a0, zero,0xffffff00 + c.sw a2, 124(a0) + c.lw a0, 124(s1) + c.sw a0, 124(s1) + c.sw a0, 124(a5) + mul a5, ra, s1 + divu s6, ra, s6 + auipc s10, 1013927 + sub ra, ra, s10 + div t0, t2, ra +# (example of) final self-check test + li a0, 0xCAFE; + li a1, 0xCAFE; + xor a2, a0, a1; + beqz a2, pass; + +fail: + # Failure post-processing (messages, ecall setup etc.) + li a0, 0x0; + jal exit; + +pass: + # Success post-processing (messages, ecall setup etc.) + li a0, 0x0; + jal exit; diff --git a/verif/tests/custom/issues/compressed-fpreg-commits-rv32.S b/verif/tests/custom/issues/compressed-fpreg-commits-rv32.S new file mode 100644 index 0000000000..5dfed7d07b --- /dev/null +++ b/verif/tests/custom/issues/compressed-fpreg-commits-rv32.S @@ -0,0 +1,32 @@ +# Copyright 2022 Thales DIS France +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Original Author: Zbigniew CHAMSKI (zbigniew.chamski@thalesgroup.fr) + +#***************************************************************************** +# compressed-fpregs-commits-rv32.S +#----------------------------------------------------------------------------- +# + + .globl main +main: + la s1, tohost; + c.flw fs0, 0(s1); + c.flwsp fs0, 0(sp); + xor a2, a0, a0; # trivial PASS... + beqz a2, pass; + +fail: + # Failure post-processing; set retcode to 1. + li a0, 0x1; + jal exit; + +pass: + # Success post-processing: set retcode to 0. + li a0, 0x0; + jal exit; + diff --git a/verif/tests/custom/issues/compressed-fpreg-commits-rv64.S b/verif/tests/custom/issues/compressed-fpreg-commits-rv64.S new file mode 100644 index 0000000000..cceb243da7 --- /dev/null +++ b/verif/tests/custom/issues/compressed-fpreg-commits-rv64.S @@ -0,0 +1,32 @@ +# Copyright 2022 Thales DIS France +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Original Author: Zbigniew CHAMSKI (zbigniew.chamski@thalesgroup.fr) + +#***************************************************************************** +# compressed-fpreg-commits.S +#----------------------------------------------------------------------------- +# + + .globl main +main: + la s1, tohost; + c.fld fs0, 0(s1); + c.fldsp fs1, 0(sp); + xor a2, a0, a0; # trivial PASS... + beqz a2, pass; + +fail: + # Failure post-processing; set retcode to 1. + li a0, 0x1; + jal exit; + +pass: + # Success post-processing: set retcode to 0. + li a0, 0x0; + jal exit; + diff --git a/verif/tests/testlist_custom.yaml b/verif/tests/testlist_custom.yaml new file mode 100644 index 0000000000..b7a06c5225 --- /dev/null +++ b/verif/tests/testlist_custom.yaml @@ -0,0 +1,38 @@ +# Copyright Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# ================================================================================ +# Regression test list format +# -------------------------------------------------------------------------------- +# test : Assembly test name +# description : Description of this test +# gen_opts : Instruction generator options +# iterations : Number of iterations of this test +# no_iss : Enable/disable ISS simulator (Optional) +# gen_test : Test name used by the instruction generator +# asm_tests : Path to directed, hand-coded assembly test file or directory +# rtl_test : RTL simulation test name +# cmp_opts : Compile options passed to the instruction generator +# sim_opts : Simulation options passed to the instruction generator +# no_post_compare : Enable/disable comparison of trace log and ISS log (Optional) +# compare_opts : Options for the RTL & ISS trace comparison +# gcc_opts : gcc compile options +# -------------------------------------------------------------------------------- + +- test: custom_test_template + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -T ../tests/custom/common/test.ld" + asm_tests: <path_var>/custom/hello_world/custom_test_template.S + diff --git a/verif/tests/testlist_cvxif.yaml b/verif/tests/testlist_cvxif.yaml new file mode 100644 index 0000000000..f8861a1025 --- /dev/null +++ b/verif/tests/testlist_cvxif.yaml @@ -0,0 +1,80 @@ +# Copyright 2021 Thales DIS design services SAS +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https:#solderpad.org/licenses/ +# +# Original Author: Zineb EL KACIMI (zineb.el-kacimi@external.thalesgroup.com) + +# ================================================================================ +# Regression test list format +# -------------------------------------------------------------------------------- +# test : Assembly test name +# description : Description of this test +# gen_opts : Instruction generator options +# iterations : Number of iterations of this test +# no_iss : Enable/disable ISS simulator (Optional) +# gen_test : Test name used by the instruction generator +# asm_tests : Path to directed, hand-coded assembly test file or directory +# rtl_test : RTL simulation test name +# cmp_opts : Compile options passed to the instruction generator +# sim_opts : Simulation options passed to the instruction generator +# no_post_compare : Enable/disable comparison of trace log and ISS log (Optional) +# compare_opts : Options for the RTL & ISS trace comparison +# gcc_opts : gcc compile options +# -------------------------------------------------------------------------------- + +- test: cvxif_add_nop + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -T ../tests/custom/common/test.ld" + asm_tests: <path_var>/custom/cv_xif/cvxif_add_nop.S + +- test: cvxif_multi + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -T ../tests/custom/common/test.ld" + asm_tests: <path_var>/custom/cv_xif/cvxif_multi.S + +- test: cvxif_rs3 + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -T ../tests/custom/common/test.ld" + asm_tests: <path_var>/custom/cv_xif/cvxif_rs3.S + +- test: cvxif_exc + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -T ../tests/custom/common/test.ld" + asm_tests: <path_var>/custom/cv_xif/cvxif_exc.S + +- test: cvxif_illegal + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -T ../tests/custom/common/test.ld" + asm_tests: <path_var>/custom/cv_xif/cvxif_illegal.S + +- test: cvxif_nopexc + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -T ../tests/custom/common/test.ld" + asm_tests: <path_var>/custom/cv_xif/cvxif_nopexc.S + +- test: cvxif_issexc + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -T ../tests/custom/common/test.ld" + asm_tests: <path_var>/custom/cv_xif/cvxif_issexc.S + +- test: cvxif_s_mode + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -T ../tests/custom/common/test.ld -lgcc" + asm_tests: <path_var>/custom/cv_xif/cvxif_s_mode.S + +- test: cvxif_u_mode + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -T ../tests/custom/common/test.ld -lgcc" + asm_tests: <path_var>/custom/cv_xif/cvxif_u_mode.S diff --git a/verif/tests/testlist_hwconfig.yaml b/verif/tests/testlist_hwconfig.yaml new file mode 100644 index 0000000000..291915d607 --- /dev/null +++ b/verif/tests/testlist_hwconfig.yaml @@ -0,0 +1,186 @@ +# Copyright Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# ================================================================================ +# Regression test list format +# -------------------------------------------------------------------------------- +# test : Assembly test name +# description : Description of this test +# gen_opts : Instruction generator options +# iterations : Number of iterations of this test +# no_iss : Enable/disable ISS simulator (Optional) +# gen_test : Test name used by the instruction generator +# asm_tests : Path to directed, hand-coded assembly test file or directory +# rtl_test : RTL simulation test name +# cmp_opts : Compile options passed to the instruction generator +# sim_opts : Simulation options passed to the instruction generator +# no_post_compare : Enable/disable comparison of trace log and ISS log (Optional) +# compare_opts : Options for the RTL & ISS trace comparison +# gcc_opts : gcc compile options +# -------------------------------------------------------------------------------- + +#- import: <riscv_dv_root>/target/rv64imc/testlist.yaml + +# ISA tests +- test: rv64ui-p-add + iterations: 1 + needs: + - xlen: 64 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/add.S + +- test: rv32ui-p-add + iterations: 1 + needs: + - xlen: 32 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/add.S + +- test: rv64ui-v-add + iterations: 1 + needs: + - xlen: 64 + - fpu: 1 + - c_ext: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/add.S + +- test: rv32ui-v-add + iterations: 1 + needs: + - xlen: 32 + - fpu: 1 + - c_ext: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/add.S + +- test: rv64ui-p-sw + iterations: 1 + needs: + - xlen: 64 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/sw.S + +- test: rv32ui-p-sw + iterations: 1 + needs: + - xlen: 32 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/sw.S + +- test: rv64ui-p-lw + iterations: 1 + needs: + - xlen: 64 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/lw.S + +- test: rv32ui-p-lw + iterations: 1 + needs: + - xlen: 32 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/lw.S + +- test: rv64um-p-div + iterations: 1 + needs: + - xlen: 64 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64um/div.S + +- test: rv32um-p-div + iterations: 1 + needs: + - xlen: 32 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32um/div.S + +- test: rv64um-p-mul + iterations: 1 + needs: + - xlen: 64 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64um/mul.S + +- test: rv32um-p-mul + iterations: 1 + needs: + - xlen: 32 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32um/mul.S + +- test: rv64uf-p-fcmp + iterations: 1 + needs: + - xlen: 64 + - fpu: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64uf/fcmp.S + +- test: rv32uf-p-fcmp + iterations: 1 + needs: + - xlen: 32 + - fpu: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uf/fcmp.S + +- test: rv64ua-p-amomax_d + iterations: 1 + needs: + - xlen: 64 + - a_ext: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ua/amomax_d.S + +- test: rv32ua-p-amomax_w + iterations: 1 + needs: + - xlen: 32 + - a_ext: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ua/amomax_w.S + +- test: rv64mi-p-csr + iterations: 1 + needs: + - xlen: 64 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64mi/csr.S + +- test: rv32mi-p-csr + iterations: 1 + needs: + - xlen: 32 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32mi/csr.S diff --git a/verif/tests/testlist_isacov.yaml b/verif/tests/testlist_isacov.yaml new file mode 100644 index 0000000000..c9d8d6f039 --- /dev/null +++ b/verif/tests/testlist_isacov.yaml @@ -0,0 +1,50 @@ +# Copyright 2023 Thales DIS design services SAS +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https:#solderpad.org/licenses/ +# +# Original Author: Ayoub JALALI (ayoub.jalali@external.thalesgroup.com) + +# ================================================================================ +# Regression test list format +# -------------------------------------------------------------------------------- +# test : Assembly test name +# description : Description of this test +# gen_opts : Instruction generator options +# iterations : Number of iterations of this test +# no_iss : Enable/disable ISS simulator (Optional) +# gen_test : Test name used by the instruction generator +# asm_tests : Path to directed, hand-coded assembly test file or directory +# rtl_test : RTL simulation test name +# cmp_opts : Compile options passed to the instruction generator +# sim_opts : Simulation options passed to the instruction generator +# no_post_compare : Enable/disable comparison of trace log and ISS log (Optional) +# compare_opts : Options for the RTL & ISS trace comparison +# gcc_opts : gcc compile options +# -------------------------------------------------------------------------------- + +- test: branch_test + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -T ../tests/custom/common/test.ld -lgcc" + asm_tests: <path_var>/custom/isacov/branch_to_zero.S + +- test: load_reg_hazard + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -T ../tests/custom/common/test.ld -lgcc" + asm_tests: <path_var>/custom/isacov/load_reg_hazard.S + +- test: load_store_test + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -T ../tests/custom/common/test.ld -lgcc" + asm_tests: <path_var>/custom/isacov/load_store_test.S + +- test: csr_test + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -T ../tests/custom/common/test.ld -lgcc" + asm_tests: <path_var>/custom/isacov/csr_test.S diff --git a/verif/tests/testlist_issues.yaml b/verif/tests/testlist_issues.yaml new file mode 100644 index 0000000000..e3fc0cefcb --- /dev/null +++ b/verif/tests/testlist_issues.yaml @@ -0,0 +1,44 @@ +# Copyright Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# ================================================================================ +# Regression test list format +# -------------------------------------------------------------------------------- +# test : Assembly test name +# description : Description of this test +# gen_opts : Instruction generator options +# iterations : Number of iterations of this test +# no_iss : Enable/disable ISS simulator (Optional) +# gen_test : Test name used by the instruction generator +# asm_tests : Path to directed, hand-coded assembly test file or directory +# rtl_test : RTL simulation test name +# cmp_opts : Compile options passed to the instruction generator +# sim_opts : Simulation options passed to the instruction generator +# no_post_compare : Enable/disable comparison of trace log and ISS log (Optional) +# compare_opts : Options for the RTL & ISS trace comparison +# gcc_opts : gcc compile options +# -------------------------------------------------------------------------------- + +- test: compressed-fpreg-commits-rv64 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -misa-spec=2.2 -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -T ../tests/custom/common/test.ld -lgcc" + asm_tests: <path_var>/custom/issues/compressed-fpreg-commits-rv64.S + +- test: compressed-fpreg-commits-rv32 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -misa-spec=2.2 -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -T ../tests/custom/common/test.ld -lgcc" + asm_tests: <path_var>/custom/issues/compressed-fpreg-commits-rv32.S + diff --git a/verif/tests/testlist_riscv-arch-test-cv32a60x.yaml b/verif/tests/testlist_riscv-arch-test-cv32a60x.yaml new file mode 100644 index 0000000000..7e2309bbd3 --- /dev/null +++ b/verif/tests/testlist_riscv-arch-test-cv32a60x.yaml @@ -0,0 +1,472 @@ +# Copyright Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# ================================================================================ +# Regression test list format +# -------------------------------------------------------------------------------- +# test : Assembly test name +# description : Description of this test +# gen_opts : Instruction generator options +# iterations : Number of iterations of this test +# no_iss : Enable/disable ISS simulator (Optional) +# gen_test : Test name used by the instruction generator +# asm_tests : Path to directed, hand-coded assembly test file or directory +# rtl_test : RTL simulation test name +# cmp_opts : Compile options passed to the instruction generator +# sim_opts : Simulation options passed to the instruction generator +# no_post_compare : Enable/disable comparison of trace log and ISS log (Optional) +# compare_opts : Options for the RTL & ISS trace comparison +# gcc_opts : gcc compile options +# -------------------------------------------------------------------------------- +## C +- test: rv32im-cadd-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cadd-01.S + +- test: rv32im-caddi-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/caddi-01.S + +- test: rv32im-caddi16sp-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/caddi16sp-01.S + +- test: rv32im-caddi4spn-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/caddi4spn-01.S + +- test: rv32im-cand-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cand-01.S + +- test: rv32im-candi-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/candi-01.S + +- test: rv32im-cbeqz-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cbeqz-01.S + +- test: rv32im-cbnez-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cbnez-01.S + +- test: rv32im-cebreak-01 + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cebreak-01.S + +- test: rv32im-cj-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cj-01.S + +- test: rv32im-cjal-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cjal-01.S + +- test: rv32im-cjalr-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cjalr-01.S + +- test: rv32im-cjr-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cjr-01.S + +- test: rv32im-cli-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cli-01.S + +- test: rv32im-clui-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/clui-01.S + +- test: rv32im-clw-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/clw-01.S + +- test: rv32im-clwsp-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/clwsp-01.S + +- test: rv32im-cmv-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cmv-01.S + +- test: rv32im-cnop-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cnop-01.S + +- test: rv32im-cor-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cor-01.S + +- test: rv32im-cslli-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cslli-01.S + +- test: rv32im-csrai-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/csrai-01.S + +- test: rv32im-csrli-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/csrli-01.S + +- test: rv32im-csub-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/csub-01.S + +- test: rv32im-csw-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/csw-01.S + +- test: rv32im-cswsp-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cswsp-01.S + +- test: rv32im-cxor-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cxor-01.S + + # I +- test: rv32im-add-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/add-01.S + +- test: rv32im-addi-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/addi-01.S + +- test: rv32im-and-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/and-01.S + +- test: rv32im-andi-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/andi-01.S + +- test: rv32im-auipc-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/auipc-01.S + +- test: rv32im-beq-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/beq-01.S + +- test: rv32im-bge-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/bge-01.S + +- test: rv32im-bgeu-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/bgeu-01.S + +- test: rv32im-blt-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/blt-01.S + +- test: rv32im-bltu-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/bltu-01.S + +- test: rv32im-bne-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/bne-01.S + +- test: rv32im-fence-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/fence-01.S + +- test: rv32im-jal-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/jal-01.S + +- test: rv32im-jalr-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/jalr-01.S + +- test: rv32im-lb-align-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/lb-align-01.S + +- test: rv32im-lbu-align-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/lbu-align-01.S + +- test: rv32im-lh-align-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/lh-align-01.S + +- test: rv32im-lhu-align-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/lhu-align-01.S + +- test: rv32im-lui-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/lui-01.S + +- test: rv32im-lw-align-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/lw-align-01.S + +- test: rv32im-or-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/or-01.S + +- test: rv32im-ori-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/ori-01.S + +- test: rv32im-sb-align-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sb-align-01.S + +- test: rv32im-sh-align-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sh-align-01.S + +- test: rv32im-sll-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sll-01.S + +- test: rv32im-slli-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/slli-01.S + +- test: rv32im-slt-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/slt-01.S + +- test: rv32im-slti-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/slti-01.S + +- test: rv32im-sltiu-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sltiu-01.S + +- test: rv32im-sltu-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sltu-01.S + +- test: rv32im-sra-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sra-01.S + +- test: rv32im-srai-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/srai-01.S + +- test: rv32im-srl-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/srl-01.S + +- test: rv32im-srli-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/srli-01.S + +- test: rv32im-sub-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sub-01.S + +- test: rv32im-sw-align-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sw-align-01.S + +- test: rv32im-xor-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/xor-01.S + +- test: rv32im-xori-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/xori-01.S + + # M +- test: rv32im-div-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/M/src/div-01.S + +- test: rv32im-divu-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/M/src/divu-01.S + +- test: rv32im-mul-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/M/src/mul-01.S + +- test: rv32im-mulh-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/M/src/mulh-01.S + +- test: rv32im-mulhsu-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/M/src/mulhsu-01.S + +- test: rv32im-mulhu-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/M/src/mulhu-01.S + +- test: rv32im-rem-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/M/src/rem-01.S + +- test: rv32im-remu-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=32 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/M/src/remu-01.S + diff --git a/verif/tests/testlist_riscv-arch-test-cv64a6_imafdc_sv39.yaml b/verif/tests/testlist_riscv-arch-test-cv64a6_imafdc_sv39.yaml new file mode 100644 index 0000000000..f0665006e5 --- /dev/null +++ b/verif/tests/testlist_riscv-arch-test-cv64a6_imafdc_sv39.yaml @@ -0,0 +1,776 @@ +# Copyright Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# ================================================================================ +# Regression test list format +# -------------------------------------------------------------------------------- +# test : Assembly test name +# description : Description of this test +# gen_opts : Instruction generator options +# iterations : Number of iterations of this test +# no_iss : Enable/disable ISS simulator (Optional) +# gen_test : Test name used by the instruction generator +# asm_tests : Path to directed, hand-coded assembly test file or directory +# rtl_test : RTL simulation test name +# cmp_opts : Compile options passed to the instruction generator +# sim_opts : Simulation options passed to the instruction generator +# no_post_compare : Enable/disable comparison of trace log and ISS log (Optional) +# compare_opts : Options for the RTL & ISS trace comparison +# gcc_opts : gcc compile options +# -------------------------------------------------------------------------------- + +#- import: <riscv_dv_root>/target/rv64imc/testlist.yaml + +##I +- test: rv64i_m-add-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/add-01.S + +- test: rv64i_m-addi-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/addi-01.S + +- test: rv64i_m-addiw-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/addiw-01.S + +- test: rv64i_m-addw-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/addw-01.S + +- test: rv64i_m-and-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/and-01.S + +- test: rv64i_m-andi-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/andi-01.S + +- test: rv64i_m-auipc-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/auipc-01.S + +- test: rv64i_m-beq-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/beq-01.S + +- test: rv64i_m-bge-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/bge-01.S + +- test: rv64i_m-bgeu-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/bgeu-01.S + +- test: rv64i_m-blt-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/blt-01.S + +- test: rv64i_m-bltu-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/bltu-01.S + +- test: rv64i_m-bne-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/bne-01.S + +- test: rv64i_m-fence-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/fence-01.S + +- test: rv64i_m-jal-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/jal-01.S + +- test: rv64i_m-jalr-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/jalr-01.S + +- test: rv64i_m-lb-align01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/lb-align-01.S + +- test: rv64i_m-lbu-align01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/lbu-align-01.S + +- test: rv64i_m-ld-align01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/ld-align-01.S + +- test: rv64i_m-lh-align01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/lh-align-01.S + +- test: rv64i_m-lhu-align01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/lhu-align-01.S + +- test: rv64i_m-lui + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/lui-01.S + +- test: rv64i_m-lw-align01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/lw-align-01.S + +- test: rv64i_m-lb-align01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/lb-align-01.S + +- test: rv64i_m-or + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/or-01.S + +- test: rv64i_m-ori + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/ori-01.S + +- test: rv64i_m-sb-align01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/sb-align-01.S + +- test: rv64i_m-sd-align01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/sd-align-01.S + +- test: rv64i_m-sh-align01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/sh-align-01.S + +- test: rv64i_m-sw-align01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/sw-align-01.S + +- test: rv64i_m-sll + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/sll-01.S + +- test: rv64i_m-slli + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/slli-01.S + +- test: rv64i_m-slliw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/slliw-01.S + +- test: rv64i_m-sllw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/sllw-01.S + +- test: rv64i_m-slt + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/slt-01.S + +- test: rv64i_m-slti + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/slti-01.S + +- test: rv64i_m-sltiu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/sltiu-01.S + +- test: rv64i_m-sltu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/sltu-01.S + +- test: rv64i_m-sra + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/sra-01.S + +- test: rv64i_m-srai + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/srai-01.S + +- test: rv64i_m-sraiw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/sraiw-01.S + +- test: rv64i_m-sraw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/sraw-01.S + +- test: rv64i_m-srl + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/srl-01.S + +- test: rv64i_m-srli + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/srli-01.S + +- test: rv64i_m-srliw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/srliw-01.S + +- test: rv64i_m-srlw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/srlw-01.S + +- test: rv64i_m-sub + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/sub-01.S + +- test: rv64i_m-subw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/subw-01.S + +- test: rv64i_m-xor + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/xor-01.S + +- test: rv64i_m-xori + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/xori-01.S + + #M +- test: rv64i_m-div-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/M/src/div-01.S + +- test: rv64i_m-divu-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/M/src/divu-01.S + +- test: rv64i_m-divuw-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/M/src/divuw-01.S + +- test: rv64i_m-divw-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/M/src/divw-01.S + +- test: rv64i_m-mul-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/M/src/mul-01.S + +- test: rv64i_m-mulh-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/M/src/mulh-01.S + +- test: rv64i_m-mulhsu-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/M/src/mulhsu-01.S + +- test: rv64i_m-mulhu-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/M/src/mulhu-01.S + +- test: rv64i_m-mulw-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/M/src/mulw-01.S + +- test: rv64i_m-rem-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/M/src/rem-01.S + +- test: rv64i_m-remu-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/M/src/remu-01.S + +- test: rv64i_m-remuw-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/M/src/remuw-01.S + +- test: rv64i_m-remw-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/M/src/remw-01.S + + #C +- test: rv64i_m-cadd-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cadd-01.S + +- test: rv64i_m-caddi-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/C/src/caddi-01.S + +- test: rv64i_m-caddi16sp-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/C/src/caddi16sp-01.S + +- test: rv64i_m-caddi4spn-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/C/src/caddi4spn-01.S + +- test: rv64i_m-caddiw-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/C/src/caddiw-01.S + +- test: rv64i_m-caddw-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/C/src/caddw-01.S + +- test: rv64i_m-cand-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cand-01.S + +- test: rv64i_m-candi-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/C/src/candi-01.S + +- test: rv64i_m-cbeqz-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cbeqz-01.S + +- test: rv64i_m-cbnez-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cbnez-01.S + +- test: rv64i_m-cebreak-01 + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cebreak-01.S + +- test: rv64i_m-cj-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cj-01.S + +- test: rv64i_m-cjalr-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cjalr-01.S + +- test: rv64i_m-cjr-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cjr-01.S + +- test: rv64i_m-cld-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cld-01.S + +- test: rv64i_m-cldsp-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cldsp-01.S + +- test: rv64i_m-cli-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cli-01.S + +- test: rv64i_m-clui-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/C/src/clui-01.S + +- test: rv64i_m-clw-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/C/src/clw-01.S + +- test: rv64i_m-clwsp-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/C/src/clwsp-01.S + +- test: rv64i_m-cmv-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cmv-01.S + +- test: rv64i_m-cnop-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cnop-01.S + +- test: rv64i_m-cor-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cor-01.S + +- test: rv64i_m-csd-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/C/src/csd-01.S + +- test: rv64i_m-csdsp-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/C/src/csdsp-01.S + +- test: rv64i_m-cslli-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cslli-01.S + +- test: rv64i_m-csrai-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/C/src/csrai-01.S + +- test: rv64i_m-csrli-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/C/src/csrli-01.S + +- test: rv64i_m-csub-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/C/src/csub-01.S + +- test: rv64i_m-csubw-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/C/src/csubw-01.S + +- test: rv64i_m-csw-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/C/src/csw-01.S + +- test: rv64i_m-cswsp-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cswsp-01.S + +- test: rv64i_m-cxor-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/C/src/cxor-01.S + +#D +- test: rv64i_m-fcvt.d.l_b25-01 + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.d.l_b25-01.S + +- test: rv64i_m-fcvt.d.l_b26-01 + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.d.l_b26-01.S + +- test: rv64i_m-fcvt.d.lu_b25-01 + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.d.lu_b25-01.S + +- test: rv64i_m-fcvt.d.lu_b26-01 + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.d.lu_b26-01.S + +- test: rv64i_m-fcvt.l.d_b1-01 + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.l.d_b1-01.S + +- test: rv64i_m-fcvt.l.d_b22-01.S + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.l.d_b22-01.S + +- test: rv64i_m-fcvt.l.d_b23-01.S + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.l.d_b23-01.S + +- test: rv64i_m-fcvt.l.d_b24-01 + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.l.d_b24-01.S + +- test: rv64i_m-fcvt.l.d_b27-01 + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.l.d_b27-01.S + +- test: rv64i_m-fcvt.l.d_b28-01 + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.l.d_b28-01.S + +- test: rv64i_m-fcvt.l.d_b29-01 + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.l.d_b29-01.S + +- test: rv64i_m-fcvt.lu.d_b1-01 + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.lu.d_b1-01.S + +- test: rv64i_m-fcvt.lu.d_b22-01 + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.lu.d_b22-01.S + +- test: rv64i_m-fcvt.lu.d_b23-01 + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.lu.d_b23-01.S + +- test: rv64i_m-fcvt.lu.d_b24-01 + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.lu.d_b24-01.S + +- test: rv64i_m-fcvt.lu.d_b27-01 + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.lu.d_b27-01.S + +- test: rv64i_m-fcvt.lu.d_b28-01 + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.lu.d_b28-01.S + +- test: rv64i_m-fcvt.lu.d_b29-01 + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.lu.d_b29-01.S + +- test: rv64i_m-fmv.d.x_b25-01 + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fmv.d.x_b25-01.S + +- test: rv64i_m-fmv.d.x_b26-01 + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fmv.d.x_b26-01.S + +- test: rv64i_m-fmv.x.d_b1-01 + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fmv.x.d_b1-01.S + +- test: rv64i_m-fmv.x.d_b22-01 + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fmv.x.d_b22-01.S + +- test: rv64i_m-fmv.x.d_b23-01 + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fmv.x.d_b23-01.S + +- test: rv64i_m-fmv.x.d_b24-01 + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fmv.x.d_b24-01.S + +- test: rv64i_m-fmv.x.d_b27-01 + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fmv.x.d_b27-01.S + +- test: rv64i_m-fmv.x.d_b28-01 + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fmv.x.d_b28-01.S + +- test: rv64i_m-fmv.x.d_b29-01 + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DXLEN=64 -DFLEN=64 -DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-test-suite/env/ -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fmv.x.d_b29-01.S + diff --git a/verif/tests/testlist_riscv-compliance-cv32a60x.yaml b/verif/tests/testlist_riscv-compliance-cv32a60x.yaml new file mode 100644 index 0000000000..dd11dc1321 --- /dev/null +++ b/verif/tests/testlist_riscv-compliance-cv32a60x.yaml @@ -0,0 +1,1131 @@ +# Copyright Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# ================================================================================ +# Regression test list format +# -------------------------------------------------------------------------------- +# test : Assembly test name +# description : Description of this test +# gen_opts : Instruction generator options +# iterations : Number of iterations of this test +# no_iss : Enable/disable ISS simulator (Optional) +# gen_test : Test name used by the instruction generator +# asm_tests : Path to directed, hand-coded assembly test file or directory +# rtl_test : RTL simulation test name +# cmp_opts : Compile options passed to the instruction generator +# sim_opts : Simulation options passed to the instruction generator +# no_post_compare : Enable/disable comparison of trace log and ISS log (Optional) +# compare_opts : Options for the RTL & ISS trace comparison +# gcc_opts : gcc compile options +# -------------------------------------------------------------------------------- + +#- import: <riscv_dv_root>/target/rv64imc/testlist.yaml + +- test: rv64im-REMUW + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv64im/src/REMUW.S + +- test: rv64im-MULW + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv64im/src/MULW.S + +- test: rv64i-SRAW + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv64i/src/SRAW.S + +- test: rv64i-ADDW + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv64i/src/ADDW.S + +- test: rv64i-ADDIW + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv64i/src/ADDIW.S + +- test: rv64i-SLLW + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv64i/src/SLLW.S + +- test: rv64i-SUBW + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv64i/src/SUBW.S + +- test: rv64i-SRLW + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv64i/src/SRLW.S + +- test: rv64i-SLLIW + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv64i/src/SLLIW.S + +- test: rv64i-SRLIW + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv64i/src/SRLIW.S + +- test: rv64i-SRAIW + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv64i/src/SRAIW.S + +- test: rv32uc-rvc + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32uc/src/rvc.S + +- test: rv32Zifencei-I-FENCE.I-01 # FAILED on spike + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32Zifencei/src/I-FENCE.I-01.S + +- test: rv32im-MULHSU + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32im/src/MULHSU.S + +- test: rv32im-DIVU + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32im/src/DIVU.S + +- test: rv32im-REMU + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32im/src/REMU.S + +- test: rv32im-MUL + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32im/src/MUL.S + +- test: rv32im-DIV + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32im/src/DIV.S + +- test: rv32im-MULH + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32im/src/MULH.S + +- test: rv32im-MULHU + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32im/src/MULHU.S + +- test: rv32im-REM + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32im/src/REM.S + +- test: rv32ui-jal + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/jal.S + +- test: rv32ui-bge + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/bge.S + +- test: rv32ui-blt + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/blt.S + +- test: rv32ui-bgeu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/bgeu.S + +- test: rv32ui-sw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/sw.S + +- test: rv32ui-lbu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/lbu.S + +- test: rv32ui-sb + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/sb.S + +- test: rv32ui-sw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/slti.S + +- test: rv32ui-sra + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/sra.S + +- test: rv32ui-srl + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/srl.S + +- test: rv32ui-sh + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/sh.S + +- test: rv32ui-lw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/lw.S + +- test: rv32ui-andi + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/andi.S + +- test: rv32ui-srli + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/srli.S + +- test: rv32ui-slli + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/slli.S + +- test: rv32ui-beq + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/beq.S + +- test: rv32ui-sll + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/sll.S + +- test: rv32ui-addi + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/addi.S + +- test: rv32ui-lh + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/lh.S + +- test: rv32ui-and + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/and.S + +- test: rv32ui-xori + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/xori.S + +- test: rv32ui-sub + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/sub.S + +- test: rv32ui-slt + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/slt.S + +- test: rv32ui-lb + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/lb.S + +- test: rv32ui-or + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/or.S + +- test: rv32ui-lui + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/lui.S + +- test: rv32ui-ori + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/ori.S + +- test: rv32ui-bltu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/bltu.S + +- test: rv32ui-fence_i + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/fence_i.S + +- test: rv32ui-auipc + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/auipc.S + +- test: rv32ui-srai + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/srai.S + +- test: rv32ui-jalr + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/jalr.S + +- test: rv32ui-xor + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/xor.S + +- test: rv32ui-simple + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/simple.S + +- test: rv32ui-lhu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/lhu.S + +- test: rv32ui-bne + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/bne.S + +- test: rv32ui-add + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/add.S + +- test: rv32ui-sltiu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/sltiu.S + +- test: rv32ui-sltu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/sltu.S + +- test: rv32mi-sbreak + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32mi/src/sbreak.S + +- test: rv32mi-breakpoint + iterations: 0 # csrr a0, tdata1 => 0x20000000 (spike), 0x00000000 (cva6) + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32mi/src/breakpoint.S + +- test: rv32mi-scall + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32mi/src/scall.S + +- test: rv32mi-ma_addr + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32mi/src/ma_addr.S + +- test: rv32mi-mcsr + iterations: 0 # expected as different marchid + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32mi/src/mcsr.S + +- test: rv32mi-ma_fetch + iterations: 0 # expected as different misa + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32mi/src/ma_fetch.S + +- test: rv32mi-shamt + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32mi/src/shamt.S + +- test: rv32mi-illegal + iterations: 0 # cva6 does not record illegal instructions in log file + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32mi/src/illegal.S + +- test: rv32mi-csr + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32mi/src/csr.S + +- test: rv32i-I-AND-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-AND-01.S + +- test: rv32i-I-BNE-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-BNE-01.S + +- test: rv32i-I-IO + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-IO.S + +- test: rv32i-I-BLT-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-BLT-01.S + +- test: rv32i-I-SB-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SB-01.S + +- test: rv32i-I-MISALIGN_LDST-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-MISALIGN_LDST-01.S + +- test: rv32i-I-ECALL-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-ECALL-01.S + +- test: rv32i-I-LHU-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-LHU-01.S + +- test: rv32i-I-SRLI-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SRLI-01.S + +- test: rv32i-I-BLTU-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-BLTU-01.S + +- test: rv32i-I-LH-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-LH-01.S + +- test: rv32i-I-AUIPC-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-AUIPC-01.S + +- test: rv32i-I-ORI-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-ORI-01.S + +- test: rv32i-I-SLLI-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SLLI-01.S + +- test: rv32i-I-RF_width-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-RF_width-01.S + +- test: rv32i-I-XOR-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-XOR-01.S + +- test: rv32i-I-DELAY_SLOTS-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-DELAY_SLOTS-01.S + +- test: rv32i-I-EBREAK-01 # infinite loop with spike + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-EBREAK-01.S + +- test: rv32i-I-SRAI-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SRAI-01.S + +- test: rv32i-I-SLTU-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SLTU-01.S + +- test: rv32i-I-OR-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-OR-01.S + +- test: rv32i-I-MISALIGN_JMP-01 # infinite loop with spike + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-MISALIGN_JMP-01.S + +- test: rv32i-I-JALR-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-JALR-01.S + +- test: rv32i-I-XORI-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-XORI-01.S + +- test: rv32i-I-ADDI-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-ADDI-01.S + +- test: rv32i-I-BGE-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-BGE-01.S + +- test: rv32i-I-ANDI-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-ANDI-01.S + +- test: rv32i-I-SH-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SH-01.S + +- test: rv32i-I-SLT-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SLT-01.S + +- test: rv32i-I-SLTIU-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SLTIU-01.S + +- test: rv32i-I-SLL-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SLL-01.S + +- test: rv32i-I-SRL-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SRL-01.S + +- test: rv32i-I-LUI-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-LUI-01.S + +- test: rv32i-I-SUB-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SUB-01.S + +- test: rv32i-I-LB-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-LB-01.S + +- test: rv32i-I-LW-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-LW-01.S + +- test: rv32i-I-SW-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SW-01.S + +- test: rv32i-I-SLTI-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SLTI-01.S + +- test: rv32i-I-SRA-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SRA-01.S + +- test: rv32i-I-RF_size-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-RF_size-01.S + +- test: rv32i-I-BEQ-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-BEQ-01.S + +- test: rv32i-I-BGEU-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-BGEU-01.S + +- test: rv32i-I-JAL-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-JAL-01.S + +- test: rv32i-I-LBU-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-LBU-01.S + +- test: rv32i-I-ENDIANESS-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-ENDIANESS-01.S + +- test: rv32i-I-RF_x0-01 # assembly error + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-RF_x0-01.S + +- test: rv32i-I-NOP-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-NOP-01.S + +- test: rv32i-I-ADD-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-ADD-01.S + +- test: rv32si-sbreak + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32si/src/sbreak.S + +- test: rv32si-scall + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32si/src/scall.S + +- test: rv32si-ma_fetch + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32si/src/ma_fetch.S + +- test: rv32si-wfi + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32si/src/wfi.S + +- test: rv32si-dirty + iterations: 0 # exception on spike + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32si/src/dirty.S + +- test: rv32si-csr + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32si/src/csr.S + +- test: rv32imc-C-LW + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-LW.S + +- test: rv32imc-C-LWSP + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-LWSP.S + +- test: rv32imc-C-ADD + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-ADD.S + +- test: rv32imc-C-JAL # assembly error + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-JAL.S + +- test: rv32imc-C-SRAI + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-SRAI.S + +- test: rv32imc-C-JALR + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-JALR.S + +- test: rv32imc-C-XOR + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-XOR.S + +- test: rv32imc-C-SUB + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-SUB.S + +- test: rv32imc-C-ADDI + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-ADDI.S + +- test: rv32imc-C-BEQZ + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-BEQZ.S + +- test: rv32imc-C-ADDI16SP + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-ADDI16SP.S + +- test: rv32imc-C-LI + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-LI.S + +- test: rv32imc-C-SW + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-SW.S + +- test: rv32imc-C-OR + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-OR.S + +- test: rv32imc-C-ADDI4SPN + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-ADDI4SPN.S + +- test: rv32imc-C-AND + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-AND.S + +- test: rv32imc-C-SRLI + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-SRLI.S + +- test: rv32imc-C-SWSP + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-SWSP.S + +- test: rv32imc-C-SLLI + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-SLLI.S + +- test: rv32imc-C-JR + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-JR.S + +- test: rv32imc-C-BNEZ + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-BNEZ.S + +- test: rv32imc-C-MV + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-MV.S + +- test: rv32imc-C-LUI + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-LUI.S + +- test: rv32imc-C-J + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-J.S + +- test: rv32imc-C-ANDI + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-ANDI.S + +- test: rv32Zicsr-I-CSRRC-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32Zicsr/src/I-CSRRC-01.S + +- test: rv32Zicsr-I-CSRRS-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32Zicsr/src/I-CSRRS-01.S + +- test: rv32Zicsr-I-CSRRSI-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32Zicsr/src/I-CSRRSI-01.S + +- test: rv32Zicsr-I-CSRRW-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32Zicsr/src/I-CSRRW-01.S + +- test: rv32Zicsr-I-CSRRCI-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32Zicsr/src/I-CSRRCI-01.S + +- test: rv32Zicsr-I-CSRRWI-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32Zicsr/src/I-CSRRWI-01.S + +- test: rv32ua-amoxor_w + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ua/src/amoxor_w.S + +- test: rv32ua-amoadd_w + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ua/src/amoadd_w.S + +- test: rv32ua-amoor_w + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ua/src/amoor_w.S + +- test: rv32ua-amomin_w + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ua/src/amomin_w.S + +- test: rv32ua-amoand_w + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ua/src/amoand_w.S + +- test: rv32ua-amomaxu_w + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ua/src/amomaxu_w.S + +- test: rv32ua-amoswap_w + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ua/src/amoswap_w.S + +- test: rv32ua-amominu_w + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ua/src/amominu_w.S + +- test: rv32ua-amomax_w + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ua/src/amomax_w.S + +- test: rv32uf-fclass + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32uf/src/fclass.S + +- test: rv32uf-ldst + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32uf/src/ldst.S + +- test: rv32uf-fmadd + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32uf/src/fmadd.S + +- test: rv32uf-recoding + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32uf/src/recoding.S + +- test: rv32uf-fcvt + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32uf/src/fcvt.S + +- test: rv32uf-fcmp + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32uf/src/fcmp.S + +- test: rv32uf-fcvt_w + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32uf/src/fcvt_w.S + +- test: rv32uf-fadd + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32uf/src/fadd.S + +- test: rv32uf-fmin + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32uf/src/fmin.S + +- test: rv32uf-move + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32uf/src/move.S + +- test: rv32uf-fdiv + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32uf/src/fdiv.S + +- test: rv32ud-fclass + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ud/src/fclass.S + +- test: rv32ud-ldst + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ud/src/ldst.S + +- test: rv32ud-fmadd + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ud/src/fmadd.S + +- test: rv32ud-recoding + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ud/src/recoding.S + +- test: rv32ud-fcvt + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ud/src/fcvt.S + +- test: rv32ud-fcmp + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ud/src/fcmp.S + +- test: rv32ud-fadd + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ud/src/fadd.S + +- test: rv32ud-fmin + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ud/src/fmin.S + +- test: rv32ud-fdiv + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ud/src/fdiv.S diff --git a/verif/tests/testlist_riscv-compliance-cv32a6_imac_sv0.yaml b/verif/tests/testlist_riscv-compliance-cv32a6_imac_sv0.yaml new file mode 100644 index 0000000000..1bfce7d8fd --- /dev/null +++ b/verif/tests/testlist_riscv-compliance-cv32a6_imac_sv0.yaml @@ -0,0 +1,1131 @@ +# Copyright Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# ================================================================================ +# Regression test list format +# -------------------------------------------------------------------------------- +# test : Assembly test name +# description : Description of this test +# gen_opts : Instruction generator options +# iterations : Number of iterations of this test +# no_iss : Enable/disable ISS simulator (Optional) +# gen_test : Test name used by the instruction generator +# asm_tests : Path to directed, hand-coded assembly test file or directory +# rtl_test : RTL simulation test name +# cmp_opts : Compile options passed to the instruction generator +# sim_opts : Simulation options passed to the instruction generator +# no_post_compare : Enable/disable comparison of trace log and ISS log (Optional) +# compare_opts : Options for the RTL & ISS trace comparison +# gcc_opts : gcc compile options +# -------------------------------------------------------------------------------- + +#- import: <riscv_dv_root>/target/rv64imc/testlist.yaml + +- test: rv64im-REMUW + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv64im/src/REMUW.S + +- test: rv64im-MULW + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv64im/src/MULW.S + +- test: rv64i-SRAW + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv64i/src/SRAW.S + +- test: rv64i-ADDW + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv64i/src/ADDW.S + +- test: rv64i-ADDIW + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv64i/src/ADDIW.S + +- test: rv64i-SLLW + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv64i/src/SLLW.S + +- test: rv64i-SUBW + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv64i/src/SUBW.S + +- test: rv64i-SRLW + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv64i/src/SRLW.S + +- test: rv64i-SLLIW + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv64i/src/SLLIW.S + +- test: rv64i-SRLIW + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv64i/src/SRLIW.S + +- test: rv64i-SRAIW + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv64i/src/SRAIW.S + +- test: rv32uc-rvc + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32uc/src/rvc.S + +- test: rv32Zifencei-I-FENCE.I-01 # FAILED on spike + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32Zifencei/src/I-FENCE.I-01.S + +- test: rv32im-MULHSU + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32im/src/MULHSU.S + +- test: rv32im-DIVU + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32im/src/DIVU.S + +- test: rv32im-REMU + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32im/src/REMU.S + +- test: rv32im-MUL + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32im/src/MUL.S + +- test: rv32im-DIV + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32im/src/DIV.S + +- test: rv32im-MULH + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32im/src/MULH.S + +- test: rv32im-MULHU + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32im/src/MULHU.S + +- test: rv32im-REM + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32im/src/REM.S + +- test: rv32ui-jal + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/jal.S + +- test: rv32ui-bge + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/bge.S + +- test: rv32ui-blt + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/blt.S + +- test: rv32ui-bgeu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/bgeu.S + +- test: rv32ui-sw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/sw.S + +- test: rv32ui-lbu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/lbu.S + +- test: rv32ui-sb + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/sb.S + +- test: rv32ui-sw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/slti.S + +- test: rv32ui-sra + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/sra.S + +- test: rv32ui-srl + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/srl.S + +- test: rv32ui-sh + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/sh.S + +- test: rv32ui-lw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/lw.S + +- test: rv32ui-andi + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/andi.S + +- test: rv32ui-srli + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/srli.S + +- test: rv32ui-slli + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/slli.S + +- test: rv32ui-beq + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/beq.S + +- test: rv32ui-sll + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/sll.S + +- test: rv32ui-addi + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/addi.S + +- test: rv32ui-lh + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/lh.S + +- test: rv32ui-and + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/and.S + +- test: rv32ui-xori + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/xori.S + +- test: rv32ui-sub + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/sub.S + +- test: rv32ui-slt + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/slt.S + +- test: rv32ui-lb + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/lb.S + +- test: rv32ui-or + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/or.S + +- test: rv32ui-lui + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/lui.S + +- test: rv32ui-ori + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/ori.S + +- test: rv32ui-bltu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/bltu.S + +- test: rv32ui-fence_i + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/fence_i.S + +- test: rv32ui-auipc + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/auipc.S + +- test: rv32ui-srai + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/srai.S + +- test: rv32ui-jalr + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/jalr.S + +- test: rv32ui-xor + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/xor.S + +- test: rv32ui-simple + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/simple.S + +- test: rv32ui-lhu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/lhu.S + +- test: rv32ui-bne + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/bne.S + +- test: rv32ui-add + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/add.S + +- test: rv32ui-sltiu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/sltiu.S + +- test: rv32ui-sltu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/sltu.S + +- test: rv32mi-sbreak + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32mi/src/sbreak.S + +- test: rv32mi-breakpoint + iterations: 0 # csrr a0, tdata1 => 0x20000000 (spike), 0x00000000 (cva6) + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32mi/src/breakpoint.S + +- test: rv32mi-scall + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32mi/src/scall.S + +- test: rv32mi-ma_addr + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32mi/src/ma_addr.S + +- test: rv32mi-mcsr + iterations: 0 # expected as different marchid + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32mi/src/mcsr.S + +- test: rv32mi-ma_fetch + iterations: 0 # expected as different misa + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32mi/src/ma_fetch.S + +- test: rv32mi-shamt + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32mi/src/shamt.S + +- test: rv32mi-illegal + iterations: 0 # cva6 does not record illegal instructions in log file + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32mi/src/illegal.S + +- test: rv32mi-csr + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32mi/src/csr.S + +- test: rv32i-I-AND-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-AND-01.S + +- test: rv32i-I-BNE-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-BNE-01.S + +- test: rv32i-I-IO + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-IO.S + +- test: rv32i-I-BLT-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-BLT-01.S + +- test: rv32i-I-SB-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SB-01.S + +- test: rv32i-I-MISALIGN_LDST-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-MISALIGN_LDST-01.S + +- test: rv32i-I-ECALL-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-ECALL-01.S + +- test: rv32i-I-LHU-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-LHU-01.S + +- test: rv32i-I-SRLI-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SRLI-01.S + +- test: rv32i-I-BLTU-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-BLTU-01.S + +- test: rv32i-I-LH-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-LH-01.S + +- test: rv32i-I-AUIPC-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-AUIPC-01.S + +- test: rv32i-I-ORI-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-ORI-01.S + +- test: rv32i-I-SLLI-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SLLI-01.S + +- test: rv32i-I-RF_width-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-RF_width-01.S + +- test: rv32i-I-XOR-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-XOR-01.S + +- test: rv32i-I-DELAY_SLOTS-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-DELAY_SLOTS-01.S + +- test: rv32i-I-EBREAK-01 # infinite loop with spike + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-EBREAK-01.S + +- test: rv32i-I-SRAI-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SRAI-01.S + +- test: rv32i-I-SLTU-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SLTU-01.S + +- test: rv32i-I-OR-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-OR-01.S + +- test: rv32i-I-MISALIGN_JMP-01 # infinite loop with spike + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-MISALIGN_JMP-01.S + +- test: rv32i-I-JALR-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-JALR-01.S + +- test: rv32i-I-XORI-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-XORI-01.S + +- test: rv32i-I-ADDI-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-ADDI-01.S + +- test: rv32i-I-BGE-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-BGE-01.S + +- test: rv32i-I-ANDI-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-ANDI-01.S + +- test: rv32i-I-SH-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SH-01.S + +- test: rv32i-I-SLT-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SLT-01.S + +- test: rv32i-I-SLTIU-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SLTIU-01.S + +- test: rv32i-I-SLL-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SLL-01.S + +- test: rv32i-I-SRL-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SRL-01.S + +- test: rv32i-I-LUI-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-LUI-01.S + +- test: rv32i-I-SUB-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SUB-01.S + +- test: rv32i-I-LB-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-LB-01.S + +- test: rv32i-I-LW-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-LW-01.S + +- test: rv32i-I-SW-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SW-01.S + +- test: rv32i-I-SLTI-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SLTI-01.S + +- test: rv32i-I-SRA-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SRA-01.S + +- test: rv32i-I-RF_size-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-RF_size-01.S + +- test: rv32i-I-BEQ-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-BEQ-01.S + +- test: rv32i-I-BGEU-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-BGEU-01.S + +- test: rv32i-I-JAL-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-JAL-01.S + +- test: rv32i-I-LBU-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-LBU-01.S + +- test: rv32i-I-ENDIANESS-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-ENDIANESS-01.S + +- test: rv32i-I-RF_x0-01 # assembly error + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-RF_x0-01.S + +- test: rv32i-I-NOP-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-NOP-01.S + +- test: rv32i-I-ADD-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-ADD-01.S + +- test: rv32si-sbreak + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32si/src/sbreak.S + +- test: rv32si-scall + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32si/src/scall.S + +- test: rv32si-ma_fetch + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32si/src/ma_fetch.S + +- test: rv32si-wfi + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32si/src/wfi.S + +- test: rv32si-dirty + iterations: 0 # exception on spike + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32si/src/dirty.S + +- test: rv32si-csr + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32si/src/csr.S + +- test: rv32imc-C-LW + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-LW.S + +- test: rv32imc-C-LWSP + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-LWSP.S + +- test: rv32imc-C-ADD + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-ADD.S + +- test: rv32imc-C-JAL # assembly error + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-JAL.S + +- test: rv32imc-C-SRAI + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-SRAI.S + +- test: rv32imc-C-JALR + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-JALR.S + +- test: rv32imc-C-XOR + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-XOR.S + +- test: rv32imc-C-SUB + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-SUB.S + +- test: rv32imc-C-ADDI + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-ADDI.S + +- test: rv32imc-C-BEQZ + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-BEQZ.S + +- test: rv32imc-C-ADDI16SP + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-ADDI16SP.S + +- test: rv32imc-C-LI + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-LI.S + +- test: rv32imc-C-SW + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-SW.S + +- test: rv32imc-C-OR + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-OR.S + +- test: rv32imc-C-ADDI4SPN + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-ADDI4SPN.S + +- test: rv32imc-C-AND + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-AND.S + +- test: rv32imc-C-SRLI + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-SRLI.S + +- test: rv32imc-C-SWSP + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-SWSP.S + +- test: rv32imc-C-SLLI + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-SLLI.S + +- test: rv32imc-C-JR + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-JR.S + +- test: rv32imc-C-BNEZ + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-BNEZ.S + +- test: rv32imc-C-MV + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-MV.S + +- test: rv32imc-C-LUI + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-LUI.S + +- test: rv32imc-C-J + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-J.S + +- test: rv32imc-C-ANDI + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-ANDI.S + +- test: rv32Zicsr-I-CSRRC-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32Zicsr/src/I-CSRRC-01.S + +- test: rv32Zicsr-I-CSRRS-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32Zicsr/src/I-CSRRS-01.S + +- test: rv32Zicsr-I-CSRRSI-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32Zicsr/src/I-CSRRSI-01.S + +- test: rv32Zicsr-I-CSRRW-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32Zicsr/src/I-CSRRW-01.S + +- test: rv32Zicsr-I-CSRRCI-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32Zicsr/src/I-CSRRCI-01.S + +- test: rv32Zicsr-I-CSRRWI-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32Zicsr/src/I-CSRRWI-01.S + +- test: rv32ua-amoxor_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ua/src/amoxor_w.S + +- test: rv32ua-amoadd_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ua/src/amoadd_w.S + +- test: rv32ua-amoor_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ua/src/amoor_w.S + +- test: rv32ua-amomin_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ua/src/amomin_w.S + +- test: rv32ua-amoand_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ua/src/amoand_w.S + +- test: rv32ua-amomaxu_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ua/src/amomaxu_w.S + +- test: rv32ua-amoswap_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ua/src/amoswap_w.S + +- test: rv32ua-amominu_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ua/src/amominu_w.S + +- test: rv32ua-amomax_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ua/src/amomax_w.S + +- test: rv32uf-fclass + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32uf/src/fclass.S + +- test: rv32uf-ldst + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32uf/src/ldst.S + +- test: rv32uf-fmadd + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32uf/src/fmadd.S + +- test: rv32uf-recoding + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32uf/src/recoding.S + +- test: rv32uf-fcvt + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32uf/src/fcvt.S + +- test: rv32uf-fcmp + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32uf/src/fcmp.S + +- test: rv32uf-fcvt_w + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32uf/src/fcvt_w.S + +- test: rv32uf-fadd + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32uf/src/fadd.S + +- test: rv32uf-fmin + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32uf/src/fmin.S + +- test: rv32uf-move + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32uf/src/move.S + +- test: rv32uf-fdiv + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32uf/src/fdiv.S + +- test: rv32ud-fclass + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ud/src/fclass.S + +- test: rv32ud-ldst + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ud/src/ldst.S + +- test: rv32ud-fmadd + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ud/src/fmadd.S + +- test: rv32ud-recoding + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ud/src/recoding.S + +- test: rv32ud-fcvt + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ud/src/fcvt.S + +- test: rv32ud-fcmp + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ud/src/fcmp.S + +- test: rv32ud-fadd + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ud/src/fadd.S + +- test: rv32ud-fmin + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ud/src/fmin.S + +- test: rv32ud-fdiv + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ud/src/fdiv.S diff --git a/verif/tests/testlist_riscv-compliance-cv64a6_imafdc_sv39.yaml b/verif/tests/testlist_riscv-compliance-cv64a6_imafdc_sv39.yaml new file mode 100644 index 0000000000..b7a6d3df9f --- /dev/null +++ b/verif/tests/testlist_riscv-compliance-cv64a6_imafdc_sv39.yaml @@ -0,0 +1,1131 @@ +# Copyright Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# ================================================================================ +# Regression test list format +# -------------------------------------------------------------------------------- +# test : Assembly test name +# description : Description of this test +# gen_opts : Instruction generator options +# iterations : Number of iterations of this test +# no_iss : Enable/disable ISS simulator (Optional) +# gen_test : Test name used by the instruction generator +# asm_tests : Path to directed, hand-coded assembly test file or directory +# rtl_test : RTL simulation test name +# cmp_opts : Compile options passed to the instruction generator +# sim_opts : Simulation options passed to the instruction generator +# no_post_compare : Enable/disable comparison of trace log and ISS log (Optional) +# compare_opts : Options for the RTL & ISS trace comparison +# gcc_opts : gcc compile options +# -------------------------------------------------------------------------------- + +#- import: <riscv_dv_root>/target/rv64imc/testlist.yaml + +- test: rv64im-REMUW + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv64im/src/REMUW.S + +- test: rv64im-MULW + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv64im/src/MULW.S + +- test: rv64i-SRAW + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv64i/src/SRAW.S + +- test: rv64i-ADDW + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv64i/src/ADDW.S + +- test: rv64i-ADDIW + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv64i/src/ADDIW.S + +- test: rv64i-SLLW + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv64i/src/SLLW.S + +- test: rv64i-SUBW + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv64i/src/SUBW.S + +- test: rv64i-SRLW + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv64i/src/SRLW.S + +- test: rv64i-SLLIW + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv64i/src/SLLIW.S + +- test: rv64i-SRLIW + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv64i/src/SRLIW.S + +- test: rv64i-SRAIW + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv64i/src/SRAIW.S + +- test: rv32uc-rvc + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32uc/src/rvc.S + +- test: rv32Zifencei-I-FENCE.I-01 # FAILED on spike + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32Zifencei/src/I-FENCE.I-01.S + +- test: rv32im-MULHSU + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32im/src/MULHSU.S + +- test: rv32im-DIVU + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32im/src/DIVU.S + +- test: rv32im-REMU + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32im/src/REMU.S + +- test: rv32im-MUL + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32im/src/MUL.S + +- test: rv32im-DIV + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32im/src/DIV.S + +- test: rv32im-MULH + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32im/src/MULH.S + +- test: rv32im-MULHU + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32im/src/MULHU.S + +- test: rv32im-REM + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32im/src/REM.S + +- test: rv32ui-jal + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/jal.S + +- test: rv32ui-bge + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/bge.S + +- test: rv32ui-blt + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/blt.S + +- test: rv32ui-bgeu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/bgeu.S + +- test: rv32ui-sw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/sw.S + +- test: rv32ui-lbu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/lbu.S + +- test: rv32ui-sb + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/sb.S + +- test: rv32ui-sw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/slti.S + +- test: rv32ui-sra + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/sra.S + +- test: rv32ui-srl + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/srl.S + +- test: rv32ui-sh + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/sh.S + +- test: rv32ui-lw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/lw.S + +- test: rv32ui-andi + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/andi.S + +- test: rv32ui-srli + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/srli.S + +- test: rv32ui-slli + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/slli.S + +- test: rv32ui-beq + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/beq.S + +- test: rv32ui-sll + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/sll.S + +- test: rv32ui-addi + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/addi.S + +- test: rv32ui-lh + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/lh.S + +- test: rv32ui-and + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/and.S + +- test: rv32ui-xori + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/xori.S + +- test: rv32ui-sub + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/sub.S + +- test: rv32ui-slt + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/slt.S + +- test: rv32ui-lb + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/lb.S + +- test: rv32ui-or + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/or.S + +- test: rv32ui-lui + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/lui.S + +- test: rv32ui-ori + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/ori.S + +- test: rv32ui-bltu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/bltu.S + +- test: rv32ui-fence_i + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/fence_i.S + +- test: rv32ui-auipc + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/auipc.S + +- test: rv32ui-srai + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/srai.S + +- test: rv32ui-jalr + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/jalr.S + +- test: rv32ui-xor + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/xor.S + +- test: rv32ui-simple + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/simple.S + +- test: rv32ui-lhu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/lhu.S + +- test: rv32ui-bne + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/bne.S + +- test: rv32ui-add + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/add.S + +- test: rv32ui-sltiu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/sltiu.S + +- test: rv32ui-sltu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/sltu.S + +- test: rv32mi-sbreak + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32mi/src/sbreak.S + +- test: rv32mi-breakpoint + iterations: 0 # csrr a0, tdata1 => 0x2000000000000000 (spike), 0x0000000000000000 (cva6) + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32mi/src/breakpoint.S + +- test: rv32mi-scall + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32mi/src/scall.S + +- test: rv32mi-ma_addr + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32mi/src/ma_addr.S + +- test: rv32mi-mcsr + iterations: 0 # expected as different marchid + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32mi/src/mcsr.S + +- test: rv32mi-ma_fetch + iterations: 0 # expected as different misa + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32mi/src/ma_fetch.S + +- test: rv32mi-shamt + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32mi/src/shamt.S + +- test: rv32mi-illegal + iterations: 0 # cva6 does not record illegal instructions in log file + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32mi/src/illegal.S + +- test: rv32mi-csr + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32mi/src/csr.S + +- test: rv32i-I-AND-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-AND-01.S + +- test: rv32i-I-BNE-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-BNE-01.S + +- test: rv32i-I-IO + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-IO.S + +- test: rv32i-I-BLT-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-BLT-01.S + +- test: rv32i-I-SB-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SB-01.S + +- test: rv32i-I-MISALIGN_LDST-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-MISALIGN_LDST-01.S + +- test: rv32i-I-ECALL-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-ECALL-01.S + +- test: rv32i-I-LHU-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-LHU-01.S + +- test: rv32i-I-SRLI-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SRLI-01.S + +- test: rv32i-I-BLTU-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-BLTU-01.S + +- test: rv32i-I-LH-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-LH-01.S + +- test: rv32i-I-AUIPC-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-AUIPC-01.S + +- test: rv32i-I-ORI-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-ORI-01.S + +- test: rv32i-I-SLLI-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SLLI-01.S + +- test: rv32i-I-RF_width-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-RF_width-01.S + +- test: rv32i-I-XOR-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-XOR-01.S + +- test: rv32i-I-DELAY_SLOTS-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-DELAY_SLOTS-01.S + +- test: rv32i-I-EBREAK-01 # infinite loop with spike + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-EBREAK-01.S + +- test: rv32i-I-SRAI-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SRAI-01.S + +- test: rv32i-I-SLTU-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SLTU-01.S + +- test: rv32i-I-OR-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-OR-01.S + +- test: rv32i-I-MISALIGN_JMP-01 # infinite loop with spike + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-MISALIGN_JMP-01.S + +- test: rv32i-I-JALR-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-JALR-01.S + +- test: rv32i-I-XORI-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-XORI-01.S + +- test: rv32i-I-ADDI-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-ADDI-01.S + +- test: rv32i-I-BGE-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-BGE-01.S + +- test: rv32i-I-ANDI-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-ANDI-01.S + +- test: rv32i-I-SH-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SH-01.S + +- test: rv32i-I-SLT-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SLT-01.S + +- test: rv32i-I-SLTIU-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SLTIU-01.S + +- test: rv32i-I-SLL-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SLL-01.S + +- test: rv32i-I-SRL-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SRL-01.S + +- test: rv32i-I-LUI-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-LUI-01.S + +- test: rv32i-I-SUB-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SUB-01.S + +- test: rv32i-I-LB-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-LB-01.S + +- test: rv32i-I-LW-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-LW-01.S + +- test: rv32i-I-SW-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SW-01.S + +- test: rv32i-I-SLTI-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SLTI-01.S + +- test: rv32i-I-SRA-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SRA-01.S + +- test: rv32i-I-RF_size-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-RF_size-01.S + +- test: rv32i-I-BEQ-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-BEQ-01.S + +- test: rv32i-I-BGEU-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-BGEU-01.S + +- test: rv32i-I-JAL-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-JAL-01.S + +- test: rv32i-I-LBU-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-LBU-01.S + +- test: rv32i-I-ENDIANESS-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-ENDIANESS-01.S + +- test: rv32i-I-RF_x0-01 # assembly error + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-RF_x0-01.S + +- test: rv32i-I-NOP-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-NOP-01.S + +- test: rv32i-I-ADD-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-ADD-01.S + +- test: rv32si-sbreak + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32si/src/sbreak.S + +- test: rv32si-scall + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32si/src/scall.S + +- test: rv32si-ma_fetch + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32si/src/ma_fetch.S + +- test: rv32si-wfi + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32si/src/wfi.S + +- test: rv32si-dirty + iterations: 0 # exception on spike + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32si/src/dirty.S + +- test: rv32si-csr + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32si/src/csr.S + +- test: rv32imc-C-LW + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-LW.S + +- test: rv32imc-C-LWSP + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-LWSP.S + +- test: rv32imc-C-ADD + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-ADD.S + +- test: rv32imc-C-JAL # assembly error + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-JAL.S + +- test: rv32imc-C-SRAI + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-SRAI.S + +- test: rv32imc-C-JALR + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-JALR.S + +- test: rv32imc-C-XOR + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-XOR.S + +- test: rv32imc-C-SUB + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-SUB.S + +- test: rv32imc-C-ADDI + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-ADDI.S + +- test: rv32imc-C-BEQZ + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-BEQZ.S + +- test: rv32imc-C-ADDI16SP + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-ADDI16SP.S + +- test: rv32imc-C-LI + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-LI.S + +- test: rv32imc-C-SW + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-SW.S + +- test: rv32imc-C-OR + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-OR.S + +- test: rv32imc-C-ADDI4SPN + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-ADDI4SPN.S + +- test: rv32imc-C-AND + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-AND.S + +- test: rv32imc-C-SRLI + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-SRLI.S + +- test: rv32imc-C-SWSP + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-SWSP.S + +- test: rv32imc-C-SLLI + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-SLLI.S + +- test: rv32imc-C-JR + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-JR.S + +- test: rv32imc-C-BNEZ + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-BNEZ.S + +- test: rv32imc-C-MV + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-MV.S + +- test: rv32imc-C-LUI + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-LUI.S + +- test: rv32imc-C-J + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-J.S + +- test: rv32imc-C-ANDI + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-ANDI.S + +- test: rv32Zicsr-I-CSRRC-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32Zicsr/src/I-CSRRC-01.S + +- test: rv32Zicsr-I-CSRRS-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32Zicsr/src/I-CSRRS-01.S + +- test: rv32Zicsr-I-CSRRSI-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32Zicsr/src/I-CSRRSI-01.S + +- test: rv32Zicsr-I-CSRRW-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32Zicsr/src/I-CSRRW-01.S + +- test: rv32Zicsr-I-CSRRCI-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32Zicsr/src/I-CSRRCI-01.S + +- test: rv32Zicsr-I-CSRRWI-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32Zicsr/src/I-CSRRWI-01.S + +- test: rv32ua-amoxor_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ua/src/amoxor_w.S + +- test: rv32ua-amoadd_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ua/src/amoadd_w.S + +- test: rv32ua-amoor_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ua/src/amoor_w.S + +- test: rv32ua-amomin_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ua/src/amomin_w.S + +- test: rv32ua-amoand_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ua/src/amoand_w.S + +- test: rv32ua-amomaxu_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ua/src/amomaxu_w.S + +- test: rv32ua-amoswap_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ua/src/amoswap_w.S + +- test: rv32ua-amominu_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ua/src/amominu_w.S + +- test: rv32ua-amomax_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ua/src/amomax_w.S + +- test: rv32uf-fclass + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32uf/src/fclass.S + +- test: rv32uf-ldst + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32uf/src/ldst.S + +- test: rv32uf-fmadd + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32uf/src/fmadd.S + +- test: rv32uf-recoding + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32uf/src/recoding.S + +- test: rv32uf-fcvt + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32uf/src/fcvt.S + +- test: rv32uf-fcmp + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32uf/src/fcmp.S + +- test: rv32uf-fcvt_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32uf/src/fcvt_w.S + +- test: rv32uf-fadd + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32uf/src/fadd.S + +- test: rv32uf-fmin + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32uf/src/fmin.S + +- test: rv32uf-move + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32uf/src/move.S + +- test: rv32uf-fdiv + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32uf/src/fdiv.S + +- test: rv32ud-fclass + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ud/src/fclass.S + +- test: rv32ud-ldst + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ud/src/ldst.S + +- test: rv32ud-fmadd + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ud/src/fmadd.S + +- test: rv32ud-recoding + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ud/src/recoding.S + +- test: rv32ud-fcvt + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ud/src/fcvt.S + +- test: rv32ud-fcmp + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ud/src/fcmp.S + +- test: rv32ud-fadd + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ud/src/fadd.S + +- test: rv32ud-fmin + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ud/src/fmin.S + +- test: rv32ud-fdiv + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ud/src/fdiv.S diff --git a/verif/tests/testlist_riscv-compliance-rv32ima.yaml b/verif/tests/testlist_riscv-compliance-rv32ima.yaml new file mode 100644 index 0000000000..7b48c07128 --- /dev/null +++ b/verif/tests/testlist_riscv-compliance-rv32ima.yaml @@ -0,0 +1,1131 @@ +# Copyright Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# ================================================================================ +# Regression test list format +# -------------------------------------------------------------------------------- +# test : Assembly test name +# description : Description of this test +# gen_opts : Instruction generator options +# iterations : Number of iterations of this test +# no_iss : Enable/disable ISS simulator (Optional) +# gen_test : Test name used by the instruction generator +# asm_tests : Path to directed, hand-coded assembly test file or directory +# rtl_test : RTL simulation test name +# cmp_opts : Compile options passed to the instruction generator +# sim_opts : Simulation options passed to the instruction generator +# no_post_compare : Enable/disable comparison of trace log and ISS log (Optional) +# compare_opts : Options for the RTL & ISS trace comparison +# gcc_opts : gcc compile options +# -------------------------------------------------------------------------------- + +#- import: <riscv_dv_root>/target/rv64imc/testlist.yaml + +- test: rv64im-REMUW + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv64im/src/REMUW.S + +- test: rv64im-MULW + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv64im/src/MULW.S + +- test: rv64i-SRAW + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv64i/src/SRAW.S + +- test: rv64i-ADDW + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv64i/src/ADDW.S + +- test: rv64i-ADDIW + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv64i/src/ADDIW.S + +- test: rv64i-SLLW + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv64i/src/SLLW.S + +- test: rv64i-SUBW + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv64i/src/SUBW.S + +- test: rv64i-SRLW + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv64i/src/SRLW.S + +- test: rv64i-SLLIW + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv64i/src/SLLIW.S + +- test: rv64i-SRLIW + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv64i/src/SRLIW.S + +- test: rv64i-SRAIW + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv64i/src/SRAIW.S + +- test: rv32uc-rvc + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32uc/src/rvc.S + +- test: rv32Zifencei-I-FENCE.I-01 # FAILED on spike + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32Zifencei/src/I-FENCE.I-01.S + +- test: rv32im-MULHSU + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32im/src/MULHSU.S + +- test: rv32im-DIVU + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32im/src/DIVU.S + +- test: rv32im-REMU + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32im/src/REMU.S + +- test: rv32im-MUL + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32im/src/MUL.S + +- test: rv32im-DIV + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32im/src/DIV.S + +- test: rv32im-MULH + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32im/src/MULH.S + +- test: rv32im-MULHU + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32im/src/MULHU.S + +- test: rv32im-REM + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32im/src/REM.S + +- test: rv32ui-jal + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/jal.S + +- test: rv32ui-bge + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/bge.S + +- test: rv32ui-blt + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/blt.S + +- test: rv32ui-bgeu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/bgeu.S + +- test: rv32ui-sw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/sw.S + +- test: rv32ui-lbu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/lbu.S + +- test: rv32ui-sb + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/sb.S + +- test: rv32ui-sw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/slti.S + +- test: rv32ui-sra + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/sra.S + +- test: rv32ui-srl + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/srl.S + +- test: rv32ui-sh + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/sh.S + +- test: rv32ui-lw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/lw.S + +- test: rv32ui-andi + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/andi.S + +- test: rv32ui-srli + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/srli.S + +- test: rv32ui-slli + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/slli.S + +- test: rv32ui-beq + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/beq.S + +- test: rv32ui-sll + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/sll.S + +- test: rv32ui-addi + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/addi.S + +- test: rv32ui-lh + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/lh.S + +- test: rv32ui-and + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/and.S + +- test: rv32ui-xori + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/xori.S + +- test: rv32ui-sub + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/sub.S + +- test: rv32ui-slt + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/slt.S + +- test: rv32ui-lb + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/lb.S + +- test: rv32ui-or + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/or.S + +- test: rv32ui-lui + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/lui.S + +- test: rv32ui-ori + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/ori.S + +- test: rv32ui-bltu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/bltu.S + +- test: rv32ui-fence_i + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/fence_i.S + +- test: rv32ui-auipc + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/auipc.S + +- test: rv32ui-srai + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/srai.S + +- test: rv32ui-jalr + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/jalr.S + +- test: rv32ui-xor + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/xor.S + +- test: rv32ui-simple + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/simple.S + +- test: rv32ui-lhu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/lhu.S + +- test: rv32ui-bne + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/bne.S + +- test: rv32ui-add + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/add.S + +- test: rv32ui-sltiu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/sltiu.S + +- test: rv32ui-sltu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ui/src/sltu.S + +- test: rv32mi-sbreak + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32mi/src/sbreak.S + +- test: rv32mi-breakpoint + iterations: 0 # csrr a0, tdata1 => 0x20000000 (spike), 0x00000000 (cva6) + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32mi/src/breakpoint.S + +- test: rv32mi-scall + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32mi/src/scall.S + +- test: rv32mi-ma_addr + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32mi/src/ma_addr.S + +- test: rv32mi-mcsr + iterations: 0 # expected as different marchid + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32mi/src/mcsr.S + +- test: rv32mi-ma_fetch + iterations: 0 # expected as different misa + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32mi/src/ma_fetch.S + +- test: rv32mi-shamt + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32mi/src/shamt.S + +- test: rv32mi-illegal + iterations: 0 # cva6 does not record illegal instructions in log file + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32mi/src/illegal.S + +- test: rv32mi-csr + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32mi/src/csr.S + +- test: rv32i-I-AND-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-AND-01.S + +- test: rv32i-I-BNE-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-BNE-01.S + +- test: rv32i-I-IO + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-IO.S + +- test: rv32i-I-BLT-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-BLT-01.S + +- test: rv32i-I-SB-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SB-01.S + +- test: rv32i-I-MISALIGN_LDST-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-MISALIGN_LDST-01.S + +- test: rv32i-I-ECALL-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-ECALL-01.S + +- test: rv32i-I-LHU-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-LHU-01.S + +- test: rv32i-I-SRLI-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SRLI-01.S + +- test: rv32i-I-BLTU-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-BLTU-01.S + +- test: rv32i-I-LH-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-LH-01.S + +- test: rv32i-I-AUIPC-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-AUIPC-01.S + +- test: rv32i-I-ORI-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-ORI-01.S + +- test: rv32i-I-SLLI-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SLLI-01.S + +- test: rv32i-I-RF_width-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-RF_width-01.S + +- test: rv32i-I-XOR-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-XOR-01.S + +- test: rv32i-I-DELAY_SLOTS-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-DELAY_SLOTS-01.S + +- test: rv32i-I-EBREAK-01 # infinite loop with spike + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-EBREAK-01.S + +- test: rv32i-I-SRAI-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SRAI-01.S + +- test: rv32i-I-SLTU-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SLTU-01.S + +- test: rv32i-I-OR-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-OR-01.S + +- test: rv32i-I-MISALIGN_JMP-01 # infinite loop with spike + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-MISALIGN_JMP-01.S + +- test: rv32i-I-JALR-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-JALR-01.S + +- test: rv32i-I-XORI-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-XORI-01.S + +- test: rv32i-I-ADDI-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-ADDI-01.S + +- test: rv32i-I-BGE-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-BGE-01.S + +- test: rv32i-I-ANDI-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-ANDI-01.S + +- test: rv32i-I-SH-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SH-01.S + +- test: rv32i-I-SLT-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SLT-01.S + +- test: rv32i-I-SLTIU-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SLTIU-01.S + +- test: rv32i-I-SLL-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SLL-01.S + +- test: rv32i-I-SRL-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SRL-01.S + +- test: rv32i-I-LUI-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-LUI-01.S + +- test: rv32i-I-SUB-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SUB-01.S + +- test: rv32i-I-LB-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-LB-01.S + +- test: rv32i-I-LW-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-LW-01.S + +- test: rv32i-I-SW-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SW-01.S + +- test: rv32i-I-SLTI-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SLTI-01.S + +- test: rv32i-I-SRA-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-SRA-01.S + +- test: rv32i-I-RF_size-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-RF_size-01.S + +- test: rv32i-I-BEQ-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-BEQ-01.S + +- test: rv32i-I-BGEU-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-BGEU-01.S + +- test: rv32i-I-JAL-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-JAL-01.S + +- test: rv32i-I-LBU-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-LBU-01.S + +- test: rv32i-I-ENDIANESS-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-ENDIANESS-01.S + +- test: rv32i-I-RF_x0-01 # assembly error + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-RF_x0-01.S + +- test: rv32i-I-NOP-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-NOP-01.S + +- test: rv32i-I-ADD-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32i/src/I-ADD-01.S + +- test: rv32si-sbreak + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32si/src/sbreak.S + +- test: rv32si-scall + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32si/src/scall.S + +- test: rv32si-ma_fetch + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32si/src/ma_fetch.S + +- test: rv32si-wfi + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32si/src/wfi.S + +- test: rv32si-dirty + iterations: 0 # exception on spike + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32si/src/dirty.S + +- test: rv32si-csr + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32si/src/csr.S + +- test: rv32imc-C-LW + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-LW.S + +- test: rv32imc-C-LWSP + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-LWSP.S + +- test: rv32imc-C-ADD + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-ADD.S + +- test: rv32imc-C-JAL # assembly error + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-JAL.S + +- test: rv32imc-C-SRAI + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-SRAI.S + +- test: rv32imc-C-JALR + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-JALR.S + +- test: rv32imc-C-XOR + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-XOR.S + +- test: rv32imc-C-SUB + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-SUB.S + +- test: rv32imc-C-ADDI + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-ADDI.S + +- test: rv32imc-C-BEQZ + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-BEQZ.S + +- test: rv32imc-C-ADDI16SP + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-ADDI16SP.S + +- test: rv32imc-C-LI + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-LI.S + +- test: rv32imc-C-SW + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-SW.S + +- test: rv32imc-C-OR + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-OR.S + +- test: rv32imc-C-ADDI4SPN + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-ADDI4SPN.S + +- test: rv32imc-C-AND + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-AND.S + +- test: rv32imc-C-SRLI + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-SRLI.S + +- test: rv32imc-C-SWSP + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-SWSP.S + +- test: rv32imc-C-SLLI + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-SLLI.S + +- test: rv32imc-C-JR + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-JR.S + +- test: rv32imc-C-BNEZ + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-BNEZ.S + +- test: rv32imc-C-MV + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-MV.S + +- test: rv32imc-C-LUI + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-LUI.S + +- test: rv32imc-C-J + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-J.S + +- test: rv32imc-C-ANDI + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32imc/src/C-ANDI.S + +- test: rv32Zicsr-I-CSRRC-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32Zicsr/src/I-CSRRC-01.S + +- test: rv32Zicsr-I-CSRRS-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32Zicsr/src/I-CSRRS-01.S + +- test: rv32Zicsr-I-CSRRSI-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32Zicsr/src/I-CSRRSI-01.S + +- test: rv32Zicsr-I-CSRRW-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32Zicsr/src/I-CSRRW-01.S + +- test: rv32Zicsr-I-CSRRCI-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32Zicsr/src/I-CSRRCI-01.S + +- test: rv32Zicsr-I-CSRRWI-01 + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32Zicsr/src/I-CSRRWI-01.S + +- test: rv32ua-amoxor_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ua/src/amoxor_w.S + +- test: rv32ua-amoadd_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ua/src/amoadd_w.S + +- test: rv32ua-amoor_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ua/src/amoor_w.S + +- test: rv32ua-amomin_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ua/src/amomin_w.S + +- test: rv32ua-amoand_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ua/src/amoand_w.S + +- test: rv32ua-amomaxu_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ua/src/amomaxu_w.S + +- test: rv32ua-amoswap_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ua/src/amoswap_w.S + +- test: rv32ua-amominu_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ua/src/amominu_w.S + +- test: rv32ua-amomax_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ua/src/amomax_w.S + +- test: rv32uf-fclass + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32uf/src/fclass.S + +- test: rv32uf-ldst + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32uf/src/ldst.S + +- test: rv32uf-fmadd + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32uf/src/fmadd.S + +- test: rv32uf-recoding + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32uf/src/recoding.S + +- test: rv32uf-fcvt + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32uf/src/fcvt.S + +- test: rv32uf-fcmp + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32uf/src/fcmp.S + +- test: rv32uf-fcvt_w + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32uf/src/fcvt_w.S + +- test: rv32uf-fadd + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32uf/src/fadd.S + +- test: rv32uf-fmin + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32uf/src/fmin.S + +- test: rv32uf-move + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32uf/src/move.S + +- test: rv32uf-fdiv + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32uf/src/fdiv.S + +- test: rv32ud-fclass + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ud/src/fclass.S + +- test: rv32ud-ldst + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ud/src/ldst.S + +- test: rv32ud-fmadd + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ud/src/fmadd.S + +- test: rv32ud-recoding + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ud/src/recoding.S + +- test: rv32ud-fcvt + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ud/src/fcvt.S + +- test: rv32ud-fcmp + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ud/src/fcmp.S + +- test: rv32ud-fadd + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ud/src/fadd.S + +- test: rv32ud-fmin + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ud/src/fmin.S + +- test: rv32ud-fdiv + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-compliance/riscv-test-env/ -I<path_var>/riscv-compliance/riscv-test-env/p/ -I<path_var>/riscv-compliance/riscv-target/spike/" + asm_tests: <path_var>/riscv-compliance/riscv-test-suite/rv32ud/src/fdiv.S diff --git a/verif/tests/testlist_riscv-csr-access-test-cv32a60x.yaml b/verif/tests/testlist_riscv-csr-access-test-cv32a60x.yaml new file mode 100644 index 0000000000..cb0da95683 --- /dev/null +++ b/verif/tests/testlist_riscv-csr-access-test-cv32a60x.yaml @@ -0,0 +1,9 @@ +- test: MSCRATCH_CSR + iterations: 1 + path_var: TESTS_PATH + # Prerequisite: install riscv-arch-test (== run 'cva6/regress/install-riscv-arch-test.sh') first. + # It will populate '<path_var>/riscv-arch-test/riscv-target/spike/' using the current Spike installation. + gcc_opts: "-DTEST_CASE_1=True -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-arch-test/riscv-target/spike/" + asm_tests: <path_var>/custom/csr_access_tests/riscv_mscratch_csr_test_0.S + + diff --git a/verif/tests/testlist_riscv-tests-cv32a60x-p.yaml b/verif/tests/testlist_riscv-tests-cv32a60x-p.yaml new file mode 100644 index 0000000000..5993bab255 --- /dev/null +++ b/verif/tests/testlist_riscv-tests-cv32a60x-p.yaml @@ -0,0 +1,601 @@ +# Copyright Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# ================================================================================ +# Regression test list format +# -------------------------------------------------------------------------------- +# test : Assembly test name +# description : Description of this test +# gen_opts : Instruction generator options +# iterations : Number of iterations of this test +# no_iss : Enable/disable ISS simulator (Optional) +# gen_test : Test name used by the instruction generator +# asm_tests : Path to directed, hand-coded assembly test file or directory +# rtl_test : RTL simulation test name +# cmp_opts : Compile options passed to the instruction generator +# sim_opts : Simulation options passed to the instruction generator +# no_post_compare : Enable/disable comparison of trace log and ISS log (Optional) +# compare_opts : Options for the RTL & ISS trace comparison +# gcc_opts : gcc compile options +# -------------------------------------------------------------------------------- + +#- import: <riscv_dv_root>/target/rv32imc/testlist.yaml + +# ISA tests +- test: rv32ui-p-add + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/add.S + +- test: rv32ui-p-addi + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/addi.S + +- test: rv32ui-p-and + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/and.S + +- test: rv32ui-p-andi + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/andi.S + +- test: rv32ui-p-auipc + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/auipc.S + +- test: rv32ui-p-beq + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/beq.S + +- test: rv32ui-p-bge + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/bge.S + +- test: rv32ui-p-bgeu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/bgeu.S + +- test: rv32ui-p-blt + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/blt.S + +- test: rv32ui-p-bltu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/bltu.S + +- test: rv32ui-p-bne + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/bne.S + +- test: rv32ui-p-simple + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/simple.S + +- test: rv32ui-p-fence_i + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/fence_i.S + +- test: rv32ui-p-jal + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/jal.S + +- test: rv32ui-p-jalr + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/jalr.S + +- test: rv32ui-p-lb + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/lb.S + +- test: rv32ui-p-lbu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/lbu.S + +- test: rv32ui-p-lh + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/lh.S + +- test: rv32ui-p-lhu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/lhu.S + +- test: rv32ui-p-lw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/lw.S + +- test: rv32ui-p-lui + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/lui.S + +- test: rv32ui-p-or + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/or.S + +- test: rv32ui-p-ori + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/ori.S + +- test: rv32ui-p-sb + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/sb.S + +- test: rv32ui-p-sh + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/sh.S + +- test: rv32ui-p-sw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/sw.S + +- test: rv32ui-p-sll + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/sll.S + +- test: rv32ui-p-slli + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/slli.S + +- test: rv32ui-p-slt + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/slt.S + +- test: rv32ui-p-slti + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/slti.S + +- test: rv32ui-p-sltiu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/sltiu.S + +- test: rv32ui-p-sltu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/sltu.S + +- test: rv32ui-p-sra + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/sra.S + +- test: rv32ui-p-srai + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/srai.S + +- test: rv32ui-p-srl + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/srl.S + +- test: rv32ui-p-srli + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/srli.S + +- test: rv32ui-p-sub + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/sub.S + +- test: rv32ui-p-xor + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/xor.S + +- test: rv32ui-p-xori + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/xori.S + +- test: rv32mi-p-breakpoint + iterations: 0 # csrr a0, tdata1 => 0x20000000 (spike), 0x00000000 (cva6) + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32mi/breakpoint.S + +- test: rv32mi-p-csr + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32mi/csr.S + +- test: rv32mi-p-mcsr + iterations: 0 # expected as different marchid + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32mi/mcsr.S + +- test: rv32mi-p-illegal + iterations: 0 # cva6 does not record illegal instructions in log file + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32mi/illegal.S + +- test: rv32mi-p-ma_addr + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32mi/ma_addr.S + +- test: rv32mi-p-ma_fetch + iterations: 0 # expected as different misa + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32mi/ma_fetch.S + +- test: rv32mi-p-sbreak + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32mi/sbreak.S + +- test: rv32mi-p-scall + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32mi/scall.S + +- test: rv32mi-p-shamt + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32mi/shamt.S + +- test: rv32si-p-csr + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32si/csr.S + +- test: rv32si-p-ma_fetch + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32si/ma_fetch.S + +- test: rv32si-p-scall + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32si/scall.S + +- test: rv32si-p-wfi + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32si/wfi.S + +- test: rv32si-p-sbreak + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32si/sbreak.S + +- test: rv32si-p-dirty + iterations: 0 # to be explained + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32si/dirty.S + +- test: rv32uc-p-rvc + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uc/rvc.S + +# FPU tests +- test: rv32uf-p-fadd + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uf/fadd.S + +- test: rv32uf-p-fclass + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uf/fclass.S + +- test: rv32uf-p-fcmp + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uf/fcmp.S + +- test: rv32uf-p-fcvt + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uf/fcvt.S + +- test: rv32uf-p-fcvt_w + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uf/fcvt_w.S + +- test: rv32uf-p-fdiv + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uf/fdiv.S + +- test: rv32uf-p-fmadd + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uf/fmadd.S + +- test: rv32uf-p-fmin + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uf/fmin.S + +- test: rv32uf-p-ldst + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uf/ldst.S + +- test: rv32uf-p-move + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uf/move.S + +- test: rv32uf-p-recoding + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uf/recoding.S + +- test: rv32ud-p-fadd + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ud/fadd.S + +- test: rv32ud-p-fclass + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ud/fclass.S + +- test: rv32ud-p-fcmp + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ud/fcmp.S + +- test: rv32ud-p-fcvt + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ud/fcvt.S + +- test: rv32ud-p-fcvt_w + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ud/fcvt_w.S + +- test: rv32ud-p-fdiv + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ud/fdiv.S + +- test: rv32ud-p-fmadd + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ud/fmadd.S + +- test: rv32ud-p-fmin + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ud/fmin.S + +- test: rv32ud-p-ldst + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ud/ldst.S + +- test: rv32ud-p-recoding + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ud/recoding.S + +# MUL/DIV tests +- test: rv32um-p-div + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32um/div.S + +- test: rv32um-p-divu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32um/divu.S + +- test: rv32um-p-mul + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32um/mul.S + +- test: rv32um-p-mulh + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32um/mulh.S + +- test: rv32um-p-mulhsu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32um/mulhsu.S + +- test: rv32um-p-mulhu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32um/mulhu.S + +- test: rv32um-p-rem + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32um/rem.S + +- test: rv32um-p-remu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32um/remu.S + +# AMO tests +- test: rv32ua-p-amoadd_w + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ua/amoadd_w.S + +- test: rv32ua-p-amoand_w + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ua/amoand_w.S + +- test: rv32ua-p-amomax_w + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ua/amomax_w.S + +- test: rv32ua-p-amomaxu_w + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ua/amomaxu_w.S + +- test: rv32ua-p-amomin_w + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ua/amomin_w.S + +- test: rv32ua-v-amominu_w + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ua/amominu_w.S + +- test: rv32ua-p-amoor_w + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ua/amoor_w.S + +- test: rv32ua-p-amoxor_w + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ua/amoxor_w.S + +- test: rv32ua-p-amoswap_w + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ua/amoswap_w.S + +- test: rv32ua-p-lrsc + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ua/lrsc.S diff --git a/verif/tests/testlist_riscv-tests-cv32a60x-v.yaml b/verif/tests/testlist_riscv-tests-cv32a60x-v.yaml new file mode 100644 index 0000000000..e0b59c706f --- /dev/null +++ b/verif/tests/testlist_riscv-tests-cv32a60x-v.yaml @@ -0,0 +1,511 @@ +# Copyright Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# ================================================================================ +# Regression test list format +# -------------------------------------------------------------------------------- +# test : Assembly test name +# description : Description of this test +# gen_opts : Instruction generator options +# iterations : Number of iterations of this test +# no_iss : Enable/disable ISS simulator (Optional) +# gen_test : Test name used by the instruction generator +# asm_tests : Path to directed, hand-coded assembly test file or directory +# rtl_test : RTL simulation test name +# cmp_opts : Compile options passed to the instruction generator +# sim_opts : Simulation options passed to the instruction generator +# no_post_compare : Enable/disable comparison of trace log and ISS log (Optional) +# compare_opts : Options for the RTL & ISS trace comparison +# gcc_opts : gcc compile options +# -------------------------------------------------------------------------------- + +#- import: <riscv_dv_root>/target/rv32imc/testlist.yaml + +# ISA tests +- test: rv32ui-v-add + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/add.S + +- test: rv32ui-v-addi + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/addi.S + +- test: rv32ui-v-and + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/and.S + +- test: rv32ui-v-andi + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/andi.S + +- test: rv32ui-v-auipc + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/auipc.S + +- test: rv32ui-v-beq + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/beq.S + +- test: rv32ui-v-bge + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/bge.S + +- test: rv32ui-v-bgeu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/bgeu.S + +- test: rv32ui-v-blt + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/blt.S + +- test: rv32ui-v-bltu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/bltu.S + +- test: rv32ui-v-bne + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/bne.S + +- test: rv32ui-v-simple + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/simple.S + +- test: rv32ui-v-fence_i + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/fence_i.S + +- test: rv32ui-v-jal + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/jal.S + +- test: rv32ui-v-jalr + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/jalr.S + +- test: rv32ui-v-lb + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/lb.S + +- test: rv32ui-v-lbu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/lbu.S + +- test: rv32ui-v-lh + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/lh.S + +- test: rv32ui-v-lhu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/lhu.S + +- test: rv32ui-v-lw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/lw.S + +- test: rv32ui-v-lui + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/lui.S + +- test: rv32ui-v-or + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/or.S + +- test: rv32ui-v-ori + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/ori.S + +- test: rv32ui-v-sb + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/sb.S + +- test: rv32ui-v-sh + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/sh.S + +- test: rv32ui-v-sw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/sw.S + +- test: rv32ui-v-sll + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/sll.S + +- test: rv32ui-v-slli + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/slli.S + +- test: rv32ui-v-slt + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/slt.S + +- test: rv32ui-v-slti + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/slti.S + +- test: rv32ui-v-sltiu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/sltiu.S + +- test: rv32ui-v-sltu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/sltu.S + +- test: rv32ui-v-sra + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/sra.S + +- test: rv32ui-v-srai + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/srai.S + +- test: rv32ui-v-srl + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/srl.S + +- test: rv32ui-v-srli + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/srli.S + +- test: rv32ui-v-sub + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/sub.S + +- test: rv32ui-v-xor + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/xor.S + +- test: rv32ui-v-xori + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/xori.S + +- test: rv32uc-p-rvc + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uc/rvc.S + +# FPU tests +- test: rv32uf-v-fadd + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uf/fadd.S + +- test: rv32uf-v-fclass + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uf/fclass.S + +- test: rv32uf-v-fcmp + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uf/fcmp.S + +- test: rv32uf-v-fcvt + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uf/fcvt.S + +- test: rv32uf-v-fcvt_w + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uf/fcvt_w.S + +- test: rv32uf-v-fdiv + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uf/fdiv.S + +- test: rv32uf-v-fmadd + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uf/fmadd.S + +- test: rv32uf-v-fmin + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uf/fmin.S + +- test: rv32uf-v-ldst + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uf/ldst.S + +- test: rv32uf-v-move + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uf/move.S + +- test: rv32uf-v-recoding + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uf/recoding.S + +- test: rv32ud-v-fadd + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ud/fadd.S + +- test: rv32ud-v-fclass + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ud/fclass.S + +- test: rv32ud-v-fcmp + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ud/fcmp.S + +- test: rv32ud-v-fcvt + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ud/fcvt.S + +- test: rv32ud-v-fcvt_w + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ud/fcvt_w.S + +- test: rv32ud-v-fdiv + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ud/fdiv.S + +- test: rv32ud-v-fmadd + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ud/fmadd.S + +- test: rv32ud-v-fmin + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ud/fmin.S + +- test: rv32ud-v-ldst + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ud/ldst.S + +- test: rv32ud-v-recoding + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ud/recoding.S + +# MUL/DIV tests +- test: rv32um-v-div + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32um/div.S + +- test: rv32um-v-divu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32um/divu.S + +- test: rv32um-v-mul + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32um/mul.S + +- test: rv32um-v-mulh + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32um/mulh.S + +- test: rv32um-v-mulhsu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32um/mulhsu.S + +- test: rv32um-v-mulhu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32um/mulhu.S + +- test: rv32um-v-rem + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32um/rem.S + +- test: rv32um-v-remu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32um/remu.S + +# AMO tests +- test: rv32ua-v-amoadd_w + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ua/amoadd_w.S + +- test: rv32ua-v-amoand_w + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ua/amoand_w.S + +- test: rv32ua-v-amomax_w + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ua/amomax_w.S + +- test: rv32ua-v-amomaxu_w + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ua/amomaxu_w.S + +- test: rv32ua-v-amomin_w + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ua/amomin_w.S + +- test: rv32ua-v-amominu_w + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ua/amominu_w.S + +- test: rv32ua-v-amoor_w + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ua/amoor_w.S + +- test: rv32ua-v-amoxor_w + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ua/amoxor_w.S + +- test: rv32ua-v-amoswap_w + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ua/amoswap_w.S + +- test: rv32ua-v-lrsc + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ua/lrsc.S diff --git a/verif/tests/testlist_riscv-tests-cv32a6_imac_sv0-p.yaml b/verif/tests/testlist_riscv-tests-cv32a6_imac_sv0-p.yaml new file mode 100644 index 0000000000..46fa5cdea0 --- /dev/null +++ b/verif/tests/testlist_riscv-tests-cv32a6_imac_sv0-p.yaml @@ -0,0 +1,601 @@ +# Copyright Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# ================================================================================ +# Regression test list format +# -------------------------------------------------------------------------------- +# test : Assembly test name +# description : Description of this test +# gen_opts : Instruction generator options +# iterations : Number of iterations of this test +# no_iss : Enable/disable ISS simulator (Optional) +# gen_test : Test name used by the instruction generator +# asm_tests : Path to directed, hand-coded assembly test file or directory +# rtl_test : RTL simulation test name +# cmp_opts : Compile options passed to the instruction generator +# sim_opts : Simulation options passed to the instruction generator +# no_post_compare : Enable/disable comparison of trace log and ISS log (Optional) +# compare_opts : Options for the RTL & ISS trace comparison +# gcc_opts : gcc compile options +# -------------------------------------------------------------------------------- + +#- import: <riscv_dv_root>/target/rv32imc/testlist.yaml + +# ISA tests +- test: rv32ui-p-add + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/add.S + +- test: rv32ui-p-addi + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/addi.S + +- test: rv32ui-p-and + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/and.S + +- test: rv32ui-p-andi + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/andi.S + +- test: rv32ui-p-auipc + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/auipc.S + +- test: rv32ui-p-beq + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/beq.S + +- test: rv32ui-p-bge + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/bge.S + +- test: rv32ui-p-bgeu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/bgeu.S + +- test: rv32ui-p-blt + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/blt.S + +- test: rv32ui-p-bltu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/bltu.S + +- test: rv32ui-p-bne + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/bne.S + +- test: rv32ui-p-simple + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/simple.S + +- test: rv32ui-p-fence_i + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/fence_i.S + +- test: rv32ui-p-jal + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/jal.S + +- test: rv32ui-p-jalr + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/jalr.S + +- test: rv32ui-p-lb + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/lb.S + +- test: rv32ui-p-lbu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/lbu.S + +- test: rv32ui-p-lh + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/lh.S + +- test: rv32ui-p-lhu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/lhu.S + +- test: rv32ui-p-lw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/lw.S + +- test: rv32ui-p-lui + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/lui.S + +- test: rv32ui-p-or + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/or.S + +- test: rv32ui-p-ori + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/ori.S + +- test: rv32ui-p-sb + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/sb.S + +- test: rv32ui-p-sh + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/sh.S + +- test: rv32ui-p-sw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/sw.S + +- test: rv32ui-p-sll + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/sll.S + +- test: rv32ui-p-slli + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/slli.S + +- test: rv32ui-p-slt + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/slt.S + +- test: rv32ui-p-slti + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/slti.S + +- test: rv32ui-p-sltiu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/sltiu.S + +- test: rv32ui-p-sltu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/sltu.S + +- test: rv32ui-p-sra + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/sra.S + +- test: rv32ui-p-srai + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/srai.S + +- test: rv32ui-p-srl + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/srl.S + +- test: rv32ui-p-srli + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/srli.S + +- test: rv32ui-p-sub + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/sub.S + +- test: rv32ui-p-xor + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/xor.S + +- test: rv32ui-p-xori + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/xori.S + +- test: rv32mi-p-breakpoint + iterations: 0 # csrr a0, tdata1 => 0x20000000 (spike), 0x00000000 (cva6) + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32mi/breakpoint.S + +- test: rv32mi-p-csr + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32mi/csr.S + +- test: rv32mi-p-mcsr + iterations: 0 # expected as different marchid + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32mi/mcsr.S + +- test: rv32mi-p-illegal + iterations: 0 # cva6 does not record illegal instructions in log file + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32mi/illegal.S + +- test: rv32mi-p-ma_addr + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32mi/ma_addr.S + +- test: rv32mi-p-ma_fetch + iterations: 0 # expected as different misa + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32mi/ma_fetch.S + +- test: rv32mi-p-sbreak + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32mi/sbreak.S + +- test: rv32mi-p-scall + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32mi/scall.S + +- test: rv32mi-p-shamt + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32mi/shamt.S + +- test: rv32si-p-csr + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32si/csr.S + +- test: rv32si-p-ma_fetch + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32si/ma_fetch.S + +- test: rv32si-p-scall + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32si/scall.S + +- test: rv32si-p-wfi + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32si/wfi.S + +- test: rv32si-p-sbreak + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32si/sbreak.S + +- test: rv32si-p-dirty + iterations: 0 # to be explained + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32si/dirty.S + +- test: rv32uc-p-rvc + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uc/rvc.S + +# FPU tests +- test: rv32uf-p-fadd + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uf/fadd.S + +- test: rv32uf-p-fclass + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uf/fclass.S + +- test: rv32uf-p-fcmp + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uf/fcmp.S + +- test: rv32uf-p-fcvt + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uf/fcvt.S + +- test: rv32uf-p-fcvt_w + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uf/fcvt_w.S + +- test: rv32uf-p-fdiv + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uf/fdiv.S + +- test: rv32uf-p-fmadd + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uf/fmadd.S + +- test: rv32uf-p-fmin + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uf/fmin.S + +- test: rv32uf-p-ldst + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uf/ldst.S + +- test: rv32uf-p-move + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uf/move.S + +- test: rv32uf-p-recoding + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uf/recoding.S + +- test: rv32ud-p-fadd + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ud/fadd.S + +- test: rv32ud-p-fclass + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ud/fclass.S + +- test: rv32ud-p-fcmp + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ud/fcmp.S + +- test: rv32ud-p-fcvt + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ud/fcvt.S + +- test: rv32ud-p-fcvt_w + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ud/fcvt_w.S + +- test: rv32ud-p-fdiv + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ud/fdiv.S + +- test: rv32ud-p-fmadd + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ud/fmadd.S + +- test: rv32ud-p-fmin + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ud/fmin.S + +- test: rv32ud-p-ldst + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ud/ldst.S + +- test: rv32ud-p-recoding + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ud/recoding.S + +# MUL/DIV tests +- test: rv32um-p-div + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32um/div.S + +- test: rv32um-p-divu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32um/divu.S + +- test: rv32um-p-mul + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32um/mul.S + +- test: rv32um-p-mulh + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32um/mulh.S + +- test: rv32um-p-mulhsu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32um/mulhsu.S + +- test: rv32um-p-mulhu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32um/mulhu.S + +- test: rv32um-p-rem + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32um/rem.S + +- test: rv32um-p-remu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32um/remu.S + +# AMO tests +- test: rv32ua-p-amoadd_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ua/amoadd_w.S + +- test: rv32ua-p-amoand_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ua/amoand_w.S + +- test: rv32ua-p-amomax_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ua/amomax_w.S + +- test: rv32ua-p-amomaxu_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ua/amomaxu_w.S + +- test: rv32ua-p-amomin_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ua/amomin_w.S + +- test: rv32ua-v-amominu_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ua/amominu_w.S + +- test: rv32ua-p-amoor_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ua/amoor_w.S + +- test: rv32ua-p-amoxor_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ua/amoxor_w.S + +- test: rv32ua-p-amoswap_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ua/amoswap_w.S + +- test: rv32ua-p-lrsc + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ua/lrsc.S diff --git a/verif/tests/testlist_riscv-tests-cv32a6_imac_sv0-v.yaml b/verif/tests/testlist_riscv-tests-cv32a6_imac_sv0-v.yaml new file mode 100644 index 0000000000..ef51bfc692 --- /dev/null +++ b/verif/tests/testlist_riscv-tests-cv32a6_imac_sv0-v.yaml @@ -0,0 +1,511 @@ +# Copyright Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# ================================================================================ +# Regression test list format +# -------------------------------------------------------------------------------- +# test : Assembly test name +# description : Description of this test +# gen_opts : Instruction generator options +# iterations : Number of iterations of this test +# no_iss : Enable/disable ISS simulator (Optional) +# gen_test : Test name used by the instruction generator +# asm_tests : Path to directed, hand-coded assembly test file or directory +# rtl_test : RTL simulation test name +# cmp_opts : Compile options passed to the instruction generator +# sim_opts : Simulation options passed to the instruction generator +# no_post_compare : Enable/disable comparison of trace log and ISS log (Optional) +# compare_opts : Options for the RTL & ISS trace comparison +# gcc_opts : gcc compile options +# -------------------------------------------------------------------------------- + +#- import: <riscv_dv_root>/target/rv32imc/testlist.yaml + +# ISA tests +- test: rv32ui-v-add + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/add.S + +- test: rv32ui-v-addi + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/addi.S + +- test: rv32ui-v-and + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/and.S + +- test: rv32ui-v-andi + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/andi.S + +- test: rv32ui-v-auipc + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/auipc.S + +- test: rv32ui-v-beq + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/beq.S + +- test: rv32ui-v-bge + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/bge.S + +- test: rv32ui-v-bgeu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/bgeu.S + +- test: rv32ui-v-blt + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/blt.S + +- test: rv32ui-v-bltu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/bltu.S + +- test: rv32ui-v-bne + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/bne.S + +- test: rv32ui-v-simple + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/simple.S + +- test: rv32ui-v-fence_i + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/fence_i.S + +- test: rv32ui-v-jal + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/jal.S + +- test: rv32ui-v-jalr + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/jalr.S + +- test: rv32ui-v-lb + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/lb.S + +- test: rv32ui-v-lbu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/lbu.S + +- test: rv32ui-v-lh + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/lh.S + +- test: rv32ui-v-lhu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/lhu.S + +- test: rv32ui-v-lw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/lw.S + +- test: rv32ui-v-lui + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/lui.S + +- test: rv32ui-v-or + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/or.S + +- test: rv32ui-v-ori + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/ori.S + +- test: rv32ui-v-sb + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/sb.S + +- test: rv32ui-v-sh + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/sh.S + +- test: rv32ui-v-sw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/sw.S + +- test: rv32ui-v-sll + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/sll.S + +- test: rv32ui-v-slli + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/slli.S + +- test: rv32ui-v-slt + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/slt.S + +- test: rv32ui-v-slti + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/slti.S + +- test: rv32ui-v-sltiu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/sltiu.S + +- test: rv32ui-v-sltu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/sltu.S + +- test: rv32ui-v-sra + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/sra.S + +- test: rv32ui-v-srai + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/srai.S + +- test: rv32ui-v-srl + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/srl.S + +- test: rv32ui-v-srli + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/srli.S + +- test: rv32ui-v-sub + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/sub.S + +- test: rv32ui-v-xor + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/xor.S + +- test: rv32ui-v-xori + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/xori.S + +- test: rv32uc-p-rvc + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uc/rvc.S + +# FPU tests +- test: rv32uf-v-fadd + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uf/fadd.S + +- test: rv32uf-v-fclass + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uf/fclass.S + +- test: rv32uf-v-fcmp + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uf/fcmp.S + +- test: rv32uf-v-fcvt + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uf/fcvt.S + +- test: rv32uf-v-fcvt_w + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uf/fcvt_w.S + +- test: rv32uf-v-fdiv + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uf/fdiv.S + +- test: rv32uf-v-fmadd + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uf/fmadd.S + +- test: rv32uf-v-fmin + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uf/fmin.S + +- test: rv32uf-v-ldst + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uf/ldst.S + +- test: rv32uf-v-move + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uf/move.S + +- test: rv32uf-v-recoding + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uf/recoding.S + +- test: rv32ud-v-fadd + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ud/fadd.S + +- test: rv32ud-v-fclass + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ud/fclass.S + +- test: rv32ud-v-fcmp + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ud/fcmp.S + +- test: rv32ud-v-fcvt + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ud/fcvt.S + +- test: rv32ud-v-fcvt_w + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ud/fcvt_w.S + +- test: rv32ud-v-fdiv + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ud/fdiv.S + +- test: rv32ud-v-fmadd + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ud/fmadd.S + +- test: rv32ud-v-fmin + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ud/fmin.S + +- test: rv32ud-v-ldst + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ud/ldst.S + +- test: rv32ud-v-recoding + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ud/recoding.S + +# MUL/DIV tests +- test: rv32um-v-div + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32um/div.S + +- test: rv32um-v-divu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32um/divu.S + +- test: rv32um-v-mul + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32um/mul.S + +- test: rv32um-v-mulh + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32um/mulh.S + +- test: rv32um-v-mulhsu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32um/mulhsu.S + +- test: rv32um-v-mulhu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32um/mulhu.S + +- test: rv32um-v-rem + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32um/rem.S + +- test: rv32um-v-remu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32um/remu.S + +# AMO tests +- test: rv32ua-v-amoadd_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ua/amoadd_w.S + +- test: rv32ua-v-amoand_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ua/amoand_w.S + +- test: rv32ua-v-amomax_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ua/amomax_w.S + +- test: rv32ua-v-amomaxu_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ua/amomaxu_w.S + +- test: rv32ua-v-amomin_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ua/amomin_w.S + +- test: rv32ua-v-amominu_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ua/amominu_w.S + +- test: rv32ua-v-amoor_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ua/amoor_w.S + +- test: rv32ua-v-amoxor_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ua/amoxor_w.S + +- test: rv32ua-v-amoswap_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ua/amoswap_w.S + +- test: rv32ua-v-lrsc + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ua/lrsc.S diff --git a/verif/tests/testlist_riscv-tests-cv64a6_imafdc_sv39-p.yaml b/verif/tests/testlist_riscv-tests-cv64a6_imafdc_sv39-p.yaml new file mode 100644 index 0000000000..656997a83e --- /dev/null +++ b/verif/tests/testlist_riscv-tests-cv64a6_imafdc_sv39-p.yaml @@ -0,0 +1,769 @@ +# Copyright Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# ================================================================================ +# Regression test list format +# -------------------------------------------------------------------------------- +# test : Assembly test name +# description : Description of this test +# gen_opts : Instruction generator options +# iterations : Number of iterations of this test +# no_iss : Enable/disable ISS simulator (Optional) +# gen_test : Test name used by the instruction generator +# asm_tests : Path to directed, hand-coded assembly test file or directory +# rtl_test : RTL simulation test name +# cmp_opts : Compile options passed to the instruction generator +# sim_opts : Simulation options passed to the instruction generator +# no_post_compare : Enable/disable comparison of trace log and ISS log (Optional) +# compare_opts : Options for the RTL & ISS trace comparison +# gcc_opts : gcc compile options +# -------------------------------------------------------------------------------- + +#- import: <riscv_dv_root>/target/rv64imc/testlist.yaml + +# ISA tests +- test: rv64ui-p-add + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/add.S + +- test: rv64ui-p-addi + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/addi.S + +- test: rv64ui-p-addiw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/addiw.S + +- test: rv64ui-p-addw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/addw.S + +- test: rv64ui-p-and + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/and.S + +- test: rv64ui-p-andi + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/andi.S + +- test: rv64ui-p-auipc + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/auipc.S + +- test: rv64ui-p-beq + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/beq.S + +- test: rv64ui-p-bge + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/bge.S + +- test: rv64ui-p-bgeu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/bgeu.S + +- test: rv64ui-p-blt + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/blt.S + +- test: rv64ui-p-bltu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/bltu.S + +- test: rv64ui-p-bne + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/bne.S + +- test: rv64ui-p-simple + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/simple.S + +- test: rv64ui-p-fence_i + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/fence_i.S + +- test: rv64ui-p-jal + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/jal.S + +- test: rv64ui-p-jalr + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/jalr.S + +- test: rv64ui-p-lb + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/lb.S + +- test: rv64ui-p-lbu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/lbu.S + +- test: rv64ui-p-lh + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/lh.S + +- test: rv64ui-p-lhu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/lhu.S + +- test: rv64ui-p-lw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/lw.S + +- test: rv64ui-p-lwu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/lwu.S + +- test: rv64ui-p-ld + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/ld.S + +- test: rv64ui-p-lui + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/lui.S + +- test: rv64ui-p-or + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/or.S + +- test: rv64ui-p-ori + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/ori.S + +- test: rv64ui-p-sb + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/sb.S + +- test: rv64ui-p-sh + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/sh.S + +- test: rv64ui-p-sw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/sw.S + +- test: rv64ui-p-sd + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/sd.S + +- test: rv64ui-p-sll + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/sll.S + +- test: rv64ui-p-slli + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/slli.S + +- test: rv64ui-p-slliw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/slliw.S + +- test: rv64ui-p-sllw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/sllw.S + +- test: rv64ui-p-slt + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/slt.S + +- test: rv64ui-p-slti + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/slti.S + +- test: rv64ui-p-sltiu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/sltiu.S + +- test: rv64ui-p-sltu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/sltu.S + +- test: rv64ui-p-sra + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/sra.S + +- test: rv64ui-p-srai + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/srai.S + +- test: rv64ui-p-sraiw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/sraiw.S + +- test: rv64ui-p-sraw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/sraw.S + +- test: rv64ui-p-srl + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/srl.S + +- test: rv64ui-p-srli + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/srli.S + +- test: rv64ui-p-srliw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/srliw.S + +- test: rv64ui-p-srlw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/srlw.S + +- test: rv64ui-p-sub + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/sub.S + +- test: rv64ui-p-subw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/subw.S + +- test: rv64ui-p-xor + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/xor.S + +- test: rv64ui-p-xori + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/xori.S + +- test: rv64mi-p-access + iterations: 0 # to be explained + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64mi/access.S + +- test: rv64mi-p-breakpoint + iterations: 0 # csrr a0, tdata1 => 0x2000000000000000 (spike), 0x0000000000000000 (cva6) + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64mi/breakpoint.S + +- test: rv64mi-p-csr + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64mi/csr.S + +- test: rv64mi-p-mcsr + iterations: 0 # expected as different marchid + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64mi/mcsr.S + +- test: rv64mi-p-illegal + iterations: 0 # cva6 does not record illegal instructions in log file + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64mi/illegal.S + +- test: rv64mi-p-ma_fetch + iterations: 0 # expected as different misa + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64mi/ma_fetch.S + +- test: rv64mi-p-ma_addr + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64mi/ma_addr.S + +- test: rv64mi-p-scall + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64mi/scall.S + +- test: rv64mi-p-sbreak + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64mi/sbreak.S + +- test: rv64si-p-csr + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64si/csr.S + +- test: rv64si-p-dirty + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64si/dirty.S + +- test: rv64si-p-ma_fetch + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64si/ma_fetch.S + +- test: rv64si-p-scall + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64si/scall.S + +- test: rv64si-p-wfi + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64si/wfi.S + +- test: rv64si-p-sbreak + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64si/sbreak.S + +- test: rv64uc-p-rvc + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64uc/rvc.S + +# FPU tests +- test: rv64uf-p-fadd + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64uf/fadd.S + +- test: rv64uf-p-fclass + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64uf/fclass.S + +- test: rv64uf-p-fcmp + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64uf/fcmp.S + +- test: rv64uf-p-fcvt + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64uf/fcvt.S + +- test: rv64uf-p-fcvt_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64uf/fcvt_w.S + +- test: rv64uf-p-fdiv + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64uf/fdiv.S + +- test: rv64uf-p-fmadd + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64uf/fmadd.S + +- test: rv64uf-p-fmin + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64uf/fmin.S + +- test: rv64uf-p-ldst + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64uf/ldst.S + +- test: rv64uf-p-move + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64uf/move.S + +- test: rv64uf-p-recoding + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64uf/recoding.S + +- test: rv64ud-p-fadd + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ud/fadd.S + +- test: rv64ud-p-fclass + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ud/fclass.S + +- test: rv64ud-p-fcmp + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ud/fcmp.S + +- test: rv64ud-p-fcvt + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ud/fcvt.S + +- test: rv64ud-p-fcvt_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ud/fcvt_w.S + +- test: rv64ud-p-fdiv + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ud/fdiv.S + +- test: rv64ud-p-fmadd + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ud/fmadd.S + +- test: rv64ud-p-fmin + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ud/fmin.S + +- test: rv64ud-p-ldst + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ud/ldst.S + +- test: rv64ud-p-move + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ud/move.S + +- test: rv64ud-p-recoding + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ud/recoding.S + +- test: rv64ud-p-structural + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ud/structural.S + +# MUL/DIV tests +- test: rv64um-p-div + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64um/div.S + +- test: rv64um-p-divu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64um/divu.S + +- test: rv64um-p-divw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64um/divw.S + +- test: rv64um-p-divuw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64um/divuw.S + +- test: rv64um-p-mul + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64um/mul.S + +- test: rv64um-p-mulh + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64um/mulh.S + +- test: rv64um-p-mulhsu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64um/mulhsu.S + +- test: rv64um-p-mulhu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64um/mulhu.S + +- test: rv64um-p-mulw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64um/mulw.S + +- test: rv64um-p-rem + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64um/rem.S + +- test: rv64um-p-remu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64um/remu.S + +- test: rv64um-p-remuw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64um/remuw.S + +- test: rv64um-p-remw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64um/remw.S + +# AMO tests +- test: rv64ua-p-amoadd_d + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ua/amoadd_d.S + +- test: rv64ua-p-amoand_d + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ua/amoand_d.S + +- test: rv64ua-p-amomax_d + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ua/amomax_d.S + +- test: rv64ua-p-amomaxu_d + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ua/amomaxu_d.S + +- test: rv64ua-p-amomin_d + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ua/amomin_d.S + +- test: rv64ua-p-amominu_d + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ua/amominu_d.S + +- test: rv64ua-p-amoor_d + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ua/amoor_d.S + +- test: rv64ua-p-amoxor_d + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ua/amoxor_d.S + +- test: rv64ua-p-amoswap_d + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ua/amoswap_d.S + +- test: rv64ua-p-amoadd_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ua/amoadd_w.S + +- test: rv64ua-p-amoand_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ua/amoand_w.S + +- test: rv64ua-p-amomax_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ua/amomax_w.S + +- test: rv64ua-p-amomaxu_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ua/amomaxu_w.S + +- test: rv64ua-p-amomin_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ua/amomin_w.S + +- test: rv64ua-p-amominu_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ua/amominu_w.S + +- test: rv64ua-p-amoor_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ua/amoor_w.S + +- test: rv64ua-p-amoxor_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ua/amoxor_w.S + +- test: rv64ua-p-amoswap_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ua/amoswap_w.S + +- test: rv64ua-p-lrsc + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ua/lrsc.S diff --git a/verif/tests/testlist_riscv-tests-cv64a6_imafdc_sv39-v.yaml b/verif/tests/testlist_riscv-tests-cv64a6_imafdc_sv39-v.yaml new file mode 100644 index 0000000000..311b2e67a7 --- /dev/null +++ b/verif/tests/testlist_riscv-tests-cv64a6_imafdc_sv39-v.yaml @@ -0,0 +1,679 @@ +# Copyright Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# ================================================================================ +# Regression test list format +# -------------------------------------------------------------------------------- +# test : Assembly test name +# description : Description of this test +# gen_opts : Instruction generator options +# iterations : Number of iterations of this test +# no_iss : Enable/disable ISS simulator (Optional) +# gen_test : Test name used by the instruction generator +# asm_tests : Path to directed, hand-coded assembly test file or directory +# rtl_test : RTL simulation test name +# cmp_opts : Compile options passed to the instruction generator +# sim_opts : Simulation options passed to the instruction generator +# no_post_compare : Enable/disable comparison of trace log and ISS log (Optional) +# compare_opts : Options for the RTL & ISS trace comparison +# gcc_opts : gcc compile options +# -------------------------------------------------------------------------------- + +#- import: <riscv_dv_root>/target/rv64imc/testlist.yaml + +# ISA tests +- test: rv64ui-v-add + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/add.S + +- test: rv64ui-v-addi + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/addi.S + +- test: rv64ui-v-addiw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/addiw.S + +- test: rv64ui-v-addw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/addw.S + +- test: rv64ui-v-and + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/and.S + +- test: rv64ui-v-andi + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/andi.S + +- test: rv64ui-v-auipc + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/auipc.S + +- test: rv64ui-v-beq + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/beq.S + +- test: rv64ui-v-bge + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/bge.S + +- test: rv64ui-v-bgeu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/bgeu.S + +- test: rv64ui-v-blt + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/blt.S + +- test: rv64ui-v-bltu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/bltu.S + +- test: rv64ui-v-bne + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/bne.S + +- test: rv64ui-v-simple + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/simple.S + +- test: rv64ui-v-fence_i + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/fence_i.S + +- test: rv64ui-v-jal + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/jal.S + +- test: rv64ui-v-jalr + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/jalr.S + +- test: rv64ui-v-lb + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/lb.S + +- test: rv64ui-v-lbu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/lbu.S + +- test: rv64ui-v-lh + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/lh.S + +- test: rv64ui-v-lhu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/lhu.S + +- test: rv64ui-v-lw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/lw.S + +- test: rv64ui-v-lwu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/lwu.S + +- test: rv64ui-v-ld + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/ld.S + +- test: rv64ui-v-lui + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/lui.S + +- test: rv64ui-v-or + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/or.S + +- test: rv64ui-v-ori + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/ori.S + +- test: rv64ui-v-sb + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/sb.S + +- test: rv64ui-v-sh + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/sh.S + +- test: rv64ui-v-sw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/sw.S + +- test: rv64ui-v-sd + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/sd.S + +- test: rv64ui-v-sll + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/sll.S + +- test: rv64ui-v-slli + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/slli.S + +- test: rv64ui-v-slliw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/slliw.S + +- test: rv64ui-v-sllw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/sllw.S + +- test: rv64ui-v-slt + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/slt.S + +- test: rv64ui-v-slti + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/slti.S + +- test: rv64ui-v-sltiu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/sltiu.S + +- test: rv64ui-v-sltu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/sltu.S + +- test: rv64ui-v-sra + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/sra.S + +- test: rv64ui-v-srai + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/srai.S + +- test: rv64ui-v-sraiw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/sraiw.S + +- test: rv64ui-v-sraw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/sraw.S + +- test: rv64ui-v-srl + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/srl.S + +- test: rv64ui-v-srli + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/srli.S + +- test: rv64ui-v-srliw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/srliw.S + +- test: rv64ui-v-srlw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/srlw.S + +- test: rv64ui-v-sub + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/sub.S + +- test: rv64ui-v-subw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/subw.S + +- test: rv64ui-v-xor + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/xor.S + +- test: rv64ui-v-xori + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ui/xori.S + +- test: rv64uc-v-rvc + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64uc/rvc.S + +# FPU tests +- test: rv64uf-v-fadd + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64uf/fadd.S + +- test: rv64uf-v-fclass + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64uf/fclass.S + +- test: rv64uf-v-fcmp + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64uf/fcmp.S + +- test: rv64uf-v-fcvt + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64uf/fcvt.S + +- test: rv64uf-v-fcvt_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64uf/fcvt_w.S + +- test: rv64uf-v-fdiv + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64uf/fdiv.S + +- test: rv64uf-v-fmadd + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64uf/fmadd.S + +- test: rv64uf-v-fmin + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64uf/fmin.S + +- test: rv64uf-v-ldst + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64uf/ldst.S + +- test: rv64uf-v-move + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64uf/move.S + +- test: rv64uf-v-recoding + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64uf/recoding.S + +- test: rv64ud-v-fadd + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ud/fadd.S + +- test: rv64ud-v-fclass + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ud/fclass.S + +- test: rv64ud-v-fcmp + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ud/fcmp.S + +- test: rv64ud-v-fcvt + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ud/fcvt.S + +- test: rv64ud-v-fcvt_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ud/fcvt_w.S + +- test: rv64ud-v-fdiv + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ud/fdiv.S + +- test: rv64ud-v-fmadd + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ud/fmadd.S + +- test: rv64ud-v-fmin + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ud/fmin.S + +- test: rv64ud-v-ldst # error with spike + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ud/ldst.S + +- test: rv64ud-v-move + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ud/move.S + +- test: rv64ud-v-recoding + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ud/recoding.S + +- test: rv64ud-v-structural + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ud/structural.S + +# MUL/DIV tests +- test: rv64um-v-div + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64um/div.S + +- test: rv64um-v-divu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64um/divu.S + +- test: rv64um-v-divuw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64um/divuw.S + +- test: rv64um-v-divw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64um/divw.S + +- test: rv64um-v-mul + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64um/mul.S + +- test: rv64um-v-mulh + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64um/mulh.S + +- test: rv64um-v-mulhsu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64um/mulhsu.S + +- test: rv64um-v-mulhu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64um/mulhu.S + +- test: rv64um-v-mulw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64um/mulw.S + +- test: rv64um-v-rem + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64um/rem.S + +- test: rv64um-v-remu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64um/remu.S + +- test: rv64um-v-remuw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64um/remuw.S + +- test: rv64um-v-remw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64um/remw.S + +# AMO tests +- test: rv64ua-v-amoadd_d + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ua/amoadd_d.S + +- test: rv64ua-v-amoand_d + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ua/amoand_d.S + +- test: rv64ua-v-amomax_d + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ua/amomax_d.S + +- test: rv64ua-v-amomaxu_d + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ua/amomaxu_d.S + +- test: rv64ua-v-amomin_d + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ua/amomin_d.S + +- test: rv64ua-v-amominu_d + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ua/amominu_d.S + +- test: rv64ua-v-amoor_d + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ua/amoor_d.S + +- test: rv64ua-v-amoxor_d + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ua/amoxor_d.S + +- test: rv64ua-v-amoswap_d + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ua/amoswap_d.S + +- test: rv64ua-v-amoadd_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ua/amoadd_w.S + +- test: rv64ua-v-amoand_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ua/amoand_w.S + +- test: rv64ua-v-amomax_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ua/amomax_w.S + +- test: rv64ua-v-amomaxu_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ua/amomaxu_w.S + +- test: rv64ua-v-amomin_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ua/amomin_w.S + +- test: rv64ua-v-amominu_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ua/amominu_w.S + +- test: rv64ua-v-amoor_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ua/amoor_w.S + +- test: rv64ua-v-amoxor_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ua/amoxor_w.S + +- test: rv64ua-v-amoswap_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ua/amoswap_w.S + +- test: rv64ua-v-lrsc + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv64ua/lrsc.S diff --git a/verif/tests/testlist_riscv-tests-rv32ima-p.yaml b/verif/tests/testlist_riscv-tests-rv32ima-p.yaml new file mode 100644 index 0000000000..eb24fd8bc3 --- /dev/null +++ b/verif/tests/testlist_riscv-tests-rv32ima-p.yaml @@ -0,0 +1,601 @@ +# Copyright Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# ================================================================================ +# Regression test list format +# -------------------------------------------------------------------------------- +# test : Assembly test name +# description : Description of this test +# gen_opts : Instruction generator options +# iterations : Number of iterations of this test +# no_iss : Enable/disable ISS simulator (Optional) +# gen_test : Test name used by the instruction generator +# asm_tests : Path to directed, hand-coded assembly test file or directory +# rtl_test : RTL simulation test name +# cmp_opts : Compile options passed to the instruction generator +# sim_opts : Simulation options passed to the instruction generator +# no_post_compare : Enable/disable comparison of trace log and ISS log (Optional) +# compare_opts : Options for the RTL & ISS trace comparison +# gcc_opts : gcc compile options +# -------------------------------------------------------------------------------- + +#- import: <riscv_dv_root>/target/rv32ima/testlist.yaml + +# ISA tests +- test: rv32ui-p-add + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/add.S + +- test: rv32ui-p-addi + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/addi.S + +- test: rv32ui-p-and + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/and.S + +- test: rv32ui-p-andi + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/andi.S + +- test: rv32ui-p-auipc + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/auipc.S + +- test: rv32ui-p-beq + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/beq.S + +- test: rv32ui-p-bge + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/bge.S + +- test: rv32ui-p-bgeu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/bgeu.S + +- test: rv32ui-p-blt + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/blt.S + +- test: rv32ui-p-bltu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/bltu.S + +- test: rv32ui-p-bne + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/bne.S + +- test: rv32ui-p-simple + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/simple.S + +- test: rv32ui-p-fence_i + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/fence_i.S + +- test: rv32ui-p-jal + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/jal.S + +- test: rv32ui-p-jalr + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/jalr.S + +- test: rv32ui-p-lb + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/lb.S + +- test: rv32ui-p-lbu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/lbu.S + +- test: rv32ui-p-lh + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/lh.S + +- test: rv32ui-p-lhu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/lhu.S + +- test: rv32ui-p-lw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/lw.S + +- test: rv32ui-p-lui + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/lui.S + +- test: rv32ui-p-or + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/or.S + +- test: rv32ui-p-ori + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/ori.S + +- test: rv32ui-p-sb + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/sb.S + +- test: rv32ui-p-sh + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/sh.S + +- test: rv32ui-p-sw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/sw.S + +- test: rv32ui-p-sll + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/sll.S + +- test: rv32ui-p-slli + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/slli.S + +- test: rv32ui-p-slt + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/slt.S + +- test: rv32ui-p-slti + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/slti.S + +- test: rv32ui-p-sltiu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/sltiu.S + +- test: rv32ui-p-sltu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/sltu.S + +- test: rv32ui-p-sra + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/sra.S + +- test: rv32ui-p-srai + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/srai.S + +- test: rv32ui-p-srl + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/srl.S + +- test: rv32ui-p-srli + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/srli.S + +- test: rv32ui-p-sub + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/sub.S + +- test: rv32ui-p-xor + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/xor.S + +- test: rv32ui-p-xori + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/xori.S + +- test: rv32mi-p-breakpoint + iterations: 0 # csrr a0, tdata1 => 0x20000000 (spike), 0x00000000 (cva6) + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32mi/breakpoint.S + +- test: rv32mi-p-csr + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32mi/csr.S + +- test: rv32mi-p-mcsr + iterations: 0 # expected as different marchid + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32mi/mcsr.S + +- test: rv32mi-p-illegal + iterations: 0 # cva6 does not record illegal instructions in log file + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32mi/illegal.S + +- test: rv32mi-p-ma_addr + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32mi/ma_addr.S + +- test: rv32mi-p-ma_fetch + iterations: 0 # expected as different misa + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32mi/ma_fetch.S + +- test: rv32mi-p-sbreak + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32mi/sbreak.S + +- test: rv32mi-p-scall + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32mi/scall.S + +- test: rv32mi-p-shamt + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32mi/shamt.S + +- test: rv32si-p-csr + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32si/csr.S + +- test: rv32si-p-ma_fetch + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32si/ma_fetch.S + +- test: rv32si-p-scall + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32si/scall.S + +- test: rv32si-p-wfi + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32si/wfi.S + +- test: rv32si-p-sbreak + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32si/sbreak.S + +- test: rv32si-p-dirty + iterations: 0 # to be explained + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32si/dirty.S + +- test: rv32uc-p-rvc + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uc/rvc.S + +# FPU tests +- test: rv32uf-p-fadd + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uf/fadd.S + +- test: rv32uf-p-fclass + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uf/fclass.S + +- test: rv32uf-p-fcmp + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uf/fcmp.S + +- test: rv32uf-p-fcvt + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uf/fcvt.S + +- test: rv32uf-p-fcvt_w + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uf/fcvt_w.S + +- test: rv32uf-p-fdiv + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uf/fdiv.S + +- test: rv32uf-p-fmadd + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uf/fmadd.S + +- test: rv32uf-p-fmin + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uf/fmin.S + +- test: rv32uf-p-ldst + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uf/ldst.S + +- test: rv32uf-p-move + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uf/move.S + +- test: rv32uf-p-recoding + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uf/recoding.S + +- test: rv32ud-p-fadd + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ud/fadd.S + +- test: rv32ud-p-fclass + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ud/fclass.S + +- test: rv32ud-p-fcmp + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ud/fcmp.S + +- test: rv32ud-p-fcvt + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ud/fcvt.S + +- test: rv32ud-p-fcvt_w + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ud/fcvt_w.S + +- test: rv32ud-p-fdiv + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ud/fdiv.S + +- test: rv32ud-p-fmadd + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ud/fmadd.S + +- test: rv32ud-p-fmin + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ud/fmin.S + +- test: rv32ud-p-ldst + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ud/ldst.S + +- test: rv32ud-p-recoding + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ud/recoding.S + +# MUL/DIV tests +- test: rv32um-p-div + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32um/div.S + +- test: rv32um-p-divu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32um/divu.S + +- test: rv32um-p-mul + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32um/mul.S + +- test: rv32um-p-mulh + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32um/mulh.S + +- test: rv32um-p-mulhsu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32um/mulhsu.S + +- test: rv32um-p-mulhu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32um/mulhu.S + +- test: rv32um-p-rem + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32um/rem.S + +- test: rv32um-p-remu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32um/remu.S + +# AMO tests +- test: rv32ua-p-amoadd_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ua/amoadd_w.S + +- test: rv32ua-p-amoand_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ua/amoand_w.S + +- test: rv32ua-p-amomax_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ua/amomax_w.S + +- test: rv32ua-p-amomaxu_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ua/amomaxu_w.S + +- test: rv32ua-p-amomin_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ua/amomin_w.S + +- test: rv32ua-v-amominu_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ua/amominu_w.S + +- test: rv32ua-p-amoor_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ua/amoor_w.S + +- test: rv32ua-p-amoxor_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ua/amoxor_w.S + +- test: rv32ua-p-amoswap_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ua/amoswap_w.S + +- test: rv32ua-p-lrsc + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ua/lrsc.S diff --git a/verif/tests/testlist_riscv-tests-rv32ima-v.yaml b/verif/tests/testlist_riscv-tests-rv32ima-v.yaml new file mode 100644 index 0000000000..9a48ac49c8 --- /dev/null +++ b/verif/tests/testlist_riscv-tests-rv32ima-v.yaml @@ -0,0 +1,511 @@ +# Copyright Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# ================================================================================ +# Regression test list format +# -------------------------------------------------------------------------------- +# test : Assembly test name +# description : Description of this test +# gen_opts : Instruction generator options +# iterations : Number of iterations of this test +# no_iss : Enable/disable ISS simulator (Optional) +# gen_test : Test name used by the instruction generator +# asm_tests : Path to directed, hand-coded assembly test file or directory +# rtl_test : RTL simulation test name +# cmp_opts : Compile options passed to the instruction generator +# sim_opts : Simulation options passed to the instruction generator +# no_post_compare : Enable/disable comparison of trace log and ISS log (Optional) +# compare_opts : Options for the RTL & ISS trace comparison +# gcc_opts : gcc compile options +# -------------------------------------------------------------------------------- + +#- import: <riscv_dv_root>/target/rv32ima/testlist.yaml + +# ISA tests +- test: rv32ui-v-add + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/add.S + +- test: rv32ui-v-addi + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/addi.S + +- test: rv32ui-v-and + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/and.S + +- test: rv32ui-v-andi + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/andi.S + +- test: rv32ui-v-auipc + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/auipc.S + +- test: rv32ui-v-beq + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/beq.S + +- test: rv32ui-v-bge + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/bge.S + +- test: rv32ui-v-bgeu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/bgeu.S + +- test: rv32ui-v-blt + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/blt.S + +- test: rv32ui-v-bltu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/bltu.S + +- test: rv32ui-v-bne + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/bne.S + +- test: rv32ui-v-simple + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/simple.S + +- test: rv32ui-v-fence_i + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/fence_i.S + +- test: rv32ui-v-jal + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/jal.S + +- test: rv32ui-v-jalr + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/jalr.S + +- test: rv32ui-v-lb + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/lb.S + +- test: rv32ui-v-lbu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/lbu.S + +- test: rv32ui-v-lh + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/lh.S + +- test: rv32ui-v-lhu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/lhu.S + +- test: rv32ui-v-lw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/lw.S + +- test: rv32ui-v-lui + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/lui.S + +- test: rv32ui-v-or + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/or.S + +- test: rv32ui-v-ori + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/ori.S + +- test: rv32ui-v-sb + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/sb.S + +- test: rv32ui-v-sh + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/sh.S + +- test: rv32ui-v-sw + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/sw.S + +- test: rv32ui-v-sll + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/sll.S + +- test: rv32ui-v-slli + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/slli.S + +- test: rv32ui-v-slt + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/slt.S + +- test: rv32ui-v-slti + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/slti.S + +- test: rv32ui-v-sltiu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/sltiu.S + +- test: rv32ui-v-sltu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/sltu.S + +- test: rv32ui-v-sra + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/sra.S + +- test: rv32ui-v-srai + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/srai.S + +- test: rv32ui-v-srl + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/srl.S + +- test: rv32ui-v-srli + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/srli.S + +- test: rv32ui-v-sub + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/sub.S + +- test: rv32ui-v-xor + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/xor.S + +- test: rv32ui-v-xori + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ui/xori.S + +- test: rv32uc-p-rvc + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uc/rvc.S + +# FPU tests +- test: rv32uf-v-fadd + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uf/fadd.S + +- test: rv32uf-v-fclass + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uf/fclass.S + +- test: rv32uf-v-fcmp + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uf/fcmp.S + +- test: rv32uf-v-fcvt + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uf/fcvt.S + +- test: rv32uf-v-fcvt_w + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uf/fcvt_w.S + +- test: rv32uf-v-fdiv + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uf/fdiv.S + +- test: rv32uf-v-fmadd + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uf/fmadd.S + +- test: rv32uf-v-fmin + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uf/fmin.S + +- test: rv32uf-v-ldst + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uf/ldst.S + +- test: rv32uf-v-move + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uf/move.S + +- test: rv32uf-v-recoding + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32uf/recoding.S + +- test: rv32ud-v-fadd + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ud/fadd.S + +- test: rv32ud-v-fclass + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ud/fclass.S + +- test: rv32ud-v-fcmp + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ud/fcmp.S + +- test: rv32ud-v-fcvt + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ud/fcvt.S + +- test: rv32ud-v-fcvt_w + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ud/fcvt_w.S + +- test: rv32ud-v-fdiv + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ud/fdiv.S + +- test: rv32ud-v-fmadd + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ud/fmadd.S + +- test: rv32ud-v-fmin + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ud/fmin.S + +- test: rv32ud-v-ldst + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ud/ldst.S + +- test: rv32ud-v-recoding + iterations: 0 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ud/recoding.S + +# MUL/DIV tests +- test: rv32um-v-div + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32um/div.S + +- test: rv32um-v-divu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32um/divu.S + +- test: rv32um-v-mul + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32um/mul.S + +- test: rv32um-v-mulh + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32um/mulh.S + +- test: rv32um-v-mulhsu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32um/mulhsu.S + +- test: rv32um-v-mulhu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32um/mulhu.S + +- test: rv32um-v-rem + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32um/rem.S + +- test: rv32um-v-remu + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32um/remu.S + +# AMO tests +- test: rv32ua-v-amoadd_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ua/amoadd_w.S + +- test: rv32ua-v-amoand_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ua/amoand_w.S + +- test: rv32ua-v-amomax_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ua/amomax_w.S + +- test: rv32ua-v-amomaxu_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ua/amomaxu_w.S + +- test: rv32ua-v-amomin_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ua/amomin_w.S + +- test: rv32ua-v-amominu_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ua/amominu_w.S + +- test: rv32ua-v-amoor_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ua/amoor_w.S + +- test: rv32ua-v-amoxor_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ua/amoxor_w.S + +- test: rv32ua-v-amoswap_w + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ <path_var>/riscv-tests/env/v/entry.S <path_var>/riscv-tests/env/v/vm.c <path_var>/riscv-tests/env/v/string.c -I<path_var>/riscv-tests/env/v/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ua/amoswap_w.S + +- test: rv32ua-v-lrsc + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DENTROPY=0x1 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I<path_var>/riscv-tests/isa/macros/scalar/ -I<path_var>/riscv-tests/env/p/ -I<path_var>/riscv-tests/riscv-target/spike/" + asm_tests: <path_var>/riscv-tests/isa/rv32ua/lrsc.S diff --git a/verif/tests/uvmt/base-tests/uvmt_cva6_base_test.sv b/verif/tests/uvmt/base-tests/uvmt_cva6_base_test.sv new file mode 100644 index 0000000000..c487d501de --- /dev/null +++ b/verif/tests/uvmt/base-tests/uvmt_cva6_base_test.sv @@ -0,0 +1,410 @@ +// Copyright 2020 OpenHW Group +// Copyright 2020 Datum Technologies +// Copyright 2021 Thales DIS Design Services SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 + + +`ifndef __UVMT_CVA6_BASE_TEST_SV__ +`define __UVMT_CVA6_BASE_TEST_SV__ + + +/** + * Abstract component from which all other CVA6 test cases must + * ultimately extend. + * Subclasses must provide stimulus via the virtual sequencer by implementing + * UVM runtime phases. + */ +class uvmt_cva6_base_test_c extends uvm_test; + + // Objects + rand uvmt_cva6_test_cfg_c test_cfg ; + rand uvme_cva6_cfg_c env_cfg ; + uvme_cva6_cntxt_c env_cntxt; + uvml_logs_rs_text_c rs ; + uvml_logs_reg_logger_cbs_c reg_cbs ; + + // Components + uvme_cva6_env_c env ; + uvme_cva6_vsqr_c vsequencer; + + // Handles testbench interfaces + virtual uvmt_rvfi_if rvfi_vif; // virtual peripheral status +// virtual uvmt_cva6_core_cntrl_if core_cntrl_vif; // control inputs to the core + + // Default sequences + rand uvme_cva6_reset_vseq_c reset_vseq; + + // Variable can be modified from command line, to change the AXI agent mode + int force_axi_mode = -1; + + + `uvm_component_utils_begin(uvmt_cva6_base_test_c) + `uvm_field_object(test_cfg , UVM_DEFAULT) + `uvm_field_object(env_cfg , UVM_DEFAULT) + `uvm_field_object(env_cntxt, UVM_DEFAULT) + `uvm_field_int (force_axi_mode , UVM_DEFAULT) + `uvm_component_utils_end + + + constraint env_cfg_cons { + env_cfg.enabled == 1; + env_cfg.is_active == UVM_ACTIVE; + env_cfg.trn_log_enabled == 1; + } + + constraint axi_agent_cfg_cons { + force_axi_mode == -1 -> env_cfg.axi_cfg.is_active == UVM_ACTIVE; + force_axi_mode != -1 -> env_cfg.axi_cfg.is_active == uvm_active_passive_enum'(force_axi_mode); + } + + constraint test_type_default_cons { + soft test_cfg.tpt == NO_TEST_PROGRAM; + } + + + /** + * 1. Replaces default report server with rs. + * 2. Creates reset_vseq. + */ + extern function new(string name="uvmt_cva6_base_test", uvm_component parent=null); + + /** + * 1. Builds test_cfg & env_cfg via create_cfg() + * 2. Randomizes entire test class via randomize_test() + * 3. Passes env_cfg to env via uvm_config_db via assign_cfg() + * 4. Builds env_cntxt via create_cntxt() + * 5. Passes env_cntxt to env using UVM Configuration Database via assign_cntxt() + * 6. Builds env via create_env() + * 7. Builds the rest of the components/objects via create_components() + */ + extern virtual function void build_phase(uvm_phase phase); + + /** + * 1. Assigns environment's virtual sequencer handle to vsequencer. + * 2. Add register callback (reg_cbs) to all registers & fields. + */ + extern virtual function void connect_phase(uvm_phase phase); + + /** + * 1. Triggers the start of clock generation via start_clk() + * 2. Starts the watchdog timeout via watchdog_timeout() + */ + extern virtual task run_phase(uvm_phase phase); + + /** + * Runs reset_vseq. + */ + extern virtual task reset_phase(uvm_phase phase); + + /** + * In a typical UVM env, this task writes contents of RAL to the DUT. + * Here, test_cfg is used to determine if the test program is loaded into + * the TB's instruction memory. + */ + extern virtual task configure_phase(uvm_phase phase); + + /** + * Prints out start of phase banners. + */ + extern virtual function void phase_started(uvm_phase phase); + + /** + * Indicates to the test bench (uvmt_cva6_tb) that the test has completed. + * This is done by checking the properties of the phase argument. + */ + extern virtual function void phase_ended(uvm_phase phase); + + /** + * Retrieves virtual interfaces from UVM configuration database. + */ + extern function void retrieve_vifs(); + + /** + * Creates test_cfg and env_cfg. Assigns ral handle to env_cfg's. + */ + extern virtual function void create_cfg(); + + /** + * 1. Calls test_cfg's process_cli_args() + * 2. Calls randomize on 'this' and fatals out if it fails. + */ + extern virtual function void randomize_test(); + + /** + * Configures uvml_default_hrtbt_monitor. + */ + extern function void cfg_hrtbt_monitor(); + + /** + * Assigns environment configuration (env_cfg) handle to environment (env) + * using UVM Configuration Database. + */ + extern virtual function void assign_cfg(); + + /** + * Creates env_cntxt. + */ + extern virtual function void create_cntxt(); + + /** + * Assigns environment context (env_cntxt) handle to environment (env) using + * UVM Configuration Database. + */ + extern virtual function void assign_cntxt(); + + /** + * Creates env. + */ + extern virtual function void create_env(); + + /** + * Creates additional (non-environment) components (and objects). + */ + extern virtual function void create_components(); + + /** + * Prints overlined and underlined text in uppercase. + */ + extern function void print_banner(string text); + + /** + * Fatals out after watchdog_timeout has elapsed. + */ + extern virtual task watchdog_timer(); + +endclass : uvmt_cva6_base_test_c + + +function uvmt_cva6_base_test_c::new(string name="uvmt_cva6_base_test", uvm_component parent=null); + + super.new(name, parent); + + // Replaces default report server + // Gives you short-and-sweet looger messages like this: + // UVM_INFO @ 9.750 ns : uvmt_cva6_dut_wrap.sv(79) reporter [DUT_WRAP] load_instr_mem asserted! + rs = new("rs"); + + + // Terminate simulation after a "reasonable" number of errors + uvm_report_server::set_server(rs); + reset_vseq = uvme_cva6_reset_vseq_c::type_id::create("reset_vseq"); +endfunction : new + + +function void uvmt_cva6_base_test_c::build_phase(uvm_phase phase); + + super.build_phase(phase); + + rs.set_max_quit_count(.count(5), .overridable(1)); + + retrieve_vifs (); + create_cfg (); + randomize_test (); + cfg_hrtbt_monitor(); + assign_cfg (); + create_cntxt (); + assign_cntxt (); + create_env (); + create_components(); + +endfunction : build_phase + + +function void uvmt_cva6_base_test_c::connect_phase(uvm_phase phase); + + super.connect_phase(phase); + + vsequencer = env.vsequencer; + uvm_reg_cb::add(null, reg_cbs); + +endfunction : connect_phase + + +task uvmt_cva6_base_test_c::run_phase(uvm_phase phase); + + super.run_phase(phase); + + watchdog_timer(); + +endtask : run_phase + + +task uvmt_cva6_base_test_c::reset_phase(uvm_phase phase); + + super.reset_phase(phase); + + phase.raise_objection(this); + + `uvm_info("BASE TEST", $sformatf("Starting reset virtual sequence:\n%s", reset_vseq.sprint()), UVM_NONE) + reset_vseq.start(vsequencer); + `uvm_info("BASE TEST", $sformatf("Finished reset virtual sequence:\n%s", reset_vseq.sprint()), UVM_NONE) + + phase.drop_objection(this); + +endtask : reset_phase + + +task uvmt_cva6_base_test_c::configure_phase(uvm_phase phase); + + uvm_status_e status; + + //super.configure_phase(phase); + + //`uvm_info("BASE TEST", $sformatf("Starting to update DUT with RAL contents:\n%s", ral.sprint()), UVM_NONE) + //ral.update(status); + //`uvm_info("BASE TEST", "Finished updating DUT with RAL contents", UVM_NONE) + + //TODO: is this OK?!? + super.configure_phase(phase); + `uvm_info("BASE TEST", "configure_phase() complete", UVM_HIGH) + +endtask : configure_phase + + +function void uvmt_cva6_base_test_c::phase_started(uvm_phase phase); + + string phase_name = phase.get_name(); + + super.phase_started(phase); + + print_banner($sformatf("start of %s phase", phase_name)); + +endfunction : phase_started + + +function void uvmt_cva6_base_test_c::phase_ended(uvm_phase phase); + + super.phase_ended(phase); + + if (phase.is(uvm_final_phase::get())) begin + // Set sim_finished (otherwise tb will flag that sim was aborted) + uvm_config_db#(bit)::set(null, "", "sim_finished", 1); + + print_banner("test finished"); + end + +endfunction : phase_ended + + +function void uvmt_cva6_base_test_c::retrieve_vifs(); + + if (!uvm_config_db#(virtual uvmt_rvfi_if)::get(this, "", "rvfi_vif", rvfi_vif)) begin + `uvm_fatal("VIF", $sformatf("Could not find rvfi_vif handle of type %s in uvm_config_db", $typename(rvfi_vif))) + end + else begin + `uvm_info("VIF", $sformatf("Found rvfi_vif handle of type %s in uvm_config_db", $typename(rvfi_vif)), UVM_DEBUG) + end + +endfunction : retrieve_vifs + + +function void uvmt_cva6_base_test_c::create_cfg(); + + test_cfg = uvmt_cva6_test_cfg_c::type_id::create("test_cfg"); + env_cfg = uvme_cva6_cfg_c ::type_id::create("env_cfg" ); + //ral = env_cfg.ral; + +endfunction : create_cfg + + +function void uvmt_cva6_base_test_c::randomize_test(); + + test_cfg.process_cli_args(); + if (!this.randomize()) begin + `uvm_fatal("BASE TEST", "Failed to randomize test"); + end + `uvm_info("BASE TEST", $sformatf("Top-level environment configuration:\n%s", env_cfg.sprint()), UVM_NONE) + `uvm_info("BASE TEST", $sformatf("Testcase configuration:\n%s", test_cfg.sprint()), UVM_NONE) + +endfunction : randomize_test + + +function void uvmt_cva6_base_test_c::cfg_hrtbt_monitor(); + + uvml_default_hrtbt.enabled = 0; + //`uvml_hrtbt_set_cfg(startup_timeout , test_cfg.startup_timeout) + uvml_default_hrtbt.startup_timeout = test_cfg.startup_timeout; // TODO DOP: Fix heartbeat macros + //`uvml_hrtbt_set_cfg(heartbeat_period, test_cfg.heartbeat_period) + uvml_default_hrtbt.startup_timeout = test_cfg.heartbeat_period; // TODO DOP: Fix heartbeat macros + +endfunction : cfg_hrtbt_monitor + + +function void uvmt_cva6_base_test_c::assign_cfg(); + + uvm_config_db#(uvme_cva6_cfg_c)::set(this, "env", "cfg", env_cfg); + +endfunction : assign_cfg + + +function void uvmt_cva6_base_test_c::create_cntxt(); + + env_cntxt = uvme_cva6_cntxt_c::type_id::create("env_cntxt"); + +endfunction : create_cntxt + + +function void uvmt_cva6_base_test_c::assign_cntxt(); + + uvm_config_db#(uvme_cva6_cntxt_c)::set(this, "env", "cntxt", env_cntxt); + +endfunction : assign_cntxt + + +function void uvmt_cva6_base_test_c::create_env(); + + env = uvme_cva6_env_c::type_id::create("env", this); + +endfunction : create_env + + +function void uvmt_cva6_base_test_c::create_components(); + + reg_cbs = uvml_logs_reg_logger_cbs_c::type_id::create("reg_cbs"); + +endfunction : create_components + + +function void uvmt_cva6_base_test_c::print_banner(string text); + + if (test_cfg != null) begin + if (test_cfg.print_uvm_runflow_banner) begin + $display(""); + $display("*******************************************************************************"); + $display(text.toupper()); + $display("*******************************************************************************"); + end + else begin + `uvm_info("BASE_TEST", "Printing of UVM run-flow banner disabled", UVM_HIGH) + end + end + +endfunction : print_banner + + +task uvmt_cva6_base_test_c::watchdog_timer(); + + fork + begin + #(test_cfg.watchdog_timeout * 1ns); + `uvm_fatal("TIMEOUT", $sformatf("Global timeout after %0dns. Heartbeat list:\n%s", test_cfg.watchdog_timeout, uvml_default_hrtbt.print_comp_names())) + end + join_none + +endtask : watchdog_timer + + +`endif // __UVMT_CVA6_BASE_TEST_SV__ diff --git a/verif/tests/uvmt/base-tests/uvmt_cva6_test_cfg.sv b/verif/tests/uvmt/base-tests/uvmt_cva6_test_cfg.sv new file mode 100644 index 0000000000..fb719ea16a --- /dev/null +++ b/verif/tests/uvmt/base-tests/uvmt_cva6_test_cfg.sv @@ -0,0 +1,151 @@ +// Copyright 2020 OpenHW Group +// Copyright 2020 Datum Technology Corporation +// Copyright 2021 Thales DIS Design Services SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 + + +`ifndef __UVMT_CVA6_TEST_CFG_SV__ +`define __UVMT_CVA6_TEST_CFG_SV__ + + +/** + * Configuration object for testcases + */ +class uvmt_cva6_test_cfg_c extends uvm_object; + + //typedef enum { + // PREEXISTING_SELFCHECKING, + // PREEXISTING_NOTSELFCHECKING, + // GENERATED_SELFCHECKING, + // GENERATED_NOTSELFCHECKING, + // NONE + // } test_program_type; + + + // Knobs for environment control + rand int unsigned startup_timeout ; // Specified in nanoseconds (ns) + rand int unsigned heartbeat_period; // Specified in nanoseconds (ns) + rand int unsigned watchdog_timeout; // Specified in nanoseconds (ns) + + // Knobs for test-program control + rand test_program_type tpt; + + // Command line arguments for controlling RAL + // (note: its not clear if this ENV will use the RAL) + string cli_block_name_str = "BLKNM"; + bit cli_block_name_override = 0; + //uvm_reg_block cli_selected_block; + + // Command line arguments for FIRMWARE (Test Program) selection + // +firmware=<path_to_hexfile_test_program> + string cli_firmware_select_str = "firmware"; + bit cli_firmware_select_override = 0; + string cli_firmware_name_str = ""; + + // Command line arguments to control whether the UVM run-flow banner is + // written to stdout. (A bit overkill for on/off control.) + // +print_uvm_runflow_banner=1 + string cli_uvm_banner_select_str = "print_uvm_runflow_banner"; + bit cli_uvm_banner_select_override = 0; + string cli_uvm_banner_name_str = ""; + + // Run-time control + bit run_riscv_gcc_toolchain = 0; + bit print_uvm_runflow_banner = 0; + + `uvm_object_utils_begin(uvmt_cva6_test_cfg_c) + `uvm_field_int(heartbeat_period, UVM_DEFAULT) + `uvm_field_int(watchdog_timeout, UVM_DEFAULT) + + `uvm_field_enum(test_program_type, tpt, UVM_DEFAULT) + + //`uvm_field_object(cli_selected_block, UVM_DEFAULT) + `uvm_field_int(run_riscv_gcc_toolchain, UVM_DEFAULT) + `uvm_field_int(print_uvm_runflow_banner, UVM_DEFAULT) + `uvm_object_utils_end + + + constraint timeouts_default_cons { + soft startup_timeout == 100_000_000; // Set to be huge for now so that sim can finish + soft heartbeat_period == 200_000; // 2 us // TODO Set default Heartbeat Monitor period for uvmt_cva6_base_test_c + soft watchdog_timeout == 100_000_000; // 10 ms // TODO Set default Watchdog timeout period for uvmt_cva6_base_test_c + } + + //constraint test_type_default_cons { + // soft tpt == NONE; + //} + + /** + * Default constructor. + */ + extern function new(string name="uvmt_cva6_test_cfg"); + + /** + * TODO Describe uvmt_cva6_test_cfg_c::process_cli_args() + */ + extern function void process_cli_args(); + +endclass : uvmt_cva6_test_cfg_c + + +function uvmt_cva6_test_cfg_c::new(string name="uvmt_cva6_test_cfg"); + + super.new(name); + +endfunction : new + + +function void uvmt_cva6_test_cfg_c::process_cli_args(); + + string cli_block_name_parsed_str = ""; + + // RAL control + cli_block_name_override = 0; //default + if (uvm_cmdline_proc.get_arg_value({"+", cli_block_name_str, "="}, cli_block_name_parsed_str)) begin + if (cli_block_name_parsed_str != "") begin + cli_block_name_override = 1; + //cli_selected_block = ral.get_block_by_name(cli_block_name_parsed_str); + `uvm_info("TEST_CFG", $sformatf("process_cli_args() RAL block_name=%s", cli_block_name_str), UVM_LOW) + end + end + + // Test program (firmware) selection + cli_firmware_select_override = 0; // default + if (uvm_cmdline_proc.get_arg_value({"+", cli_firmware_select_str, "="}, cli_firmware_name_str)) begin + if (cli_firmware_name_str != "") begin + cli_firmware_select_override = 1; + run_riscv_gcc_toolchain = 1; + `uvm_info("TEST_CFG", $sformatf("process_cli_args() firmware=%s", cli_firmware_name_str), UVM_LOW) + end + end + + // Turn on printing of UVM run-flow banner (any arg will work) + // void'($value$plusargs("print_uvm_runflow_banner=%0d", print_uvm_runflow_banner)); + cli_uvm_banner_select_override = 0; // default + if (uvm_cmdline_proc.get_arg_value({"+", cli_uvm_banner_select_str, "="}, cli_uvm_banner_name_str)) begin + if (cli_firmware_name_str != "") begin + cli_uvm_banner_select_override = 1; + print_uvm_runflow_banner = 1; + `uvm_info("TEST_CFG", $sformatf("process_cli_args() cli_uvm_banner_select_str=%s", cli_uvm_banner_name_str), UVM_LOW) + end + end + + `uvm_info("TEST_CFG", "process_cli_args() complete", UVM_HIGH) + +endfunction : process_cli_args + + +`endif // __UVMT_CVA6_TEST_CFG_SV__ diff --git a/verif/tests/uvmt/compliance-tests/uvmt_cva6_firmware_test.sv b/verif/tests/uvmt/compliance-tests/uvmt_cva6_firmware_test.sv new file mode 100644 index 0000000000..e6d73a71a1 --- /dev/null +++ b/verif/tests/uvmt/compliance-tests/uvmt_cva6_firmware_test.sv @@ -0,0 +1,204 @@ +// Copyright 2020 OpenHW Group +// Copyright 2020 Datum Technology Corporation +// Copyright 2020 Silicon Labs, Inc. +// Copyright 2021 Thales DIS Design Services SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 + + +`ifndef __UVMT_CVA6_FIRMWARE_TEST_SV__ +`define __UVMT_CVA6_FIRMWARE_TEST_SV__ + + +/** + * CVA6 "firmware" test. + * This class relies on a pre-existing "firmware" file written in C and/or + * RISC-V assembly code. This class will invoke the riscv-gcc-toolchain to + * translate the firmware into a "hexfile" that is read into the CVA6 + * instruction memory in the testbench module. + * + * This class doesn't care what the firmware does, it mearly compiles it. + * + */ +class uvmt_cva6_firmware_test_c extends uvmt_cva6_base_test_c; + + //constraint env_cfg_cons { + // env_cfg.enabled == 1; + // env_cfg.is_active == UVM_ACTIVE; + // env_cfg.trn_log_enabled == 1; + //} + + constraint test_type_cons { + test_cfg.tpt == PREEXISTING_SELFCHECKING; + } + + + `uvm_component_utils(uvmt_cva6_firmware_test_c) + + /** + */ + extern function new(string name="uvmt_cva6_firmware_test", uvm_component parent=null); + + /** + * Runs reset_vseq. + */ + extern virtual task reset_phase(uvm_phase phase); + + /** + * Loads the test program (the "firmware") into memory. + */ + extern virtual task configure_phase(uvm_phase phase); + + /** + * Enable program execution, wait for completion. + */ + extern virtual task run_phase(uvm_phase phase); + + /** + * Start the interrupt sequencer to apply random interrupts during test + */ + extern virtual task irq_noise(); + + /** + * Randomly assert/deassert fetch_enable_i + */ + extern virtual task random_fetch_toggle(); + +endclass : uvmt_cva6_firmware_test_c + + +function uvmt_cva6_firmware_test_c::new(string name="uvmt_cva6_firmware_test", uvm_component parent=null); + + super.new(name, parent); + `uvm_info("TEST", "This is the FIRMWARE TEST", UVM_NONE) + +endfunction : new + + +task uvmt_cva6_firmware_test_c::reset_phase(uvm_phase phase); + super.reset_phase(phase); + +endtask : reset_phase + + +task uvmt_cva6_firmware_test_c::configure_phase(uvm_phase phase); + + //string firmware; + //int fd; + + super.configure_phase(phase); + + /* + ** Moved to uvmt_cva6_dut_wrap.sv to avoid XMRs across packages. + ** TODO: delete all this once you are confident of the approach. + ** + // Load the pre-compiled firmware + if($value$plusargs("firmware=%s", firmware)) begin + // First, check if it exists... + fd = $fopen (firmware, "r"); + if (fd) `uvm_info("TEST", $sformatf("%s was opened successfully : (fd=%0d)", firmware, fd), UVM_NONE) + else `uvm_fatal("TEST", $sformatf("%s was NOT opened successfully : (fd=%0d)", firmware, fd)) + $fclose(fd); + // Now load it... + `uvm_info("TEST", $sformatf("loading firmware %0s", firmware), UVM_NONE) + $readmemh(firmware, uvmt_cva6_tb.dut_wrap.ram_i.dp_ram_i.mem); + end + else begin + `uvm_error("TEST", "No firmware specified!") + end + */ + +endtask : configure_phase + + +task uvmt_cva6_firmware_test_c::run_phase(uvm_phase phase); + + // start_clk() and watchdog_timer() are called in the base_test + super.run_phase(phase); + + if ($test$plusargs("gen_irq_noise")) begin + fork + irq_noise(); + join_none + end + + if ($test$plusargs("random_fetch_toggle")) begin + fork + random_fetch_toggle(); + join_none + end + + phase.raise_objection(this); + @(posedge env_cntxt.clknrst_cntxt.vif.reset_n); + repeat (33) @(posedge env_cntxt.clknrst_cntxt.vif.clk); + `uvm_info("TEST", "Started RUN", UVM_NONE) + // The firmware is expected to write exit status and pass/fail indication to the Virtual Peripheral. + // The format of rvfi_vif.tb_exit_o is { wire[31:1] exit_code, wire test_finished }. + wait ( + (rvfi_vif.tb_exit_o[0] == 1'b1) + ); + `uvm_info("TEST", "Test FINISHED", UVM_NONE) + // Set sim_finished (otherwise tb will flag that sim was aborted) + uvm_config_db#(bit)::set(null, "", "sim_finished", 1); + uvm_config_db#(int)::set(null, "", "test_exit_code", { 0'b0, rvfi_vif.tb_exit_o[31:1] }); + // Let the termination-triggering instruction appear in the log. + @(posedge env_cntxt.clknrst_cntxt.vif.clk); + // Allow termination from now on. + phase.drop_objection(this); + repeat (100) @(posedge env_cntxt.clknrst_cntxt.vif.clk); + +endtask : run_phase + +task uvmt_cva6_firmware_test_c::irq_noise(); + `uvm_info("TEST", "Starting IRQ Noise thread in UVM test", UVM_NONE); +// while (1) begin +// uvme_cva6_interrupt_noise_c interrupt_noise_vseq; + +// interrupt_noise_vseq = uvme_cva6_interrupt_noise_c::type_id::create("interrupt_noise_vseqr"); +// assert(interrupt_noise_vseq.randomize() with { +// reserved_irq_mask == 32'h0; +// }); +// interrupt_noise_vseq.start(vsequencer); +// break; +// end +endtask : irq_noise + +task uvmt_cva6_firmware_test_c::random_fetch_toggle(); + `uvm_info("TEST", "Starting random_fetch_toggle thread in UVM test", UVM_NONE); + while (1) begin + int unsigned fetch_assert_cycles; + int unsigned fetch_deassert_cycles; + + // Randomly assert for a random number of cycles + randcase + 9: fetch_assert_cycles = $urandom_range(100_000, 100); + 1: fetch_assert_cycles = $urandom_range(100, 1); + 1: fetch_assert_cycles = $urandom_range(3, 1); + endcase +// repeat (fetch_assert_cycles) @(core_cntrl_vif.drv_cb); +// core_cntrl_vif.stop_fetch(); + + // Randomly dessert for a random number of cycles + randcase + 3: fetch_deassert_cycles = $urandom_range(100, 1); + 1: fetch_deassert_cycles = $urandom_range(3, 1); + endcase +// repeat (fetch_deassert_cycles) @(core_cntrl_vif.drv_cb); +// core_cntrl_vif.go_fetch(); + end + +endtask : random_fetch_toggle + +`endif // __UVMT_CVA6_FIRMWARE_TEST_SV__ diff --git a/verif/tests/uvmt/vseq/uvmt_cva6_vseq_lib.sv b/verif/tests/uvmt/vseq/uvmt_cva6_vseq_lib.sv new file mode 100644 index 0000000000..be4e822df2 --- /dev/null +++ b/verif/tests/uvmt/vseq/uvmt_cva6_vseq_lib.sv @@ -0,0 +1,53 @@ +// Copyright 2021 Thales DIS Design Services SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 + + +`ifndef __UVMT_CVA6_VSEQ_LIB_SV__ +`define __UVMT_CVA6_VSEQ_LIB_SV__ + + +/** + * Object holding virtual sequence library for CVA6 test cases. + */ +class uvmt_cva6_vseq_lib_c extends uvm_sequence_library#( + .REQ(uvm_sequence_item), + .RSP(uvm_sequence_item) +); + + `uvm_object_utils (uvmt_cva6_vseq_lib_c) + `uvm_sequence_library_utils(uvmt_cva6_vseq_lib_c) + + + /** + * Initializes sequence library. + */ + extern function new(string name="uvmt_cva6_vseq_lib"); + +endclass : uvmt_cva6_vseq_lib_c + + +function uvmt_cva6_vseq_lib_c::new(string name="uvmt_cva6_vseq_lib"); + + super.new(name); + init_sequence_library(); + + // TODO Add sequences to uvmt_cva6_vseq_lib_c + // Ex: add_sequence(uvmt_cva6_abc_vseq_c::get_type()); + +endfunction : new + + +`endif // __UVMT_CVA6_VSEQ_LIB_SV__